WO2016145769A1 - 薄膜晶体管及其制作方法、阵列基板及显示装置 - Google Patents

薄膜晶体管及其制作方法、阵列基板及显示装置 Download PDF

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WO2016145769A1
WO2016145769A1 PCT/CN2015/086443 CN2015086443W WO2016145769A1 WO 2016145769 A1 WO2016145769 A1 WO 2016145769A1 CN 2015086443 W CN2015086443 W CN 2015086443W WO 2016145769 A1 WO2016145769 A1 WO 2016145769A1
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electrode
insulating layer
forming
layer
active layer
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French (fr)
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张立
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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Priority to US14/914,228 priority Critical patent/US9882063B2/en
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Priority to JP2016567745A priority patent/JP6521534B2/ja
Priority to KR1020167031863A priority patent/KR101863217B1/ko
Publication of WO2016145769A1 publication Critical patent/WO2016145769A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/035—Manufacture or treatment of data-storage electrodes comprising conductor-insulator-conductor-insulator-semiconductor structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
    • H10P76/2041—Photolithographic processes

Definitions

  • the present disclosure relates to the field of semiconductor device fabrication technologies, and in particular, to a thin film transistor and a method for fabricating the same, an array substrate, and a display device.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • the source electrode 3, the drain electrode 4, and the gate electrode 1 are disposed on the same side of the active layer 2. According to the position of the gate electrode 1 with respect to the active layer 2, the coplanar TFT is divided into a top gate type coplanar TFT (in combination with FIG. 1) and a bottom gate type coplanar TFT (in combination with FIG. 2).
  • the pixel electrode 5 is in electrical contact with the drain electrode 4 through the via hole penetrating the passivation layer 102 and the gate insulating layer 101. . Since the depth of the via hole is too large, it is difficult to climb the slope, and the pixel electrode 5 is easily broken, and electrical contact failure occurs. On the other hand, if the electrical connection between the pixel electrode 5 and the drain electrode 4 is realized in the form of jumper, the number of Masks is increased, and the production cost is increased. For the bottom gate type coplanar TFT, as shown in FIG.
  • the active layer 2 is overlapped on the source electrode 3 and the drain electrode 4, and the etching process for forming the source electrode 3 and the drain electrode 4 causes the side of the source and drain metal to be rough. Since the thickness of the active layer 2 is thin and the sides of the source electrode 3 and the drain electrode 4 are rough, when the active layer 2 is overlapped on the source electrode 3 and the drain electrode 4, the climbing problem easily occurs, resulting in an active layer. 2 easy to disconnect. Further, in the above case, the thickness of the active layer 2 is not uniform, and it is easy to break through the short circuit during power-on.
  • the present disclosure provides a thin film transistor and a fabrication method thereof for solving the above technical problems existing in a coplanar thin film transistor and its application.
  • the present disclosure also improves the device yield by using the above-described thin film transistor through an array substrate and a display device.
  • a thin film transistor including:
  • An active layer the entire active layer being located in the same plane;
  • a source electrode disposed on the active layer in contact with the active layer
  • the first insulating layer including a first via
  • drain electrode on the first insulating layer, the drain electrode being in contact with the active layer through the first via.
  • a method for fabricating a thin film transistor is further provided in the embodiment of the present disclosure, including:
  • Forming an active layer the entire active layer being located in the same plane;
  • a drain electrode is formed on the first insulating layer, and the drain electrode is in contact with the active layer through the first via.
  • an array substrate is further provided in the embodiment of the present disclosure, including:
  • a pixel electrode on the second insulating layer wherein the second insulating layer has a third via hole, and the pixel electrode is in electrical contact with a drain electrode of the thin film transistor through the third via hole.
  • a display device including the array substrate as described above is also provided in the embodiment of the present disclosure.
  • the embodiment of the present disclosure further provides a method for fabricating an array substrate, including:
  • Forming an active layer the entire active layer being located in the same plane;
  • a pixel electrode of the array substrate is formed while forming the first portion of the gate electrode, and the pixel electrode is in electrical contact with the drain electrode through the third via.
  • the source electrode and the drain electrode of the thin film transistor are disposed on the active layer to ensure that the active layer is located in the same plane, which overcomes the problem of easy disconnection caused by difficulty in climbing of the active layer in the prior art. Moreover, the thickness of the active layer is uniform, the breakdown short circuit does not occur, and the yield of the thin film transistor is improved.
  • the source electrode and the drain electrode are arranged in a non-same layer structure, and the distance between the source electrode and the drain electrode can be flexibly adjusted, and the narrow channel can be more easily realized, and the performance of the thin film transistor can be improved.
  • FIG. 1 is a schematic view showing the structure of a top gate type coplanar thin film transistor array substrate in the prior art
  • FIG. 2 is a schematic structural view of a bottom gate type coplanar thin film transistor array substrate in the prior art
  • FIG. 3 is a schematic structural view of a coplanar thin film transistor array substrate in an embodiment of the present disclosure
  • 4 to 9 are schematic views showing a process of fabricating a coplanar thin film transistor array substrate in an embodiment of the present disclosure.
  • the present disclosure provides a thin film transistor in which a source electrode and a drain electrode are located on an active layer, and the entire active layer is located in the same plane, so that the active layer does not have a problem of easy disconnection caused by difficulty in climbing. Moreover, the thickness of the active layer is uniform, and the breakdown short circuit is less likely to occur during the working process, and the yield of the thin film transistor is improved.
  • the source electrode and the drain electrode are arranged in a non-same layer structure, and the distance between the source electrode and the drain electrode can be flexibly adjusted, and the narrow channel can be more easily realized, and the performance of the thin film transistor can be improved.
  • the electrode on the array substrate that is in electrical contact with the drain electrode of the thin film transistor is a transparent pixel electrode, and the material may be indium tin oxide (ITO) or indium zinc oxide (IZO).
  • the bottom electrode on the array substrate that is in electrical contact with the drain electrode of the driving thin film transistor is a cathode or an anode of the OLED, which may be a transparent conductive material or an opaque conductive material (eg, Cu). , Al), and, in general, the bottom electrode is also referred to as a pixel electrode (this disclosure is referred to as a pixel electrode).
  • a thin film transistor is provided in the embodiment of the present disclosure, in which the entire active layer 2 is located in the same plane.
  • the source electrode 3 and the drain electrode 4 of the thin film transistor are disposed on the active layer 2 and are disposed in contact with the active layer 2.
  • a first insulating layer 130 is disposed between the source electrode 3 and the drain electrode 4.
  • the drain electrode 4 is disposed on the first insulating layer 130 and is in contact with the active layer 2 through the first via 6 in the first insulating layer 130.
  • the active layer 2 is located in the same plane, and there is no problem of easy disconnection caused by difficulty in climbing, and the thickness thereof is uniform, and it is not easy to break through the short circuit during the working process, and the bottom gate type of the prior art is overcome.
  • Technical problems with coplanar thin film transistors At the same time, the source electrode 3 and the drain electrode 4 have a non-same layer structure, which makes it easier to realize a narrow channel and improve the performance of the thin film transistor.
  • a method for fabricating a thin film transistor in an embodiment of the present disclosure includes:
  • a drain electrode 4 is formed on the first insulating layer 130, and the drain electrode 4 passes through the first via hole 6 and the active layer 2 contact.
  • the source electrode 3 and the drain electrode 4 have a non-same layer structure, and the two are formed by different film layers.
  • the source electrode 3 may be located in a region where the active layer 2 of the thin film transistor is located, and the entire source electrode 3 is disposed in contact with the active layer 2, as shown in FIG.
  • the source electrode 3 and the active layer 2 can be simultaneously formed in one patterning process to simplify the fabrication process.
  • the patterning process for forming the source electrode 3 and the active layer 2 specifically includes:
  • a photoresist is coated on the source metal layer 120, and the photoresist is exposed and developed to form a photoresist completely reserved region 200, a photoresist semi-retained region 201, and a photoresist non-retained region 202, and the photoresist is completely completed.
  • the reserved region 200 corresponds to a region where the source electrode of the thin film transistor is located
  • the photoresist semi-reserved region 201 corresponds to a region where the active layer of the thin film transistor does not correspond to the position of the source electrode
  • the photoresist non-reserved region 202 corresponds to other regions, as shown in FIG. 5. Shown
  • the remaining photoresist is stripped to form the active layer 2 and the source electrode 3 of the thin film transistor as shown in FIG.
  • the above steps simultaneously form the active layer 2 and the source electrode 3 of the thin film transistor by one patterning process.
  • the active layer 2 and the source electrode 3 of the thin film transistor are simultaneously formed by one patterning process, and the width of the source electrode 3 can be effectively reduced.
  • the source electrode 3 and the drain electrode 4 have a non-same layer structure, and the two are formed by different film layers.
  • the projection width of the thin film transistor is constant, the width of the drain electrode 4 can be appropriately increased (as seen in FIGS. 1 and 3).
  • only one layer of the second insulating layer 140 may be disposed between the drain electrode 4 and the pixel electrode 5.
  • the gate electrode of the top gate type coplanar thin film transistor includes a first portion 10 on the second insulating layer 140, and the first portion 10 has a region corresponding to the source electrode 3 and the drain electrode 4. part.
  • the first portion 10 of the gate electrode and the pixel electrode 5 of the array substrate have the same layer structure and are formed by the same film layer.
  • the first portion 10 of the gate electrode and the pixel electrode 5 may be formed by forming a conductive layer on the second insulating layer 140 and patterning the conductive layer, and the first portion 10 of the gate electrode has a corresponding source electrode 3 and A portion of the region between the drain electrodes 4.
  • the manufacturing method of the thin film transistor further includes:
  • a gate electrode is formed, the gate electrode including a first portion 10 on the second insulating layer 140, the first portion 10 having a portion corresponding to a region between the source electrode 3 and the drain electrode 4, as shown in FIG.
  • the first portion 10 of the gate electrode and the pixel electrode 5 of the array substrate have the same layer structure and are formed by the same conductive layer.
  • the pixel electrode 5 is in electrical contact with the drain electrode 4 through the third via 8 in the second insulating layer 140, as shown in FIGS. 3 and 9. Since there is only one layer of the second insulating layer 140 between the pixel electrode 5 and the drain electrode 4, the depth of the third via hole 8 is small, and the pixel electrode 5 does not have the problem of easy disconnection caused by difficulty in climbing, thereby improving the goodness of the device. rate.
  • the gate electrode may further include a second portion 11 electrically connected to the first portion 10 of the gate electrode, the material of which is a gate metal.
  • the thin film transistor can be turned on or off to the gate electrode through the gate line (formed by the gate metal layer and in the same layer structure as the second portion 11 of the gate electrode) without changing the wiring structure of the transmission signal. The signal does not increase the manufacturing process and is easy to implement.
  • the second portion 11 of the gate electrode may have the same layer structure as the drain electrode 4 and be formed by the same gate metal layer. Also, the second insulating layer 140 covers the second portion 11 and the drain electrode 4 of the gate electrode.
  • the array substrate is a top gate type coplanar thin film transistor array substrate
  • the gate electrode of the thin film transistor includes the first portion 10 and the second portion 11.
  • the first portion 10 has a portion corresponding to a region between the source electrode 3 and the drain electrode 4, and has the same layer structure as the pixel electrode 5 of the array substrate.
  • the material of the second portion 11 is a gate metal, which is in the same layer structure as the drain electrode 4, and the source electrode 3 is formed of a source metal layer.
  • a second insulating layer 140 is disposed between the first portion 10 and the second portion 11 of the gate electrode, and is electrically contacted through the second via 7 in the second insulating layer 140. Accordingly, the fabrication of the array substrate Methods include:
  • the active layer 2 and the source electrode 3 of the thin film transistor are formed by one patterning process to simplify the fabrication process.
  • the active layer 2 and the source electrode 3 can also be formed separately by two patterning processes.
  • the gate electrode when the gate electrode includes the second portion 11 having the same material as the gate metal and having the same layer structure as the drain electrode 4, optionally, the second portion 11 is disposed at the source electrode 3 away from the drain electrode 4 On one side, as shown in FIG. 3, the coupling capacitance formed between the second portion 11 and the source electrode 3 and the drain electrode 4 is reduced to improve the display quality of the device.
  • the thin film transistor in the embodiment of the present disclosure specifically includes:
  • the active layer 2, the entire active layer 2 is located in the same plane;
  • first insulating layer 130 disposed on the source electrode 3, the first insulating layer 130 having a first via hole therein;
  • the material is a gate metal
  • the second portion 11 is located on a side of the source electrode 3 away from the drain electrode 4;
  • the first portion 10 of the gate electrode disposed on the second insulating layer 140 is in electrical contact with the second portion 11 through the second via hole 7.
  • a second insulating layer 140 covering the drain electrode 4 of the thin film transistor
  • the pixel electrode 5 is disposed on the second insulating layer 140 in the same layer structure as the first portion 10 of the gate electrode, and is in electrical contact with the drain electrode 4 through the third via hole in the second insulating layer 140.
  • the manufacturing method of the thin film transistor in the embodiment of the present disclosure specifically includes:
  • step S1 a base substrate 100 such as a transparent substrate such as a glass substrate, a quartz substrate, or an organic resin substrate is provided, and the active layer 2 and the source electrode 3 are formed on the base substrate 100.
  • a transparent substrate such as a glass substrate, a quartz substrate, or an organic resin substrate
  • the material of the active layer 2 may be a silicon semiconductor or a metal oxide semiconductor.
  • the material of the source electrode 3 is a metal such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W, and an alloy of these metals, and the source electrode 3 may have a single layer structure or a multilayer structure, and a plurality of layers.
  • the structure is such as Cu ⁇ Mo, Ti ⁇ Cu ⁇ Ti, Mo ⁇ Al ⁇ Mo, and the like.
  • the step of forming the active layer 2 and the source electrode 3 on the base substrate 100 may include:
  • a photoresist is coated on the source metal layer 120, and the photoresist is exposed and developed to form a photoresist completely reserved region 200, a photoresist semi-retained region 201, and a photoresist non-retained region 202, and the photoresist is completely completed.
  • the reserved region 200 corresponds to a region where the source electrode of the thin film transistor is located
  • the photoresist semi-reserved region 201 corresponds to a region where the active layer of the thin film transistor does not correspond to the position of the source electrode
  • the photoresist non-reserved region 202 corresponds to other regions, as shown in FIG. 5. Shown
  • the remaining photoresist is stripped to form the active layer 2 and the source electrode 3 of the thin film transistor as shown in FIG.
  • Step S2 forming a first insulating layer 130 on the base substrate 100 completing step S1, for the first
  • the insulating layer 130 is patterned to form the first via hole 6, exposing the active layer 2 as shown in FIG.
  • the first insulating layer 130 may be SiNx, SiOx or Si(ON)x.
  • Step S3 forming a gate metal layer (not shown) on the base substrate 100 completing step S2, and patterning the gate metal layer to form a second portion 11, a drain electrode 4, and a gate line of the gate electrode.
  • the second portion 11 of the gate electrode is electrically connected to the gate line
  • the drain electrode 4 is electrically connected to the active layer 2 through the first via hole 6, as shown in FIG. 8 and FIG.
  • the gate metal layer may be a metal such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W, and an alloy of these metals, and the gate metal layer may be a single layer structure or a multilayer structure,
  • the layer structure is, for example, Cu ⁇ Mo, Ti ⁇ Cu ⁇ Ti, Mo ⁇ Al ⁇ Mo, and the like.
  • Step S4 forming a second insulating layer 140 on the base substrate 100 completing the step S3, and patterning the second insulating layer 140 to form the second via hole 7 and the third via hole 8, as shown in FIG.
  • the second insulating layer 140 may be SiNx, SiOx or Si(ON)x.
  • Step S5 forming a conductive layer on the base substrate 100 completing step S4, performing a patterning process on the conductive layer to form a first portion 10 of the gate electrode, and the first portion 10 of the gate electrode has a corresponding source electrode 3 and drain electrode 4.
  • the portion of the inter-region is electrically contacted with the second portion 11 through the second via 7, as shown in Figures 3 and 9.
  • the step of forming the first portion 10 and the pixel electrode 5 of the gate electrode is specifically as follows:
  • a conductive layer is formed on the base substrate 100 in which the step S4 is completed, and the conductive layer is patterned to form the first portion 10 of the gate electrode and the pixel electrode 5.
  • a display device including the array substrate as described above, is further provided in the embodiment of the present disclosure to improve the yield and display quality of the display device.
  • the display device may be a liquid crystal display device or an organic light emitting diode display device.
  • the display device may be: a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigation device, etc. Functional product or part.
  • the source electrode and the drain electrode of the thin film transistor are disposed on the active layer to ensure that the active layer is located in the same plane, which overcomes the problem of easy disconnection caused by difficulty in climbing the active layer in the prior art. Moreover, the thickness of the active layer is uniform, the breakdown short circuit does not occur, and the yield of the thin film transistor is improved.
  • the source electrode and the drain electrode are arranged in a non-same layer structure, and the distance between the source electrode and the drain electrode can be flexibly adjusted, and the narrow channel can be more easily realized, and the performance of the thin film transistor can be improved.

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  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

公开了一种薄膜晶体管及其制作方法、阵列基板及显示装置。所述薄膜晶体管包括：有源层（2），整个所述有源层（2）位于同一平面内；位于有源层（2）上、与所述有源层（2）接触设置的源电极（3）；位于源电极（3）上的第一绝缘层（130），所述第一绝缘层（130）包括第一过孔（6）；位于所述第一绝缘层（130）上的漏电极（4），所述漏电极（4）通过第一过孔（6）与有源层（2）接触。

Description

薄膜晶体管及其制作方法、阵列基板及显示装置
相关申请的交叉引用
本申请主张在2015年3月18日在中国提交的中国专利申请号No.201510121068.X的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及半导体器件制备技术领域，特别是涉及一种薄膜晶体管及其制作方法、阵列基板及显示装置。
背景技术
薄膜晶体管液晶显示器(Thin Film Transistor Liquid Crystal Display，简称TFT-LCD)具有体积小、功耗低、无辐射、制造成本相对较低等特点，在当前的平板显示器市场占据了主导地位。
结合图1和图2所示，在共面薄膜晶体管(Thin Film Transistor，简称TFT)中，源电极3、漏电极4和栅电极1均设置在有源层2的同一侧上。根据栅电极1相对有源层2的位置，共面TFT其分为顶栅型共面TFT(结合图1所示)和底栅型共面TFT(结合图2所示)。
当共面TFT用于TFT-LCD中时，对于顶栅型共面TFT，如图1所示，像素电极5通过贯穿钝化层102和栅绝缘层101的过孔与漏电极4电性接触。由于过孔的深度过大，导致爬坡困难，像素电极5容易断线，出现电性接触不良。而如果以跳接的形式实现像素电极5与漏电极4的电性连接时，会增加Mask数量，提高生产成本。而对于底栅型共面TFT，如图2所示，有源层2搭接在源电极3和漏电极4上，形成源电极3和漏电极4的刻蚀工艺导致源漏金属的侧面粗糙，由于有源层2的厚度很薄而且源电极3和漏电极4的侧面粗糙，当有源层2搭接在源电极3和漏电极4上时，容易发生爬坡问题，导致有源层2容易断线。而且上述情况下，有源层2的厚度不均匀，在加电过程中容易击穿短路。
发明内容
本公开提供一种薄膜晶体管及其制作方法，用以解决共面薄膜晶体管及其应用存在的上述技术问题。
本公开还通过一种阵列基板及显示装置，通过采用上述的薄膜晶体管，用以提高器件的良率。
为解决上述技术问题，本公开实施例中提供一种薄膜晶体管，包括：
有源层，整个所述有源层位于同一平面内；
位于有源层上、与所述有源层接触设置的源电极；
位于源电极上的第一绝缘层，所述第一绝缘层包括第一过孔；
位于所述第一绝缘层上的漏电极，所述漏电极通过第一过孔与有源层接触。
本公开实施例中还提供一种薄膜晶体管的制作方法，包括：
形成有源层，整个所述有源层位于同一平面内；
在所述有源层上形成与所述有源层接触设置的源电极；
在所述源电极上形成第一绝缘层，并在所述第一绝缘层中形成第一过孔；
在所述第一绝缘层上形成漏电极，所述漏电极通过第一过孔与有源层接触。
同时，本公开实施例中还提供一种阵列基板，包括：
如上所述的薄膜晶体管；
覆盖薄膜晶体管的漏电极的第二绝缘层；
位于所述第二绝缘层上的像素电极，所述第二绝缘层中具有第三过孔，所述像素电极通过所述第三过孔与薄膜晶体管的漏电极电性接触。
本公开实施例中还提供一种显示装置，包括如上所述的阵列基板。
本公开实施例中还提供一种阵列基板的制作方法，包括：
形成有源层，整个所述有源层位于同一平面内；
在所述有源层上形成与所述有源层接触设置的源电极；
在所述源电极上形成第一绝缘层，并在所述第一绝缘层中形成第一过孔；
在所述第一绝缘层上形成栅金属层，对所述栅金属层进行构图工艺，形成栅电极的第二部分和漏电极，所述漏电极通过第一绝缘层中的第一过孔与有源层接触；
形成覆盖漏电极的第二绝缘层；在所述第二绝缘层中形成第二过孔和第三过孔；
在所述第二绝缘层上形成栅电极的第一部分，所述第一部分具有对应源电极和漏电极之间区域的部分，并通过第二绝缘层中的第二过孔与栅电极的第二部分电性接触；
在形成栅电极的第一部分的同时，形成阵列基板的像素电极，像素电极通过第三过孔与漏电极电性接触。
本公开的上述技术方案的有益效果如下：
上述技术方案中，通过设置薄膜晶体管的源电极和漏电极位于有源层上，保证有源层位于同一平面内，克服了现有技术中有源层由于爬坡困难导致的易断线问题。而且有源层的厚度均匀，不会出现击穿短路现象，提高了薄膜晶体管的良率。并设置源电极和漏电极为非同层结构，能够灵活调节源电极和漏电极的距离，更易实现窄沟道，提高薄膜晶体管的性能。
附图说明
为了更清楚地说明本公开实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1表示现有技术中顶栅型共面薄膜晶体管阵列基板的结构示意图；
图2表示现有技术中底栅型共面薄膜晶体管阵列基板的结构示意图；
图3表示本公开实施例中共面薄膜晶体管阵列基板的结构示意图；
图4-图9表示本公开实施例中共面薄膜晶体管阵列基板的制作过程示意图。
具体实施方式
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置 关系，当被描述对象的绝对位置改变后，则该相对位置关系也相应地改变。
本公开提供一种薄膜晶体管，其源电极和漏电极位于有源层上，整个有源层位于同一平面内，从而有源层不存在爬坡困难导致的易断线问题。而且有源层的厚度均匀，在工作过程中不易出现击穿短路现象，提高了薄膜晶体管的良率。并设置源电极和漏电极为非同层结构，能够灵活调节源电极和漏电极的距离，更易实现窄沟道，提高薄膜晶体管的性能。
对于液晶显示器件，阵列基板上与薄膜晶体管的漏电极电性接触的电极为透明的像素电极，材料可以为铟锡氧化物(ITO)或铟锌氧化物(IZO)。对于有机发光二极管(OLED)显示器件，阵列基板上与驱动薄膜晶体管的漏电极电性接触的底电极为OLED的阴极或阳极，其可以为透明导电材料，也可以为不透明导电材料(如：Cu、Al)，并且，通常底电极又称作像素电极(本公开均称其为像素电极)。
下面将结合附图和实施例，对本公开的具体实施方式作进一步详细描述。以下实施例用于说明本公开，但不用来限制本公开的范围。
结合图3和图8所示，本公开实施例中提供一种薄膜晶体管，其整个有源层2位于同一平面内。所述薄膜晶体管的源电极3和漏电极4位于有源层2上，并与有源层2接触设置。源电极3和漏电极4之间设置有第一绝缘层130。漏电极4设置在第一绝缘层130上，通过第一绝缘层130中的第一过孔6与有源层2接触。
上述技术方案中，有源层2位于同一平面内，不会出现爬坡困难导致的易断线问题，而且其厚度均匀，在工作过程中不易击穿短路，克服了现有技术中底栅型共面薄膜晶体管存在的技术问题。同时，源电极3和漏电极4为非同层结构，更易实现窄沟道，提高薄膜晶体管的性能。
结合图3所示，本公开实施例中薄膜晶体管的制作方法包括：
形成有源层2，整个所述有源层2位于同一平面内；
在有源层2上形成与有源层2接触设置的源电极3；
在源电极3上形成第一绝缘层130，并在第一绝缘层130中形成第一过孔6；
在第一绝缘层130上形成漏电极4，漏电极4通过第一过孔6与有源层2 接触。
其中，源电极3与漏电极4为非同层结构，两者由不同膜层形成。
其中，源电极3可以位于薄膜晶体管的有源层2所在的区域内，且整个源电极3与有源层2接触设置，如图3所示。在实际制作工艺中，可以通过一次构图工艺中同时形成源电极3和有源层2，以简化制作工艺。结合图4-图7所示，形成源电极3和有源层2的构图工艺具体包括：
形成有源层薄膜110；
在有源层薄膜110上形成源金属层120，如图4所示；
在源金属层120上涂覆光刻胶，对光刻胶进行曝光、显影，形成光刻胶完全保留区域200、光刻胶半保留区域201和光刻胶不保留区域202，光刻胶完全保留区域200对应薄膜晶体管的源电极所在的区域，光刻胶半保留区域201对应薄膜晶体管的有源层不与源电极位置对应的区域，光刻胶不保留区域202对应其他区域，如图5所示；
刻蚀掉光刻胶不保留区域202的源金属层和有源层薄膜，形成有源层2的图案，如图6所示；
去除光刻胶半保留区域201的光刻胶；
刻蚀掉光刻胶半保留区域201的源金属层；
剥离剩余的光刻胶，形成薄膜晶体管的有源层2和源电极3，如图7所示。
上述步骤通过一次构图工艺同时形成薄膜晶体管的有源层2和源电极3。
相对于现有技术中的顶栅型共面结构，通过一次构图工艺同时形成薄膜晶体管的有源层2和源电极3，可以有效减小源电极3的宽度。而源电极3与漏电极4为非同层结构，两者由不同膜层形成，在薄膜晶体管的投影宽度一定的情况下，能够适当增加漏电极4的宽度(对比图1和图3可见)。而且，漏电极4与像素电极5之间可以仅设置一层第二绝缘层140，则像素电极5通过第二绝缘层140中的过孔与漏电极4电性接触时，过孔深度较小，不易出现断线的问题，提高了器件的良率。
此外，还可以设计栅电极的一部分和阵列基板的像素电极5为同层结构，并保证栅电极和像素电极5之间的距离足够远，使两者之间形成的耦合电容 足够小，不会影响器件的性能。
具体地，在本公开的一个实施例中，顶栅型共面薄膜晶体管的栅电极包括位于第二绝缘层140上的第一部分10，第一部分10具有对应源电极3和漏电极4之间区域的部分。可选地，栅电极的第一部分10与阵列基板的像素电极5为同层结构，由同一膜层形成。具体地，可以通过在第二绝缘层140上形成导电层，并对所述导电层进行构图工艺来形成栅电极的第一部分10和像素电极5，栅电极的第一部分10具有对应源电极3和漏电极4之间区域的部分。
则，薄膜晶体管的制作方法还包括：
形成覆盖漏电极4的第二绝缘层140；
形成栅电极，所述栅电极包括位于第二绝缘层140上的第一部分10，第一部分10具有对应源电极3和漏电极4之间区域的部分，结合图3所示。
其中，栅电极的第一部分10与阵列基板的像素电极5为同层结构，由同一导电层形成。像素电极5通过第二绝缘层140中的第三过孔8与漏电极4电性接触，结合图3和图9所示。由于像素电极5和漏电极4之间只有一层第二绝缘层140，第三过孔8的深度较小，像素电极5不会出现爬坡困难导致的易断线问题，提高了器件的良率。
进一步地，所述栅电极还可以包括第二部分11，与栅电极的第一部分10电性连接，其材料为栅金属。而且，可以在不改变传输信号的配线结构的前提下，仍然通过栅线(由栅金属层形成，与栅电极的第二部分11为同层结构)向栅电极传输开启或关闭薄膜晶体管的信号，不会增加制作工艺，便于实现。其中，栅电极的第二部分11可以与漏电极4为同层结构，由同一栅金属层形成。并且，第二绝缘层140覆盖栅电极的第二部分11和漏电极4。
作为一个可选的实施方式，阵列基板为顶栅型共面薄膜晶体管阵列基板，薄膜晶体管的栅电极包括第一部分10和第二部分11。第一部分10具有对应源电极3和漏电极4之间区域的部分，并与阵列基板的像素电极5为同层结构。第二部分11的材料为栅金属，与漏电极4为同层结构，源电极3由源金属层形成。栅电极的第一部分10与第二部分11之间设置有第二绝缘层140，并通过第二绝缘层140中的第二过孔7电性接触。相应地，阵列基板的制作 方法包括：
形成薄膜晶体管的有源层2和源电极3，源电极3与有源层2电性接触；
在源电极3上形成第一绝缘层130，并在第一绝缘层130中形成第一过孔6；
形成栅金属层，对所述栅金属层进行构图工艺，形成栅电极的第二部分11和漏电极4；漏电极4通过第一绝缘层130中的第一过孔6与有源层2接触；
形成覆盖漏电极4的第二绝缘层140；
在第二绝缘层140上形成导电层，对所述导电层进行构图工艺，形成栅电极的第一部分10和阵列基板的像素电极5，所述栅电极的第一部分10具有对应源电极3和漏电极4之间区域的部分，并通过第二绝缘层140中的第二过孔7与第二部分11电性接触，像素电极5通过第二绝缘层140中的第三过孔8与漏电极4电性接触。
上述步骤中，可选地，薄膜晶体管的有源层2和源电极3通过一次构图工艺形成，以简化制作工艺。当然，也可以通过两次构图工艺，分别形成有源层2和源电极3。
对于顶栅型共面薄膜晶体管，当栅电极包括材料为栅金属并与漏电极4为同层结构的第二部分11时，可选地，设置第二部分11位于源电极3远离漏电极4的一侧，如图3所示，以减小第二部分11与源电极3、漏电极4之间形成的耦合电容，提高器件的显示品质。
结合图3所示，本公开实施例中的薄膜晶体管具体包括：
有源层2，整个所述有源层2位于同一平面内；
设置在有源层2上的源电极3，位于有源层2所在的区域内，且整个源电极2与有源层2接触设置；
设置在源电极3上的第一绝缘层130，第一绝缘层130中具有第一过孔；
设置在第一绝缘层130上的栅电极的第二部分11和漏电极4，漏电极4通过所述第一过孔与有源层2接触设置，栅电极的第二部分11和漏电极4为同层结构，材料为栅金属，第二部分11位于源电极3远离漏电极4的一侧；
设置在漏电极4上的第二绝缘层140，第二绝缘层140中具有第二过孔7 和第三过孔8；
设置在第二绝缘层140上的栅电极的第一部分10，通过所述第二过孔7与第二部分11电性接触。
本公开实施例中的阵列基板具体包括：
上述的薄膜晶体管；
覆盖薄膜晶体管的漏电极4的第二绝缘层140；
像素电极5，设置在第二绝缘层140上，与栅电极的第一部分10为同层结构，通过第二绝缘层140中的第三过孔与漏电极4电性接触。
结合图3-图9所示，本公开实施例中薄膜晶体管的制作方法具体包括：
步骤S1、提供一衬底基板100，如：玻璃基板、石英基板、有机树脂基板等透明基板，并在衬底基板100上形成有源层2和源电极3。
其中，有源层2的材料可以为硅半导体，也可以为金属氧化物半导体。源电极3的材料为Cu，Al，Ag，Mo，Cr，Nd，Ni，Mn，Ti，Ta，W等金属以及这些金属的合金，源电极3可以为单层结构或者多层结构，多层结构比如Cu\Mo，Ti\Cu\Ti，Mo\Al\Mo等。
具体地，在衬底基板100上形成有源层2和源电极3的步骤可以包括：
在衬底基板100上依次形成有源层薄膜110和源金属层120；
在源金属层120上涂覆光刻胶，对光刻胶进行曝光、显影，形成光刻胶完全保留区域200、光刻胶半保留区域201和光刻胶不保留区域202，光刻胶完全保留区域200对应薄膜晶体管的源电极所在的区域，光刻胶半保留区域201对应薄膜晶体管的有源层不与源电极位置对应的区域，光刻胶不保留区域202对应其他区域，如图5所示；
刻蚀掉光刻胶不保留区域202的源金属层和有源层薄膜，形成有源层的图案2，如图6所示；
去除光刻胶半保留区域201的光刻胶；
刻蚀掉光刻胶半保留区域201的源金属层；
剥离剩余的光刻胶，形成薄膜晶体管的有源层2和源电极3，如图7所示。
步骤S2、在完成步骤S1的衬底基板100上形成第一绝缘层130，对第一 绝缘层130进行构图工艺形成第一过孔6，露出有源层2，如图8所示。
第一绝缘层130可以是SiNx，SiOx或Si(ON)x。
步骤S3、在完成步骤S2的衬底基板100上形成栅金属层(图中未示出)，对所述栅金属层进行构图工艺，形成栅电极的第二部分11、漏电极4和栅线，其中，栅电极的第二部分11与栅线电性连接，漏电极4通过第一过孔6与有源层2电性接触，结合图8和图9所示。
其中，栅金属层可以是Cu，Al，Ag，Mo，Cr，Nd，Ni，Mn，Ti，Ta，W等金属以及这些金属的合金，栅金属层可以为单层结构或者多层结构，多层结构比如Cu\Mo，Ti\Cu\Ti，Mo\Al\Mo等。
步骤S4、在完成步骤S3的衬底基板100上形成第二绝缘层140，对第二绝缘层140进行构图工艺形成第二过孔7和第三过孔8，如图9所示。
第二绝缘层140可以是SiNx，SiOx或Si(ON)x。
步骤S5、在完成步骤S4的衬底基板100上形成导电层，对所述导电层进行构图工艺，形成栅电极的第一部分10，栅电极的第一部分10具有对应源电极3和漏电极4之间区域的部分，通过第二过孔7与第二部分11电性接触，结合图3和图9所示。
至此完成薄膜晶体管的制作。
本公开实施例中阵列基板的制作方法具体包括：
通过上述步骤S1-S5形成薄膜晶体管，并在步骤S5中形成栅电极的第一部分10的同时，形成阵列基板的像素电极5，像素电极5通过第三过孔8与漏电极4电性接触，结合图3和图9所示。
其中，形成栅电极的第一部分10和像素电极5的步骤具体为：
在完成步骤S4的衬底基板100上形成导电层，对所述导电层进行构图工艺，形成栅电极的第一部分10和像素电极5。
本公开实施例中还提供一种显示装置，包括如上所述的阵列基板，用以提高显示器件的良率和显示品质。
所述显示装置可以为液晶显示装置，也可以为有机发光二极管显示装置。具体的，所述显示装置可以为：液晶面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示 功能的产品或部件。
本公开的技术方案，通过设置薄膜晶体管的源电极和漏电极位于有源层上，保证有源层位于同一平面内，克服了现有技术中有源层由于爬坡困难导致的易断线问题，而且有源层的厚度均匀，不会出现击穿短路现象，提高了薄膜晶体管的良率。并设置源电极和漏电极为非同层结构，能够灵活调节源电极和漏电极的距离，更易实现窄沟道，提高薄膜晶体管的性能。
以上所述仅是本公开的可选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开技术原理的前提下，还可以做出若干改进和替换，这些改进和替换也应视为本公开的保护范围。

Claims (17)

  1. 一种薄膜晶体管，包括：
    有源层，整个所述有源层位于同一平面内；
    位于有源层上、与所述有源层接触设置的源电极；
    位于源电极上的第一绝缘层，所述第一绝缘层包括第一过孔；
    位于所述第一绝缘层上的漏电极，所述漏电极通过第一过孔与有源层接触。
  2. 根据权利要求1所述的薄膜晶体管，还包括：
    覆盖漏电极的第二绝缘层；
    栅电极，包括位于所述第二绝缘层上的第一部分，所述第一部分具有对应源电极和漏电极之间区域的部分。
  3. 根据权利要求2所述的薄膜晶体管，其中，所述栅电极还包括第二部分，与栅电极的第一部分电性连接；
    所述漏电极与所述栅电极的第二部分为同层结构，所述第二绝缘层覆盖所述栅电极的第二部分和漏电极。
  4. 根据权利要求3所述的薄膜晶体管，其中，所述栅电极的第二部分位于源电极远离漏电极的一侧。
  5. 根据权利要求3所述的薄膜晶体管，其中，所述第二绝缘层包括第二过孔，所述栅电极的第一部分通过所述第二过孔与栅电极的第二部分电性接触。
  6. 根据权利要求3所述的薄膜晶体管，其中，所述栅电极的第二部分和漏电极的材料为栅金属。
  7. 根据权利要求2所述的薄膜晶体管，其中，所述栅电极的第一部分为透明导电材料。
  8. 根据权利要求1-7任一项所述的薄膜晶体管，其中，所述源电极位于薄膜晶体管的有源层所在的区域内，且整个源电极与所述有源层接触设置。
  9. 一种薄膜晶体管的制作方法，包括：
    形成有源层，整个所述有源层位于同一平面内；
    在所述有源层上形成与所述有源层接触设置的源电极；
    在所述源电极上形成第一绝缘层，并在所述第一绝缘层中形成第一过孔；
    在所述第一绝缘层上形成漏电极，所述漏电极通过第一过孔与有源层接触。
  10. 根据权利要求9所述的制作方法，还包括：
    形成覆盖漏电极的第二绝缘层；
    形成栅电极，所述栅电极包括位于所述第二绝缘层上的第一部分，所述第一部分具有对应源电极和漏电极之间区域的部分。
  11. 根据权利要求10所述的制作方法，还包括：
    在所述第二绝缘层中形成第二过孔；
    形成栅电极和漏电极的步骤包括：
    在所述第一绝缘层上形成栅金属层，对所述栅金属层进行构图工艺，形成栅电极的第二部分和漏电极，所述漏电极通过第一绝缘层中的第一过孔与有源层接触；
    在所述第二绝缘层上形成导电层，对所述导电层进行构图工艺，形成栅电极的第一部分，所述栅电极的第一部分具有对应源电极和漏电极之间区域的部分，并通过第二绝缘层中的第二过孔与栅电极的第二部分电性接触。
  12. 根据权利要求9-11任一项所述的制作方法，其中，形成有源层和源电极的步骤包括：
    形成有源层薄膜；
    在所述有源层薄膜上形成源金属层；
    在所述源金属层上涂覆光刻胶，对光刻胶进行曝光、显影，形成光刻胶完全保留区域、光刻胶半保留区域和光刻胶不保留区域，所述光刻胶完全保留区域对应薄膜晶体管的源电极所在的区域，所述光刻胶半保留区域对应薄膜晶体管的有源层不与源电极位置对应的区域，所述光刻胶不保留区域对应其他区域；
    刻蚀掉光刻胶不保留区域的源金属层和有源层薄膜，形成有源层的图案；
    去除光刻胶半保留区域的光刻胶；
    刻蚀掉光刻胶半保留区域的源金属层；
    剥离剩余的光刻胶，形成薄膜晶体管的有源层和源电极。
  13. 一种阵列基板，包括：
    权利要求1-8任一项所述的薄膜晶体管；
    覆盖薄膜晶体管的漏电极的第二绝缘层，所述第二绝缘层中具有第三过孔；
    位于所述第二绝缘层上的像素电极，所述像素电极通过所述第三过孔与薄膜晶体管的漏电极电性接触。
  14. 根据权利要求13所述的阵列基板，还包括：
    栅电极，包括位于所述第二绝缘层上的第一部分，所述第一部分具有对应源电极和漏电极之间区域的部分，所述栅电极的第一部分与像素电极为同层结构。
  15. 一种显示装置，其中，包括权利要求13或14所述的阵列基板。
  16. 一种阵列基板的制作方法，包括：
    形成有源层，整个所述有源层位于同一平面内；
    在所述有源层上形成与所述有源层接触设置的源电极；
    在所述源电极上形成第一绝缘层，并在所述第一绝缘层中形成第一过孔；
    在所述第一绝缘层上形成栅金属层，对所述栅金属层进行构图工艺，形成栅电极的第二部分和漏电极，所述漏电极通过第一绝缘层中的第一过孔与有源层接触；
    形成覆盖漏电极的第二绝缘层；在所述第二绝缘层中形成第二过孔和第三过孔；
    在所述第二绝缘层上形成栅电极的第一部分，所述第一部分具有对应源电极和漏电极之间区域的部分，并通过第二绝缘层中的第二过孔与栅电极的第二部分电性接触；
    在形成栅电极的第一部分的同时，形成阵列基板的像素电极，像素电极通过第三过孔与漏电极电性接触。
  17. 根据权利要求16所述的制作方法，其中，形成栅电极的第一部分和像素电极的步骤具体为：
    在所述第二绝缘层上形成导电层，对所述导电层进行构图工艺，形成栅 电极的第一部分和像素电极。
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Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104716196B (zh) 2015-03-18 2017-08-08 京东方科技集团股份有限公司 薄膜晶体管及其制作方法、阵列基板及显示装置
CN105607366B (zh) * 2016-01-05 2019-03-05 京东方科技集团股份有限公司 防静电器件及其制造方法、基板
CN105826397B (zh) * 2016-05-31 2019-08-13 厦门天马微电子有限公司 薄膜晶体管及其制作方法、阵列基板及显示装置
CN107611181A (zh) * 2017-10-26 2018-01-19 京东方科技集团股份有限公司 薄膜晶体管、阵列基板及其制造方法、显示装置
CN109411545A (zh) * 2018-09-30 2019-03-01 南京中电熊猫平板显示科技有限公司 一种薄膜晶体管及其制造方法
CN109659238B (zh) * 2019-03-12 2019-05-31 南京中电熊猫平板显示科技有限公司 一种薄膜晶体管及其制造方法
CN111430380A (zh) * 2020-04-14 2020-07-17 Tcl华星光电技术有限公司 显示面板及其制作方法
CN112530978B (zh) * 2020-12-01 2024-02-13 京东方科技集团股份有限公司 开关器件结构及其制备方法、薄膜晶体管膜层、显示面板
CN115295609A (zh) * 2022-08-24 2022-11-04 惠科股份有限公司 薄膜晶体管、薄膜晶体管的制备方法及显示面板

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101154677A (zh) * 2006-09-27 2008-04-02 群康科技(深圳)有限公司 主动矩阵式有机电激发光显示器及其制造方法
CN102054833A (zh) * 2009-11-09 2011-05-11 京东方科技集团股份有限公司 薄膜晶体管基板及其制造方法
US20130178012A1 (en) * 2012-01-05 2013-07-11 PengFei WANG Method for manufacturing a gate-control diode semiconductor device
CN103219389A (zh) * 2013-03-21 2013-07-24 京东方科技集团股份有限公司 一种薄膜晶体管及其制作方法、阵列基板和显示装置
CN104269379A (zh) * 2014-10-17 2015-01-07 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示装置
US20150034943A1 (en) * 2013-08-05 2015-02-05 Hannstar Display Corp. Thin film transistor array substrate
CN104716196A (zh) * 2015-03-18 2015-06-17 京东方科技集团股份有限公司 薄膜晶体管及其制作方法、阵列基板及显示装置

Family Cites Families (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5100816A (en) * 1990-07-20 1992-03-31 Texas Instruments Incorporated Method of forming a field effect transistor on the surface of a substrate
JP3615556B2 (ja) * 1992-11-04 2005-02-02 セイコーエプソン株式会社 アクティブマトリックス基板とその製造方法
CN1462481A (zh) * 2001-05-18 2003-12-17 三洋电机株式会社 薄膜晶体管及有源矩阵型显示装置及其制造方法
JP2003179233A (ja) * 2001-12-13 2003-06-27 Fuji Xerox Co Ltd 薄膜トランジスタ、及びそれを備えた表示素子
KR100887997B1 (ko) * 2002-12-26 2009-03-09 엘지디스플레이 주식회사 기생 용량 편차가 최소화된 액정 표시 장치용 박막트랜지스터
KR100760939B1 (ko) * 2003-05-23 2007-09-21 엘지.필립스 엘시디 주식회사 반사투과형 액정표시장치 및 그의 제조방법
KR100611147B1 (ko) 2003-11-25 2006-08-09 삼성에스디아이 주식회사 유기전계발광표시장치
KR100966453B1 (ko) * 2005-12-30 2010-06-28 엘지디스플레이 주식회사 액정표시소자 제조방법
TWI267213B (en) * 2006-01-27 2006-11-21 Ind Tech Res Inst Organic light emitting device with integrated color filter and method of manufacturing the same
JP2009194351A (ja) * 2007-04-27 2009-08-27 Canon Inc 薄膜トランジスタおよびその製造方法
JP5567770B2 (ja) * 2007-09-21 2014-08-06 株式会社ジャパンディスプレイ 表示装置及び表示装置の製造方法
KR101406889B1 (ko) * 2007-12-24 2014-06-13 삼성디스플레이 주식회사 박막트랜지스터 및 그의 제조 방법
JP5213458B2 (ja) * 2008-01-08 2013-06-19 キヤノン株式会社 アモルファス酸化物及び電界効果型トランジスタ
JP2009267399A (ja) * 2008-04-04 2009-11-12 Fujifilm Corp 半導体装置，半導体装置の製造方法，表示装置及び表示装置の製造方法
WO2011037102A1 (ja) 2009-09-28 2011-03-31 凸版印刷株式会社 アクティブマトリクス基板及びその製造方法並びに画像表示装置
KR101600879B1 (ko) * 2010-03-16 2016-03-09 삼성디스플레이 주식회사 박막트랜지스터, 그 제조방법 및 박막트랜지스터를 이용한 표시기판
JP5812730B2 (ja) * 2010-07-13 2015-11-17 住友化学株式会社 有機半導体組成物、有機薄膜及びこれを備える有機薄膜トランジスタ
CN102082179A (zh) * 2010-11-04 2011-06-01 友达光电股份有限公司 薄膜晶体管与具有此薄膜晶体管的像素结构
JP2013050509A (ja) * 2011-08-30 2013-03-14 Panasonic Liquid Crystal Display Co Ltd 液晶表示装置
CN102543886B (zh) * 2012-01-05 2014-09-03 复旦大学 一种栅控二极管半导体存储器器件的制造方法
KR101884891B1 (ko) * 2012-02-08 2018-08-31 삼성디스플레이 주식회사 표시 장치
KR20130110490A (ko) * 2012-03-29 2013-10-10 삼성디스플레이 주식회사 어레이 기판 및 이의 제조 방법
KR101924078B1 (ko) * 2012-03-30 2018-12-03 삼성디스플레이 주식회사 유기 발광 표시 장치 및 유기 발광 표시 장치의 리페어 방법
KR101980842B1 (ko) * 2012-09-06 2019-05-22 삼성디스플레이 주식회사 센싱 유닛, 플렉서블 장치 및 표시 장치
KR102046996B1 (ko) * 2012-10-16 2019-11-21 삼성디스플레이 주식회사 박막 트랜지스터 표시판
TWI471949B (zh) * 2012-11-16 2015-02-01 Innocom Tech Shenzhen Co Ltd 薄膜電晶體基板與顯示器
CN103117285B (zh) * 2013-02-04 2015-12-02 京东方科技集团股份有限公司 一种阵列基板、显示装置及阵列基板的制造方法
CN103219392B (zh) * 2013-04-10 2017-04-12 合肥京东方光电科技有限公司 薄膜晶体管、阵列基板、制备方法以及显示装置
TWI520347B (zh) * 2013-06-19 2016-02-01 中華映管股份有限公司 氧化物半導體薄膜電晶體及其製造方法
TWI520221B (zh) * 2013-07-25 2016-02-01 中華映管股份有限公司 薄膜電晶體及其製造方法
CN103715137B (zh) * 2013-12-26 2018-02-06 京东方科技集团股份有限公司 阵列基板及其制造方法、显示装置
TWM491180U (zh) * 2014-05-08 2014-12-01 中華映管股份有限公司 薄膜電晶體及畫素結構
CN104022126B (zh) * 2014-05-28 2017-04-12 京东方科技集团股份有限公司 一种阵列基板、其制作方法及显示装置
CN104241392B (zh) * 2014-07-14 2017-07-14 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法、显示基板和显示设备

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101154677A (zh) * 2006-09-27 2008-04-02 群康科技(深圳)有限公司 主动矩阵式有机电激发光显示器及其制造方法
CN102054833A (zh) * 2009-11-09 2011-05-11 京东方科技集团股份有限公司 薄膜晶体管基板及其制造方法
US20130178012A1 (en) * 2012-01-05 2013-07-11 PengFei WANG Method for manufacturing a gate-control diode semiconductor device
CN103219389A (zh) * 2013-03-21 2013-07-24 京东方科技集团股份有限公司 一种薄膜晶体管及其制作方法、阵列基板和显示装置
US20150034943A1 (en) * 2013-08-05 2015-02-05 Hannstar Display Corp. Thin film transistor array substrate
CN104269379A (zh) * 2014-10-17 2015-01-07 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示装置
CN104716196A (zh) * 2015-03-18 2015-06-17 京东方科技集团股份有限公司 薄膜晶体管及其制作方法、阵列基板及显示装置

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