WO2016165326A1 - 一种电压转换电路 - Google Patents

一种电压转换电路 Download PDF

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Publication number
WO2016165326A1
WO2016165326A1 PCT/CN2015/095064 CN2015095064W WO2016165326A1 WO 2016165326 A1 WO2016165326 A1 WO 2016165326A1 CN 2015095064 W CN2015095064 W CN 2015095064W WO 2016165326 A1 WO2016165326 A1 WO 2016165326A1
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WO
WIPO (PCT)
Prior art keywords
power transistor
transistor
turned
source
power
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2015/095064
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English (en)
French (fr)
Inventor
汪家轲
陈亮
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Huawei Technologies Co Ltd
Original Assignee
Huawei Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Priority to EP15889022.8A priority Critical patent/EP3276805B1/en
Priority to KR1020177033185A priority patent/KR20170136639A/ko
Publication of WO2016165326A1 publication Critical patent/WO2016165326A1/zh
Priority to US15/785,206 priority patent/US10148182B2/en
Anticipated expiration legal-status Critical
Priority to US16/183,233 priority patent/US10680519B2/en
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
    • H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
    • H02M3/10—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
    • H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
    • H02M3/10—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
    • H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
    • H02M3/10—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H02M3/1588—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load comprising at least one synchronous rectifier element
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • H03K17/6872—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor using complementary field-effect transistors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the present invention relates to the field of power management technologies, and in particular, to a voltage conversion circuit.
  • PMIC Power Management Intergraded Circuit
  • the existing power management integrated circuit includes a gate controller 11, a PMOS power transistor 12, and an NMOS power transistor 13, a gate of the PMOS power transistor 12, and a gate of the NMOS power transistor 13 and a gate control.
  • the device 11 is connected, the source of the PMOS power transistor 12 is connected to the first reference voltage V1, the drain of the PMOS power transistor 12 is connected to the drain of the NMOS power transistor 13, the source of the NMOS power transistor 13 is grounded, and the PMOS power transistor 12 is A parasitic inductance L1 is formed between the source and the first reference voltage, and a parasitic inductance L2 is formed between the source of the NMOS power transistor 13 and the ground.
  • the PMOS power transistor 12 When the PMOS power transistor 12 is turned off, the current flowing through the PMOS power transistor 12 is abruptly changed to 0, and the current of the parasitic inductance L1 cannot be abruptly changed, and the drain-source capacitance of the PMOS power transistor 12 continues to flow, and the source of the PMOS power transistor 12 is generated. High voltage, the drain of the PMOS power transistor 12 is subjected to high voltage, directly burning the internal components of the power management integrated circuit.
  • the prior art increases the withstand voltage of the PMOS power transistor 12 and the NMOS power transistor 13 by adding some special MASK (dopant) during the chip manufacturing process. Manufacturing costs are increased due to the need to increase dopants.
  • Embodiments of the present invention provide a voltage conversion circuit that can avoid increasing manufacturing costs.
  • the first aspect provides a voltage conversion circuit for converting a first voltage into a second voltage,
  • the method includes: a first power transistor;
  • the second power transistor is turned off when the first power transistor is turned on, and turned on when the first power transistor is turned off;
  • a second energy storage element for coupling with the first power transistor and the second power transistor, and when the first power transistor is turned on and the second power transistor is turned off, the first power storage element is supplied by the power source that supplies the first voltage
  • the second energy storage element is charged, and when the first power transistor is turned off and the second power transistor is turned on, the second energy storage element is discharged through the first power storage element through the second power transistor, the first energy storage element and the second energy storage
  • the connection end of the component outputs a second voltage, the second voltage being dependent on the first voltage, the time when the first power transistor is turned on, and the time when the second power transistor is turned on;
  • a bleeder module for coupling with the first power transistor and providing current for current flowing from the source of the first power transistor to the ground when the first power transistor is turned off and the voltage of the source of the first power transistor reaches a source threshold path.
  • the bleeder module includes a bleeder transistor for coupling with the first power transistor and the first power transistor is turned off and the voltage of the source of the first power transistor Turns on when the source threshold is reached.
  • the value of the source threshold is the sum of the first voltage and the turn-on threshold of the bleeder transistor.
  • the circuit further includes a gate controller and a resistor, and the source of the first power transistor is connected to the power source, first a gate of the power transistor and a gate of the second power transistor are connected to the gate controller, a drain of the first power transistor is connected to a drain of the second power transistor, and a source of the second power transistor is connected to the ground, first One end of the energy storage element is connected to the drain of the first power transistor, the other end of the first energy storage element is connected to one end of the second energy storage element, and the other end of the second energy storage element is connected to the ground, the resistance and the second energy The storage elements are connected in parallel.
  • the gate of the bleeder transistor is connected to the power source, and the source of the bleeder transistor and the first power are The source of the transistor is connected, and the drain of the bleeder transistor is connected to the drain of the first power transistor.
  • the bleeder transistor is turned on, the current flowing from the source of the first power transistor to the ground flows through the bleed crystal. Tube and second power transistor.
  • the gate of the bleeder transistor is connected to the power source, and the source of the bleeder transistor and the first power are The source of the transistor is connected, and the drain of the bleeder transistor is connected to the drain of the second power transistor.
  • a second aspect provides a voltage conversion circuit for converting a first voltage to a second voltage, the method comprising:
  • the second power transistor is turned off when the first power transistor is turned on, and turned on when the first power transistor is turned off;
  • a second energy storage element for coupling with the first power transistor and the second power transistor, and charging the first energy storage element by the first voltage when the first power transistor is turned on and the second power transistor is turned off
  • the second energy storage element is charged by the power supply that supplies the first voltage and the first energy storage element, and the second power transistor and the second energy storage element are connected to the second output.
  • the voltage, the second voltage depends on the first voltage, the time when the first power transistor is turned on, and the time when the second power transistor is turned on;
  • a bleeder transistor for coupling with the first power transistor and providing current for current flowing from the drain of the first power transistor to ground when the first power transistor is turned off and the voltage of the drain of the first power transistor reaches a source threshold path.
  • the bleeder module includes a bleeder transistor for coupling with the first power transistor and the first power transistor is turned off and the voltage of the drain of the first power transistor Turns on when the source threshold is reached.
  • the value of the source threshold is the sum of the first voltage and the turn-on threshold of the bleeder transistor.
  • the circuit further includes a gate controller and a resistor, and the drain of the first power transistor passes through the first energy storage component Connected to the power source, the gate of the first power transistor and the gate of the second power transistor are connected to the gate controller, the source of the first power transistor is grounded, and the drain of the second power transistor is The drain of the first power transistor is connected, the source of the second power transistor is connected to one end of the second energy storage element, the other end of the second energy storage element is grounded, and the resistor is connected in parallel with the second energy storage element.
  • the gate of the bleeder transistor is connected between the resistor and the second power transistor, and the bleeder transistor The source is connected to the drain of the first power transistor, the drain of the bleeder transistor is connected to the source of the first power transistor, and the current flowing from the drain of the first power transistor to the ground flows through the bleeder transistor.
  • a third aspect provides a voltage conversion circuit for converting a first voltage to a second voltage, the method comprising:
  • the second power transistor is turned off when the first power transistor is turned on, and turned on when the first power transistor is turned off;
  • the fourth power transistor is turned off when the third power transistor is turned on, and turned on when the third power transistor is turned off;
  • a first energy storage element for coupling with the first power transistor and the second power transistor
  • the fourth power transistor when the fourth power transistor is turned on, the third power transistor is turned off, and when the first power transistor and the second power transistor are turned off, the first energy storage element is connected to the second energy storage element by the power source that supplies the first voltage Charging, when the first power transistor is turned off and the second power transistor is turned on, the second energy storage element is discharged through the first power storage element through the second power transistor, and the connection end of the fourth power transistor and the second energy storage element is outputted a second voltage, the second voltage being dependent on the first voltage, a time when the first power transistor is turned on, and a time when the second power transistor is turned on;
  • the first power transistor When the first power transistor is turned on, the second power transistor is turned off, and when the third power transistor is turned on and the fourth power transistor is turned off, the first energy storage element is charged by the first voltage, and the fourth power transistor is turned on.
  • the third power transistor When the third power transistor is turned off, the second energy storage element is charged by the power supply that supplies the first voltage and the first energy storage element, and the second voltage and the second voltage are outputted by the connection end of the fourth power transistor and the second energy storage element.
  • a first bleeder module for coupling with the first power transistor and flowing from the source of the first power transistor to the ground when the first power transistor is turned off and the voltage of the source of the first power transistor reaches the first source threshold Current provides a current path;
  • a second bleeder module for coupling with the third power transistor and flowing from the drain of the third power transistor to the ground when the third power transistor is turned off and the voltage of the drain of the third power transistor reaches the second source threshold
  • the current provides a current path.
  • the circuit further includes a gate controller and a resistor, the source of the first power transistor is connected to the power source, the gate of the first power transistor, and the second power transistor
  • the gate, the gate of the third power transistor, and the gate of the fourth power transistor are both connected to the gate controller, the drain of the first power transistor is connected to the drain of the second power transistor, and the source of the second power transistor Grounding, one end of the first energy storage element is connected to the drain of the first power transistor, the other end of the first energy storage element is connected to the drain of the third power transistor, the source of the third power tube is grounded, and the fourth power transistor
  • the drain is connected to the drain of the third power transistor, the source of the fourth power transistor is connected to one end of the second energy storage element, the other end of the second energy storage element is grounded, and the resistor is connected in parallel with the second energy storage element.
  • the first bleeder module includes a first bleeder transistor for coupling with the first power transistor, and the first power transistor is turned off and first The voltage of the source of the power transistor is turned on when it reaches the first source threshold.
  • the value of the first source threshold is a sum of a first voltage and a turn-on threshold of the first bleeder transistor.
  • the source of the first bleeder transistor is connected to the source of the first power transistor, and the gate of the first bleeder transistor The pole is connected to the power source, and the drain of the first bleeder transistor is connected to the drain of the first power transistor.
  • the first bleeder transistor is turned on, the current flowing from the source of the first power transistor to the ground flows through the first drain The transistor and the second power transistor are placed.
  • the source of the first bleeder transistor is connected to the source of the first power transistor, and the gate of the first bleeder transistor The pole is connected to the power source, and the drain of the first bleeder transistor is connected to the drain of the second power transistor.
  • the first bleeder transistor is turned on, the current flowing from the source of the first power transistor to the ground flows through the first drain Put the transistor.
  • the second bleeder module includes a second bleeder transistor for coupling with the third power transistor, and the third power transistor is turned off and the third The voltage of the drain of the power transistor is turned on when it reaches the second source threshold.
  • the value of the second source threshold is a sum of a first voltage and a turn-on threshold of the second bleeder transistor.
  • a gate of the second bleeder transistor is connected between the resistor and the fourth power transistor, and the second bleeder transistor is The source is connected to the drain of the third power transistor, the drain of the second bleeder transistor is connected to the source of the third power transistor, and the current flowing from the drain of the third power transistor to the ground flows through the second bleeder transistor.
  • the present invention has the beneficial effects that the present invention is coupled to the first power transistor through the bleeder module, and is the first when the first power transistor is turned off and the voltage of the source of the first power transistor reaches the source threshold.
  • the current flowing to the ground of the power transistor provides a current path, which can reduce the voltage difference between the drain and the source of the first power transistor, reduce the risk of burnout of the first power transistor, and avoid increasing manufacturing costs.
  • FIG. 1 is a circuit diagram of a conventional power management integrated circuit
  • FIG. 2 is a structural diagram of a voltage conversion circuit according to a first embodiment of the present invention.
  • Figure 3 is a circuit diagram of a voltage conversion circuit of a second embodiment of the present invention.
  • Figure 4 is a circuit diagram of a voltage conversion circuit of a third embodiment of the present invention.
  • Figure 5 is a structural diagram of a voltage conversion circuit according to a fourth embodiment of the present invention.
  • Figure 6 is a circuit diagram of a voltage conversion circuit of a fifth embodiment of the present invention.
  • Figure 7 is a block diagram showing a voltage conversion circuit of a sixth embodiment of the present invention.
  • Figure 8 is a circuit diagram of a voltage conversion circuit of a seventh embodiment of the present invention.
  • Figure 9 is a circuit diagram of a voltage conversion circuit of an eighth embodiment of the present invention.
  • Figure 10 is a circuit diagram of a voltage conversion circuit of a ninth embodiment of the present invention.
  • FIG. 2 is a circuit diagram of a voltage conversion circuit according to a first embodiment of the present invention.
  • the voltage conversion circuit 20 disclosed in this embodiment includes: a power source 21, a first power transistor 22, a second power transistor 23, a first energy storage element 24, a second energy storage element 25, and a bleeder module. 26, wherein the voltage conversion circuit 20 is for converting the first voltage V1 to the second voltage V2.
  • the power source 21 is coupled to the first power transistor 22
  • the second power transistor 23 and the first energy storage element 24 are both coupled to the first power transistor 22
  • the second energy storage element 25 is coupled to the first energy storage element 24 for venting Module 26 is coupled to first power transistor 22.
  • the second power transistor 23 is turned off when the first power transistor 22 is turned on, and turned on when the first power transistor 22 is turned off.
  • the second energy storage element 25 is configured to be coupled to the first power transistor 22 and the second power transistor 23, and when the first power transistor 22 is turned on and the second power transistor 23 is turned off, is supplied by the power source 21 that supplies the first voltage V1.
  • the first energy storage element 24 charges the second energy storage element 25, and the current that the power source 21 charges the second energy storage element 25 flows through the first power transistor 22 and the first energy storage element 24 such that the second energy storage element 25 The voltage can rise to V1.
  • the first power transistor 22 is turned off and the second power transistor 23 is turned on, the second energy storage element 25 is discharged through the first power storage element 24 through the second power transistor 23, and the second energy storage element 25 is discharged through the first current.
  • the energy storage element 24 and the second power transistor 23 are such that the voltage value of the second energy storage element 25 becomes smaller.
  • the connection end of the first energy storage element 24 and the second energy storage element 25 outputs a second voltage V2, the second voltage V2 is dependent on the first voltage V1, the time when the first power transistor 22 is turned on, and the second power transistor 23 is turned on. Time, wherein the second voltage V2 is less than the first voltage V1.
  • the first power transistor 22 is turned off and the source voltage of the first power transistor 22 reaches the source threshold In the value, the bleeder module 26 provides a current path for the current flowing from the source of the first power transistor 22 to the ground to reduce the voltage difference between the source and the drain of the first power transistor 22, reducing the first power transistor. 22 risk of burnout.
  • the first power transistor 22 is a P-type MOS transistor
  • the second power transistor 23 is an N-type MOS transistor
  • the first energy storage element 24 is an inductor
  • the second energy storage element 25 is a capacitor.
  • the bleeder module 26 disclosed in this embodiment is coupled to the first power transistor 22, and when the first power transistor 22 is turned off and the source voltage of the first power transistor 22 reaches the source threshold, the bleeder module 26 is from the first power.
  • the current flowing from the source of transistor 22 to ground provides a current path to reduce the voltage difference between the source and drain of first power transistor 22, reducing the risk of burnout of first power transistor 22.
  • the present invention also provides a voltage conversion circuit of the second embodiment, which is described on the basis of the voltage conversion circuit 20 disclosed in the first embodiment.
  • the circuit disclosed in this embodiment further includes: a first capacitor C1, a resistor R, and a gate controller 27.
  • the first capacitor C1 is connected in parallel with the power source 21, the source of the first power transistor 22 is connected to the power source 21, and the gate of the first power transistor 22 and the gate of the second power transistor 23 are connected to the gate controller 27.
  • the gate controller 27 is for controlling the on or off of the first power transistor 22 and the second power transistor 23, the drain of the first power transistor 22 is connected to the drain of the second power transistor 23, and the second power transistor 23 is The source is grounded, one end of the first energy storage element 24 is connected to the drain of the first power transistor 22, and the other end of the first energy storage element 24 is connected to one end of the second energy storage element 25, the second energy storage element 25 The other end is connected to the ground, and the resistor R is connected in parallel with the second energy storage element 25.
  • the bleeder module 26 includes a bleeder transistor, the gate of the bleeder transistor is connected to the power source 21, the source of the bleeder transistor is connected to the source of the first power transistor 22, and the drain of the bleeder transistor is connected to the first power transistor 22
  • the drain connection connects a current flowing from the source of the first power transistor 22 to the ground through the bleeder transistor and the second power transistor 23 when the bleeder transistor is turned on.
  • the power source 21 supplies the first energy storage element 24 and the second energy storage element 25 with the first voltage V1, that is, the power source 21
  • the second energy storage element 25 is charged via the first energy storage element 24, and the current that the power source 21 charges the second energy storage element 25 flows through the first power transistor 22 and the first energy storage element 24.
  • the gate controller 27 controls the first power transistor 22 to turn off and the second power transistor 23 is turned on
  • the second energy storage element 25, the first energy storage element 24, and the second power Transistor 23 forms a loop
  • second energy storage element 25 is discharged through first power storage element 24 through second power transistor 23
  • second energy storage element 25 discharge current flows through first energy storage element 24 and second power transistor 23.
  • the connection ends of the first energy storage element 24 and the second energy storage element 25 output a second voltage V2, which depends on the first voltage V1, the time when the first power transistor 22 is turned on, and the second power transistor 23 is turned on. time.
  • a first parasitic inductance Lbp is formed between the source of the first power transistor 22 and the power source 21, a source of the first power transistor 22 forms a parasitic capacitance C2 with respect to the ground, and a source and a ground of the second power transistor 23 A second parasitic inductance Lbn is formed therebetween.
  • the bleeder transistor is turned on, providing a current path for the current flowing from the source of the first power transistor 22 to the ground, that is, the first power transistor 22 A current flowing from the source to the ground flows through the bleeder transistor and the second power transistor 23 to lower the voltage of the source of the first power transistor 22.
  • the bleeder transistor is turned off.
  • the value of the source threshold is preferably the sum of the first voltage V1 and the conduction threshold of the bleeder transistor, and the bleeder transistor is preferably a P-type MOS transistor.
  • the voltage difference Vdspmos between the source S and the drain D of the first power transistor 22 is:
  • Vdspmos V1+Vth+Vd (1)
  • the voltage difference Vdspmos between the source and the drain of the first power transistor 22 is embedded, and the reliability of the first power transistor 22 can be ensured even if the first power transistor 22 is quickly turned off.
  • the present invention further provides a voltage conversion circuit of the third embodiment, which is different from the voltage conversion circuit disclosed in the second embodiment in that, as shown in FIG. 4, the gate of the bleeder transistor disclosed in this embodiment is The power source 21 is connected, the source of the bleeder transistor is connected to the source of the first power transistor 22, and the drain of the bleeder transistor is connected to the drain of the second power transistor 23, when the bleeder transistor is turned on, from the first power A current flowing from the source of the transistor 22 to the ground flows through the bleeder transistor.
  • the present invention further provides the voltage conversion circuit of the fourth embodiment.
  • the voltage conversion circuit 50 disclosed in this embodiment includes: a power source 51, a first power transistor 52, a second power transistor 53, and a first energy storage.
  • the power source 51 is coupled to the first energy storage element 54
  • the second power transistor 53 and the first energy storage element 54 are both coupled to the first power transistor 52
  • the second energy storage element 25 and the first power transistor 52 and the second power Transistor 53 is coupled and bleeder module 56 is coupled to first power transistor 52.
  • the second power transistor 53 is turned off when the first power transistor 52 is turned on, and turned on when the first power transistor 52 is turned off.
  • the first power transistor 52 When the first power transistor 52 is turned on and the second power transistor 53 is turned off, the first energy storage element 54 is charged by the first voltage V1, and the current that the power source 51 charges the first energy storage element 54 flows through the first energy storage element. 54 and the first power transistor 52 are configured to enable the voltage of the first energy storage element 54 to rise to V1.
  • the second energy storage element 55 When the first power transistor 52 is turned off and the second power transistor 53 is turned on, the second energy storage element 55 is charged by the power source 51 that supplies the first voltage V1 and the first energy storage element 54, and the second energy storage element 55 charges current. It flows through the first energy storage element 54 and the second power transistor 53.
  • connection end of the second power transistor 53 and the second energy storage element 55 outputs a second voltage V2, and the second voltage V2 depends on the first voltage V1, the time when the first power transistor 52 is turned on, and the second power transistor 53 is turned on. Time, wherein the second voltage V2 is greater than the first voltage V1.
  • the bleeder module 56 When the first power transistor 52 is turned off and the drain voltage of the first power transistor 52 reaches the source threshold, the bleeder module 56 provides a current path for current flowing from the drain of the first power transistor 52 to ground to reduce the first The voltage difference between the source and drain of power transistor 52 reduces the risk of burnout of first power transistor 52.
  • the first power transistor 52 is an N-type MOS transistor
  • the second power transistor 53 is a P-type MOS transistor
  • the first energy storage element 54 is an inductor
  • the second energy storage element 55 is a capacitor.
  • the bleeder module 56 disclosed in this embodiment is coupled to the first power transistor 52.
  • the bleeder module 56 is from the first power.
  • the current flowing from the source of transistor 52 to ground provides a current path to reduce the voltage difference between the source and drain of first power transistor 52, reducing the risk of burnout of first power transistor 52.
  • the present invention also provides a voltage conversion circuit of the fifth embodiment, which is described on the basis of the voltage conversion circuit 50 disclosed in the fourth embodiment.
  • the circuit disclosed in this embodiment further includes: a first capacitor C1, a resistor R, and a gate controller 57.
  • the first capacitor C1 is connected in parallel with the power source 51, and the drain of the first power transistor 52 passes through the first energy storage element 54 and the electricity.
  • the source 51 is connected, the gate of the first power transistor 52 and the gate of the second power transistor 53 are connected to the gate controller 57, and the gate controller 57 is used to control the conduction of the first power transistor 52 and the second power transistor 53.
  • the source of the first power transistor 52 is grounded, the drain of the second power transistor 53 is connected to the drain of the first power transistor 52, and one end of the second energy storage element 55 is opposite to the source of the second power transistor 22. Connected, the other end of the second energy storage element 55 is grounded, and the resistor R is connected in parallel with the second energy storage element 55.
  • the bleeder module 56 includes a bleeder transistor having a gate connected between the resistor R and the second power transistor 53, a source of the bleeder transistor connected to the drain of the first power transistor 52, and a drain of the bleeder transistor The pole is connected to the source of the first power transistor 52, and the current flowing from the drain of the first power transistor 52 to the ground flows through the second power transistor 53 when the bleeder transistor is turned on.
  • the power source 51 supplies the first energy storage element 54 with the first voltage V1, that is, the power source 51 to the first energy storage element 54. Charging, the current that the power source 51 charges the first energy storage element 54 flows through the first energy storage element 54 and the first power transistor 52.
  • the gate controller 57 controls the first power transistor 52 to turn off and the second power transistor 53 is turned on
  • the second energy storage element 55 is charged by the power source 51 that supplies the first voltage V1 and the first energy storage element 54 to charge current. It flows through the first energy storage element 54, the second power transistor 23, and the second energy storage element 55.
  • the connection end of the second power transistor 53 and the second energy storage element 55 outputs a second voltage V2, and the second voltage V2 depends on the first voltage V1, the time when the first power transistor 52 is turned on, and the second power transistor 53 is turned on. time.
  • a first parasitic inductance Lbn is formed between the source of the first power transistor 52 and the ground, a drain of the first power transistor 52 forms a parasitic capacitance C2 with respect to the ground, and a source and a second of the second power transistor 53
  • a second parasitic inductance Lbp is formed between the energy storage elements 55.
  • the bleeder transistor is turned on, providing a current path for the current flowing from the drain of the first power transistor 52 to the ground, that is, the first power transistor 52 A current flowing from the drain to the ground flows through the bleeder transistor to lower the voltage of the drain of the first power transistor 52.
  • the bleeder transistor is turned off.
  • the value of the source threshold is preferably the first voltage V1 and the derivative of the bleeder transistor
  • the bleeder transistor is preferably a P-type MOS transistor.
  • the present invention also provides the voltage conversion circuit of the sixth embodiment.
  • the voltage conversion circuit disclosed in this embodiment includes: a first power transistor 71, a second power transistor 72, a third power transistor 73, and a fourth.
  • the voltage conversion circuit is configured to convert the first voltage V1 into the second voltage V2.
  • the first power transistor 71 is coupled to the power source 79
  • the second power transistor 72 and the first energy storage element 75 are both coupled to the first power transistor 71
  • the third power transistor 73 and the fourth power transistor 74 are both coupled to the first energy storage.
  • Element 75 is coupled
  • second energy storage element 76 is coupled to third power transistor 73 and fourth power transistor 74
  • first bleeder module 77 is coupled to first power transistor 71
  • second bleeder module 78 and third power transistor 73 coupling The second power transistor 72 is turned off when the first power transistor 71 is turned on, and turned on when the first power transistor 71 is turned off
  • the fourth power transistor 74 is turned off when the third power transistor 73 is turned on, and is turned off at the third power transistor 73. Turn on.
  • the voltage converting circuit operates in the same manner as the voltage converting circuit 20 disclosed in the first embodiment.
  • the first power transistor 71 is turned on and the second power transistor 72 is turned off, the second energy storage element 76 is charged by the power source 79 that supplies the first voltage V1 via the first energy storage element 75, and the power source 79 is paired with the second energy.
  • the current charged by the storage element 76 flows through the first power transistor 71, the first energy storage element 75, and the fourth power transistor 74 such that the voltage of the second energy storage element 76 can rise to V1; at the first power transistor 71, When the second power transistor 72 is turned on, the second energy storage element 76 is discharged through the second power transistor 72 via the fourth power transistor 74 and the first energy storage element 75, and the second energy storage element 76 discharges current through the fourth power transistor. 74.
  • the first energy storage element 71 and the second power transistor 72 are such that the voltage value of the second energy storage element 76 becomes smaller.
  • connection end of the fourth power transistor 74 and the second energy storage element 76 outputs a second voltage V2, and the second voltage V2 depends on the first voltage V1, the time when the first power transistor 71 is turned on, and the second power transistor 72 is turned on. Time, wherein the second voltage V2 is less than the first voltage V1.
  • the first bleeder module 77 provides a current path for the current flowing from the source of the first power transistor 71 to the ground to reduce The voltage difference between the source and the drain of the first power transistor 71 is lowered by the first The risk of burnout of the power transistor 71.
  • the voltage conversion circuit When the second power transistor 72 is turned off and the first power transistor 71 is turned on, the voltage conversion circuit operates in the same manner as the voltage conversion circuit 50 disclosed in the fourth embodiment.
  • the third power transistor 73 When the third power transistor 73 is turned on and the fourth power transistor 74 is turned off, the first energy storage element 75 is charged by the first voltage V1, and the current that the power source 79 charges the first energy storage element 75 flows through the first power transistor 71.
  • the first energy storage element 75 and the third power transistor 73 are configured to enable the voltage of the first energy storage element 75 to rise to V1.
  • the second energy storage element 76 When the third power transistor 73 is turned off and the fourth power transistor 74 is turned on, the second energy storage element 76 is charged by the power source 79 that supplies the first voltage V1 and the first energy storage element 75, and the second energy storage element 76 charges current. It flows through the first power transistor 71, the first energy storage element 75, and the fourth power transistor 74.
  • the connection end of the fourth power transistor 74 and the second energy storage element 76 outputs a second voltage V2, and the second voltage V2 depends on the first voltage V1, the time when the third power transistor 73 is turned on, and the fourth power transistor 74 is turned on. Time, wherein the second voltage V2 is greater than the first voltage V1.
  • the second bleeder module 78 provides a current path for the current flowing from the drain of the third power transistor 73 to the ground to reduce The voltage difference between the source and the drain of the third power transistor 73 reduces the risk of burnout of the third power transistor 73.
  • the first power transistor 71 is a P-type MOS transistor
  • the second power transistor 72 is an N-type MOS transistor
  • the third power transistor 73 is an N-type MOS transistor
  • the fourth power transistor 74 is a P-type MOS transistor
  • the storage element 75 is an inductor and the second energy storage element 76 is a capacitor.
  • the present invention also provides a voltage conversion circuit of the eighth embodiment, which is described on the basis of the voltage conversion circuit disclosed in the seventh embodiment.
  • the circuit disclosed in this embodiment further includes a first capacitor C1, a resistor R, and a gate controller 80.
  • the first capacitor C1 is connected in parallel with the power source 79, the source of the first power transistor 71 is connected to the power source 79, the gate of the first power transistor 71, the gate of the second power transistor 72, and the gate of the third power transistor 73.
  • the gates of the poles and the fourth power transistor 74 are both connected to the gate controller 80, the drain of the first power transistor 71 is connected to the drain of the second power transistor 72, and the source of the second power transistor 72 is grounded, first One end of the energy storage element 75 is connected to the drain of the first power transistor 71, the other end of the first energy storage element 75 is connected to the drain of the third power transistor 73, and the source of the third power transistor 73 is grounded, the fourth power The drain of the transistor 74 is connected to the drain of the third power transistor 73, and the fourth power crystal The source of the tube 74 is connected to one end of the second energy storage element 76, the other end of the second energy storage element 76 is grounded, and the resistor R is connected in parallel with the second energy storage element 76.
  • the gate controller 80 controls the third power transistor 73 to turn off and the fourth power transistor turns on 74
  • the gate controller 80 also controls the first power transistor 71 to be turned on, the second power transistor 72 to be turned off, and the power source 79 to be turned first.
  • the energy storage element 75 and the second energy storage element 76 provide a first voltage V1, ie, the power source 79 is charged to the second energy storage element 76 via the first energy storage element 75, and the current that the power source 79 charges the second energy storage element 76 flows through.
  • the gate controller 80 controls the first power transistor 71 to turn off and the second power transistor 72 is turned on, the second energy storage element 76, the fourth power transistor 74, the first energy storage element 75, and the second power transistor 72 form a loop.
  • the second energy storage element 76 is discharged through the first power storage element 75 through the second power transistor 72, and the second energy storage element 76 discharge current flows through the fourth power transistor 74, the first energy storage element 75, and the second power transistor 72. .
  • the first bleeder module 77 includes a first bleeder transistor, the gate of the first bleeder transistor is connected to the power source 79, the source of the first bleeder transistor is connected to the source of the first power transistor 71, and the first bleeder transistor The drain is connected to the drain of the first power transistor 71.
  • the second voltage V2 depends on the first voltage V1, the time during which the first power transistor 71 is turned on, and the time at which the second power transistor 72 is turned on.
  • a first parasitic inductance Lbp1 is formed between the source of the first power transistor 71 and the power source 79, a source of the first power transistor 71 forms a parasitic capacitance C2 with respect to the ground, and a source and a ground of the second power transistor 72
  • a second parasitic inductance Lbn1 is formed therebetween
  • a third parasitic inductance Lbn2 is formed between the source of the third power transistor 73 and the ground
  • a drain of the third power transistor 73 forms a parasitic capacitance C3 with respect to the ground
  • the fourth power transistor 74 is
  • a fourth parasitic inductance Lbp2 is formed between the second energy storage elements 76.
  • the first power transistor 71 When the first power transistor 71 is turned off, since the current flowing through the first parasitic inductance Lbp1 cannot be abruptly changed, the current flowing through the first parasitic inductance Lbp1 continues to charge the parasitic capacitance C2, causing the source voltage of the first power transistor 71 to be charged. High, when the voltage of the source of the first power transistor 71 reaches the source threshold, the first bleeder transistor is turned on, providing a current path for the current flowing from the source of the first power transistor 71 to the ground, that is, the first power transistor A current flowing from the source of the source 71 to the ground flows through the first bleeder transistor and the second power transistor 72 to lower the voltage of the source of the first power transistor 71.
  • the first bleeder transistor When the voltage of the source of the first power transistor 71 is less than the source threshold, the first bleeder transistor is turned off.
  • the value of the source threshold is preferably the first voltage V1 and the conduction threshold of the first bleeder transistor.
  • the first bleeder transistor is preferably a P-type MOS transistor.
  • the present invention also provides the voltage conversion circuit of the ninth embodiment, which is different from the voltage conversion circuit disclosed in the eighth embodiment in that, as shown in FIG. 9, the gate of the first bleeder transistor disclosed in this embodiment The pole is connected to the power source 79, the source of the first bleeder transistor is connected to the source of the first power transistor 71, and the drain of the first bleeder transistor is connected to the drain of the second power transistor 72 at the first bleeder transistor. When turned on, current flowing from the source of the first power transistor 71 to the ground flows through the first bleeder transistor.
  • the present invention also provides the voltage conversion circuit of the tenth embodiment, which is different from the voltage conversion circuit disclosed in the eighth embodiment in that, as shown in FIG. 10, when the gate controller 80 controls the second power transistor 72 to be turned off.
  • the gate controller 80 controls the third power transistor 73 to be turned on
  • the fourth power transistor 74 is turned off
  • the power source 79 supplies the first voltage V1 to the first energy storage element 75, that is, the power source 79.
  • the first energy storage element 75 is charged, and the current that the power source 79 charges the first energy storage element 75 flows through the first power transistor 71, the first energy storage element 75, and the third power transistor 73.
  • the second bleeder module 78 includes a second bleeder transistor having a gate connected between the fourth power transistor 74 and the second energy storage element 76, a source of the second bleeder transistor and a third power The drain of the transistor 73 is connected, and the drain of the second bleeder transistor is connected to the source of the third power transistor 73.
  • the second voltage V2 depends on the first voltage V1, the time at which the third power transistor 73 is turned on, and the time at which the fourth power transistor 74 is turned on.
  • the third power transistor 73 when the third power transistor 73 is turned off, since the current flowing through the third parasitic inductance Lbn2 cannot be abruptly changed, the current flowing through the third parasitic inductance Lbn2 continues to charge the parasitic capacitance C3, resulting in the drain of the third power transistor 73.
  • the second bleeder transistor When the voltage is high, when the voltage of the drain of the third power transistor 73 reaches the source threshold, the second bleeder transistor is turned on to provide a current path for the current flowing from the drain of the third power transistor 73 to the ground, that is, the third A current flowing to the ground of the drain of the power transistor 73 flows through the second bleeder transistor to lower the voltage of the drain of the third power transistor 73.
  • the second bleeder transistor When the voltage of the drain of the third power transistor 73 is less than the source threshold, the second bleeder transistor is turned off.
  • the value of the source threshold is preferably the sum of the first voltage V1 and the conduction threshold of the second bleeder transistor, and the second bleeder transistor It is preferably a P-type MOS tube.
  • the present invention is connected in parallel with the first power transistor or the third power transistor through the bleeder module, which can reduce the voltage difference between the drain and the source of the first power transistor or the third power transistor, and reduce the first power transistor. Or the risk of burnout of the third power transistor and avoiding increased manufacturing costs.

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Abstract

一种电压转换电路（20），包括：第一功率晶体管（22）；第二功率晶体管（23），第二功率晶体管在第一功率晶体管导通时截止，在第一功率晶体管截止时导通；第一能量存储元件（24）；第二能量存储元件（25），用于与第一功率晶体管及第二功率晶体管耦合；泄放模块（26），用于与第一功率晶体管耦合，并在第一功率晶体管截止且第一功率晶体管的源极的电压达到源极阈值时为自第一功率晶体管的源极流向地的电流提供电流通路。该电压转换电路能够减小第一功率晶体管的漏极与源极之间的压差，降低第一功率晶体管烧坏的风险，并且避免增加制造成本。

Description

一种电压转换电路
本申请要求于2015年04月17日提交中国专利局、申请号为201510187425.2、发明名称为“一种电压转换电路”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及电源管理技术领域，特别是涉及一种电压转换电路。
背景技术
随着消费类的电子产品的快速发展，电源管理集成电路(Power Management Intergraded Circuit，PMIC)作为电子产品的重要部分，其具有集成度高、转换效率高、成本低等优点。近几年来，只能手机、平板电脑等电子产品快速更新换代，对电源管理集成电路的要求也越来越高。
如图1所示，现有的电源管理集成电路包括栅极控制器11、PMOS功率管12以及NMOS功率管13，PMOS功率管12的栅极和NMOS功率管13的栅极均与栅极控制器11连接，PMOS功率管12的源极与第一参考电压V1连接，PMOS功率管12的漏极与NMOS功率管13的漏极连接，NMOS功率管13的源极接地，PMOS功率管12的源极与第一参考电压之间形成寄生电感L1，NMOS功率管13的源极与接地之间形成寄生电感L2。
当PMOS功率管12关闭时，流过PMOS功率管12的电流突变为0，而寄生电感L1的电流无法突变，继续流过PMOS功率管12的漏源电容，在PMOS功率管12的源极产生高压，PMOS功率管12的漏极承受高压，直接烧毁电源管理集成电路的内部器件。
为了避免上述情况，现有技术通过在芯片制造的过程中增加一些特殊的MASK(掺杂物)，以提高PMOS功率管12和NMOS功率管13的耐压。由于需要增加掺杂物，因此增加制造成本。
发明内容
本发明实施例提供了一种电压转换电路，能够避免增加制造成本。
第一方面提供一种电压转换电路，用于将第一电压转换为第二电压，其 包括：第一功率晶体管；
第二功率晶体管，第二功率晶体管在第一功率晶体管导通时截止，在第一功率晶体管截止时导通；
第一能量存储元件；
第二能量存储元件，用于与第一功率晶体管及第二功率晶体管耦合，并在第一功率晶体管导通、第二功率晶体管截止时，由提供第一电压的电源经第一能量存储元件对第二能量存储元件充电，在第一功率晶体管截止、第二功率晶体管导通时，第二能量存储元件经第一能量存储元件通过第二功率晶体管放电，第一能量存储元件与第二能量存储元件的连接端输出第二电压，第二电压取决于第一电压、第一功率晶体管导通的时间及第二功率晶体管导通的时间；及
泄放模块，用于与第一功率晶体管耦合，并在第一功率晶体管截止且第一功率晶体管的源极的电压达到源极阈值时为自第一功率晶体管的源极流向地的电流提供电流通路。
结合第一方面的实现方式，在第一种实现方式中，泄放模块包括泄放晶体管，用于与第一功率晶体管耦合，并在第一功率晶体管截止且第一功率晶体管的源极的电压达到源极阈值时导通。
结合第一方面的第一种实现方式，在第二种实现方式中，源极阈值的值为第一电压与泄放晶体管的导通阈值的和。
结合第一方面的实现方式至第三种实现方式中的任意一种，在第三种实现方式中，电路还包括栅极控制器和电阻，第一功率晶体管的源极与电源连接，第一功率晶体管的栅极和第二功率晶体管的栅极与栅极控制器连接，第一功率晶体管的漏极与第二功率晶体管的漏极连接，第二功率晶体管的源极与地连接，第一能量存储元件的一端与第一功率晶体管的漏极连接，第一能量存储元件的另一端与第二能量存储元件的一端连接，第二能量存储元件的另一端与地连接，电阻与第二能量存储元件并联连接。
结合第一方面的第一种实现方式至第三种实现方式中的任意一种，在第四种实现方式中，泄放晶体管的栅极与电源连接，泄放晶体管的源极与第一功率晶体管的源极连接，泄放晶体管的漏极与第一功率晶体管的漏极连接，在泄放晶体管导通时，自第一功率晶体管的源极流向地的电流流经泄放晶体 管和第二功率晶体管。
结合第一方面的第一种实现方式至第三种实现方式中的任意一种，在第五种实现方式中，泄放晶体管的栅极与电源连接，泄放晶体管的源极与第一功率晶体管的源极连接，泄放晶体管的漏极与第二功率晶体管的漏极连接，在泄放晶体管导通时，自第一功率晶体管的源极流向地的电流流经泄放晶体管。
第二方面提供一种电压转换电路，用于将第一电压转换为第二电压，其包括：
第一功率晶体管；
第二功率晶体管，第二功率晶体管在第一功率晶体管导通时截止，在第一功率晶体管截止时导通；
第一能量存储元件；
第二能量存储元件，用于与第一功率晶体管及第二功率晶体管耦合，并在第一功率晶体管导通、第二功率晶体管截止时，由第一电压对第一能量存储元件充电，在第一功率晶体管截止、第二功率晶体管导通时，由提供第一电压的电源与第一能量存储元件对第二能量存储元件充电，第二功率晶体管与第二能量存储元件的连接端输出第二电压，第二电压取决于第一电压、第一功率晶体管导通的时间及第二功率晶体管导通的时间；及
泄放晶体管，用于与第一功率晶体管耦合，并在第一功率晶体管截止且第一功率晶体管的漏极的电压达到源极阈值时为自第一功率晶体管的漏极流向地的电流提供电流通路。
结合第二方面的实现方式，在第一种实现方式中，泄放模块包括泄放晶体管，用于与第一功率晶体管耦合，并在第一功率晶体管截止且第一功率晶体管的漏极的电压达到源极阈值时导通。
结合第二方面的第一种实现方式，在第二种实现方式中，源极阈值的值为第一电压与泄放晶体管的导通阈值的和。
结合第二方面的实现方式至第二种实现方式中的任意一种，在第三种实现方式中，电路还包括栅极控制器和电阻，第一功率晶体管的漏极通过第一能量存储元件与电源连接，第一功率晶体管的栅极和第二功率晶体管的栅极与栅极控制器连接，第一功率晶体管的源极接地，第二功率晶体管的漏极与 第一功率晶体管的漏极连接，第二功率晶体管的源极与第二能量存储元件的一端连接，第二能量存储元件的另一端接地，电阻与第二能量存储元件并联连接。
结合第二方面的第一种实现方式至第三种实现方式中的任意一种，在第四种实现方式中，泄放晶体管的栅极连接至电阻与第二功率晶体管之间，泄放晶体管的源极与第一功率晶体管的漏极连接，泄放晶体管的漏极与第一功率晶体管的源极连接，自第一功率晶体管的漏极流向地的电流流经泄放晶体管。
第三方面提供一种电压转换电路，用于将第一电压转换为第二电压，其包括：
第一功率晶体管；
第二功率晶体管，第二功率晶体管在第一功率晶体管导通时截止，在第一功率晶体管截止时导通；
第三功率晶体管；
第四功率晶体管，第四功率晶体管在第三功率晶体管导通时截止，在第三功率晶体管截止时导通；
第一能量存储元件，用于与第一功率晶体管以及第二功率晶体管耦合；
第二能量存储元件，用于与第三功率晶体管及第四功率晶体管耦合；
其中，在第四功率晶体管导通、第三功率晶体管截止时，并在第一功率晶体管、第二功率晶体管截止时，由提供第一电压的电源经第一能量存储元件对第二能量存储元件充电，在第一功率晶体管截止、第二功率晶体管导通时，第二能量存储元件经第一能量存储元件通过第二功率晶体管放电，第四功率晶体管与第二能量存储元件的连接端输出第二电压，第二电压取决于第一电压、第一功率晶体管导通的时间以及第二功率晶体管导通的时间；
在第一功率晶体管导通、第二功率晶体管截止时，并在第三功率晶体管导通、第四功率晶体管截止时，由第一电压对第一能量存储元件充电，在第四功率晶体管导通、第三功率晶体管截止时，由提供第一电压的电源与第一能量存储元件对第二能量存储元件充电，第四功率晶体管与第二能量存储元件的连接端输出第二电压，第二电压取决于第一电压、第三功率晶体管导通的时间以及第四功率晶体管导通的时间；
第一泄放模块，用于与第一功率晶体管耦合，并在第一功率晶体管截止且第一功率晶体管的源极的电压达到第一源极阈值时为自第一功率晶体管的源极流向地的电流提供电流通路；及
第二泄放模块，用于与第三功率晶体管耦合，并在第三功率晶体管截止且第三功率晶体管的漏极的电压达到第二源极阈值时为自第三功率晶体管的漏极流向地的电流提供电流通路。
结合第三方面的实现方式，在第一种实现方式中，电路还包括栅极控制器和电阻，第一功率晶体管的源极与电源连接，第一功率晶体管的栅极、第二功率晶体管的栅极、第三功率晶体管的栅极以及第四功率晶体管的栅极均与栅极控制器连接，第一功率晶体管的漏极与第二功率晶体管的漏极连接，第二功率晶体管的源极接地，第一能量存储元件的一端与第一功率晶体管的漏极连接，第一能量存储元件的另一端与第三功率晶体管的漏极连接，第三功率管的源极接地，第四功率晶体管的漏极与第三功率晶体管的漏极连接，第四功率晶体管的源极与第二能量存储元件的一端连接，第二能量存储元件的另一端接地，电阻与第二能量存储元件并联连接。
结合第三方面的第一种实现方式，在第二种实现方式中，第一泄放模块包括第一泄放晶体管，用于与第一功率晶体管耦合，并在第一功率晶体管截止且第一功率晶体管的源极的电压达到第一源极阈值时导通。
结合第三方面的第二种实现方式，在第三种实现方式中，第一源极阈值的值为第一电压与第一泄放晶体管的导通阈值的和。
结合第三方面的第二种实现方式或第三种实现方式，在第四种实现方式中，第一泄放晶体管的源极与第一功率晶体管的源极连接，第一泄放晶体管的栅极与电源连接，第一泄放晶体管的漏极与第一功率晶体管的漏极连接，在第一泄放晶体管导通时，自第一功率晶体管的源极流向地的电流流经第一泄放晶体管和第二功率晶体管。
结合第三方面的第二种实现方式或第三种实现方式，在第五种实现方式中，第一泄放晶体管的源极与第一功率晶体管的源极连接，第一泄放晶体管的栅极与电源连接，第一泄放晶体管的漏极与第二功率晶体管的漏极连接，在第一泄放晶体管导通时，自第一功率晶体管的源极流向地的电流流经第一泄放晶体管。
结合第三方面的第一种实现方式，在第六种实现方式中，第二泄放模块包括第二泄放晶体管，用于与第三功率晶体管耦合，并在第三功率晶体管截止且第三功率晶体管的漏极的电压达到第二源极阈值时导通。
结合第三方面的第六种实现方式，在第七种实现方式中，第二源极阈值的值为第一电压与第二泄放晶体管的导通阈值的和。
结合第三方面的第六种实现方式或第七种实现方式，在第八种实现方式中，第二泄放晶体管的栅极连接至电阻与第四功率晶体管之间，第二泄放晶体管的源极与第三功率晶体管的漏极连接，第二泄放晶体管的漏极与第三功率晶体管的源极连接，自第三功率晶体管的漏极流向地的电流流经第二泄放晶体管。
通过上述方案，本发明的有益效果是：本发明通过泄放模块与第一功率晶体管耦合，并在第一功率晶体管截止且第一功率晶体管的源极的电压达到源极阈值时为自第一功率晶体管的源极流向地的电流提供电流通路，能够减小第一功率晶体管的漏极与源极之间的压差，降低第一功率晶体管烧坏的风险，并且避免增加制造成本。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。其中：
图1是现有的电源管理集成电路的电路图；
图2是本发明第一实施例的电压转换电路的结构图；
图3是本发明第二实施例的电压转换电路的电路图；
图4是本发明第三实施例的电压转换电路的电路图；
图5是本发明第四实施例的电压转换电路的结构图；
图6是本发明第五实施例的电压转换电路的电路图；
图7是本发明第六实施例的电压转换电路的结构图；
图8是本发明第七实施例的电压转换电路的电路图；
图9是本发明第八实施例的电压转换电路的电路图；
图10是本发明第九实施例的电压转换电路的电路图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性的劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参见图2，图2是本发明第一实施例的电压转换电路的电路图。如图2所示，本实施例所揭示的电压转换电路20包括：电源21、第一功率晶体管22、第二功率晶体管23、第一能量存储元件24、第二能量存储元件25以及泄放模块26，其中电压转换电路20用于将第一电压V1转换为第二电压V2。
其中，电源21与第一功率晶体管22耦合，第二功率晶体管23和第一能量存储元件24均与第一功率晶体管22耦合，第二能量存储元件25与第一能量存储元件24耦合，泄放模块26与第一功率晶体管22耦合。第二功率晶体管23在第一功率晶体管22导通时截止，在第一功率晶体管22截止时导通。
第二能量存储元件25用于与第一功率晶体管22及第二功率晶体管23耦合，并在第一功率晶体管22导通、第二功率晶体管23截止时，由提供第一电压V1的电源21经第一能量存储元件24对第二能量存储元件25充电，电源21对第二能量存储元件25充电的电流流经第一功率晶体管22和第一能量存储元件24，以使第二能量存储元件25的电压能够升到V1。在第一功率晶体管22截止、第二功率晶体管23导通时，第二能量存储元件25经第一能量存储元件24通过第二功率晶体管23放电，第二能量存储元件25放电电流流经第一能量存储元件24和第二功率晶体管23，以使第二能量存储元件25的电压值变小。第一能量存储元件24与第二能量存储元件25的连接端输出第二电压V2，第二电压V2取决于第一电压V1、第一功率晶体管22导通的时间及第二功率晶体管23导通的时间，其中第二电压V2小于第一电压V1。
在第一功率晶体管22截止且第一功率晶体管22的源极电压达到源极阈 值时，泄放模块26为自第一功率晶体管22的源极流向地的电流提供电流通路，以减小第一功率晶体管22的源极和漏极之间的电压差，降低第一功率晶体管22烧坏的风险。
优选地，第一功率晶体管22为P型MOS管，第二功率晶体管23为N型MOS管，第一能量存储元件24为电感，第二能量存储元件25为电容。
本实施例所揭示的泄放模块26与第一功率晶体管22耦合，在第一功率晶体管22截止且第一功率晶体管22的源极电压达到源极阈值时，泄放模块26为自第一功率晶体管22的源极流向地的电流提供电流通路，以减小第一功率晶体管22的源极和漏极之间的电压差，降低第一功率晶体管22烧坏的风险。
本发明还提供第二实施例的电压转换电路，其在第一实施例所揭示的电压转换电路20的基础上进行描述。如图3所示，本实施例所揭示的电路还包括：第一电容C1、电阻R以及栅极控制器27。其中，第一电容C1与电源21并联连接，第一功率晶体管22的源极与电源21连接，第一功率晶体管22的栅极和第二功率晶体管23的栅极与栅极控制器27连接，栅极控制器27用于控制第一功率晶体管22和第二功率晶体管23的导通或截止，第一功率晶体管22的漏极与第二功率晶体管23的漏极连接，第二功率晶体管23的源极接地，第一能量存储元件24的一端与第一功率晶体管22的漏极连接，第一能量存储元件24的另一端与第二能量存储元件25的一端连接，第二能量存储元件25的另一端与地连接，电阻R与第二能量存储元件25并联连接。泄放模块26包括泄放晶体管，泄放晶体管的栅极与电源21连接，泄放晶体管的源极与第一功率晶体管22的源极连接，泄放晶体管的漏极与第一功率晶体管22的漏极连接，在泄放晶体管导通时，自第一功率晶体管22的源极流向地的电流流经泄放晶体管和第二功率晶体管23。
其中，当栅极控制器27控制第一功率晶体管22导通、第二功率晶体管23截止时，电源21向第一能量存储元件24和第二能量存储元件25提供第一电压V1，即电源21经第一能量存储元件24向第二能量存储元件25充电，电源21对第二能量存储元件25充电的电流流经第一功率晶体管22和第一能量存储元件24。当栅极控制器27控制第一功率晶体管22截止，第二功率晶体管23导通时，第二能量存储元件25、第一能量存储元件24、第二功率 晶体管23形成回路，第二能量存储元件25经第一能量存储元件24通过第二功率晶体管23放电，第二能量存储元件25放电电流流经第一能量存储元件24和第二功率晶体管23。第一能量存储元件24和第二能量存储元件25的连接端输出第二电压V2，第二电压V2取决于第一电压V1、第一功率晶体管22导通的时间及第二功率晶体管23导通的时间。
其中，在第一功率晶体管22的源极与电源21之间形成第一寄生电感Lbp，第一功率晶体管22的源极相对于地形成一寄生电容C2，第二功率晶体管23的源极与地之间形成第二寄生电感Lbn。在第一功率晶体管22截止时，由于流过第一寄生电感Lbp的电流不能突变，则流过第一寄生电感Lbp的电流继续给寄生电容C2充电，导致第一功率晶体管22的源极电压充高，在第一功率晶体管22的源极的电压达到源极阈值时，泄放晶体管导通，为自第一功率晶体管22的源极流向地的电流提供电流通路，即第一功率晶体管22的源极流向地的电流流经泄放晶体管和第二功率晶体管23，以降低第一功率晶体管22的源极的电压。在第一功率晶体管22的源极的电压小于源极阈值时，泄放晶体管截止。源极阈值的值优选为第一电压V1与泄放晶体管的导通阈值的和，泄放晶体管优选为P型MOS管。
其中第一功率晶体管22的源极S和漏极D之间的压差Vdspmos为：
Vdspmos＝V1+Vth+Vd         (1)
根据公式(1)可知，第一功率晶体管22的源极和漏极之间的压差Vdspmos被嵌位住，即使第一功率晶体管22快速关闭，也可以保证第一功率晶体管22的可靠性。
本发明还提供第三实施例的电压转换电路，其与第二实施例所揭示的电压转换电路的不同之处在于：如图4所示，本实施例所揭示的泄放晶体管的栅极与电源21连接，泄放晶体管的源极与第一功率晶体管22的源极连接，泄放晶体管的漏极与第二功率晶体管23的漏极连接，在泄放晶体管导通时，自第一功率晶体管22的源极流向地的电流流经泄放晶体管。
本发明还提供第四实施例的电压转换电路，如图5所示，本实施例所揭示的电压转换电路50包括：电源51、第一功率晶体管52、第二功率晶体管53、第一能量存储元件54、第二能量存储元件55以及泄放模块56，其中电压转换电路50用于将第一电压V1转换为第二电压V2。
其中，电源51与第一能量存储元件54耦合，第二功率晶体管53和第一能量存储元件54均与第一功率晶体管52耦合，第二能量存储元件25与第一功率晶体管52以及第二功率晶体管53耦合，泄放模块56与第一功率晶体管52耦合。第二功率晶体管53在第一功率晶体管52导通时截止，在第一功率晶体管52截止时导通。
在第一功率晶体管52导通、第二功率晶体管53截止时，由第一电压V1对第一能量存储元件54充电，电源51对第一能量存储元件54充电的电流流经第一能量存储元件54和第一功率晶体管52，以使第一能量存储元件54的电压能够升到V1。在第一功率晶体管52截止、第二功率晶体管53导通时，由提供第一电压V1的电源51与第一能量存储元件54对第二能量存储元件55充电，第二能量存储元件55充电电流流经第一能量存储元件54和第二功率晶体管53。第二功率晶体管53与第二能量存储元件55的连接端输出第二电压V2，第二电压V2取决于第一电压V1、第一功率晶体管52导通的时间及第二功率晶体管53导通的时间，其中第二电压V2大于第一电压V1。
在第一功率晶体管52截止且第一功率晶体管52的漏极电压达到源极阈值时，泄放模块56为自第一功率晶体管52的漏极流向地的电流提供电流通路，以减小第一功率晶体管52的源极和漏极之间的电压差，降低第一功率晶体管52烧坏的风险。
优选地，第一功率晶体管52为N型MOS管，第二功率晶体管53为P型MOS管，第一能量存储元件54为电感，第二能量存储元件55为电容。
本实施例所揭示的泄放模块56与第一功率晶体管52耦合，在第一功率晶体管52截止且第一功率晶体管52的漏极电压达到源极阈值时，泄放模块56为自第一功率晶体管52的源极流向地的电流提供电流通路，以减小第一功率晶体管52的源极和漏极之间的电压差，降低第一功率晶体管52烧坏的风险。
本发明还提供第五实施例的电压转换电路，其在第四实施例所揭示的电压转换电路50的基础上进行描述。如图6所示，本实施例所揭示的电路还包括：第一电容C1、电阻R以及栅极控制器57。其中，第一电容C1与电源51并联连接，第一功率晶体管52的漏极通过第一能量存储元件54与电 源51连接，第一功率晶体管52的栅极和第二功率晶体管53的栅极与栅极控制器57连接，栅极控制器57用于控制第一功率晶体管52和第二功率晶体管53的导通或截止，第一功率晶体管52的源极接地，第二功率晶体管53的漏极与第一功率晶体管52的漏极连接，第二能量存储元件55的一端与第二功率晶体管22的源极连接，第二能量存储元件55的另一端接地，电阻R与第二能量存储元件55并联连接。泄放模块56包括泄放晶体管，泄放晶体管的栅极连接至电阻R与第二功率晶体管53之间，泄放晶体管的源极与第一功率晶体管52的漏极连接，泄放晶体管的漏极与第一功率晶体管52的源极连接，在泄放晶体管导通时，自第一功率晶体管52的漏极流向地的电流流经第二功率晶体管53。
其中，当栅极控制器57控制第一功率晶体管52导通、第二功率晶体管53截止时，电源51向第一能量存储元件54提供第一电压V1，即电源51向第一能量存储元件54充电，电源51对第一能量存储元件54充电的电流流经第一能量存储元件54和第一功率晶体管52。当栅极控制器57控制第一功率晶体管52截止，第二功率晶体管53导通时，由提供第一电压V1的电源51与第一能量存储元件54对第二能量存储元件55充电，充电电流流经第一能量存储元件54、第二功率晶体管23和第二能量存储元件55。第二功率晶体管53与第二能量存储元件55的连接端输出第二电压V2，第二电压V2取决于第一电压V1、第一功率晶体管52导通的时间及第二功率晶体管53导通的时间。
其中，在第一功率晶体管52的源极与地之间形成第一寄生电感Lbn，第一功率晶体管52的漏极相对于地形成一寄生电容C2，第二功率晶体管53的源极与第二能量存储元件55之间形成第二寄生电感Lbp。在第一功率晶体管52截止时，由于流过第一寄生电感Lbn的电流不能突变，则流过第一寄生电感Lbn的电流继续给寄生电容C2充电，导致第一功率晶体管52的漏极电压充高，在第一功率晶体管52的漏极的电压达到源极阈值时，泄放晶体管导通，为自第一功率晶体管52的漏极流向地的电流提供电流通路，即第一功率晶体管52的漏极流向地的电流流经泄放晶体管，以降低第一功率晶体管52的漏极的电压。在第一功率晶体管52的漏极的电压小于源极阈值时，泄放晶体管截止。源极阈值的值优选为第一电压V1与泄放晶体管的导 通阈值的和，泄放晶体管优选为P型MOS管。
本发明还提供第六实施例的电压转换电路，如图7所示，本实施例所揭示的电压转换电路包括：第一功率晶体管71、第二功率晶体管72、第三功率晶体管73、第四功率晶体管74、第一能量存储元件75、第二能量存储元件76、第一泄放模块77、第二泄放模块78以及电源79。其中电压转换电路用于将第一电压V1转换为第二电压V2。
其中，第一功率晶体管71与电源79耦合，第二功率晶体管72和第一能量存储元件75均与第一功率晶体管71耦合，第三功率晶体管73和第四功率晶体管74均与第一能量存储元件75耦合，第二能量存储元件76与第三功率晶体管73和第四功率晶体管74耦合，第一泄放模块77与第一功率晶体管71耦合，第二泄放模块78与第三功率晶体管73耦合。第二功率晶体管72在第一功率晶体管71导通时截止，在第一功率晶体管71截止时导通；第四功率晶体管74在第三功率晶体管73导通时截止，在第三功率晶体管73截止时导通。
当第三功率晶体管73截止，第四功率晶体管74导通时，电压转换电路与第一实施例所揭示的电压转换电路20工作原理相同。在第一功率晶体管71导通、第二功率晶体管72截止时，由提供第一电压V1的电源79经第一能量存储元件75对所述第二能量存储元件76充电，电源79对第二能量存储元件76充电的电流流经第一功率晶体管71、第一能量存储元件75以及第四功率晶体管74，以使第二能量存储元件76的电压能够升到V1；在第一功率晶体管71截止、第二功率晶体管72导通时，第二能量存储元件76经第四功率晶体管74和第一能量存储元件75通过第二功率晶体管72放电，第二能量存储元件76放电电流流经第四功率晶体管74、第一能量存储元件71和第二功率晶体管72，以使第二能量存储元件76的电压值变小。第四功率晶体管74与第二能量存储元件76的连接端输出第二电压V2，第二电压V2取决于第一电压V1、第一功率晶体管71导通的时间及第二功率晶体管72导通的时间，其中第二电压V2小于第一电压V1。
在第一功率晶体管71截止且第一功率晶体管71的源极电压达到源极阈值时，第一泄放模块77为自第一功率晶体管71的源极流向地的电流提供电流通路，以减小第一功率晶体管71的源极和漏极之间的电压差，降低第一 功率晶体管71烧坏的风险。
当第二功率晶体管72截止，第一功率晶体管71导通时，电压转换电路与第四实施例所揭示的电压转换电路50工作原理相同。在第三功率晶体管73导通、第四功率晶体管74截止时，由第一电压V1对第一能量存储元件75充电，电源79对第一能量存储元件75充电的电流流经第一功率晶体管71、第一能量存储元件75和第三功率晶体管73，以使第一能量存储元件75的电压能够升到V1。在第三功率晶体管73截止、第四功率晶体管74导通时，由提供第一电压V1的电源79与第一能量存储元件75对第二能量存储元件76充电，第二能量存储元件76充电电流流经第一功率晶体管71、第一能量存储元件75和第四功率晶体管74。第四功率晶体管74与第二能量存储元件76的连接端输出第二电压V2，第二电压V2取决于第一电压V1、第三功率晶体管73导通的时间及第四功率晶体管74导通的时间，其中第二电压V2大于第一电压V1。
在第三功率晶体管73截止且第三功率晶体管73的漏极电压达到源极阈值时，第二泄放模块78为自第三功率晶体管73的漏极流向地的电流提供电流通路，以减小第三功率晶体管73的源极和漏极之间的电压差，降低第三功率晶体管73烧坏的风险。
优选地，第一功率晶体管71为P型MOS管，第二功率晶体管72为N型MOS管，第三功率晶体管73为N型MOS管，第四功率晶体管74为P型MOS管，第一能量存储元件75为电感，第二能量存储元件76为电容。
本发明还提供第八实施例的电压转换电路，其在第七实施例所揭示的电压转换电路的基础上进行描述。如图8所示，本实施例所揭示的电路还包括第一电容C1、电阻R以及栅极控制器80。其中，第一电容C1与电源79并联连接，第一功率晶体管71的源极与电源79连接，第一功率晶体管71的栅极、第二功率晶体管72的栅极、第三功率晶体管73的栅极以及第四功率晶体管74的栅极均与栅极控制器80连接，第一功率晶体管71的漏极与第二功率晶体管72的漏极连接，第二功率晶体管72的源极接地，第一能量存储元件75的一端与第一功率晶体管71的漏极连接，第一能量存储元件75的另一端与第三功率晶体管73的漏极连接，第三功率晶体管73的源极接地，第四功率晶体管74的漏极与第三功率晶体管73的漏极连接，第四功率晶体 管74的源极与第二能量存储元件76的一端连接，第二能量存储元件76的另一端接地，电阻R与第二能量存储元件76并联连接。
当栅极控制器80控制第三功率晶体管73截止，第四功率晶体管导通74时，栅极控制器80还控制第一功率晶体管71导通、第二功率晶体管72截止，电源79向第一能量存储元件75和第二能量存储元件76提供第一电压V1，即电源79经第一能量存储元件75向第二能量存储元件76充电，电源79对第二能量存储元件76充电的电流流经第一功率晶体管71、第一能量存储元件75以及第四功率晶体管74。当栅极控制器80控制第一功率晶体管71截止，第二功率晶体管72导通时，第二能量存储元件76、第四功率晶体管74、第一能量存储元件75、第二功率晶体管72形成回路，第二能量存储元件76经第一能量存储元件75通过第二功率晶体管72放电，第二能量存储元件76放电电流流经第四功率晶体管74、第一能量存储元件75和第二功率晶体管72。第一泄放模块77包括第一泄放晶体管，第一泄放晶体管的栅极与电源79连接，第一泄放晶体管的源极与第一功率晶体管71的源极连接，第一泄放晶体管的漏极与第一功率晶体管71的漏极连接。第二电压V2取决于第一电压V1、第一功率晶体管71导通的时间及第二功率晶体管72导通的时间。
其中，在第一功率晶体管71的源极与电源79之间形成第一寄生电感Lbp1，第一功率晶体管71的源极相对于地形成一寄生电容C2，第二功率晶体管72的源极与地之间形成第二寄生电感Lbn1，第三功率晶体管73的源极与地之间形成第三寄生电感Lbn2，第三功率晶体管73的漏极相对于地形成寄生电容C3，第四功率晶体管74与第二能量存储元件76之间形成第四寄生电感Lbp2。在第一功率晶体管71截止时，由于流过第一寄生电感Lbp1的电流不能突变，则流过第一寄生电感Lbp1的电流继续给寄生电容C2充电，导致第一功率晶体管71的源极电压充高，在第一功率晶体管71的源极的电压达到源极阈值时，第一泄放晶体管导通，为自第一功率晶体管71的源极流向地的电流提供电流通路，即第一功率晶体管71的源极流向地的电流流经第一泄放晶体管和第二功率晶体管72，以降低第一功率晶体管71的源极的电压。在第一功率晶体管71的源极的电压小于源极阈值时，第一泄放晶体管截止。源极阈值的值优选为第一电压V1与第一泄放晶体管的导通阈值 的和，第一泄放晶体管优选为P型MOS管。
本发明还提供第九实施例的电压转换电路，其与第八实施例所揭示的电压转换电路的不同之处在于：如图9所示，本实施例所揭示的第一泄放晶体管的栅极与电源79连接，第一泄放晶体管的源极与第一功率晶体管71的源极连接，第一泄放晶体管的漏极与第二功率晶体管72的漏极连接，在第一泄放晶体管导通时，自第一功率晶体管71的源极流向地的电流流经第一泄放晶体管。
本发明还提供第十实施例的电压转换电路，其与第八实施例所揭示的电压转换电路的不同之处在于：如图10所示，当栅极控制器80控制第二功率晶体管72截止，第一功率晶体管导通71时，栅极控制器80还控制第三功率晶体管73导通、第四功率晶体管74截止，电源79向第一能量存储元件75提供第一电压V1，即电源79向第一能量存储元件75充电，电源79对第一能量存储元件75充电的电流流经第一功率晶体管71、第一能量存储元件75以及第三功率晶体管73。当栅极控制器80控制第三功率晶体管73截止，第四功率晶体管74导通时，由提供第一电压V1的电源79与第一能量存储元件75对第二能量存储元件76充电，充电电流流经第一功率晶体管71、第一能量存储元件75、第四功率晶体管74和第二能量存储元件76。第二泄放模块78包括第二泄放晶体管，第二泄放晶体管的栅极连接至第四功率晶体管74和第二能量存储元件76之间，第二泄放晶体管的源极与第三功率晶体管73的漏极连接，第二泄放晶体管的漏极与第三功率晶体管73的源极连接。第二电压V2取决于第一电压V1、第三功率晶体管73导通的时间及第四功率晶体管74导通的时间。
其中，在第三功率晶体管73截止时，由于流过第三寄生电感Lbn2的电流不能突变，则流过第三寄生电感Lbn2的电流继续给寄生电容C3充电，导致第三功率晶体管73的漏极电压充高，在第三功率晶体管73的漏极的电压达到源极阈值时，第二泄放晶体管导通，为自第三功率晶体管73的漏极流向地的电流提供电流通路，即第三功率晶体管73的漏极流向地的电流流经第二泄放晶体管，以降低第三功率晶体管73的漏极的电压。在第三功率晶体管73的漏极的电压小于源极阈值时，第二泄放晶体管截止。源极阈值的值优选为第一电压V1与第二泄放晶体管的导通阈值的和，第二泄放晶体管 优选为P型MOS管。
综上所述，本发明通过泄放模块与第一功率晶体管或者第三功率晶体管并联连接，能够减少第一功率晶体管或第三功率晶体管的漏极与源极的压差，降低第一功率晶体管或第三功率晶体管烧坏的风险，并且避免增加制造成本。
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (20)

  1. 一种电压转换电路，用于将第一电压转换为第二电压，其特征在于，包括：
    第一功率晶体管；
    第二功率晶体管，所述第二功率晶体管在所述第一功率晶体管导通时截止，在所述第一功率晶体管截止时导通；
    第一能量存储元件；
    第二能量存储元件，用于与所述第一功率晶体管及第二功率晶体管耦合，并在所述第一功率晶体管导通、所述第二功率晶体管截止时，由提供所述第一电压的电源经第一能量存储元件对所述第二能量存储元件充电，在所述第一功率晶体管截止、所述第二功率晶体管导通时，所述第二能量存储元件经所述第一能量存储元件通过所述第二功率晶体管放电，所述第一能量存储元件与所述第二能量存储元件的连接端输出所述第二电压，所述第二电压取决于所述第一电压、所述第一功率晶体管导通的时间及所述第二功率晶体管导通的时间；及
    泄放模块，用于与所述第一功率晶体管耦合，并在所述第一功率晶体管截止且所述第一功率晶体管的源极的电压达到源极阈值时为自所述第一功率晶体管的源极流向地的电流提供电流通路。
  2. 根据权利要求1所述的电路，其特征在于，所述泄放模块包括泄放晶体管，用于与所述第一功率晶体管耦合，并在所述第一功率晶体管截止且所述第一功率晶体管的源极的电压达到源极阈值时导通。
  3. 根据权利要求2所述的电路，其特征在于，所述源极阈值的值为所述第一电压与所述泄放晶体管的导通阈值的和。
  4. 根据权利要求1-3任意一项所述的电路，其特征在于，所述电路还包括栅极控制器和电阻，所述第一功率晶体管的源极与所述电源连接，所述第一功率晶体管的栅极和所述第二功率晶体管的栅极与所述栅极控制器连接，所述第一功率晶体管的漏极与所述第二功率晶体管的漏极连接，所述第二功率晶体管的源极与地连接，所述第一能量存储元件的一端与所述第一功率晶体管的漏极连接，所述第一能量存储元件的另一端与所述第二能量存储元件的一端连接，所述第二能量存储元件的另一端与地连接，所述电阻与所 述第二能量存储元件并联连接。
  5. 根据权利要求2-4任意一项所述的电路，其特征在于，所述泄放晶体管的栅极与所述电源连接，所述泄放晶体管的源极与所述第一功率晶体管的源极连接，所述泄放晶体管的漏极与所述第一功率晶体管的漏极连接，在所述泄放晶体管导通时，自所述第一功率晶体管的源极流向地的电流流经所述泄放晶体管和所述第二功率晶体管。
  6. 根据权利要求2-4任意一项所述的电路，其特征在于，所述泄放晶体管的栅极与所述电源连接，所述泄放晶体管的源极与所述第一功率晶体管的源极连接，所述泄放晶体管的漏极与所述第二功率晶体管的漏极连接，在所述泄放晶体管导通时，自所述第一功率晶体管的源极流向地的电流流经所述泄放晶体管。
  7. 一种电压转换电路，用于将第一电压转换为第二电压，其特征在于，包括：
    第一功率晶体管；
    第二功率晶体管，所述第二功率晶体管在所述第一功率晶体管导通时截止，在所述第一功率晶体管截止时导通；
    第一能量存储元件；
    第二能量存储元件，用于与所述第一功率晶体管及第二功率晶体管耦合，并在所述第一功率晶体管导通、所述第二功率晶体管截止时，由所述第一电压对所述第一能量存储元件充电，在所述第一功率晶体管截止、所述第二功率晶体管导通时，由提供所述第一电压的电源与所述第一能量存储元件对所述第二能量存储元件充电，所述第二功率晶体管与所述第二能量存储元件的连接端输出所述第二电压，所述第二电压取决于所述第一电压、所述第一功率晶体管导通的时间及所述第二功率晶体管导通的时间；及
    泄放晶体管，用于与所述第一功率晶体管耦合，并在所述第一功率晶体管截止且所述第一功率晶体管的漏极的电压达到源极阈值时为自所述第一功率晶体管的漏极流向地的电流提供电流通路。
  8. 根据权利要求7所述的电路，其特征在于，所述泄放模块包括泄放晶体管，用于与所述第一功率晶体管耦合，并在所述第一功率晶体管截止且所述第一功率晶体管的漏极的电压达到源极阈值时导通。
  9. 根据权利要求8所述的电路，其特征在于，所述源极阈值的值为所述第一电压与所述泄放晶体管的导通阈值的和。
  10. 根据权利要求7-9任意一项所述的电路，其特征在于，所述电路还包括栅极控制器和电阻，所述第一功率晶体管的漏极通过所述第一能量存储元件与所述电源连接，所述第一功率晶体管的栅极和所述第二功率晶体管的栅极与所述栅极控制器连接，所述第一功率晶体管的源极接地，所述第二功率晶体管的漏极与所述第一功率晶体管的漏极连接，所述第二功率晶体管的源极与所述第二能量存储元件的一端连接，所述第二能量存储元件的另一端接地，所述电阻与所述第二能量存储元件并联连接。
  11. 根据权利要求8-10任意一项所述的电路，其特征在于，所述泄放晶体管的栅极连接至所述电阻与所述第二功率晶体管之间，所述泄放晶体管的源极与所述第一功率晶体管的漏极连接，所述泄放晶体管的漏极与所述第一功率晶体管的源极连接，自所述第一功率晶体管的漏极流向地的电流流经所述泄放晶体管。
  12. 一种电压转换电路，用于将第一电压转换为第二电压，其特征在于，包括：
    第一功率晶体管；
    第二功率晶体管，所述第二功率晶体管在所述第一功率晶体管导通时截止，在所述第一功率晶体管截止时导通；
    第三功率晶体管；
    第四功率晶体管，所述第四功率晶体管在所述第三功率晶体管导通时截止，在所述第三功率晶体管截止时导通；
    第一能量存储元件，用于与所述第一功率晶体管和第二功率晶体管耦合；
    第二能量存储元件，用于与所述第三功率晶体管及第四功率晶体管耦合；
    其中，在所述第四功率晶体管导通、所述第三功率晶体管截至时，并在所述第一功率晶体管导通、所述第二功率晶体管截止时，由提供所述第一电压的电源经第一能量存储元件对所述第二能量存储元件充电，在所述第一功率晶体管截止、所述第二功率晶体管导通时，所述第二能量存储元件经所述 第一能量存储元件通过所述第二功率晶体管放电，所述第四功率晶体管与所述第二能量存储元件的连接端输出所述第二电压，所述第二电压取决于所述第一电压、所述第一功率晶体管导通的时间以及所述第二功率晶体管导通的时间；
    在所述第一功率晶体管导通、所述第二功率晶体管截至时，并在所述第三功率晶体管导通、所述第四功率晶体管截止时，由所述第一电压对所述第一能量存储元件充电，在所述第四功率晶体管导通、所述第三功率晶体管截止时，由提供所述第一电压的电源与所述第一能量存储元件对所述第二能量存储元件充电；所述第四功率晶体管与所述第二能量存储元件的连接端输出所述第二电压，所述第二电压取决于所述第一电压、所述第三功率晶体管导通的时间以及所述第四功率晶体管导通的时间；
    第一泄放模块，用于与所述第一功率晶体管耦合，并在所述第一功率晶体管截止且所述第一功率晶体管的源极的电压达到第一源极阈值时为自所述第一功率晶体管的源极流向地的电流提供电流通路；及
    第二泄放模块，用于与所述第三功率晶体管耦合，并在所述第三功率晶体管截止且所述第三功率晶体管的漏极的电压达到第二源极阈值时为自所述第三功率晶体管的漏极流向地的电流提供电流通路。
  13. 根据权利要求12所述的电路，其特征在于，所述电路还包括栅极控制器和电阻，所述第一功率晶体管的源极与所述电源连接，所述第一功率晶体管的栅极、所述第二功率晶体管的栅极、所述第三功率晶体管的栅极以及所述第四功率晶体管的栅极均与所述栅极控制器连接，所述第一功率晶体管的漏极与所述第二功率晶体管的漏极连接，所述第二功率晶体管的源极接地，所述第一能量存储元件的一端与所述第一功率晶体管的漏极连接，所述第一能量存储元件的另一端与所述第三功率晶体管的漏极连接，所述第三功率管的源极接地，所述第四功率晶体管的漏极与所述第三功率晶体管的漏极连接，所述第四功率晶体管的源极与所述第二能量存储元件的一端连接，所述第二能量存储元件的另一端接地，所述电阻与所述第二能量存储元件并联连接。
  14. 根据权利要求13所述的电路，其特征在于，所述第一泄放模块包括第一泄放晶体管，用于与所述第一功率晶体管耦合，并在所述第一功率晶 体管截止且所述第一功率晶体管的源极的电压达到第一源极阈值时导通。
  15. 根据权利要求14所述的电路，其特征在于，所述第一源极阈值的值为所述第一电压与所述第一泄放晶体管的导通阈值的和。
  16. 根据权利要求14或15所述的电路，其特征在于，所述第一泄放晶体管的源极与所述第一功率晶体管的源极连接，所述第一泄放晶体管的栅极与所述电源连接，所述第一泄放晶体管的漏极与所述第一功率晶体管的漏极连接，在所述第一泄放晶体管导通时，自所述第一功率晶体管的源极流向地的电流流经所述第一泄放晶体管和所述第二功率晶体管。
  17. 根据权利要求14或15所述的电路，其特征在于，所述第一泄放晶体管的源极与所述第一功率晶体管的源极连接，所述第一泄放晶体管的栅极与所述电源连接，所述第一泄放晶体管的漏极与所述第二功率晶体管的漏极连接，在所述第一泄放晶体管导通时，自所述第一功率晶体管的源极流向地的电流流经所述第一泄放晶体管。
  18. 根据权利要求13所述的电路，其特征在于，所述第二泄放模块包括第二泄放晶体管，用于与所述第三功率晶体管耦合，并在所述第三功率晶体管截止且所述第三功率晶体管的漏极的电压达到第二源极阈值时导通。
  19. 根据权利要求18所述的电路，其特征在于，所述第二源极阈值的值为所述第一电压与所述第二泄放晶体管的导通阈值的和。
  20. 根据权利要求18或19所述的电路，其特征在于，所述第二泄放晶体管的栅极连接至所述电阻与所述第四功率晶体管之间，所述第二泄放晶体管的源极与所述第三功率晶体管的漏极连接，所述第二泄放晶体管的漏极与所述第三功率晶体管的源极连接，自所述第三功率晶体管的漏极流向地的电流流经所述第二泄放晶体管。
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