WO2016179740A1 - 处理信号的方法及装置 - Google Patents

处理信号的方法及装置 Download PDF

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Publication number
WO2016179740A1
WO2016179740A1 PCT/CN2015/078526 CN2015078526W WO2016179740A1 WO 2016179740 A1 WO2016179740 A1 WO 2016179740A1 CN 2015078526 W CN2015078526 W CN 2015078526W WO 2016179740 A1 WO2016179740 A1 WO 2016179740A1
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Prior art keywords
signals
signal
input signal
filtered
frequency domain
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English (en)
French (fr)
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庄良
杨刚华
梁文亮
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Priority to CN201580030466.9A priority Critical patent/CN106462556B/zh
Priority to EP15891447.3A priority patent/EP3211538A4/en
Priority to PCT/CN2015/078526 priority patent/WO2016179740A1/zh
Publication of WO2016179740A1 publication Critical patent/WO2016179740A1/zh
Priority to US15/650,619 priority patent/US10826464B2/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/0211—Frequency selective networks using specific transformation algorithms, e.g. WALSH functions, Fermat transforms, Mersenne transforms, polynomial transforms, Hilbert transforms
    • H03H17/0213—Frequency domain filters using Fourier transforms
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/14—Fourier, Walsh or analogous domain transformations, e.g. Laplace, Hilbert, Karhunen-Loeve, transforms
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/14—Fourier, Walsh or analogous domain transformations, e.g. Laplace, Hilbert, Karhunen-Loeve, transforms
    • G06F17/141—Discrete Fourier transforms
    • G06F17/142—Fast Fourier transforms, e.g. using a Cooley-Tukey type algorithm
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/14—Fourier, Walsh or analogous domain transformations, e.g. Laplace, Hilbert, Karhunen-Loeve, transforms
    • G06F17/147—Discrete orthonormal transforms, e.g. discrete cosine transform, discrete sine transform, and variations therefrom, e.g. modified discrete cosine transform, integer transforms approximating the discrete cosine transform
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/0202—Two or more dimensional filters; Filters for complex signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/0211—Frequency selective networks using specific transformation algorithms, e.g. WALSH functions, Fermat transforms, Mersenne transforms, polynomial transforms, Hilbert transforms
    • H03H17/0213—Frequency domain filters using Fourier transforms
    • H03H2017/0214—Frequency domain filters using Fourier transforms with input-sampling frequency and output-delivery frequency which differ, e.g. interpolation, extrapolation; anti-aliasing

Definitions

  • Embodiments of the present invention relate to the field of communications and, more particularly, to methods and apparatus for processing signals.
  • FFT Fast Fourier Transform
  • IFFT Inverse Fast Fourier Transform
  • FFT and IFFT are widely used to realize the conversion of the signal in the time domain and the frequency domain.
  • FFT and IFFT are required in a single carrier system to achieve frequency domain equalization.
  • the amount of computation of the FFT and IFFT is related to the number of samples of the FFT and IFFT.
  • the number of additions to the direct FFT transform is approximately Nlog 2 N, and the number of multiplications is approximately Where N is the number of samples.
  • N is the number of samples.
  • SC-FDE single-carrier frequency domain equalization
  • the FFT or IFFT real-time calculation pressure is small.
  • the number of samples of the signal increases, the computational complexity of FFT and IFFT increases, and the computational complexity increases, which brings difficulties for real-time processing.
  • how to quickly implement FFT and IFFT and reduce its computational complexity is an urgent problem to be solved in broadband communication systems.
  • Embodiments of the present invention provide a method and apparatus for processing a signal, which can reduce computational complexity.
  • a method of processing a signal comprising: performing M-path filtering on an input signal to decompose the input signal into M filtered signals, the input signal being a time domain signal having N sampling points
  • M is an integer greater than or equal to 2
  • N is a positive integer
  • the sum of the sampling points is N; performing fast Fourier transform FFT on the M decimation signals to obtain M frequency domain signals; and determining an output signal according to the M frequency domain signals.
  • the M filtered signals are The frequency band of each filtered signal occupies 1/M of the frequency band of the input signal.
  • the number of sampling points of each of the extracted signals is N/M.
  • the performing M-path filtering on the input signal to decompose the input signal into M filtered signals includes: The input signal is copied to obtain M replica signals of the input signal; the M replica signals are separately filtered in series or in parallel to obtain the M filtered signals.
  • a second aspect provides a method for processing a signal, comprising: decomposing an input signal to obtain M decomposition signals, wherein frequency bands of the M decomposition signals do not overlap each other, and the input signal is N sampling points.
  • a frequency domain signal a sum of sampling points of the M decomposition signals is N, M is an integer greater than or equal to 2, and N is a positive integer; performing inverse fast Fourier transform IFFT on the M decomposition signals to obtain M Time domain signal; interpolating M time domain signals respectively, obtaining M interpolation signals, the number of sampling points of each interpolation signal is N; respectively filtering the M interpolation signals to obtain M filtered signals;
  • the M filtered signals determine an output signal.
  • a frequency band of each of the resolved signals occupies 1/M of a frequency band of the input signal.
  • the number of sampling points of each of the decomposition signals is N/M.
  • the performing the fast Fourier transform IFFT on the M decomposition signals respectively, to obtain M time domain signals including: serial or Performing fast inverse Fourier transform IFFT on the M decomposition signals in parallel to obtain M time domain signals.
  • a method for processing a signal includes: performing M-path first filtering on an input signal to decompose the input signal into M first filtered signals, the input signal having N sampling points
  • M is an integer greater than or equal to 2
  • N is a positive integer
  • the M first filtered signals are respectively extracted to obtain M extracts.
  • a signal the sum of the number of sampling points of the M decimated signals is N; performing fast Fourier transform FFT on the M decimated signals to obtain M frequency domain signals; performing frequency domain processing on the M frequency domain signals respectively M frequency domain processing signals are obtained.
  • the M first filtering letters The frequency band of each filtered signal in the number occupies 1/M of the frequency band of the input signal.
  • the number of sampling points of each of the extracted signals is N/M.
  • the method further includes performing an inverse fast Fourier transform IFFT on the M frequency domain processed signals to obtain M time domains. a signal; performing interpolation on the M time domain signals to obtain each M interpolation signals, and the number of sampling points of each of the interpolation signals is N; performing second filtering on the M interpolation signals to obtain M first a second filtered signal; determining an output signal based on the M second filtered signals.
  • a fourth aspect provides an apparatus for processing a signal, including: a filtering unit, where the filtering unit includes M filters, wherein the M filters are respectively used to filter an input signal to obtain M filtered signals,
  • the input signal is a time domain signal having N sampling points, the frequency bands of the M filtered signals do not overlap each other, M is an integer greater than or equal to 2, N is a positive integer;
  • the extracting unit includes the M a decimator, wherein the M decimators are connected in one-to-one correspondence with the M filters, and the M decimators are respectively configured to respectively extract the M filtered signals obtained by the filtering unit to obtain M a decimated signal, the sum of the number of sampling points of the M decimated signals is N;
  • a fast Fourier transform FFT unit the FFT unit includes M FFTs, and the M FFTs correspond to the M decimators one-to-one Connecting, the M FFTs are configured to perform fast Fourier transform FFT on the M decimated signals obtained by the decimating
  • a frequency band of each of the M filtered signals accounts for 1/M of a frequency band of the input signal.
  • the number of sampling points of each of the extracted signals is N/M.
  • the filtering unit is specifically configured to: copy the input signal to obtain M replica signals of the input signal,
  • the M filters respectively filter the M replica signals in series or in parallel to obtain the M filtered signals.
  • a fifth aspect provides an apparatus for processing a signal, comprising: a decomposition unit, configured to decompose an input signal to obtain M decomposition signals, wherein frequency bands of the M decomposition signals do not overlap each other,
  • the input signal is a frequency domain signal having N sampling points, the sum of the sampling points of the M decomposition signals is N, M is an integer greater than or equal to 2, N is a positive integer;
  • an inverse fast Fourier transform IFFT unit The IFFT unit includes M IFFTs, and the M decomposition signals are respectively input into the M IFFTs, and the M IFFTs are used to perform fast Fourier inverse on the M decomposition signals obtained by the decomposition unit respectively.
  • an interpolation unit Transforming the IFFT to obtain M time domain signals; an interpolation unit, the interpolation unit includes M interpolators, and the M interpolators are connected in one-to-one correspondence with the M IFFTs, and the M interpolators are used for
  • the M time domain signals obtained by the IFFT unit are respectively interpolated to obtain M interpolation signals, and the number of sampling points of each of the interpolation signals is N.
  • the filtering unit includes M filters, and the M The filters are connected in one-to-one correspondence with the M interpolators, and the M filters are used to respectively filter the M interpolation signals obtained by the interpolation unit to obtain M filtered signals; According to the filtering unit To the M filtered signals to determine the output signal.
  • a frequency band of each of the decomposition signals accounts for 1/M of a frequency band of the input signal.
  • the number of sampling points of each of the decomposition signals is N/M.
  • the M IFFTs are specifically configured to perform an inverse fast Fourier transform IFFT on the M decomposition signals in series or in parallel. M time domain signals.
  • an apparatus for processing a signal includes: a first filtering unit, the first filtering unit includes M first filters, and the M first filters are configured to perform an M path on the input signal Filtering to decompose the input signal into M first filtered signals, the input signal is a time domain signal having N sampling points, the frequency bands of the M first filtered signals do not overlap each other, and M is greater than Or an integer equal to 2, N is a positive integer;
  • the extracting unit includes M decimators, and the M decimators are connected in one-to-one correspondence with the M first filters, and the M decimators are used Extracting the M first filtered signals respectively to obtain M decimation signals, the sum of the number of sampling points of the M decimation signals is N;
  • a fast Fourier transform FFT unit the FFT unit includes M FFTs, The M FFTs are connected in one-to-one correspondence with the M decimators, and the M FFTs are configured to perform fast Fourier transform FFT on the M decimated signals respectively to obtain
  • a frequency band of each of the M first filtered signals accounts for 1/M of a frequency band of the input signal.
  • the number of sampling points of each of the extracted signals is N/M.
  • the apparatus further includes: an inverse fast Fourier transform IFFT unit, where the IFFT unit includes M IFFs, the M IFFTs And the M frequency-domain equalizers are respectively connected to the M frequency-domain equalizers, and the M IFFTs are used to respectively perform inverse fast Fourier transform IFFT on the M frequency-domain processing signals to obtain M time-domain signals; and an interpolation unit.
  • the IFFT unit includes M IFFs
  • the M IFFTs And the M frequency-domain equalizers are respectively connected to the M frequency-domain equalizers, and the M IFFTs are used to respectively perform inverse fast Fourier transform IFFT on the M frequency-domain processing signals to obtain M time-domain signals
  • an interpolation unit where the IFFT unit includes M IFFs, the M IFFTs And the M frequency-domain equalizers are respectively connected to the M frequency-domain equalizers, and the M IFFTs are used to respectively perform inverse fast Fourier transform IFFT on the M frequency-domain processing
  • the interpolating unit includes M interpolators, and the M interpolators are connected in one-to-one correspondence with the M IFFTs, and the M interpolators are used for interpolating the M time domain signals respectively to obtain each M Interpolating signals, the number of sampling points of each interpolation signal is N; a second filtering unit, the second filtering unit includes M second filters, and the M second filters and the M interpolators a corresponding connection, the M second filters are configured to perform second filtering on the M interpolation signals respectively to obtain M second filtered signals; and determining unit, configured to determine an output according to the M second filtered signals signal.
  • the input signal is M-channel filtered, and the filtered signal is extracted to obtain a decimation signal, so that the sum of the sampling points of the M decimation signals is the sampling point of the input signal, so that the M decimation signals can be respectively
  • the FFT is performed to avoid the problem of increasing the computational complexity caused by directly performing FFT on the input signal, and the computational complexity can be reduced.
  • FIG. 1 is a schematic flow chart of a method of processing a signal according to an embodiment of the present invention.
  • FIG. 2 is a schematic flow chart of a method of processing a signal according to another embodiment of the present invention.
  • FIG. 3 is a schematic flowchart of a method of processing a signal according to still another embodiment of the present invention.
  • FIG. 4 is a schematic diagram of a process of processing a signal according to an embodiment of the present invention.
  • 5A and 5B are two different amplitude-frequency characteristic diagrams of a decomposition filter according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of a process of processing a signal according to another embodiment of the present invention.
  • FIG. 7 is a schematic diagram of a process of processing a signal according to still another embodiment of the present invention.
  • FIG. 8 is a block diagram of an apparatus for processing signals in accordance with one embodiment of the present invention.
  • FIG. 9 is a block diagram of an apparatus for processing signals in accordance with another embodiment of the present invention.
  • FIG. 10 is a block diagram of an apparatus for processing signals in accordance with still another embodiment of the present invention.
  • FIG. 11 is a block diagram of an apparatus for processing signals in accordance with one embodiment of the present invention.
  • Figure 12 is a block diagram of an apparatus for processing signals in accordance with another embodiment of the present invention.
  • FIG. 13 is a block diagram of an apparatus for processing signals in accordance with still another embodiment of the present invention.
  • the embodiments of the present invention do not limit the specific application scenarios.
  • the technical solution of the embodiment of the present invention can be applied to various communication systems, for example, single-carrier frequency domain equalization (SC-FDE).
  • SC-FDE single-carrier frequency domain equalization
  • Embodiments of the present invention can also be applied to image processing. Any method involving the use of the method of the present invention to reduce the amount of computation of FFT or IFFT or to increase the degree of computational parallelism is within the scope of the present invention.
  • FIG. 1 is a schematic flow chart of a method of processing a signal according to an embodiment of the present invention.
  • the embodiment of the invention performs M-path filtering on the input signal, and performs filtering on the filtered signal.
  • the extracted signal is extracted, so that the sum of the sampling points of the M decimated signals is the number of sampling points of the input signal, so that the FFT can be performed on each of the M decimated signals, so as to avoid the problem of increasing the computational complexity caused by the FFT directly on the input signal. Can reduce the computational complexity.
  • the amount of computation of the FFT and IFFT is related to the number of samples for performing FFT and IFFT operations. For example, the number of additions to the FFT of the signal with the number of samples is approximately Nlog 2 N, and the number of multiplications is approximately
  • Nlog 2 N the number of samples of the FFT
  • the calculation amount of the FFT and the IFFT is also small.
  • the system bandwidth increases or decreases, the number of samples transmitted in the system will also increase dramatically.
  • the number of samples is an integer power of 2, so it is actually implemented with 65536 samples.
  • the number of additions of FFT and IFFT operations increases, and the number of multiplications increases, that is, the computational complexity increases, and the computational overhead is large.
  • N the number of sampling points of the input signal in the embodiment of the present invention.
  • N 2 m and m is a positive integer.
  • the embodiment of the present invention does not limit the number of sampling points of each extracted signal. It is within the scope of the present invention to satisfy the original signal by IFFT after the signal after extraction is satisfied.
  • the number of sampling points of each of the extracted signals is N/M.
  • N/M 2 p and p is a positive integer. It should be understood that when the number of samples of the signal is not the exponential power of 2, the signal may be zero-padded before the FFT is performed, so that the number of samples of the signal is an exponential power of 2.
  • the length of the frequency band of each filtered signal is not limited in the embodiment of the present invention. As long as the frequency band of the input signal can be decomposed into the frequency bands of the M filtered signals, such an invention is within the scope of the present invention.
  • the frequency band of each of the M filtered signals accounts for 1/M of the frequency band of the input signal.
  • the filtering in the embodiment of the present invention may be digital filtering or analog filtering. That is, the filtering process of the input signal can be implemented by digital filtering, and the filtering process of the input signal can be implemented by a plurality of filters, which is not limited in the embodiment of the present invention.
  • the M-path of the array can be decomposed and filtered by a program or a decomposition filter bank.
  • the signals of different branches are filtered by different amplitudes to preserve the signal of a certain frequency band on a certain path, and filter out the remaining frequency bands. signal.
  • the signal can be filtered according to the amplitude-frequency characteristics of the filter.
  • the input signal with the sample number N is input to the decomposition filter array, and the input signal of each channel is the same as the original input signal, and the number of samples is N.
  • M replica signals can be obtained by copying the input signals, and then the replica signals of each channel are separately processed. It should be understood that different branches can also be connected via a bus, each of which obtains the same signal as the original input signal.
  • the decomposition filter array may include M filters each having its own amplitude-frequency characteristic.
  • the input signal on the M path of the decomposition filter array may be filtered to obtain a filtered signal of each path, and M is an integer greater than or equal to 2.
  • the filtered signal of each channel is extracted to obtain a decimation signal of each channel, and the sum of the sampling points of the M decimation signals is N.
  • the fast Fourier transform FFT is performed on each of the extracted signals to obtain a frequency domain signal of each channel.
  • the signal is filtered, and the signal is divided into M signals of different frequency bands from the frequency, and M different branches respectively process one segment of the M segment signals.
  • the frequency bands of the M filtered signals in the embodiments of the present invention are not strictly defined, and it is within the protection scope of the present invention that the M frequency bands can recover the original signals substantially without distortion.
  • the mutual non-overlapping in the embodiment of the present invention may be that M filters are orthogonal to each other.
  • the filtered signal of each channel may be extracted by M times to obtain a decimation signal of each channel, and the number of samples of the demodulated signal of each channel is N/M.
  • the M-time extraction can sequentially extract one sample from the M samples as a new sample in the extracted signal. In this way, the number of samples of each signal can be changed to 1/M of the original signal sample number, that is, the long sequence signal can be split into multiple short sequence signals to perform FFT on the short sequence signal.
  • a fast Fourier transform FFT can be performed on each of the extracted signals to obtain a frequency domain signal for each channel.
  • the computational complexity can be reduced.
  • the signal transmission bandwidth is 40M
  • the embodiment of the present invention may perform serial-to-parallel conversion on a signal to be processed before performing M-path filtering on the input signal, to obtain a parallel pending signal, and then to parallel the pending signal.
  • the signal that the signal to be processed can receive can also be the generated signal.
  • the frequency domain signal of the M channel may also be subjected to frequency domain processing.
  • the frequency domain signal of the M channel is subjected to frequency domain equalization processing to obtain a frequency domain equalization signal of the M channel.
  • the frequency domain equalization signal is parallel-serial converted to obtain a serial signal corresponding to the frequency domain equalization signal, and the serial signal is determined as an output signal.
  • the M-channel frequency domain signal may be directly parallel-converted to obtain a serial signal corresponding to the M-channel frequency domain signal, and the The serial signal is determined to be an output signal.
  • the input signals on the M path can be processed separately.
  • processing separately includes performing parallel processing or serial processing on all signals of the M path.
  • M-path filtering is performed on the input signal to decompose the input signal into M filtered signals, including: replicating the input signal to obtain M replica signals of the input signal, and serially The M replica signals are separately filtered to obtain M filtered signals.
  • All signals of the M channel are serially processed, and all signals can be processed by one processor.
  • a processor is used to filter, extract, and FFT all signals of the M path. That is, each processor is separately subjected to decomposition filtering, decimation, and FFT by one processor.
  • the input signal is M-channel filtered to decompose the input signal into M filtered signals, including copying the input signal to obtain M replica signals of the input signal, in parallel
  • the M replica signals are separately filtered to obtain M filtered signals.
  • Parallel processing of all signals of the M channel can process signals of different paths through different processors. For example, each of the M channels is filtered, extracted, and FFTed by one of the M processors. That is, each channel is processed by one processor, so that the signals of the M branches can be processed in parallel by M processors.
  • the specific sequence of processing the signal of the M channel is not limited in the embodiment of the present invention.
  • the processing of the same signal on the M branches may be performed by serially processing the same signals on the M branches in turn, or parallel processing the signals on the M branches in parallel.
  • the M tributary signals may be serially processed in sequence, so that the computational complexity can be reduced by using the implementation of the present invention.
  • the processing platform has sufficient computing power, the M tributary signals can be processed in parallel, so that in addition to reducing the computational complexity, the computational parallelism can be improved, and the processing speed can be greatly accelerated.
  • the parallel processing of the embodiment of the present invention is applied to an image processing unit (GPU) to implement single instruction multi-thread (SIMT) processing of an image, or the embodiment of the present invention is
  • the parallel processing is applied to an Application-Specific Integrated Circuit (ASIC) or a Field-Programmable Gate Array (FPGA), which can greatly improve the processing speed.
  • ASIC Application-Specific Integrated Circuit
  • FPGA Field-Programmable Gate Array
  • the M signals can be simultaneously processed in the frequency domain, or each channel can be separately processed in the frequency domain.
  • frequency domain processing may be performed on one signal, or frequency domain processing may be performed on multiple signals after obtaining frequency domain signals of multiple signals. This embodiment of the present invention does not limit this.
  • the M signals can be simultaneously and serially converted, and each signal can be separately and serially converted.
  • a processor separately processes multiple signals, it is possible to perform parallel-to-serial conversion on one signal, or to perform parallel-to-serial conversion on multiple signals after obtaining frequency domain signals of multiple signals. This embodiment of the invention does not Make a limit.
  • FIG. 2 is a schematic flow chart of a method of processing a signal according to another embodiment of the present invention.
  • the input signal is a frequency domain signal having N sampling points, and the sum of the sampling points of the M decomposition signals is N, M An integer greater than or equal to 2, N is a positive integer.
  • IFFT fast inverse Fourier transform
  • the input signal is decomposed, and the decomposed signal is separately subjected to IFFT, and then the time domain signal obtained by the IFFT is interpolated, and finally the interpolated signal is filtered, and an output signal is obtained.
  • the amount of computation of the FFT and IFFT is related to the number of samples for performing FFT and IFFT operations. As the number of samples increases, the number of additions of FFT and IFFT operations increases, and the number of multiplications increases, that is, the computational complexity increases, and the computational overhead is large.
  • the embodiment of the invention provides how to reduce the computational complexity as much as possible when the number of samples of the IFFT operation increases.
  • the embodiment of the present invention does not limit the number of sampling points of each decomposition signal. It is within the scope of the present invention to satisfy the original signal by IFFT after the decomposition signal after decomposition is satisfied. The sum of the number of sampling points of the M decomposition signals is N.
  • the number of sampling points of each of the decomposition signals is N/M.
  • N/M 2 p and p is a positive integer. It should be understood that when the number of sampling points of the signal is not the exponential power of 2, the signal may be zero-padded before the IFFT filtering, so that the number of samples of the signal is an exponential power of 2.
  • the length of the frequency band of each decomposition signal is not limited in the embodiment of the present invention. As long as the frequency band of the input signal can be decomposed into the frequency bands of the M decomposed signals, such an invention is within the scope of the present invention.
  • the frequency band of each of the M decomposition signals accounts for 1/M of the frequency band of the input signal.
  • each interpolation signal can be filtered, the image is removed to obtain a signal of a certain frequency band, and then added to recover the distortion-free baseband signal.
  • the filtering in the embodiment of the present invention may be digital filtering or analog filtering. That is, the filtering processing of the signal may be implemented by means of digital filtering, and the filtering processing of the signal may be implemented by a plurality of filters, which is not limited in the embodiment of the present invention.
  • filtering each signal on the M-path of the filter array can also be implemented by a program or a filter bank, and performing different amplitude filtering processes on the sequence signals of different paths to preserve the signal of a certain frequency band and filter out Signals for the remaining bands.
  • the signal can be filtered according to the amplitude-frequency characteristic of the synthesis filter.
  • an inverse fast Fourier transform can be performed on each of the M channels of the synthesis filter array to obtain an IFFT signal for each channel.
  • N/M the number of samples per signal
  • N/M 2 p
  • p the number of samples of the interpolated signal for each path
  • N 2 m
  • m a positive integer.
  • the number of samples N of the interpolated interpolation signal. Interpolation can be used to interpolate between two samples of the original signal. For example, M times can add M-1 zero values between every two samples in the signal.
  • the interpolation signal is subjected to filtering processing to obtain a composite filtered signal for each channel.
  • the filtered signals of each channel are signals of different frequency bands.
  • the signal can be restored to the original signal by performing IFFT on the multiple short sequence signals and then interpolating and filtering the multiple short sequence signals. Decomposing the IFFT of a long-sequence signal into an IFFT of the M-channel short-sequence signal can reduce the computational complexity.
  • a filtered signal may be parallel-serial converted to obtain a serial signal corresponding to one filtered signal.
  • An embodiment of the present invention can filter the M-channel interpolation signal and synthesize the M filtered signals into a total frequency band to obtain an output signal.
  • the number of samples of the output signal is N.
  • the synthesis may be to accumulate the Qth point of each signal in the M path to obtain the Qth point of the synthesized filtered signal, and Q is a positive integer.
  • signals in the embodiments of the present invention may be video, audio, data, images, and the like.
  • the invention is not limited thereto.
  • the frequency bands of the M filtered signals in the embodiments of the present invention do not overlap each other and are not strictly limited. It is within the scope of the present invention that only M frequency bands can recover the original signal substantially without distortion.
  • the mutual non-overlapping in the embodiment of the present invention may be that M filters are orthogonal to each other.
  • the decomposition signals of the M channels can be processed separately.
  • processing separately includes performing parallel processing or serial processing on all signals of the M path.
  • performing inverse fast Fourier transform IFFT on the M decomposition signals respectively, and obtaining M time domain signals includes: performing inverse fast Fourier transform IFFT on the M decomposition signals separately, to obtain M time domain signals.
  • All signals of the M channel are serially processed, and all signals can be processed by one processor.
  • a processor is used to perform IFFT, interpolation, and filtering on all signals of the M path. That is, each signal of the M branches is respectively subjected to IFFT, interpolation, and filtering by one processor.
  • performing inverse fast Fourier transform IFFT on the M decomposition signals respectively, and obtaining M time domain signals includes: performing inverse fast Fourier transform IFFT on the M decomposition signals in parallel to obtain M Time domain signals.
  • Parallel processing of all signals of the M channel can be used to process signals of different paths by different pass processors.
  • each of the M channels is subjected to IFFT, interpolation, and filtering by one of the M processors. That is, each channel is processed by one processor, so that the signals of the M branches can be processed in parallel by M processors, which can improve the computational parallelism while reducing the computational complexity.
  • the specific sequence of processing the signal of the M channel is not limited in the embodiment of the present invention.
  • the processing of the same signal on the M road may be performed by serially processing the same signal on the M road in turn, or parallel processing the signals on the M road in parallel.
  • the M signals can be serially processed in sequence, which can reduce the computational complexity.
  • the M tributary signals can be processed in parallel, which can reduce the computational complexity and increase the computational parallelism, which can greatly speed up the processing.
  • the parallel processing of the embodiment of the present invention is applied to an image processing unit (GPU) to implement single instruction multi-thread (SIMT) processing of an image, or the embodiment of the present invention is
  • the parallel processing is applied to an Application-Specific Integrated Circuit (ASIC) or a Field-Programmable Gate Array (FPGA), which can greatly improve the processing speed.
  • ASIC Application-Specific Integrated Circuit
  • FPGA Field-Programmable Gate Array
  • the M signals can be simultaneously processed in the frequency domain, or each channel can be separately processed in the frequency domain.
  • frequency domain processing may be performed on one signal, or frequency domain processing may be performed on multiple signals after obtaining frequency domain signals of multiple signals. This embodiment of the present invention does not limit this.
  • the M signals can be simultaneously and serially converted, and each signal can be separately and serially converted.
  • a processor separately processes multiple signals, it is possible to perform parallel-to-serial conversion on one signal, or to perform parallel-to-serial conversion on multiple signals after obtaining frequency domain signals of multiple signals. This embodiment of the present invention does not limit this.
  • FFT and IFFT appear in pairs.
  • the filtering of the signal corresponding to the FFT in FIG. 1 is referred to as a first filtering
  • the filtering of the signal corresponding to the IFFT in FIG. 2 is referred to as a second filtering.
  • Two filterings should satisfy certain constraints: for example, Where M is the number of branches, H k (z) is the frequency characteristic of the first filter, F k (z) is the frequency characteristic of the second filter, and T(z) has a pure delay characteristic.
  • FIG. 3 is a schematic flowchart of a method of processing a signal according to still another embodiment of the present invention.
  • the method of Figure 3 can be performed by a receiver of a single carrier system.
  • M-path first filtering on the input signal, to decompose the input signal into M first filtered signals, where the input signal is a time domain signal having N sampling points, and frequency bands of the M first filtered signals do not overlap each other.
  • M is an integer greater than or equal to 2
  • N is a positive integer.
  • the input signal is M-channel filtered, and the filtered signal is extracted to obtain a decimation signal, so that the sum of the sampling points of the M decimation signals is the sampling point of the input signal, so that the M decimation signals can be respectively
  • the FFT is performed to avoid the problem of increasing the computational complexity caused by directly performing FFT on the input signal, and the computational complexity can be reduced.
  • N the number of sampling points of the input signal in the embodiment of the present invention.
  • N 2 m and m is a positive integer.
  • the embodiment of the present invention does not limit the number of sampling points of each extracted signal. It is within the scope of the present invention to satisfy the original signal by IFFT after the signal after extraction is satisfied.
  • the number of sampling points of each of the extracted signals is N/M.
  • N/M 2 p and p is a positive integer. It should be understood that when the number of samples of the signal is not the exponential power of 2, the signal may be zero-padded before the FFT is performed, so that the number of samples of the signal is an exponential power of 2.
  • the length of the frequency band of each first filtered signal is not limited in the embodiment of the present invention. As long as the frequency band of the input signal can be decomposed into the frequency bands of the M first filtered signals, such an invention is within the scope of the present invention.
  • the frequency band of each of the M first filtered signals accounts for 1/ of the frequency band of the input signal.
  • the frequency domain signal of the M channel may be subjected to frequency domain processing to obtain M frequency domain processed signals.
  • the frequency domain signal of the M channel is subjected to frequency domain equalization processing to obtain M frequency domain equalization signals.
  • the M frequency domain equalization signals can be used as the input signals of the IFFT, and the IFFT is performed on each of the frequency domain equalization signals on the M path.
  • the M frequency domain processed signals after obtaining the M frequency domain processed signals, performing fast inverse Fourier transform IFFT on the M frequency domain processed signals to obtain M time domain signals.
  • M time-domain signals are respectively interpolated to obtain every M interpolation signals, and the number of sampling points of each interpolation signal is N.
  • the M filtering signals are respectively subjected to second filtering to obtain M second filtered signals.
  • the output signal is determined based on the M second filtered signals.
  • each interpolation signal can be filtered, the image is removed to obtain a signal of a certain frequency band, and then added to recover the distortion-free baseband signal.
  • the filtering in the embodiment of the present invention may be digital filtering or analog filtering. That is, the filtering processing of the signal may be implemented by means of digital filtering, and the filtering processing of the signal may be implemented by a plurality of filters, which is not limited in the embodiment of the present invention. For example, filtering each signal on the M-path of the filter array can also be implemented by a program or a filter bank, and performing different amplitudes on the sequence signals of different paths.
  • the filtering process is to preserve the signal of a certain frequency band and filter out the signals of the remaining frequency bands.
  • the signal can be filtered according to the amplitude-frequency characteristic of the synthesis filter.
  • the input signals on the M path can be processed separately.
  • processing separately includes performing parallel processing or serial processing on all signals of the M path.
  • M-path filtering is performed on the input signal to decompose the input signal into M filtered signals, including: replicating the input signal to obtain M replica signals of the input signal, and serially The M replica signals are separately filtered to obtain M filtered signals.
  • All signals of the M channel are serially processed, and all signals can be processed by one processor.
  • a first processor performs first filtering, decimation, FFT, frequency domain processing, IFFT, interpolation, and second filtering on all signals of the M path.
  • performing M-path filtering on the input signal to decompose the input signal into M filtered signals including: replicating the input signal to obtain M replica signals of the input signal, in parallel The M replica signals are separately filtered to obtain M filtered signals.
  • Parallel processing of all signals of the M channel can process signals of different paths through different processors.
  • each of the M channels is subjected to first filtering, decimation, FFT, frequency domain processing, IFFT, interpolation, and second filtering, respectively, using one of the M processors.
  • FFT and IFFT appear in pairs.
  • the filtering of the signal corresponding to the FFT is referred to as a first filtering
  • the filtering of the signal corresponding to the IFFT is referred to as a second filtering.
  • Two filterings should satisfy certain constraints: for example, Where M is the number of branches, H k (z) is the frequency characteristic of the first filter, F k (z) is the frequency characteristic of the second filter, and T(z) has a pure delay characteristic.
  • FIG. 4 is a schematic diagram of a process of processing a signal according to an embodiment of the present invention.
  • M is an integer greater than or equal to 2.
  • M-path filtering is performed on the input signal to decompose the input signal into M filtered signals.
  • the input signal is a time domain signal having N sampling points, the frequency bands of the M filtered signals do not overlap each other, and M is an integer greater than or equal to 2. , N is a positive integer.
  • the signals to be processed may be serial-to-parallel converted to obtain parallel signals to be processed, and the parallel signals to be processed are used as input signals.
  • M replicated signals can be obtained by replicating parallel signals to be processed.
  • the number of samples per copy signal is the same as the number of samples of the signal to be processed, and is N.
  • M filtered signals y 0 (n), y 1 (n)...y M-1 (n) are obtained by M-path filtering processing.
  • FIG. 5A and 5B are two different amplitude-frequency characteristic diagrams of a decomposition filter according to an embodiment of the present invention.
  • M 2
  • the amplitude-frequency characteristic of the decomposition filter can be as shown in Fig. 5A.
  • the decomposition filter bank shown in Fig. 5A includes two decomposition filters, one of which may be a low-pass filter, and the amplitude of the frequency response is
  • Another decomposition filter can be a high pass filter with a frequency response amplitude of
  • M is greater than 2
  • the amplitude-frequency characteristic of the decomposition filter can be as shown in Fig. 5B.
  • Each decomposition filter processes the signal to obtain a signal that is a frequency band.
  • the frequency bands of the M filtered signals in the embodiments of the present invention are not strictly defined, and it is within the protection scope of the present invention that the M frequency bands can recover the original signals substantially without distortion.
  • the mutual non-overlapping in the embodiment of the present invention may be that M filters are orthogonal to each other.
  • the signal is filtered here, and analog filtering and digital filtering can be used.
  • the invention is not limited thereto.
  • the signal may be decomposed or synthesized by a decomposition or synthesis filter bank, or the signal may be decomposed or synthesized and filtered by digital filtering.
  • M filtering signals are respectively extracted by M times to obtain M decimation signals, and the number of samples of the decimation signal is reduced to 1/M of the number of samples of the signal to be processed. Assuming that the number of samples of the signal to be processed is N, after M-times extraction, the number of samples of the signal in each branch becomes N/M. For example, after 2 times of extraction, the number of samples of the signal in each branch becomes N/2.
  • the M frequency domain signals may be separately subjected to frequency domain processing to obtain M frequency domain processed signals.
  • the frequency domain processing here can be a frequency domain equalization process. It should be understood that each frequency domain signal may be subjected to frequency domain equalization processing in series. It is also possible to perform frequency domain equalization processing on the M-channel frequency domain signals in parallel.
  • the frequency domain processed signal can be parallel-serial converted, and the result of the parallel-serial conversion is output as an output signal.
  • the M channel signal may be processed serially, or the M channel signal may be processed in parallel.
  • the computational complexity can be further reduced while the computational complexity is reduced, and the rate of processing signals can be increased.
  • FIG. 6 is a schematic diagram of a process of processing a signal according to still another embodiment of the present invention.
  • the M decomposition signals are obtained by decomposing the input signals.
  • the frequency bands of the M decomposition signals do not overlap each other, and the input signal is a frequency domain signal having N sampling points.
  • the sum of the sampling points of the M decomposition signals is N, M is an integer greater than or equal to 2, and N is a positive integer.
  • the signals to be processed may be serial-to-parallel converted to obtain parallel signals to be processed, and the parallel signals to be processed are decomposed to obtain M decomposition signals.
  • IFFT inverse fast Fourier transform
  • each signal Before performing the inverse fast Fourier transform IFFT on the M decomposition signals, each signal can be decomposed, and the decomposed signal is subjected to frequency domain processing, and the obtained signal is used as a decomposition signal.
  • M-time interpolation is performed on each of the M time domain signals.
  • Interpolation can be used to interpolate between two samples of the time domain signal. For example, M times can add M-1 zero values between every two samples in the signal.
  • the number of sampling points of the input signal is N
  • the number of samples per decomposition signal is N/M
  • the number of samples per interpolation signal is N.
  • each interpolation signal is separately filtered to obtain M filtered signals.
  • Interpolate the signal After processing, the signal frequency band of each channel is expanded, and the interpolation signal includes a frequency domain image signal. In order to eliminate the image signal, each interpolation signal can be filtered to obtain a signal of a certain frequency band.
  • the filtering in the embodiment of the present invention may be digital filtering or analog filtering.
  • the M filtered signals may be serial-to-parallel converted to obtain a parallel signal, and the parallel signal is outputted.
  • the M branches can be serially processed, and the M branches can be processed in parallel.
  • Parallel processing can further improve computational parallelism while reducing computational complexity.
  • FIG. 7 is a schematic diagram of a process of processing a signal according to still another embodiment of the present invention.
  • the input signal is a time domain signal having N sampling points, and the frequency bands of the M filtered signals do not overlap each other, and M is greater than or An integer equal to 2, where N is a positive integer.
  • the signals to be processed may be serial-to-parallel converted to obtain parallel signals to be processed, and the parallel signals to be processed are used as input signals.
  • M replicated signals can be obtained by replicating parallel signals to be processed.
  • the number of samples per copy signal is the same as the number of samples of the signal to be processed, and is N.
  • M filtered signals y 0 (n), y 1 (n)...y M-1 (n) are obtained by the M-path first filtering process.
  • the M first filtered signals are respectively extracted by M times to obtain M extracted signals, and the number of samples of the extracted signals is reduced to 1/M of the number of samples to be processed. Assuming that the number of samples of the signal to be processed is N, after M-times extraction, the number of samples of each signal becomes N/M. For example, after 2 times of extraction, the number of samples of the signal in each branch becomes N/2.
  • frequency domain processing is performed on each of the M frequency domain signals, so that M frequency domain processed signals can be obtained.
  • the frequency domain processing here can be a frequency domain equalization process. It should be understood that each frequency domain signal may be subjected to frequency domain equalization processing in series. It is also possible to perform frequency domain equalization on the M-channel frequency domain signals in parallel. Reason.
  • the fast Fourier transform IFFT is performed on the M frequency domain processed signals to obtain M time domain signals.
  • M-time interpolation is performed on each of the M time domain signals.
  • each interpolation signal can be filtered to obtain a signal of a certain frequency band.
  • the synthesis filtering in the embodiment of the present invention may be digital filtering or analog filtering.
  • the M second filtered signals may be serial-to-parallel converted to obtain a parallel signal, and the parallel signal is used as an output signal.
  • the receiver of a single carrier system includes both an FFT and an IFFT, so that the amount of computation can be reduced by filtering and extracting the signal before the FFT and interpolating and filtering the signal after the IFFT. Further, when the signals of the M channels are processed in parallel, the degree of parallelism of the calculation can be further improved, and the processing of the data is accelerated.
  • FIGS. 1 through 7 A method of processing a signal according to an embodiment of the present invention is described in detail above with reference to FIGS. 1 through 7, and an apparatus for processing a signal according to an embodiment of the present invention will be described below with reference to FIGS. 8 through 13.
  • FIG. 8 is a block diagram of an apparatus for processing signals in accordance with one embodiment of the present invention.
  • the apparatus 10 of FIG. 8 includes a filtering unit 11, an extracting unit 12, a fast Fourier transform FFT unit 13, and a determining unit 14.
  • the filtering unit 11 includes M filters, and the filtering unit 11 includes M filters, and the M filters are respectively used to filter the input signals to obtain M filtered signals, and the input signals are There are N time-domain signals of sampling points, the frequency bands of M filtering signals do not overlap each other, M is an integer greater than or equal to 2, and N is a positive integer.
  • the decimating unit 12 includes M decimators, and the M decimators are connected with the M filters one by one.
  • the M decimators are respectively used to extract the M filtered signals obtained by the filtering unit to obtain M decimated signals, M
  • the sum of the number of sampling points of the extracted signals is N.
  • the fast Fourier transform FFT unit 13 includes M FFTs, and M FFTs are connected in one-to-one correspondence with M decimators.
  • the M FFTs are used to perform fast Fourier transform FFT on the M decimated signals obtained by the decimating unit, respectively, to obtain M FFTs. Frequency domain signal.
  • the determining unit 14 is configured to obtain an output signal according to the M frequency domain signals obtained by the FFT unit.
  • the input signal is M-channel filtered, and the filtered signal is extracted to obtain a decimation signal, so that the sum of the sampling points of the M decimation signals is the sampling point of the input signal, so that the M decimation signals can be respectively
  • the FFT is performed to avoid the problem of increasing the computational complexity caused by directly performing FFT on the input signal, and the computational complexity can be reduced.
  • a frequency band of each of the M filtered signals accounts for 1/M of a frequency band of the input signal.
  • the number of sampling points of each extracted signal is N/M.
  • the filtering unit is specifically configured to copy the input signal to obtain M replica signals of the input signal, and the M filters respectively filter the M replica signals in series or in parallel. M filtered signals are obtained.
  • a device for processing a signal according to an embodiment of the present invention may correspond to a corresponding device in the method of the embodiment of the present invention, and each unit/module in the device and the other operations and/or functions described above are respectively implemented to implement FIG.
  • the corresponding process of the method and the corresponding process in FIG. 4 are not repeated here for brevity.
  • FIG. 9 is a block diagram of an apparatus for processing signals in accordance with another embodiment of the present invention.
  • the apparatus 20 of FIG. 9 includes a decomposition unit 21, an inverse fast Fourier transform IFFT unit 22, an interpolation unit 23, a filtering unit 24, and a determination unit 25.
  • the decomposing unit 21 is configured to decompose the input signal to obtain M decomposed signals.
  • the frequency bands of the M decomposition signals do not overlap each other, and the input signal is a frequency domain signal having N sampling points.
  • the sum of the sampling points of the M decomposition signals is N, M is an integer greater than or equal to 2, and N is a positive integer.
  • the fast Fourier inverse transform IFFT unit 22 includes M IFFTs.
  • M decomposition signals are respectively input into M IFFTs, and M IFFTs are used to obtain M pieces for the decomposition unit.
  • the decomposed signals are respectively subjected to fast inverse Fourier transform IFFT to obtain M time domain signals.
  • the interpolation unit 23 includes M interpolators.
  • M interpolators are connected in one-to-one correspondence with M IFFTs, and M interpolators are used to interpolate M time-domain signals obtained by the IFFT unit to obtain M interpolated signals, and the number of sampling points of each interpolated signal is N.
  • Filtering unit 24 includes M filters. M filters are connected in one-to-one correspondence with M interpolators, and M filters are used to respectively filter M interpolation signals obtained by the interpolation unit to obtain M filtered signals.
  • the determining unit 25 is configured to determine an output signal according to the M filtered signals obtained by the filtering unit.
  • the input signal is decomposed, and the decomposed signal is separately subjected to IFFT, and then the time domain signal obtained by the IFFT is interpolated, and finally the interpolated signal is filtered, and an output signal is obtained.
  • the frequency band of each decomposition signal occupies 1/M of the frequency band of the input signal.
  • the number of sampling points of each decomposition signal is N/M.
  • the M IFFs are specifically configured to perform an inverse fast Fourier transform IFFT on the M decomposition signals in series or in parallel to obtain M time domain signals.
  • the apparatus for processing a signal may correspond to the apparatus in the method of the embodiment of the present invention, and each unit/module in the apparatus and the other operations and/or functions described above are respectively implemented to implement the method shown in FIG.
  • the corresponding process and the corresponding process in FIG. 6 are not described here for brevity.
  • FIG. 10 is a block diagram of an apparatus for processing signals in accordance with still another embodiment of the present invention.
  • the apparatus 30 of FIG. 10 includes a first filtering unit 31, a decimation unit 32, a fast Fourier transform FFT unit 33, and a frequency domain equalization unit 34.
  • the first filtering unit 31 includes M first filters, and M first filters are used to perform M-path first filtering on the input signal to decompose the input signal into M first filtered signals, and the input signal has N samples.
  • M is an integer greater than or equal to 2
  • N is a positive integer.
  • the extracting unit 32 includes M decimators, and the M decimators are connected in one-to-one correspondence with the M first filters. M decimators are used to respectively extract the M first filtered signals to obtain M decimated signals, and the sum of the sampling points of the M decimated signals is N.
  • the fast Fourier transform FFT unit 33 includes M FFTs.
  • M FFTs are connected in one-to-one correspondence with M decimators, and M FFTs are used to perform fast Fourier transform FFT on M decimated signals respectively to obtain M frequency domain signals.
  • the frequency domain equalization unit 34 includes M frequency domain equalizers, and M frequency domain equalizers are connected in one-to-one correspondence with M FFTs. M frequency domain equalizers are used to perform frequency domain processing on M frequency domain signals respectively to obtain M frequency domain processed signals.
  • the input signal is M-channel filtered, and the filtered signal is extracted to obtain a decimation signal, so that the sum of the sampling points of the M decimation signals is the sampling point of the input signal, so that the M decimation signals can be respectively
  • the FFT is performed to avoid the problem of increasing the computational complexity caused by directly performing FFT on the input signal, and the computational complexity can be reduced.
  • a frequency band of each of the M first filtered signals accounts for 1/M of a frequency band of the input signal.
  • the number of sampling points of each extracted signal is N/M.
  • the apparatus 30 may further include an inverse fast Fourier transform IFFT unit 35, an interpolation unit 36, a second filtering unit 37, and a determining unit 38.
  • the fast Fourier transform inverse IFFT unit 35 includes M IFFTs, and the M IFFTs are connected in one-to-one correspondence with the M frequency domain equalizers.
  • M IFFTs are used to perform inverse fast Fourier transform (IFFT) on M frequency domain processed signals to obtain M time domain signals.
  • the interpolation unit 36 includes M interpolators, and the M interpolators are connected in one-to-one correspondence with the M IFFTs.
  • the M interpolators are used to interpolate the M time domain signals respectively to obtain each M interpolated signals, and the number of sampling points of each interpolated signal is N.
  • the second filtering unit 37 includes M second filters, and the M second filters are connected in one-to-one correspondence with the M interpolators.
  • the M second filters are used for performing second filtering on the M interpolation signals to obtain M second filtered signals.
  • the determining unit 38 is configured to determine an output signal based on the M second filtered signals.
  • the apparatus for processing signals according to an embodiment of the present invention may correspond to the apparatus in the method of the embodiment of the present invention, and each unit/module in the apparatus and the other operations and/or functions described above are respectively implemented to implement the method shown in FIG.
  • the corresponding process and the corresponding process of FIG. 7 are not repeated here for brevity.
  • FIG 11 is a block diagram of an apparatus for processing signals in accordance with still another embodiment of the present invention.
  • the apparatus 40 of FIG. 11 includes a processor 41, a memory 42, and a bus system 43.
  • the processor 41 controls the operation of the device 40.
  • the memory 42 may include a read only memory and a random access memory, and
  • the processor 41 provides instructions and data.
  • a portion of the memory 42 may also include a Non-Volatile Random Access Memory (NVRAM).
  • NVRAM Non-Volatile Random Access Memory
  • the various components of the apparatus are coupled together by a bus system 43 which includes, in addition to the data bus, a power bus, a control bus, and a status signal bus. However, for clarity of description, various buses are labeled as the bus system 43 in the figure.
  • the method disclosed in the foregoing embodiment of the present invention may be applied to the processor 41 or implemented by the processor 41.
  • each step of the above method may be completed by an integrated logic circuit of hardware in the processor 41 or an instruction in a form of software.
  • the processor 41 can be a general purpose processor, a digital signal processor, an application specific integrated circuit, a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, and can implement or perform the embodiments of the present invention.
  • a general purpose processor can be a microprocessor or any conventional processor or the like.
  • the steps of the method disclosed in the embodiments of the present invention may be directly implemented as a hardware processor, or may be performed by a combination of hardware and software modules in the processor.
  • the software module can be located in a conventional storage medium such as random access memory, flash memory, read only memory, programmable read only memory or electrically erasable programmable memory, registers, and the like.
  • the storage medium is located in the memory 42, and the processor 41 reads the information in the memory 42 and performs the steps of the above method in combination with its hardware.
  • the processor 41 may filter the input signal by using M filters to obtain M filtered signals, where the input signal is a time domain signal with N sampling points, and the frequency bands of the M filtered signals do not overlap each other, and M is An integer greater than or equal to 2, where N is a positive integer.
  • M decimators are used to respectively extract M filtered signals to obtain M decimated signals, and the sum of the sampling points of the M decimated signals is N.
  • output signals are obtained according to M frequency domain signals.
  • the device 40 can implement the steps in the foregoing method embodiments, and is not described in detail to avoid repetition.
  • the frequency band of each of the M filtered signals occupies 1/M of the frequency band of the input signal.
  • the number of samples per decimated signal is N/M.
  • the processor 41 may copy the input signal to obtain M replica signals of the input signal, and separately filter the M replica signals in series or in parallel to obtain the M. Filtered signals.
  • a device for processing a signal according to an embodiment of the present invention may correspond to a corresponding device in the method of the embodiment of the present invention, and each unit/module in the device and the other operations and/or functions described above are respectively implemented to implement FIG.
  • the corresponding process of the method and the corresponding process in FIG. 4 are not repeated here for brevity.
  • FIG. 12 is a block diagram of an apparatus for processing signals in accordance with still another embodiment of the present invention.
  • the apparatus 50 of FIG. 12 includes a processor 51, a memory 52, and a bus system 53.
  • the processor 51 controls the operation of the device 50.
  • Memory 52 can include read only memory and random access memory and provides instructions and data to processor 51.
  • a portion of the memory 52 may also include a Non-Volatile Random Access Memory (NVRAM).
  • NVRAM Non-Volatile Random Access Memory
  • the various components of the apparatus are coupled together by a bus system 53, wherein the bus system 53 includes, in addition to the data bus, a power bus, a control bus, and a status signal bus. However, for clarity of description, various buses are labeled as the bus system 53 in the figure.
  • the method disclosed in the foregoing embodiments of the present invention may be applied to the processor 51 or implemented by the processor 51.
  • each step of the above method may be completed by an integrated logic circuit of hardware in the processor 51 or an instruction in a form of software.
  • the processor 51 can be a general purpose processor, a digital signal processor, an application specific integrated circuit, a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, which can be implemented or executed in an embodiment of the invention.
  • a general purpose processor can be a microprocessor or any conventional processor or the like.
  • the steps of the method disclosed in the embodiments of the present invention may be directly implemented as a hardware processor, or may be performed by a combination of hardware and software modules in the processor.
  • the software module can be located in a conventional storage medium such as random access memory, flash memory, read only memory, programmable read only memory or electrically erasable programmable memory, registers, and the like.
  • the storage medium is located in the memory 52, and the processor 51 reads the information in the memory 52 and performs the steps of the above method in combination with its hardware.
  • the processor 51 may decompose the input signal to obtain M decomposed signals, and the frequency bands of the M decomposed signals do not overlap each other, and the input signal is a frequency domain signal having N sampling points, and the number of sampling points of the M decomposed signals is And is N, M is an integer greater than or equal to 2, and N is a positive integer.
  • M time-domain signals are respectively interpolated to obtain M interpolation signals, and the number of sampling points of each interpolation signal is N.
  • the M interpolation signals are separately filtered to obtain M filtered signals, and the output signals are determined according to the M filtered signals.
  • the input signal is decomposed, and the decomposed signal is separately subjected to IFFT, and then the time domain signal obtained by the IFFT is interpolated, and finally the interpolated signal is filtered, and an output signal is obtained.
  • the apparatus 50 for processing signals according to an embodiment of the present invention may correspond to the apparatus in the method of the embodiment of the present invention, and the respective units/modules in the apparatus and the other operations and/or functions described above are respectively implemented in order to implement FIG.
  • the corresponding process of the method and the corresponding flow in FIG. 6 are not repeated here for brevity.
  • the frequency band of each of the resolved signals occupies 1/M of the frequency band of the input signal.
  • the number of samples per decomposition signal is N/M.
  • the processor 51 is configured to perform inverse fast Fourier transform (IFFT) on the M decomposition signals in series or in parallel to obtain M time domain signals.
  • IFFT inverse fast Fourier transform
  • FIG. 13 is a block diagram of an apparatus for processing signals in accordance with still another embodiment of the present invention.
  • the apparatus 60 of FIG. 6 includes a processor 61, a memory 62, and a bus system 63.
  • the processor 61 controls the operation of the device 60.
  • Memory 62 can include read only memory and random access memory and provides instructions and data to processor 61.
  • a portion of the memory 62 may also include a Non-Volatile Random Access Memory (NVRAM).
  • NVRAM Non-Volatile Random Access Memory
  • the various components of the apparatus are coupled together by a bus system 63, which in addition to the data bus includes a power bus, a control bus, and a status signal bus. However, for clarity of description, various buses are labeled as bus system 63 in the figure.
  • the method disclosed in the above embodiments of the present invention may be applied to the processor 61 or implemented by the processor 61.
  • each step of the above method may be completed by an integrated logic circuit of hardware in the processor 61 or an instruction in a form of software.
  • the processor 61 can be a general purpose processor, a digital signal processor, an application specific integrated circuit, a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, which can be implemented or executed in an embodiment of the invention.
  • a general purpose processor can be a microprocessor or any conventional processor or the like.
  • the steps of the method disclosed in the embodiments of the present invention may be directly implemented as a hardware processor, or may be performed by a combination of hardware and software modules in the processor.
  • the software module can be located in a conventional storage medium such as random access memory, flash memory, read only memory, programmable read only memory or electrically erasable programmable memory, registers, and the like.
  • the storage medium is located The memory 62, the processor 61 reads the information in the memory 62, and completes the steps of the above method in combination with its hardware.
  • the processor 61 may perform M-path first filtering on the input signal to decompose the input signal into M first filtered signals, where the input signal is a time domain signal with N sampling points, and M first filtered signals.
  • the frequency bands do not overlap each other, M is an integer greater than or equal to 2, and N is a positive integer.
  • the M first filtered signals are respectively extracted to obtain M decimation signals, and the sum of the sampling points of the M decimation signals is N.
  • Perform fast Fourier transform FFT on each of the M decimation signals to obtain M frequency domain signals.
  • the frequency domain processing is performed on each of the M frequency domain signals to obtain M frequency domain processed signals.
  • the input signal is M-channel filtered, and the filtered signal is extracted to obtain a decimation signal, so that the sum of the sampling points of the M decimation signals is the sampling point of the input signal, so that the M decimation signals can be respectively
  • the FFT is performed to avoid the problem of increasing the computational complexity caused by directly performing FFT on the input signal, and the computational complexity can be reduced.
  • a frequency band of each of the M first filtered signals accounts for 1/M of a frequency band of the input signal.
  • the number of sampling points of each extracted signal is N/M.
  • the processor 61 may further perform an inverse fast Fourier transform IFFT on the M frequency domain processed signals to obtain M time domain signals.
  • the M time domain signals are respectively interpolated to obtain every M interpolation signals, and the number of sampling points of each interpolation signal is N.
  • the device 60 can implement the steps in the foregoing method embodiments, and is not described in detail to avoid repetition.
  • the apparatus for processing signals according to an embodiment of the present invention may correspond to the apparatus in the method of the embodiment of the present invention, and each unit/module in the apparatus and the other operations and/or functions described above are respectively implemented to implement the method shown in FIG.
  • the corresponding process and the corresponding process of FIG. 7 are not repeated here for brevity.
  • the size of the sequence numbers of the above processes does not mean the order of execution, and the order of execution of each process should be determined by its function and internal logic, and should not be taken to the embodiments of the present invention.
  • the implementation process constitutes any limitation.
  • B corresponding to A means that B is associated with A, and B can be determined according to A.
  • determining B from A does not mean that B is only determined based on A, and that B can also be determined based on A and/or other information.
  • system and “network” are used interchangeably herein. It should be understood that the term “and/or” herein is merely an association relationship describing an associated object, indicating that there may be three relationships, for example, A and/or B, which may indicate that A exists separately, and A and B exist simultaneously. There are three cases of B alone. In addition, the character "/" in this article generally indicates that the contextual object is an "or" relationship.
  • the disclosed systems, devices, and methods may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in various embodiments of the present invention may be integrated in one processing unit
  • each unit may exist physically separately, or two or more units may be integrated into one unit.

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Abstract

本发明实施例提供了一种处理信号的方法和装置。该方法包括对输入信号进行M路滤波，得到M个滤波信号，并对M个滤波信号分别进行抽取，得到M个抽取信号，然后对M个抽取信号分别进行快速傅立叶变换FFT，得到M个频域信号，最后根据M个频域信号确定输出信号。本发明实施例通过对信号进行滤波和抽取，然后进行FFT，这样可以降低运算复杂度。

Description

处理信号的方法及装置 技术领域
本发明实施例涉及通信领域，并且更具体地，涉及处理信号的方法及装置。
背景技术
在信号处理系统中，人们广泛使用快速傅立叶变换(Fast Fourier Transform，FFT)和快速傅立叶逆变换(Inverse Fast Fourier Transform，IFFT)来实现对信号时域和频域的转换。例如，单载波系统中需要使用FFT和IFFT才能实现频域均衡。
FFT和IFFT的运算量与FFT和IFFT的样点数有关。例如，直接FFT变换的加法次数约为Nlog2N,乘法次数约为
Figure PCTCN2015078526-appb-000001
其中N为样点数。目前，常用的通信协议中FFT的样点数比较少。对于只有2048个样点的单载波频域均衡系统(single-carrier frequency domain equalization,SC-FDE)，FFT或IFFT实时计算压力较小。但是，随着宽带技术的应用，信号的样点数增加，FFT和IFFT的运算量增大，运算复杂度增大，为实时处理带来困难。对同一样点数N，如何快速实现FFT和IFFT，并减小其计算复杂度是宽带通信系统中亟待解决的问题。
发明内容
本发明实施例提供一种处理信号的方法及装置，能够降低运算复杂度。
第一方面，提供了一种处理信号的方法，包括：对输入信号进行M路滤波，以将所述输入信号分解成M个滤波信号，所述输入信号为具有N个采样点的时域信号，所述M个滤波信号的频段互不重叠，M为大于或等于2的整数，N为正整数；对所述M个滤波信号分别进行抽取，得到M个抽取信号，所述M个抽取信号的采样点数之和为N；对所述M个抽取信号分别进行快速傅立叶变换FFT，得到M个频域信号；根据所述M个频域信号确定输出信号。
结合第一方面，在第一方面的一种实现方式中，所述M个滤波信号中 的每个滤波信号的频段占所述输入信号的频段的1/M。
结合第一方面及其上述实现方式，在第一方面的另一种实现方式中，每个所述抽取信号的采样点数为N/M。
结合第一方面及其上述实现方式，在第一方面的另一种实现方式中，所述对输入信号进行M路滤波，以将所述输入信号分解成M个滤波信号，包括：对所述输入信号进行复制，得到所述输入信号的M个复制信号；串行或并行地对所述M个复制信号分别进行滤波，得到所述M个滤波信号。
第二方面，提供了一种处理信号的方法，包括：对输入信号进行分解，得到M个分解信号，所述M个分解信号的频段互不重叠，所述输入信号为具有N个采样点的频域信号，所述M个分解信号的采样点数之和为N，M为大于或等于2的整数，N为正整数；对所述M个分解信号分别进行快速傅立叶逆变换IFFT，得到M个时域信号；对M个时域信号分别进行插值，得到M个插值信号，所述每个插值信号的采样点数为N；对所述M个插值信号分别进行滤波，得到M个滤波信号；根据所述M个滤波信号确定输出信号。
结合第二方面，在第二方面的一种实现方式中，每个所述分解信号的频段占所述输入信号的频段的1/M。
结合第二方面及其上述实现方式，在第二方面的另一种实现方式中，每个所述分解信号的采样点数为N/M。
结合第二方面及其上述实现方式，在第二方面的另一种实现方式中，所述对所述M个分解信号分别进行快速傅立叶逆变换IFFT，得到M个时域信号包括：串行或并行地对所述M个分解信号分别进行快速傅立叶逆变换IFFT，得到M个时域信号。
第三方面，提供了一种处理信号的方法，包括：对输入信号进行M路第一滤波，以将所述输入信号分解成M个第一滤波信号，所述输入信号为具有N个采样点的时域信号，所述M个第一滤波信号的频段互不重叠，M为大于或等于2的整数，N为正整数；对所述M个第一滤波信号分别进行抽取，得到M个抽取信号，所述M个抽取信号采样点数之和为N；对所述M个抽取信号分别进行快速傅立叶变换FFT，得到M个频域信号；对所述M个频域信号分别进行频域处理，得到M个频域处理信号。
结合第三方面，在第三方面的一种实现方式中，所述M个第一滤波信 号中的每个滤波信号的频段占所述输入信号的频段的1/M。
结合第三方面及其上述实现方式，在第三方面的另一种实现方式中，每个所述抽取信号的采样点数为N/M。
结合第三方面及其上述实现方式，在第三方面的另一种实现方式中，所述方法还包括：对所述M个频域处理信号分别进行快速傅立叶逆变换IFFT，得到M个时域信号；对所述M个时域信号分别进行插值，得到每M个插值信号，每个所述插值信号的采样点数为N；对所述M个插值信号分别进行第二滤波，得到M个第二滤波信号；根据所述M个第二滤波信号确定输出信号。
第四方面，提供了一种处理信号的装置，包括：滤波单元，所述滤波单元包括M个滤波器，所述M个滤波器分别用于对输入信号进行滤波，以得到M个滤波信号，所述输入信号为具有N个采样点的时域信号，所述M个滤波信号的频段互不重叠，M为大于或等于2的整数，N为正整数；抽取单元，所述抽取单元包括M个抽取器，所述M个抽取器与所述M个滤波器一一对应连接，所述M个抽取器分别用于对所述滤波单元得到的所述M个滤波信号分别进行抽取，得到M个抽取信号，所述M个抽取信号的采样点数之和为N；快速傅立叶变换FFT单元，所述FFT单元包括M个FFT器，所述M个FFT器与所述M个抽取器一一对应连接，所述M个FFT器用于对所述抽取单元得到的所述M个抽取信号分别进行快速傅立叶变换FFT，得到M个频域信号；确定单元，用于根据所述FFT单元得到的所述M个频域信号得到输出信号。
结合第四方面，在第四方面的一种实现方式中，所述M个滤波信号中的每个滤波信号的频段占所述输入信号的频段的1/M。
结合第四方面及其上述实现方式，在第四方面的另一种实现方式中，每个所述抽取信号的采样点数为N/M。
结合第四方面及其上述实现方式，在第四方面的另一种实现方式中，所述滤波单元具体用于对所述输入信号进行复制，得到所述输入信号的M个复制信号，所述M个滤波器串行或并行地对所述M个复制信号分别进行滤波，得到所述M个滤波信号。
第五方面，提供了一种处理信号的装置，包括：分解单元，用于对输入信号进行分解，得到M个分解信号，所述M个分解信号的频段互不重叠， 所述输入信号为具有N个采样点的频域信号，所述M个分解信号的采样点数之和为N，M为大于或等于2的整数，N为正整数；快速傅立叶逆变换IFFT单元，所述IFFT单元包括M个IFFT器，M个分解信号一一对应分别进行输入M个IFFT器，所述M个IFFT器用于对所述分解单元得到的所述M个分解信号分别进行快速傅立叶逆变换IFFT，得到M个时域信号；插值单元，所述插值单元包括M个插值器，所述M个插值器与所述M个IFFT器一一对应连接，所述M个插值器用于对所述IFFT单元得到的所述M个时域信号分别进行插值，得到M个插值信号，每个所述插值信号的采样点数为N；滤波单元，所述滤波单元包括M个滤波器，所述M个滤波器与所述M个插值器一一对应连接，所述M个滤波器用于对所述插值单元得到的所述M个插值信号分别进行滤波，得到M个滤波信号；确定单元，用于根据所述滤波单元得到的所述M个滤波信号确定输出信号。
结合第五方面，在第五方面的一种实现方式中，每个所述分解信号的频段占所述输入信号的频段的1/M。
结合第五方面及其上述实现方式，在第五方面的另一种实现方式中，每个所述分解信号的采样点数为N/M。
结合第五方面及其上述实现方式，在第五方面的另一种实现方式中，M个IFFT器具体用于串行或并行地对所述M个分解信号分别进行快速傅立叶逆变换IFFT，得到M个时域信号。
第六方面，提供了一种处理信号的装置，包括：第一滤波单元，所述第一滤波单元包括M个第一滤波器，所述M个第一滤波器用于对输入信号进行M路第一滤波，以将所述输入信号分解成M个第一滤波信号，所述输入信号为具有N个采样点的时域信号，所述M个第一滤波信号的频段互不重叠，M为大于或等于2的整数，N为正整数；抽取单元，所述抽取单元包括M个抽取器，所述M个抽取器与所述M个第一滤波器一一对应连接，所述M个抽取器用于对所述M个第一滤波信号分别进行抽取，得到M个抽取信号，所述M个抽取信号采样点数之和为N；快速傅立叶变换FFT单元，所述FFT单元包括M个FFT器，所述M个FFT与所述M个抽取器一一对应连接，所述M个FFT器用于对所述M个抽取信号分别进行快速傅立叶变换FFT，得到M个频域信号；频域均衡单元，所述频域均衡单元包括M个频域均衡器，所述M个频域均衡器与所述M个FFT一一对应连接，所述M 个频域均衡器用于对所述M个频域信号分别进行频域处理，得到M个频域处理信号。
结合第六方面，在第六方面的一种实现方式中，所述M个第一滤波信号中的每个滤波信号的频段占所述输入信号的频段的1/M。
结合第六方面及其上述实现方式，在第六方面的另一种实现方式中，每个所述抽取信号的采样点数为N/M。
结合第六方面及其上述实现方式，在第六方面的另一种实现方式中，所述装置还包括：快速傅立叶逆变换IFFT单元，所述IFFT单元包括M个IFFT器，所述M个IFFT器与所述M个频域均衡器一一对应连接，所述M个IFFT用于对所述M个频域处理信号分别进行快速傅立叶逆变换IFFT，得到M个时域信号；插值单元，所述插值单元包括M个插值器，所述M个插值器与所述M个IFFT器一一对应连接，所述M个插值器用于对所述M个时域信号分别进行插值，得到每M个插值信号，所述每个插值信号的采样点数为N；第二滤波单元，所述第二滤波单元包括M个第二滤波器，所述M个第二滤波器与所述M个插值器一一对应连接，所述M个第二滤波器用于对所述M个插值信号分别进行第二滤波，得到M个第二滤波信号；确定单元，用于根据所述M个第二滤波信号确定输出信号。
本发明实施例对输入信号进行M路滤波，并对滤波后的滤波信号进行抽取得到抽取信号，使得M个抽取信号的采样点数之和为输入信号的采样点数，这样可以对M个抽取信号分别进行FFT，避免对输入信号直接进行FFT带来的运算复杂度递增的问题，能够降低运算复杂度。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对本发明实施例中所需要使用的附图作简单地介绍，显而易见地，下面所描述的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明一个实施例的处理信号的方法的示意性流程图。
图2是本发明另一实施例的处理信号的方法的示意性流程图。
图3是本发明再一实施例的处理信号的方法的示意性流程图。
图4是本发明一个实施例的处理信号的过程的示意图。
图5A和5B是本发明一个实施例的分解滤波器的两个不同的幅频特性图。
图6是本发明另一实施例的处理信号的过程的示意图。
图7是本发明再一实施例的处理信号的过程的示意图。
图8是本发明一个实施例的处理信号的装置的框图。
图9是本发明另一实施例的处理信号的装置的框图。
图10是本发明再一实施例的处理信号的装置的框图。
图11是本发明一个实施例的处理信号的装置的框图。
图12是本发明另一实施例的处理信号的装置的框图。
图13是本发明再一实施例的处理信号的装置的框图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明的一部分实施例，而不是全部实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动的前提下所获得的所有其他实施例，都应属于本发明保护的范围。
应理解，本发明实施例对具体应用场景不做限定。例如，本发明实施例的技术方案可以应用于各种通信系统，例如：单载波频域均衡系统(single-carrier frequency domain equalization,SC-FDE)等。本发明实施例还可以应用在图像处理中。凡是涉及利用本发明的方法来减少FFT或IFFT的运算量或提高计算并行度的方法都在本发明的保护范围之内。
图1是本发明一个实施例的处理信号的方法的示意性流程图。
101，对输入信号进行M路滤波，以将输入信号分解成M个滤波信号，输入信号为具有N个采样点的时域信号，M个滤波信号的频段互不重叠，M为大于或等于2的整数，N为正整数。
102，对M个滤波信号分别进行抽取，得到M个抽取信号，M个抽取信号的采样点数之和为N。
103，对M个抽取信号分别进行快速傅立叶变换FFT，得到M个频域信号。
104，根据M个频域信号确定输出信号。
本发明实施例对输入信号进行M路滤波，并对滤波后的滤波信号进行 抽取得到抽取信号，使得M个抽取信号的采样点数之和为输入信号的采样点数，这样可以对M个抽取信号分别进行FFT，避免对输入信号直接进行FFT带来的运算复杂度递增的问题，能够降低运算复杂度。
目前，广泛使用直接FFT和IFFT来进行FFT和IFFT的计算。FFT和IFFT的运算量与进行FFT和IFFT运算的样点数有关。例如，样点数为N的信号直接进行FFT变换的加法次数约为Nlog2N,乘法次数约为
Figure PCTCN2015078526-appb-000002
常用的通信协议中FFT的样点数比较少，FFT和IFFT的运算量也小。但是，随着系统带宽的增减，系统中传输信号的样点数也会激增。例如：在某宽带系统，例如，SC-FDE系统中，带宽从20M增加至500M时，一个数据信号进行IFFT运算的样点数从现有的2048激增为2048*(500/20)＝51200，一般地，样点数为2的整数次幂，所以，实际上要用65536样点来实现。随着样点数增加，FFT和IFFT运算的加法次数增多，乘法次数增多，即运算复杂度增加，计算开销大。
假设本发明实施例中输入信号的采样点数为N，N为正整数。优选地，N＝2m，m为正整数。
应理解，本发明实施例对每个抽取信号的采样点数不做限定。只要满足通过抽取之后的信号能够通过IFFT恢复出原始信号，都在本发明的保护范围之内。
可选地，作为本发明的一个实施例，当对输入信号的样点数在M路上平均分配时，每个抽取信号的采样点数为N/M。优选地，N/M＝2p，p为正整数。应理解，信号的样点数不为2的指数次幂时，在进行FFT之前可以将信号补零，使得信号的样点数为2的指数次幂。
应理解，本发明实施例对每个滤波信号的频段的长度不做限定。只要输入信号的频段可以分解成的M个滤波信号的频段，这样的发明都在本发明的保护范围之内。
可选地，作为本发明的一个实施例，当对输入信号的频段在M路上进行平均分配时，M个滤波信号中的每个滤波信号的频段占输入信号的频段的1/M。
本发明实施例中的滤波可以为数字滤波，也可以为模拟滤波。即，可以通过数字滤波的方式实现对输入信号的滤波处理，也可以通过多个滤波器实现对输入信号的滤波处理，本发明实施例对此不做限定。例如，对分解滤波 阵列的M路进行分解滤波处理可以通过程序或分解滤波器组来实现，对不同支路的信号进行不同幅值的滤波处理，以在某一路上保留某一频段的信号，滤除其余频段的信号。这里可以根据滤波器的幅频特性对信号进行滤波处理。
本发明实施例中将样点数为N的输入信号输入分解滤波阵列，每路的输入信号与原输入信号相同，样点数都为N。这里可以通过对输入信号进行复制得到M个复制信号，然后对每路的复制信号分别进行处理。应理解，也可以对不同支路通过总线相连接，每路都得到与原输入信号相同的信号。分解滤波阵列可以包括M个滤波器，各个分解滤波器具有各自的幅频特性。
长点数的IFFT或FFT计算复杂度高，计算开销大。本发明实施例如果将信号直接进行抽取得到M段信号，并对M段信号分别进行FFT，这样可以降低运算复杂度，但是这样很可能会发生频谱混叠现象，导致对端不能从接收的信号恢复出原始信号。本发明实施例给出了如何在保证频谱不混叠，并可以恢复出原始信号的同时，尽可能降低运算复杂度，并在一些应用场景中进一步地，提高计算并行度。
具体地，可以对分解滤波阵列的M路上的输入信号进行滤波处理，得到每路的滤波信号，M为大于或等于2的整数。接着，对每路的滤波信号进行抽取，得到每路的抽取信号，M个抽取信号的采样点数之和为N。然后，对每路的抽取信号进行快速傅立叶逆变换FFT，得到每路的频域信号。这里，对信号进行滤波处理，从频率上将信号分为M个不同频段的信号，M条不同支路分别处理M段信号中的一段。
应理解，本发明实施例中的M个滤波信号的频段互不重叠不做严格限定，只要M个频段能够基本不失真地恢复出原始信号的都在本发明的保护范围之内。例如，本发明实施例中的互不重叠可以为M个滤波器相互正交。
可选地，作为本发明的一个实施例，可以对每路的滤波信号进行M倍抽取，得到每路的抽取信号，每路的抽取信号的样点数为N/M。M倍抽取可以依次从M个样点中抽取一个样点作为抽取信号中的新样点。这样可以将每路信号的样点数变为原始信号样点数的1/M，即将长序列的信号可以拆分成多个短序列的信号，以对短序列信号进行FFT。
在本发明的一个实施例中，可以对每路的抽取信号进行快速傅立叶变换FFT，得到每路的频域信号。这样通过将长序列信号的FFT分为若干个短序 列信号的FFT，可以降低运算复杂度。例如，信号的传输带宽为40M，可以将样点数为4096的信号分解为2个样点数为2048的信号。如果对4096样点进行一路FFT变换，那么FFT运算时，加法次数为Nlog2N＝4096*12＝49152。乘法次数为
Figure PCTCN2015078526-appb-000003
当采用两路分别处理信号时，FFT运算的加法次数为Nlog2(N/2)＝45056，乘法次数为
Figure PCTCN2015078526-appb-000004
另外，如果分解滤波器使用的是23点的分解滤波器。那么，每个23点的分解滤波器对信号进行分解滤波处理时，执行加法运算次数为22，乘法运算次数为23。所以，FFT和分解滤波处理总共的加法次数总数为45056+22*2，仍小于采用一路IFFT对4096样点进行处理的加法次数49152。同理，FFT和分解滤波处理两步的乘法次数总数为22528+23*2，仍小于采用一路IFFT对4096样点进行处理的乘法次数24576。
可选地，作为本发明的一个实施例，本发明实施例可以在对对输入信号进行M路滤波之前对待处理的信号进行串并转换，得到并行的待处理信号，然后将并行的待处理信号作为输入信号。这里，待处理的信号可以接收的信号，也可以为生成的信号。
可选地，作为本发明的一个实施例，在FFT得到频域信号之后，还可以对M路的频域信号进行频域处理。优选地，对M路的频域信号进行频域均衡处理，得到M路的频域均衡信号。然后，对该频域均衡信号进行并串转换，得到与频域均衡信号对应的串行信号，并将该串行信号确定为输出信号。
可选地，作为本发明的一个实施例，在FFT得到频域信号之后，还可以直接对M路频域信号进行并串转换，得到与M路频域信号对应的串行信号，并将该串行信号确定为输出信号。
本发明一个实施例中，可以对M路上的输入信号分别进行处理。这里，分别进行处理包括对M路的所有信号进行并行处理或串行处理。
可选地，作为本发明的一个实施例，对输入信号进行M路滤波，以将输入信号分解成M个滤波信号，包括：对输入信号进行复制，得到输入信号的M个复制信号，串行地对M个复制信号分别进行滤波，得到M个滤波信号。
对M路所有信号进行串行处理，可以用一个处理器对所有的信号进行处理。例如，用一个处理器对M路的所有信号进行滤波处理、抽取和FFT。即，用一个处理器对每路信号分别通过分解滤波、抽取、FFT。
可选地，作为本发明的一个实施例，对输入信号进行M路滤波，以将输入信号分解成M个滤波信号，包括对输入信号进行复制，得到输入信号的M个复制信号，并行地对M个复制信号分别进行滤波，得到M个滤波信号。
对M路所有信号进行并行处理，可以通过不同的处理器处理不同路的信号。例如，分别用M个处理器中的一个处理器对M路的每路信号进行滤波处理、抽取和FFT。即，每路用一个处理器处理，这样，可以用M个处理器对M条支路的信号进行并行处理。
本发明实施例对分别对M路的信号进行处理的具体顺序不做限定。分别对M条支路上同一种信号进行处理可以为分别依次对M条支路上同一种信号进行串行处理，也可以并行地对M条支路上的信号进行并行处理。例如，当处理平台计算能力有限时，可以为分别依次对M条支路信号进行串行处理，这样可以利用本发明的实现方式降低计算复杂度。当处理平台有足够计算能力时，可以对M条支路信号进行并行处理，这样除了能够降低计算复杂度，还可以提高计算并行度，可以大幅度的加速处理速度。特别地，将本发明实施例的并行处理应用到图像处理单元(Graphics Processing Unit，GPU)中实现单指令多线程(Single Instruction Multi-thread，SIMT)对图像进行处理，或者，将本发明实施例的并行处理应用到专用集成电路(Application-Specific Integrated Circuit，ASIC)或现场可编程门阵列(Field-Programmable Gate Array，FPGA)中，可以很大程度上提高处理速度。例如，使用FPGA进行65536点的FFT，由于将65536点的FFT转成32个2048点的FFT后，可以采用32个FFT分支并行处理，从而能够将计算速度提高32倍，缩短计算时间。
当用多个处理器对多路信号进行并行处理时，可以对M路信号同时进行频域处理，也可以对每路信号分别进行频域处理。当用一个处理器分别对多路信号进行处理时，可以对一路信号进行频域处理，也可以在得到多路信号的频域信号之后，对多路信号进行频域处理。本发明实施例对此不做限定。
同理，当用多个处理器对多路信号进行并行处理时，可以对M路信号同时进行并串转换，也可以对每路信号分别进行并串转换。当用一个处理器分别对多路信号进行处理时，可以对一路信号进行并串转换，也可以在得到多路信号的频域信号之后，对多路信号进行并串转换。本发明实施例对此不 做限定。
图2是本发明另一实施例的处理信号的方法的示意性流程图。
201，对输入信号进行分解，得到M个分解信号，M个分解信号的频段互不重叠，输入信号为具有N个采样点的频域信号，M个分解信号的采样点数之和为N，M为大于或等于2的整数，N为正整数。
202，对M个分解信号分别进行快速傅立叶逆变换IFFT，得到M个时域信号。
203，对M个时域信号分别进行插值，得到M个插值信号，每个插值信号的采样点数为N。
204，对M个插值信号分别进行滤波，得到M个滤波信号。
205，根据M个滤波信号确定输出信号。
本发明实施例对输入信号进行分解，并对分解后的分解信号分别进行IFFT，然后对IFFT得到的时域信号进行插值，最后对插值后的信号进行滤波，并得到输出信号。这样通过对M个分解信号分别进行IFFT，避免对输入信号直接进行IFFT带来的运算复杂度递增的问题，能够降低运算复杂度。
目前，广泛使用直接FFT和IFFT来进行FFT和IFFT的计算。FFT和IFFT的运算量与进行FFT和IFFT运算的样点数有关。随着样点数增加，FFT和IFFT运算的加法次数增多，乘法次数增多，即运算复杂度增加，计算开销大。本发明实施例给出了如何在IFFT运算的样点数增加时，尽可能降低运算复杂度。
应理解，本发明实施例对每个分解信号的采样点数不做限定。只要满足通过分解之后的分解信号能够通过IFFT恢复出原始信号，都在本发明的保护范围之内。M个分解信号的采样点数之和为N。
可选地，作为本发明的一个实施例，当对输入信号的样点数经过分解在M路上平均分配时，每个分解信号的采样点数为N/M。优选地，N/M＝2p，p为正整数。应理解，信号的采样点数不为2的指数次幂时，在进行IFFT滤波之前可以将信号补零，使得信号的样点数为2的指数次幂。
应理解，本发明实施例对每个分解信号的频段的长度不做限定。只要输入信号的频段可以分解成的M个分解信号的频段，这样的发明都在本发明的保护范围之内。
可选地，作为本发明的一个实施例，当对输入信号的频段在M路上进 行平均分配时，M个分解信号中的每个分解信号的频段占输入信号的频段的1/M。
对信号进行插值处理后，每路的信号时域扩展，频域压缩，发生畸变。为了消除畸变，可以对每路的插值信号进行滤波处理，消除镜像以得到某一频段的信号，随后进行相加，恢复出无失真的基带信号。本发明实施例中的滤波可以为数字滤波，也可以为模拟滤波。即，可以通过数字滤波的方式实现对信号的滤波处理，也可以通过多个滤波器实现对信号的滤波处理，本发明实施例对此不做限定。例如，对滤波阵列的M路上的每路信号进行滤波处理还可以通过程序或滤波器组来实现，对不同路的序列信号进行不同幅值的滤波处理，以保留某一频段的信号，滤除其余频段的信号。这里可以根据合成滤波器的幅频特性对信号进行滤波处理。IFFT信号通过插值和合成滤波处理后，可以恢复出原始信号，并同时降低运算复杂度。
在本发明实施例中，可以对合成滤波阵列的M路的每路信号进行快速傅立叶逆变换IFFT，得到每路的IFFT信号。假设每路信号的样点数为N/M，N/M＝2p，p为正整数。那么，每路的插值信号的样点数为N，N＝2m，m为正整数。然后对每路的IFFT信号进行M倍插值，得到插值信号。插值后的插值信号的样点数N。插值可以为将原信号两个样点之间补入插值。例如，M倍可以将信号中每两个样点之间补入M-1个零值。接着，对插值信号进行滤波处理，得到每路的合成滤波信号。滤波处理后，每路的滤波信号为不同频段的信号。这样，可以通过对多路短序列信号进行IFFT，然后将多路短序列信号通过插值和滤波，使得信号可以恢复到原始信号。将一个长序列信号的IFFT分解为M路短序列信号的IFFT，这样可以降低运算复杂度。
可选地，作为本发明的一个实施例，可以对一路滤波信号进行并串转换，得到一路滤波信号对应的串行信号。
本发明的一个实施例可以对M路的插值信号进行滤波后，将M个滤波信号合成到一个总的频段上得到输出信号。这里，输出信号的样点数为N。合成可以为将M路中每路信号的第Q个点累加得到合成滤波信号的第Q个点，Q为正整数。
应理解，本发明实施例中的信号可以为视频、音频、数据、图像等。本发明对此不做限定。
应理解，本发明实施例中的M个滤波信号的频段互不重叠不做严格限 定，只要M个频段能够基本不失真地恢复出原始信号的都在本发明的保护范围之内。例如，本发明实施例中的互不重叠可以为M个滤波器相互正交。
本发明一个实施例中，可以对M路的分解信号分别进行处理。这里，分别进行处理包括对M路的所有信号进行并行处理或串行处理。
可选地，作为本发明的一个实施例，对M个分解信号分别进行快速傅立叶逆变换IFFT，得到M个时域信号包括：串行地对M个分解信号分别进行快速傅立叶逆变换IFFT，得到M个时域信号。
对M路所有信号进行串行处理，可以用一个处理器对所有的信号进行处理。例如，用一个处理器对M路的所有信号进行IFFT、插值和滤波处理。即，用一个处理器对M条支路的每路信号分别通过IFFT、插值、滤波。
可选地，作为本发明的一个实施例，对M个分解信号分别进行快速傅立叶逆变换IFFT，得到M个时域信号包括：并行地对M个分解信号分别进行快速傅立叶逆变换IFFT，得到M个时域信号。这样通过将长序列信号分为若干个短序列信号进行FFT，可以降低运算复杂度。
对M路所有信号进行并行处理，可以用不同的通处理器处理不同路的信号。例如，分别用M个处理器中的一个处理器对M路的每路信号进行IFFT、插值、滤波。即，每路用一个处理器处理，这样，可以用M个处理器对M条支路的信号进行并行处理，可以在降低运算复杂度的同时，提高计算并行度。
本发明实施例对分别对M路的信号进行处理的具体顺序不做限定。分别对M路上同一种信号进行处理可以为分别依次对M路上同一种信号进行串行处理，也可以并行地对M路上的信号进行并行处理。例如，当处理平台计算能力有限时，可以为分别依次对M路信号进行串行处理，这样可以降低计算复杂度。当处理平台有足够计算能力时，可以对M条支路信号进行并行处理，这样能够在降低计算复杂度的同时，提高计算并行度，可以大幅度的加速处理速度。特别地，将本发明实施例的并行处理应用到图像处理单元(Graphics Processing Unit，GPU)中实现单指令多线程(Single Instruction Multi-thread，SIMT)对图像进行处理，或者，将本发明实施例的并行处理应用到专用集成电路(Application-Specific Integrated Circuit，ASIC)或现场可编程门阵列(Field-Programmable Gate Array，FPGA)中，可以很大程度上提高处理速度。
当用多个处理器对多路信号进行并行处理时，可以对M路信号同时进行频域处理，也可以对每路信号分别进行频域处理。当用一个处理器分别对多路信号进行处理时，可以对一路信号进行频域处理，也可以在得到多路信号的频域信号之后，对多路信号进行频域处理。本发明实施例对此不做限定。
同理，当用多个处理器对多路信号进行并行处理时，可以对M路信号同时进行并串转换，也可以对每路信号分别进行并串转换。当用一个处理器分别对多路信号进行处理时，可以对一路信号进行并串转换，也可以在得到多路信号的频域信号之后，对多路信号进行并串转换。本发明实施例对此不做限定。
本发明实施例中，一般地，FFT与IFFT成对出现。这里，将图1中与FFT对应的对信号的滤波称为第一滤波，图2中与IFFT对应的对信号的滤波称为第二滤波。两次滤波应满足一定的约束条件：例如，
Figure PCTCN2015078526-appb-000005
其中，M为支路的数目，Hk(z)为第一滤波的频率特性，Fk(z)为第二滤波的频率特性，T(z)具有纯延迟特性。
图3是本发明再一实施例的处理信号的方法的示意性流程图。图3的方法可以由单载波系统的接收机执行。
301，对输入信号进行M路第一滤波，以将输入信号分解成M个第一滤波信号，输入信号为具有N个采样点的时域信号，M个第一滤波信号的频段互不重叠，M为大于或等于2的整数，N为正整数。
302，对M个第一滤波信号分别进行抽取，得到M个抽取信号，M个抽取信号采样点数之和为N。
303，对M个抽取信号分别进行快速傅立叶变换FFT，得到M个频域信号。
304，对M个频域信号分别进行频域处理，得到M个频域处理信号。
本发明实施例对输入信号进行M路滤波，并对滤波后的滤波信号进行抽取得到抽取信号，使得M个抽取信号的采样点数之和为输入信号的采样点数，这样可以对M个抽取信号分别进行FFT，避免对输入信号直接进行FFT带来的运算复杂度递增的问题，能够降低运算复杂度。
假设本发明实施例中输入信号的采样点数为N，N为正整数。优选地， N＝2m，m为正整数。
应理解，本发明实施例对每个抽取信号的采样点数不做限定。只要满足通过抽取之后的信号能够通过IFFT恢复出原始信号，都在本发明的保护范围之内。
可选地，作为本发明的一个实施例，当对输入信号的样点数在M路上平均分配时，每个抽取信号的采样点数为N/M。优选地，N/M＝2p，p为正整数。应理解，信号的样点数不为2的指数次幂时，在进行FFT之前可以将信号补零，使得信号的样点数为2的指数次幂。
应理解，本发明实施例对每个第一滤波信号的频段的长度不做限定。只要输入信号的频段可以分解成的M个第一滤波信号的频段，这样的发明都在本发明的保护范围之内。
可选地，作为本发明的一个实施例，当对输入信号的频段在M路上进行平均分配时，M个第一滤波信号中的每个第一滤波信号的频段占输入信号的频段的1/M。
可选地，作为本发明的一个实施例，在FFT得到频域信号之后，还可以对M路的频域信号进行频域处理，得到M个频域处理信号。优选地，对M路的频域信号进行频域均衡处理，得到M个频域均衡信号。
本发明实施例中，可以将M个频域均衡信号作为IFFT的输入信号，在M路上对每个频域均衡信号进行IFFT。
可选地，作为本发明的一个实施例，可以在得到M个频域处理信号之后，对M个频域处理信号分别进行快速傅立叶逆变换IFFT，得到M个时域信号。接着，对M个时域信号分别进行插值，得到每M个插值信号，每个插值信号的采样点数为N。然后，对M个插值信号分别进行第二滤波，得到M个第二滤波信号。最后，根据M个第二滤波信号确定输出信号。
对信号进行插值处理后，每路的信号时域扩展，频域压缩，发生畸变。为了消除畸变，可以对每路的插值信号进行滤波处理，消除镜像以得到某一频段的信号，随后进行相加，恢复出无失真的基带信号。本发明实施例中的滤波可以为数字滤波，也可以为模拟滤波。即，可以通过数字滤波的方式实现对信号的滤波处理，也可以通过多个滤波器实现对信号的滤波处理，本发明实施例对此不做限定。例如，对滤波阵列的M路上的每路信号进行滤波处理还可以通过程序或滤波器组来实现，对不同路的序列信号进行不同幅值 的滤波处理，以保留某一频段的信号，滤除其余频段的信号。这里可以根据合成滤波器的幅频特性对信号进行滤波处理。IFFT信号通过插值和合成滤波处理后，可以恢复出原始信号，并同时降低运算复杂度。
本发明一个实施例中，可以对M路上的输入信号分别进行处理。这里，分别进行处理包括对M路的所有信号进行并行处理或串行处理。
可选地，作为本发明的一个实施例，对输入信号进行M路滤波，以将输入信号分解成M个滤波信号，包括：对输入信号进行复制，得到输入信号的M个复制信号，串行地对M个复制信号分别进行滤波，得到M个滤波信号。
对M路所有信号进行串行处理，可以用一个处理器对所有的信号进行处理。例如，用一个处理器对M路的所有信号进行第一滤波、抽取、FFT、频域处理、IFFT、插值和第二滤波。
可选地，作为本发明的一个实施例，对输入信号进行M路滤波，以将输入信号分解成M个滤波信号，包括：对输入信号进行复制，得到输入信号的M个复制信号，并行地对M个复制信号分别进行滤波，得到M个滤波信号。
对M路所有信号进行并行处理，可以通过不同的处理器处理不同路的信号。例如，分别用M个处理器中的一个处理器对M路的每路信号进行第一滤波、抽取、FFT、频域处理、IFFT、插值和第二滤波。
本发明实施例中，一般地，FFT与IFFT成对出现。这里，将FFT对应的对信号的滤波称为第一滤波，与IFFT对应的对信号的滤波称为第二滤波。两次滤波应满足一定的约束条件：例如，例如，
Figure PCTCN2015078526-appb-000006
其中，M为支路的数目，Hk(z)为第一滤波的频率特性，Fk(z)为第二滤波的频率特性，T(z)具有纯延迟特性。
下面结合具体例子更加详细地描述本发明的实施例。
下面将结合图4至图7，以及具体例子详细说明本发明的处理信号的方法。应注意，这些例子只是为了帮助本领域技术人员更好地理解本发明实施例，而非限制本发明实施例的范围。
图4是本发明一个实施例的处理信号的过程的示意图。这里仅以M条不同的支路为例进行示例性说明，M为大于或等于2的整数。
401，对输入信号进行M路滤波。
对输入信号进行M路滤波，以将输入信号分解成M个滤波信号，输入信号为具有N个采样点的时域信号，M个滤波信号的频段互不重叠，M为大于或等于2的整数，N为正整数。
在对输入信号进行M路滤波之前，还可以对待处理的信号进行串并转换，得到并行的待处理信号，将该并行的待处理信号作为输入信号。
应理解，可以通过对并行的待处理信号进行复制，得到M个复制信号。每个复制信号的采样点数与待处理信号的采样点数相同，都为N。
假定输入信号为x(n)，通过M路滤波处理后得到M个滤波信号y0(n)、y1(n)…yM-1(n)。
图5A和5B是本发明一个实施例的分解滤波器的两个不同的幅频特性图。M＝2时，分解滤波器的幅频特性可以如图5A所示。图5A中所示的分解滤波器组包括两个分解滤波器，一个分解滤波器可以为低通滤波器，频率响应的幅值为|H0(ejw)|。另一个分解滤波器可以为高通滤波器，频率响应的幅值为|H1(ejw)|。当M大于2时，分解滤波器的幅频特性可以如图5B所示。每个分解滤波器对信号进行处理后，得到是一个频段的信号。
应理解，本发明实施例中的M个滤波信号的频段互不重叠不做严格限定，只要M个频段能够基本不失真地恢复出原始信号的都在本发明的保护范围之内。例如，本发明实施例中的互不重叠可以为M个滤波器相互正交。
应理解，这里对信号进行滤波处理，可以使用模拟滤波和数字滤波。本发明对此不作限定。例如，可以通过分解或合成滤波器组对信号进行分解或合成滤波处理，也可以通过数字滤波来实现对信号的分解或合成滤波处理。
402，对滤波信号进行M倍抽取。
分别对M个滤波信号通过M倍抽取，得到M个抽取信号，抽取信号的样点数减为待处理信号样点数的1/M。假设待处理信号的样点数为N，经过M倍抽取之后，每条支路中信号的样点数变为N/M。例如，经过2倍抽取之后，每条支路中信号的样点数变为N/2。
403，对抽取信号进行FFT。
对M个抽取信号分别进行FFT，得到M个频域信号。这样，通过滤波、抽取和FFT之后得到FFT信号的运算量相比直接对待处理信号进行FFT的运算量要小，可以降低运算复杂度。
404，对频域信号进行频域处理，得到频域处理信号。
可选地，可以对M个频域信号分别进行频域处理，得到M个频域处理信号。这里的频域处理可以为频域均衡处理。应理解，可以串行地对每路频域信号进行频域均衡处理。也可以并行地对M路频域信号进行频域均衡处理。
最后可以对频域处理信号进行并串转换，将并串转换的结果作为输出信号而输出。
本发明实施例可以串行对M路信号进行处理，也可以并行地对M路信号进行处理。并行处理时，可以在降低运算复杂度的同时，以进一步地提高计算并行度，提高处理信号的速率。
图6是本发明再一实施例的处理信号的过程的示意图。
601，对M个分解信号分别进行快速傅立叶逆变换IFFT。
对M个分解信号分别进行快速傅立叶逆变换IFFT，得到M个时域信号。
这里，M个分解信号是对输入信号进行分解得到的。M个分解信号的频段互不重叠，输入信号为具有N个采样点的频域信号，M个分解信号的采样点数之和为N，M为大于或等于2的整数，N为正整数。
在对M个分解信号分别进行快速傅立叶逆变换IFFT之前，还可以对待处理的信号进行串并转换，得到并行的待处理信号，并将并行的待处理信号进行分解，得到M个分解信号。
在对M个分解信号分别进行快速傅立叶逆变换IFFT之前，还可以对每路信号进行分解，并将分解后的信号进行频域处理，得到的信号作为分解信号。
602，对M个时域信号分别进行M倍插值。
对M个时域信号分别进行M倍插值，得到M个插值信号y0′(n)、……yM-1′(n)，每个插值信号的样点数与原输入x(n)的样点数相同。插值可以为将时域信号两个样点之间补入插值。例如，M倍可以将信号中每两个样点之间补入M-1个零值。
假设输入信号的采样点数为N，每个分解信号的样点数N/M，那么每个插值信号的样点数为N。
603，对M个插值信号分别进行滤波处理。
对M个插值信号分别进行滤波，得到M个滤波信号。对信号进行插值 处理后，每路的信号频段得到扩展，插值信号中包括频域镜像信号，为了消除镜像信号，可以对每路的插值信号进行滤波处理，以得到某一频段的信号。本发明实施例中的滤波可以为数字滤波，也可以为模拟滤波。
可选地，在得到M个插值信号之后，可以对M个滤波信号进行串并转换，得到并行信号，并将该并行信号进行输出信号。
本发明实施例可以对M条支路进行串行处理，也可以对M条支路进行并行处理。并行处理可以在降低运算复杂度的同时，进一步提高计算并行度。
图7是本发明再一实施例的处理信号的过程的示意图。
701，对输入信号进行M路第一滤波。
对输入信号进行M路第一滤波，以将输入信号分解成M个第一滤波信号，输入信号为具有N个采样点的时域信号，M个滤波信号的频段互不重叠，M为大于或等于2的整数，N为正整数。
在对输入信号进行M路第一滤波之前，还可以对待处理的信号进行串并转换，得到并行的待处理信号，将该并行的待处理信号作为输入信号。
应理解，可以通过对并行的待处理信号进行复制，得到M个复制信号。每个复制信号的采样点数与待处理信号的采样点数相同，都为N。
假定输入信号为x(n)，通过M路第一滤波处理后得到M个滤波信号y0(n)、y1(n)…yM-1(n)。
702，对第一滤波信号进行M倍抽取。
分别对M个第一滤波信号通过M倍抽取，得到M个抽取信号，抽取信号的样点数减为待处理信号样点数的1/M。假设待处理信号的样点数为N，经过M倍抽取之后，每路中信号的样点数变为N/M。例如，经过2倍抽取之后，每条支路中信号的样点数变为N/2。
703，对抽取信号进行FFT。
对M个抽取信号分别进行FFT，得到M个频域信号。这样，通过滤波、抽取和FFT之后得到FFT信号的运算量相比直接对待处理信号进行FFT的运算量要小，可以降低运算复杂度。
704，对频域信号进行频域处理，得到频域处理信号。
可选地，对M个频域信号分别进行频域处理，可以得到M个频域处理信号。这里的频域处理可以为频域均衡处理。应理解，可以串行地对每路频域信号进行频域均衡处理。也可以并行地对M路频域信号进行频域均衡处 理。
705，对M个频域处理信号分别进行IFFT。
对M个频域处理信号进行快速傅立叶逆变换IFFT，得到M个时域信号。
706，对M个时域信号分别进行M倍插值。
对M个时域信号分别进行M倍插值，得到M个插值信号y0′(n)、……yM-1′(n)，M个插值信号的样点数与输出信号x(n)的样点数相同。插值可以为将时域信号两个样点之间补入插值。
707，对M个插值信号进行第二滤波处理。
对M个插值信号进行第二滤波处理，得到每路的第二滤波信号。对信号进行插值处理后，每路的信号频段得到扩展，插值信号中包括频域镜像信号，为了消除镜像信号，可以对每路的插值信号进行滤波处理，以得到某一频段的信号。本发明实施例中的合成滤波可以为数字滤波，也可以为模拟滤波。
在得到第二滤波信号之后，可以对M个第二滤波信号进行进行串并转换，得到并行信号，并将该并行信号作为输出信号。
单载波系统的接收机包括既包括FFT，又包括IFFT，这样通过在FFT之前对信号进行滤波和抽取，并在IFFT之后对信号进行插值和滤波，可以减小运算量。进一步地，当对M路的信号进行并行处理时，还可以进一步地提高计算并行度，加速对数据进行处理。
应理解，本发明实施例不仅可以应用在通信系统中，还可以应用在图像处理中，只要涉及FFT、IFFT成对出现并通过本发明的实现方式降低运算量的方案都在本发明的保护范围之内。
应理解，本发明实施例不仅可以应用在一维系统中，还可以应用在二维系统中，本发明实施例对此不做限定。
上文中结合图1到图7，详细描述了根据本发明实施例的处理信号的方法，下面将结合图8到图13描述根据本发明实施例的处理信号的装置。
图8是本发明一个实施例的处理信号的装置的框图。图8的装置10包括：滤波单元11，抽取单元12、快速傅立叶变换FFT单元13和确定单元14。
滤波单元11包括M个滤波器，滤波单元11包括M个滤波器，M个滤波器分别用于对输入信号进行滤波，以得到M个滤波信号，输入信号为具 有N个采样点的时域信号，M个滤波信号的频段互不重叠，M为大于或等于2的整数，N为正整数。
抽取单元12包括M个抽取器，M个抽取器与M个滤波器一一对应连接，M个抽取器分别用于对滤波单元得到的M个滤波信号分别进行抽取，得到M个抽取信号，M个抽取信号的采样点数之和为N。
快速傅立叶变换FFT单元13包括M个FFT器，M个FFT器与M个抽取器一一对应连接，M个FFT器用于对抽取单元得到的M个抽取信号分别进行快速傅立叶变换FFT，得到M个频域信号。
确定单元14用于根据FFT单元得到的M个频域信号得到输出信号。
本发明实施例对输入信号进行M路滤波，并对滤波后的滤波信号进行抽取得到抽取信号，使得M个抽取信号的采样点数之和为输入信号的采样点数，这样可以对M个抽取信号分别进行FFT，避免对输入信号直接进行FFT带来的运算复杂度递增的问题，能够降低运算复杂度。
可选地，作为本发明的一个实施例，M个滤波信号中的每个滤波信号的频段占输入信号的频段的1/M。
可选地，作为本发明的一个实施例，每个抽取信号的采样点数为N/M。
可选地，作为本发明的一个实施例，滤波单元具体用于对输入信号进行复制，得到输入信号的M个复制信号，M个滤波器串行或并行地对M个复制信号分别进行滤波，得到M个滤波信号。
根据本发明实施例的处理信号的装置可对应于本发明实施例的方法中的对应装置，并且，该装置中的各个单元/模块和上述其他操作和/或功能分别为了实现图1中所示方法的相应流程以及图4中的相应流程，为了简洁，在此不再赘述。
图9是本发明另一实施例的处理信号的装置的框图。图9的装置20包括：分解单元21、快速傅立叶逆变换IFFT单元22、插值单元23、滤波单元24和确定单元25。
分解单元21用于对输入信号进行分解，得到M个分解信号。M个分解信号的频段互不重叠，输入信号为具有N个采样点的频域信号，M个分解信号的采样点数之和为N，M为大于或等于2的整数，N为正整数。
快速傅立叶逆变换IFFT单元22包括M个IFFT器。M个分解信号一一对应分别进行输入M个IFFT器，M个IFFT器用于对分解单元得到的M个 分解信号分别进行快速傅立叶逆变换IFFT，得到M个时域信号。
插值单元23包括M个插值器。M个插值器与M个IFFT器一一对应连接，M个插值器用于对IFFT单元得到的M个时域信号分别进行插值，得到M个插值信号，每个插值信号的采样点数为N。
滤波单元24包括M个滤波器。M个滤波器与M个插值器一一对应连接，M个滤波器用于对插值单元得到的M个插值信号分别进行滤波，得到M个滤波信号。
确定单元25用于根据滤波单元得到的M个滤波信号确定输出信号。
本发明实施例对输入信号进行分解，并对分解后的分解信号分别进行IFFT，然后对IFFT得到的时域信号进行插值，最后对插值后的信号进行滤波，并得到输出信号。这样通过对M个分解信号分别进行IFFT，避免对输入信号直接进行IFFT带来的运算复杂度递增的问题，能够降低运算复杂度。
可选地，作为本发明的一个实施例，每个分解信号的频段占所述输入信号的频段的1/M。
可选地，作为本发明的一个实施例，每个分解信号的采样点数为N/M。
可选地，作为本发明的一个实施例，M个IFFT器具体用于串行或并行地对M个分解信号分别进行快速傅立叶逆变换IFFT，得到M个时域信号。
根据本发明实施例的处理信号的装置可对应于本发明实施例的方法中的装置，并且，该装置中的各个单元/模块和上述其他操作和/或功能分别为了实现图2中所示方法的相应流程以及图6中的相应流程，为了简洁，在此不再赘述。
图10是本发明再一实施例的处理信号的装置的框图。图10的装置30包括：第一滤波单元31、抽取单元32、快速傅立叶变换FFT单元33和频域均衡单元34。
第一滤波单元31包括M个第一滤波器，M个第一滤波器用于对输入信号进行M路第一滤波，以将输入信号分解成M个第一滤波信号，输入信号为具有N个采样点的时域信号，M个第一滤波信号的频段互不重叠，M为大于或等于2的整数，N为正整数。
抽取单元32包括M个抽取器，M个抽取器与M个第一滤波器一一对应连接。M个抽取器用于对M个第一滤波信号分别进行抽取，得到M个抽取信号，M个抽取信号采样点数之和为N。
快速傅立叶变换FFT单元33包括M个FFT器。M个FFT与M个抽取器一一对应连接，M个FFT器用于对M个抽取信号分别进行快速傅立叶变换FFT，得到M个频域信号。
频域均衡单元34包括M个频域均衡器，M个频域均衡器与M个FFT一一对应连接。M个频域均衡器用于对M个频域信号分别进行频域处理，得到M个频域处理信号。
本发明实施例对输入信号进行M路滤波，并对滤波后的滤波信号进行抽取得到抽取信号，使得M个抽取信号的采样点数之和为输入信号的采样点数，这样可以对M个抽取信号分别进行FFT，避免对输入信号直接进行FFT带来的运算复杂度递增的问题，能够降低运算复杂度。
可选地，作为本发明的一个实施例，M个第一滤波信号中的每个滤波信号的频段占输入信号的频段的1/M。
可选地，作为本发明的一个实施例，每个抽取信号的采样点数为N/M。
可选地，作为本发明的一个实施例，装置30还可以包括快速傅立叶逆变换IFFT单元35、插值单元36、第二滤波单元37和确定单元38。其中，快速傅立叶逆变换IFFT单元35包括M个IFFT器，M个IFFT器与M个频域均衡器一一对应连接。M个IFFT用于对M个频域处理信号分别进行快速傅立叶逆变换IFFT，得到M个时域信号。插值单元36包括M个插值器，M个插值器与M个IFFT器一一对应连接。M个插值器用于对M个时域信号分别进行插值，得到每M个插值信号，每个插值信号的采样点数为N。第二滤波单元37包括M个第二滤波器，M个第二滤波器与M个插值器一一对应连接。M个第二滤波器用于对M个插值信号分别进行第二滤波，得到M个第二滤波信号。确定单元38用于根据M个第二滤波信号确定输出信号。
根据本发明实施例的处理信号的装置可对应于本发明实施例的方法中的装置，并且，该装置中的各个单元/模块和上述其他操作和/或功能分别为了实现图3中所示方法的相应流程以及图7的相应流程，为了简洁，在此不再赘述。
图11是本发明再一实施例的处理信号的装置的框图。
图11装置40包括处理器41、存储器42和总线系统43。处理器41控制装置40的操作。存储器42可以包括只读存储器和随机存取存储器，并向 处理器41提供指令和数据。存储器42的一部分还可以包括非易失行随机存取存储器(NVRAM，Non-Volatile Random Access Memory)。装置的各个组件通过总线系统43耦合在一起，其中总线系统43除包括数据总线之外，还包括电源总线、控制总线和状态信号总线。但是为了清楚说明起见，在图中将各种总线都标为总线系统43。
上述本发明实施例揭示的方法可以应用于处理器41中，或者由处理器41实现。在实现过程中，上述方法的各步骤可以通过处理器41中的硬件的集成逻辑电路或者软件形式的指令完成。处理器41可以是通用处理器、数字信号处理器、专用集成电路、现场可编程门阵列或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件，可以实现或者执行本发明实施例中的公开的各方法、步骤及逻辑框图。通用处理器可以是微处理器或者任何常规的处理器等。结合本发明实施例所公开的方法的步骤可以直接体现为硬件处理器执行完成，或者用处理器中的硬件及软件模块组合执行完成。软件模块可以位于随机存储器，闪存、只读存储器，可编程只读存储器或者电可擦写可编程存储器、寄存器等本领域成熟的存储介质中。该存储介质位于存储器42，处理器41读取存储器42中的信息，结合其硬件完成上述方法的步骤。
具体地，处理器41可以利用M个滤波器对输入信号进行滤波，以得到M个滤波信号，输入信号为具有N个采样点的时域信号，M个滤波信号的频段互不重叠，M为大于或等于2的整数，N为正整数。并利用M个抽取器用于对M个滤波信号分别进行抽取，得到M个抽取信号，M个抽取信号的采样点数之和为N。对M个抽取信号进行快速傅立叶变换FFT，得到M个频域信号。并根据M个频域信号得到输出信号。
装置40能够实现前述方法实施例中的步骤，为避免重复，不再详细描述。
可选地，在本发明的一个实施例中，M个滤波信号中的每个滤波信号的频段占输入信号的频段的1/M。
可选地，在本发明的一个实施例中，每个抽取信号的采样点数为N/M。
可选地，在本发明的一个实施例中，处理器41可以对输入信号进行复制，得到输入信号的M个复制信号，串行或并行地对M个复制信号分别进行滤波，得到所述M个滤波信号。
根据本发明实施例的处理信号的装置可对应于本发明实施例的方法中的对应装置，并且，该装置中的各个单元/模块和上述其他操作和/或功能分别为了实现图1中所示方法的相应流程以及图4中的相应流程，为了简洁，在此不再赘述。
图12是本发明再一实施例的处理信号的装置的框图。
图12装置50包括处理器51、存储器52和总线系统53。处理器51控制装置50的操作。存储器52可以包括只读存储器和随机存取存储器，并向处理器51提供指令和数据。存储器52的一部分还可以包括非易失行随机存取存储器(NVRAM，Non-Volatile Random Access Memory)。装置的各个组件通过总线系统53耦合在一起，其中总线系统53除包括数据总线之外，还包括电源总线、控制总线和状态信号总线。但是为了清楚说明起见，在图中将各种总线都标为总线系统53。
上述本发明实施例揭示的方法可以应用于处理器51中，或者由处理器51实现。在实现过程中，上述方法的各步骤可以通过处理器51中的硬件的集成逻辑电路或者软件形式的指令完成。处理器51可以是通用处理器、数字信号处理器、专用集成电路、现场可编程门阵列或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件，可以实现或者执行本发明实施例中的公开的各方法、步骤及逻辑框图。通用处理器可以是微处理器或者任何常规的处理器等。结合本发明实施例所公开的方法的步骤可以直接体现为硬件处理器执行完成，或者用处理器中的硬件及软件模块组合执行完成。软件模块可以位于随机存储器，闪存、只读存储器，可编程只读存储器或者电可擦写可编程存储器、寄存器等本领域成熟的存储介质中。该存储介质位于存储器52，处理器51读取存储器52中的信息，结合其硬件完成上述方法的步骤。
具体地，处理器51可以对输入信号进行分解，得到M个分解信号，M个分解信号的频段互不重叠，输入信号为具有N个采样点的频域信号述M个分解信号的采样点数之和为N，M为大于或等于2的整数，N为正整数。对M个分解信号分别进行快速傅立叶逆变换IFFT，得到M个时域信号。对M个时域信号分别进行插值，得到M个插值信号，每个插值信号的采样点数为N。对M个插值信号分别进行滤波，得到M个滤波信号，并根据M个滤波信号确定输出信号。
本发明实施例对输入信号进行分解，并对分解后的分解信号分别进行IFFT，然后对IFFT得到的时域信号进行插值，最后对插值后的信号进行滤波，并得到输出信号。这样通过对M个分解信号分别进行IFFT，避免对输入信号直接进行IFFT带来的运算复杂度递增的问题，能够降低运算复杂度。
根据本发明实施例的处理信号的装置50可对应于本发明实施例的方法中的装置，并且，该装置中的各个单元/模块和上述其他操作和/或功能分别为了实现图2中所示方法的相应流程以及图6中的相应流程，为了简洁，在此不再赘述。
可选地，在本发明的一个实施例中，每个分解信号的频段占输入信号的频段的1/M。
可选地，在本发明的一个实施例中，每个分解信号的采样点数为N/M。
可选地，在本发明的一个实施例中，处理器51用于串行或并行地对M个分解信号分别进行快速傅立叶逆变换IFFT，得到M个时域信号。
图13是本发明再一实施例的处理信号的装置的框图。
图6装置60包括处理器61、存储器62和总线系统63。处理器61控制装置60的操作。存储器62可以包括只读存储器和随机存取存储器，并向处理器61提供指令和数据。存储器62的一部分还可以包括非易失行随机存取存储器(NVRAM，Non-Volatile Random Access Memory)。装置的各个组件通过总线系统63耦合在一起，其中总线系统63除包括数据总线之外，还包括电源总线、控制总线和状态信号总线。但是为了清楚说明起见，在图中将各种总线都标为总线系统63。
上述本发明实施例揭示的方法可以应用于处理器61中，或者由处理器61实现。在实现过程中，上述方法的各步骤可以通过处理器61中的硬件的集成逻辑电路或者软件形式的指令完成。处理器61可以是通用处理器、数字信号处理器、专用集成电路、现场可编程门阵列或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件，可以实现或者执行本发明实施例中的公开的各方法、步骤及逻辑框图。通用处理器可以是微处理器或者任何常规的处理器等。结合本发明实施例所公开的方法的步骤可以直接体现为硬件处理器执行完成，或者用处理器中的硬件及软件模块组合执行完成。软件模块可以位于随机存储器，闪存、只读存储器，可编程只读存储器或者电可擦写可编程存储器、寄存器等本领域成熟的存储介质中。该存储介质位于 存储器62，处理器61读取存储器62中的信息，结合其硬件完成上述方法的步骤。
具体地，处理器61可以对输入信号进行M路第一滤波，以将输入信号分解成M个第一滤波信号，输入信号为具有N个采样点的时域信号，M个第一滤波信号的频段互不重叠，M为大于或等于2的整数，N为正整数。对M个第一滤波信号分别进行抽取，得到M个抽取信号，M个抽取信号采样点数之和为N。对M个抽取信号分别进行快速傅立叶变换FFT，得到M个频域信号。对M个频域信号分别进行频域处理，得到M个频域处理信号。
本发明实施例对输入信号进行M路滤波，并对滤波后的滤波信号进行抽取得到抽取信号，使得M个抽取信号的采样点数之和为输入信号的采样点数，这样可以对M个抽取信号分别进行FFT，避免对输入信号直接进行FFT带来的运算复杂度递增的问题，能够降低运算复杂度。
可选地，作为本发明的一个实施例，M个第一滤波信号中的每个滤波信号的频段占输入信号的频段的1/M。
可选地，作为本发明的一个实施例，每个抽取信号的采样点数为N/M。
可选地，作为本发明的一个实施例，处理器61还可以对M个频域处理信号分别进行快速傅立叶逆变换IFFT，得到M个时域信号。对M个时域信号分别进行插值，得到每M个插值信号，每个插值信号的采样点数为N。对M个插值信号分别进行第二滤波，得到M个第二滤波信号。并根据M个第二滤波信号确定输出信号。
装置60能够实现前述方法实施例中的步骤，为避免重复，不再详细描述。
根据本发明实施例的处理信号的装置可对应于本发明实施例的方法中的装置，并且，该装置中的各个单元/模块和上述其他操作和/或功能分别为了实现图3中所示方法的相应流程以及图7的相应流程，为了简洁，在此不再赘述。
应理解，说明书通篇中提到的“一个实施例”或“一实施例”意味着与实施例有关的特定特征、结构或特性包括在本发明的至少一个实施例中。因此，在整个说明书各处出现的“在一个实施例中”或“在一实施例中”未必一定指相同的实施例。此外，这些特定的特征、结构或特性可以任意适合的方式结合在一个或多个实施例中。
应理解，在本发明的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本发明实施例的实施过程构成任何限定。
应理解，在本发明实施例中，“与A相应的B”表示B与A相关联，根据A可以确定B。但还应理解，根据A确定B并不意味着仅仅根据A确定B，还可以根据A和/或其它信息确定B。
另外，本文中术语“系统”和“网络”在本文中常可互换使用。应理解，本文中术语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，本文中字符“/”，一般表示前后关联对象是一种“或”的关系。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本发明的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本发明各个实施例中的各功能单元可以集成在一个处理单元 中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (24)

  1. 一种处理信号的方法，其特征在于，包括：
    对输入信号进行M路滤波，以将所述输入信号分解成M个滤波信号，所述输入信号为具有N个采样点的时域信号，所述M个滤波信号的频段互不重叠，M为大于或等于2的整数，N为正整数；
    对所述M个滤波信号分别进行抽取，得到M个抽取信号，所述M个抽取信号的采样点数之和为N；
    对所述M个抽取信号分别进行快速傅立叶变换FFT，得到M个频域信号；
    根据所述M个频域信号确定输出信号。
  2. 如权利要求1所述的方法，其特征在于，所述M个滤波信号中的每个滤波信号的频段占所述输入信号的频段的1/M。
  3. 如权利要求1或2所述的方法，其特征在于，每个所述抽取信号的采样点数为N/M。
  4. 如权利要求1-3中任一项所述的方法，其特征在于，所述对输入信号进行M路滤波，以将所述输入信号分解成M个滤波信号，包括：
    对所述输入信号进行复制，得到所述输入信号的M个复制信号；
    串行或并行地对所述M个复制信号分别进行滤波，得到所述M个滤波信号。
  5. 一种处理信号的方法，其特征在于，包括：
    对输入信号进行分解，得到M个分解信号，所述M个分解信号的频段互不重叠，所述输入信号为具有N个采样点的频域信号，所述M个分解信号的采样点数之和为N，M为大于或等于2的整数，N为正整数；
    对所述M个分解信号分别进行快速傅立叶逆变换IFFT，得到M个时域信号；
    对M个时域信号分别进行插值，得到M个插值信号，所述每个插值信号的采样点数为N；
    对所述M个插值信号分别进行滤波，得到M个滤波信号；
    根据所述M个滤波信号确定输出信号。
  6. 如权利要求5所述的方法，其特征在于，每个所述分解信号的频段 占所述输入信号的频段的1/M。
  7. 如权利要求5或6所述的方法，其特征在于，
    每个所述分解信号的采样点数为N/M。
  8. 如权利要求5-7中任一项所述的方法，其特征在于，所述对所述M个分解信号分别进行快速傅立叶逆变换IFFT，得到M个时域信号包括：
    串行或并行地对所述M个分解信号分别进行快速傅立叶逆变换IFFT，得到M个时域信号。
  9. 一种处理信号的方法，其特征在于，包括：
    对输入信号进行M路第一滤波，以将所述输入信号分解成M个第一滤波信号，所述输入信号为具有N个采样点的时域信号，所述M个第一滤波信号的频段互不重叠，M为大于或等于2的整数，N为正整数；
    对所述M个第一滤波信号分别进行抽取，得到M个抽取信号，所述M个抽取信号采样点数之和为N；
    对所述M个抽取信号分别进行快速傅立叶变换FFT，得到M个频域信号；
    对所述M个频域信号分别进行频域处理，得到M个频域处理信号。
  10. 如权利要求9所述的方法，其特征在于，所述M个第一滤波信号中的每个滤波信号的频段占所述输入信号的频段的1/M。
  11. 如权利要求9或10所述的方法，其特征在于，每个所述抽取信号的采样点数为N/M。
  12. 如权利要求9-11中任一项所述的方法，其特征在于，所述方法还包括：
    对所述M个频域处理信号分别进行快速傅立叶逆变换IFFT，得到M个时域信号；
    对所述M个时域信号分别进行插值，得到每M个插值信号，每个所述插值信号的采样点数为N；
    对所述M个插值信号分别进行第二滤波，得到M个第二滤波信号；
    根据所述M个第二滤波信号确定输出信号。
  13. 一种处理信号的装置，其特征在于，包括：
    滤波单元，所述滤波单元包括M个滤波器，所述M个滤波器分别用于对输入信号进行滤波，以得到M个滤波信号，所述输入信号为具有N个采 样点的时域信号，所述M个滤波信号的频段互不重叠，M为大于或等于2的整数，N为正整数；
    抽取单元，所述抽取单元包括M个抽取器，所述M个抽取器与所述M个滤波器一一对应连接，所述M个抽取器分别用于对所述滤波单元得到的所述M个滤波信号分别进行抽取，得到M个抽取信号，所述M个抽取信号的采样点数之和为N；
    快速傅立叶变换FFT单元，所述FFT单元包括M个FFT器，所述M个FFT器与所述M个抽取器一一对应连接，所述M个FFT器用于对所述抽取单元得到的所述M个抽取信号分别进行快速傅立叶变换FFT，得到M个频域信号；
    确定单元，用于根据所述FFT单元得到的所述M个频域信号得到输出信号。
  14. 如权利要求13所述的装置，其特征在于，所述M个滤波信号中的每个滤波信号的频段占所述输入信号的频段的1/M。
  15. 如权利要求13或14所述的装置，其特征在于，每个所述抽取信号的采样点数为N/M。
  16. 如权利要求13-15中任一项所述的装置，其特征在于，所述滤波单元具体用于对所述输入信号进行复制，得到所述输入信号的M个复制信号，所述M个滤波器串行或并行地对所述M个复制信号分别进行滤波，得到所述M个滤波信号。
  17. 一种处理信号的装置，其特征在于，包括：
    分解单元，用于对输入信号进行分解，得到M个分解信号，所述M个分解信号的频段互不重叠，所述输入信号为具有N个采样点的频域信号，所述M个分解信号的采样点数之和为N，M为大于或等于2的整数，N为正整数；
    快速傅立叶逆变换IFFT单元，所述IFFT单元包括M个IFFT器，M个分解信号一一对应分别进行输入M个IFFT器，所述M个IFFT器用于对所述分解单元得到的所述M个分解信号分别进行快速傅立叶逆变换IFFT，得到M个时域信号；
    插值单元，所述插值单元包括M个插值器，所述M个插值器与所述M个IFFT器一一对应连接，所述M个插值器用于对所述IFFT单元得到的所 述M个时域信号分别进行插值，得到M个插值信号，每个所述插值信号的采样点数为N；
    滤波单元，所述滤波单元包括M个滤波器，所述M个滤波器与所述M个插值器一一对应连接，所述M个滤波器用于对所述插值单元得到的所述M个插值信号分别进行滤波，得到M个滤波信号；
    确定单元，用于根据所述滤波单元得到的所述M个滤波信号确定输出信号。
  18. 如权利要求17所述的装置，其特征在于，
    每个所述分解信号的频段占所述输入信号的频段的1/M。
  19. 如权利要求17或18所述的装置，其特征在于，
    每个所述分解信号的采样点数为N/M。
  20. 如权利要求17-19中任一项所述的装置，其特征在于，所述M个IFFT器具体用于串行或并行地对所述M个分解信号分别进行快速傅立叶逆变换IFFT，得到M个时域信号。
  21. 一种处理信号的装置，其特征在于，包括：
    第一滤波单元，所述第一滤波单元包括M个第一滤波器，所述M个第一滤波器用于对输入信号进行M路第一滤波，以将所述输入信号分解成M个第一滤波信号，所述输入信号为具有N个采样点的时域信号，所述M个第一滤波信号的频段互不重叠，M为大于或等于2的整数，N为正整数；
    抽取单元，所述抽取单元包括M个抽取器，所述M个抽取器与所述M个第一滤波器一一对应连接，所述M个抽取器用于对所述M个第一滤波信号分别进行抽取，得到M个抽取信号，所述M个抽取信号采样点数之和为N；
    快速傅立叶变换FFT单元，所述FFT单元包括M个FFT器，所述M个FFT与所述M个抽取器一一对应连接，所述M个FFT器用于对所述M个抽取信号分别进行快速傅立叶变换FFT，得到M个频域信号；
    频域均衡单元，所述频域均衡单元包括M个频域均衡器，所述M个频域均衡器与所述M个FFT一一对应连接，所述M个频域均衡器用于对所述M个频域信号分别进行频域处理，得到M个频域处理信号。
  22. 如权利要求21所述的装置，其特征在于，所述M个第一滤波信号中的每个滤波信号的频段占所述输入信号的频段的1/M。
  23. 如权利要求21或22所述的装置，其特征在于，每个所述抽取信号的采样点数为N/M。
  24. 如权利要求21-23中任一项所述的装置，其特征在于，所述装置还包括：
    快速傅立叶逆变换IFFT单元，所述IFFT单元包括M个IFFT器，所述M个IFFT器与所述M个频域均衡器一一对应连接，所述M个IFFT用于对所述M个频域处理信号分别进行快速傅立叶逆变换IFFT，得到M个时域信号；
    插值单元，所述插值单元包括M个插值器，所述M个插值器与所述M个IFFT器一一对应连接，所述M个插值器用于对所述M个时域信号分别进行插值，得到每M个插值信号，所述每个插值信号的采样点数为N；
    第二滤波单元，所述第二滤波单元包括M个第二滤波器，所述M个第二滤波器与所述M个插值器一一对应连接，所述M个第二滤波器用于对所述M个插值信号分别进行第二滤波，得到M个第二滤波信号；
    确定单元，用于根据所述M个第二滤波信号确定输出信号。
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