WO2016179982A1 - 移位寄存器及其驱动方法、栅极驱动电路和显示装置 - Google Patents

移位寄存器及其驱动方法、栅极驱动电路和显示装置 Download PDF

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Publication number
WO2016179982A1
WO2016179982A1 PCT/CN2015/094182 CN2015094182W WO2016179982A1 WO 2016179982 A1 WO2016179982 A1 WO 2016179982A1 CN 2015094182 W CN2015094182 W CN 2015094182W WO 2016179982 A1 WO2016179982 A1 WO 2016179982A1
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Prior art keywords
transistor
pull
shift register
module
signal
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PCT/CN2015/094182
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English (en)
French (fr)
Inventor
李金钰
陈希
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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Priority to US15/326,846 priority Critical patent/US9972238B2/en
Priority to EP15891678.3A priority patent/EP3296997B1/en
Publication of WO2016179982A1 publication Critical patent/WO2016179982A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a shift register and a driving method thereof, a gate driving circuit, and a display device.
  • High-resolution, narrow-frame has become the development trend of flat-panel display technology, and integrating the gate drive circuit on the display panel is the most important solution to achieve high-resolution, narrow-frame display.
  • the gate driving circuit is composed of a plurality of stages of shift registers
  • FIG. 1 is a circuit diagram of a shift register provided by the prior art.
  • the shift register includes: a trigger transistor T100, a reset transistor T200, and a first pull-up transistor T300.
  • the first pull-up transistor T300 is used to pull up the signal output from the output of the shift register
  • the second pull-up transistor T400 is used to pull up the signal output from the transfer signal output of the shift register.
  • the transfer signal output terminal of the shift register is a cascade terminal of the cascade shift register and the previous shift register and the next shift register.
  • the first node PU1 is a connection point of the bootstrap capacitor C100 and the gate of the second pull-up transistor T400.
  • STV is a start signal input to the start signal terminal connected to the gate of the trigger transistor T100
  • RESET is a reset signal input to the reset signal terminal connected to the gate of the reset transistor T200
  • CLK is a drain with the second pull-up transistor T400.
  • the clock signal input to the clock signal terminal of the pole connection, OUTPUT is the signal outputted by the output terminal of the shift register
  • VZ is the transmission signal outputted by the output terminal of the shift register
  • VGH represents the voltage of the high level
  • VGL represents the low voltage. Flat voltage.
  • the voltage of the first node PU1 jumps, that is, jumps from a high level to a low level, and the voltage coupling effect of the bootstrap capacitor C100 directly causes the transfer of the shift register.
  • the signal output VZ of the output of the signal output produces a spike, which seriously affects the stability of the shift transfer of the shift register.
  • the stability of the shift transfer of the shift register reduces the noise of the shift register circuit, thereby affecting the shift register.
  • the present invention is directed to the above technical problems existing in the prior art, and provides a shift register, a driving method thereof, a gate driving circuit, and a display device.
  • the denoising module By setting the denoising module to make the voltage of the pull-up node jump, the coupling effect of the capacitor can be prevented, so that the transmission signal outputted by the shift register output signal produces a spike and other noise, thereby shifting
  • the bit transfer of the bit register is more stable, which makes the signal output from the shift register more stable.
  • the invention provides a shift register comprising a pull-up module, a first capacitor and a pull-down module, characterized in that it further comprises a denoising module.
  • the first end of the denoising module is connected to the second end of the first capacitor, and the second end of the denoising module is connected to the output signal output end; wherein the output of the pull-up module and the shift register a terminal coupled to the transfer signal output and coupled to the first end of the first capacitor, and for outputting a signal to an output of the shift register under control of the first end of the first capacitor And a signal pull-up outputted by the output signal, the connection point of the pull-up module and the first end of the first capacitor is a pull-up node; the pull-down module and the output of the shift register
  • the transfer signal output terminal is connected and connected to the first end of the first capacitor, and is configured to pull down a signal outputted by the output end of the shift register and a signal outputted by the transfer signal output terminal in a pull-down phase;
  • the denoising module includes a ninth transistor, a gate of the ninth transistor and a first pole connected to a second end of the first capacitor, and a second pole of the ninth transistor is connected to the transfer signal Output.
  • the ninth transistor is an N-type transistor having a first drain and a second source.
  • the denoising module includes a ninth transistor, the first pole of the ninth transistor is connected to the second end of the first capacitor, and the gate and the second pole of the ninth transistor are connected to the transmission signal output end.
  • the ninth transistor is a P-type transistor having a first source and a second drain.
  • the pull-up module includes a first sub-module and a second sub-module, the first sub-module and the second sub-module are connected to the pull-up node, and the first sub-module is further connected to the first a clock signal end and the transfer signal output end, the second submodule further connected to the first power source and the output end of the shift register; the first submodule is configured to output a signal to the transfer signal output end get on Pulling up; the second submodule is configured to pull up a signal outputted by the output of the shift register.
  • the pull-down module includes a third sub-module and a fourth sub-module, the third sub-module and the fourth sub-module are connected to a pull-down node, and the third sub-module is connected to the second clock signal end and the a first power supply, the fourth sub-module is connected to the second power source, the output end, the second pole of the ninth transistor, and the transfer signal output end, and the fourth sub-module and the first a submodule and the second submodule are connected to the pull-up node; the third sub-module is configured to control a potential of the pull-down node in a pull-down phase; and the fourth sub-module is configured to The signal output from the output of the shift register and the signal output from the output of the transfer signal are pulled down.
  • the first sub-module includes a fourth transistor, a gate of the fourth transistor is connected to the pull-up node, and a first pole of the fourth transistor is connected to the first clock signal end, a second pole of the four transistor is connected to the output signal output terminal;
  • the second submodule includes a third transistor, a gate of the third transistor is connected to the pull-up node, and a first pole of the third transistor is connected The first power source, the second electrode of the third transistor is coupled to an output of the shift register.
  • the third sub-module includes a fifth transistor and a sixth transistor, a gate of the fifth transistor and a first pole connected to the second clock signal end, and a second pole connection of the fifth transistor a gate of the sixth transistor; a first electrode of the sixth transistor is connected to the first power source and a first pole of the third transistor, and a second pole of the sixth transistor is connected to the pull-down node;
  • the fourth sub-module includes a seventh transistor, an eighth transistor, a tenth transistor, and an eleventh transistor, wherein a gate of the tenth transistor and a first pole of the seventh transistor are both connected to the pull-up node; a first pole of the tenth transistor, a gate of the seventh transistor, a gate of the eighth transistor, and a gate of the eleventh transistor are all connected to the pull-down node; a second pole, a second pole of the seventh transistor, a second pole of the eighth transistor, and a second pole of the eleventh transistor are all connected to the second power source; a first
  • the first clock signal outputted by the first clock signal end and the second clock signal outputted by the second clock signal end are 180 degrees out of phase.
  • the shift register further includes a trigger reset module for charging and discharging the pull-up node according to a start signal input by the start signal input terminal and a reset signal input by the reset signal input terminal.
  • the triggering reset module includes a triggering submodule and a resetting submodule, the triggering submodule and the resetting submodule are connected to the pullup node, and the triggering submodule is connected to the third power source.
  • the reset sub-module is connected to the fourth power source; the trigger sub-module is configured to charge the pull-up node according to a start signal input by the start signal input terminal; and the reset sub-module is configured to be used according to the reset A reset signal input to the signal input discharges the pull-up node.
  • the trigger sub-module includes a first transistor, a gate of the first transistor is connected to the start signal input end, and a first pole of the first transistor is connected to the third power supply, the first a second pole of the transistor is connected to the pull-up node;
  • the reset sub-module includes a second transistor, a gate of the second transistor is connected to the reset signal input end, and a first pole of the second transistor is connected to the Pulling up the node, the second pole of the second transistor is connected to the fourth power source.
  • the first to eighth transistors and the tenth and eleventh transistors are N-type transistors, the first of which is the extreme drain and the second of which is the source.
  • the present invention also provides a gate driving circuit comprising: a multi-stage shift register, wherein the shift register uses the shift register, and the transfer signal output end of the shift register of the present stage is shifted from the previous stage The reset signal input terminal of the register is connected to the start signal input terminal of the shift register of the next stage.
  • the present invention also provides a display device including the above-described gate driving circuit.
  • the present invention also provides a driving method of a shift register, comprising: in a first stage, the first capacitor is charged, and the pull-up module outputs the output of the shift register under the control of the pull-up node The output signal is pulled up; in the second stage, the first capacitor boosts the voltage of the pull-up node at the stage, and the pull-up module continues to pull up the signal outputted by the output of the shift register, and the upper
  • the pull module pulls up the signal outputted by the output signal output terminal; in the third stage, the first capacitor is discharged, and the pull-down module outputs a signal outputted to the output end of the shift register and the output of the transfer signal output end The signal is pulled down, and the denoising module cuts off a connection path between the transfer signal output end and the second end of the first capacitor.
  • the shift register and the gate driving circuit provided by the present invention can prevent the coupling effect of the first capacitor when the voltage of the shift register jumps at the pull-up node by setting the denoising module
  • the transfer signal outputted by the shift register transmission signal output generates noise such as spikes, so that the interstage shift transfer signal of the shift register is more stable, and the noise of the shift register circuit is also reduced, thereby making the shift register The signal output at the output is more stable.
  • the display device provided by the present invention improves the display quality of the display device by using the gate driving circuit to make the display of the display device more stable.
  • 1 is a circuit schematic diagram of a shift register in the prior art
  • FIG. 2 is a timing diagram of the shift register of FIG. 1;
  • FIG. 3 is a circuit schematic diagram of a shift register in Embodiment 1 of the present invention.
  • FIG. 4 is a circuit schematic diagram of the denoising module of FIG. 3 being an N-type transistor
  • Figure 5 is a circuit diagram of the shift register of Figure 3.
  • FIG. 6 is a timing chart of driving of the shift register of FIG. 5;
  • FIG. 7 is a circuit schematic diagram of a P-type transistor in a denoising module according to Embodiment 2 of the present invention.
  • FIG. 8 is a circuit diagram of a shift register in Embodiment 2 of the present invention.
  • FIG. 9 is a schematic diagram of cascade connection of a gate driving circuit in Embodiment 3 of the present invention.
  • the embodiment provides a shift register, as shown in FIG. 3, including a trigger reset module 1, a pull-up module 2, a first capacitor C1 and a pull-down module 3, and further includes a denoising module 4.
  • the reset module 1, the pull-up module 2, the pull-down module 3, and the first capacitor C1 are triggered.
  • the first end of the denoising module 4 is connected to the second end of the first capacitor C1, the second end of the denoising module 4 is connected to the pull-down module 3 and the output signal output terminal OUT1;
  • Both the module 2 and the pull-down module 3 are connected to the output terminal OUT2 of the shift register;
  • the pull-up module 2 and the pull-down module 3 are also connected to the transfer signal output terminal OUT1.
  • the trigger reset module 1 is configured to charge and discharge the pull-up node PU according to the start signal INPUT input from the start signal input terminal and the reset signal RESET input from the reset signal input terminal, thereby implementing triggering or resetting on the pull-up module 2.
  • the pull-up module 2 is used to pull up the signal output from the output terminal OUT2 of the shift register and the signal output from the output signal terminal OUT1.
  • the first capacitor C1 is used to boost the voltage of the pull-up node PU during the pull-up phase.
  • the pull-down module 3 is used to pull down the signal output from the output terminal OUT2 of the shift register and the signal output from the output signal OUT1.
  • the transfer signal output terminal OUT1 is used to output an inter-stage shift transfer signal between the shift register of the first stage and the shift register of the previous stage and the shift register of the next stage.
  • the denoising module 4 is for denoising the shift transmission signal outputted by the transmission signal output terminal OUT1 in the pull-down phase.
  • the voltage coupling effect of the first capacitor C1 can be prevented from causing the shift transmission signal outputted by the shift register transmission signal output terminal OUT1 to be generated.
  • Noise such as spikes, so that the inter-stage shift transfer signal of the shift register is more stable, and the noise of the shift register circuit can be reduced, so that the signal outputted from the output terminal OUT2 of the shift register is more stable.
  • the denoising module 4 includes a ninth transistor M9.
  • the gate of the ninth transistor M9 and the first pole are connected to the second end of the first capacitor C1, and the second pole of the ninth transistor M9.
  • the connection signal output terminal OUT1 and the pull-down module 3 are connected.
  • the path of OUT1 further avoids the influence of the coupling effect of the first capacitor C1 on the transmitted signal outputted by the signal output terminal OUT1, ensuring that the transmitted signal does not generate noise such as spikes, and finally ensures the shift register shift signal between the shift registers. Stability.
  • the pull-up module 2 includes a first sub-module 21 and a second sub-module 22, and the first sub-module 21 and the second sub-module 22 are connected to the pull-up node PU, and the first sub-module 21 is also connected to the first clock signal terminal CLK and the signal output terminal OUT1, and the second sub-module 22 is also connected to the first power source VDD and the output terminal OUT2 of the shift register.
  • the first sub-module 21 is configured to pull up the signal VZ outputted from the signal output terminal OUT1.
  • the second sub-module 22 is used for the shift register The signal Gn outputted from the output terminal OUT2 is pulled up.
  • the pull-down module 3 includes a third sub-module 31 and a fourth sub-module 32.
  • the third sub-module 31 and the fourth sub-module 32 are connected to the pull-down node PD, and the third sub-module 31 is further connected to the second clock signal end. CLKB and the first power supply VDD, the fourth sub-module 32 is further connected to the second power source VSS, the output terminal OUT2, the second pole of the ninth transistor M9 and the signal output terminal OUT1, and the fourth sub-module 32 is also connected to the first sub-module 21 and the second sub-module 22 are connected to the pull-up node PU.
  • the third sub-module 31 is used to control the voltage of the pull-down node PD during the pull-down phase.
  • the fourth sub-module 32 is configured to pull down the signal Gn outputted from the output terminal OUT2 of the shift register and the signal VZ outputted from the signal output terminal OUT1.
  • the first sub-module 21 includes a fourth transistor M4, the gate of the fourth transistor M4 is connected to the pull-up node PU and the first end of the first capacitor C1, and the first pole of the fourth transistor M4 is connected to the first clock.
  • the signal terminal CLK, the second electrode of the fourth transistor M4 is connected to the signal output terminal OUT1, the second electrode of the ninth transistor M9, and the fourth sub-module 32.
  • the second sub-module 22 includes a third transistor M3, the gate of the third transistor M3 is connected to the pull-up node PU, and the first pole of the third transistor M3 is connected to the first power supply VDD and the third sub-module 31, and the third transistor M3
  • the diode is connected to the output terminal OUT2 of the shift register and the fourth sub-module 32.
  • the first power source VDD is a DC power source
  • the third transistor M3 is controlled by the DC power source to pull up the signal Gn outputted from the output terminal OUT2 of the shift register, and the third transistor M3 is shifted by using the AC power source in the prior art.
  • the signal Gn outputted from the output terminal OUT2 of the register is pulled up, which not only reduces the power consumption of the shift register, but also enables the signal Gn outputted from the output terminal OUT2 of the shift register to be unaffected by the capacitive coupling effect, that is, shifting
  • the output terminal OUT2 of the register outputs a more stable signal Gn, which reduces the noise of the shift register.
  • the third sub-module 31 includes a fifth transistor M5 and a sixth transistor M6.
  • the gate of the fifth transistor M5 and the first pole are connected to the second clock signal terminal CLKB, the second pole of the fifth transistor M5 is connected to the gate of the sixth transistor M6; the first pole of the sixth transistor M6 is connected to the first power source VDD and The first pole of the third transistor M3 and the second pole of the sixth transistor M6 are connected to the pull-down node PD.
  • the fourth sub-module 32 includes a seventh transistor M7, an eighth transistor M8, a tenth transistor M10, and an eleventh transistor M11.
  • the gate of the tenth transistor M10 and the first pole of the seventh transistor M7 are both connected to the pull-up node PU; the first pole of the tenth transistor M10, the gate of the seventh transistor M7, the gate of the eighth transistor M8, and the tenth
  • the gate of one transistor M11 is connected to pull down a node PD; a second pole of the tenth transistor M10, a second pole of the seventh transistor M7, a second pole of the eighth transistor M8, and a second pole of the eleventh transistor M11 are all connected to the second power source VSS; the eighth transistor M8
  • the first pole is connected to the second pole of the ninth transistor M9, the second pole of the fourth transistor M4, and the transfer signal output terminal OUT1; the first pole of the eleventh transistor M11 is connected to the second pole of the third transistor M3 and is shifted
  • the second power source VSS is a DC power source, and the voltage of the first power source VDD is higher than the voltage of the second power source VSS.
  • the second clock signal and the second power source VSS can jointly control the third sub-module 31 and the fourth sub-module 32 to stably pull down the signal Gn outputted by the shift register and the transfer signal VZ outputted by the shift register, thereby effectively reducing the shift register. Output noise.
  • the first clock signal outputted by the first clock signal terminal CLK and the second clock signal outputted by the second clock signal terminal CLKB are opposite, or the phases are 180 degrees out of phase.
  • the trigger reset module 1 includes a trigger submodule 11 and a reset submodule 12.
  • the trigger sub-module 11 and the reset sub-module 12 are connected to the pull-up node PU, the trigger sub-module 11 is connected to the start signal input terminal and the third power source VDF, and the reset sub-module 12 is connected to the reset signal input terminal and the fourth power source VDB.
  • the trigger sub-module 11 is configured to trigger the pull-up module 2 according to the start signal INPUT input from the start signal input terminal.
  • the reset sub-module 12 is configured to reset the pull-up module 2 according to the reset signal RESET input by the reset signal input terminal.
  • the trigger sub-module 11 includes a first transistor M1, the gate of the first transistor M1 is connected to the start signal input end, the first pole of the first transistor M1 is connected to the third power source VDF, and the second transistor M1 is second. The pole is connected to the pull-up node PU.
  • the reset sub-module 12 includes a second transistor M2, the gate of the second transistor M2 is connected to the reset signal input terminal, the first pole of the second transistor M2 is connected to the pull-up node PU, and the second pole of the second transistor M2 is connected to the fourth power supply VDB. .
  • the third power source VDF and the fourth power source VDB are both DC power sources, and the voltage of the third power source VDF is higher than the voltage of the fourth power source VDB.
  • the start signal INPUT and the third power source VDF can jointly pull up the voltage of the pull-up node PU, so that the output terminal OUT2 of the shift register outputs the gate drive signal Gn, and the output signal output terminal OUT1 of the shift register is output. Pass the signal VZ.
  • the reset signal RESET and the fourth power supply VDB can jointly pull down the voltage of the pull-up node PU, so that the output terminal OUT2 of the shift register no longer outputs the gate drive signal Gn, and the output signal output terminal OUT1 of the shift register is not The transfer signal VZ is output again.
  • the embodiment further provides a driving method of the shift register, and the driving method specifically includes the following five stages.
  • the present embodiment will be described with reference to FIG. 6. The various stages of the driving method of the example.
  • the trigger reset module 1 triggers the pull-up module 2 according to the start signal INPUT input from the start signal input terminal, and the pull-up module 2 pulls up the signal Gn outputted from the output terminal OUT2 of the shift register.
  • the start signal INPUT is at a high level
  • the signal output from the first clock signal terminal CLK is at a low level
  • the signal output from the second clock signal terminal CLKB is at a high level.
  • the first transistor M1 is turned on to charge the pull-up node PU; as the voltage of the pull-up node PU increases during the charging process, the third transistor M3 is in a semi-conductance In the on state, the output terminal OUT2 of the shift register has a certain output function, and the fourth transistor M4 is also in a semi-conducting state, and the output terminal OUT1 of the shift register is at a low level; during charging of the pull-up node PU, The ninth transistor M9 is turned on. Since the signal output from the second clock signal terminal CLKB is at a high level, the fifth transistor M5 and the sixth transistor M6 are turned on to charge the pull-down node PD.
  • the tenth transistor M10 since the voltage of the pull-up node PU is constantly rising during charging, the tenth transistor M10 is turned on, and the voltage of the pull-down node PD is pulled low by the second power source VSS.
  • the channels of the sixth transistor M6 and the tenth transistor M10 it is possible to cause the voltage of the pull-down node PD to be pulled low when the sixth transistor M6 and the tenth transistor M10 are simultaneously turned on.
  • the voltage of the pull-down node PD is pulled low, so that the seventh transistor M7, the eighth transistor M8, and the eleventh transistor M11 in the pull-down module 3 are kept off, that is, The pull-down module 3 does not work at this stage, so that the signal Gn outputted by the output terminal OUT2 of the shift register is not affected by the circuit in the pull-down module 3 in the initial stage of the pull-up, thereby ensuring the output terminal OUT2 of the shift register. Stable output.
  • the first capacitor C1 raises the voltage of the pull-up node PU at this stage, and the pull-up module 2 continues to pull up the signal outputted by the output terminal OUT2 of the shift register, and at the same time, the pull-up module 2 transmits the signal.
  • the signal output from the output is Gn pulled up.
  • the start signal INPUT is low
  • the signal outputted by the first clock signal terminal CLK is high level
  • the signal outputted by the second clock signal terminal CLKB is low level.
  • the fourth transistor M4 since the voltage of the pull-up node PU is at a high level, the fourth transistor M4 is turned on, and since the signal output from the first clock signal terminal CLK is at a high level, the transfer signal VZ output from the output signal output terminal OUT1 is high. Level, the transfer signal VZ can function to shift the shift between the shift register of the first stage and the shift register of the previous stage and the shift register of the next stage. At this time, the potential of the pull-up node PU continues to rise by the bootstrap effect of the first capacitor C1, and the third transistor M3 is finished.
  • the signal Gn outputted from the output terminal OUT2 of the shift register is at a high level (the output signal Gn of the high level provides a gate driving signal for one scanning line in the display device).
  • the ninth transistor M9 remains turned on.
  • the tenth transistor M10 continues to conduct, causing the pull-down node PD to maintain a low level.
  • the level of the pull-down node PD is kept low, so that the seventh transistor M7, the eighth transistor M8, and the eleventh transistor M11 in the pull-down module 3 are both maintained.
  • the cut-off module 3 does not work at this stage, so that the signal Gn outputted from the output terminal OUT2 of the shift register is not affected by the circuit in the pull-down module 3 in the initial stage of the pull-up, thereby ensuring the shift register.
  • the output terminal OUT2 is stable.
  • the trigger reset module 1 resets the pull-up module 2 according to the reset signal RESET input from the reset signal input terminal, and the pull-down module 3 outputs the signal Gn outputted from the output terminal OUT2 of the shift register and the signal output from the output signal output terminal OUT1.
  • VZ pulls down.
  • the denoising module 4 denoises the transfer signal VZ output from the transfer signal output terminal OUT1.
  • the start signal INPUT is kept low, the signal outputted by the first clock signal terminal CLK is low level, the signal outputted by the second clock signal terminal CLKB is high level, and the reset signal RESET is high level.
  • the reset signal RESET is at a high level
  • the second transistor M2 is turned on, and the fourth power source VDB pulls down the voltage of the pull-up node PU, so that the third transistor M3 and the tenth transistor M10 are turned off.
  • the fifth transistor M5 and the sixth transistor M6 are turned on, and the pull-down node PD becomes a high level; then the seventh transistor M7, the eighth transistor M8, and the The eleven transistor M11 is turned on; the seventh transistor M7 further pulls down the voltage of the pull-up node PU, and the eighth transistor M8 pulls down the transfer signal VZ outputted from the signal output terminal OUT1 to a low level, and the eleventh transistor M11 is shifted.
  • the signal Gn output from the bit register output terminal OUT2 is pulled down to a low level.
  • the voltage of the pull-up node PU changes from a high level to a low level, the voltage of the first end of the first capacitor C1 decreases, and according to the charge and discharge principle of the capacitor, the voltage of the second end of the first capacitor C1 Also decreasing, thereby turning off the ninth transistor M9; after the ninth transistor M9 is turned off, the coupling effect generated when the first capacitor C1 jumps at the pull-up node PU can be cut off to the path of the signal output terminal OUT1, thereby avoiding the first
  • the coupling effect of the capacitor C1 causes the transmission signal VZ outputted from the signal output terminal OUT1 to generate noise such as spikes, thereby ensuring the stability of the shift register shift transfer signal VZ.
  • the start signal INPUT is kept low, the signal outputted by the first clock signal terminal CLK is high level, and the signal outputted by the second clock signal terminal CLKB is low level, the reset signal is RESET is low.
  • the fifth transistor M5 since the gate of the fifth transistor M5 is connected to the first electrode, the fifth transistor M5 has a latching effect, and the sixth transistor M6 remains turned on. At this time, the pull-down node PD is still at a high level.
  • the seventh transistor M7, the eighth transistor M8, and the eleventh transistor M11 are kept turned on, so that the signal Gn outputted from the output terminal OUT2 of the shift register and the transfer signal VZ outputted from the output terminal OUT1 are kept at a low level.
  • the start signal INPUT is kept low, the signal outputted by the first clock signal terminal CLK is low level, the signal outputted by the second clock signal terminal CLKB is high level, and the reset signal RESET is low level. Since the signal output from the second clock signal terminal CLKB is at a high level, the fifth transistor M5 and the sixth transistor M6 remain turned on; the pull-down node PD is at a high level, and the seventh transistor M7, the eighth transistor M8, and the eleventh transistor M11 remains turned on, so that the signal Gn outputted from the output terminal OUT2 of the shift register and the transfer signal VZ outputted from the output terminal OUT1 are kept at a low level.
  • the second clock signal and the first power supply VDD can jointly control the shift register to obtain a more stable pull-down control signal, thereby effectively reducing the output noise of the shift register.
  • the shift register of the present embodiment repeats the operations of the fourth phase and the fifth phase until the start signal input terminal INPUT is input again.
  • the shift register can be made to provide a more stable output signal Gn and a transfer signal VZ.
  • the voltage of the third power source VDF may also be lower than the voltage of the fourth power source VDB.
  • the start signal INPUT is input at the reset signal input end, and the reset signal is input at the start signal input end. RESET, this enables reverse scanning of the cascaded shift register circuit, ie the cascaded shift register circuit scans from the last row of the display panel (ie the tail row) until the end of the scan to the first row (ie the first row) .
  • the denoising module 4 includes a ninth transistor M9, and the first pole of the ninth transistor M9 is connected to the first capacitor C1. At the second end, the gate and the second pole of the ninth transistor M9 are connected to the signal output terminal OUT1 and the pull-down module 3.
  • the ninth transistor M9 When the voltage of the signal output terminal OUT1 transitions from a high level to a low level, the ninth transistor M9 is turned off, thereby cutting off the coupling effect of the first capacitor C1 to the path of the output signal output terminal OUT1, thereby avoiding the first
  • the coupling effect of the capacitor C1 affects the transfer signal outputted by the signal output terminal OUT1, ensuring that the transmitted signal does not generate noise such as spikes, and finally ensures the stability of the shift register signal between the shift register stages.
  • the denoising module 4 of the shift register in this embodiment also denoises the transfer signal VZ outputted from the transfer signal output terminal OUT1 in the third stage of the driving method, but the specific denoising process is different from that of the first embodiment.
  • the denoising process of the denoising module 4 in this embodiment is specifically described based on the above circuit connection of the denoising module 4 in this embodiment.
  • the start signal INPUT is kept low, the signal outputted by the first clock signal terminal CLK is low level, the signal outputted by the second clock signal terminal CLKB is high level, and the reset signal RESET is high level.
  • the reset signal RESET is at a high level
  • the second transistor M2 is turned on, and the fourth power source VDB pulls down the voltage of the pull-up node PU, so that the third transistor M3 and the tenth transistor M10 are turned off.
  • the fifth transistor M5 and the sixth transistor M6 are turned on, and the pull-down node PD becomes a high level; then the seventh transistor M7, the eighth transistor M8, and the The eleven transistor M11 is turned on; the seventh transistor M7 further pulls down the voltage of the pull-up node PU, and the eighth transistor M8 pulls down the transfer signal VZ outputted from the output signal output terminal OUT1 to a low level, thereby turning off the ninth transistor M9.
  • the coupling effect generated when the first capacitor C1 jumps at the pull-up node PU can be cut off to the path of the signal output terminal OUT1, thereby avoiding the coupling effect of the first capacitor C1 and transmitting the signal output end.
  • the transfer signal VZ of the OUT1 output generates noise such as spikes, thereby ensuring the stability of the shift register shift transfer signal VZ.
  • the shift register provided in Embodiment 1-2 can prevent the first capacitor by setting a denoising module to cause the shift register to jump when the voltage of the pull-up node is changed.
  • the coupling effect causes the transfer signal outputted by the shift register to output a signal such as spikes, which makes the interstage shift transfer signal of the shift register more stable, and also reduces the noise of the shift register circuit, thereby shifting The output from the output of the register is more stable.
  • the embodiment provides a gate driving circuit, as shown in FIG. 9, comprising: a multi-stage shift register, the shift register adopting the shift register in Embodiment 1 or 2, and the transfer signal output of the shift register of the present stage
  • the terminal OUT1 is connected to the reset signal input terminal RESET of the upper stage shift register and the start signal input terminal INPUT of the next stage shift register.
  • the noise of the gate driving circuit is reduced, and the gate driving signal outputted by the gate driving circuit is made more stable.
  • the embodiment provides a display device including the gate driving circuit in Embodiment 3.
  • the display of the display device is made more stable, thereby improving the display quality of the display device.

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Abstract

一种移位寄存器及其驱动方法、栅极驱动电路和显示装置。该移位寄存器包括触发复位模块、上拉模块、第一电容和下拉模块，还包括去噪模块。上拉模块用于对移位寄存器的输出端输出的信号和传递信号输出端输出的信号进行上拉；下拉模块，用于对移位寄存器的输出端输出的信号和传递信号输出端输出的信号进行下拉；去噪模块，用于在下拉阶段切断所述传递信号输出端与所述第一电容的第二端的连接通路。该移位寄存器通过设置去噪模块，使其在上拉节点的电压发生跳变时，能防止电容的耦合效应使传递信号输出端输出的传递信号产生尖刺等噪声，从而使移位寄存器的移位传递信号更加稳定，进而使移位寄存器输出的信号更加稳定。

Description

移位寄存器及其驱动方法、栅极驱动电路和显示装置 技术领域
本发明涉及显示技术领域，具体地，涉及一种移位寄存器及其驱动方法、栅极驱动电路和显示装置。
背景技术
高分辨率、窄边框已经成为平板显示技术的发展潮流，而在显示面板上集成栅极驱动电路是实现高分辨率、窄边框显示最重要的解决办法。
栅极驱动电路由多级移位寄存器依次级联组成，图1为现有技术提供的移位寄存器的电路图，该移位寄存器包括：触发晶体管T100、复位晶体管T200、第一上拉晶体管T300、第二上拉晶体管T400、自举电容C100和下拉模块。第一上拉晶体管T300用于上拉移位寄存器的输出端输出的信号，第二上拉晶体管T400用于上拉移位寄存器的传递信号输出端输出的信号。移位寄存器的传递信号输出端为本级移位寄存器与上一级移位寄存器和下一级移位寄存器级联的级联端。第一节点PU1为自举电容C100和第二上拉晶体管T400的栅极的连接点。STV为与触发晶体管T100的栅极连接的起始信号端输入的起始信号，RESET为复位晶体管T200的栅极连接的复位信号端输入的复位信号，CLK为与第二上拉晶体管T400的漏极连接的时钟信号端输入的时钟信号，OUTPUT为移位寄存器的输出端输出的信号，VZ为移位寄存器的传递信号输出端输出的传递信号，VGH表示高电平的电压，VGL表示低电平的电压。
如图2所示，在移位寄存器的上拉阶段，STV为高电平(RESET为低电平)，触发晶体管T100导通，VGH对自举电容C100进行充电，将第一节点PU1的电压上拉为高电平；第二上拉晶体管T400导通，CLK为高电平，对移位寄存器的传递信号输出端输出的信号进行上拉，使移位寄存器的传递信号输出端输出高电平的传递信号。在移位寄存器的下拉阶段，RESET为高电平(STV为低电平)，下拉模块将第一节点PU1的高电平下拉为低电平，同时将移位寄存器的传递信号输出端输出的传递信号从高电平下拉为低电平。
在移位寄存器的下拉阶段，第一节点PU1的电压发生跳变，即由高电平跳变为低电平，自举电容C100的电压耦合效应会直接导致移位寄存器的传递 信号输出端输出的传递信号VZ产生尖刺，严重影响移位寄存器移位传递的稳定性，移位寄存器移位传递的稳定性降低会使移位寄存器电路的噪声提高，从而影响移位寄存器的输出端输出信号的稳定性。
发明内容
本发明针对现有技术中存在的上述技术问题，提供一种移位寄存器及其驱动方法、栅极驱动电路和显示装置。该移位寄存器通过设置去噪模块，使其在上拉节点的电压发生跳变时，能防止电容的耦合效应使移位寄存器传递信号输出端输出的传递信号产生尖刺等噪声，从而使移位寄存器的移位传递信号更加稳定，进而使移位寄存器输出的信号更加稳定。
本发明提供一种移位寄存器，包括上拉模块、第一电容和下拉模块，其特征在于，还包括去噪模块。所述去噪模块的第一端连接所述第一电容的第二端，所述去噪模块的第二端连接传递信号输出端；其中，所述上拉模块与所述移位寄存器的输出端和所述传递信号输出端连接并且与所述第一电容的第一端连接，并且用于在所述第一电容的第一端的控制下对所述移位寄存器的输出端输出的信号和所述传递信号输出端输出的信号上拉，所述上拉模块与所述第一电容的第一端的连接点为上拉节点；所述下拉模块与所述移位寄存器的输出端和所述传递信号输出端连接并且与所述第一电容的第一端连接，并且用于在下拉阶段对所述移位寄存器的输出端输出的信号和所述传递信号输出端输出的信号下拉；所述去噪模块用于在下拉阶段切断所述传递信号输出端与所述第一电容的第二端的连接通路。
优选地，所述去噪模块包括第九晶体管，所述第九晶体管的栅极和第一极连接所述第一电容的第二端，所述第九晶体管的第二极连接所述传递信号输出端。所述第九晶体管为N型晶体管，其第一极为漏极，其第二极为源极。
优选地，所述去噪模块包括第九晶体管，所述第九晶体管第一极连接所述第一电容的第二端，所述第九晶体管的栅极和第二极连接所述传递信号输出端。所述第九晶体管为P型晶体管，其第一极为源极，其第二极为漏极。
优选地，所述上拉模块包括第一子模块和第二子模块，所述第一子模块和所述第二子模块连接于所述上拉节点，所述第一子模块还连接第一时钟信号端和所述传递信号输出端，所述第二子模块还连接第一电源和所述移位寄存器的输出端；所述第一子模块用于对所述传递信号输出端输出的信号进行 上拉；所述第二子模块用于对所述移位寄存器的输出端输出的信号进行上拉。
优选地，所述下拉模块包括第三子模块和第四子模块，所述第三子模块和所述第四子模块连接于下拉节点，所述第三子模块连接第二时钟信号端和所述第一电源，所述第四子模块连接第二电源、所述输出端、所述第九晶体管的第二极和所述传递信号输出端，且所述第四子模块与所述第一子模块和所述第二子模块连接于所述上拉节点；所述第三子模块用于在下拉阶段控制所述下拉节点的电位；所述第四子模块用于在下拉阶段对所述移位寄存器的输出端输出的信号和所述传递信号输出端输出的信号进行下拉。
优选地，所述第一子模块包括第四晶体管，所述第四晶体管的栅极连接所述上拉节点，所述第四晶体管的第一极连接所述第一时钟信号端，所述第四晶体管的第二极连接所述传递信号输出端；所述第二子模块包括第三晶体管，所述第三晶体管的栅极连接所述上拉节点，所述第三晶体管的第一极连接所述第一电源，所述第三晶体管的第二极连接所述移位寄存器的输出端。
优选地，所述第三子模块包括第五晶体管和第六晶体管，所述第五晶体管的栅极和第一极连接所述第二时钟信号端，所述第五晶体管的第二极连接所述第六晶体管的栅极；所述第六晶体管的第一极连接所述第一电源和所述第三晶体管的第一极，所述第六晶体管的第二极连接所述下拉节点；所述第四子模块包括第七晶体管、第八晶体管、第十晶体管和第十一晶体管，所述第十晶体管的栅极和所述第七晶体管的第一极均连接所述上拉节点；所述第十晶体管的第一极、所述第七晶体管的栅极、所述第八晶体管的栅极和所述第十一晶体管的栅极均连接所述下拉节点；所述第十晶体管的第二极、所述第七晶体管的第二极、所述第八晶体管的第二极和所述第十一晶体管的第二极均连接所述第二电源；所述第八晶体管的第一极连接所述第九晶体管的第二极、所述第四晶体管的第二极和所述传递信号输出端；所述第十一晶体管的第一极连接所述第三晶体管的第二极和所述移位寄存器的输出端。
优选地，所述第一时钟信号端输出的第一时钟信号和所述第二时钟信号端输出的第二时钟信号相位相差180度。
优选地，所述移位寄存器还包括触发复位模块，用于根据起始信号输入端输入的起始信号和复位信号输入端输入的复位信号对所述上拉节点进行充电和放电。所述触发复位模块包括触发子模块和复位子模块，所述触发子模块和所述复位子模块连接于所述上拉节点，所述触发子模块连接第三电源， 所述复位子模块连接第四电源；所述触发子模块用于根据所述起始信号输入端输入的起始信号对所述上拉节点进行充电；所述复位子模块用于根据所述复位信号输入端输入的复位信号对所述上拉节点进行放电。
优选地，所述触发子模块包括第一晶体管，所述第一晶体管的栅极连接所述起始信号输入端，所述第一晶体管的第一极连接所述第三电源，所述第一晶体管的第二极连接所述上拉节点；所述复位子模块包括第二晶体管，所述第二晶体管的栅极连接所述复位信号输入端，所述第二晶体管的第一极连接所述上拉节点，所述第二晶体管的第二极连接所述第四电源。
优选地，所述第一到第八晶体管以及第十和第十一晶体管为N型晶体管，其第一极为漏极，其第二极为源极。
本发明还提供一种栅极驱动电路，包括：多级移位寄存器，所述移位寄存器采用上述移位寄存器，本级所述移位寄存器的传递信号输出端与上一级所述移位寄存器的复位信号输入端和下一级所述移位寄存器的起始信号输入端连接。
本发明还提供一种显示装置，包括上述栅极驱动电路。
本发明还提供一种移位寄存器的驱动方法，包括：第一阶段，所述第一电容被充电，所述上拉模块在所述上拉节点的控制下对所述移位寄存器的输出端输出的信号上拉；第二阶段，所述第一电容在该阶段提升上拉节点的电压，所述上拉模块继续对所述移位寄存器的输出端输出的信号上拉，并且所述上拉模块对传递信号输出端输出的信号上拉；第三阶段，所述第一电容被放电，所述下拉模块对所述移位寄存器的输出端输出的信号和所述传递信号输出端输出的信号下拉，并且所述去噪模块切断所述传递信号输出端与所述第一电容的第二端的连接通路。
本发明的有益效果：本发明所提供的移位寄存器和栅极驱动电路，通过设置去噪模块，使该移位寄存器在上拉节点的电压发生跳变时，能防止第一电容的耦合效应使移位寄存器传递信号输出端输出的传递信号产生尖刺等噪声，从而使移位寄存器的级间移位传递信号更加稳定，同时还能降低移位寄存器电路的噪声，进而使移位寄存器的输出端输出的信号更加稳定。
本发明所提供的显示装置，通过采用上述栅极驱动电路，使该显示装置的显示更加稳定，从而提升了该显示装置的显示质量。
附图说明
通过结合附图对本发明实施例进行更详细的描述，本发明的上述以及其它目的、特征和优势将变得更加明显。附图用来提供对本发明实施例的进一步理解，并且构成说明书的一部分，与本发明实施例一起用于解释本发明，并不构成对本发明的限制。在附图中，相同的参考标号通常代表相同部件或步骤。
图1为现有技术中移位寄存器的电路原理图；
图2为图1中移位寄存器的时序图；
图3为本发明实施例1中移位寄存器的电路原理图；
图4为图3中的去噪模块为N型晶体管的电路原理图；
图5为图3中移位寄存器的电路图；
图6为图5中移位寄存器的驱动时序图；
图7为本发明实施例2中去噪模块为P型晶体管的电路原理图；
图8为本发明实施例2中移位寄存器的电路图；
图9为本发明实施例3中栅极驱动电路的级联示意图。
具体实施方式
为了使得本发明实施例的目的、技术方案和优点更为明显，下面将参照附图详细描述本发明的示例实施例。显然，所描述的示例实施例仅仅是本发明的一部分实施例，而不是本发明的全部实施例，本领域技术人员在没有付出创造性劳动的情况下所得到的所有其它实施例都应落入本发明的保护范围之内。
这里，需要注意的是，在附图中，将相同的附图标记赋予基本上具有相同或类似结构和功能的组成部分，并且将省略关于它们的重复描述。
下面，将结合附图和具体实施方式对本发明所提供的一种移位寄存器及其驱动方法、栅极驱动电路和显示装置作进一步详细描述。
实施例1：
本实施例提供一种移位寄存器，如图3所示，包括触发复位模块1、上拉模块2、第一电容C1和下拉模块3，并且还包括去噪模块4。
如图3所示，触发复位模块1、上拉模块2、下拉模块3和第一电容C1 的第一端连接于上拉节点PU；去噪模块4的第一端连接第一电容C1的第二端，去噪模块4的第二端连接下拉模块3和传递信号输出端OUT1；上拉模块2和下拉模块3均与移位寄存器的输出端OUT2连接；上拉模块2和下拉模块3还与传递信号输出端OUT1连接。
触发复位模块1用于根据起始信号输入端输入的起始信号INPUT和复位信号输入端输入的复位信号RESET对上拉节点PU进行充电和放电，从而实现对上拉模块2触发或复位。上拉模块2用于对移位寄存器的输出端OUT2输出的信号和传递信号输出端OUT1输出的信号进行上拉。第一电容C1用于在上拉阶段提升上拉节点PU的电压。下拉模块3用于对移位寄存器的输出端OUT2输出的信号和传递信号输出端OUT1输出的信号进行下拉。传递信号输出端OUT1用于输出本级移位寄存器与上一级移位寄存器和下一级移位寄存器之间的级间移位传递信号。去噪模块4用于在下拉阶段对传递信号输出端OUT1输出的移位传递信号去噪。
通过设置去噪模块4，使该移位寄存器在上拉节点PU的电压发生跳变时，能防止第一电容C1的电压耦合效应使移位寄存器传递信号输出端OUT1输出的移位传递信号产生尖刺等噪声，从而使移位寄存器的级间移位传递信号更加稳定，同时还能降低移位寄存器电路的噪声，使移位寄存器的输出端OUT2输出的信号更加稳定。
本实施例中，如图4所示，去噪模块4包括第九晶体管M9，第九晶体管M9的栅极和第一极连接第一电容C1的第二端，第九晶体管M9的第二极连接传递信号输出端OUT1和下拉模块3。当连接第一电容C1的第一端的上拉节点PU的电压由高电平向低电平跳变时，第九晶体管M9截止，从而切断了第一电容C1的耦合效应到达传递信号输出端OUT1的路径，进而避免了第一电容C1的耦合效应对传递信号输出端OUT1输出的传递信号的影响，确保传递信号不会产生尖刺等噪声，最终确保了移位寄存器级间移位传递信号的稳定性。
本实施例中，如图5所示，上拉模块2包括第一子模块21和第二子模块22，第一子模块21和第二子模块22连接于上拉节点PU，第一子模块21还连接第一时钟信号端CLK和传递信号输出端OUT1，第二子模块22还连接第一电源VDD和移位寄存器的输出端OUT2。第一子模块21用于对传递信号输出端OUT1输出的信号VZ进行上拉。第二子模块22用于对移位寄存器 的输出端OUT2输出的信号Gn进行上拉。
本实施例中，下拉模块3包括第三子模块31和第四子模块32，第三子模块31和第四子模块32连接于下拉节点PD，第三子模块31还连接第二时钟信号端CLKB和第一电源VDD，第四子模块32还连接第二电源VSS、输出端OUT2、第九晶体管M9的第二极和传递信号输出端OUT1，并且第四子模块32还与第一子模块21和第二子模块22连接于上拉节点PU。第三子模块31用于在下拉阶段控制下拉节点PD的电压。第四子模块32用于对移位寄存器的输出端OUT2输出的信号Gn和传递信号输出端OUT1输出的信号VZ进行下拉。
本实施例中，第一子模块21包括第四晶体管M4，第四晶体管M4的栅极连接上拉节点PU和第一电容C1的第一端，第四晶体管M4的第一极连接第一时钟信号端CLK，第四晶体管M4的第二极连接传递信号输出端OUT1、第九晶体管M9的第二极和第四子模块32。第二子模块22包括第三晶体管M3，第三晶体管M3的栅极连接上拉节点PU，第三晶体管M3的第一极连接第一电源VDD和第三子模块31，第三晶体管M3的第二极连接移位寄存器的输出端OUT2和第四子模块32。
第一电源VDD为直流电源，由直流电源控制第三晶体管M3对移位寄存器的输出端OUT2输出的信号Gn进行上拉，相比于现有技术中采用交流电源控制第三晶体管M3对移位寄存器的输出端OUT2输出的信号Gn进行上拉，不仅降低了移位寄存器的功耗，而且能使移位寄存器的输出端OUT2输出的信号Gn不受电容耦合效应的影响，即能使移位寄存器的输出端OUT2输出更加稳定的信号Gn，降低移位寄存器的噪声。
本实施例中，第三子模块31包括第五晶体管M5和第六晶体管M6。第五晶体管M5的栅极和第一极连接第二时钟信号端CLKB，第五晶体管M5的第二极连接第六晶体管M6的栅极；第六晶体管M6的第一极连接第一电源VDD和第三晶体管M3的第一极，第六晶体管M6的第二极连接下拉节点PD。
本实施例中，第四子模块32包括第七晶体管M7、第八晶体管M8、第十晶体管M10和第十一晶体管M11。第十晶体管M10的栅极和第七晶体管M7的第一极均连接上拉节点PU；第十晶体管M10的第一极、第七晶体管M7的栅极、第八晶体管M8的栅极和第十一晶体管M11的栅极均连接下拉 节点PD；第十晶体管M10的第二极、第七晶体管M7的第二极、第八晶体管M8的第二极和第十一晶体管M11的第二极均连接第二电源VSS；第八晶体管M8的第一极连接第九晶体管M9的第二极、第四晶体管M4的第二极和传递信号输出端OUT1；第十一晶体管M11的第一极连接第三晶体管M3的第二极和移位寄存器的输出端OUT2。
第二电源VSS为直流电源，且第一电源VDD的电压高于第二电源VSS的电压。第二时钟信号和第二电源VSS能够联合控制第三子模块31和第四子模块32对移位寄存器输出的信号Gn和移位寄存器输出的传递信号VZ进行稳定下拉，有效减少移位寄存器的输出噪声。
本实施例中，第一时钟信号端CLK输出的第一时钟信号和第二时钟信号端CLKB输出的第二时钟信号相反，或者相位相差180度。
本实施例中，触发复位模块1包括触发子模块11和复位子模块12。触发子模块11和复位子模块12连接于上拉节点PU，触发子模块11连接起始信号输入端和第三电源VDF，复位子模块12连接复位信号输入端和第四电源VDB。触发子模块11用于根据起始信号输入端输入的起始信号INPUT对上拉模块2进行触发。复位子模块12用于根据复位信号输入端输入的复位信号RESET对上拉模块2进行复位。
本实施例中，触发子模块11包括第一晶体管M1，第一晶体管M1的栅极连接起始信号输入端，第一晶体管M1的第一极连接第三电源VDF，第一晶体管M1的第二极连接上拉节点PU。复位子模块12包括第二晶体管M2，第二晶体管M2的栅极连接复位信号输入端，第二晶体管M2的第一极连接上拉节点PU，第二晶体管M2的第二极连接第四电源VDB。
本实施例中，第三电源VDF和第四电源VDB均为直流电源，且第三电源VDF的电压高于第四电源VDB的电压。起始信号INPUT和第三电源VDF能够联合对上拉节点PU的电压进行上拉，以使移位寄存器的输出端OUT2输出栅极驱动信号Gn，并使移位寄存器的传递信号输出端OUT1输出传递信号VZ。复位信号RESET和第四电源VDB能够联合对上拉节点PU的电压进行下拉，以使移位寄存器的输出端OUT2不再输出栅极驱动信号Gn，并使移位寄存器的传递信号输出端OUT1不再输出传递信号VZ。
基于移位寄存器的上述结构，本实施例还提供一种该移位寄存器的驱动方法，该驱动方法具体包括以下五个阶段。下面，将参考图6来描述本实施 例的驱动方法的各个阶段。
第一阶段，触发复位模块1根据起始信号输入端输入的起始信号INPUT对上拉模块2进行触发，上拉模块2对移位寄存器的输出端OUT2输出的信号Gn进行上拉。
在该阶段，起始信号INPUT为高电平，第一时钟信号端CLK输出的信号为低电平，第二时钟信号端CLKB输出的信号为高电平。
具体地，由于起始信号INPUT为高电平，第一晶体管M1导通，对上拉节点PU充电；随着上拉节点PU的电压在充电过程中不断升高，第三晶体管M3处于半导通状态，移位寄存器的输出端OUT2有一定的输出功能，同时第四晶体管M4也处于半导通状态，移位寄存器的输出端OUT1为低电平；在上拉节点PU充电的过程中，第九晶体管M9导通。由于第二时钟信号端CLKB输出的信号为高电平，第五晶体管M5和第六晶体管M6导通，对下拉节点PD充电。另一方面，因为上拉节点PU的电压在充电过程中不断升高，所以第十晶体管M10导通，并通过第二电源VSS将下拉节点PD的电压拉低。通过合理设计第六晶体管M6和第十晶体管M10的沟道，可以使得在第六晶体管M6和第十晶体管M10同时导通时，下拉节点PD的电压被拉低。
在该第一阶段(即上拉的初始阶段)，下拉节点PD的电压被拉低，能使下拉模块3中的第七晶体管M7、第八晶体管M8和第十一晶体管M11均保持截止，即下拉模块3在该阶段不工作，从而使该移位寄存器的输出端OUT2输出的信号Gn在上拉的初始阶段不会受下拉模块3中电路的影响，进而能够确保移位寄存器的输出端OUT2稳定输出。
第二阶段，第一电容C1在该阶段提升上拉节点PU的电压，上拉模块2继续对移位寄存器的输出端OUT2输出的信号进行上拉，同时，所述上拉模块2对传递信号输出端输出的信号进行Gn上拉。
在该阶段，起始信号INPUT为低电平，第一时钟信号端CLK输出的信号为高电平，第二时钟信号端CLKB输出的信号为低电平。
具体地，由于上拉节点PU的电压为高电平，第四晶体管M4导通，并且由于第一时钟信号端CLK输出的信号为高电平，传递信号输出端OUT1输出的传递信号VZ为高电平，该传递信号VZ能够起到使本级移位寄存器与上一级移位寄存器和下一级移位寄存器之间进行移位传递的功能。此时，通过第一电容C1的自举效应，上拉节点PU的电位继续拉升，第三晶体管M3完 全导通，移位寄存器的输出端OUT2输出的信号Gn为高电平(该高电平的输出信号Gn为显示装置中的一条扫描线提供栅极驱动信号)。同时，第九晶体管M9保持导通。与此同时，第十晶体管M10继续导通，使下拉节点PD维持低电平。同样地，在第二阶段(即继续上拉阶段)使下拉节点PD的电平保持被拉低，能使下拉模块3中的第七晶体管M7、第八晶体管M8和第十一晶体管M11均保持截止，即下拉模块3在该阶段不工作，从而使该移位寄存器的输出端OUT2输出的信号Gn在上拉的初始阶段不会受下拉模块3中电路的影响，进而能够确保移位寄存器的输出端OUT2稳定输出。
第三阶段，触发复位模块1根据复位信号输入端输入的复位信号RESET对上拉模块2进行复位，下拉模块3对移位寄存器的输出端OUT2输出的信号Gn和传递信号输出端OUT1输出的信号VZ进行下拉。此外，在该阶段，去噪模块4对传递信号输出端OUT1输出的传递信号VZ去噪。
在该阶段，起始信号INPUT保持低电平，第一时钟信号端CLK输出的信号为低电平，第二时钟信号端CLKB输出的信号为高电平，复位信号RESET为高电平。
具体地，由于复位信号RESET为高电平，第二晶体管M2导通，第四电源VDB将上拉节点PU的电压拉低，使得第三晶体管M3和第十晶体管M10截止。同时，由于第二时钟信号端CLKB输出的信号为高电平，第五晶体管M5和第六晶体管M6导通，下拉节点PD变为高电平；继而第七晶体管M7、第八晶体管M8和第十一晶体管M11导通；第七晶体管M7将上拉节点PU的电压进一步拉低，第八晶体管M8将传递信号输出端OUT1输出的传递信号VZ下拉为低电平，第十一晶体管M11将移位寄存器输出端OUT2输出的信号Gn下拉为低电平。
在该阶段，在上拉节点PU的电压由高电平跳变为低电平时，第一电容C1的第一端的电压降低，根据电容的充放电原理，第一电容C1的第二端的电压也降低，从而使第九晶体管M9截止；第九晶体管M9截止后，能够切断第一电容C1在上拉节点PU跳变时产生的耦合效应到达传递信号输出端OUT1的路径，从而能够避免第一电容C1的耦合效应使传递信号输出端OUT1输出的传递信号VZ产生尖刺等噪声，进而确保了移位寄存器移位传递信号VZ的稳定性。
至此，该移位寄存器输出栅极驱动信号的过程结束。此后，在除该移位 寄存器以外的其他移位寄存器输出栅极驱动信号的工作过程中，只需要保持该移位寄存器的输出端OUT2和传递信号输出端OUT1持续输出低电平信号即可。保持该移位寄存器的输出端OUT2和传递信号输出端OUT1持续输出低电平信号的过程具体为：
在紧接着第三阶段的第四阶段，起始信号INPUT保持低电平，第一时钟信号端CLK输出的信号为高电平，第二时钟信号端CLKB输出的信号为低电平，复位信号RESET为低电平。
在第四阶段中，由于第五晶体管M5的栅极与第一极连接，使第五晶体管M5具有锁存的作用，第六晶体管M6保持导通，此时，下拉节点PD仍为高电平，第七晶体管M7、第八晶体管M8和第十一晶体管M11保持导通，使移位寄存器的输出端OUT2输出的信号Gn和传递信号输出端OUT1输出的传递信号VZ均保持低电平。
在第五阶段，起始信号INPUT保持低电平，第一时钟信号端CLK输出的信号为低电平，第二时钟信号端CLKB输出的信号为高电平，复位信号RESET为低电平。由于第二时钟信号端CLKB输出的信号为高电平，第五晶体管M5和第六晶体管M6保持导通；下拉节点PD为高电平，第七晶体管M7、第八晶体管M8和第十一晶体管M11保持导通，使移位寄存器的输出端OUT2输出的信号Gn和传递信号输出端OUT1输出的传递信号VZ均保持低电平。
在第四阶段和第五阶段，第二时钟信号和第一电源VDD能够联合控制移位寄存器获得更加稳定的下拉控制信号，从而有效减少移位寄存器的输出噪声。
此后，本实施例的移位寄存器重复第四阶段和第五阶段的操作，直至起始信号输入端再次输入起始信号INPUT。
通过顺序完成上述阶段使移位寄存器完成移位寄存功能，能够使移位寄存器提供更加稳定的输出信号Gn和传递信号VZ。
需要说明的是，本实施例中，第三电源VDF的电压也可以低于第四电源VDB的电压，这时，在复位信号输入端输入起始信号INPUT，在起始信号输入端输入复位信号RESET，如此能实现级联的移位寄存器电路的反向扫描，即级联的移位寄存器电路从显示面板的最后一行(即尾行)开始扫描，直至扫描至第一行(即首行)结束。
实施例2：
本实施例提供一种移位寄存器，与实施例1不同的是，如图7和图8所示，去噪模块4包括第九晶体管M9，第九晶体管M9的第一极连接第一电容C1的第二端，第九晶体管M9的栅极和第二极连接传递信号输出端OUT1和下拉模块3。
当传递信号输出端OUT1的电压由高电平向低电平跳变时，第九晶体管M9截止，从而切断了第一电容C1的耦合效应到达传递信号输出端OUT1的路径，进而避免了第一电容C1的耦合效应对传递信号输出端OUT1输出的传递信号的影响，确保传递信号不会产生尖刺等噪声，最终确保了移位寄存器级间移位传递信号的稳定性。
本实施例中移位寄存器的其他结构及驱动方法与实施例1中相同，此处不再赘述。
本实施例中移位寄存器的去噪模块4同样在驱动方法的第三阶段对传递信号输出端OUT1输出的传递信号VZ去噪，但具体的去噪过程与实施例1不同。下面，基于本实施例中去噪模块4的上述电路连接，具体描述本实施例中去噪模块4的去噪过程。
在第三阶段，起始信号INPUT保持低电平，第一时钟信号端CLK输出的信号为低电平，第二时钟信号端CLKB输出的信号为高电平，复位信号RESET为高电平。
具体地，由于复位信号RESET为高电平，第二晶体管M2导通，第四电源VDB将上拉节点PU的电压拉低，使得第三晶体管M3和第十晶体管M10截止。同时，由于第二时钟信号端CLKB输出的信号为高电平，第五晶体管M5和第六晶体管M6导通，下拉节点PD变为高电平；继而第七晶体管M7、第八晶体管M8和第十一晶体管M11导通；第七晶体管M7将上拉节点PU的电压进一步拉低，第八晶体管M8将传递信号输出端OUT1输出的传递信号VZ下拉为低电平，从而使第九晶体管M9截止；第九晶体管M9截止后，能够切断第一电容C1在上拉节点PU跳变时产生的耦合效应到达传递信号输出端OUT1的路径，从而能够避免第一电容C1的耦合效应使传递信号输出端OUT1输出的传递信号VZ产生尖刺等噪声，进而确保了移位寄存器移位传递信号VZ的稳定性。
实施例1-2的有益效果：实施例1-2中所提供的移位寄存器，通过设置去噪模块，使该移位寄存器在上拉节点的电压发生跳变时，能防止第一电容的耦合效应使移位寄存器传递信号输出端输出的传递信号产生尖刺等噪声，从而使移位寄存器的级间移位传递信号更加稳定，同时还能降低移位寄存器电路的噪声，进而使移位寄存器的输出端输出的信号更加稳定。
实施例3：
本实施例提供一种栅极驱动电路，如图9所示，包括：多级移位寄存器，该移位寄存器采用实施例1或2中的移位寄存器，本级移位寄存器的传递信号输出端OUT1与上一级移位寄存器的复位信号输入端RESET和下一级移位寄存器的起始信号输入端INPUT连接。
通过采用实施例1或2中的移位寄存器，降低了该栅极驱动电路的噪声，使该栅极驱动电路输出的栅极驱动信号更加稳定。
实施例4：
本实施例提供一种显示装置，包括实施例3中的栅极驱动电路。
通过采用实施例3中的栅极驱动电路，使该显示装置的显示更加稳定，从而提升了该显示装置的显示质量。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。
本申请要求2015年5月13日提交的申请号为“201510242821.0”且发明名称为“移位寄存器及其驱动方法、栅极驱动电路和显示装置”的中国优先申请的优先权，通过引用将其全部内容并入于此。

Claims (16)

  1. 一种移位寄存器，包括上拉模块、第一电容和下拉模块，其特征在于，还包括去噪模块，
    所述去噪模块的第一端连接所述第一电容的第二端，所述去噪模块的第二端连接传递信号输出端；
    其中，所述上拉模块与所述移位寄存器的输出端和所述传递信号输出端连接并且与所述第一电容的第一端连接，并且用于在所述第一电容的第一端的控制下对所述移位寄存器的输出端输出的信号和所述传递信号输出端输出的信号上拉，所述上拉模块与所述第一电容的第一端的连接点为上拉节点；
    所述下拉模块与所述移位寄存器的输出端和所述传递信号输出端连接并且与所述第一电容的第一端连接，并且用于在下拉阶段对所述移位寄存器的输出端输出的信号和所述传递信号输出端输出的信号下拉；
    所述去噪模块用于在下拉阶段切断所述传递信号输出端与所述第一电容的第二端的连接通路。
  2. 根据权利要求1所述的移位寄存器，其特征在于，所述去噪模块包括第九晶体管，所述第九晶体管的栅极和第一极连接所述第一电容的第二端，所述第九晶体管的第二极连接所述传递信号输出端。
  3. 根据权利要求1所述的移位寄存器，其特征在于，所述去噪模块包括第九晶体管，所述第九晶体管的第一极连接所述第一电容的第二端，所述第九晶体管的栅极和第二极连接所述传递信号输出端。
  4. 根据权利要求2或3所述的移位寄存器，其特征在于，所述上拉模块包括第一子模块和第二子模块，所述第一子模块和所述第二子模块连接于所述上拉节点，所述第一子模块还连接第一时钟信号端和所述传递信号输出端，所述第二子模块还连接第一电源和所述移位寄存器的输出端；
    所述第一子模块用于对所述传递信号输出端输出的信号进行上拉；
    所述第二子模块用于对所述移位寄存器的输出端输出的信号进行上拉。
  5. 根据权利要求4所述的移位寄存器，其特征在于，所述下拉模块包括第三子模块和第四子模块，所述第三子模块和所述第四子模块连接于下拉节点，所述第三子模块还连接第二时钟信号端和所述第一电源，所述第四子模块还连接第二电源、所述输出端、所述第九晶体管的第二极和所述传递信号输出端，且所述第四子模块与所述第一子模块和所述第二子模块连接于所述上拉节点；
    所述第三子模块用于在下拉阶段控制所述下拉节点的电位；
    所述第四子模块用于在下拉阶段对所述移位寄存器的输出端输出的信号和所述传递信号输出端输出的信号进行下拉。
  6. 根据权利要求5所述的移位寄存器，其特征在于，所述第一子模块包括第四晶体管，所述第四晶体管的栅极连接所述上拉节点，所述第四晶体管的第一极连接所述第一时钟信号端，所述第四晶体管的第二极连接所述传递信号输出端；
    所述第二子模块包括第三晶体管，所述第三晶体管的栅极连接所述上拉节点，所述第三晶体管的第一极连接所述第一电源，所述第三晶体管的第二极连接所述移位寄存器的输出端。
  7. 根据权利要求6所述的移位寄存器，其特征在于，所述第三子模块包括第五晶体管和第六晶体管，所述第五晶体管的栅极和第一极连接所述第二时钟信号端，所述第五晶体管的第二极连接所述第六晶体管的栅极；所述第六晶体管的第一极连接所述第一电源和所述第三晶体管的第一极，所述第六晶体管的第二极连接所述下拉节点；
    所述第四子模块包括第七晶体管、第八晶体管、第十晶体管和第十一晶体管，所述第十晶体管的栅极和所述第七晶体管的第一极均连接所述上拉节点；所述第十晶体管的第一极、所述第七晶体管的栅极、所述第八晶体管的栅极和所述第十一晶体管的栅极均连接所述下拉节点；所述第十晶体管的第二极、所述第七晶体管的第二极、所述第八晶体管的第二极和所述第十一晶体管的第二极均连接所述第二电源；所述第八晶体管的第一极连接所述第九晶体管的第二极、所述第四晶体管的第二极和所述传递信号输出端；所述第十一晶体管的第一极连接所述第三晶体管的第二极和所述移位寄存器的输出 端。
  8. 根据权利要求7所述的移位寄存器，其特征在于，所述第一时钟信号端输出的第一时钟信号和所述第二时钟信号端输出的第二时钟信号相位相差180度。
  9. 根据权利要求7所述的移位寄存器，其特征在于，还包括触发复位模块，用于根据起始信号输入端输入的起始信号和复位信号输入端输入的复位信号对所述上拉节点进行充电和放电，
    所述触发复位模块包括触发子模块和复位子模块，所述触发子模块和所述复位子模块连接于所述上拉节点，所述触发子模块连接第三电源，所述复位子模块连接第四电源；
    所述触发子模块用于根据所述起始信号输入端输入的起始信号对所述上拉节点进行充电；
    所述复位子模块用于根据所述复位信号输入端输入的复位信号对所述上拉节点进行放电。
  10. 根据权利要求9所述的移位寄存器，其特征在于，所述触发子模块包括第一晶体管，所述第一晶体管的栅极连接所述起始信号输入端，所述第一晶体管的第一极连接所述第三电源，所述第一晶体管的第二极连接所述上拉节点；
    所述复位子模块包括第二晶体管，所述第二晶体管的栅极连接所述复位信号输入端，所述第二晶体管的第一极连接所述上拉节点，所述第二晶体管的第二极连接所述第四电源。
  11. 根据权利要求2所述的移位寄存器，其特征在于，所述第九晶体管为N型晶体管，其第一极为漏极，其第二极为源极。
  12. 根据权利要求3所述的移位寄存器，其特征在于，所述第九晶体管为P型晶体管，其第一极为源极，其第二极为漏极。
  13. 根据权利要求10所述的移位寄存器，其特征在于，所述第一到第八晶体管以及第十和第十一晶体管为N型晶体管，其第一极为漏极，其第二极为源极。
  14. 一种栅极驱动电路，包括：多级移位寄存器，其特征在于，所述移位寄存器采用权利要求1-13任一项所述的移位寄存器，本级所述移位寄存器的传递信号输出端与上一级所述移位寄存器的复位信号输入端和下一级所述移位寄存器的起始信号输入端连接。
  15. 一种显示装置，其特征在于，包括权利要求14所述的栅极驱动电路。
  16. 一种根据权利要求1-13任一项所述的移位寄存器的驱动方法，其特征在于，所述驱动方法包括：
    第一阶段，所述第一电容被充电，所述上拉模块在所述上拉节点的控制下对所述移位寄存器的输出端输出的信号上拉；
    第二阶段，所述第一电容在该阶段提升所述上拉节点的电压，所述上拉模块继续对所述移位寄存器的输出端输出的信号上拉，并且所述上拉模块对传递信号输出端输出的信号上拉；
    第三阶段，所述第一电容被放电，所述下拉模块对所述移位寄存器的输出端输出的信号和所述传递信号输出端输出的信号下拉，并且所述去噪模块切断所述传递信号输出端与所述第一电容的第二端的连接通路。
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