WO2016201818A1 - 用于tft-lcd的源极驱动器、驱动电路及驱动方法 - Google Patents

用于tft-lcd的源极驱动器、驱动电路及驱动方法 Download PDF

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Publication number
WO2016201818A1
WO2016201818A1 PCT/CN2015/090496 CN2015090496W WO2016201818A1 WO 2016201818 A1 WO2016201818 A1 WO 2016201818A1 CN 2015090496 W CN2015090496 W CN 2015090496W WO 2016201818 A1 WO2016201818 A1 WO 2016201818A1
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Prior art keywords
output
pulse
level
loading
data
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PCT/CN2015/090496
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English (en)
French (fr)
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王慧
冯伟
梁恒镇
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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Priority to US15/037,217 priority Critical patent/US9953559B2/en
Priority to EP15858099.3A priority patent/EP3312828B1/en
Publication of WO2016201818A1 publication Critical patent/WO2016201818A1/zh
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2018—Display of intermediate tones by time modulation using two or more time intervals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0814—Several active elements per pixel in active matrix panels used for selection purposes, e.g. logical AND for partial update
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0828—Several active elements per pixel in active matrix panels forming a digital to analog [D/A] conversion circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/025—Reduction of instantaneous peaks of current
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/06—Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular, to a source driver, a driving circuit, and a driving method for a TFT-LCD.
  • TFT-LCDs Thin film transistor liquid crystal displays
  • a TFT-LCD includes a liquid crystal panel having pixel units arranged in a matrix, wherein a driving circuit is provided to drive a display function of the pixel unit.
  • a TFT-LCD device includes a liquid crystal panel having m ⁇ n pixel units arranged in a matrix, m source lines (also referred to as data lines) S1 to Sm and n gate lines G1 to which mutually intersect each other Gn and a thin film transistor disposed at an intersection of the data line and the gate line, a source driver for supplying data to the data lines S1 to Sm of the liquid crystal panel, and for supplying a scan pulse to the gate lines G1 to Gn Gate driver.
  • the gate driver sequentially outputs scan pulses on the gate lines G1, G2, . . .
  • Gn (also referred to as scan lines) in response to the clock signal to control turn-on and turn-off of the TFTs on the respective gate lines, and the source driver
  • the display data is converted to a gray scale voltage when the TFT is turned on to charge the pixel unit to realize display of data.
  • TFT-LCD is currently developing in the direction of large size and high resolution. Due to the large size of the panel, the RC of the gate line and the common electrode line is large. If the difference between the adjacent two lines of display data (ie, the gray scale voltage) is large, the load capacity of the source driver is insufficient. Moreover, the VCOM voltage is pulled due to a sudden change in the gray scale voltage, thereby destabilizing the voltage applied to the pixel unit. These often cause undesirable display effects such as artifacts and crosstalk.
  • the problem to be solved by the present invention is to avoid insufficient display capability of the source driver and/or display effects such as artifacts and crosstalk caused by a large difference between adjacent two lines of display data.
  • a source driver for a TFT-LCD comprising:
  • a data register for registering a plurality of display data, the plurality of display data corresponding to a plurality of pixel units in a row of pixel units of the TFT-LCD; a data latch having a first terminal for receiving a first loading pulse and a second terminal for receiving a second loading pulse, the data lock
  • the register is responsive to a first edge from the first level to the second level of the first load pulse and a first edge from the first level to the second level of the second load pulse in the data register a plurality of display data for latching; a digital-to-analog converter for converting a plurality of display data latched in the data latch into a corresponding plurality of gray scale voltages; and an output buffer comprising a plurality of buffer units Transmitting, by the output ends of the plurality of buffer units, the plurality of gray scale voltages; wherein the first load pulse is supplied to the output buffer such that the output buffer is responsive to the first Outputting a grayscale voltage of the odd output to a corresponding T
  • a driving circuit for a TFT-LCD comprising: at least one source driver as described in the second aspect of the invention; and a timing controller for The at least one source driver provides a first loading pulse and a second loading pulse.
  • a driving method for a TFT-LCD comprising: providing a first loading pulse and a second loading pulse; according to a first loading pulse from a first level to a second level And latching the plurality of display data by the first edge of the first edge and the second loading pulse from the first level to the second level; converting the latched plurality of display data into corresponding grays a step voltage; and outputting the plurality of gray scale voltages via outputs of the plurality of buffer units of the output buffer; wherein outputting the plurality of gray scale voltages comprises: providing the first load pulse to the output buffer And causing the output buffer to start outputting the gray scale voltage of the odd output end to the corresponding edge according to the second edge of the first edge from the second level to the first level of the first loading pulse a TFT source, and supplying the second load pulse to the output buffer such that the output buffer is in accordance with the second load from the second level to the first edge of the second load pulse a second edge of
  • the present invention can relieve the source driver overload caused by excessive data difference between two adjacent rows by providing two sets of unsynchronized loading pulses (TP signals) to allow the parity column pixels not to be charged at the same time (and thus the charging of the pixel electrodes is insufficient) And mitigate the pull effect on the VCOM voltage due to pixel voltage abrupt changes. More generally, the present invention can reduce image quality loss such as artifacts, crosstalk, and the like of a large-sized liquid crystal display.
  • Figure 1 schematically illustrates a circuit block diagram of a typical TFT-LCD
  • FIG. 2 schematically illustrates a block diagram of a source driver for a TFT-LCD in accordance with one embodiment of the present invention
  • FIG. 3 schematically illustrates a timing relationship between a first loading pulse, a second loading pulse, and a gate scan pulse for a source driver in accordance with an embodiment of the present invention
  • FIG. 4 schematically illustrates a block diagram of a source driver for a TFT-LCD according to another embodiment of the present invention
  • FIG. 5 schematically illustrates a block diagram of one implementation of the data difference determination circuit shown in FIG.
  • FIG. 2 schematically illustrates a block diagram of a source driver 200 for a TFT-LCD in accordance with one embodiment of the present invention.
  • the source driver 200 can include a data register 210, a data latch 220, a digital to analog converter 230, and an output buffer 240.
  • the timing controller is part of the drive circuitry of the TFT-LCD that can provide the source driver 200 with signals including video/image signals (display data) and clock signals.
  • the source driver 200 actually includes a plurality of output channels (corresponding to a plurality of columns) from the data register 210 to the output buffer 240, each of which is connected to a different column of pixel cells.
  • the source of the TFT When the current line is scanned, the scan pulse from the gate driver controls the TFTs in all pixel cells in the row to become conductive. At this time, the output signal from each of the output channels charges the pixel electrode in the pixel unit in the current row to drive the liquid crystal panel.
  • the data register 210 may include a plurality of register units for registering a plurality of display data, the number of the plurality of register units corresponding to the number of output channels of the source driver 200. In one example, assuming that the source driver 200 has 384 output channels, the data register 210 can have 384 register cells. Depending on the bit width of the display data, each register unit can be implemented, for example, with multiple transparent latches.
  • Data latch 220 can include a plurality of latch units that can generally latch a plurality of display data in data register 210 in response to a rising edge of a load pulse (TP signal).
  • data latch 220 can include 384 latch units.
  • the load pulse may include a first load pulse and a second load pulse (discussed later), and the data latch 220 may have a first terminal (not shown) for receiving the first load pulse and And receiving a second terminal (not shown) of the second loading pulse.
  • the data latch 220 may be responsive to a first edge from the first level to the second level of the first loading pulse and a first edge from the first level to the second level of the second loading pulse A plurality of display data in the data register are latched.
  • the data latch 220 may latch display data corresponding to the odd output channels in the data register 210 in response to the first edge of the first load pulse from the first level to the second level, and in response to The first edge of the second load pulse from the first level to the second level latches the display data in the data register 210 corresponding to the even output channel.
  • the digital to analog converter 230 may include a plurality of digital to analog converter (DAC) units that can convert a plurality of display data latched in the data latch 220 into corresponding plurality of Gray scale voltage.
  • digital to analog converter 230 may include 384 digital to analog converter (DAC) units. It should be understood that the digital to analog converter 230 can generally perform digital to analog conversion by selecting an analog voltage generated by a gray scale voltage generating circuit (not shown) corresponding to the digital data.
  • the output buffer 240 may include a plurality of buffer units that may output a plurality of gray scale voltages selected by the digital to analog converter 230 via a plurality of output terminals.
  • the output buffer 240 may include 384 buffer units.
  • the respective gray scale voltages output from these buffer units will be supplied to the pixel electrodes (via TFTs in the pixel unit) to control the deflection of the liquid crystal molecules to realize display of data.
  • these buffer units are illustrated as voltage followers formed by the operational amplifier OPA, despite the situation This may not be the case.
  • FIG. 3 schematically illustrates a timing relationship between a first load pulse TPO, a second load pulse TPE, and a gate scan pulse for the source driver 200 in accordance with an embodiment of the present invention.
  • the first load pulse TPO is a load pulse corresponding to an odd output channel
  • the second load pulse TPE is a load pulse corresponding to an even output channel.
  • the second loading pulse TPE is illustrated as a delayed version of the first loading pulse TPO (ie, the second loading pulse TPE is obtained by delaying the first loading pulse TPO), in which case the source
  • the pole driver 200 can include a delay circuit (not shown) for delaying the raw load pulse TP (from the timing controller) for a predetermined amount of time.
  • the raw loading pulse TP can act as the first loading pulse TPO and the delayed version of the original loading pulse TP can act as the second loading pulse TPE.
  • the first load pulse TPO is provided to the buffer cells in the odd output channels of the output buffer 240 such that those buffer cells can be responsive to the second edge of the first load pulse TPO from the second level to the first level (eg, , falling edge) and start to output the gray scale voltage of the odd output to the corresponding TFT source.
  • the second load pulse TPE is provided to the buffer cells in the even output channels of the output buffer 240 such that those buffer cells can begin to gray the even outputs in response to the second edge (eg, falling edge) of the second load pulse TPE
  • the step voltage is output to the corresponding TFT source.
  • the second edge of the first loading pulse TPO is not synchronized with the second edge of the second loading pulse TPE.
  • the time interval ⁇ t between the two edges can be set depending on the driving capability of the source driver, and is generally set to satisfy the expected TFT charging rate. For example, for a resolution of 3840x2160, the time interval ⁇ t can be between 0.5 ⁇ s and 0.8 ⁇ s.
  • the first level of the first load pulse TPO can be used as an enable signal for the odd buffer unit of the output buffer 240 to enable the output of the gray scale voltage from the odd output
  • the second load pulse TPE The first level can be used as an enable signal for the even buffer unit of output buffer 240 to enable the output of the gray scale voltage from the even output.
  • the output buffer 240 can further include a plurality of switching elements (not shown), each of the plurality of switching elements and the output of the plurality of buffering units of the output buffer 240 Corresponding one in series.
  • the first load pulse TPO may be provided to the control terminals of the switching elements in series with the odd outputs such that the switching elements are turned on at the first level of the first load pulse TPO.
  • the second loading pulse TPE can be provided to the control terminals of the switching elements in series with the even outputs, such that these switching elements It is turned on at the first level of the second load pulse TPE.
  • the switching elements can be thin film transistors, transmission gates, and the like.
  • the first level is a low level and the second level is a high level.
  • the first level can be a high level and the second level can be a low level.
  • the rising edge of the first loading pulse TPO and the rising edge of the second loading pulse TPE are illustrated as being out of sync. However, in other implementations, this may not be the case, ie, the two rising edges may be synchronized.
  • the falling edge of the first load pulse TPO is illustrated as occurring before the falling edge of the second load pulse TPE, although this may not be the case, ie, the falling edge of the second load pulse TPE may occur at the first load pulse TPO Before the falling edge.
  • the first load pulse TPO can be a delayed version in the second load pulse TPE.
  • the odd-column pixel unit and the even-numbered column pixel unit are not simultaneously charged, alleviating the (possible) difference between the adjacent two lines of display data.
  • the adverse consequences caused by the big are not synchronized, the odd-column pixel unit and the even-numbered column pixel unit are not simultaneously charged, alleviating the (possible) difference between the adjacent two lines of display data. The adverse consequences caused by the big.
  • first load pulse TPO and the second load pulse TPE which are not synchronized are always provided, regardless of the actual difference between the adjacent two lines of display data.
  • a certain judging mechanism may be introduced such that only two out-of-synchronization load pulses are provided when it is determined that the difference between adjacent two lines of display data is too large, otherwise to the odd-numbered column pixel unit The same (original) load pulse is provided for the even-numbered column pixel unit.
  • FIG. 4 schematically illustrates a block diagram of a source driver 400 for a TFT-LCD in accordance with another embodiment of the present invention.
  • data register 410, data latch 420, digital to analog converter 430, and output buffer 440 correspond to data register 210, data latch 220, digital to analog converter 230, and output buffer, respectively, in FIG. 240 will not be described in detail for the sake of brevity.
  • the source driver 400 may include a data difference judging circuit 450 that can judge a plurality of display data in the n+1th row registered in the data register 410 and a nth latched in the data latch 420 when updating one line of display data Whether the difference between the multiple display data in the row is large.
  • data register 410 and data latch 420 each store 384 display data (which corresponds to 384 columns), all of which are input to data difference determination circuit 450, where each column is calculated. The two display differences between the data and then compare it to a first predetermined threshold to derive Two lines show the judgment result of the difference in data.
  • the data difference determination circuit 450 provides different inputs to the timing controller (as shown in FIG. 4).
  • the input can be a high or low level representing a different logic value.
  • a high level may indicate a large difference between the display data of the n+1th row and the display data of the nth row.
  • the timing controller may or may not provide the first load pulse TPO and the second load pulse TPE.
  • the first load pulse TPO and the second load pulse TPE that are not synchronized are provided only when the input indicates a large difference between the display data of the n+1th row and the display data of the nth row, otherwise a first one is provided.
  • the same load pulse may also be understood that the “large difference” may mean that at least one or more of the respective differences between the plurality of display data in the n+1th row and the plurality of display data in the nth row is greater than the first predetermined. Threshold.
  • FIG. 5 schematically illustrates a block diagram of one implementation of the data difference determination circuit 450 shown in FIG.
  • the data difference determination circuit 450 may include a subtractor 451 that can respectively subtract the plurality of display data in the n+1th row from the plurality of display data in the nth row, and may subtract the result in the subtraction result.
  • Each of the first value comparators 452 is compared to a first predetermined threshold TH1.
  • 384 display data D1(n+1), D2(n+1), ..., D384(n+1) in the n+1th row and 384 displays in the nth row
  • the data D1(n), D2(n), ..., D384(n) are input to the subtractor 451 for subtraction, and output 384 corresponding differences S1, S2, ..., S384, which are 384
  • the difference values are then input to the first value comparator 452 for comparison with the first predetermined threshold TH1.
  • the first value comparator 452 can output 384 comparison results C1, C2, ..., C384 representing different logical relationships (i.e., greater than, equal to, or less than). Implementations of the subtractor and the first numerical comparator are known in the art and will not be described in detail herein.
  • the "large difference” means that at least one of the difference between the plurality of display data in the n+1th row and the plurality of display data in the nth row is greater than the first predetermined threshold, depending on
  • the defined signal logic eg, a logical "0" may indicate that the difference is greater than the first threshold, or a logic "1” may indicate that the difference is greater than the first threshold
  • the data difference determining circuit 450 may further include the first AND gate or the first An OR gate 453 is used to perform an AND operation or an OR operation on each of the output results of the first value comparator 452.
  • the output of the first AND gate or the first OR gate 453 may be supplied to the timing controller as an input indicating the judgment result of the data difference judging circuit 450.
  • the "large difference" refers to a plurality of display data in the (n+1)th row.
  • the data difference determination circuit 450 may further include, in another implementation, a first numerical comparator Each of the output results is an adder that adds and a second value comparator that compares the addition result to a second predetermined threshold. The output of the second numerical comparator is supplied to the timing controller as an input indicating the judgment result of the data difference judging circuit 450.
  • the addition result is less than the second predetermined threshold indicating a large difference between the plurality of display data in the n+1th row and the plurality of display data in the nth row.
  • the logic "1" indicates that the difference is greater than the first threshold
  • the addition result is greater than the second predetermined threshold indicating a large difference between the plurality of display data in the n+1th row and the plurality of display data in the nth row.
  • the source driver is typically in the form of a source driver chip, and the source driver chip, the gate driver chip, the timing controller, and other peripheral circuits together form a driver circuit for the display panel.
  • the delay circuit was described as part of the source driver 200, although this may not be the case.
  • the delay circuit can also be a separate circuit that is part of the drive circuit.
  • data difference determination circuit 450 is described as part of source driver 400, although this may not be the case.
  • the data difference determination circuit 450 may also be a separate circuit that is part of the drive circuit.
  • multiple cascaded source driver chips may be required when driving one display panel.
  • the driver chip has 384 outputs) and requires 10 cascaded source driver chips to drive the SXGA display panel.
  • the driving circuit may further include a second AND gate or a second OR gate for data difference judging circuit from each of the plurality of source driving chips The output is ORed or ORed.
  • the output of the second AND gate or the second OR gate may be provided to the timing controller as a final judgment result indicating that the adjacent two rows display data differences.
  • Embodiments also provide a driving method for a TFT-LCD, comprising: providing a first loading pulse TPO and a second loading pulse TPE; according to a first loading pulse TPO from a first level to a second level The first edge and the first edge of the second loading pulse TPE from the first level to the second level latch a plurality of display data; converting the latched plurality of display data into corresponding grays a step voltage; and outputting the plurality of gray scale voltages via outputs of the plurality of buffer units of the output buffers 240, 440; wherein outputting the plurality of gray scale voltages comprises: providing the first load pulse TPO to The output buffers 240, 440 are such that the output buffers 240, 440 are in accordance with the second edge of the first loading pulse TPO immediately following the first edge from the second level to the first level Starting to output the gray scale voltage of the odd output to the corresponding TFT source, and

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  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种用于ＴＦＴ－ＬＣＤ的源极驱动器（400），包括：数据寄存器（410）、数据锁存器（420）、数模转换器（430）以及输出缓冲器（440）。第一装载脉冲（TPO）被提供给输出缓冲器（440），使得输出缓冲器（440）响应于第一装载脉冲（TPO）的紧接着第一边沿的从第二电平到第一电平的第二边沿而开始将奇数输出端的灰阶电压输出到对应的ＴＦＴ源极，并且第二装载脉冲（TPE）被提供给输出缓冲器（440），使得输出缓冲器（440）响应于第二装载脉冲（TPE）的紧接着第一边沿的从第二电平到第一电平的第二边沿而开始将偶数输出端的灰阶电压输出到对应的ＴＦＴ源极。至少第一装载脉冲（TPO）的第二边沿与第二装载脉冲（TPE）的第二边沿不同步。还提供了相应的驱动电路和驱动方法。该源极驱动器（400）、驱动电路和驱动方法可以缓解由相邻两行显示数据差异过大引起的不良后果。

Description

用于TFT-LCD的源极驱动器、驱动电路及驱动方法 技术领域
本发明涉及液晶显示技术领域，特别地涉及一种用于TFT-LCD的源极驱动器、驱动电路及驱动方法。
背景技术
薄膜晶体管液晶显示器(TFT-LCD)广泛应用于诸如电视、计算机、移动电话之类的消费电子产品中。通常，TFT-LCD包括具有以矩阵布置的像素单元的液晶面板，其中驱动电路被提供用来驱动像素单元的显示功能。
图1示意性地图示了一种典型的TFT-LCD的电路框图。参照图1，TFT-LCD器件包括具有以矩阵布置的m×n个像素单元的液晶面板，相互交叉的m条源极线(也被称为数据线)S1至Sm与n条栅线G1至Gn以及设置在数据线和栅线的交叉点处的薄膜晶体管，用于将数据提供到液晶面板的数据线S1至Sm的源极驱动器，以及用于将扫描脉冲提供到栅线G1至Gn的栅极驱动器。栅极驱动器响应于时钟信号依次在栅线G1，G2，...Gn(也被称为扫描线)上输出扫描脉冲以控制相应栅线上的TFT的导通和关断，而源极驱动器在TFT导通时将显示数据转换成灰阶电压来对像素单元充电以实现数据的显示。
TFT-LCD目前正向大尺寸、高解析度的方向发展。由于面板尺寸较大导致栅线及公共电极线的RC较大，若相邻两行显示数据(即，灰阶电压)之间的差异较大，会使源极驱动器的带载能力不足。而且，VCOM电压会由于灰阶电压的突变而受到拉动，从而使施加在像素单元上的电压不稳定。这些往往造成伪像、串扰等不良显示效果。
因此，需要一种改进的用于TFT-LCD的源极驱动器以及相应的驱动电路和驱动方法。
发明内容
本发明要解决的问题是，避免相邻两行显示数据之间的差异较大引起的源极驱动器的带载能力不足和/或伪像、串扰等不良的显示效果。
根据本发明的第一方面，提供了一种用于TFT-LCD的源极驱动器，包括：
数据寄存器，用于寄存多个显示数据，所述多个显示数据对应于 所述TFT-LCD的一行像素单元中的多个像素单元；数据锁存器，具有用于接收第一装载脉冲的第一端子和用于接收第二装载脉冲的第二端子，所述数据锁存器响应于第一装载脉冲的从第一电平到第二电平的第一边沿和第二装载脉冲的从第一电平到第二电平的第一边沿对所述数据寄存器中的多个显示数据进行锁存；数模转换器，用于将所述数据锁存器中锁存的多个显示数据转换成对应的多个灰阶电压；以及输出缓冲器，包括多个缓冲单元，用于经由所述多个缓冲单元的输出端输出所述多个灰阶电压；其中，所述第一装载脉冲被提供给所述输出缓冲器，使得所述输出缓冲器响应于所述第一装载脉冲的紧接着所述第一边沿的从第二电平到第一电平的第二边沿而开始将奇数输出端的灰阶电压输出到对应的TFT源极，并且其中，所述第二装载脉冲被提供给所述输出缓冲器，使得所述输出缓冲器响应于所述第二装载脉冲的紧接着所述第一边沿的从第二电平到第一电平的第二边沿而开始将偶数输出端的灰阶电压输出到对应的TFT源极，至少所述第一装载脉冲的第二边沿与所述第二装载脉冲的第二边沿不同步。
根据本发明的第二方面，提供了一种用于TFT-LCD的驱动电路，包括：至少一个如本发明的第二方面中所述的源极驱动器；以及时序控制器，其用于向所述至少一个源极驱动器提供第一装载脉冲和第二装载脉冲。
根据本发明的第三方面，提供了一种用于TFT-LCD的驱动方法，包括：提供第一装载脉冲和第二装载脉冲；根据第一装载脉冲的从第一电平到第二电平的第一边沿和第二装载脉冲的从第一电平到第二电平的第一边沿对多个显示数据进行锁存；将锁存的所述多个显示数据转换成对应的多个灰阶电压；以及经由输出缓冲器的多个缓冲单元的输出端输出所述多个灰阶电压；其中，输出所述多个灰阶电压包括：将所述第一装载脉冲提供给所述输出缓冲器，使得所述输出缓冲器根据所述第一装载脉冲的紧接着所述第一边沿的从第二电平到第一电平的第二边沿而开始将奇数输出端的灰阶电压输出到对应的TFT源极，并且将所述第二装载脉冲提供给所述输出缓冲器，使得所述输出缓冲器根据所述第二装载脉冲的紧接着所述第一边沿的从第二电平到第一电平的第二边沿而开始将偶数输出端的灰阶电压输出到对应的TFT源极，至少所述第一装载脉冲的第二边沿与所述第二装载脉冲的第二边 沿不同步。
本发明通过提供两组不同步的装载脉冲(TP信号)以允许奇偶列像素不同时充电，可以缓解由相邻两行显示数据差异过大引起的源极驱动器过载(并且因此像素电极的充电不足)以及减轻由于像素电压突变对VCOM电压的拉动效应。更一般地，本发明可以降低大尺寸液晶显示器的伪像、串扰等画质损失。
根据在下文中所描述的实施例，本发明的这些和其它方面将是显而易见的，并且将参考在下文中所描述的实施例而被阐明。
附图说明
图1示意性地图示了一种典型的TFT-LCD的电路框图；
图2示意性地图示了根据本发明的一个实施例的用于TFT-LCD的源极驱动器的框图；
图3示意性地图示了用于根据本发明的一个实施例的源极驱动器的第一装载脉冲、第二装载脉冲以及栅极扫描脉冲之间的时序关系；
图4示意性地图示了根据本发明的另一个实施例的用于TFT-LCD的源极驱动器的框图；以及
图5示意性地图示了图4中示出的数据差异判断电路的一个实现方式的框图。
具体实施方式
以下结合附图对本发明的各实施例进行详细描述。
图2示意性地图示了根据本发明的一个实施例的用于TFT-LCD的源极驱动器200的框图。出于解释的目的，仅示出了与本发明的实施例有关的元件，而省略了与本发明的实施例无关的元件，诸如移位寄存器、电平移位器、灰阶电压生成电路等等。像这样地，源极驱动器200可以包括数据寄存器210、数据锁存器220、数模转换器230以及输出缓冲器240。此外，如本领域已知的，时序控制器是TFT-LCD的驱动电路的一部分，其可以为源极驱动器200提供包括视频/图像信号(显示数据)和时钟信号在内的信号。
如图2所示，源极驱动器200实际上包括从数据寄存器210到输出缓冲器240的多个输出通道(对应于多个列)，它们中的每一个都连接到不同的一列像素单元中的TFT的源极。当扫描到当前行时，来自栅极驱动器的扫描脉冲控制该行内所有像素单元中的TFT变成导通。 此时，来自每一个输出通道的输出信号对当前行内的像素单元中的像素电极进行充电，实现对液晶面板的驱动。
数据寄存器210可以包括用于寄存多个显示数据的多个寄存器单元，该多个寄存器单元的数目对应于源极驱动器200的输出通道的数目。在一个示例中，假定源极驱动器200具有384个输出通道，则数据寄存器210可以具有384个寄存器单元。取决于显示数据的位宽，每一个寄存器单元可以例如用多个透明锁存器实现。
数据锁存器220可以包括多个锁存器单元，该多个锁存器单元一般地可以响应于装载脉冲(TP信号)的上升沿而对数据寄存器210中的多个显示数据进行锁存。依照前面假设的示例，数据锁存器220可以包括384个锁存器单元。在本实施例中，装载脉冲可以包括第一装载脉冲和第二装载脉冲(后面讨论)，并且数据锁存器220可以具有用于接收第一装载脉冲的第一端子(未示出)和用于接收第二装载脉冲的第二端子(未示出)。数据锁存器220可以响应于第一装载脉冲的从第一电平到第二电平的第一边沿和第二装载脉冲的从第一电平到第二电平的第一边沿对所述数据寄存器中的多个显示数据进行锁存。具体地，数据锁存器220可以响应于第一装载脉冲的从第一电平到第二电平的第一边沿将数据寄存器210中对应于奇数输出通道的显示数据进行锁存，并且响应于第二装载脉冲的从第一电平到第二电平的第一边沿将数据寄存器210中对应于偶数输出通道的显示数据进行锁存。
数模转换器230可以包括多个数模转换器(DAC)单元，该多个数模转换器(DAC)单元可以将数据锁存器220中锁存的多个显示数据转换成对应的多个灰阶电压。依照前面假设的示例，数模转换器230可以包括384个数模转换器(DAC)单元。应当理解，数模转换器230通常可以通过选择数字数据对应的由灰阶电压生成电路(未示出)生成的模拟电压而施行数模转换。
输出缓冲器240可以包括多个缓冲单元，该多个缓冲单元可以经由多个输出端输出所述数模转换器230选择的多个灰阶电压。依照前面假设的示例，输出缓冲器240可以包括384个缓冲单元。从这些缓冲单元输出的各个灰阶电压将被(经由像素单元中的TFT)提供给像素电极以控制液晶分子的偏转从而实现数据的显示。在图2的示例中，这些缓冲单元被图示为由运算放大器OPA形成的电压跟随器，尽管情 况可以并非如此。
图3示意性地图示了用于根据本发明实施例的源极驱动器200的第一装载脉冲TPO、第二装载脉冲TPE以及栅极扫描脉冲之间的时序关系。第一装载脉冲TPO是对应于奇数输出通道的装载脉冲，并且第二装载脉冲TPE是对应于偶数输出通道的装载脉冲。
下面结合图2和3进一步描述本发明的实施例。在图3中，第二装载脉冲TPE被图示为第一装载脉冲TPO的延时版本(即，第二装载脉冲TPE由第一装载脉冲TPO经延时而得到)，在该情况下，源极驱动器200可以包括用于延迟(来自时序控制器的)原始装载脉冲TP一预定时间量的延时电路(未示出)。这样，该原始装载脉冲TP可以充当第一装载脉冲TPO，并且延时版本的原始装载脉冲TP可以充当第二装载脉冲TPE。第一装载脉冲TPO被提供给输出缓冲器240的奇数输出通道中的缓冲单元，使得那些缓冲单元可以响应于第一装载脉冲TPO的从第二电平到第一电平的第二边沿(例如，下降沿)而开始将奇数输出端的灰阶电压输出到对应的TFT源极。第二装载脉冲TPE被提供给输出缓冲器240的偶数输出通道中的缓冲单元，使得那些缓冲单元可以响应于第二装载脉冲TPE的第二边沿(例如，下降沿)而开始将偶数输出端的灰阶电压输出到对应的TFT源极。如图3所示的，第一装载脉冲TPO的第二边沿与第二装载脉冲TPE的第二边沿不同步。这两个边沿之间的时间间隔Δt可以取决于源极驱动器的驱动能力来设置，并且一般地被设置为满足预期的TFT充电率。举例而言，对于3840x2160的分辨率，该时间间隔Δt可以介于0.5μs～0.8μs之间。
在一个实现方式中，第一装载脉冲TPO的第一电平可以用作输出缓冲器240的奇数缓冲单元的使能信号来使能灰阶电压从奇数输出端的输出，并且第二装载脉冲TPE的第一电平可以用作输出缓冲器240的偶数缓冲单元的使能信号来使能灰阶电压从偶数输出端的输出。
在一个供替换的实现方式中，输出缓冲器240可以还包括多个开关元件(未示出)，该多个开关元件中的每一个与输出缓冲器240的多个缓冲单元的输出端中的相应一个串联。第一装载脉冲TPO可以被提供给与奇数输出端串联的开关元件的控制端，使得这些开关元件在第一装载脉冲TPO的第一电平下导通。类似地，第二装载脉冲TPE可以被提供给与偶数输出端串联的开关元件的控制端，使得这些开关元件 在第二装载脉冲TPE的第一电平下导通。通过举例的方式而非限制，开关元件可以是薄膜晶体管、传输门等。
需要指出的是，在图3的示例中，第一电平为低电平，并且第二电平为高电平。然而，在其他实现方式中，情况可以并非如此。例如，第一电平可以为高电平，并且第二电平可以为低电平。另外，第一装载脉冲TPO的上升沿与第二装载脉冲TPE的上升沿被图示为不同步。然而，在其他实现方式中，情况可以并非如此，即，这两个上升沿可以是同步的。此外，第一装载脉冲TPO的下降沿被图示为发生在第二装载脉冲TPE的下降沿之前，尽管情况可以并非如此，即，第二装载脉冲TPE的下降沿可以发生在第一装载脉冲TPO的下降沿之前。例如，第一装载脉冲TPO可以是第二装载脉冲TPE中的延时版本。
由于第一装载脉冲TPO和第二装载脉冲TPE不同步的原因，奇数列的像素单元和偶数列的像素单元不是同时被充电，缓解了相邻两行显示数据之间的(可能的)差异过大所引起的不利后果。
前面讨论的是其中总是提供不同步的第一装载脉冲TPO和第二装载脉冲TPE的情况，而不管相邻两行显示数据之间的实际差异如何。然而，根据本发明的另一个实施例，可以引入某种判断机制使得只有在确定相邻两行显示数据之间的差异过大时才提供不同步的两个装载脉冲，否则向奇数列像素单元和偶数列像素单元提供同一个(原始的)装载脉冲。
图4示意性地图示了根据本发明的另一个实施例的用于TFT-LCD的源极驱动器400的框图。在该图中，数据寄存器410、数据锁存器420、数模转换器430以及输出缓冲器440分别对应于图2中的数据寄存器210、数据锁存器220、数模转换器230以及输出缓冲器240，为了简洁起见它们全部将不进行详细描述。
源极驱动器400可以包括数据差异判断电路450，其可以在更新一行显示数据时判断数据寄存器410中寄存的第n+1行中的多个显示数据与数据锁存器420中锁存的第n行中的多个显示数据之间的差异是否为大。例如，依照前面假设的示例，数据寄存器410和数据锁存器420每一个都存储了384个显示数据(其对应于384列)，它们全部输入到数据差异判断电路450，在那里计算每一列上的两个显示数据之间的差值并且然后将其与一个第一预定阈值相比较，以便得出关于相邻 两行显示数据的差异的判断结果。根据不同的判断结果，数据差异判断电路450向(如图4中所示的)时序控制器提供不同的输入。该输入可以是一个表示不同逻辑值的高电平或低电平。举例而言，高电平可以表示第n+1行的显示数据与第n行的显示数据的大的差异。然后，根据来自数据差异判断电路450的输入，时序控制器可以提供或可以不提供第一装载脉冲TPO和第二装载脉冲TPE。如前所述，只有该输入指示第n+1行的显示数据与第n行的显示数据的大的差异时，才提供不同步的第一装载脉冲TPO和第二装载脉冲TPE，否则提供一个相同的装载脉冲。还应当理解，所述“大的差异”可以指的是第n+1行中的多个显示数据与第n行中的多个显示数据的相应差值中至少一个或多个大于第一预定阈值。
图5示意性地图示了图4中示出的数据差异判断电路450的一个实现方式的框图。在该实现方式中，数据差异判断电路450可以包括可以将第n+1行中的多个显示数据与第n行中的多个显示数据分别相减的减法器451和可以将减法结果中的每一个分别与第一预定阈值TH1相比较的第一数值比较器452。依照前面假设的示例，第n+1行中的384个显示数据D1(n+1)，D2(n+1)，...，D384(n+1)与第n行中的384个显示数据D1(n)，D2(n)，...，D384(n)被输入到该减法器451中相减，并且输出384个对应的差值S1，S2，...，S384，该384个差值然后被输入到第一数值比较器452以与第一预定阈值TH1相比较。第一数值比较器452可以输出表示不同逻辑关系(即，大于、等于或小于)的384个比较结果C1，C2，...，C384。减法器和第一数值比较器的实现是本领域中已知的，并且将不在此详细描述。
在所述“大的差异”指的是第n+1行中的多个显示数据与第n行中的多个显示数据的差值中的至少一个大于第一预定阈值的情况下，取决于所定义的信号逻辑(例如，逻辑“0”可以表示差值大于第一阈值，或者逻辑“1”可以表示差值大于第一阈值)，数据差异判断电路450可以还包括第一与门或第一或门453，用于将第一数值比较器452的输出结果中的每一个进行与运算或或运算。第一与门或第一或门453的输出可以作为指示数据差异判断电路450的判断结果的输入被提供给时序控制器。
替换地，在所述“大的差异”指的是第n+1行中的多个显示数据 与第n行中的多个显示数据的差值中的至少预定数目个大于第一预定阈值的情况下，数据差异判断电路450在另一个实现方式中可以还包括用于将第一数值比较器的输出结果中的每一个进行相加的加法器和用于将加法结果与第二预定阈值相比较的第二数值比较器。第二数值比较器的输出作为指示数据差异判断电路450的判断结果的输入被提供给时序控制器。例如，如果逻辑“0”表示差值大于第一阈值，则加法结果小于第二预定阈值指示第n+1行中的多个显示数据与第n行中的多个显示数据的大的差异。替代地，如果逻辑“1”表示差值大于第一阈值，则加法结果大于第二预定阈值指示第n+1行中的多个显示数据与第n行中的多个显示数据的大的差异。加法器和第二数值比较器的实现是本领域中已知的，并且将不在此详细描述。
在实践中，源极驱动器通常采取源极驱动芯片的形式，并且由源极驱动芯片、栅极驱动芯片、时序控制器以及其他外围电路一起构成用于显示面板的驱动电路。在前面的实施例中，延时电路是作为源极驱动器200的一部分描述的，尽管情况可以并非如此。例如，延时电路也可以是作为驱动电路的一部分的单独的电路。另外，在前面的实施例中，数据差异判断电路450是作为源极驱动器400的一部分描述的，尽管情况可以并非如此。例如，数据差异判断电路450也可以是作为驱动电路的一部分的单独的电路。
进一步地，在驱动一个显示面板时可能需要多个级联的源极驱动芯片。例如，对于分辨率为1280x1024的SXGA显示面板，一行显示数据对应1280x3＝3840个像素单元(因为一个像素包括R、G、B 3个像素单元)，此时依照前面假设的示例(即一个源极驱动芯片具有384个输出)，需要10个级联的源极驱动芯片来驱动该SXGA显示面板。在多个源极驱动芯片的情况下，取决于所定义的信号逻辑(例如，逻辑“0”可以指示第n+1行中的多个显示数据与第n行中的多个显示数据的大的差异，或者逻辑“1”可以指示该大的差异)，驱动电路还可以包括第二与门或第二或门，用于将来自多个源极驱动芯片中的每一个的数据差异判断电路的输出进行与运算或或运算。第二与门或第二或门的输出可以作为指示相邻两行显示数据差异的最终判断结果被提供给时序控制器。
与前面参照图2到5描述的实施例相对应，根据本发明的另一个 实施例，还提供了一种用于TFT-LCD的驱动方法，包括：提供第一装载脉冲TPO和第二装载脉冲TPE；根据第一装载脉冲TPO的从第一电平到第二电平的第一边沿和第二装载脉冲TPE的从第一电平到第二电平的第一边沿对多个显示数据进行锁存；将锁存的所述多个显示数据转换成对应的多个灰阶电压；以及经由输出缓冲器240、440的多个缓冲单元的输出端输出所述多个灰阶电压；其中，输出所述多个灰阶电压包括：将所述第一装载脉冲TPO提供给所述输出缓冲器240、440，使得所述输出缓冲器240、440根据所述第一装载脉冲TPO的紧接着所述第一边沿的从第二电平到第一电平的第二边沿而开始将奇数输出端的灰阶电压输出到对应的TFT源极，并且将所述第二装载脉冲TPE提供给所述输出缓冲器240、440，使得所述输出缓冲器240、440根据所述第二装载脉冲TPE的紧接着所述第一边沿的从第二电平到第一电平的第二边沿而开始将偶数输出端的灰阶电压输出到对应的TFT源极，至少所述第一装载脉冲TPO的第二边沿与所述第二装载脉冲TPE的第二边沿不同步。
应当理解，所述驱动方法的其他特征和优点已经体现在前面对于栅极驱动器200、400和驱动电路的描述中，并且因此在此不进行详细描述。
虽然前面的讨论包含若干特定的实现细节，但是这些不应解释为对任何发明或者可能要求保护的范围的限制，而应解释为对可能仅限于特定发明的特定实施例的特征的描述。在本说明书中不同的实施例中描述的特定特征也可以在单个实施例中以组合形式实现。与此相反，在单个实施例中描述的不同特征也可以在多个实施例中分别地或者以任何适当的子组合形式实现。此外，尽管前面可能将特征描述为以特定组合起作用，甚至最初也被如此要求保护，但是来自所要求保护的组合中的一个或多个特征在某些情况下也可以从该组合中排除，并且该要求保护的组合可以被导向子组合或子组合的变型。
鉴于前面的描述并结合阅读附图，对前述本发明的示例性实施例的各种修改和改动对于相关领域的技术人员可以变得显而易见。任何和所有修改仍将落入本发明的非限制性和示例性实施例的范围内。此外，属于本发明的这些实施例所属领域的技术人员，在得益于前面的描述和相关附图所给出的教导后，将会想到在此描述的本发明的其他 实施例。
因此，应当理解，本发明的实施例并不限于所公开的特定实施例，并且修改和其他的实施例也意图被包含在所附权利要求书的范围内。尽管此处使用了特定术语，但是它们仅在通用和描述性意义上使用，而非为了限制的目的。

Claims (25)

  1. 一种用于TFT-LCD的源极驱动器，包括：
    数据寄存器，用于寄存多个显示数据，所述多个显示数据对应于所述TFT-LCD的一行像素单元中的多个像素单元；
    数据锁存器，具有用于接收第一装载脉冲的第一端子和用于接收第二装载脉冲的第二端子，所述数据锁存器响应于第一装载脉冲的从第一电平到第二电平的第一边沿和第二装载脉冲的从第一电平到第二电平的第一边沿对所述数据寄存器中的多个显示数据进行锁存；
    数模转换器，用于将所述数据锁存器中锁存的多个显示数据转换成对应的多个灰阶电压；以及
    输出缓冲器，包括多个缓冲单元，用于经由所述多个缓冲单元的输出端输出所述多个灰阶电压；
    其中，所述第一装载脉冲被提供给所述输出缓冲器，使得所述输出缓冲器响应于所述第一装载脉冲的紧接着所述第一边沿的从第二电平到第一电平的第二边沿而开始将奇数输出端的灰阶电压输出到对应的TFT源极，并且
    其中，所述第二装载脉冲被提供给所述输出缓冲器，使得所述输出缓冲器响应于所述第二装载脉冲的紧接着所述第一边沿的从第二电平到第一电平的第二边沿而开始将偶数输出端的灰阶电压输出到对应的TFT源极，至少所述第一装载脉冲的第二边沿与所述第二装载脉冲的第二边沿不同步。
  2. 根据权利要求1所述的源极驱动器，其中，所述第一装载脉冲的第一电平被用作所述输出缓冲器的奇数缓冲单元的使能信号来使能所述灰阶电压从奇数输出端的输出，并且所述第二装载脉冲的第一电平被用作所述输出缓冲器的偶数缓冲单元的使能信号来使能所述灰阶电压从偶数输出端的输出。
  3. 根据权利要求1所述的源极驱动器，其中，所述输出缓冲器还包括多个开关元件，该多个开关元件中的每一个与所述输出缓冲器的多个缓冲单元的输出端中的相应一个串联，其中，所述第一装载脉冲被提供给与奇数输出端串联的开关元件的控制端，使得所述开关元件在所述第一装载脉冲的第一电平下导通并且所述第二装载脉冲被提供 给与偶数输出端串联的开关元件的控制端，使得所述开关元件在所述第二装载脉冲的第一电平下导通。
  4. 根据权利要求1所述的源极驱动器，还包括数据差异判断电路，用于在更新一行显示数据时判断所述数据寄存器中寄存的第n+1行中的多个显示数据与所述数据锁存器中锁存的第n行中的多个显示数据之间的相应差值中的至少一个或多个是否大于第一预定阈值，其中，所述数据差异判断电路根据不同的判断结果向所述TFT-LCD的时序控制器提供不同的输入。
  5. 根据权利要求4所述的源极驱动器，其中，所述数据差异判断电路包括用于将第n+1行中的所述多个显示数据与第n行中的所述多个显示数据分别相减的减法器和用于将减法结果中的每一个分别与第一预定阈值相比较的第一数值比较器。
  6. 根据权利要求5所述的源极驱动器，其中，所述数据差异判断电路还包括第一与门或第一或门，分别用于将所述第一数值比较器的输出结果中的每一个进行与运算或或运算，所述第一与门或第一或门的输出作为指示所述数据差异判断电路的判断结果的所述输入被提供给所述时序控制器。
  7. 根据权利要求5所述的源极驱动器，其中，所述数据差异判断电路还包括用于将所述第一数值比较器的输出结果中的每一个进行相加的加法器和用于将加法结果与第二预定阈值相比较的第二数值比较器，所述第二数值比较器的输出作为指示所述数据差异判断电路的判断结果的所述输入被提供给所述时序控制器。
  8. 根据权利要求1所述的源极驱动器，其中，所述第一装载脉冲和所述第二装载脉冲中的一个由另一个经延时而得到。
  9. 根据权利要求8所述的源极驱动器，还包括延时电路，其用于延迟原始装载脉冲一预定时间量，所述第一装载脉冲和所述第二装载脉冲中的一个是所述原始装载脉冲，另一个是经延迟的所述原始装载脉冲。
  10. 一种用于TFT-LCD的驱动电路，包括：
    至少一个如权利要求1所述的源极驱动器；以及
    时序控制器，其用于向所述至少一个源极驱动器提供第一装载脉冲和第二装载脉冲。
  11. 根据权利要求10所述的驱动电路，其中，所述时序控制器向所述输出缓冲器提供所述第一装载脉冲以将所述第一装载脉冲的第一电平用作所述输出缓冲器的奇数缓冲单元的使能信号来使能所述灰阶电压从奇数输出端的输出，并且所述时序控制器向所述输出缓冲器提供所述第二装载脉冲以将所述第二装载脉冲的第一电平用作所述输出缓冲器的偶数缓冲单元的使能信号来使能所述灰阶电压从偶数输出端的输出。
  12. 根据权利要求10所述的驱动电路，其中，所述输出缓冲器还包括多个开关元件，该多个开关元件中的每一个与所述输出缓冲器的多个缓冲单元的输出端中的相应一个串联，其中，所述时序控制器将所述第一装载脉冲提供给与奇数输出端串联的开关元件的控制端，使得所述开关元件在所述第一装载脉冲的第一电平下导通并且将所述第二装载脉冲提供给与偶数输出端串联的开关元件的控制端，使得所述开关元件在所述第二装载脉冲的第一电平下导通。
  13. 根据权利要求10所述的驱动电路，还包括数据差异判断电路，用于在更新一行显示数据时判断所述数据寄存器中寄存的第n+1行中的多个显示数据与所述数据锁存器中锁存的第n行中的多个显示数据之间的相应差值中的至少一个或多个是否大于第一预定阈值，其中，所述数据差异判断电路根据不同的判断结果向所述时序控制器提供不同的输入。
  14. 根据权利要求13所述的驱动电路，所述时序控制器根据来自所述数据差异判断电路的指示第n+1行中的所述多个显示数据与第n行中的所述多个显示数据的相应差值中的至少一个或多个大于第一预定阈值的所述输入而提供所述第一装载脉冲和第二装载脉冲。
  15. 根据权利要求13所述的驱动电路，其中，所述数据差异判断电路包括用于将第n+1行中的所述多个显示数据与第n行中的所述多个显示数据分别相减的减法器和用于将减法结果中的每一个分别与第一预定阈值相比较的第一数值比较器。
  16. 根据权利要求15所述的驱动电路，其中，所述数据差异判断电路还包括第一与门或第一或门，用于将所述第一数值比较器的输出结果中的每一个进行与运算或或运算，所述第一与门或第一或门的输出作为指示所述数据差异判断电路的判断结果的所述输入被提供给所 述时序控制器。
  17. 根据权利要求15所述的驱动电路，其中，所述数据差异判断电路还包括用于将所述第一数值比较器的输出结果中的每一个进行相加的加法器和用于将加法结果与第二预定阈值相比较的第二数值比较器，所述第二数值比较器的输出作为指示所述数据差异判断电路的判断结果的所述输入被提供给所述时序控制器。
  18. 根据权利要求16或17所述的驱动电路，其中，在多个所述源极驱动器的情况下，所述驱动电路还包括第二与门或第二或门，用于将来自所述多个源极驱动器中的每一个的数据差异判断电路的输出进行与运算或或运算，所述第二与门或第二或门的输出作为指示所述数据差异判断电路的最终判断结果的所述输入被提供给所述时序控制器。
  19. 根据权利要求10所述的驱动电路，其中，所述第一装载脉冲和所述第二装载脉冲中的一个由另一个经延时而得到。
  20. 根据权利要求19所述的驱动电路，还包括延时电路，其用于延迟所述时序控制器生成的原始装载脉冲一预定时间量，所述第一装载脉冲和所述第二装载脉冲中的一个是所述原始装载脉冲，另一个是经延迟的所述原始装载脉冲。
  21. 一种用于TFT-LCD的驱动方法，包括：
    提供第一装载脉冲和第二装载脉冲；
    根据第一装载脉冲的从第一电平到第二电平的第一边沿和第二装载脉冲的从第一电平到第二电平的第一边沿对多个显示数据进行锁存；
    将锁存的所述多个显示数据转换成对应的多个灰阶电压；以及
    经由输出缓冲器的多个缓冲单元的输出端输出所述多个灰阶电压；
    其中，输出所述多个灰阶电压包括：
    将所述第一装载脉冲提供给所述输出缓冲器，使得所述输出缓冲器根据所述第一装载脉冲的紧接着所述第一边沿的从第二电平到第一电平的第二边沿而开始将奇数输出端的灰阶电压输出到对应的TFT源极，并且
    将所述第二装载脉冲提供给所述输出缓冲器，使得所述输出缓冲 器根据所述第二装载脉冲的紧接着所述第一边沿的从第二电平到第一电平的第二边沿而开始将偶数输出端的灰阶电压输出到对应的TFT源极，至少所述第一装载脉冲的第二边沿与所述第二装载脉冲的第二边沿不同步。
  22. 根据权利要求21所述的驱动方法，其中，将所述第一装载脉冲提供给所述输出缓冲器包括：将所述第一装载脉冲的第一电平用作所述输出缓冲器的奇数缓冲单元的使能信号来使能所述灰阶电压从奇数输出端的输出，并且
    其中，将所述第二装载脉冲提供给所述输出缓冲器包括：将所述第二装载脉冲的第一电平用作所述输出缓冲器的偶数缓冲单元的使能信号来使能所述灰阶电压从偶数输出端的输出。
  23. 根据权利要求21所述的驱动方法，还包括提供多个开关元件，该多个开关元件中的每一个与所述输出缓冲器的多个缓冲单元的输出端中的相应一个串联，
    其中，将所述第一装载脉冲提供给所述输出缓冲器包括：将所述第一装载脉冲提供给与奇数输出端串联的开关元件的控制端，使得所述开关元件在所述第一装载脉冲的第一电平下导通，并且
    其中，将所述第二装载脉冲提供给所述输出缓冲器包括：将所述第二装载脉冲提供给与偶数输出端串联的开关元件的控制端，使得所述开关元件在所述第二装载脉冲的第一电平下导通。
  24. 根据权利要求21所述的驱动方法，还包括：
    在更新一行显示数据时判断第n+1行中的所述多个显示数据与第n行中的所述多个显示数据之间的差异是否为大，并且仅在所述判断的结果指示大的所述差异时，才提供所述第一装载脉冲和第二装载脉冲。
  25. 根据权利要求21所述的驱动方法，其中，所述第一装载脉冲和所述第二装载脉冲中的一个由另一个经延时而得到。
PCT/CN2015/090496 2015-06-19 2015-09-24 用于tft-lcd的源极驱动器、驱动电路及驱动方法 Ceased WO2016201818A1 (zh)

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EP3312828A4 (en) 2018-10-24
US9953559B2 (en) 2018-04-24
CN104867474A (zh) 2015-08-26

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