WO2016201874A1 - 阵列基板及其制作方法以及显示装置 - Google Patents

阵列基板及其制作方法以及显示装置 Download PDF

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Publication number
WO2016201874A1
WO2016201874A1 PCT/CN2015/094583 CN2015094583W WO2016201874A1 WO 2016201874 A1 WO2016201874 A1 WO 2016201874A1 CN 2015094583 W CN2015094583 W CN 2015094583W WO 2016201874 A1 WO2016201874 A1 WO 2016201874A1
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WIPO (PCT)
Prior art keywords
spacer
sub
electrode
array substrate
pixel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2015/094583
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English (en)
French (fr)
Inventor
杨小飞
杨玉清
辛燕霞
莫再隆
蒋学
牟勋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US15/110,230 priority Critical patent/US10025143B2/en
Priority to EP15874424.3A priority patent/EP3312668B1/en
Publication of WO2016201874A1 publication Critical patent/WO2016201874A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
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    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G02F1/13396—Spacers having different sizes
    • G—PHYSICS
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G—PHYSICS
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F1/1333—Constructional arrangements; Manufacturing methods
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    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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Definitions

  • Embodiments of the present invention relate to an array substrate, a method of fabricating the array substrate, and a display device including the array substrate.
  • the liquid crystal display device mainly includes an array substrate and an opposite substrate disposed opposite to each other, and a liquid crystal layer sandwiched between the array substrate and the opposite substrate.
  • a spacer is further disposed between the array substrate and the opposite substrate.
  • FIG. 1 is a schematic plan view of an array substrate according to a technique
  • FIG. 2 is a schematic cross-sectional view of a liquid crystal display device according to a technique, which is taken along line A-A' of FIG.
  • the array substrate includes a base substrate 01, and a buffer layer 02, an active layer 03, a gate insulating layer 04, and a gate line layer (including a gate line 05 and a gate electrode) which are sequentially disposed on the base substrate 01. G), interlayer insulating layer 06, data line layer (including data line 07, source S and drain D), passivation layer 08, and via hole 09, pixel electrode 010, and electrode disposed in passivation layer 08
  • the gate line 05 and the data line 07 cross each other to define a plurality of sub-pixels, each of which includes a thin film transistor and a pixel electrode.
  • the active layer 03, the gate G, the source S, and the drain D constitute the thin film transistor
  • the pixel electrode 010 is connected to the drain D of the thin film transistor through the via 09.
  • the opposite substrate includes another base substrate 016, and a black matrix 013, a passivation layer 014, and a spacer 015 which are sequentially disposed on the base substrate 016.
  • the spacers 015 are disposed on the opposite substrate and the top portions thereof abut against the flat regions of the array substrate between the adjacent two sub-pixels.
  • the size of a single sub-pixel becomes smaller and smaller; in this case, the area of the flat region of the array substrate between adjacent two sub-pixels is reduced due to the presence of the via 09 If the liquid crystal display device is subjected to an external force, the spacer 05 is extremely slidable into the via hole 09, and the alignment layer (not shown) on the surface of the array substrate is scratched during the sliding process.
  • the spacer 05 When the spacer 05 is slid into the via 09, it will be difficult to achieve a uniform gap between the array substrate and the opposite substrate and it is difficult to maintain the thickness of the liquid crystal layer.
  • the uniformity of the degree causes the display picture to be uneven and the display quality to be degraded; and when the alignment layer is scratched, the liquid crystal layer may be abnormally oriented, causing light leakage.
  • an array substrate includes: a base substrate; a plurality of gate lines and a plurality of data lines formed on the base substrate, the plurality of gate lines and the plurality of data lines crossing each other to define a plurality of sub-pixels, each of the sub-pixels including a thin film transistor and a pixel electrode, the plurality of sub-pixels including a first sub-pixel; a passivation layer formed on the base substrate and covering the gate line, the data line, and the thin film transistor, the passivation layer Providing a via hole in which the pixel electrode is formed on the passivation layer and connected to a drain or a source of the thin film transistor through the via hole; a first spacer, And disposed in the via of the first sub-pixel.
  • the plurality of sub-pixels further include a second sub-pixel
  • the array substrate further includes a second spacer disposed in a via of the second sub-pixel.
  • the height of the first spacer on the base substrate is greater than the height of the second spacer.
  • each of the sub-pixels further includes a common electrode and an inter-electrode insulating layer between the common electrode and the pixel electrode; the inter-electrode insulating layer has a portion on the first spacer instead of Having a portion on the second spacer; and/or the common electrode has a portion on the first spacer without a portion on the second spacer.
  • the height of the first spacer on the base substrate is the same as the height of the second spacer; each of the sub-pixels further includes a common electrode and the common electrode and the pixel electrode Inter-electrode insulating layer; the inter-electrode insulating layer has a portion on the first spacer without a portion on the second spacer; and/or the common electrode has a location The portion on the first spacer does not have a portion on the second spacer.
  • the array substrate further includes a third spacer; the third spacer is located above the gate line and/or the data line.
  • the array substrate further includes a shield electrode on the third spacer.
  • each of the sub-pixels further includes a common electrode and an inter-electrode insulating layer between the common electrode and the pixel electrode; the shielding electrode is disposed in the same layer as the common electrode.
  • each of the sub-pixels further includes a common electrode and an inter-electrode insulating layer between the common electrode and the pixel electrode; the inter-electrode insulating layer has a location a portion on the first spacer and the common electrode has a portion on the first spacer; the third spacer has a shield electrode thereon, and the shield electrode is in the same layer as the common electrode Settings.
  • a display device includes any of the array substrate, the counter substrate, and the liquid crystal layer as described above.
  • the opposite substrate is disposed opposite to the array substrate, wherein an end of the first spacer abuts on the opposite substrate.
  • the liquid crystal layer is located between the array substrate and the opposite substrate.
  • the counter substrate includes a color film layer having a portion above the first spacer.
  • a method of fabricating an array substrate includes: forming a plurality of gate lines and a plurality of data lines on the base substrate, the plurality of gate lines and the plurality of data lines crossing each other to define a plurality of sub-pixels, each of the sub-pixels including a thin film transistor and a pixel electrode, the plurality of sub-pixels including a first sub-pixel; a passivation layer covering the gate line, the data line, and the thin film transistor is formed on the base substrate, and the passivation layer is disposed a hole in which the pixel electrode is formed on the passivation layer and connected to a drain or a source of the thin film transistor through the via; and in the first sub-pixel A first spacer is formed in the hole.
  • FIG. 1 is a schematic plan view of an array substrate according to a technique
  • FIG. 2a and 2b are schematic cross-sectional views of a liquid crystal display device according to a technique taken along line A-A' of FIG. 1;
  • FIG. 3 is a plan view 1 of an array substrate according to an embodiment of the invention.
  • FIG. 4a and 4b are schematic cross-sectional views of an array substrate according to an embodiment of the present invention taken along line AA' of FIG. 3, wherein a height of the first spacer on the base substrate is greater than a height of the second spacer;
  • 5a and 5b are schematic cross-sectional views of an array substrate according to an embodiment of the present invention taken along line A-A' of FIG. 3, wherein a height of the first spacer on the base substrate is equal to a height of the second spacer;
  • FIG. 6 is a plan view 2 of an array substrate according to an embodiment of the invention.
  • FIG. 7a and 7b are schematic cross-sectional views of an array substrate according to an embodiment of the present invention taken along line A-A' of FIG. 6, wherein a third spacer is formed;
  • FIG. 8a and 8b are schematic cross-sectional views of an array substrate according to an embodiment of the present invention taken along line AA' of FIG. 6, wherein the height of the first spacer on the base substrate, the height of the second spacer, and The third spacer has the same height;
  • 9a and 9b are schematic cross-sectional views of a display device according to an embodiment of the present invention.
  • FIGS. 10a and 10b are schematic cross-sectional views of a display device according to an embodiment of the present invention.
  • FIG. 11a and 11b are schematic cross-sectional views of a display device according to an embodiment of the present invention.
  • 12a and 12b are schematic cross-sectional views of a display device according to an embodiment of the present invention.
  • FIG. 13a and 13b are schematic cross-sectional views of a display device according to an embodiment of the present invention.
  • 14a and 14b to 16a and 16b are schematic flowcharts 1 of a method for fabricating an array substrate according to an embodiment of the invention
  • 17a and 17b to 18a and 18b are schematic flow diagrams 2 of a method of fabricating an array substrate according to an embodiment of the invention
  • 19a and 19b to 20a and 20b are schematic flowcharts 3 of a method of fabricating an array substrate according to an embodiment of the invention.
  • an array substrate is provided.
  • 3 is a plan view of an array substrate according to an embodiment of the present invention.
  • FIGS. 4a and 4b are schematic cross-sectional views taken along line A-A' of FIG. 3 and 4a, FIG.
  • an array substrate includes: a base substrate 1; a plurality of gate lines 5 and a plurality of data lines 7 formed on the base substrate 1, the plurality of gates The line 5 and the plurality of data lines 7 cross each other to define a plurality of sub-pixels, each of the sub-pixels including a thin film transistor and a pixel electrode 10, the plurality of sub-pixels including a first sub-pixel; formed on the base substrate 1 and covered by a gate line 5, the data line 7 and a passivation layer 8 of the thin film transistor, wherein the passivation layer is provided with a via hole 9 in which the pixel electrode 10 is formed in the blunt
  • the via layer 8 is connected to the drain D or the source S of the thin film transistor through the via hole 9; and the first spacer 15 is disposed in the via hole of the first sub-pixel.
  • the end of the first spacer abuts on the opposite substrate, which can be used to maintain uniformity between the array substrate and the opposite substrate
  • the gap maintains the thickness uniformity of the liquid crystal layer sandwiched between the array substrate and the opposite substrate.
  • the first spacer is disposed in the via of the first sub-pixel. Therefore, even if the display device is subjected to an external force, the first spacer does not easily slide, so that the thickness unevenness of the liquid crystal layer and the alignment layer due to the sliding of the first spacer into the via hole can be avoided (not shown in the drawing)
  • the case where it is located on the surface of the array substrate facing the opposite substrate is scratched. Thereby, a uniform gap can be provided between the array substrate and the counter substrate, the thickness uniformity of the liquid crystal layer can be well maintained, light leakage caused by scratching of the alignment layer can be prevented, and display quality can be improved.
  • the thin film transistor includes an active layer 3, a gate G, a source S, and a drain D, the gate G is connected to or formed integrally with the gate line 5, and the source S or the drain D is connected to the data line 7 Or formed integrally with the data line 7, the drain D or the source S is connected to the pixel electrode 10.
  • the buffer layer 2 is first formed on the base substrate 1 to prevent impurities in the base substrate 1 from entering the active layer 3 and improving The film quality of the active layer 3; and the active layer 3, the gate insulating layer 4, the gate line layer (including the gate line 5 and the gate G), the interlayer insulating layer 6, and the data line layer (including the data line 7, A source S and a drain D) are sequentially formed on the buffer layer 2.
  • the array substrate according to the embodiment of the present invention may not employ a buffer layer, and the active layer 3, the gate insulating layer 4, and the gate line layer (including the gate line 5 and the gate line G)
  • the interlayer insulating layer 6, and the data line layer (including the data line 7 and the source S and the drain D) may be provided in any known stacking order.
  • the thin film transistor may be of a bottom gate type, a top gate type, or of any known type.
  • the plurality of sub-pixels further includes a second sub-pixel different from the first sub-pixel
  • the array substrate according to the embodiment of the present invention further includes a second A spacer 16 is disposed in the via 9 of the second sub-pixel.
  • the height of the first spacer 15 on the base substrate 1 is greater than the height of the second spacer 16; in this case, the first spacer 15 can be regarded as the main spacer.
  • the cushion, and the second spacer 16 can be regarded as a secondary spacer.
  • the liquid crystal layer shrinks and the volume becomes small. If the number of spacers is too large, the opposite substrate does not substantially deform, and if the display device is suddenly subjected to an external force, a vacuum is generated in the liquid crystal layer.
  • Bubbles resulting in poor low temperature bubbles; if the number of spacers is reduced, low temperature bubble defects can be avoided to a certain extent, but the support effect of the spacers on the opposite substrate is weakened, and a large external force is applied to the opposite substrate. When it acts, it will produce a large deformation and it will not easily return to its original state, resulting in poor pressing.
  • the first spacer 15 and the second spacer 16 are disposed, and the height of the first spacer 15 is greater than the height of the second spacer 16, so that the above can be avoided.
  • the low temperature bubble defect can avoid the above pressing failure.
  • the second spacer 16 since the second spacer 16 is disposed in the via 9 of the second sub-pixel, the second spacer 16 can be prevented from sliding and the alignment layer is scratched, so that the liquid crystal alignment abnormality caused by the scratch of the alignment layer can be avoided. Light leaks.
  • the first spacer 15 and the second spacer 16 may be formed by two patterning processes using two ordinary masks; In order to reduce the number of masks and simplify the fabrication process, the first spacers 15 and the second spacers 16 may be formed by one patterning process using a two-tone mask.
  • each sub-pixel further includes a common electrode 12 and is located The inter-electrode insulating layer 11 between the common electrode 12 and the pixel electrode 10.
  • the inter-electrode insulating layer 11 has a portion on the first spacer 15 without a portion on the second spacer 16, and/or the common electrode 12 has a portion on the first spacer 15 There is no portion on the second spacer 16.
  • the first spacer 15 and the second spacer 16 may be formed by one patterning process using a two-tone mask; however, in order to effectively avoid low-temperature bubble defects and poor pressing, it is required in the first spacer 15 and A sufficiently large height difference is formed between the second spacers 16, which increases the process difficulty of the patterning process using the two-tone mask.
  • the inter-electrode insulating layer 11 by having the inter-electrode insulating layer 11 have a portion on the first spacer 15 without having a portion on the second spacer 16 and/or having the common electrode 12
  • the portion on the first spacer 15 without the portion on the second spacer 16 can reduce the process of patterning using the two-tone mask while effectively avoiding low-temperature bubble defects and poor pressing.
  • the design flexibility of the first spacer 15 and the second spacer 16 is required and increased.
  • the first spacer 15 and the interelectrode insulating layer 11 and/or the common electrode 12 located thereon may be regarded as a main spacer.
  • portion of the inter-electrode insulating layer 11 on the first spacer 15 may be disconnected or connected with other portions of the inter-electrode insulating layer 11, and the common electrode 12 is located on the first spacer 15. Portions may be disconnected or connected to other portions of the common electrode 12.
  • the inter-electrode insulating layer 11 and the common electrode 12 are both formed on the first spacer 15 in FIG. 4a; however, the height of the first spacer 15 is greater than the second spacer. In the case of the height of 16, the first spacer 15 may be formed without forming the inter-electrode insulating layer 11 or the common electrode 12 or only one of the inter-electrode insulating layer 11 and the common electrode 12 may be formed on the first spacer 15 on.
  • FIGS. 5a and 5b are schematic cross-sectional views of an array substrate according to an embodiment of the present invention taken along line AA' of FIG. 3, wherein the height of the first spacer 15 on the base substrate 1 is equal to the second spacer 16 the height of. Since the height of the first spacer 15 is equal to the height of the second spacer 16, the first spacer 15 and the second spacer 16 can be formed by one patterning process using a common mask, which can reduce the process difficulty and process. cost. Further, as shown, for example, in FIGS.
  • the inter-electrode insulating layer 11 has a portion on the first spacer 15 without a portion on the second spacer 16 and/or the common electrode 12 has The portion on the first spacer 15 does not have a portion on the second spacer 16, so that low-temperature bubble defects and poor pressing can be avoided as well.
  • the first spacer 15 and the interelectrode insulating layer 11 and/or the common electrode 12 located thereon may be regarded as a main spacer.
  • portion of the inter-electrode insulating layer 11 on the first spacer 15 may be disconnected or connected with other portions of the inter-electrode insulating layer 11, and the common electrode 12 is located on the first spacer 15. Portions may be disconnected or connected to other portions of the common electrode 12.
  • inter-electrode insulating layer 11 and the common electrode 12 are both formed on the first spacer 15 in FIG. 5a; however, the height of the first spacer 15 is equal to the second spacer. In the case of the height of 16, only one of the inter-electrode insulating layer 11 and the common electrode 12 may be formed on the first spacer 15.
  • the first spacer 15 and the second spacer 16 may be neither disposed in the via of one or some sub-pixels.
  • the distribution ratio of the first spacer 15 to the second spacer 16 is, for example, 1:10 to 1:100, and further, for example, 1:18 or 1:36.
  • FIG. 6 is a plan view 2 of an array substrate according to an embodiment of the present invention
  • FIGS. 7a and 7b are schematic cross-sectional views taken along line A-A' of FIG. 6.
  • the array substrate according to an embodiment of the present invention further includes a third spacer 17 on the data line 7 and/or the gate line 5. Since the third spacer 17 has a certain height, the power line between the adjacent two sub-pixels can be blocked, so that electric field interference between adjacent sub-pixels can be reduced.
  • an array substrate includes a display area in which the plurality of sub-pixels are disposed and a peripheral area located around the display area.
  • the length of the third spacer 17 is less than or equal to the length of the display area in the direction in which the third spacer 17 extends, that is, the third spacer 17 is located in the display area.
  • an array substrate may include a shield electrode 18 on the third spacer 17 to further reduce electric field interference between adjacent sub-pixels.
  • no voltage may be applied to the shield electrode 18.
  • a voltage may be applied to the shield electrode 18, such as a low level voltage, further such as a zero level voltage.
  • the shield electrode 18 may be disposed in the same layer as the common electrode 12, so that the shield electrode 18 and the common electrode 12 may be simultaneously formed by one patterning process, simplifying the fabrication process.
  • the shield electrode 18 may be connected to the common electrode 12 such that a common voltage is applied to the shield electrode 18.
  • the shield electrode 18 can be disconnected from the common electrode 12 so that the shield electrode 18 and the common electrode 12 can be driven separately.
  • a portion of the inter-electrode insulating layer 11 may be further located between the shield electrode 18 and the third spacer 17.
  • a portion of the interelectrode insulating layer 11 between the shield electrode 18 and the third spacer 17 may be disconnected or connected to other portions of the interelectrode insulating layer 11.
  • the shield electrode 18 covers the upper surface and the side surface of the third spacer 17.
  • the first spacer 15, the second spacer 16, and the third spacer 17 may be made to have the same height, as shown in FIGS. 8a and 8b; in this case, The conventional single-tone mask simultaneously forms the first spacer 15, the second spacer 16, and the third spacer 17 by one patterning process.
  • the interelectrode insulating layer 11 has a portion on the first spacer 15 and the common electrode 12 has a portion on the first spacer 15, and a shield electrode 18 disposed in the same layer as the common electrode 12 is formed in The third spacer 17; thus, the first spacer 15 and the interelectrode insulating layer 11 and the common electrode 12 located thereon can be regarded as a main spacer as a whole, and the third spacer 17 and the upper spacer 17 thereon
  • the shielding electrode 18 can be regarded as a first sub-spacer as a whole, and the second spacer 16 can be regarded as a second sub-spacer, the height of the main spacer, the height of the first sub-spacer and the second sub-spacer
  • the height of the mat is distributed in a stepped manner, whereby low-temperature bubble defects and poor pressing can be better avoided.
  • the insulating layer 6, the data line layer (including the data line 7, the source S and the drain D), the passivation layer 8, the pixel electrode 10, the inter-electrode insulating layer 11, and the common electrode 12 may be formed by any known materials and methods. , will not repeat them here.
  • the active layer 3 is formed of low temperature polysilicon.
  • the passivation layer 8 is formed of an organic resin such as an acrylic resin.
  • the spacers are formed of an organic resin material such as a negative PR glue.
  • the materials forming the first spacer 15, the second spacer 16, and the third spacer 17 may be the same or different.
  • first spacer 15 and the second spacer 16 formed in the via 9 are directly in contact with the pixel electrode 10 formed in the via 9 in FIGS. 3 to 8b;
  • embodiments of the present invention are not limited thereto, and other insertion layers may be formed between the first spacer 15, the second spacer 16, and the pixel electrode 10 as needed.
  • a display device includes: an array substrate as described above; an opposite substrate disposed opposite to the array substrate, wherein an end of the first spacer abuts on the opposite substrate; and a liquid crystal layer on the array substrate and the opposite substrate between. Since the display device according to an embodiment of the present invention includes the array substrate as described above, even if the display device is received Force, the first spacer does not slide easily, so that the thickness of the liquid crystal layer due to the sliding of the first spacer into the via hole and the alignment layer (not shown in the figure, which is located on the array substrate) can be avoided. The case where the surface facing the opposite substrate is scratched. Thereby, a uniform gap can be provided between the array substrate and the counter substrate, the thickness uniformity of the liquid crystal layer can be well maintained, light leakage caused by scratching of the alignment layer can be prevented, and display quality can be improved.
  • Figures 9a and 9b, Figures 10a and 10b, Figures 11a and 11b, Figures 12a and 12b, and Figures 13a and 13b are schematic cross-sectional views of a display device in accordance with an embodiment of the present invention.
  • the opposite substrate includes a base substrate 20, and a black matrix 13 and a passivation layer 14, which are sequentially formed on the base substrate 20, a first spacer 15, a second spacer 16, and a first spacer
  • the three spacers 17 are all located in the area covered by the black matrix 13.
  • the display device shown in Figures 9a and 9b uses the array substrate shown in Figures 4a and 4b, and the display device shown in Figures 10a and 10b uses the array substrate shown in Figures 5a and 5b, and the display shown in Figures 11a and 11b.
  • the device uses the array substrate shown in Figs. 7a and 7b, and the display device shown in Figs. 12a and 12b uses the array substrate shown in Figs. 8a and 8b, and therefore will not be described again.
  • the display device shown in Figures 13a and 13b is substantially identical to the display device shown in Figures 9a and 9b except for the opposite substrate.
  • the opposite substrate further includes a color film layer 19.
  • the color film layer 19 has a portion above the first spacer 15 without a portion above the second spacer 16, thereby also helping to avoid low temperature bubble defects and poor pressing.
  • the process requirements for the patterning process using the two-tone mask can be further reduced and the design flexibility of the first spacer 15 and the second spacer 16 can be increased.
  • the opposite substrate shown in FIGS. 13a and 13b can be used in place of the opposing substrates shown in FIGS. 10a and 10b, FIGS. 11a and 11b, and FIGS. 12a and 12b.
  • the display device may be any product or component having a display function such as a liquid crystal display panel, a liquid crystal display device, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a liquid crystal display panel, a liquid crystal display device, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a method of fabricating an array substrate comprises: forming a plurality of gate lines 5 and a plurality of data lines 7 on the base substrate 1, the plurality of gate lines 5 and the plurality of data lines 7 crossing each other to define a plurality of sub-pixels, each of the sub-pixels
  • the pixel includes a thin film transistor and a pixel electrode 10, the plurality of sub-pixels including a first sub-pixel; and a passivation layer 8 covering the gate line 5, the data line 7, and the thin film transistor is formed on the base substrate 1
  • Blunt A via 9 is provided in the layer 8, in which the pixel electrode 10 is formed on the passivation layer 8 and connected to the drain D or source of the thin film transistor through the via 9 a pole S; and a first spacer 15 formed in the via 9 of the first sub-pixel.
  • the first spacer is formed in a via of the first sub-pixel. Therefore, even if the display device formed by the array substrate and the counter substrate is subjected to an external force, the first spacer does not easily slide, thereby avoiding the thickness of the liquid crystal layer caused by the sliding of the first spacer into the via hole.
  • the uneven and oriented layer (not shown in the drawing, which is located on the surface of the array substrate facing the opposite substrate) is scratched. Thereby, a uniform gap can be provided between the array substrate and the counter substrate, the thickness uniformity of the liquid crystal layer can be well maintained, light leakage caused by scratching of the alignment layer can be prevented, and display quality can be improved.
  • the plurality of sub-pixels further includes a second sub-pixel
  • the method of fabricating the array substrate further includes: forming a second spacer 16 in the via 9 of the second sub-pixel.
  • FIGS. 14a and 14b to 16a and 16b are schematic flowcharts 1 of a method of fabricating an array substrate according to an embodiment of the invention.
  • a buffer layer 2 is formed on the base substrate 1, and an active layer 3, a gate insulating layer 4, a gate line layer (including a gate line 5 and a gate G) are sequentially formed on the buffer layer,
  • the active layer 3, the gate G, the source S, and the drain D constitute a thin film transistor, and the pixel electrode 10 is connected to the drain D or the source S of the thin film transistor through the via 9 in the passivation layer 8.
  • Each of the above film layers may be formed by any known materials and methods, and will not be described herein.
  • the order of laminating the above respective film layers is not limited to the order shown in Figs. 14a and 14b, and can be adjusted according to actual needs, and will not be described herein.
  • a spacer material layer (for example, formed of PR glue and having a thickness of 4-6 ⁇ m) is formed, and the spacer material layer is patterned using a two-tone mask (for example, a halftone mask and a gray tone mask).
  • a two-tone mask for example, a halftone mask and a gray tone mask.
  • the method for fabricating the array substrate further includes: forming an inter-electrode insulating layer 11 on the pixel electrode 10, the inter-electrode insulating layer 11 having a portion on the first spacer 15 without having a second spacer
  • the portion on 16 is shown in Figures 16a and 16b.
  • the method of fabricating the array substrate further includes: forming a common electrode 12 on the inter-electrode insulating layer 11, the common electrode 12 having a portion on the first spacer 15 without being located on the second spacer 16 Part of which can be obtained
  • FIGS. 14a and 14b are schematic flow diagrams 2 of a method of fabricating an array substrate according to an embodiment of the invention.
  • a spacer material layer for example, formed of PR glue and having a thickness of 4-6 ⁇ m
  • the first spacer 15 and the second spacer 16 are simultaneously formed by one patterning process, and the height of the first spacer 15 is equal to the height of the second spacer 16, as shown in Figs. 17a and 17b.
  • the method for fabricating the array substrate further includes: forming an inter-electrode insulating layer 11 on the pixel electrode 10, the inter-electrode insulating layer 11 having a portion on the first spacer 15 without having a second spacer
  • the portion on 16 is shown in Figures 18a and 18b.
  • the method of fabricating the array substrate further includes: forming a common electrode 12 on the inter-electrode insulating layer 11, the common electrode 12 having a portion on the first spacer 15 without being located on the second spacer 16
  • the portion of the array substrate shown in Figures 5a and 5b can thus be obtained.
  • FIGS. 19a and 19b to 20a and 20b are schematic flowcharts 3 of a method of fabricating an array substrate according to an embodiment of the invention.
  • a first spacer 15, a second spacer 16, and a third spacer 17 are formed as shown in Figs. 19a and 19b.
  • the first spacer 15, the second spacer 16, and the third spacer 17 may be formed by three patterning processes using three masks.
  • the first spacer 15 and the second spacer 16 may be formed by one patterning process using a two-tone mask, and then the third spacer 17 may be formed by one patterning process using a single-tone mask.
  • the first spacer 15, the second spacer 16, and the third spacer 17 may be made to have the same height, so that the first color mask can be used to form the first one by one patterning process.
  • the method for fabricating the array substrate further includes: forming an inter-electrode insulating layer 11 on the pixel electrode 10, the inter-electrode insulating layer 11 having a portion on the first spacer 15 without having a second spacer The portion on 16 is shown in Figures 20a and 20b.
  • the method of fabricating the array substrate further includes: forming a common electrode 12 on the inter-electrode insulating layer 11, the common electrode 12 having a portion on the first spacer 15 without being located on the second spacer 16 Further, the method of fabricating the array substrate further includes: forming a shield electrode 18 on the third spacer 17, whereby the array substrate shown in FIGS. 7a and 7b can be obtained.
  • the common electrode 12 and the shield electrode 18 are simultaneously formed by patterning a common electrode material layer.

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Abstract

一种阵列基板及其制作方法以及显示装置。该阵列基板包括：基底基板(1)；形成在所述基底基板(1)上的多条栅线(5)和多条数据线(7)，所述多条栅线(5)和所述多条数据线(7)彼此交叉限定多个子像素，每个子像素包括薄膜晶体管和像素电极(10)，所述多个子像素包括第一子像素；形成在所述基底基板(1)上且覆盖所述栅线(5)、所述数据线(7)和所述薄膜晶体管的钝化层(8)，所述钝化层(8)中设置有过孔(9)，在所述每个子像素中所述像素电极(10)形成在所述钝化层(8)上且通过所述过孔(9)连接到所述薄膜晶体管的漏极或源极；第一隔垫物(15)，设置在所述第一子像素的过孔(9)中。可以使阵列基板和对向基板之间具有均匀的间隙，可以很好地维持液晶层的厚度均匀性，防止取向层划伤而引起的漏光，提高显示质量。

Description

阵列基板及其制作方法以及显示装置 技术领域
本发明的实施例涉及阵列基板，该阵列基板的制作方法，以及包括该阵列基板的显示装置。
背景技术
目前，液晶显示装置在平板显示器市场中占主导地位。液晶显示装置主要包括相对设置的阵列基板和对向基板，以及夹持在阵列基板和对向基板之间的液晶层。为了控制阵列基板和对向基板之间具有均匀的间隙且保持液晶层厚度的均匀性，在阵列基板和对向基板之间还设置有隔垫物。
图1为根据一种技术的阵列基板的平面示意图；图2为根据一种技术的液晶显示装置的截面示意图，该截面示意图沿图1的A-A’线截取。如图1和图2所示，阵列基板包括基底基板01，以及依次设置在基底基板01上的缓冲层02、有源层03、栅绝缘层04、栅线层(包括栅线05和栅极G)、层间绝缘层06、数据线层(包括数据线07、源极S及漏极D)、钝化层08和设置在钝化层08中的过孔09、像素电极010、电极间绝缘层011以及公共电极012。栅线05和数据线07彼此交叉限定多个子像素，每个子像素包括薄膜晶体管和像素电极。在每个子像素中，有源层03、栅极G、源极S及漏极D构成所述薄膜晶体管，像素电极010通过过孔09连接到薄膜晶体管的漏极D。对向基板包括另一基底基板016，以及依次设置在基底基板016上的黑矩阵013、钝化层014以及隔垫物015。
继续参照图1和图2，隔垫物015设置在对向基板上且其顶部抵靠在阵列基板的位于相邻两个子像素之间的平坦区域上。随着液晶显示装置分辨率的增加，单个子像素的尺寸越来越小；在此情况下，由于过孔09的存在，阵列基板的位于相邻两个子像素之间的平坦区域的面积减小，如果液晶显示装置受到外力的作用，隔垫物05极易滑动到过孔09中，并且在滑动的过程中划伤位于阵列基板表面的取向层(未示出)。当隔垫物05滑动到过孔09中时，将难以在阵列基板和对向基板之间实现均匀的间隙且难以保持液晶层厚 度的均匀性，导致显示画面不均匀，显示质量下降；而当取向层被划伤时，液晶层会出现取向异常，引起漏光。
发明内容
根据本发明的实施例，提供一种阵列基板。该阵列基板包括：基底基板；形成在所述基底基板上的多条栅线和多条数据线，所述多条栅线和所述多条数据线彼此交叉限定多个子像素，每个子像素包括薄膜晶体管和像素电极，所述多个子像素包括第一子像素；形成在所述基底基板上且覆盖所述栅线、所述数据线和所述薄膜晶体管的钝化层，所述钝化层中设置有过孔，在所述每个子像素中所述像素电极形成在所述钝化层上且通过所述过孔连接到所述薄膜晶体管的漏极或源极；第一隔垫物，设置在所述第一子像素的过孔中。
例如，所述多个子像素还包括第二子像素，并且所述阵列基板还包括第二隔垫物，所述第二隔垫物设置在所述第二子像素的过孔中。
例如，在所述基底基板上所述第一隔垫物的高度大于所述第二隔垫物的高度。
例如，所述每个子像素还包括公共电极和位于所述公共电极与所述像素电极之间的电极间绝缘层；所述电极间绝缘层具有位于所述第一隔垫物上的部分而不具有位于所述第二隔垫物上的部分；并且/或者所述公共电极具有位于所述第一隔垫物上的部分而不具有位于所述第二隔垫物上的部分。
例如，在所述基底基板上所述第一隔垫物的高度与所述第二隔垫物的高度相同；所述每个子像素还包括公共电极和位于所述公共电极与所述像素电极之间的电极间绝缘层；所述电极间绝缘层具有位于所述第一隔垫物上的部分而不具有位于所述第二隔垫物上的部分；并且/或者所述公共电极具有位于所述第一隔垫物上的部分而不具有位于所述第二隔垫物上的部分。
例如，所述阵列基板还包括第三隔垫物；所述第三隔垫物位于所述栅线和/或数据线的上方。
例如，所述阵列基板还包括位于所述第三隔垫物上的屏蔽电极。
例如，所述每个子像素还包括公共电极和位于所述公共电极与所述像素电极之间的电极间绝缘层；所述屏蔽电极与所述公共电极同层设置。
例如，在所述基底基板上所述第一隔垫物的高度、所述第二隔垫物的高 度和所述第三隔垫物的高度相同；所述每个子像素还包括公共电极和位于所述公共电极与所述像素电极之间的电极间绝缘层；所述电极间绝缘层具有位于所述第一隔垫物上的部分且所述公共电极具有位于所述第一隔垫物上的部分；所述第三隔垫物上具有屏蔽电极，所述屏蔽电极与所述公共电极同层设置。
根据本发明的实施例，提供一种显示装置。该显示装置包括：如上所述的任一种阵列基板、对向基板和液晶层。所述对向基板与所述阵列基板相对设置，其中所述第一隔垫物的端部抵靠在所述对向基板上。所述液晶层位于所述阵列基板与所述对向基板之间。
例如，所述对向基板包括彩膜层，所述彩膜层具有位于所述第一隔垫物上方的部分。
根据本发明的实施例，提供一种阵列基板的制作方法。该阵列基板的制作方法包括：在基底基板上形成多条栅线和多条数据线，所述多条栅线和所述多条数据线彼此交叉限定多个子像素，每个子像素包括薄膜晶体管和像素电极，所述多个子像素包括第一子像素；在所述基底基板上形成覆盖所述栅线、所述数据线和所述薄膜晶体管的钝化层，所述钝化层中设置有过孔，在所述每个子像素中所述像素电极形成在所述钝化层上且通过所述过孔连接到所述薄膜晶体管的漏极或源极；以及在所述第一子像素的过孔中形成第一隔垫物。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1为根据一种技术的阵列基板的平面示意图；
图2a和图2b为沿图1的A-A’线截取的根据一种技术的液晶显示装置的截面示意图；
图3为根据本发明实施例的阵列基板的平面示意图一；
图4a和图4b为沿图3的A-A’线截取的根据本发明实施例的阵列基板的截面示意图，其中在基底基板上第一隔垫物的高度大于第二隔垫物的高度；
图5a和图5b为沿图3的A-A’线截取的根据本发明实施例的阵列基板的截面示意图，其中在基底基板上第一隔垫物的高度等于第二隔垫物的高度；
图6为根据本发明实施例的阵列基板的平面示意图二；
图7a和图7b为沿图6的A-A’线截取的根据本发明实施例的阵列基板的截面示意图，其中形成了第三隔垫物；
图8a和图8b为沿图6的A-A’线截取的根据本发明实施例的阵列基板的截面示意图，其中在基底基板上第一隔垫物的高度、第二隔垫物的高度和第三隔垫物的高度相同；
图9a和9b为根据本发明实施例的显示装置的截面示意图一；
图10a和10b为根据本发明实施例的显示装置的截面示意图二；
图11a和11b为根据本发明实施例的显示装置的截面示意图三；
图12a和12b为根据本发明实施例的显示装置的截面示意图四；
图13a和13b为根据本发明实施例的显示装置的截面示意图五；
图14a和14b至图16a和16b为根据本发明实施例的阵列基板的制作方法的流程示意图一；
图17a和17b至图18a和18b为根据本发明实施例的阵列基板的制作方法的流程示意图二；以及
图19a和19b至图20a和20b为根据本发明实施例的阵列基板的制作方法的流程示意图三。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本发明专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该” 等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现在“包括”或者“包含”前面的元件或者物件涵盖出现在“包括”或者“包含”后面列举的元件或者物件及其等同，并不排除其他元件或者物件。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
根据本发明的实施例，提供一种阵列基板。图3为根据本发明实施例的阵列基板的平面示意图；图4a和图4b为沿图3的A-A’线截取的截面示意图。结合图3和图4a、图4b，根据本发明实施例的阵列基板包括：基底基板1；形成在所述基底基板1上的多条栅线5和多条数据线7，所述多条栅线5和所述多条数据线7彼此交叉限定多个子像素，每个子像素包括薄膜晶体管和像素电极10，所述多个子像素包括第一子像素；形成在所述基底基板1上且覆盖所述栅线5、所述数据线7和所述薄膜晶体管的钝化层8，所述钝化层中设置有过孔9，在所述每个子像素中所述像素电极10形成在所述钝化层8上且通过所述过孔9连接到所述薄膜晶体管的漏极D或源极S；以及第一隔垫物15，设置在所述第一子像素的过孔中。
在根据本发明实施例的阵列基板与对向基板对盒形成显示装置之后，第一隔垫物的端部抵靠在对向基板上，可以用于保持阵列基板和对向基板之间具有均匀的间隙并维持夹持在阵列基板与对向基板之间的液晶层的厚度均匀性。
在根据本发明实施例阵列基板中，第一隔垫物设置在第一子像素的过孔中。因此，即使显示装置受到外力，第一隔垫物也不会轻易滑动，从而可以避免由于第一隔垫物滑动到过孔中造成的液晶层厚度不均匀及取向层(在图中未示出，其位于阵列基板的面向对向基板的表面上)被划伤的情形。由此，可以使阵列基板和对向基板之间具有均匀的间隙，可以很好地维持液晶层的厚度均匀性，防止取向层划伤而引起的漏光，提高显示质量。
例如，薄膜晶体管包括有源层3、栅极G、源极S和漏极D，栅极G连接到栅线5或与栅线5一体形成，源极S或漏极D连接到数据线7或与数据线7一体形成，漏极D或源极S连接到像素电极10。
例如，如图4a和4b所示，在根据本发明实施例的阵列基板中，缓冲层2首先形成基底基板1上以防止基底基板1中的杂质进入到有源层3并改善 有源层3的膜层质量；并且有源层3、栅绝缘层4、栅线层(包括栅线5和栅极G)、层间绝缘层6、以及数据线层(包括数据线7、源极S和漏极D)依次形成在缓冲层2上。然而，本发明实施例并不局限于此，根据本发明实施例的阵列基板可以不采用缓冲层，并且有源层3、栅极绝缘层4、栅线层(包括栅线5和栅极G)、层间绝缘层6、以及数据线层(包括数据线线7与源极S和漏极D)这些层可以采用任何已知的层叠顺序来设置。相应地，在根据本发明实施例的阵列基板中，薄膜晶体管可以为底栅型、顶栅型或任何已知的类型。
例如，进一步参见图3和图4a、图4b，所述多个子像素还包括第二子像素，该第二子像素不同于上述第一子像素，根据本发明实施例的阵列基板还包括第二隔垫物16，该第二隔垫物16设置在第二子像素的过孔9中。
例如，如图4a和4b所示，在所述基底基板1上第一隔垫物15的高度大于第二隔垫物16的高度；在此情形下，第一隔垫物15可以看做主隔垫物，而第二隔垫物16可以看做副隔垫物。通常地，在低温时液晶层会收缩而体积会变小，如果隔垫物设置的数量过多，对向基板基本不产生形变，这时如果显示装置突然受到外力冲击，液晶层中会产生真空气泡，从而导致低温气泡不良；如果减少隔垫物的数量，可以在一定程度上避免低温气泡不良，但却使隔垫物对对向基板的支撑作用减弱，当对向基板受到较大的外力作用时会产生较大的形变且不易回复原状，从而导致按压不良产生。在根据本发明实施例的阵列基板中，设置了第一隔垫物15和第二隔垫物16，第一隔垫物15的高度大于第二隔垫物16的高度，这样既可以避免上述的低温气泡不良又可以避免上述的按压不良。
另外，由于第二隔垫物16设置在第二子像素的过孔9中，可以防止第二隔垫物16滑动而划伤取向层，从而可以避免由于取向层划伤引起的液晶取向异常和漏光。
在第一隔垫物15的高度大于第二隔垫物16的高度的情形下，第一隔垫物15和第二隔垫物16可以采用两块普通掩模板通过两次构图工艺形成；然而，为了减少掩模板的数量并简化制作工艺，第一隔垫物15和第二隔垫物16可以采用双色调掩模板通过一次构图工艺形成。
例如，进一步参见图4a和图4b，每个子像素还包括公共电极12和位于 公共电极12与像素电极10之间的电极间绝缘层11。例如，电极间绝缘层11具有位于第一隔垫物15上的部分而不具有位于第二隔垫物16上的部分，并且/或者公共电极12具有位于第一隔垫物15上的部分而不具有位于第二隔垫物16上的部分。如上所述，第一隔垫物15和第二隔垫物16可以采用双色调掩模板通过一次构图工艺形成；然而，为了有效避免低温气泡不良和按压不良，需要在第一隔垫物15和第二隔垫物16之间形成足够大的高度差，这会增大采用双色调掩模板的构图工艺的工艺难度。在根据本发明实施例的阵列基板中，通过使电极间绝缘层11具有位于第一隔垫物15上的部分而不具有位于第二隔垫物16上的部分并且/或者使公共电极12具有位于第一隔垫物15上的部分而不具有位于第二隔垫物16上的部分，可以在有效地避免低温气泡不良和按压不良的同时，降低对采用双色调掩模板的构图工艺的工艺要求并增加第一隔垫物15和第二隔垫物16的设计灵活性。在此情形下，可以将第一隔垫物15及位于其上的电极间绝缘层11和/或公共电极12整体看做主隔垫物。
需要说明的是，电极间绝缘层11的位于第一隔垫物15上的部分可以与电极间绝缘层11的其他部分断开或连接，并且公共电极12的位于第一隔垫物15上的部分可以与公共电极12的其他部分断开或连接。
需要说明的是，尽管在图4a中示出了电极间绝缘层11及公共电极12均形成在第一隔垫物15上；然而，在第一隔垫物15的高度大于第二隔垫物16的高度的情形下，第一隔垫物15上可以既不形成电极间绝缘层11也不形成公共电极12或者仅电极间绝缘层11和公共电极12之一形成在第一隔垫物15上。
图5a和图5b为沿图3的A-A’线截取的根据本发明实施例的阵列基板的截面示意图，其中在基底基板1上第一隔垫物15的高度等于第二隔垫物16的高度。由于第一隔垫物15的高度等于第二隔垫物16的高度，第一隔垫物15和第二隔垫物16可以采用普通掩模板通过一次构图工艺形成，这样可以降低工艺难度和工艺成本。进一步地，例如如图5a和图5b所示，电极间绝缘层11具有位于第一隔垫物15上的部分而不具有位于第二隔垫物16上的部分并且/或者公共电极12具有位于第一隔垫物15上的部分而不具有位于第二隔垫物16上的部分，这样一来同样也可以避免低温气泡不良和按压不良。在 此情形下，可以将第一隔垫物15及位于其上的电极间绝缘层11和/或公共电极12整体看做主隔垫物。
需要说明的是，电极间绝缘层11的位于第一隔垫物15上的部分可以与电极间绝缘层11的其他部分断开或连接，并且公共电极12的位于第一隔垫物15上的部分可以与公共电极12的其他部分断开或连接。
需要说明的是，尽管在图5a中示出了电极间绝缘层11及公共电极12均形成在第一隔垫物15上；然而，在第一隔垫物15的高度等于第二隔垫物16的高度的情形下，可以仅电极间绝缘层11和公共电极12之一形成在第一隔垫物15上。
需要说明的是，在根据本发明实施例的阵列基板中，某个或某些子像素的过孔中可以既不设置第一隔垫物15也不设置第二隔垫物16。
在根据本发明实施例的阵列基板中，第一隔垫物15与第二隔垫物16的分布比例例如为1:10～1:100，进一步地例如为1:18或1:36。
图6为根据本发明实施例的阵列基板的平面示意图二，图7a和图7b为沿图6的A-A’线截取的截面示意图。参见图6和图7a、图7b，根据本发明实施例的阵列基板还包括位于数据线7和/或栅线5上的第三隔垫物17。由于第三隔垫物17具有一定的高度，因而可以阻断相邻两个子像素之间的电力线，从而可以减少相邻子像素之间的电场干扰。
例如，根据本发明实施例的阵列基板包括设置所述多个子像素的显示区域和位于显示区域周围的周边区域。例如，第三隔垫物17的长度小于或等于所述显示区域的沿第三隔垫物17延伸方向的长度，即第三隔垫物17位于显示区域内。
例如，进一步参见图6和图7a、图7b，根据本发明实施例的阵列基板可以包括位于所述第三隔垫物17上的屏蔽电极18，以进一步减少相邻子像素之间的电场干扰。例如，屏蔽电极18上可以不施加电压。例如，屏蔽电极18上可以施加电压，例如低电平电压，进一步地例如0电平电压。例如，屏蔽电极18可以与公共电极12同层设置，从而屏蔽电极18和公共电极12可以通过一次构图工艺同时形成，简化制作工艺。例如，屏蔽电极18可以与公共电极12连接，从而屏蔽电极18上被施加公共电压。例如，屏蔽电极18可以与公共电极12断开，从而屏蔽电极18和公共电极12可以分开驱动。例 如，电极间绝缘层11的一部分可以进一步位于屏蔽电极18和第三隔垫物17之间。例如，电极间绝缘层11的位于屏蔽电极18和第三隔垫物17之间的部分可以与电极间绝缘层11的其他部分断开或连接。例如，屏蔽电极18覆盖第三隔垫物17的上表面和侧表面。
例如，为了简化制作工艺，可以将第一隔垫物15、第二隔垫物16、第三隔垫物17制作为具有相同的高度，如图8a和8b所示；在此情形下可以采用普通的单色调掩模板通过一次构图工艺同时形成第一隔垫物15、第二隔垫物16和第三隔垫物17。进一步地，例如，电极间绝缘层11具有位于第一隔垫物15上的部分且公共电极12具有位于第一隔垫物15上的部分，与公共电极12同层设置的屏蔽电极18形成在第三隔垫物17上；由此，第一隔垫物15及位于其上的电极间绝缘层11和公共电极12可整体看做主隔垫物，第三隔垫物17及位于其上的屏蔽电极18可整体看做第一副隔垫物，第二隔垫物16可看做第二副隔垫物，主隔垫物的高度、第一副隔垫物的高度和第二副隔垫物的高度呈台阶状分布，由此可以更好地避免低温气泡不良和按压不良。
需要说明的是，在根据本发明实施例的阵列基板中，基底基板1、缓冲层2、有源层3、栅绝缘层4、栅线层(包括栅线5和栅极G)、层间绝缘层6、数据线层(包括数据线7、源极S和漏极D)、钝化层8、像素电极10、电极间绝缘层11和公共电极12可以采用任何已知的材料和方法形成，在此不再赘述。例如，有源层3由低温多晶硅形成。例如，钝化层8由有机树脂形成，例如亚克力树脂。例如，隔垫物(包括第一隔垫物15，第二隔垫物16和第三隔垫物17)由有机树脂材料形成，例如负性PR胶。例如，形成第一隔垫物15、第二隔垫物16和第三隔垫物17的材料可以相同或者不同。
需要说明的是，在图3至图8b中均示出了形成在过孔9中的第一隔垫物15和第二隔垫物16与形成在过孔9中的像素电极10直接接触；然而，本发明的实施例并不局限于此，在第一隔垫物15、第二隔垫物16和像素电极10之间还可以根据需要形成其他的插入层。
根据本发明的实施例，还提供一种显示装置。该显示装置包括：如上所述的阵列基板；对向基板，与阵列基板相对设置，其中第一隔垫物的端部抵靠在对向基板上；以及液晶层，位于阵列基板和对向基板之间。由于根据本发明实施例的显示装置包括如上所述的阵列基板，因此即使显示装置受到外 力，第一隔垫物也不会轻易滑动，从而可以避免由于第一隔垫物滑动到过孔中造成的液晶层厚度不均匀及取向层(在图中未示出，其位于阵列基板的面向对向基板的表面上)被划伤的情形。由此，可以使阵列基板和对向基板之间具有均匀的间隙，可以很好地保持液晶层的厚度均匀性，防止取向层划伤而引起的漏光，提高显示质量。
图9a和9b、图10a和10b、图11a和11b、图12a和12b、以及图13a和13b为根据本发明实施例的显示装置的截面示意图。如图9a至图13b所示，对向基板包括基底基板20、以及依次形成在基底基板20上的黑矩阵13和钝化层14，第一隔垫物15、第二隔垫物16和第三隔垫物17均位于黑矩阵13所覆盖的区域中。
图9a和9b所示的显示装置采用了图4a和4b所示的阵列基板，图10a和10b所示的显示装置采用了图5a和5b所示的阵列基板，图11a和11b所示的显示装置采用了图7a和7b所示的阵列基板，图12a和12b所示的显示装置采用了图8a和8b所示的阵列基板，因此在此不再赘述。
除了对向基板之外，图13a和13b所示的显示装置与图9a和9b所示的显示装置基本相同。在图13a和图13b所示的显示装置中，对向基板还包括彩膜层19。例如，该彩膜层19具有位于所述第一隔垫物15上方的部分而不具有位于所述第二隔垫物16上方的部分，由此同样有助于避免低温气泡不良和按压不良，并且可进一步降低对采用双色调掩模板的构图工艺的工艺要求并增加第一隔垫物15和第二隔垫物16的设计灵活性。需要说明的是，图13a和13b所示的对向基板可以用于代替图10a和10b、图11a和11b、以及图12a和12b中所示对向基板。
例如，根据本发明实施例的显示装置可以为：液晶显示面板、液晶显示装置、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
根据本发明的实施例，还提供一种阵列基板的制作方法。该阵列基板的制作方法包括：在基底基板1上形成多条栅线5和多条数据线7，所述多条栅线5和所述多条数据线7彼此交叉限定多个子像素，每个子像素包括薄膜晶体管和像素电极10，所述多个子像素包括第一子像素；在所述基底基板1上形成覆盖所述栅线5、所述数据线7和所述薄膜晶体管的钝化层8，所述钝 化层8中设置有过孔9，在所述每个子像素中所述像素电极10形成在所述钝化层8上且通过所述过孔9连接到所述薄膜晶体管的漏极D或源极S；以及在所述第一子像素的过孔9中形成第一隔垫物15。
在根据本发明实施例的阵列基板的制作方法中，将第一隔垫物形成在第一子像素的过孔中。因此，即使所述阵列基板与对向基板对盒形成的显示装置受到外力，第一隔垫物也不会轻易滑动，从而可以避免由于第一隔垫物滑动到过孔中造成的液晶层厚度不均匀及取向层(在图中未示出，其位于阵列基板的面向对向基板的表面上)被划伤的情形。由此，可以使阵列基板和对向基板之间具有均匀的间隙，可以很好地维持液晶层的厚度均匀性，防止取向层划伤而引起的漏光，提高显示质量。
例如，所述多个子像素还包括第二子像素，所述阵列基板的制作方法还包括：在第二子像素的过孔9中形成第二隔垫物16。
图14a和14b至图16a和16b为根据本发明实施例的阵列基板的制作方法的流程示意图一。首先，如图14a和14b所示，基底基板1上形成缓冲层2，并且在缓冲层上依次形成有源层3、栅绝缘层4、栅线层(包括栅线5和栅极G)、层间绝缘层6、数据线层(包括数据线7、源极S和漏极D)、钝化层8及过孔9、以及像素电极10。有源层3、栅极G、源极S和漏极D构成薄膜晶体管，像素电极10通过钝化层8中的过孔9连接到薄膜晶体管的漏极D或源极S。上述各膜层可以采用任何已知的材料和方法形成，在此不再赘述。上述各膜层的层叠顺序不限于图14a和14b所示的顺序，可以根据实际需要进行调整，在此也不再赘述。
然后，形成隔垫物材料层(例如，由PR胶形成且厚度为4-6μm)，采用双色调掩模板(例如，半色调掩模板和灰色调掩模板)对隔垫物材料层进行图案化，以通过一次构图工艺同时形成第一隔垫物15和第二隔垫物16，第一隔垫物15的高度大于第二隔垫物16的高度，如图15a和15b所示。例如，所述阵列基板的制作方法还包括：在像素电极10上形成电极间绝缘层11，该电极间绝缘层11具有位于第一隔垫物15上的部分而不具有位于第二隔垫物16上的部分，如图16a和16b所示。例如，所述阵列基板的制作方法还包括：在电极间绝缘层11上形成公共电极12，该公共电极12具有位于第一隔垫物15上的部分而不具有位于第二隔垫物16上的部分，由此可以得到 图4a和4b所示的阵列基板。
图17a和17b至图18a和18b为根据本发明实施例的阵列基板的制作方法的流程示意图二。在形成图14a和14b所示的结构之后，形成隔垫物材料层(例如，由PR胶形成且厚度为4-6μm)，采用普通单色调掩模板对隔垫物材料层进行图案化，以通过一次构图工艺同时形成第一隔垫物15和第二隔垫物16，第一隔垫物15的高度等于第二隔垫物16的高度，如图17a和17b所示。例如，所述阵列基板的制作方法还包括：在像素电极10上形成电极间绝缘层11，该电极间绝缘层11具有位于第一隔垫物15上的部分而不具有位于第二隔垫物16上的部分，如图18a和18b所示。例如，所述阵列基板的制作方法还包括：在电极间绝缘层11上形成公共电极12，该公共电极12具有位于第一隔垫物15上的部分而不具有位于第二隔垫物16上的部分，由此可以得到图5a和5b所示的阵列基板。
图19a和19b至图20a和20b为根据本发明实施例的阵列基板的制作方法的流程示意图三。在形成图14a和14b所示的结构之后，形成第一隔垫物15、第二隔垫物16和第三隔垫物17，如图19a和19b所示。例如，可以采用三块掩模板通过三次构图工艺形成第一隔垫物15、第二隔垫物16和第三隔垫物17。例如，可以采用双色调掩模板通过一次构图工艺形成第一隔垫物15和第二隔垫物16，然后再采用单色调掩模板通过一次构图工艺形成第三隔垫物17。为了简化制作工艺，可以将第一隔垫物15、第二隔垫物16和第三隔垫物17制作为具有相同的高度，这样一来可以采用单色调掩模板通过一次构图工艺形成第一隔垫物15、第二隔垫物16和第三隔垫物17。例如，所述阵列基板的制作方法还包括：在像素电极10上形成电极间绝缘层11，该电极间绝缘层11具有位于第一隔垫物15上的部分而不具有位于第二隔垫物16上的部分，如图20a和20b所示。例如，所述阵列基板的制作方法还包括：在电极间绝缘层11上形成公共电极12，该公共电极12具有位于第一隔垫物15上的部分而不具有位于第二隔垫物16上的部分；进一地，该阵列基板的制作方法还包括：在第三隔垫物17上形成屏蔽电极18，由此可以得到图7a和7b所示的阵列基板。例如，所述公共电极12与所述屏蔽电极18通过对公共电极材料层进行图案化而同时形成。
以上所述仅是本发明的示范性实施例，而非用于限制本发明的保护范围，本发明的保护范围由权利要求确定。

Claims (20)

  1. 一种阵列基板，包括：
    基底基板；
    形成在所述基底基板上的多条栅线和多条数据线，所述多条栅线和所述多条数据线彼此交叉限定多个子像素，每个子像素包括薄膜晶体管和像素电极，所述多个子像素包括第一子像素；
    形成在所述基底基板上且覆盖所述栅线、所述数据线和所述薄膜晶体管的钝化层，所述钝化层中设置有过孔，在所述每个子像素中所述像素电极形成在所述钝化层上且通过所述过孔连接到所述薄膜晶体管的漏极或源极；
    第一隔垫物，设置在所述第一子像素的过孔中。
  2. 根据权利要求1所述的阵列基板，其中，
    所述多个子像素还包括第二子像素，并且
    所述阵列基板还包括第二隔垫物，所述第二隔垫物设置在所述第二子像素的过孔中。
  3. 根据权利要求2所述的阵列基板，其中在所述基底基板上所述第一隔垫物的高度大于所述第二隔垫物的高度。
  4. 根据权利要求3所述的阵列基板，其中
    所述每个子像素还包括公共电极和位于所述公共电极与所述像素电极之间的电极间绝缘层；
    所述电极间绝缘层具有位于所述第一隔垫物上的部分而不具有位于所述第二隔垫物上的部分；并且/或者所述公共电极具有位于所述第一隔垫物上的部分而不具有位于所述第二隔垫物上的部分。
  5. 根据权利要求2所述的阵列基板，其中
    在所述基底基板上所述第一隔垫物的高度与所述第二隔垫物的高度相同；
    所述每个子像素还包括公共电极和位于所述公共电极与所述像素电极之间的电极间绝缘层；
    所述电极间绝缘层具有位于所述第一隔垫物上的部分而不具有位于所述第二隔垫物上的部分；并且/或者所述公共电极具有位于所述第一隔垫物上的 部分而不具有位于所述第二隔垫物上的部分。
  6. 根据权利要求2所述的阵列基板，还包括第三隔垫物；所述第三隔垫物位于所述栅线和/或数据线的上方。
  7. 根据权利要求6所述的阵列基板，还包括位于所述第三隔垫物上的屏蔽电极。
  8. 根据权利要求7所述的阵列基板，其中
    所述每个子像素还包括公共电极和位于所述公共电极与所述像素电极之间的电极间绝缘层；
    所述屏蔽电极与所述公共电极同层设置。
  9. 根据权利要求6所述的阵列基板，其中
    在所述基底基板上所述第一隔垫物的高度、所述第二隔垫物的高度和所述第三隔垫物的高度相同；
    所述每个子像素还包括公共电极和位于所述公共电极与所述像素电极之间的电极间绝缘层；
    所述电极间绝缘层具有位于所述第一隔垫物上的部分且所述公共电极具有位于所述第一隔垫物上的部分；
    所述第三隔垫物上具有屏蔽电极，所述屏蔽电极与所述公共电极同层设置。
  10. 一种显示装置，包括：
    阵列基板，所述阵列基板包括：
    基底基板；
    形成在所述基底基板上的多条栅线和多条数据线，所述多条栅线和所述多条数据线彼此交叉限定多个子像素，每个子像素包括薄膜晶体管和像素电极，所述多个子像素包括第一子像素；
    形成在所述基底基板上且覆盖所述栅线、所述数据线和所述薄膜晶体管的钝化层，所述钝化层中设置有过孔，在所述每个子像素中所述像素电极形成在所述钝化层上且通过所述过孔连接到所述薄膜晶体管的漏极或源极；
    第一隔垫物，设置在所述第一子像素的过孔中；
    对向基板，与所述阵列基板相对设置，其中所述第一隔垫物的端部抵靠在所述对向基板上；以及
    液晶层，位于所述阵列基板与所述对向基板之间。
  11. 根据权利要求10所述的阵列基板，其中，
    所述多个子像素还包括第二子像素，并且
    所述阵列基板还包括第二隔垫物，所述第二隔垫物设置在所述第二子像素的过孔中。
  12. 根据权利要求11所述的阵列基板，其中在所述基底基板上所述第一隔垫物的高度大于所述第二隔垫物的高度。
  13. 根据权利要求12所述的阵列基板，其中
    所述每个子像素还包括公共电极和位于所述公共电极与所述像素电极之间的电极间绝缘层；
    所述电极间绝缘层具有位于所述第一隔垫物上的部分而不具有位于所述第二隔垫物上的部分；并且/或者所述公共电极具有位于所述第一隔垫物上的部分而不具有位于所述第二隔垫物上的部分。
  14. 根据权利要求11所述的阵列基板，其中
    在所述基底基板上所述第一隔垫物的高度与所述第二隔垫物的高度相同；
    所述每个子像素还包括公共电极和位于所述公共电极与所述像素电极之间的电极间绝缘层；
    所述电极间绝缘层具有位于所述第一隔垫物上的部分而不具有位于所述第二隔垫物上的部分；并且/或者所述公共电极具有位于所述第一隔垫物上的部分而不具有位于所述第二隔垫物上的部分。
  15. 根据权利要求11所述的阵列基板，还包括第三隔垫物；所述第三隔垫物位于所述栅线和/或数据线的上方。
  16. 根据权利要求15所述的阵列基板，还包括位于所述第三隔垫物上的屏蔽电极。
  17. 根据权利要求16所述的阵列基板，其中
    所述每个子像素还包括公共电极和位于所述公共电极与所述像素电极之间的电极间绝缘层；
    所述屏蔽电极与所述公共电极同层设置。
  18. 根据权利要求15所述的阵列基板，其中
    在所述基底基板上所述第一隔垫物的高度、所述第二隔垫物的高度和所述第三隔垫物的高度相同；
    所述每个子像素还包括公共电极和位于所述公共电极与所述像素电极之间的电极间绝缘层；
    所述电极间绝缘层具有位于所述第一隔垫物上的部分且所述公共电极具有位于所述第一隔垫物上的部分；
    所述第三隔垫物上具有屏蔽电极，所述屏蔽电极与所述公共电极同层设置。
  19. 根据权利要求10所述的显示装置，其中所述对向基板包括彩膜层，所述彩膜层具有位于所述第一隔垫物上方的部分。
  20. 一种阵列基板的制作方法，包括：
    在基底基板上形成多条栅线和多条数据线，所述多条栅线和所述多条数据线彼此交叉限定多个子像素，每个子像素包括薄膜晶体管和像素电极，所述多个子像素包括第一子像素；
    在所述基底基板上形成覆盖所述栅线、所述数据线和所述薄膜晶体管的钝化层，所述钝化层中设置有过孔，在所述每个子像素中所述像素电极形成在所述钝化层上且通过所述过孔连接到所述薄膜晶体管的漏极或源极；以及
    在所述第一子像素的过孔中形成第一隔垫物。
PCT/CN2015/094583 2015-06-19 2015-11-13 阵列基板及其制作方法以及显示装置 Ceased WO2016201874A1 (zh)

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