WO2016201909A1 - 移位寄存器单元、栅极驱动电路和显示装置 - Google Patents

移位寄存器单元、栅极驱动电路和显示装置 Download PDF

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Publication number
WO2016201909A1
WO2016201909A1 PCT/CN2015/095991 CN2015095991W WO2016201909A1 WO 2016201909 A1 WO2016201909 A1 WO 2016201909A1 CN 2015095991 W CN2015095991 W CN 2015095991W WO 2016201909 A1 WO2016201909 A1 WO 2016201909A1
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Prior art keywords
signal
pull
control node
output
shift register
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Ceased
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PCT/CN2015/095991
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English (en)
French (fr)
Inventor
张晓洁
邵贤杰
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BOE Technology Group Co Ltd
Hefei BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei BOE Optoelectronics Technology Co Ltd
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Priority to US15/100,572 priority Critical patent/US20170309240A1/en
Priority to EP15891402.8A priority patent/EP3309775A4/en
Publication of WO2016201909A1 publication Critical patent/WO2016201909A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/34—Digital stores in which the information is moved stepwise, e.g. shift registers using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C19/36—Digital stores in which the information is moved stepwise, e.g. shift registers using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using multistable semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present disclosure relates to a shift register unit, a gate drive circuit, and a display device.
  • Liquid crystal display has been widely used in mobile phones, tablets, televisions, monitors, notebook computers due to its low power consumption, light weight, thin thickness, no electromagnetic radiation and no pollution.
  • display functions such as cameras, camcorders, digital photo frames, navigators, etc.
  • the gate drive circuit often uses a GOA (Gate Driver on Array) design to integrate a thin film transistor (TFT) gate switch circuit on the array substrate of the display panel.
  • the scan driving is performed on the display panel, and the gate line driving circuit is used to provide a scan signal to the gate scan lines of the pixel array to realize progressive scan of the pixel array.
  • GOA Gate Driver on Array
  • the signal writing time of the data driving circuit is shorter and shorter, and the use of the existing gate driving circuit causes the falling time of the output waveform of the gate driving circuit to be shorter.
  • the result is insufficient writing of the pixel voltage, which affects the display screen and display quality of the liquid crystal display.
  • Embodiments of the present disclosure provide a shift register unit, a gate driving circuit, and a display device, which are capable of enhancing an output capability of a signal output terminal and shortening a fall time of an output waveform of a signal output terminal.
  • a shift register unit including:
  • a first output module which is respectively connected to the pull-up control node, the clock signal end, and the second output module, for outputting the signal of the clock signal end to the second output module under the control of the pull-up control node ;
  • a second output module respectively connected to the signal output end, the clock signal end and the first output module, configured to, under the control of the first output module, the clock signal end a signal output to the signal output terminal;
  • the input module is respectively connected to the pull-up control node, the first power terminal, and the signal input terminal, and is configured to output the voltage of the first power terminal to the pull-up control node under the signal control of the signal input end;
  • a pull-down control module respectively connected to the signal input end, the pull-down control node and the second power supply end, for pulling down the signal of the pull-down control node to the voltage of the second power supply terminal under the signal control of the signal input end ;
  • a pull-down module respectively connected to the pull-down control node, the pull-up control node, the signal output end, and the second power supply end, for controlling the pull-up control node under the control of the pull-down control node And a signal pulled down from the signal output terminal to a voltage at the second power terminal;
  • the reset module is respectively connected to the first power terminal, the reset signal terminal, and the pull-down control node, and is configured to output the signal of the first power terminal to the pull-down control node under the control of the reset signal terminal.
  • a gate driving circuit comprising at least two stages of shift register units as described above;
  • the signal output end of the shift register unit of the next stage is connected to the reset signal end of the shift register unit of the previous stage;
  • the signal output end of the shift register unit of the previous stage is connected to the signal input end of the shift register unit of the next stage;
  • the reset signal terminal of the last pole shift register inputs a reset signal.
  • a display device including the gate drive circuit as described above is provided.
  • a driving method for driving a shift register unit as described above comprising:
  • a low level is input at the clock signal end and the reset signal end, and a high level is input to the signal input end;
  • Controlling by the input signal module, the voltage of the first voltage terminal to the pull-up control node, and pulling up the potential of the pull-up control node; and controlling the signal at the signal input end Lowering the pull-down control with the pull-down control module The signal of the node is pulled down to the voltage of the second power terminal;
  • a high level is input at the clock signal end, and a low level is input at the signal input end and the reset signal end;
  • a low level is input to the clock signal end and the signal input end, and a high level is input at the reset signal end;
  • the pull-down module pulls down the signal of the pull-up control node and the signal of the signal output terminal to the voltage of the second power terminal to implement reset.
  • the embodiment of the present disclosure provides a shift register unit, a gate driving circuit, and a display device, where the shift register unit includes: a first output module, which is respectively connected to the pull-up control node, the clock signal end, and the second An output module, configured to output, by the pull-up control node, a signal of the clock signal end to the second output module; and a second output module respectively connected to the signal output end, the clock signal And the first output module, configured to output, by the first output module, a signal of the clock signal end to the signal output end; and input modules respectively connected to the pull-up control node and the first power supply a signal input end for outputting the voltage of the first power terminal to the pull-up control node under the signal control of the signal input end; the pull-down control module is respectively connected to the signal input end and the pull-down control node And a second power terminal for pulling down the signal of the pull-down control node to the second power source under the signal control of the signal input end a voltage pull-down module
  • the pull-down control module can signal control at the signal input. Forming, pulling down the potential of the pull-down control node to ensure normal output of the signal output; in the output stage, the first output module is to control the clock signal under the control of the pull-up control node a signal outputted to the signal output end, the second output module outputs a signal of the clock signal output end to the signal output end under the control of the first output module, so that the a signal outputted from the clock signal is output to the signal output end, and a scan signal of the signal output end is input to a corresponding gate line; the output capability of the shift register unit can be improved, and the reset module can perform pull-down control during the reset phase The potential of the node is pulled up, and the potential of the pull-up control node and the potential of the signal output end are pulled down by the pull-down module to improve the reset efficiency.
  • the output capability of the shift register unit can be greatly enhanced in the output stage, and the fall time of the output waveform can be shortened in the reset phase, thereby improving the output characteristics of the gate drive circuit and preventing The screen display is abnormal due to a drop in output characteristics.
  • FIG. 1 is a schematic structural diagram of a shift register unit according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of a gate driving circuit formed by cascading a plurality of shift register units shown in FIG. 1 according to an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of a shift register unit shown in FIG. 1 according to an embodiment of the present disclosure
  • FIG. 4 is a timing diagram of control signals of the shift register unit shown in FIG. 3 in the embodiment of the present disclosure.
  • FIG. 1 is a schematic structural diagram of a shift register unit according to an embodiment of the present disclosure. As shown in FIG. 1, the shift register unit may include:
  • the first output module 10 is connected to the pull-up control node PU, the clock signal terminal CLK, and the second output module 20, respectively, for outputting the signal of the clock signal terminal CLK under the control of the pull-up control node PU.
  • the second output module 20 To the second output module 20;
  • the second output module 20 is connected to the signal output terminal OUT, the clock signal terminal CLK and the first output module 10, respectively, for controlling the clock signal terminal CLK under the control of the first output module 10 Signal output to the signal output terminal OUT;
  • the input module 30 is connected to the pull-up control node PU, the first power terminal VDD, and the signal input terminal IN for outputting the voltage of the first power terminal VDD under the signal control of the signal input terminal IN.
  • the pull-down control module 40 is connected to the signal input terminal IN, the pull-down control node PD, and the second power terminal VSS, respectively, for pulling down the signal of the pull-down control node PD to the signal control of the signal input terminal IN to a voltage of the second power terminal VSS;
  • a pull-down module 50 which is respectively connected to the pull-down control node PD, the pull-up control node PU, the signal output terminal OUT, and the second power terminal VSS, under the control of the pull-down control node PD, The signal of the pull-up control node PU and the signal output terminal OUT is pulled down to the voltage of the second power terminal VSS;
  • the reset module 60 is connected to the first power terminal VDD, the reset signal terminal RESET, and the pull-down control node PD, respectively, for outputting the signal of the first power terminal VDD under the control of the reset signal terminal RESET To the pull-down control node PD.
  • the shift register unit can greatly enhance the output capability of the shift register unit in the output stage, and shorten the fall time of the output waveform in the reset phase, thereby improving the output characteristics of the gate drive circuit and preventing The screen display is abnormal due to a drop in output characteristics.
  • FIG. 2 is a schematic structural diagram of a gate driving circuit formed by cascading a plurality of shift register units shown in FIG. 1 according to an embodiment of the present disclosure.
  • At least two stages of shift register units (SR0, SR1, . . . SRn) as described above can constitute a gate drive circuit, and each pole shift register unit is progressively lined up to each row of gate lines.
  • Input the scan signal (G0, G1...Gn).
  • the signal input terminal IN of the first stage shift register unit SR0 receives the start signal input from the start signal terminal STV.
  • the signal input terminal IN of each of the shift register units is connected to the signal output terminal OUT of the adjacent upper stage shift register unit.
  • the reset signal terminal RESET of each of the shift register units is connected to the signal output terminal OUT of the adjacent next stage shift register unit.
  • the reset signal terminal RESET of the last stage shift register unit SRn can input a reset signal input by the reset signal terminal RST.
  • the first voltage terminal VDD is input to the high level
  • the second voltage terminal VSS is input to the low level as an example.
  • the embodiment of the present disclosure provides a shift register unit, a gate driving circuit, and a display device.
  • the shift register unit includes: a first output module 10 connected to the pull-up control node PU, the clock signal terminal CLK, and the second output, respectively. a module, configured to output a signal of the clock signal terminal CLK to the second output module 20 under the control of the pull-up control node PU; and a second output module 20 connected to the signal output terminal OUT, respectively
  • the clock signal terminal CLK and the first output module 10 are configured to output a signal of the clock signal terminal CLK to the signal output terminal OUT under the control of the first output module 10; the input module 30, Connecting the pull-up control node PU, the first power terminal VDD, and the signal input terminal IN, respectively, for outputting the voltage of the first power terminal VDD to the pull-up control under the signal control of the signal input terminal IN a node PU; a pull-down control module 40, respectively connected to the signal input terminal IN, the pull-down control
  • the input module 30 outputs the voltage of the first power terminal VDD to the pull-up control node PU under the control of the signal input terminal IN, and pulls up the pull-up.
  • the control node PU is raised to a high level, and the first capacitor C1 is charged.
  • the pull-down control module 40 can perform noise reduction on the pull-down control node PD under the signal control of the signal input terminal IN. Processing provides conditions for normal charging of the first capacitor C1.
  • the first output module 10 outputs a signal of the clock signal output terminal CLK to the signal output terminal OUT under the control of the pull-up control node PU
  • the second output module 20 is The signal of the clock signal output terminal CLK is output to the signal output terminal OUT under the control of the first output module 10, so that the signal of the clock signal output terminal CLK can be simultaneously output to the signal output terminal.
  • the scan signal of the signal output terminal OUT is input to the corresponding gate line; the output capability of the shift register unit can be improved, and at the same time, the pull-down control module 40 can control the signal under the signal input terminal IN
  • the potential of the pull-down control node PD is pulled down to ensure the normal output of the signal output terminal OUT.
  • the reset module 60 can pull up the potential of the pull-down control node PD, and pull down the potential of the pull-up control node PU and the potential of the signal output terminal OUT through the pull-down module 50 to improve the reset. effectiveness.
  • the output capability of the shift register unit can be greatly enhanced in the output stage, and the falling time of the output waveform can be shortened in the reset phase, thereby improving the output characteristics of the gate driving circuit and preventing The screen displayed abnormally due to a drop in output characteristics.
  • FIG. 3 is a schematic diagram showing a specific structure of a shift register unit shown in FIG. 1 according to an embodiment of the present disclosure.
  • the first output module 10 can include:
  • the first transistor M1 has a gate connected to the pull-up control node PU, a first pole connected to the clock signal terminal CLK, and a second pole connected to the second output module 20;
  • the first capacitor C1 has one end connected to the pull-up control node PU and the other end connected to the second output module 20.
  • the pull-up control node PU is at a high level, and the signal of the clock signal terminal CLK is at a high level, the first transistor M1 can be turned on to pass the clock through the first transistor M1.
  • the high level signal input by the signal terminal CLK is output to the second output module 20 for controlling the second output module 20 to output a high level signal.
  • the second output module 20 can include:
  • the second transistor M2 has a gate connected to the first output module 10, a first pole connected to the clock signal terminal CLK, and a second pole connected to the signal output terminal OUT.
  • a gate of the second transistor M2 is coupled to a second pole of the first transistor.
  • the second transistor M2 may be turned on to output a high level signal input by the clock signal terminal CLK through the second transistor M2 to
  • the signal output terminal OUT scans the gate lines corresponding to the shift register units (SR0, SR1, ..., SRn) as scan signals (G0, G1, ..., Gn).
  • the output capability of the signal output terminal of the shift register unit is enhanced, thereby improving the output characteristics of the entire gate output circuit.
  • the input module 30 can include:
  • the third transistor M3 has a gate connected to the signal input terminal IN, a first pole connected to the first power terminal VDD, and a second pole connected to the pull-up control node PU.
  • the third transistor M3 may be turned on to raise the pull-up control node PU to a high level, and pass the pull-up control.
  • the node PU charges the first capacitor C1 to prepare the shift register unit for outputting a scan signal.
  • the pull-down control module 40 includes:
  • the fourth transistor M4 has a gate connected to the signal input terminal IN, a first pole connected to the pull-down control node PD, and a second pole connected to the second power terminal VSS;
  • the gate of the fourth transistor M4 can be turned on, and the de-noising control node PD is continuously subjected to noise reduction processing, thereby avoiding The potential of the control node PD rises, and the first output module 10 and the second output module 20 are turned on by mistake, so that the signal output terminal OUT of the shift register unit is erroneously output.
  • the pull-down module 50 includes:
  • a fifth transistor M5 having a gate connected to the pull-down control node PD, a first pole connected to the pull-up control node PU, and a second pole connected to the second power supply terminal VSS;
  • the sixth transistor M6 has a gate connected to the pull-down control node PD, a first pole connected to the signal output terminal OUT, and a second pole connected to the second power supply terminal VSS.
  • the fourth transistor M4, the fifth transistor M5 and the sixth transistor M6 are turned off, and the first capacitor can be C1 performs continuous charging; in the output stage, under the control of the low level signal of the pull-down control node PD, the fourth transistor M4, the fourth transistor M4, the fifth transistor M5 and the sixth transistor M6 are in an off state, ensuring The normal output of the signal output terminal OUT.
  • the reset module 60 can include:
  • the seventh transistor M7 has a gate connected to the reset signal terminal RESET, a first pole connected to the first power terminal VDD, and a second pole connected to the pull-down control node PD.
  • the seventh transistor M7 is turned on, so that the pull-down control node PD rises to a high level, and at this time, the fifth transistor M5 and The sixth transistor M6 is turned on, and the fifth transistor M5 and the sixth transistor M6 pull down the signal of the pull-up control node PU and the signal output terminal OUT, and quickly pull the pull-up control node PU and the The voltage drop at the signal output terminal OUT is low, which can shorten the fall time of the output waveform and improve the reset efficiency.
  • the first pole of the transistor may be a source
  • the second pole may be a drain
  • the first pole of the transistor may be a drain
  • the second pole may be a source, which is not limited in this disclosure. system.
  • the reset module 60 is connected to the second power terminal VSS, and the reset module 60 may further include:
  • the second capacitor C2 has one end connected to the pull-down control node PD and the other end connected to the second power terminal VSS.
  • the second capacitor C2 in the charging phase, since the fifth transistor M5 and the sixth transistor M6 are turned off, it is possible to prevent drift of the self threshold voltage and successively charge the second capacitor C2.
  • the first capacitor C1 is insufficiently charged; in the reset phase, under the control of the high level signal of the reset signal terminal RESET, the seventh transistor M7 is turned on, and the second capacitor C2 is charged, and the next frame signal arrives.
  • the pull-down control node PD As the signal of the clock signal terminal CLK changes periodically, the pull-down control node PD always maintains a high potential due to the presence of the second capacitor C2, continuously outputting the pull-up control node PU and the signal
  • the terminal OUT performs noise reduction processing to ensure the accuracy and stability of the output of the signal output terminal OUT.
  • FIG. 4 is a timing chart showing control signals of the shift register unit shown in FIG. 3 in the embodiment of the present disclosure.
  • the input signal terminal IN signal is at a high level, the third transistor M3 is turned on, the pull-up control node PU is raised to a high level, and the first capacitor C1 is charged by the pull-up control node PU.
  • the input signal terminal IN signal is at a high level
  • the signal at the reset signal terminal RESET is at a low level
  • the gate of the fourth transistor M4 is turned on
  • the pull-down control node PD is continuously subjected to noise reduction processing.
  • the second capacitor C2 is in a discharging state
  • the fifth transistor M5 and the sixth transistor M6 are in an off state
  • the pull-down control node PD is at a low level, effectively preventing the fifth transistor M5 and the sixth transistor.
  • the M6 is gradually charged due to the drift of the self-threshold voltage, and the first capacitor C1 is insufficiently charged.
  • the pull-up control node PU rises to a high level, at this time, the first crystal The gate of the transistor M1 is turned on, but since the signal of the clock signal terminal CLK is at a low level, the first transistor M1 is not turned on, the second transistor M2 is also in an off state, and the signal output terminal OUT The output is low.
  • the signal of the clock signal terminal CLK is at a high level
  • the signal of the signal input terminal IN is at a low level
  • the first transistor M1 is in an off state. Since the pull-up control node PU is at a high level, the first transistor M1 is turned on, and the second transistor M2 is also turned on, and the signal output terminal OUT outputs a high level. At this time, since the first transistor M1 and the second transistor M2 are simultaneously output, the output capability of the signal output terminal is enhanced.
  • the signal of the signal input terminal IN is low level
  • the signal of the reset signal terminal RESET is low level
  • the fourth transistor M4 the fifth transistor M5 and the sixth transistor M6 are both cut off. State, the PD point remains low, ensuring the normal output of the signal output OUT.
  • the signal of the reset signal terminal RESET is at a high level
  • the seventh transistor M7 is turned on
  • the second capacitor C2 is charged to raise the pull-down control node PD to a high level.
  • the fifth transistor M5 and the sixth transistor M6 are turned on, and simultaneously discharges the first capacitor C1, so that the signal of the pull-up control node PU and the signal output terminal OUT is rapidly lowered to low. Level to implement the reset function.
  • the pull-down control node PD Before the arrival of the next frame signal, as the signal of the clock signal terminal CLK changes periodically, the pull-down control node PD always maintains a high potential due to the presence of the second capacitor C2, continuously to the pull-up control node PU. And the signal output terminal OUT performs noise reduction processing to ensure the accuracy and stability of the output of the signal output terminal OUT.
  • T1 to T3 stages may be referred to as the operating time of the shift register unit.
  • Signal output OUT only outputs a high level in the second stage T2, so the second stage T2 can be the data output stage of the shift register unit.
  • the T1 and T3 phases are the non-output phases of the shift register unit, and the signal output terminal OUT outputs a low level during this phase.
  • a driving method for driving a shift register unit includes the following work process:
  • a low level is input to the clock signal end and the reset signal end, and a high level is input to the signal input end; under the signal control of the signal input end, the voltage of the first voltage end is output to the upper by the input module. Pulling a control node to pull up a potential of the pull-up control node; and under a signal control of the signal input end, pulling down a signal of the pull-down control node to a voltage of the second power terminal by using a pull-down control module;
  • a high level is input at the clock signal end, and the signal input end and the reset signal end are input with a low level; under the control of the pull-up control node, the first output module is used The signal of the clock signal end is output to the second output module; under the control of the first output module, the signal of the clock signal end is output to the signal output end by the second output module;
  • a low level is input to the clock signal end and the signal input end, and the reset signal end is input with a high level; under the signal control of the reset signal end, the first power source is reset by the reset module.
  • the signal of the terminal is output to the pull-down control node, and the pull-down control node is pulled up. Under the control of the pull-down control node, the signal of the pull-up control node and the signal of the signal output end are pulled down by a pull-down module.
  • the voltage to the second power terminal is reset.
  • the above transistors may be all P-type transistors.
  • the transistors in the shift register unit and the transistors connected to the gate lines in the pixel unit are P-type transistors. The timing of the drive signal and the input signal of the circuit need to be adjusted accordingly.
  • Embodiments of the present disclosure provide a display device including any of the gate drive circuits described above.
  • the same advantages as the gate driving circuit provided by the foregoing embodiments of the present disclosure are provided, and since the gate driving circuit has been described in detail in the foregoing embodiments, details are not described herein again.
  • the display device may specifically be any liquid crystal display product or component having a display function, such as a liquid crystal display, a liquid crystal television, a digital photo frame, a mobile phone, a tablet computer, or the like.
  • Embodiments of the present disclosure provide a driver for driving any one of the above shift register units
  • the method can include:
  • the input module 30 may output the voltage of the first voltage terminal to the pull-up control node PU under the signal control of the signal input terminal IN, and pull up the potential of the pull-up control node PU;
  • the control module 40 can pull down the signal of the pull-down control node PD to the voltage of the second power terminal VSS under the control of the signal input terminal IN; thereby implementing continuous charging of the pull-up control node PU, Prepare for the shift register unit to output a scan signal.
  • the first output module 10 may output the clock signal CLK input by the clock signal terminal CLK to the second output module 20, where the second output module 20 may be in the Under the control of an output module 10, the clock signal CLK input by the clock signal terminal CLK is output to the signal output terminal OUT, so that the signal output terminal OUT inputs a scan signal to the gate line connected to the shift register unit.
  • the output capability of the shift register unit can be increased by adding an output module.
  • the reset module 60 may output a signal of the first power terminal VDD to the pull-down control node PD under the control of the signal of the reset signal terminal RESET, and pull up the pull-down control node PD, the pull-down module Under the control of the pull-down control node PD, the signal of the pull-up control node PU and the signal of the signal output terminal OUT are pulled down to the voltage of the second power terminal VSS to implement reset.
  • the voltage of the signal output terminal OUT decreases, but is still at a high level.
  • the second transistor M2 in the second output module 20 is still in an on state, so that the voltage of the signal output terminal OUT is quickly pulled from a high level to a low level, and the falling time of the output waveform is shortened, and the reset function is The efficiency is greatly improved.
  • the foregoing program may be stored in a computer readable storage medium, and the program is executed when executed.
  • the foregoing storage medium includes: a medium that can store program codes, such as a ROM, a RAM, a magnetic disk, or an optical disk.

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Abstract

一种移位寄存器单元包含：第一输出模块（10）与第二输出模块（20），用于在上拉控制节点（PU）的控制下，将时钟信号端（CLK）的信号输出至信号输出端（OUT）；输入模块（30），用于在信号输入端（IN）的信号控制下，将第一电源端（VDD）的电压输出至上拉控制节点（PU）；下拉控制模块（40），用于在信号输入端（IN）的信号控制下，将下拉控制节点（PD）的信号下拉至第二电源端（VSS）的电压；下拉模块（50），用于在下拉控制节点（PD）的控制下，将上拉控制节点（PU）与信号输出端（OUT）的信号下拉至第二电源端（VSS）的电压；复位模块（60），用于在复位信号端（RESET）的控制下，将第一电源端（VDD）的信号输出至下拉控制节点（PD）。该移位寄存器单元能够增强信号输出端（OUT）的输出能力，缩短输出波形下降时间。还提供了一种栅极驱动电路和显示装置。

Description

移位寄存器单元、栅极驱动电路和显示装置 技术领域
本公开涉及一种移位寄存器单元、栅极驱动电路和显示装置。
背景技术
液晶显示器(Liquid Crystal Display，简称LCD)由于具有低功耗、重量轻、厚度薄、无电磁辐射以及无污染等优点，已广泛地应用于包括手机、平板电脑、电视机、显示器、笔记本电脑、照相机、摄像机、数码相框、导航仪等在内的具有显示功能的产品或部件中。
在现有的液晶显示器中，栅极驱动电路常采用GOA(Gate Driver on Array，阵列基板行驱动)设计将薄膜场效应晶体管(Thin Film Transistor，TFT)栅极开关电路集成在显示面板的阵列基板上以形成对显示面板的扫描驱动，并且采用栅线驱动电路给像素阵列的栅极扫描线提供扫描信号，实现像素阵列的逐行扫描。
然而，随着液晶显示器的分辨率越来越高，数据驱动电路的信号写入时间越来越短，采用现有的栅极驱动电路，会使得所述栅极驱动电路输出波形的下降时间较长而导致像素电压写入不足，影响液晶显示器的显示画面以及显示品质。
发明内容
本公开的实施例提供一种移位寄存器单元、栅极驱动电路和显示装置，能够增强信号输出端的输出能力，缩短信号输出端输出波形的下降时间。
在本公开的一个实施例中，提供一种移位寄存器单元，包括：
第一输出模块，分别连接上拉控制节点、时钟信号端以及第二输出模块，用于在所述上拉控制节点的控制下，将所述时钟信号端的信号，输出至所述第二输出模块；
第二输出模块，分别连接信号输出端，所述时钟信号端以及所述第一输出模块，用于在所述第一输出模块的控制下，将所述时钟信号端的 信号输出至所述信号输出端；
输入模块，分别连接所述上拉控制节点、第一电源端、信号输入端，用于在所述信号输入端的信号控制下，将所述第一电源端的电压输出至所述上拉控制节点；
下拉控制模块，分别连接所述信号输入端、下拉控制节点以及第二电源端，用于在所述信号输入端的信号控制下，将所述下拉控制节点的信号下拉至所述第二电源端的电压；
下拉模块，分别连接所述下拉控制节点、所述上拉控制节点、所述信号输出端以及所述第二电源端，用于在所述下拉控制节点的控制下，将所述上拉控制节点与所述信号输出端的信号下拉至第二电源端的电压；
复位模块，分别连接所述第一电源端、复位信号端以及所述下拉控制节点，用于在所述复位信号端的控制下，将所述第一电源端的信号输出至所述下拉控制节点。
在本公开的另一实施例中，提供一种栅极驱动电路，包含至少两级如上述所述的移位寄存器单元；
除第一级移位寄存器单元以外，下一级移位寄存器单元的信号输出端与上一级移位寄存器单元的复位信号端相连接；
除最后一级移位寄存器单元以外，上一级移位寄存器单元的信号输出端与下一级移位寄存器单元的信号输入端相连接；
所述第一极移位寄存器的信号输入端输入帧起始信号；
所述最后一极移位寄存器的复位信号端输入复位信号。
在本公开的再一实施例中，提供一种显示装置，包括如上述所述的栅极驱动电路。
在本公开的又一实施例中，提供一种用于驱动如上述所述的移位寄存器单元的驱动方法，包括：
在第一阶段中，在时钟信号端、复位信号端输入低电平，信号输入端输入高电平；
在所述信号输入端的信号控制下，用所述输入模块将所述第一电压端的电压输出至上拉控制节点，对所述上拉控制节点的电位进行上拉；在所述信号输入端的信号控制下，用所述下拉控制模块将所述下拉控制 节点的信号下拉至所述第二电源端的电压；
在第二阶段中，在所述时钟信号端输入高电平，并在所述信号输入端、所述复位信号端输入低电平；
在所述上拉控制节点的控制下，用所述第一输出模块将所述时钟信号端的信号输出至所述第二输出模块；在所述第一输出模块的控制下，用所述第二输出模块将所述时钟信号端的信号输出至所述信号输出端；
在第三阶段中，在所述时钟信号端、所述信号输入端输入低电平，在所述复位信号端输入高电平；
在所述复位信号端的信号控制下，用复位模块将第一电源端的信号输出至所述下拉控制节点，对所述下拉控制节点进行上拉，在所述下拉控制节点的控制下，用所述下拉模块将所述上拉控制节点的信号以及所述信号输出端的信号下拉至所述第二电源端的电压，实现复位。
由此可见，本公开实施例提供一种移位寄存器单元、栅极驱动电路和显示装置，所述移位寄存器单元包括：第一输出模块，分别连接上拉控制节点、时钟信号端以及第二输出模块，用于在所述上拉控制节点的控制下，将所述时钟信号端的信号，输出至所述第二输出模块；第二输出模块，分别连接所述信号输出端，所述时钟信号端以及所述第一输出模块，用于在所述第一输出模块的控制下，将所述时钟信号端的信号输出至所述信号输出端；输入模块，分别连接上拉控制节点、第一电源端、信号输入端，用于在所述信号输入端的信号控制下，将所述第一电源端的电压输出至所述上拉控制节点；下拉控制模块，分别连接所述信号输入端、下拉控制节点以及第二电源端，用于在所述信号输入端的信号控制下，将所述下拉控制节点的信号下拉至所述第二电源端的电压；下拉模块，分别连接所述下拉控制节点、所述上拉控制节点、所述信号输出端以及所述第二电源端，用于在所述下拉控制节点的控制下，将所述上拉控制节点与所述信号输出端的信号下拉至第二电源端的电压；复位模块，分别连接所述第一电源端、复位信号端、所述下拉控制节点，用于在所述复位信号端的控制下，将所述第一电源端的信号输出至所述下拉控制节点。
这样一来，在充电阶段，下拉控制模块可以在信号输入端的信号控 制下，将所述下拉控制节点的电位进行下拉，以保证所述信号输出端的正常输出；在输出阶段，所述第一输出模块在所述上拉控制节点的控制下，将所述时钟信号输出端的信号输出至所述信号输出端，所述第二输出模块在所述第一输出模块的控制下，将所述时钟信号输出端的信号输出至所述信号输出端，从而能够同时将所述时钟信号输出端的信号输出至所述信号输出端，所述信号输出端的扫描信号输入至对应的栅线上；能够提升所述移位寄存器单元的输出能力，在复位阶段，复位模块可以对下拉控制节点的电位进行上拉，并通过所述下拉模块将所述上拉控制节点的电位以及所述信号输出端的电位进行下拉，提高复位效率。综上所述，通过增加一个输出模块，能够在输出阶段大大增强所述移位寄存器单元的输出能力，以及在复位阶段缩短输出波形的下降时间，进而提升栅极驱动电路的输出特性，防止由于输出特性下降而造成的画面显示异常。
附图说明
图1为本公开实施例提供的一种移位寄存器单元的结构示意图；
图2为本公开实施例提供的一种由图1所示的多个移位寄存器单元级联而构成的栅极驱动电路的结构示意图；
图3为本公开实施例提供的一种基于图1所示的移位寄存器单元的具体结构示意图；
图4为本公开实施例中图3所示的移位寄存器单元的控制信号时序图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
在本公开的描述中，需要理解的是，术语“中心”、“上”、“下”、“前”、 “后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。在本公开的描述中，除非另有说明，“多个”的含义是两个或两个以上。
图1示出本公开实施例提供一种移位寄存器单元的结构示意图。如图1所示，该移位寄存器单元可以包括：
第一输出模块10，分别连接上拉控制节点PU、时钟信号端CLK以及第二输出模块20，用于在所述上拉控制节点PU的控制下，将所述时钟信号端CLK的信号，输出至所述第二输出模块20；
第二输出模块20，分别连接信号输出端OUT、所述时钟信号端CLK以及所述第一输出模块10，用于在所述第一输出模块10的控制下，将所述时钟信号端CLK的信号输出至所述信号输出端OUT；
输入模块30，分别连接所述上拉控制节点PU、第一电源端VDD、信号输入端IN，用于在所述信号输入端IN的信号控制下，将所述第一电源端VDD的电压输出至所述上拉控制节点PU；
下拉控制模块40，分别连接所述信号输入端IN、下拉控制节点PD以及第二电源端VSS，用于在所述信号输入端IN的信号控制下，将所述下拉控制节点PD的信号下拉至所述第二电源端VSS的电压；
下拉模块50，分别连接所述下拉控制节点PD、所述上拉控制节点PU、所述信号输出端OUT以及所述第二电源端VSS，用于在所述下拉控制节点PD的控制下，将所述上拉控制节点PU与所述信号输出端OUT的信号下拉至第二电源端VSS的电压；
复位模块60，分别连接所述第一电源端VDD、复位信号端RESET以及所述下拉控制节点PD，用于在所述复位信号端RESET的控制下，将所述第一电源端VDD的信号输出至所述下拉控制节点PD。
该移位寄存器单元通过增加一个输出模块，能够在输出阶段大大增强所述移位寄存器单元的输出能力，以及在复位阶段缩短输出波形的下降时间，进而提升栅极驱动电路的输出特性，防止由于输出特性下降而造成的画面显示异常。
图2示出本公开实施例提供的一种由图1所示的多个移位寄存器单元级联而构成的栅极驱动电路的结构示意图。
示例性地，如图2所示，至少两级如上所述的移位寄存器单元(SR0、SR1…SRn)能够构成一种栅极驱动电路，每一极移位寄存器单元向各行栅线逐行输入扫描信号(G0、G1…Gn)。
其中，第一级移位寄存器单元SR0的信号输入端IN接收起始信号端STV输入的起始信号。
除第一级移位寄存器单元SR0外，其余每个移位寄存器单元的信号输入端IN与其相邻的上一级移位寄存器单元的信号输出端OUT相连接。
除最后一级移位寄存器单元SRn外，其余每个移位寄存器单元的复位信号端RESET与其相邻的下一级移位寄存器单元的信号输出端OUT相连接。
最后一级移位寄存器单元SRn的复位信号端RESET可以输入由复位信号端RST输入的复位信号。
上述栅极驱动电路具有前述实施例中的移位寄存器单元相同的有益效果，由于已经对移位寄存器单元的结构和有益效果进行了描述，在此不再赘述。
另外，本公开实施例中是以第一电压端VDD输入高电平，第二电压端VSS输入低电平为例进行的说明。
本公开实施例提供一种移位寄存器单元、栅极驱动电路和显示装置，所述移位寄存器单元包括：第一输出模块10，分别连接上拉控制节点PU、时钟信号端CLK以及第二输出模块，用于在所述上拉控制节点PU的控制下，将所述时钟信号端CLK的信号，输出至所述第二输出模块20；第二输出模块20，分别连接信号输出端OUT、所述时钟信号端CLK以及所述第一输出模块10，用于在所述第一输出模块10的控制下，将所述时钟信号端CLK的信号输出至所述信号输出端OUT；输入模块30，分别连接上拉控制节点PU、第一电源端VDD、信号输入端IN，用于在所述信号输入端IN的信号控制下，将所述第一电源端VDD的电压输出至所述上拉控制节点PU；下拉控制模块40，分别连接所述信号输入端IN、所述下拉控制节点PD以及第二电源端VSS，用于在所述信号输入端IN 的信号控制下，将所述下拉控制节点PD的信号下拉至所述第二电源端VSS的电压；下拉模块50，分别连接所述下拉控制节点PD、所述上拉控制节点PU、所述信号输出端OUT以及所述第二电源端VSS，用于在所述下拉控制节点PD的控制下，将所述上拉控制节点PU与所述信号输出端OUT的信号下拉至第二电源端VSS的电压；复位模块60，分别连接所述第一电源端VDD、复位信号端RESET以及下拉控制节点PD，用于在所述复位信号端RESET的控制下，将所述第一电源端VDD的信号输出至所述下拉控制节点PD。
这样一来，在充电阶段，所述输入模块30在所述信号输入端IN的信号控制下，将所述第一电源端VDD的电压输出至所述上拉控制节点PU，将所述上拉控制节点PU升至高电平，并对所述第一电容C1进行充电，同时，所述下拉控制模块40可以在所述信号输入端IN的信号控制下，对所述下拉控制节点PD进行降噪处理，为所述第一电容C1的正常充电提供条件。在输出阶段，所述第一输出模块10在所述上拉控制节点PU的控制下，将所述时钟信号输出端CLK的信号输出至所述信号输出端OUT，所述第二输出模块20在所述第一输出模块10的控制下，将所述时钟信号输出端CLK的信号输出至所述信号输出端OUT，从而能够同时将所述时钟信号输出端CLK的信号输出至所述信号输出端OUT，所述信号输出端OUT的扫描信号输入至对应的栅线上；能够提升所述移位寄存器单元的输出能力，同时，下拉控制模块40可以在信号输入端IN的信号控制下，将所述下拉控制节点PD的电位进行下拉，以保证所述信号输出端OUT的正常输出。在复位阶段，复位模块60可以对下拉控制节点PD的电位进行上拉，并通过所述下拉模块50将所述上拉控制节点PU的电位以及所述信号输出端OUT的电位进行下拉，提高复位效率。综上所述，通过再增加一个输出模块，能够在输出阶段大大增强所述移位寄存器单元的输出能力，以及在复位阶段缩短输出波形的下降时间，进而提升栅极驱动电路的输出特性，防止由于输出特性下降而造成的画面显示异常。
图3示出本公开实施例提供的一种基于图1所示的移位寄存器单元的具体结构示意图。
以下对如图3所示的移位寄存器单元的具体结构进行详细的举例说明。
如图3所示，所述第一输出模块10可以包含：
第一晶体管M1，其栅极连接上拉控制节点PU，第一极连接所述时钟信号端CLK，第二极连接所述第二输出模块20；
第一电容C1，其一端连接所述上拉控制节点PU，另一端连接所述第二输出模块20。
例如，在输出阶段，所述上拉控制节点PU为高电平，时钟信号端CLK的信号为高电平，可将所述第一晶体管M1导通，以通过所述第一晶体管M1将时钟信号端CLK输入的高电平信号输出至所述第二输出模块20，用于控制所述第二输出模块20输出高电平信号。
如图3所示，所述第二输出模块20可以包含：
第二晶体管M2，其栅极连接所述第一输出模块10，第一极连接所述时钟信号端CLK，第二极连接信号输出端OUT。在本公开实施例中，所述第二晶体管M2的栅极连接所述第一晶体管的第二极。
例如，在输出阶段，在所述第一输出模块10的控制下，可以将所述第二晶体管M2导通，以通过所述第二晶体管M2将时钟信号端CLK输入的高电平信号输出至所述信号输出端OUT，以作为扫描信号(G0、G1…Gn)对于移位寄存器单元(SR0、SR1…SRn)相对应的栅线进行扫描。
在所述第一输出模块10与所述第二输出模块20的共同作用下，使得所述移位寄存器单元的信号输出端的输出能力增强，从而提升整个栅极输出电路的输出特性。
如图3所示，所述输入模块30可以包含：
第三晶体管M3，其栅极连接信号输入端IN，第一极连接第一电源端VDD，第二极连接上拉控制节点PU。
例如，在充电阶段，在信号输入端IN的高电平信号控制下，可以将所述第三晶体管M3导通使得所述上拉控制节点PU升为高电平，并通过所述上拉控制节点PU对所述第一电容C1进行充电，以为移位寄存器单元输出扫描信号做准备。
如图3所示，所述下拉控制模块40包含：
第四晶体管M4，其栅极连接所述信号输入端IN，第一极连接所述下拉控制节点PD，第二极连接所述第二电源端VSS；
例如，在充电阶段，在信号输入端IN的高电平信号控制下，可以将所述第四晶体管M4的栅极打开，不断对所述下拉控制节点PD进行降噪处理，从而可以避免由于下拉控制节点PD的电位升高，误将所述第一输出模块10与所述第二输出模块20导通，使得移位寄存器单元的信号输出端OUT误输出。
如图3所示，所述下拉模块50包含：
第五晶体管M5，其栅极连接所述下拉控制节点PD，第一极连接所述上拉控制节点PU，第二极连接所述第二电源端VSS；
第六晶体管M6，其栅极连接所述下拉控制节点PD，第一极连接所述信号输出端OUT，第二极连接所述第二电源端VSS。
例如，在充电阶段，在所述下拉控制节点PD的低电平信号控制下，所述第四晶体管M4、所述第五晶体管M5与所述第六晶体管M6截止，能够对所述第一电容C1进行持续充电；在输出阶段，在所述下拉控制节点PD的低电平信号控制下，所述第四晶体管M4、第四晶体管M4、第五晶体管M5与第六晶体管M6处于截止状态，保证了所述信号输出端OUT的正常输出。
如图3所示，所述复位模块60可以包含：
第七晶体管M7，其栅极连接所述复位信号端RESET，第一极连接所述第一电源端VDD，第二极连接所述下拉控制节点PD。
例如，在复位阶段，在复位信号端RESET的高电平信号控制下，所述第七晶体管M7导通，使得所述下拉控制节点PD升至高电平，此时，所述第五晶体管M5与第六晶体管M6导通，所述第五晶体管M5与第六晶体管M6将所述上拉控制节点PU与所述信号输出端OUT的信号进行下拉，迅速将所述上拉控制节点PU与所述信号输出端OUT的电压降为低电平，能够缩短输出波形的下降时间，提高复位效率。
需要说明的是，本公开实施例中的所有晶体管均以N型晶体管为例进行的说明。其中晶体管的第一极可以为源极，第二极可以为漏极，或者晶体管的第一极可以为漏极，第二极可以为源极，本公开对此不作限 制。
可替换地，所述复位模块60与所述第二电源端VSS连接，所述复位模块60还可以包含：
第二电容C2，其一端连接所述下拉控制节点PD，另一端连接所述第二电源端VSS。
示例性地，通过设置所述第二电容C2，在充电阶段，由于所述第五晶体管M5与所述第六晶体管M6截止，能够防止自身阈值电压的漂移以及对所述第二电容C2陆续充电而导致第一电容C1充电不足；在复位阶段，在复位信号端RESET的高电平信号控制下，所述第七晶体管M7导通，对所述第二电容C2进行充电，在下一帧信号到来之前，随着时钟信号端CLK的信号的周期性变化，由于所述第二电容C2的存在，所述下拉控制节点PD始终保持高电位，不断对所述上拉控制节点PU和所述信号输出端OUT进行降噪处理，保证信号输出端OUT输出的准确性与稳定性。
图4示出了本公开实施例中图3所示的移位寄存器单元的控制信号时序图。
以下结合移位寄存器单元的时序图，如图4所示，对如图3所示的移位寄存器单元的工作过程进行详细的描述。
在第一阶段T1中，CLK＝0；PU＝1；PD＝0；IN＝1；RESET＝0。需要说明的是，以下实施例中，“0”表示低电平；“1”表示高电平。
所述输入信号端IN信号为高电平，第三晶体管M3导通，将上拉控制节点PU升至高电平，并通过所述上拉控制节点PU对所述第一电容C1充电。
与此同时，所述输入信号端IN信号为高电平，复位信号端RESET的信号为低电平，所述第四晶体管M4的栅极打开，不断对所述下拉控制节点PD进行降噪处理，使所述第二电容C2处于放电状态和所述第五晶体管M5与第六晶体管M6处于截止状态，所述下拉控制节点PD为低电平，有效防止所述第五晶体管M5与第六晶体管M6由于自身阈值电压的漂移对所述第二电容C2陆续充电而导致所述第一电容C1充电不足。
在此阶段，所述上拉控制节点PU升至高电平，此时，所述第一晶体 管M1栅极打开，但是，由于所述时钟信号端CLK的信号为低电平，所述第一晶体管M1并没有导通，所述第二晶体管M2也处于截止状态，所述信号输出端OUT输出低电平。
在第二阶段T2中，CLK＝1；PU＝1；PD＝0；IN＝0；RESET＝0。
所述时钟信号端CLK的信号为高电平，所述信号输入端IN的信号为低电平，所述第晶体管M1处于截止状态。由于所述上拉控制节点PU为高电平，所述第一晶体管M1导通，并且所述第二晶体管M2也导通，所述信号输出端OUT输出高电平。此时，由于所述第一晶体管M1与所述第二晶体管M2同时输出，增强了所述信号输出端的输出能力。
在此阶段，由于所述信号输入端IN的信号为低电平，所述复位信号端RESET的信号为低电平，所述第四晶体管M4、第五晶体管M5与第六晶体管M6均处于截止状态，PD点保持低电位，保证了所述信号输出端OUT的正常输出。
在第三阶段T3中，CLK＝0；PU＝0；PD＝1；IN＝0；RESET＝1。
所述复位信号端RESET的信号为高电平，所述第七晶体管M7导通，并对所述第二电容C2进行充电，使所述下拉控制节点PD升至高电平。此时，所述第五晶体管M5与所述第六晶体管M6导通，同时对所述第一电容C1放电，使所述上拉控制节点PU与所述信号输出端OUT的信号迅速降为低电平，实现复位功能。
在此阶段，当CLK信号从高电平转变为低电平后的短时间内，所述信号输出端OUT的电压虽有下降但还处于高电平，所述第二晶体管M2的栅极和源极还是高电平，漏极为低电平，所述第二晶体管M2还是处于导通状态，只是源漏极转换，迅速将所述信号输出端OUT的电压由高电平下拉为低电平。这样就将输出波形的下降时间缩短，复位功能的效率大大提升。
在下一帧信号到来之前，随着时钟信号端CLK的信号的周期性变化，由于所述第二电容C2的存在，所述下拉控制节点PD始终保持高电位，不断对所述上拉控制节点PU和所述信号输出端OUT进行降噪处理，保证信号输出端OUT输出的准确性与稳定性。
上述T1～T3阶段可以称为移位寄存器单元的工作时间。信号输出端 OUT只有在第二阶段T2才输出高电平，因此第二阶段T2可以为移位寄存器单元的数据输出阶段。T1、T3阶段为移位寄存器单元的非输出阶段，在此阶段内信号输出端OUT输出低电平。
示例性地，按照本公开实施例的一种用于驱动移位寄存器单元的驱动方法，包括下列工作过程：
在第一阶段中，在时钟信号端、复位信号端输入低电平，信号输入端输入高电平；在所述信号输入端的信号控制下，用输入模块将所述第一电压端的电压输出至上拉控制节点，对所述上拉控制节点的电位进行上拉；在所述信号输入端的信号控制下，用下拉控制模块将所述下拉控制节点的信号下拉至所述第二电源端的电压；
在第二阶段中，在所述时钟信号端输入高电平，所述信号输入端、所述复位信号端输入低电平；在所述上拉控制节点的控制下，用第一输出模块将所述时钟信号端的信号输出至所述第二输出模块；在所述第一输出模块的控制下，用第二输出模块将所述时钟信号端的信号输出至所述信号输出端；
在第三阶段中，在所述时钟信号端、所述信号输入端输入低电平，所述复位信号端输入高电平；在所述复位信号端的信号控制下，用复位模块将第一电源端的信号输出至所述下拉控制节点，对所述下拉控制节点进行上拉，在所述下拉控制节点的控制下，用下拉模块将所述上拉控制节点的信号以及所述信号输出端的信号下拉至所述第二电源端的电压，实现复位。
此外，上述晶体管(M1～M7)也可以均为P型晶体管。当移位寄存器单元中的晶体管，以及像素单元中与栅线相连的晶体管均为P型晶体管时。需要对驱动信号的时序，以及电路的输入信号进行相应的调整。
本公开实施例提供一种显示器件，包括如上所述的任意一种栅极驱动电路。具有与本公开前述实施例提供的栅极驱动电路相同的有益效果，由于栅极驱动电路在前述实施例中已经进行了详细说明，此处不再赘述。
该显示器件具体可以为液晶显示器、液晶电视、数码相框、手机、平板电脑等任何具有显示功能的液晶显示产品或者部件。
本公开实施例提供一种用于驱动上述任意一种移位寄存器单元的驱 动方法，可以包括：
第一阶段T1，CLK＝0；PU＝1；PD＝0；IN＝1；RESET＝0。
所述输入模块30可以在所述信号输入端IN的信号控制下，将所述第一电压端的电压输出至上拉控制节点PU，对所述上拉控制节点PU的电位进行上拉；所述下拉控制模块40可以在所述信号输入端IN的信号控制下，将所述下拉控制节点PD的信号下拉至所述第二电源端VSS的电压；从而实现对所述上拉控制节点PU持续充电，为所述移位寄存器单元输出扫描信号做准备。
第二阶段T2，CLK＝1；PU＝1；PD＝0；IN＝0；RESET＝0。
在上拉控制节点PU的控制下，所述第一输出模块10可以将所述时钟信号端CLK输入的时钟信号CLK输出至第二输出模块20，所述第二输出模块20可以在所述第一输出模块10的控制下，将所述时钟信号端CLK输入的时钟信号CLK输出至信号输出端OUT，从而使得所述信号输出端OUT向与该移位寄存器单元相连接的栅线输入扫描信号。
在本阶段，通过增加一个输出模块，能够提升所述移位寄存器单元的输出能力。
第三阶段T3，CLK＝0；PU＝0；PD＝1；IN＝0；RESET＝1。
所述复位模块60可以在所述复位信号端RESET的信号控制下，将第一电源端VDD的信号输出至所述下拉控制节点PD，对所述下拉控制节点PD进行上拉，所述下拉模块50在所述下拉控制节点PD的控制下，将所述上拉控制节点PU的信号以及所述信号输出端OUT的信号下拉至所述第二电源端VSS的电压，实现复位。
由于本阶段中，当所述时钟信号端CLK输入的时钟信号从高电平转变为低电平的短时间内，信号输出端OUT的电压虽有所下降，但还处于高电平，所述第二输出模块20中的第二晶体管M2还处于导通状态，这样，迅速将所述信号输出端OUT的电压由高电平下拉至低电平，将输出波形的下降时间缩短，复位功能的效率大大提升。
本领域普通技术人员可以理解：实现上述方法实施例的全部或部分步骤可以通过程序指令相关的硬件来完成，前述的程序可以存储于一计算机可读取存储介质中，该程序在执行时，执行包括上述方法实施例的 步骤；而前述的存储介质包括：ROM、RAM、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所附权利要求的保护范围为准。
本申请要求于2015年6月15日递交的中国专利申请第201510332638.X号的优先权，在此全文引用该中国专利申请公开的内容作为本申请的一部分。

Claims (11)

  1. 一种移位寄存器单元，包含：
    第一输出模块，分别连接上拉控制节点、时钟信号端以及第二输出模块，用于在所述上拉控制节点的控制下，将所述时钟信号端的信号，输出至所述第二输出模块；
    第二输出模块，分别连接信号输出端、所述时钟信号端以及所述第一输出模块，用于在所述第一输出模块的控制下，将所述时钟信号端的信号输出至所述信号输出端；
    输入模块，分别连接所述上拉控制节点、第一电源端、信号输入端，用于在所述信号输入端的信号控制下，将所述第一电源端的电压输出至所述上拉控制节点；
    下拉控制模块，分别连接所述信号输入端、下拉控制节点以及第二电源端，用于在所述信号输入端的信号控制下，将所述下拉控制节点的信号下拉至所述第二电源端的电压；
    下拉模块，分别连接所述下拉控制节点、所述上拉控制节点、所述信号输出端以及所述第二电源端，用于在所述下拉控制节点的控制下，将所述上拉控制节点与所述信号输出端的信号下拉至第二电源端的电压；
    复位模块，分别连接所述第一电源端、复位信号端以及所述下拉控制节点，用于在所述复位信号端的控制下，将所述第一电源端的信号输出至所述下拉控制节点。
  2. 根据权利要求1所述的移位寄存器单元，其中，所述第一输出模块包含：
    第一晶体管，其栅极连接所述上拉控制节点，第一极连接所述时钟信号端，第二极连接所述第二输出模块；
    第一电容，其一端连接所述上拉控制节点，另一端连接所述第二输出模块。
  3. 根据权利要求1所述的移位寄存器单元，其中，所述第二输出模块包含：
    第二晶体管，其栅极连接所述第一输出模块，第一极连接所述时钟 信号端，第二极连接所述信号输出端。
  4. 根据权利要求1所述的移位寄存器单元，其中，所述输入模块包含：
    第三晶体管，其栅极连接所述信号输入端，第一极连接所述第一电源端，第二极连接所述上拉控制节点。
  5. 根据权利要求1所述的移位寄存器单元，其中，所述下拉控制模块包含：
    第四晶体管，其栅极连接所述信号输入端，第一极连接所述下拉控制节点，第二极连接所述第二电源端。
  6. 根据权利要求1所述的移位寄存器单元，其中，所述下拉模块包含：
    第五晶体管，其栅极连接所述下拉控制节点，第一极连接所述上拉控制节点，第二极连接所述第二电源端；
    第六晶体管，其栅极连接所述下拉控制节点，第一极连接所述信号输出端，第二极连接所述第二电源端。
  7. 根据权利要求1所述的移位寄存器单元，其中，所述复位模块包含：
    第七晶体管，其栅极连接所述复位信号端，第一极连接所述第一电源端，第二极连接所述下拉控制节点。
  8. 根据权利要求7所述的移位寄存器单元，其中，所述复位模块与所述第二电源端连接，所述复位模块还包含：
    第二电容，其一端连接所述下拉控制节点，另一端连接所述第二电源端。
  9. 一种栅极驱动电路，其中，包含至少两级如权利要求1-8任一项所述的移位寄存器单元；
    除第一级移位寄存器单元以外，下一级移位寄存器单元的信号输出端与上一级移位寄存器单元的复位信号端相连接；
    除最后一级移位寄存器单元以外，上一级移位寄存器单元的信号输出端与下一级移位寄存器单元的信号输入端相连接；
    所述第一极移位寄存器的信号输入端输入帧起始信号；
    所述最后一极移位寄存器的复位信号端输入复位信号。
  10. 一种显示装置，其中，包括如权利要求9所述的栅极驱动电路。
  11. 一种用于驱动移位寄存器单元的驱动方法，包括：
    在第一阶段中，在时钟信号端、复位信号端输入低电平，信号输入端输入高电平；
    在所述信号输入端的信号控制下，用输入模块将所述第一电压端的电压输出至上拉控制节点，对所述上拉控制节点的电位进行上拉；在所述信号输入端的信号控制下，用下拉控制模块将所述下拉控制节点的信号下拉至所述第二电源端的电压；
    在第二阶段中，在所述时钟信号端输入高电平，所述信号输入端、所述复位信号端输入低电平；
    在所述上拉控制节点的控制下，用第一输出模块将所述时钟信号端的信号输出至所述第二输出模块；在所述第一输出模块的控制下，用第二输出模块将所述时钟信号端的信号输出至所述信号输出端；
    在第三阶段中，在所述时钟信号端、所述信号输入端输入低电平，所述复位信号端输入高电平；
    在所述复位信号端的信号控制下，用复位模块将第一电源端的信号输出至所述下拉控制节点，对所述下拉控制节点进行上拉，在所述下拉控制节点的控制下，用下拉模块将所述上拉控制节点的信号以及所述信号输出端的信号下拉至所述第二电源端的电压，实现复位。
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