WO2017000737A1 - 一种传输校验方法、节点、系统与计算机存储介质 - Google Patents

一种传输校验方法、节点、系统与计算机存储介质 Download PDF

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Publication number
WO2017000737A1
WO2017000737A1 PCT/CN2016/084314 CN2016084314W WO2017000737A1 WO 2017000737 A1 WO2017000737 A1 WO 2017000737A1 CN 2016084314 W CN2016084314 W CN 2016084314W WO 2017000737 A1 WO2017000737 A1 WO 2017000737A1
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Prior art keywords
serdes
synchronization frame
receiving
frame
normal state
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PCT/CN2016/084314
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English (en)
French (fr)
Inventor
刘新良
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Sanechips Technology Co Ltd
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Sanechips Technology Co Ltd
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Priority to EP16817101.5A priority Critical patent/EP3319249B1/en
Priority to US15/574,718 priority patent/US10523235B2/en
Publication of WO2017000737A1 publication Critical patent/WO2017000737A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/10—Arrangements for initial synchronisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B17/00—Monitoring; Testing
    • H04B17/30—Monitoring; Testing of propagation channels
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40006—Architecture of a communication node
    • H04L12/40045—Details regarding the feeding of energy to the node from the bus
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M9/00—Parallel/series conversion or vice versa
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0658—Clock or time synchronisation among packet nodes

Definitions

  • the present invention relates to data communication interface technologies, and in particular, to a transmission verification method, a node, a system, and a computer storage medium.
  • SERDES is an abbreviation for SERializer/DESerializer. It is a mainstream time division multiplexing (TDM), point-to-point (P2P) serial communication technology. That is, the multi-channel low-speed parallel signal is converted into a high-speed serial signal at the transmitting end, passes through the transmission medium (optical cable or copper wire), and finally the high-speed serial signal is reconverted into a low-speed parallel signal at the receiving end. Due to its high speed and high precision, low pin count and low power consumption, SERDES is widely used in modern communication chips. In systems using SERDES for inter-board or inter-chip data communication, SERDES instability is often encountered.
  • the cause of this phenomenon may be due to internal causes such as instability of the SERDES reference clock, and on the other hand. It is caused by external reasons such as the board's routing does not meet the requirements.
  • SERDES data communication is closely related to the external conditions required for SERDES operation, including external conditions such as clock, reset, power supply voltage, magnetic field, electric field, etc., which may affect the stability of SERDES, and this effect is not completely predictable.
  • the embodiments of the present invention provide a transmission verification method, a node, a system, and a computer storage medium, which can improve the stability and reliability of the SERDES path.
  • the embodiment of the invention provides a transmission verification method, and the method includes:
  • the SERDES transmitting end sends a first synchronization frame to the SERDES receiving end, and after receiving the second synchronization frame sent by the SERDES receiving end, the SERDES transmitting end determines that its own sending path and receiving path are in a normal state;
  • the SERDES sender sends a third synchronization frame to the SERDES receiver.
  • a first identifier bit and a second identifier bit are disposed in a frame header of the first synchronization frame, the second synchronization frame, and the third synchronization frame;
  • the preset value is used, the local receiving channel is in a normal state;
  • the second identifying position is at a preset value, the opposite receiving channel is in a normal state.
  • the embodiment of the invention further provides a transmission verification method, the method comprising:
  • the SERDES receiving end After receiving the first synchronization frame sent by the SERDES sender, the SERDES receiving end sends a second synchronization frame to the SERDES sender;
  • the SERDES receiving end After the SERDES receiving end receives the third synchronization frame sent by the SERDES transmitting end, the SERDES receiving end determines that its own sending path and receiving path are in a normal state.
  • a first identifier bit and a second identifier bit are disposed in a frame header of the first synchronization frame, the second synchronization frame, and the third synchronization frame;
  • the preset value is used, the local receiving channel is in a normal state;
  • the second identifying position is at a preset value, the opposite receiving channel is in a normal state.
  • the embodiment of the invention further provides a transmission verification method, the method comprising:
  • the SERDES sender sends the first synchronization frame to the SERDES receiver
  • the SERDES receiving end After receiving the first synchronization frame, the SERDES receiving end sends a second synchronization frame to the SERDES sending end;
  • the SERDES transmitting end After the SERDES transmitting end receives the second synchronization frame, the SERDES transmitting end determines that both the sending path and the receiving path of the SERDES are in a normal state, and sends a third synchronization frame to the SERDES receiving end.
  • the SERDES receiving end After the SERDES receiving end receives the third synchronization frame, the SERDES receiving end determines that its own transmission path and receiving path are in a normal state.
  • a first identifier bit and a second identifier bit are disposed in a frame header of the first synchronization frame, the second synchronization frame, and the third synchronization frame;
  • the preset value is used, the local receiving channel is in a normal state;
  • the second identifying position is at a preset value, the opposite receiving channel is in a normal state.
  • the SERDES sending end sends the first synchronization frame to the SERDES receiving end, including: the SERDES sending end sends the plurality of first synchronization frames and the K code at intervals;
  • the SERDES receiving end determines whether the receiving channel is in a normal state based on whether the K code is decoded.
  • the embodiment of the present invention further provides a SERDES transmitting end, where the SERDES transmitting end includes: a first sending unit and a first receiving unit;
  • the first sending unit is configured to send a first synchronization frame to the SERDES receiving end, and configured to: after the first receiving unit receives the second synchronization frame, send the third synchronization frame to the SERDES receiving end ;
  • the first receiving unit is configured to receive a second synchronization frame sent by the SERDES receiving end.
  • a first identifier bit and a second identifier bit are disposed in a frame header of the first synchronization frame, the second synchronization frame, and the third synchronization frame;
  • the preset value is used, the local receiving channel is in a normal state;
  • the second identifying position is at a preset value, the opposite receiving channel is in a normal state.
  • the embodiment of the present invention further provides a SERDES receiving end, where the SERDES receiving end includes: a second sending unit and a second receiving unit;
  • the second receiving unit is configured to receive the first synchronization frame sent by the SERDES sending end, and is further configured to receive the third synchronization frame sent by the SERDES sending end;
  • the second sending unit is configured to send the second synchronization frame to the SERDES sending end after the second receiving unit receives the first synchronization frame.
  • a first identifier bit and a second identifier bit are disposed in a frame header of the first synchronization frame, the second synchronization frame, and the third synchronization frame;
  • the preset value is used, the local receiving channel is in a normal state;
  • the second identifying position is at a preset value, the opposite receiving channel is in a normal state.
  • the embodiment of the present invention further provides a transmission verification system, where the system includes: a SERDES transmitting end and a SERDES receiving end; wherein
  • the SERDES transmitting end is configured to send a first synchronization frame to the SERDES receiving end, and is further configured to: after receiving the second synchronization frame of the SERDES receiving end, determine that both the sending path and the receiving path are in a normal state; Sending, by the SERDES receiving end, a third synchronization frame;
  • the SERDES receiving end is configured to: after receiving the first synchronization frame sent by the SERDES sending end, send a second synchronization frame to the SERDES sending end; and configured to receive the sending by the SERDES sending end After the third synchronization frame is described, it is determined that both the transmission path and the reception path of the self are in a normal state.
  • a first identifier bit and a second identifier bit are disposed in a frame header of the first synchronization frame, the second synchronization frame, and the third synchronization frame;
  • the preset value is used, the local receiving channel is in a normal state;
  • the second identifying position is at a preset value, the opposite receiving channel is in a normal state.
  • the SERDES sending end is configured to send multiple first synchronization frames and K codes at intervals;
  • the SERDES receiving end is configured to determine whether the receiving channel is in a normal state based on whether the K code is decoded.
  • the embodiment of the present invention further provides a computer storage medium, where the computer storage medium stores computer executable instructions, and the computer executable instructions are used to execute the embodiment of the present invention.
  • the transmission verification method applied to the SERDES sender is not limited to the SERDES sender.
  • the embodiment of the present invention further provides a computer storage medium, where the computer storage medium stores computer executable instructions, and the computer executable instructions are used to perform transmission verification applied to the SERDES receiving end according to the embodiment of the present invention. method.
  • the transmission verification method, the node, the system, and the computer storage medium provided by the embodiment of the present invention send a first synchronization frame to the SERDES receiving end through the SERDES sending end; after receiving the first synchronization frame, the SERDES receiving end receives the first synchronization frame The SERDES transmitting end sends a second synchronization frame. After the SERDES transmitting end receives the second synchronization frame, the SERDES transmitting end determines that both the sending path and the receiving path of the SERDES are in a normal state, and sends the SYNCDES receiving end to the SERDES receiving end.
  • the SERDES receiving end determines that its own transmission path and receiving path are in a normal state.
  • the SERDES sending end and the SERDES receiving end can determine whether the receiving channel and the sending channel of the SERDES are both at the SERDES and the SERDES receiving end can determine whether the receiving channel and the sending channel are in the same manner.
  • the normal state greatly improves the security of data transmission, ensures a stable SERDES path, and enhances the user experience.
  • FIG. 1 is a schematic flowchart of a transmission verification method according to Embodiment 1 of the present invention.
  • FIG. 2 is a schematic diagram of interaction of a transmission verification method according to Embodiment 1 of the present invention.
  • Embodiment 3 is a schematic diagram of a frame structure in Embodiment 2 of the present invention.
  • FIG. 4 is a schematic diagram of a state-based interaction of a transmission verification method according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of application of a transmission verification method according to an embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of a structure of a transmission verification system according to an embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of a structure of a SERDES transmitting end according to an embodiment of the present invention.
  • FIG. 8 is a schematic structural diagram of a structure of a SERDES receiving end according to an embodiment of the present invention.
  • the inventors in order to ensure the stability of the SERDES path, the inventors have found in practical applications that it is extremely unreliable to judge the operating state of the SERDES from signals such as the synchronization state of the SERDES. Because the synchronization of SERDES takes a while to stabilize, it is sometimes found that the sync state of the SERDES is pulled low and then pulled low, but in the end, the sync state should be high. In another case, the state of one end of the SERDES path is normal, but the state of the other end is not yet stable, and sometimes even a SERDES error state at one end is continuously reported.
  • the synchronization state of the SERDES is normal, which does not mean that the SERDES has stabilized.
  • This synchronization state may be repeated for a period of time; on the other hand, the state of one end of the SERDES path is normal or stable, and does not mean that the other end is normal. Or stable.
  • the signal according to the SERDES synchronization status is simply used as the basis for transmitting data, it is possible that the SERDES path is still in an unstable state, that is, the receiving end cannot receive the correct data.
  • the data transmission of the SERDES does not have a prescribed handshake signal, the data transmission cannot be known through immediate feedback.
  • the transmitting end of the SERDES when the data sent by the SERDES reaches the receiving end of the SERDES, the receiving end cannot immediately notify the SERDES that the data has been received, and the SERDES receiving end can only send the SERDES path to the SERDES by sending a response data.
  • the data SERDES sender knows that the SERDES receiver has received the data. By receiving the response data, the SERDES sender can also infer that the transmit channel and the receive channel of the SERDES channel can transmit and receive data normally with respect to the SERDES transmitter itself.
  • the embodiment of the invention provides a transmission verification method.
  • 1 is a schematic flowchart of a transmission verification method according to Embodiment 1 of the present invention; as shown in FIG. 1, the method includes:
  • Step 101 The SERDES sender sends a first synchronization frame to the SERDES receiver.
  • Step 102 After receiving the first synchronization frame, the SERDES receiving end sends a second synchronization frame to the SERDES sending end.
  • Step 103 After receiving the second synchronization frame, the SERDES sender sends a third synchronization frame to the SERDES receiver, so that the SERDES sender and the SERDES receiver respectively determine their own transmission path and The receiving path is in a normal state.
  • the SERDES transmitting end and the SERDES receiving end are respectively two ends of the SERDES path.
  • the SERDES includes a SERializer and a deserializer, and the serializer may be referred to as a SERDES transmitter (TX) described in this embodiment, and the deserializer may be referred to as the embodiment.
  • TX SERDES transmitter
  • RX SERDES receiving end
  • FIG. 2 is an interaction diagram of a transmission verification method according to Embodiment 1 of the present invention; the interaction between the SERDES sender and the SERDES receiver may be specifically as shown in FIG. 2 .
  • the transmission verification method of the SERDES in this embodiment includes:
  • Step 201 When the SERDES sender detects that the current synchronization state is currently in the normal state, the first synchronization frame is sent.
  • the first synchronization frame is recorded as patern0.
  • Step 202 After the SERDES receiving end receives patern0, the SERDES receiving end may determine that its receiving channel is in a normal state on the one hand, and may also know that the sending channel of the SERDES transmitting end is in a normal state. Further, the SERDES receiving end sends a second synchronization frame to the SERDES sending end, and the second synchronization frame is recorded as patern1 in this embodiment.
  • Step 203 After the SERDES sender receives the patern1, the SERDES sender may determine that both the sending channel and the receiving channel are in a normal state, and may also determine that the sending channel of the SERDES receiving end is in a normal state. . Further, the SERDES sending end sends a third synchronization frame to the SERDES receiving end, and the third synchronization frame is recorded as patern2 in this embodiment. After the SERDES receiving end receives patern2, the SERDES can determine that its own receiving channel and sending channel are in a normal state.
  • the SERDES sending end and the SERDES receiving end can determine their own receiving channel and the three-way handshake process of sending the first synchronization frame, receiving the second synchronization frame, and transmitting the third synchronization frame. Whether the sending channel is in a normal state greatly improves the security of data transmission.
  • the three-way handshake process of three synchronization frames is mutually sent by the SERDES, so that the SERDES sender and the SERDES receiver can determine whether the receiving channel and the sending channel are in a normal state. , greatly improve the security of data transmission, ensure a stable SERDES path, and enhance the user experience.
  • the first identifier bit and the first identifier bit are set in the frame headers of the first synchronization frame, the second synchronization frame, and the third synchronization frame.
  • the second identifier bit; the first identifier position indicates that the local receiving channel is in a normal state when the preset value is at a preset value; and the second identifier position indicates that the opposite end receiving channel is in a normal state when the second identifier position is at a preset value.
  • the first synchronization frame, the second synchronization frame, and the third synchronization frame are both It can be called a sync frame.
  • a data frame is transmitted in addition to the synchronization frame between the SERDES transmitting end and the SERDES receiving end; the synchronization frame and the data frame may be referred to as a private frame in this embodiment.
  • 3 is a schematic diagram of a frame structure in Embodiment 2 of the present invention; as shown in FIG. 3, the frame structure of the private frame includes: a frame header (FH, Frame Header), control information (FC, Frame Control), and a payload. (FP, Frame Payload) and Cyclic Redundancy Check (CRC).
  • FH Frame Header
  • FC Frame Control
  • FP Frame Payload
  • CRC Cyclic Redundancy Check
  • the size of the payload (FP) is preferably that the data frame length can be divisible by the bit width and meet the system's rate requirement; in one embodiment, the payload The (FP) size can be 32 bytes.
  • Table 1 is a schematic diagram of a specific mapping relationship of a private frame. As shown in Table 1, when the private frame is a synchronization frame, the bit 15 of the frame header is set to 0, indicating that the current frame is a synchronization frame, and when the private frame is When the frame is a sync frame, the payload (FP) field is not included in the frame structure.
  • the bit 15 of the frame header is set to 1, indicating that the current frame is a data frame; and the payload (FP) field of the data frame is used to carry user data.
  • the CRC part of the frame structure of the private frame is an optional part, which is used for alarming.
  • the bit 8 and the bit 7 of the frame header carry a flag indicating whether or not the synchronization is performed.
  • the bit 8 is used to indicate that the local SERDES receiving channel has already been a character.
  • bit 7 is used to indicate that the peer SERDES receiving channel has been character synchronized, so that both the SERDES transmitting end and the SERDES receiving end can determine whether the receiving channel and the transmitting channel are in a normal state, so that the SERDES transmission is more stable and reliable.
  • the user data in the process of transmitting user data through the SERDES path, that is, when transmitting a data frame, the user data is encapsulated by using a frame structure as shown in Table 1, that is, the representation is set in the data frame. Whether the local end and the opposite end are synchronized to determine whether the current SERDES sender or SERDES receiver has been synchronized during user data transmission, thereby ensuring the stability and reliability of data transmission.
  • the sending, by the SERDES, the first synchronization frame to the SERDES receiving end includes: sending, by the SERDES sending end, a plurality of first synchronization frames and a K code;
  • the SERDES receiving end determines whether the receiving channel is in a normal state based on whether the K code is decoded.
  • the SERDES sending end may send multiple synchronization frames at intervals (in this embodiment)
  • the first synchronization frame in other embodiments, it may also be a second synchronization frame or a third synchronization frame) and a K code, such as a transmission synchronization frame, a K code, a synchronization frame, a K code, etc., wherein the SERDES reception
  • the K code is obtained by decoding whether to determine whether the character boundary is correct during transmission (ie, during serial-to-parallel conversion); when decoding obtains K code, it is determined that the character boundary during transmission is correct;
  • the decoding does not obtain the K code, it is determined that the character boundary in the transmission process is incorrect, and it is necessary to move backward one frame bit, and wait until the response time to continue to judge whether to obtain the K code until the K code is successfully obtained.
  • FIG. 4 is a schematic diagram of the state-based interaction of the transmission verification method according to the embodiment of the present invention; as shown in FIG. 4, in the embodiment, four presets are provided. Status: IDLE state, TXP0 state, TXP1 state, and WAIT state;
  • IDLE state After the power-on reset, the SERDES completes the initial state after the state is synchronized. In the IDLE state, if one end of the SERDES path does not receive the patern0 synchronization frame, the state switches to the transmission state TXP0 state of the partial0 synchronization frame; if the patern0 synchronization frame is received in the IDLE state, the state switches to the transmission state TXP1 of the patern1 synchronization frame. status;
  • TXP0 state This is the transmission state of the patern0 synchronization frame.
  • the patern0 synchronization frame is sent, waiting for the patern1 synchronization frame returned by the peer.
  • the patern1 synchronization frame indicates that the current transceiver path is normal and switches to the wait state (WAIT).
  • WAIT wait state
  • a patern0 sync frame needs to be continually issued until a sufficient number of patern1 sync frames are received. If there is no patern1 synchronization frame return after waiting for the preset time, the judgment is timed out, the state jumps back to the IDLE state, and an interrupt report is generated.
  • TXP1 state This is the transmission state of the patern1 sync frame. Since the patern0 synchronization frame has been received, the patern1 synchronization frame needs to be returned to the peer to confirm. In one embodiment, by returning a certain number of patern1 sync frames, it indicates that it has received the initial patern0 sync frame, and waits for the peer to return a patern2 sync frame for acknowledgment transmission.
  • the TXP1 state the TX end is constantly The patern2 synchronization frame is sent, and the RX end receives a certain number of patern2 synchronization frames, indicating that the entire handshake process is completed, and the state is switched to the wait state (WAIT). However, if there is no patern2 synchronization frame return in the TXP1 state for a preset time, the timeout is determined, the state is switched to the IDLE state, and an interrupt report is generated.
  • WAIT state The state is to prevent the two ends of the SERDES from exiting the handshake detection mechanism from being inconsistent, resulting in detecting that the synchronization frame leaks to the user interface and increasing a delay waiting state.
  • the RX terminal first detects the received patern2 synchronization frame, and then does not receive the patern2 packet within the preset time (MAX_RX_DELAY), indicating that the handshake process ends, and the RX terminal switches from the automatic detection mechanism to the normal output.
  • the channel, the data frame received from the SERDES is directly output to the user interface.
  • the patern2 synchronization frame stops for a longer period of time (MAX_DELAY) to ensure that the TX side switches from the automatic detection mechanism to the normal user channel when both ends of the SERDES have completed the entire handshake process.
  • MAX_DELAY a longer period of time
  • the transmission verification method of the SERDES includes:
  • Step 301 After the power-on reset, one end of the SERDES path is in the IDLE state after the completion state synchronization.
  • IDLE state when the patern0 synchronization frame is not received within the first preset time, the switch is switched to the TXP0 state, and the patern0 synchronization is issued. Frame, at this point, one end of the SERDES path acts as the transmit (TX) side.
  • Step 302 The other end of the SERDES path is in the IDLE state, and after receiving the patern0 synchronization frame within the preset time, switching to the transmit state TXP1 state of the patern1 synchronization frame. At this time, the other end of the SERDES path is received. (RX) side, and send patern1 synchronization frame to the TX end.
  • Step 303 The TX end waits for the patern1 synchronization frame returned by the RX end in the TXP0 state.
  • the patern1 synchronization frame When the patern1 synchronization frame is received, it indicates that the TX end transceiver path is normal, and switches to Wait state (WAIT) and send patern2 sync frame to RX.
  • WAIT Wait state
  • Step 304 In the TXP1 state, the RX terminal waits for the TX terminal to return the patern2 synchronization frame for confirming the transmission. After receiving the patern2 synchronization frame, it indicates that the RX terminal's transmission and reception path is normal, and switches to the waiting state (WAIT), and the handshake process ends.
  • WAIT waiting state
  • FIG. 5 is a schematic diagram of application of a transmission verification method according to an embodiment of the present invention; as shown in FIG. 5, including node A and node B; A_rx and A_tx respectively represent a receiving end and a transmitting end of an A node, and B_rx and B_tx respectively represent a B node.
  • S stands for sync frame
  • K stands for K code
  • D stands for data frame.
  • Step 1 After the A node reset is completed, the A_tx interval sends the synchronization frame and the K code; the K code is for the receiver to decode the K code by using the 8B/10B decoding mode to determine whether the character boundary of the SERDES in the serial-to-parallel conversion is correct; When the receiving end receives the K code, it indicates that the character boundary is correct; when the receiving end does not receive the K code, the A_rx channel character boundary is configured to move backward by 1 frame bit (UI), and wait for the SERDES response time to continue to judge until the SERDES response time is reached. Successfully received the K code.
  • UI 1 frame bit
  • the number of K codes sent is greater than the N value (N can be pre-configured, for example, configurable to 20); when the receiving end receives N-1 K codes, it indicates that the SERDES has Character synchronization. Character synchronization ensures the correctness of the received data. This process is shown as 1 in Figure 5; then jump to Step2.
  • Step 2 A_tx continues to send the synchronization frame and the K code, and A_rx continuously detects the synchronization frame 3 times, and then informs A_tx that the frame header bit 8 of the synchronization frame header is set to 1, indicating that A_rx has received at least 3 synchronization frames. As shown in 2 of Figure 5.
  • Step 3 A_tx starts sending data frames.
  • the data frame carries timing information of the user data.
  • the K code of the intermediate interval may be 1 to 3 lengths.
  • the A node and the B node belong to a symmetric node, so the operations of the two are identical. Therefore, the transmission verification method based on the Node B SERDES will not be described again.
  • the CRC check is optional as part of the reliability design and can help check the SERDES error. Use the counter to accumulate the number of frames sent and the number of erroneous frames.
  • the three-way handshake process of three synchronous frames is mutually transmitted through the SERDES, so that both the SERDES transmitting end and the SERDES receiving end can determine whether the receiving channel and the sending channel of the SERDES are in the
  • the normal state greatly improves the security of data transmission, ensures a stable SERDES path, and improves the user experience.
  • a flag indicating whether the local end and the opposite end are synchronized is encapsulated in the data frame, so that During the user data transmission process, it is determined whether the current SERDES sender or the SERDES receiver has been synchronized, thereby ensuring the stability and reliability of data transmission; finally, by inserting the K code in the data frame or the synchronization frame, the SERDES path can be found in time. Whether it is abnormal, and timely discover whether the data is safely arrived at the peer end, thereby improving the security of data transmission.
  • the embodiment of the invention further provides a transmission verification method, the SERDES described in this embodiment
  • the transmission check method is applied to the sender.
  • the method includes:
  • Step 401 The SERDES sending end sends a first synchronization frame to the SERDES receiving end. After receiving the second synchronization frame sent by the SERDES receiving end, the SERDES transmitting end determines that both the sending path and the receiving path of the SERDES are in a normal state.
  • Step 402 The SERDES sending end sends a third synchronization frame to the SERDES receiving end.
  • a first identifier bit and a second identifier bit are disposed in the frame headers of the first synchronization frame, the second synchronization frame, and the third synchronization frame; when the first identifier position is at a preset value The local receiving channel is in a normal state; and the second identifying position is at a preset value to indicate that the opposite receiving channel is in a normal state.
  • the embodiment of the present invention further provides a transmission verification method, and the transmission verification method of the SERDES described in this embodiment is applied to a receiving end.
  • the method includes:
  • Step 501 After receiving the first synchronization frame sent by the SERDES sender, the SERDES receiver sends a second synchronization frame to the SERDES sender.
  • Step 502 After the SERDES receiving end receives the third synchronization frame sent by the SERDES sending end, the SERDES receiving end determines that its own sending path and receiving path are in a normal state.
  • a first identifier bit and a second identifier bit are disposed in the frame headers of the first synchronization frame, the second synchronization frame, and the third synchronization frame; when the first identifier position is at a preset value The local receiving channel is in a normal state; and the second identifying position is at a preset value to indicate that the opposite receiving channel is in a normal state.
  • the transmission verification method of the SERDES according to the third embodiment and the fourth embodiment of the present invention is described by the SERDES receiving end of the SERDES transmitting end as an execution subject, and the transmission verification method of the SERDES according to the embodiment of the present invention is described.
  • the third embodiment and the embodiment Specific description can be As described in the first embodiment and the second embodiment, details are not described herein again.
  • Embodiments of the present invention provide a transmission verification system.
  • 6 is a schematic structural diagram of a structure of a transmission verification system according to an embodiment of the present invention; as shown in FIG. 6, the system includes: a SERDES transmitting end and a SERDES receiving end;
  • the SERDES transmitting end is configured to send a first synchronization frame to the SERDES receiving end, and is further configured to: after receiving the second synchronization frame of the SERDES receiving end, determine that both the sending path and the receiving path are in a normal state; Sending, by the SERDES receiving end, a third synchronization frame;
  • the SERDES receiving end is configured to: after receiving the first synchronization frame sent by the SERDES sending end, send a second synchronization frame to the SERDES sending end; and configured to receive the sending by the SERDES sending end After the third synchronization frame is described, it is determined that both the transmission path and the reception path of the self are in a normal state.
  • a first identifier bit and a second identifier bit are disposed in the frame headers of the first synchronization frame, the second synchronization frame, and the third synchronization frame; when the first identifier position is at a preset value The local receiving channel is in a normal state; and the second identifying position is at a preset value to indicate that the opposite receiving channel is in a normal state.
  • the first synchronization frame, the second synchronization frame, and the third synchronization frame may be referred to as synchronization frames.
  • a data frame is transmitted in addition to the synchronization frame between the SERDES transmitting end and the SERDES receiving end; the synchronization frame and the data frame may be referred to as a private frame in this embodiment.
  • the frame structure of the private frame includes: a frame header (FH), control information (FC), a payload (FP), and a cyclic redundancy check code (CRC).
  • the size of the payload (FP) is preferably that the data frame length can be divisible by the bit width and meet the system's rate requirement; in one embodiment, the payload The (FP) size can be 32.
  • the bit 15 of the frame header is set to 0, indicating that the current frame is a synchronization frame, and when the private frame is a synchronization frame, the frame structure is not Includes payload (FP) domain.
  • the bit 15 of the frame header is set to 1, indicating that the current frame is a data frame; and the payload (FP) field of the data frame is used to carry user data.
  • the bit 8 and the bit 7 of the frame header carry a flag indicating whether or not the synchronization is performed.
  • the bit 8 is used to indicate that the local SERDES receiving channel has already been a character.
  • bit 7 is used to indicate that the peer SERDES receiving channel has been character synchronized, so that both the SERDES transmitting end and the SERDES receiving end can determine whether the receiving channel and the transmitting channel are in a normal state, so that the SERDES transmission is more stable and reliable.
  • the user data in the process of transmitting user data through the SERDES path, that is, when the SERDES transmitting end transmits a data frame, the user data is encapsulated by using a frame structure as shown in Table 1, that is, A flag indicating whether the local end and the opposite end are synchronized is set in the data frame to determine whether the current SERDES transmitting end or the SERDES receiving end has been synchronized during the user data transmission, thereby ensuring the stability and reliability of data transmission.
  • the SERDES sending end is configured to send multiple first synchronization frames and K codes at intervals;
  • the SERDES receiving end is configured to determine whether the receiving channel is in a normal state based on whether the K code is decoded.
  • the SERDES transmitting end may send multiple synchronization frames (in this embodiment, a first synchronization frame, in other embodiments, a second synchronization frame or a third synchronization frame) and a K code, for example, for example, for example,
  • the synchronization frame, the K code, the synchronization frame, and the K code are sent at intervals, wherein the SERDES receiving end obtains the K code by decoding whether it is decoded or not, and is used to determine the character boundary during the transmission process (ie, the serial-to-parallel conversion process).
  • the functions of the nodes in the transmission verification system of the embodiment of the present invention can be understood by referring to the related description of the transmission verification method of the foregoing SERDES, and the transmission verification system of the SERDES in the embodiment of the present invention
  • the node can be implemented by an analog circuit that implements the functions described in the embodiments of the present invention, or can be implemented by running the software of the functions described in the embodiments of the present invention on the smart terminal.
  • FIG. 7 is a schematic structural diagram of a SERDES transmitting end according to an embodiment of the present invention; as shown in FIG. 7, the SERDES transmitting end includes: a first sending unit and a first receiving unit;
  • the first sending unit is configured to send a first synchronization frame to the SERDES receiving end, and configured to: after the first receiving unit receives the second synchronization frame, send the third synchronization frame to the SERDES receiving end ;
  • the first receiving unit is configured to receive a second synchronization frame sent by the SERDES receiving end.
  • a first identifier bit and a second identifier bit are disposed in the frame headers of the first synchronization frame, the second synchronization frame, and the third synchronization frame; when the first identifier position is at a preset value The local receiving channel is in a normal state; and the second identifying position is at a preset value to indicate that the opposite receiving channel is in a normal state.
  • the first synchronization frame, the second synchronization frame, and the third synchronization frame may be referred to as synchronization frames.
  • a data frame is transmitted in addition to the synchronization frame between the SERDES transmitting end and the SERDES receiving end; the synchronization frame and the data frame may be referred to as a private frame in this embodiment.
  • the frame structure of the private frame includes: a frame header (FH), control information (FC), a payload (FP), and a cyclic redundancy check code (CRC).
  • FH frame header
  • FC control information
  • FP payload
  • CRC cyclic redundancy check code
  • the bit width is large and meets the system's rate requirements; in one embodiment, the payload (FP) size can be 32.
  • the payload (FP) size can be 32.
  • Table 1 when the private frame is a synchronization frame, the bit 15 of the frame header is set to 0, indicating that the current frame is a synchronization frame, and when the private frame is a synchronization frame, the frame structure does not include a net. Charge (FP) domain.
  • the bit 15 of the frame header is set to 1, indicating that the current frame is a data frame; and the payload (FP) field of the data frame is used to carry user data.
  • the bit 8 and the bit 7 of the frame header carry a flag indicating whether or not the synchronization is performed.
  • the bit 8 is used to indicate that the local SERDES receiving channel has already been a character.
  • bit 7 is used to indicate that the peer SERDES receiving channel has been character synchronized, so that both the SERDES transmitting end and the SERDES receiving end can determine whether the receiving channel and the transmitting channel are in a normal state, so that the SERDES transmission is more stable and reliable.
  • the first sending unit is further configured to: when the data frame is sent, use the frame structure as shown in Table 1 to encapsulate the user data, that is, set the data frame to indicate whether the local end and the opposite end are synchronized. Marking to determine whether the current SERDES sender or SERDES receiver has been synchronized during user data transmission, thus ensuring the stability and reliability of data transmission.
  • the first sending unit is further configured to send a plurality of first synchronization frames and K codes to the receiving end at intervals, so that when the receiving end decodes, whether the K code is obtained by decoding is used to determine the transmission process. Medium (ie during serial-to-parallel conversion), whether the character boundaries are correct.
  • the first sending unit may send multiple synchronization frames (the first synchronization frame in this embodiment, and may also be the second synchronization frame or the third synchronization frame in other embodiments) and the K code.
  • the synchronization frame, the K code, the synchronization frame, the K code, and the like are sent at intervals; wherein, when the SERDES receiving end decodes, the K code is obtained by decoding whether the character is judged during the transmission (ie, during the serial-to-parallel conversion process), the character Whether the boundary is correct; when the decoding obtains the K code, it is determined during the transmission process.
  • the character boundary in the middle is correct; when the K code is not obtained by decoding, it is determined that the character boundary in the transmission process is incorrect, and it is necessary to move backward one frame bit, and wait until the response time to continue to judge whether to obtain the K code until the success is obtained. K code so far.
  • FIG. 8 is a schematic structural diagram of a SERDES receiving end according to an embodiment of the present invention. As shown in FIG. 8, the SERDES receiving end includes: a second sending unit and a second receiving unit;
  • the second receiving unit is configured to receive the first synchronization frame sent by the SERDES sending end, and is further configured to receive the third synchronization frame sent by the SERDES sending end;
  • the second sending unit is configured to send the second synchronization frame to the SERDES sending end after the second receiving unit receives the first synchronization frame.
  • a first identifier bit and a second identifier bit are disposed in the frame headers of the first synchronization frame, the second synchronization frame, and the third synchronization frame; when the first identifier position is at a preset value The local receiving channel is in a normal state; and the second identifying position is at a preset value to indicate that the opposite receiving channel is in a normal state.
  • the first synchronization frame, the second synchronization frame, and the third synchronization frame may be referred to as synchronization frames.
  • a data frame is transmitted in addition to the synchronization frame between the SERDES transmitting end and the SERDES receiving end; the synchronization frame and the data frame may be referred to as a private frame in this embodiment.
  • the frame structure of the private frame includes: a frame header (FH), control information (FC), a payload (FP), and a cyclic redundancy check code (CRC).
  • the bit width is 16 bits, and the size of the payload (FP) is preferably such that the data frame length can divide the bit width and meet the system's rate requirement; in one embodiment, the payload (FP) size Can be 32.
  • the bit 15 of the frame header is set to 0, indicating that the current frame is a synchronization frame, and when the private frame is a synchronization frame, the frame structure does not include a net. Charge (FP) domain.
  • the bit 15 of the frame header is set to 1, indicating that the current frame is a data frame; and the payload (FP) field of the data frame is used to carry user data.
  • the bit 8 and the bit 7 of the frame header carry a flag indicating whether or not the synchronization is performed.
  • the bit 8 is used to indicate that the local SERDES receiving channel has already been a character.
  • bit 7 is used to indicate that the peer SERDES receiving channel has been character synchronized, so that both the SERDES transmitting end and the SERDES receiving end can determine whether the receiving channel and the transmitting channel are in a normal state, so that the SERDES transmission is more stable and reliable.
  • the second receiving unit is further configured to determine whether the receiving channel is in a normal state based on whether the K code is decoded.
  • the SERDES transmitting end may send multiple synchronization frames (in this embodiment, a first synchronization frame, in other embodiments, a second synchronization frame or a third synchronization frame) and a K code, for example, for example, Transmitting a synchronization frame, a K code, a synchronization frame, a K code, etc., wherein the second receiving unit determines whether the K code is obtained by decoding or not during decoding (ie, during serial-to-parallel conversion).
  • a K code for example, for example, Transmitting a synchronization frame, a K code, a synchronization frame, a K code, etc.
  • each of the processing modules in the SERDES receiving end of the embodiment of the present invention may be implemented by an analog circuit that implements the functions described in the embodiments of the present invention, or may be executed by the software executing the functions described in the embodiments of the present invention on the smart terminal. achieve.
  • the SERDES sending end and the SERDES receiving end are implemented in a practical application by a node device adopting a SERDES interface, and the first sending unit and the first in the SERDES sending end are
  • the receiving unit in practical applications, can be implemented by a transceiver antenna or a transceiver in the SERDES transmitting end.
  • the second sending unit and the second receiving unit in the SERDES receiving end may be implemented by a transceiver antenna or a transceiver in the SERDES receiving end in practical applications.
  • the disclosed apparatus and method may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner such as: multiple units or components may be combined, or Can be integrated into another system, or some features can be ignored or not executed.
  • the coupling, or direct coupling, or communication connection of the components shown or discussed may be indirect coupling or communication connection through some interfaces, devices or units, and may be electrical, mechanical or other forms. of.
  • the units described above as separate components may or may not be physically separated, and the components displayed as the unit may or may not be physical units, that is, may be located in one place or distributed to multiple network units; Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may be separately used as one unit, or two or more units may be integrated into one unit;
  • the unit can be implemented in the form of hardware or in the form of hardware plus software functional units.
  • the foregoing may be completed by a program instruction related hardware, where the foregoing program may be stored in a computer readable storage medium, and when executed, the program includes the steps of the foregoing method embodiment; and the foregoing storage medium includes: mobile storage A device that can store program code, such as a device, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.
  • ROM read-only memory
  • RAM random access memory
  • magnetic disk or an optical disk.
  • the above-described integrated unit of the present invention may be stored in a computer readable storage medium if it is implemented in the form of a software function module and sold or used as a standalone product.
  • the technical solution of the embodiments of the present invention may be embodied in the form of a software product in essence or in the form of a software product stored in a storage medium, including a plurality of instructions.
  • a computer device (which may be a personal computer, server, or network device, etc.) is caused to perform all or part of the methods described in various embodiments of the present invention.
  • the foregoing storage medium includes various media that can store program codes, such as a mobile storage device, a ROM, a RAM, a magnetic disk, or an optical disk.
  • the technical solution of the embodiment of the present invention enables the SERDES sending end and the SERDES receiving end to determine whether the receiving channel and the sending channel of the SERDES are in a normal state by using the three-way handshake process of the three synchronous frames. Improve the security of data transmission, ensure a stable SERDES path, and enhance the user experience.

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Abstract

本发明实施例公开了一种传输校验方法、节点、系统与计算机存储介质。其中，所述方法包括：SERDES发送端向SERDES接收端发送第一同步帧；所述SERDES接收端接收到所述第一同步帧后，向所述SERDES发送端发送第二同步帧；所述SERDES发送端接收到所述第二同步帧后，向所述SERDES接收端发送第三同步帧，以使所述SERDES发送端和所述SERDES接收端分别确定自身的发送通路和接收通路均处于正常状态。

Description

一种传输校验方法、节点、系统与计算机存储介质 技术领域
本发明涉及数据通信接口技术，具体涉及一种传输校验方法、节点、系统与计算机存储介质。
背景技术
SERDES是串行器(SERializer)/解串器(DESerializer)的简称。它是一种主流的时分多路复用(TDM)、点对点(P2P)的串行通信技术。即在发送端多路低速并行信号被转换成高速串行信号，经过传输媒体(光缆或铜线)，最后在接收端高速串行信号重新转换成低速并行信号。由于SERDES具有高速度高精度、引脚少，功耗低等特性，在现代通信芯片中被普遍采用。在采用SERDES进行板间或者片间数据通信的系统中，常常会遇到SERDES不稳定的问题，导致这一现象的原因，一方面可能是SERDES参考时钟不稳定等内部原因导致，另一方面可能是板上走线不符合要求等外部原因导致。总之SERDES的数据通信是跟SERDES工作所需的外界条件密切相关的，包括时钟、复位、电源电压、磁场、电场等外界条件都有可能影响SERDES的稳定，而且这种影响不是完全可预知的。
如何保证SERDES通路的稳定，提供可靠的数据传输，相关技术中，对于该问题，尚无有效解决方案。
发明内容
为解决现有存在的技术问题，本发明实施例提供一种传输校验方法、节点、系统与计算机存储介质，能够提升SERDES通路的稳定性和可靠性。
为达到上述目的，本发明实施例的技术方案是这样实现的：
本发明实施例提供了一种传输校验方法，所述方法包括：
SERDES发送端向SERDES接收端发送第一同步帧，接收到所述SERDES接收端发送的第二同步帧后，所述SERDES发送端确定自身的发送通路和接收通路均处于正常状态；
所述SERDES发送端向所述SERDES接收端发送第三同步帧。
作为一种实施方式，所述第一同步帧、所述第二同步帧和所述第三同步帧的帧头中均设置有第一标识位和第二标识位；所述第一标识位置于预设数值时表征本端接收通道处于正常状态；所述第二标识位置于预设数值时表征对端接收通道处于正常状态。
本发明实施例还提供了一种传输校验方法，所述方法包括：
SERDES接收端接收到SERDES发送端发送的第一同步帧后，向所述SERDES发送端发送第二同步帧；
所述SERDES接收端接收到所述SERDES发送端发送的第三同步帧后，所述SERDES接收端确定自身的发送通路和接收通路处于正常状态。
作为一种实施方式，所述第一同步帧、所述第二同步帧和所述第三同步帧的帧头中均设置有第一标识位和第二标识位；所述第一标识位置于预设数值时表征本端接收通道处于正常状态；所述第二标识位置于预设数值时表征对端接收通道处于正常状态。
本发明实施例还提供了一种传输校验方法，所述方法包括：
SERDES发送端向SERDES接收端发送第一同步帧；
所述SERDES接收端接收到所述第一同步帧后，向所述SERDES发送端发送第二同步帧；
所述SERDES发送端接收到所述第二同步帧后，所述SERDES发送端确定自身的发送通路和接收通路均处于正常状态，并向所述SERDES接收端发送第三同步帧，
所述SERDES接收端接收到所述第三同步帧后，所述SERDES接收端确定自身的发送通路和接收通路均处于正常状态。
作为一种实施方式，所述第一同步帧、所述第二同步帧和所述第三同步帧的帧头中均设置有第一标识位和第二标识位；所述第一标识位置于预设数值时表征本端接收通道处于正常状态；所述第二标识位置于预设数值时表征对端接收通道处于正常状态。
作为一种实施方式，所述SERDES发送端向SERDES接收端发送第一同步帧，包括：所述SERDES发送端间隔发送多个第一同步帧和K码；
相应的，所述SERDES接收端基于是否解码出K码判定接收通道是否处于正常状态。
本发明实施例还提供了一种SERDES发送端，所述SERDES发送端包括：第一发送单元和第一接收单元；其中，
所述第一发送单元，配置为向SERDES接收端发送第一同步帧；还配置为所述第一接收到单元接收到所述第二同步帧后，向所述SERDES接收端发送第三同步帧；
所述第一接收单元，配置为接收所述SERDES接收端发送的第二同步帧。
作为一种实施方式，所述第一同步帧、所述第二同步帧和所述第三同步帧的帧头中均设置有第一标识位和第二标识位；所述第一标识位置于预设数值时表征本端接收通道处于正常状态；所述第二标识位置于预设数值时表征对端接收通道处于正常状态。
本发明实施例还提供了一种SERDES接收端，所述SERDES接收端包括：第二发送单元和第二接收单元；其中，
所述第二接收单元，配置为接收到SERDES发送端发送的第一同步帧；还配置为接收到所述SERDES发送端发送的第三同步帧；
所述第二发送单元，配置为所述第二接收单元接收到所述第一同步帧后，向所述SERDES发送端发送第二同步帧。
作为一种实施方式，所述第一同步帧、所述第二同步帧和所述第三同步帧的帧头中均设置有第一标识位和第二标识位；所述第一标识位置于预设数值时表征本端接收通道处于正常状态；所述第二标识位置于预设数值时表征对端接收通道处于正常状态。
本发明实施例还提供了一种传输校验系统，所述系统包括：SERDES发送端和SERDES接收端；其中，
所述SERDES发送端，配置为向SERDES接收端发送第一同步帧；还配置为接收到所述SERDES接收端所述第二同步帧后，确定自身的发送通路和接收通路均处于正常状态；向所述SERDES接收端发送第三同步帧；
所述SERDES接收端，配置为接收到所述SERDES发送端发送的所述第一同步帧后，向所述SERDES发送端发送第二同步帧；还配置为接收到所述SERDES发送端发送的所述第三同步帧后，确定自身的发送通路和接收通路均处于正常状态。
作为一种实施方式，所述第一同步帧、所述第二同步帧和所述第三同步帧的帧头中均设置有第一标识位和第二标识位；所述第一标识位置于预设数值时表征本端接收通道处于正常状态；所述第二标识位置于预设数值时表征对端接收通道处于正常状态。
作为一种实施方式，所述SERDES发送端，配置为间隔发送多个第一同步帧和K码；
所述SERDES接收端，配置为基于是否解码出K码判定接收通道是否处于正常状态。
本发明实施例还提供了一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，所述计算机可执行指令用于执行本发明实施例 所述的应用于SERDES发送端的传输校验方法。
本发明实施例还提供了一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，所述计算机可执行指令用于执行本发明实施例所述的应用于SERDES接收端的传输校验方法。
本发明实施例提供的传输校验方法、节点、系统与计算机存储介质，通过SERDES发送端向SERDES接收端发送第一同步帧；所述SERDES接收端接收到所述第一同步帧后，向所述SERDES发送端发送第二同步帧；所述SERDES发送端接收到所述第二同步帧后，所述SERDES发送端确定自身的发送通路和接收通路均处于正常状态，并向所述SERDES接收端发送第三同步帧，所述SERDES接收端接收到所述第三同步帧后，所述SERDES接收端确定自身的发送通路和接收通路均处于正常状态。如此，采用本发明实施例的技术方案，通过SERDES两端互发三种同步帧的三次握手过程，使所述SERDES发送端和所述SERDES接收端均可确定自身的接收通道和发送通道是否处于正常状态，大大提升了数据传输的安全性，保证稳定的SERDES通路，提升用户的体验。
附图说明
图1为本发明实施例一的传输校验方法的流程示意图；
图2为本发明实施例一的传输校验方法的交互示意图；
图3为本发明实施例二中的帧结构的示意图；
图4为本发明实施例中的传输校验方法基于状态的交互示意图；
图5为本发明实施例的传输校验方法的应用示意图；
图6为本发明实施例的传输校验系统的组成结构示意图；
图7为本发明实施例的SERDES发送端的组成结构示意图；
图8为本发明实施例的SERDES接收端的组成结构示意图。
具体实施方式
下面结合附图及具体实施例对本发明作进一步详细的说明。
在本发明各种实施例中，为了保证SERDES通路的稳定，发明人在实际应用中发现，如果从SERDES的同步状态等信号来判断SERDES的工作状态，是极不可靠的。因为SERDES的同步需要一段时间稳定下来，所以有时会发现SERDES的同步状态拉高之后又会拉低，但是最终，同步状态应该是为高的。还有另外一种情况，SERDES通路的一端的状态是正常的，但是另一端的状态却还没有稳定，有时候甚至会出现某一端的SERDES错误状态不断报错的情况。以上场景说明了，一方面，SERDES的同步状态正常，不代表SERDES已经稳定了，这个同步状态一段时间内还可能反复；另一方面，SERDES通路一端的状态正常或者稳定，不代表另一端也正常或者稳定。综上所述，如果简单的根据SERDES同步状态等信号作为可以发送数据的依据，那么有可能SERDES通路依旧处于不稳定状态，即接收端接收不到正确的数据。
另一方面，由于SERDES的数据传输没有规定的握手信号，不能通过即时反馈了解数据传输的情况。比如在SERDES的发送端，当SERDES发出的数据到达SERDES的接收端，接收端无法马上通知SERDES发送端数据已经收到，SERDES接收端只能通过发一个响应数据的方式，用SERDES通路发送给SERDES发送端，使数据SERDES发送端获知SERDES接收端已经接收到数据。SERDES发送端通过收到响应数据这一现象，还可以推断，相对于SERDES发送端本身，SERDES通路的发送通道和接收通道都可以正常的收发数据。那么SERDES接收端怎么才能获知SERDES通路是正常的呢？它目前只是能接收到数据包，但是不清楚自身发出的数据包SERDES接收端能不能接收到。只要SERDES发送端，在接收到SERDES接收端返回的响应数据后，再向SERDES接收端发送一个“响应的响应消 息”，SERDES接收端接收到这个“响应的响应消息”，就知道，相对于SERDES接收端本身，SERDES通路发送通道和接收通道也是正常的。通过这样的互发响应数据包的握手过程，SERDES通路的两端都可以确认SERDES通路是否处于正常状态。
基于此，提出本发明以下实施例。
实施例一
本发明实施例提供了一种传输校验方法。图1为本发明实施例一的传输校验方法的流程示意图；如图1所示，所述方法包括：
步骤101：SERDES发送端向SERDES接收端发送第一同步帧。
步骤102：所述SERDES接收端接收到所述第一同步帧后，向所述SERDES发送端发送第二同步帧。
步骤103：所述SERDES发送端接收到所述第二同步帧后，向所述SERDES接收端发送第三同步帧，以使所述SERDES发送端和所述SERDES接收端分别确定自身的发送通路和接收通路均处于正常状态。
本实施例中，所述SERDES发送端和所述SERDES接收端分别为SERDES通路的两端。其中，SERDES包括串行器(SERializer)和解串器(DESerializer)，所述串行器可以称为本实施例中所述的SERDES发送端(TX)，所述解串器可以称为本实施例中所述的SERDES接收端(RX)，以实现在发送端多路低速并行信号被转换成高速串行信号，经过传输媒体(光缆或铜线)传输，在接收端高速串行信号重新转换成低速并行信号。
图2为本发明实施例一的传输校验方法的交互示意图；所述SERDES发送端和所述SERDES接收端之间的交互具体可如图2所示。本实施例中的SERDES的传输校验方法包括：
步骤201：当所述SERDES发送端检测到当前处于正常状态时，发出第一同步帧，本实施例中所述第一同步帧记为patern0。
步骤202：当所述SERDES接收端接收到patern0后，所述SERDES接收端一方面可确定自身的接收通道处于正常状态，另一方面也可获知所述SERDES发送端的发送通道处于正常状态。进一步地，所述SERDES接收端向所述SERDES发送端发送第二同步帧，本实施例中所述第二同步帧记为patern1。
步骤203：所述SERDES发送端接收到patern1后，所述SERDES发送端一方面可确定自身的发送通道和接收通道均处于正常状态，另一方面也可确定所述SERDES接收端的发送通道处于正常状态。进一步地，所述SERDES发送端向所述SERDES接收端发送第三同步帧，本实施例中所述第三同步帧记为patern2。所述SERDES接收端接收到patern2后，所述SERDES可确定自身的接收通道和发送通道均处于正常状态。
基于此，本发明实施例通过发送第一同步帧、接收第二同步帧和发送第三同步帧的三次握手过程，使所述SERDES发送端和所述SERDES接收端均可确定自身的接收通道和发送通道是否处于正常状态，大大提升了数据传输的安全性。
采用本发明实施例的技术方案，通过SERDES两端互发三种同步帧的三次握手过程，使所述SERDES发送端和所述SERDES接收端均可确定自身的接收通道和发送通道是否处于正常状态，大大提升了数据传输的安全性，保证稳定的SERDES通路，提升用户的体验。
实施例二
基于实施例一提供的传输校验方法，在本实施例中，所述第一同步帧、所述第二同步帧和所述第三同步帧的帧头中均设置有第一标识位和第二标识位；所述第一标识位置于预设数值时表征本端接收通道处于正常状态；所述第二标识位置于预设数值时表征对端接收通道处于正常状态。
本实施例中，所述第一同步帧、所述第二同步帧和所述第三同步帧均 可称为同步帧。本实施例中，所述SERDES发送端和所述SERDES接收端之间传输同步帧之外，还传输数据帧；所述同步帧和所述数据帧在本实施例中可称为私有帧。图3为本发明实施例二中的帧结构的示意图；如图3所示，所述私有帧的帧结构包括：帧头(FH，Frame Header)、控制信息(FC，Frame Control)、净荷(FP，Frame Payload)和循环冗余校验码(CRC，Cyclic Redundancy Check)。假设SERDES接口的位宽为16比特(bit)，净荷(FP)的大小优选为数据帧长度可以整除所述位宽大小，并且满足系统对速率的要求；在一种实施方式中，净荷(FP)大小可以为32字节。表1为私有帧的具体映射关系示意表，如表1所示，当所述私有帧为同步帧时，帧头的比特位15置为0，表征当前帧为同步帧，并且当所述私有帧为同步帧时，帧结构中不包括净荷(FP)域。当所述私有帧为数据帧时，帧头的比特位15置为1，表征当前帧为数据帧；所述数据帧的净荷(FP)域用于携带用户数据。在本实施方式中，所述私有帧的帧结构中CRC部分为可选部分(option)，用于告警。无论是同步帧或是数据帧，帧结构中，帧头的比特位8和比特位7携带有表征是否同步的标记，在本实施方式中，比特位8用于指示本端SERDES接收通道已经字符同步；比特位7用于指示对端SERDES接收通道已经字符同步，以便使SERDES发送端和SERDES接收端均可以以此判定自身的接收通道和发送通道是否处于正常状态，使SERDES传输更加稳定可靠。
Figure PCTCN2016084314-appb-000001
Figure PCTCN2016084314-appb-000002
表1
作为一种实施方式，本发明实施例中，在通过SERDES通路传输用户数据过程中，即传输数据帧时，采用如表1所示的帧结构对用户数据进行封装，即在数据帧中设置表征本端和对端是否同步的标记，以便在用户数据传输过程中确定当前SERDES发送端或SERDES接收端是否已经同步，从而保证数据传输的稳定性和可靠性。
作为本实施例的另一种实施方式，所述SERDES发送端向SERDES接收端发送第一同步帧，包括：所述SERDES发送端间隔发送多个第一同步帧和K码；
相应的，所述SERDES接收端基于是否解码出K码判定接收通道是否处于正常状态。
具体的，所述SERDES发送端可间隔的发送多个同步帧(本实施例中 为第一同步帧，在其他实施方式中也可以为第二同步帧或第三同步帧)和K码，例如发送同步帧、K码、同步帧、K码等方式间隔发送；其中，SERDES接收端在解码时，通过是否解码获得K码用来判断在传输过程中(即串并转换过程中)，字符边界是否正确；当解码获得K码时，则确定在传输过程中的字符边界正确；当解码未获得K码时，则确定在传输过程中的字符边界不正确，需要向后移动一个帧位，等到响应时间后再继续判断是否解码获得K码，直至成功获得K码为止。
基于实施例一和实施例二提供的传输校验方法，图4为本发明实施例中的传输校验方法基于状态的交互示意图；如图4所示，在本实施例中，预先设置四个状态：空闲(IDLE)态、TXP0状态、TXP1状态和等待(WAIT)状态；其中，
IDLE态：上电复位后，SERDES完成状态同步后的初始状态。在IDLE状态，如果SERDES通路的一端没有收到patern0同步帧，则状态切换到partern0同步帧的发送状态TXP0状态；如果在IDLE状态接收到了patern0同步帧，则状态切换至patern1同步帧的发送状态TXP1状态；
TXP0状态：这是patern0同步帧的发送状态，发出patern0同步帧，等待对端返回的patern1同步帧；当接收到patern1同步帧时，则表明当前收发通路正常，切换至等待状态(WAIT)。在一种实施方式中，在TXP0状态，需要不断的发出patern0同步帧，直到接收到足够数量的patern1同步帧为止。如果等待预设时间都没有patern1同步帧返回，则判定超时，状态跳转回IDLE状态，同时产生中断上报。
TXP1状态：这是patern1同步帧的发送状态。由于已经接收到了patern0同步帧，需要返回patern1同步帧给对端确认。在一种实施方式中，通过返回一定数量的patern1同步帧，表明自己已经收到了初始的patern0同步帧，并且等待对端返回确认传输的patern2同步帧。TXP1状态下，TX端不断的 发送patern2同步帧，同时RX端接收到一定数量的patern2同步帧，表明整个握手过程完成，状态切换至等待状态(WAIT)。但是，如果在TXP1状态等待预设时间都没有patern2同步帧返回，则判定超时，状态切换至IDLE状态，同时产生中断上报。
WAIT状态：所述状态是为了防止SERDES的两端退出握手检测机制的时间不一致，导致检测同步帧泄露到用户接口，而增加的一个延时等待的状态。在WAIT状态下，首先RX端检测收到的patern2同步帧，再连续预设时间(MAX_RX_DELAY)内都不再收到patern2包时，表明握手过程结束，RX端从自动检测机制切换到正常的输出通道，从SERDES收到的数据帧直接被输出给用户接口。当WAIT状态下，patern2同步帧停止的时间超过更长的一段时间(MAX_DELAY)，以确保SERDES两端都已经完成整个握手过程时，TX端从自动检测机制切换到正常的用户通道，至此，SERDES的发送和接收通道都可以通过用户层的收发接口来收发数据帧。
基于上述四种状态的描述，则在本实施方式中，所述SERDES的传输校验方法包括：
步骤301：上电复位后，SERDES通路的一端在完成状态同步后，处于IDLE态，在IDLE态下，在第一预设时间内没有接收到patern0同步帧时，切换至TXP0状态，发出patern0同步帧，此时，SERDES通路的一端作为发送(TX)端。
步骤302：SERDES通路的另一端在IDLE态下，在所述预设时间内接收到patern0同步帧后，切换至patern1同步帧的发送状态TXP1状态，此时，所述SERDES通路的另一端作为接收(RX)端，并且发送patern1同步帧至TX端。
步骤303：所述TX端在TXP0状态下，等待RX端返回的patern1同步帧，当接收到patern1同步帧时，表明所述TX端的收发通路正常，切换至 等待状态(WAIT)，并向RX端发送patern2同步帧。
步骤304：RX端在TXP1状态下，等待TX端返回确认传输的patern2同步帧，当接收到patern2同步帧后，表明所述RX端的收发通路正常，切换至等待状态(WAIT)，握手过程结束。
下面结合具体的应用对本发明实施例的SERDES的传输校验方法进行详细说明。
图5为本发明实施例的传输校验方法的应用示意图；如图5所示，包括节点A和节点B；A_rx和A_tx分别代表A节点的接收端和发送端，B_rx和B_tx分别代表B节点的接收端和发送端和发送端；S代表同步帧，K代表K码，D代表数据帧。如图5所示，包括三个过程：
步骤1：A节点复位完成后，A_tx间隔发送同步帧和K码；K码是为了接收端采用8B/10B解码方式能够解码出K码，来判断SERDES在串并转换时的字符边界是否正确；当接收端接收到K码则表示字符边界正确；当接收端接收不到K码，则配置A_rx通道字符边界顺序向后移动1个帧位(UI)，等待SERDES响应时间后再继续判断，直到成功接收到K码为止。其中，间隔发送的同步帧和K码中，K码的发送个数大于N值(N可预先配置，比如可配置为20)；当接收端接收到N-1个K码，则表示SERDES已经字符同步。字符同步确保了接收数据的正确性。本过程如图5中①所示；然后跳转至Step2。
步骤2：A_tx继续间隔发送同步帧和K码，A_rx连续检测到3次同步帧，则通知A_tx在同步帧头的帧头比特位8置为1，表示A_rx已经至少收到3次同步帧，如图5中②所示。当A_rx接收到的同步帧的帧头比特位8为1时，表示B_rx已经至少收到三次同步帧，则通知A_tx再至少发送一次同步帧，其帧头比特位7置为1，当A_rx接收到帧头比特位7为1的同步帧时，表示A节点获知通信双方A_rx和B_rx都已经同步，即节点同步。 使得收发双方都均获知对方可以正确的接收和发送数据，增加了数据传输的安全性。如图5中节点③所示。跳转至Step3。
步骤3：A_tx开始发送数据帧。所述数据帧携带有用户数据的时序信息，为了保证收发完整的数据包，要求从用户数据的帧头开始发送。此时为了提高信道利用率，中间间隔的K码可以为1～3个长度。同时基于所述数据帧中携带的表征本端和对端是否同步的标记实时检测SERDES是否失步。由于每隔一个数据帧就会有K码发送，因此可连续检测数据帧加上K码的长度；如果接收端未解码出K码，则认为SERDES失步，上报告警。即失步检测，可以及时的发现数据是否安全到达对端节点。同时跳转至Step1。
在本示意中，A节点和B节点属于对称节点，因此两者的操作完全相同。因此基于B节点的SERDES的传输校验方法不再赘述。其中，CRC检查作为可靠性设计的一部分，为可选项，可以协助检查SERDES的误码情况。使用计数器累加所发送的帧数以及错误的帧数。
采用本发明实施例的技术方案，一方面通过SERDES两端互发三种同步帧的三次握手过程，使所述SERDES发送端和所述SERDES接收端均可确定自身的接收通道和发送通道是否处于正常状态，大大提升了数据传输的安全性，保证稳定的SERDES通路，提升用户的体验；另一方面在传输数据帧时，在数据帧中封装了表征本端和对端是否同步的标记，以便在用户数据传输过程中确定当前SERDES发送端或SERDES接收端是否已经同步，从而保证数据传输的稳定性和可靠性；最后，通过在数据帧或同步帧中插入K码，可以及时的发现SERDES通路是否异常，及时发现数据是否安全到达对端，从而提升了数据传输的安全性。
实施例三
本发明实施例还提供了一种传输校验方法，本实施例所述的SERDES 的传输校验方法应用于发送端。所述方法包括：
步骤401：SERDES发送端向SERDES接收端发送第一同步帧，接收到所述SERDES接收端发送的第二同步帧后，所述SERDES发送端确定自身的发送通路和接收通路均处于正常状态。
步骤402：所述SERDES发送端向所述SERDES接收端发送第三同步帧。
其中，所述第一同步帧、所述第二同步帧和所述第三同步帧的帧头中均设置有第一标识位和第二标识位；所述第一标识位置于预设数值时表征本端接收通道处于正常状态；所述第二标识位置于预设数值时表征对端接收通道处于正常状态。
实施例四
本发明实施例还提供了一种传输校验方法，本实施例所述的SERDES的传输校验方法应用于接收端。所述方法包括：
步骤501：SERDES接收端接收到SERDES发送端发送的第一同步帧后，向所述SERDES发送端发送第二同步帧。
步骤502：所述SERDES接收端接收到所述SERDES发送端发送的第三同步帧后，所述SERDES接收端确定自身的发送通路和接收通路处于正常状态。
其中，所述第一同步帧、所述第二同步帧和所述第三同步帧的帧头中均设置有第一标识位和第二标识位；所述第一标识位置于预设数值时表征本端接收通道处于正常状态；所述第二标识位置于预设数值时表征对端接收通道处于正常状态。
本发明实施例三和实施例四所述的SERDES的传输校验方法分别从SERDES发送端的SERDES接收端作为执行主体对本发明实施例的SERDES的传输校验方法进行说明，实施例三和实施例中的具体描述可参 照实施例一和实施例二所述，这里不再赘述。
实施例五
本发明实施例提供了一种传输校验系统。图6为本发明实施例的传输校验系统的组成结构示意图；如图6所示，所述系统包括：SERDES发送端和SERDES接收端；其中，
所述SERDES发送端，配置为向SERDES接收端发送第一同步帧；还配置为接收到所述SERDES接收端所述第二同步帧后，确定自身的发送通路和接收通路均处于正常状态；向所述SERDES接收端发送第三同步帧；
所述SERDES接收端，配置为接收到所述SERDES发送端发送的所述第一同步帧后，向所述SERDES发送端发送第二同步帧；还配置为接收到所述SERDES发送端发送的所述第三同步帧后，确定自身的发送通路和接收通路均处于正常状态。
其中，所述第一同步帧、所述第二同步帧和所述第三同步帧的帧头中均设置有第一标识位和第二标识位；所述第一标识位置于预设数值时表征本端接收通道处于正常状态；所述第二标识位置于预设数值时表征对端接收通道处于正常状态。
具体的，所述第一同步帧、所述第二同步帧和所述第三同步帧均可称为同步帧。本实施例中，所述SERDES发送端和所述SERDES接收端之间传输同步帧之外，还传输数据帧；所述同步帧和所述数据帧在本实施例中可称为私有帧。如图3所示，所述私有帧的帧结构包括：帧头(FH)、控制信息(FC)、净荷(FP)和循环冗余校验码(CRC)。假设SERDES接口的位宽为16比特(bit)，净荷(FP)的大小优选为数据帧长度可以整除所述位宽大小，并且满足系统对速率的要求；在一种实施方式中，净荷(FP)大小可以为32。如表1所示，当所述私有帧为同步帧时，帧头的比特位15置为0，表征当前帧为同步帧，并且当所述私有帧为同步帧时，帧结构中不 包括净荷(FP)域。当所述私有帧为数据帧时，帧头的比特位15置为1，表征当前帧为数据帧；所述数据帧的净荷(FP)域用于携带用户数据。在本实施方式中，所述私有帧的帧结构中CRC部分为可选部分，用于告警，且CRC满足以下公式：G(x)＝X16+X15+X2+1。无论是同步帧或是数据帧，帧结构中，帧头的比特位8和比特位7携带有表征是否同步的标记，在本实施方式中，比特位8用于指示本端SERDES接收通道已经字符同步；比特位7用于指示对端SERDES接收通道已经字符同步，以便使SERDES发送端和SERDES接收端均可以以此判定自身的接收通道和发送通道是否处于正常状态，使SERDES传输更加稳定可靠。
作为一种实施方式，本发明实施例中，在通过SERDES通路传输用户数据过程中，即所述SERDES发送端传输数据帧时，采用如表1所示的帧结构对用户数据进行封装，即在数据帧中设置表征本端和对端是否同步的标记，以便在用户数据传输过程中确定当前SERDES发送端或SERDES接收端是否已经同步，从而保证数据传输的稳定性和可靠性。
作为一种实施方式，所述SERDES发送端，配置为间隔发送多个第一同步帧和K码；
所述SERDES接收端，配置为基于是否解码出K码判定接收通道是否处于正常状态。
具体的，所述SERDES发送端可间隔的发送多个同步帧(本实施例中为第一同步帧，在其他实施方式中也可以为第二同步帧或第三同步帧)和K码，例如发送同步帧、K码、同步帧、K码等方式间隔发送；其中，SERDES接收端在解码时，通过是否解码获得K码用来判断在传输过程中(即串并转换过程中)，字符边界是否正确；当解码获得K码时，则确定在传输过程中的字符边界正确；当解码未获得K码时，则确定在传输过程中的字符边界不正确，需要向后移动一个帧位，等到响应时间后再继续判断是否解码 获得K码，直至成功获得K码为止。
本领域技术人员应当理解，本发明实施例的传输校验系统中各节点的功能，可参照前述SERDES的传输校验方法的相关描述而理解，本发明实施例的SERDES的传输校验系统中各节点，可通过实现本发明实施例所述的功能的模拟电路而实现，也可以通过执行本发明实施例所述的功能的软件在智能终端上的运行而实现。
实施例六
本发明实施例还提供了一种SERDES发送端。图7为本发明实施例的SERDES发送端的组成结构示意图；如图7所示，所述SERDES发送端包括：第一发送单元和第一接收单元；其中，
所述第一发送单元，配置为向SERDES接收端发送第一同步帧；还配置为所述第一接收到单元接收到所述第二同步帧后，向所述SERDES接收端发送第三同步帧；
所述第一接收单元，配置为接收所述SERDES接收端发送的第二同步帧。
其中，所述第一同步帧、所述第二同步帧和所述第三同步帧的帧头中均设置有第一标识位和第二标识位；所述第一标识位置于预设数值时表征本端接收通道处于正常状态；所述第二标识位置于预设数值时表征对端接收通道处于正常状态。
具体的，所述第一同步帧、所述第二同步帧和所述第三同步帧均可称为同步帧。本实施例中，所述SERDES发送端和所述SERDES接收端之间传输同步帧之外，还传输数据帧；所述同步帧和所述数据帧在本实施例中可称为私有帧。如图3所示，所述私有帧的帧结构包括：帧头(FH)、控制信息(FC)、净荷(FP)和循环冗余校验码(CRC)。假设SERDES接口的位宽为16比特(bit)，净荷(FP)的大小优选为数据帧长度可以整除所述 位宽大小，并且满足系统对速率的要求；在一种实施方式中，净荷(FP)大小可以为32。如表1所示，当所述私有帧为同步帧时，帧头的比特位15置为0，表征当前帧为同步帧，并且当所述私有帧为同步帧时，帧结构中不包括净荷(FP)域。当所述私有帧为数据帧时，帧头的比特位15置为1，表征当前帧为数据帧；所述数据帧的净荷(FP)域用于携带用户数据。在本实施方式中，所述私有帧的帧结构中CRC部分为可选部分，用于告警，且CRC满足以下公式：G(x)＝X16+X15+X2+1。无论是同步帧或是数据帧，帧结构中，帧头的比特位8和比特位7携带有表征是否同步的标记，在本实施方式中，比特位8用于指示本端SERDES接收通道已经字符同步；比特位7用于指示对端SERDES接收通道已经字符同步，以便使SERDES发送端和SERDES接收端均可以以此判定自身的接收通道和发送通道是否处于正常状态，使SERDES传输更加稳定可靠。
作为一种实施方式，所述第一发送单元，还配置为发送数据帧时，采用如表1所示的帧结构对用户数据进行封装，即在数据帧中设置表征本端和对端是否同步的标记，以便在用户数据传输过程中确定当前SERDES发送端或SERDES接收端是否已经同步，从而保证数据传输的稳定性和可靠性。
作为一种实施方式，所述第一发送单元，还配置为间隔发送多个第一同步帧和K码至接收端，以便于接收端解码时，通过是否解码获得K码用来判断在传输过程中(即串并转换过程中)，字符边界是否正确。
具体的，所述第一发送单元可间隔的发送多个同步帧(本实施例中为第一同步帧，在其他实施方式中也可以为第二同步帧或第三同步帧)和K码，例如发送同步帧、K码、同步帧、K码等方式间隔发送；其中，SERDES接收端在解码时，通过是否解码获得K码用来判断在传输过程中(即串并转换过程中)，字符边界是否正确；当解码获得K码时，则确定在传输过程 中的字符边界正确；当解码未获得K码时，则确定在传输过程中的字符边界不正确，需要向后移动一个帧位，等到响应时间后再继续判断是否解码获得K码，直至成功获得K码为止。
本领域技术人员应当理解，本发明实施例的SERDES发送端中各处理模块的功能，可参照前述SERDES的传输校验方法的相关描述而理解，本发明实施例的SERDES发送端中各处理模块，可通过实现本发明实施例所述的功能的模拟电路而实现，也可以通过执行本发明实施例所述的功能的软件在智能终端上的运行而实现。
实施例七
本发明实施例还提供了一种SERDES接收端。图8为本发明实施例的SERDES接收端的组成结构示意图，如图8所示，所述SERDES接收端包括：第二发送单元和第二接收单元；其中，
所述第二接收单元，配置为接收到SERDES发送端发送的第一同步帧；还配置为接收到所述SERDES发送端发送的第三同步帧；
所述第二发送单元，配置为所述第二接收单元接收到所述第一同步帧后，向所述SERDES发送端发送第二同步帧。
其中，所述第一同步帧、所述第二同步帧和所述第三同步帧的帧头中均设置有第一标识位和第二标识位；所述第一标识位置于预设数值时表征本端接收通道处于正常状态；所述第二标识位置于预设数值时表征对端接收通道处于正常状态。
具体的，所述第一同步帧、所述第二同步帧和所述第三同步帧均可称为同步帧。本实施例中，所述SERDES发送端和所述SERDES接收端之间传输同步帧之外，还传输数据帧；所述同步帧和所述数据帧在本实施例中可称为私有帧。如图3所示，所述私有帧的帧结构包括：帧头(FH)、控制信息(FC)、净荷(FP)和循环冗余校验码(CRC)。假设SERDES接口的 位宽为16比特(bit)，净荷(FP)的大小优选为数据帧长度可以整除所述位宽大小，并且满足系统对速率的要求；在一种实施方式中，净荷(FP)大小可以为32。如表1所示，当所述私有帧为同步帧时，帧头的比特位15置为0，表征当前帧为同步帧，并且当所述私有帧为同步帧时，帧结构中不包括净荷(FP)域。当所述私有帧为数据帧时，帧头的比特位15置为1，表征当前帧为数据帧；所述数据帧的净荷(FP)域用于携带用户数据。在本实施方式中，所述私有帧的帧结构中CRC部分为可选部分，用于告警，且CRC满足以下公式：G(x)＝X16+X15+X2+1。无论是同步帧或是数据帧，帧结构中，帧头的比特位8和比特位7携带有表征是否同步的标记，在本实施方式中，比特位8用于指示本端SERDES接收通道已经字符同步；比特位7用于指示对端SERDES接收通道已经字符同步，以便使SERDES发送端和SERDES接收端均可以以此判定自身的接收通道和发送通道是否处于正常状态，使SERDES传输更加稳定可靠。
作为一种实施方式，所述第二接收单元，还配置为基于是否解码出K码判定接收通道是否处于正常状态。
具体的，所述SERDES发送端可间隔的发送多个同步帧(本实施例中为第一同步帧，在其他实施方式中也可以为第二同步帧或第三同步帧)和K码，例如发送同步帧、K码、同步帧、K码等方式间隔发送；其中，所述第二接收单元在解码时，通过是否解码获得K码用来判断在传输过程中(即串并转换过程中)，字符边界是否正确；当解码获得K码时，则确定在传输过程中的字符边界正确；当解码未获得K码时，则确定在传输过程中的字符边界不正确，需要向后移动一个帧位，等到响应时间后再继续判断是否解码获得K码，直至成功获得K码为止。
本领域技术人员应当理解，本发明实施例的SERDES接收端中各处理模块的功能，可参照前述SERDES的传输校验方法的相关描述而理解，本 发明实施例的SERDES接收端中各处理模块，可通过实现本发明实施例所述的功能的模拟电路而实现，也可以通过执行本发明实施例所述的功能的软件在智能终端上的运行而实现。
本发明实施例六和实施例七中，所述SERDES发送端和所述SERDES接收端在实际应用中，可由采用SERDES接口的节点设备实现，所述SERDES发送端中的第一发送单元和第一接收单元，在实际应用中，可由所述SERDES发送端中的收发天线或收发机实现。所述SERDES接收端中的第二发送单元和第二接收单元，在实际应用中，可由所述SERDES接收端中的收发天线或收发机实现。
在本申请所提供的几个实施例中，应该理解到，所揭露的设备和方法，可以通过其它的方式实现。以上所描述的设备实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，如：多个单元或组件可以结合，或可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示或讨论的各组成部分相互之间的耦合、或直接耦合、或通信连接可以是通过一些接口，设备或单元的间接耦合或通信连接，可以是电性的、机械的或其它形式的。
上述作为分离部件说明的单元可以是、或也可以不是物理上分开的，作为单元显示的部件可以是、或也可以不是物理单元，即可以位于一个地方，也可以分布到多个网络单元上；可以根据实际的需要选择其中的部分或全部单元来实现本实施例方案的目的。
另外，在本发明各实施例中的各功能单元可以全部集成在一个处理单元中，也可以是各单元分别单独作为一个单元，也可以两个或两个以上单元集成在一个单元中；上述集成的单元既可以采用硬件的形式实现，也可以采用硬件加软件功能单元的形式实现。
本领域普通技术人员可以理解：实现上述方法实施例的全部或部分步 骤可以通过程序指令相关的硬件来完成，前述的程序可以存储于一计算机可读取存储介质中，该程序在执行时，执行包括上述方法实施例的步骤；而前述的存储介质包括：移动存储设备、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。
或者，本发明上述集成的单元如果以软件功能模块的形式实现并作为独立的产品销售或使用时，也可以存储在一个计算机可读取存储介质中。基于这样的理解，本发明实施例的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机、服务器、或者网络设备等)执行本发明各个实施例所述方法的全部或部分。而前述的存储介质包括：移动存储设备、ROM、RAM、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。
工业实用性
本发明实施例的技术方案通过SERDES两端互发三种同步帧的三次握手过程，使所述SERDES发送端和所述SERDES接收端均可确定自身的接收通道和发送通道是否处于正常状态，大大提升了数据传输的安全性，保证稳定的SERDES通路，提升用户的体验。

Claims (16)

  1. 一种传输校验方法，所述方法包括：
    SERDES发送端向SERDES接收端发送第一同步帧，接收到所述SERDES接收端发送的第二同步帧后，所述SERDES发送端确定自身的发送通路和接收通路均处于正常状态；
    所述SERDES发送端向所述SERDES接收端发送第三同步帧。
  2. 根据权利要求1所述的方法，其中，所述第一同步帧、所述第二同步帧和所述第三同步帧的帧头中均设置有第一标识位和第二标识位；所述第一标识位置于预设数值时表征本端接收通道处于正常状态；所述第二标识位置于预设数值时表征对端接收通道处于正常状态。
  3. 一种传输校验方法，其中，所述方法包括：
    SERDES接收端接收到SERDES发送端发送的第一同步帧后，向所述SERDES发送端发送第二同步帧；
    所述SERDES接收端接收到所述SERDES发送端发送的第三同步帧后，所述SERDES接收端确定自身的发送通路和接收通路处于正常状态。
  4. 根据权利要求3所述的方法，其中，所述第一同步帧、所述第二同步帧和所述第三同步帧的帧头中均设置有第一标识位和第二标识位；所述第一标识位置于预设数值时表征本端接收通道处于正常状态；所述第二标识位置于预设数值时表征对端接收通道处于正常状态。
  5. 一种传输校验方法，所述方法包括：
    SERDES发送端向SERDES接收端发送第一同步帧；
    所述SERDES接收端接收到所述第一同步帧后，向所述SERDES发送端发送第二同步帧；
    所述SERDES发送端接收到所述第二同步帧后，所述SERDES发送端确定自身的发送通路和接收通路均处于正常状态，并向所述SERDES接收 端发送第三同步帧，
    所述SERDES接收端接收到所述第三同步帧后，所述SERDES接收端确定自身的发送通路和接收通路均处于正常状态。
  6. 根据权利要求5所述的方法，其中，所述第一同步帧、所述第二同步帧和所述第三同步帧的帧头中均设置有第一标识位和第二标识位；所述第一标识位置于预设数值时表征本端接收通道处于正常状态；所述第二标识位置于预设数值时表征对端接收通道处于正常状态。
  7. 根据权利要求5所述的方法，其中，所述SERDES发送端向SERDES接收端发送第一同步帧，包括：所述SERDES发送端间隔发送多个第一同步帧和K码；
    相应的，所述SERDES接收端基于是否解码出K码判定接收通道是否处于正常状态。
  8. 一种SERDES发送端，所述SERDES发送端包括：第一发送单元和第一接收单元；其中，
    所述第一发送单元，配置为向SERDES接收端发送第一同步帧；还配置为所述第一接收到单元接收到所述第二同步帧后，向所述SERDES接收端发送第三同步帧；
    所述第一接收单元，配置为接收所述SERDES接收端发送的第二同步帧。
  9. 根据权利要求8所述的SERDES发送端，其中，所述第一同步帧、所述第二同步帧和所述第三同步帧的帧头中均设置有第一标识位和第二标识位；所述第一标识位置于预设数值时表征本端接收通道处于正常状态；所述第二标识位置于预设数值时表征对端接收通道处于正常状态。
  10. 一种SERDES接收端，所述SERDES接收端包括：第二发送单元和第二接收单元；其中，
    所述第二接收单元，配置为接收到SERDES发送端发送的第一同步帧；还配置为接收到所述SERDES发送端发送的第三同步帧；
    所述第二发送单元，配置为所述第二接收单元接收到所述第一同步帧后，向所述SERDES发送端发送第二同步帧。
  11. 根据权利要求10所述的SERDES接收端，其中，所述第一同步帧、所述第二同步帧和所述第三同步帧的帧头中均设置有第一标识位和第二标识位；所述第一标识位置于预设数值时表征本端接收通道处于正常状态；所述第二标识位置于预设数值时表征对端接收通道处于正常状态。
  12. 一种传输校验系统，所述系统包括：SERDES发送端和SERDES接收端；其中，
    所述SERDES发送端，配置为向SERDES接收端发送第一同步帧；还配置为接收到所述SERDES接收端所述第二同步帧后，确定自身的发送通路和接收通路均处于正常状态；向所述SERDES接收端发送第三同步帧；
    所述SERDES接收端，配置为接收到所述SERDES发送端发送的所述第一同步帧后，向所述SERDES发送端发送第二同步帧；还配置为接收到所述SERDES发送端发送的所述第三同步帧后，确定自身的发送通路和接收通路均处于正常状态。
  13. 根据权利要求12所述的传输校验系统，其中，所述第一同步帧、所述第二同步帧和所述第三同步帧的帧头中均设置有第一标识位和第二标识位；所述第一标识位置于预设数值时表征本端接收通道处于正常状态；所述第二标识位置于预设数值时表征对端接收通道处于正常状态。
  14. 根据权利要求12所述的传输校验系统，其中，所述SERDES发送端，配置为间隔发送多个第一同步帧和K码；
    所述SERDES接收端，配置为基于是否解码出K码判定接收通道是否处于正常状态。
  15. 一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，所述计算机可执行指令用于执行权利要求1或2所述的传输校验方法。
  16. 一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，所述计算机可执行指令用于执行权利要求3或4所述的传输校验方法。
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