WO2017032301A1 - 一种装置及制造方法 - Google Patents

一种装置及制造方法 Download PDF

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Publication number
WO2017032301A1
WO2017032301A1 PCT/CN2016/096373 CN2016096373W WO2017032301A1 WO 2017032301 A1 WO2017032301 A1 WO 2017032301A1 CN 2016096373 W CN2016096373 W CN 2016096373W WO 2017032301 A1 WO2017032301 A1 WO 2017032301A1
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WIPO (PCT)
Prior art keywords
layer
sintered
nano metal
alloy
metal particle
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PCT/CN2016/096373
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English (en)
French (fr)
Inventor
符会利
林志荣
蔡树杰
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Priority to SG11201801027SA priority Critical patent/SG11201801027SA/en
Priority to EP16838559.9A priority patent/EP3327769B1/en
Publication of WO2017032301A1 publication Critical patent/WO2017032301A1/zh
Priority to US15/905,044 priority patent/US10784181B2/en
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/25—Arrangements for cooling characterised by their materials
    • H10W40/257—Arrangements for cooling characterised by their materials having a heterogeneous or anisotropic structure, e.g. powder or fibres in a matrix, wire mesh or porous structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/22—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections
    • H10W40/226—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections characterised by projecting parts, e.g. fins to increase surface area
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/25—Arrangements for cooling characterised by their materials
    • H10W40/255—Arrangements for cooling characterised by their materials having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/25—Arrangements for cooling characterised by their materials
    • H10W40/258—Metallic materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/70—Fillings or auxiliary members in containers or in encapsulations for thermal protection or control
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/02—Manufacture or treatment of conductive package substrates serving as an interconnection, e.g. of metal plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/01—Manufacture or treatment
    • H10W40/03—Manufacture or treatment of arrangements for cooling
    • H10W40/037—Assembling together parts thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07331—Connecting techniques
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/877—Bump connectors and die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

  • the present invention relates to the field of circuits, and in particular, to a circuit device and a method of fabricating the same.
  • the structure includes an integrated circuit chip 1A02, a thermal interface material layer 1A04, and a heat sink 1A06.
  • the heat generated during the operation of the integrated circuit chip 1A02 is poured into the heat sink 1A06 through the thermal interface material layer 1A04 on the back side of the chip. Therefore, the thermal conductivity of the thermal interface material layer 1A04 itself has an important influence on the heat dissipation of the chip.
  • Existing thermal interface material layers include silver gum based materials.
  • the silver-based material is mixed with the metal silver particles 1A08 to improve the heat conduction effect, but mainly the continuous phase formed by the silver-gel material. Silver-based materials have low thermal conductivity and it is difficult to meet the heat dissipation requirements of high-power chips.
  • Embodiments of the present invention provide an apparatus and a manufacturing method.
  • the thermal interface material between the circuit device and the heat sink has a high thermal conductivity, which greatly improves the thermal conductivity of the overall thermal path, and can better meet the heat dissipation requirements of the high power circuit device.
  • an embodiment of the present invention provides an apparatus, including: a circuit device; a heat sink; and a thermal interface material layer thermally coupled to the circuit device and the heat sink, including: a first alloy layer, and a a circuit device thermally coupled; a layer of nano metal particles thermally coupled to the first alloy layer, the nano metal particle layer comprising a plurality of nano metal particles and an intermediate mixture coupled to each other, the intermediate mixture being filled in the plurality Between the nano metal particles; and a second alloy layer, thermally coupled to the nano metal particle layer and the heat sink.
  • the first alloy layer and the nano gold a contact of the particle layer forms a sintered continuous phase structure, a contact between the plurality of nano metal particles forms a sintered continuous phase structure, and a contact between the second alloy layer and the nano metal particle layer forms a continuous sintering Phase structure.
  • the nano metal particles comprise silver.
  • the nano metal particles have a diameter between 50 and 200 nanometers.
  • a flip chip ball grid array structure In combination with the first aspect, or any of the first to third possible implementations of the first aspect, in a fourth possible implementation, for a flip chip ball grid array structure.
  • the first alloy layer comprises a first adhesive layer and a first co-sintered layer
  • the first bonding layer is thermally coupled to the circuit device
  • the first co-sintered layer is coupled to the nano metal particle layer
  • the contact between the first co-sintered layer and the nano metal particle layer forms a continuous sintering Phase structure.
  • the first adhesive layer comprises any one of the following materials: titanium, chromium, nickel or nickel vanadium alloy, the first A common sintered layer includes any of the following materials: silver, gold or copper.
  • the first alloy layer further includes a first buffer a layer between the first subsequent layer and the first co-sintered layer, the first buffer layer comprising any one of the following materials: aluminum, copper, nickel or nickel vanadium alloy.
  • the second alloy layer comprises a second adhesive layer and a second co-sintered layer
  • the second adhesive layer is thermally coupled to the heat sink
  • the second co-sintered layer is thermally coupled to the nano metal particle layer
  • the second co-sintered layer is in contact with the nano metal particle layer A sintered continuous phase structure is formed.
  • the second adhesive layer comprises any one of the following materials: titanium, chromium, nickel or nickel vanadium alloy, the first The co-sintered layer includes any of the following materials: silver, gold or copper.
  • the second alloy layer further includes a second buffer a layer between the second adhesive layer and the second co-sintered layer, the second buffer layer comprising any one of the following materials: aluminum, copper, nickel or nickel vanadium alloy.
  • the nano metal particles have a diameter of no more than 1 micrometer.
  • the intermediate mixture comprises any one of the following materials: air or Resin.
  • the circuit device comprises an integrated circuit die, the integrated circuit tube A substrate in the core is thermally coupled to the layer of thermal interface material.
  • an embodiment of the present invention provides a method of fabricating a device, comprising: generating a first alloy layer; forming a nano metal particle layer from a plurality of nano metal particles and an intermediate mixture coupled to each other, and filling the intermediate mixture with Between the plurality of nano metal particles; and a second alloy layer, wherein the first alloy layer is thermally coupled to the circuit device, the nano metal particle layer is thermally coupled to the first alloy layer, and The second alloy layer is thermally coupled to the nano metal particle layer and the heat sink.
  • the contact between the first alloy layer and the nano metal particle layer forms a sintered continuous phase structure, and the contact between the nano metal particles is sintered. a continuous phase structure, and a contact of the second alloy layer with the nano metal particle layer forms a sintered continuous phase structure.
  • the nano metal particles have a diameter of no more than 1 micrometer.
  • the intermediate mixture comprises any one of the following materials: air or resin.
  • the generating the first alloy layer includes: generating a first adhesive layer and the first Co-sintering the layer and thermally coupling the first bonding layer to the circuit device to cause the first total A sintered layer is coupled to the nano metal particle layer, and a contact of the first co-sinter layer and the nano metal particle layer forms a sintered continuous phase structure.
  • the generating the second alloy layer comprises: generating a second adhesive layer and a second Co-sintering the layer and thermally coupling the second adhesive layer to the heat sink to thermally couple the second co-sintered layer to the nano-metal particle layer, and to cause the second co-sintered layer to The contact of the nano metal particle layer forms a sintered continuous phase structure.
  • 1A is a cross-sectional view showing a package structure including a device in the prior art.
  • FIG. 1 is a cross-sectional view showing a package structure including a device according to a first embodiment of the present invention.
  • FIG. 2 includes an example cross-sectional view of a first embodiment of the thermal interface material layer of FIG. 1.
  • FIG. 3 is a cross-sectional view showing a first embodiment of the first alloy layer of FIG. 2.
  • FIG. 4 is a cross-sectional view showing a second embodiment of the first alloy layer of FIG. 2.
  • Fig. 5 is a cross-sectional view showing the first embodiment of the second alloy layer of Fig. 2.
  • Figure 6 is a cross-sectional view showing a second embodiment of the second alloy layer of Figure 2.
  • Figure 7 is a flow chart of a method of fabricating a device in accordance with a second embodiment of the present invention.
  • the flip chip ball grid array package structure includes a solder ball 108, a substrate 107, an adhesive 106, a metal bump (BUMP) 102, a circuit device (such as an integrated circuit die) 103, a thermal interface material layer 104, and a heat sink 105.
  • Integrated circuit die 103 is coupled to substrate 107 by metal bumps 102.
  • Metal bumps 102 are protected by underfill 101.
  • the heat sink 105 is fixed to the substrate 107 by an adhesive 106.
  • Thermal interface material layer 104 is thermally coupled to integrated circuit die 103 and heat sink 105.
  • thermal coupling includes different levels, different structures, or situations of heat transfer between different devices.
  • the thermal interface material layer 104 can be between the integrated circuit die 103 and the heat sink 105.
  • the substrate in integrated circuit die 103 is thermally coupled to thermal interface material layer 104. Heat from the integrated circuit die 103 reaches the heat sink 105 through the thermal interface material layer 104.
  • the integrated circuit die 103, the thermal interface material layer 104, and the heat sink 105 can be used as part or all of the components of the device, and the device can be used for, but not limited to, a flip chip ball grid array package structure as shown. .
  • the thermal interface material layer 104 is thermally coupled to the die 103 and the heat sink 105, and includes a first alloy layer 109, a nano metal particle layer 110, and a second alloy layer 112.
  • the first alloy layer 109 is thermally coupled to the integrated circuit die 103 and the nano metal particle layer 110. More specifically, as shown, the first alloy layer 109 can be over the integrated circuit die 103 below the nano metal particle layer 110. That is, the first alloy layer 109 can be between the integrated circuit die 103 and the nano metal particle layer 110. The first alloy layer 109 increases the bond strength between the integrated circuit die 103 and the nano metal particle layer 110.
  • the nano metal particle layer 110 includes nano metal particles and an intermediate mixture.
  • the intermediate mixture includes, but is not limited to, any of the following materials: air or resin.
  • the intermediate mixture is used to fill between the plurality of nano metal particles to form a plurality of nano metal particles.
  • Nano metal particles include, but are not limited to, silver.
  • the nano metal particles have a diameter of no more than 1 micron. In one embodiment, the nano metal particles have a diameter between 50 and 200 nanometers.
  • the nano metal particle layer 110 has a lower thermal resistance and forms a better heat conduction path.
  • the second alloy layer 112 is thermally coupled to the nano metal particle layer 110 and the heat sink 105. More specifically, as shown, the second alloy layer 112 can be positioned over the nano metal particle layer 110 below the heat sink 105. That is, the second alloy layer 112 may be located between the nano metal particle layer 110 and the heat sink 105. The second alloy layer 112 increases the adhesion between the nano metal particle layer 110 and the heat sink 105 strength.
  • the first alloy layer 109 forms a sintered continuous phase structure at the contact with the nano metal particle layer 110, the contact between the nano metal particles forms a sintered continuous phase structure, and the second alloy layer 112 and the nano metal particles
  • the contact of layer 110 forms a sintered continuous phase structure.
  • the sintered continuous phase structure herein includes, but is not limited to, due to the sintering behavior of the metal particles, the metal atoms in the vicinity of the metal particle interface diffuse to the metal particle interface to fuse together, so that the metal particles form a unitary structure.
  • the first alloy layer 109 includes a first adhesive layer 114 and a first co-sintered layer 115.
  • the co-sintered layer herein includes, but is not limited to, a metal layer that is interfused with the layer of thermal interface material produced during the encapsulation process, the metal layer co-sintering with the particles in the layer of thermal interface material to form a heat flow path.
  • the first subsequent layer 114 is thermally coupled to the integrated circuit die 103.
  • the first co-sintered layer 115 is thermally coupled to the nano-metal particle layer 110.
  • the contact of the first co-sintered layer 115 with the nano-metal particle layer 110 forms a sintered continuous phase structure.
  • the first via layer 114 can be over the integrated circuit die 103, and the first co-sintered layer 115 can be over the first via layer 114, under the nano-metal particle layer 110.
  • the first adhesive layer 114 includes, but is not limited to, any of the following materials: titanium, chromium, nickel, or nickel/vanadium.
  • the first subsequent layer 114 increases the bond strength between the integrated circuit die 103 and the first co-sintered layer 115.
  • the first co-sintered layer 115 includes, but is not limited to, any of the following materials: silver, gold, or copper.
  • the first alloy layer 109 of FIG. 4 further includes a first buffer layer 116 between the first subsequent layer 114 and the first co-sintered layer 115.
  • the first buffer layer 116 includes, but is not limited to, any of the following materials: aluminum, copper, or nickel.
  • the first buffer layer 116 provides a stress buffering function in the deformation due to the heat treatment, reducing the risk of cracks between the integrated circuit die 103 and the thermal interface material layer 114 or between the thermal interface material layers 114, increasing the reliability of the device.
  • FIG. 5 is a cross-sectional view showing a first embodiment of the second alloy layer 112 of FIG. 2.
  • the second alloy layer 112 includes a second co-sintered layer 118 and a second subsequent layer 117.
  • the second co-sintered layer 118 is thermally coupled to the nano-metal particle layer 110.
  • the contact of the second co-sintered layer 118 with the nano-metal particle layer 110 forms a sintered continuous phase structure.
  • the second adhesive layer 117 is thermally coupled to the heat sink 105.
  • the second co-sintered layer 118 may be located above the nano-metal particle layer 110, and the second subsequent layer 117 may be located above the second co-sintered layer 118 under the heat sink 105.
  • the second co-sintered layer 118 includes However, it is not limited to any of the following materials: silver, gold or copper.
  • the second adhesive layer 117 includes, but is not limited to, any of the following materials: titanium, chromium, nickel, or nickel/vanadium. The second adhesive layer 117 increases the bonding strength between the second co-sintered layer 115 and the heat sink 105.
  • FIG. 6 is a cross-sectional view showing a second embodiment of the second alloy layer 112 of FIG. 2.
  • the second alloy layer 112 of FIG. 6 further includes a second buffer layer 119 between the second adhesive layer 117 and the second co-sintered layer 118.
  • the second buffer layer 119 includes, but is not limited to, any of the following materials: aluminum, copper, nickel, or nickel/vanadium.
  • the second buffer layer 119 provides a buffering function in the deformation caused by the heat treatment, reducing the risk of cracks occurring between the thermal interface material layer and the heat sink 105 or the thermal interface material layer 114, increasing the reliability of the device.
  • the thermal interface material layer in the embodiment of the present invention no longer contains the polymer-based lower thermal conductive material in the silver-gel-like material, but contains the nano-metal particles, the thermal interface material in the embodiment of the present invention has The higher thermal conductivity greatly improves the thermal conductivity of the overall thermal path and can better meet the heat dissipation requirements of large power chips.
  • FIG. 7 is a flow chart 700 of a method of fabricating a device in accordance with a second embodiment of the present invention.
  • a first alloy layer is created.
  • a layer of nano metal particles is formed from the nano metal particles and the intermediate mixture.
  • the diameter of the nano metal particles is no more than 1 micrometer, for example, the diameter of the nano metal particles is between 50 and 200 nanometers.
  • the intermediate mixture includes, but is not limited to, any of the following materials: air or resin.
  • the nano metal particles include, but are not limited to, silver.
  • a second alloy layer is produced.
  • the first alloy layer is thermally coupled to the nano metal particle layer and the circuit device.
  • the second alloy layer is thermally coupled to the nano metal particle layer and the heat sink.
  • the contact between the first alloy layer and the nano metal particle layer forms a sintered continuous phase structure
  • the contact between the nano metal particles forms a sintered continuous phase structure
  • the second alloy layer and the nano metal particles are formed.
  • the contact of the layer forms a sintered continuous phase structure.
  • the method can be used with, but is not limited to, a flip chip ball grid array structure.
  • generating the first alloy layer includes forming a first adhesive layer and a first co-sintered layer, and thermally coupling the first adhesive layer to the circuit device to couple the first co-sinter layer to the nano metal particle layer, and A sintered continuous phase structure is formed at the contact of the first co-sintered layer with the nano-metal particle layer.
  • the first adhesive layer includes, but is not limited to, any of the following materials: titanium, chromium, nickel, or nickel/vanadium.
  • the first co-sintered layer includes, but is not limited to, any of the following materials: silver, gold or copper.
  • Forming the first alloy layer further includes creating a first buffer layer between the first adhesive layer and the first co-sintered layer.
  • the first buffer layer includes, but is not limited to, any of the following materials: aluminum, copper, nickel, or nickel/vanadium.
  • generating the second alloy layer includes forming a second adhesive layer and a second co-sintered layer, and thermally coupling the second adhesive layer to the heat sink to thermally couple the second sintered layer to the nano metal particle layer, And forming a sintered continuous phase structure at the contact of the second co-sintered layer and the nano metal particle layer.
  • the second adhesive layer includes, but is not limited to, any of the following materials: titanium, chromium, nickel, or nickel/vanadium.
  • the second co-sintered layer includes, but is not limited to, any of the following materials: silver, gold or copper.
  • generating the second alloy layer further includes creating a second buffer layer between the second adhesive layer and the second co-sintered layer.
  • the second buffer layer includes, but is not limited to, any of the following materials: aluminum, copper, nickel, or nickel/vanadium.
  • the circuit device can include an integrated circuit die. Thermally coupling the first alloy layer to the circuit device includes thermally coupling the first alloy layer to the substrate in the integrated circuit die.

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Abstract

一种装置，包括电路器件（103）、散热片（105）及热界面材料层（104）。热界面材料层（104）与电路器件（103）及散热片（105）热耦合。热界面材料层（104）包括第一合金层（109）、纳米金属颗粒层（110）及第二合金层（112）。第一合金层（109）与电路器件（103）热耦合。纳米金属颗粒层（110）与第一合金层（109）热耦合。纳米金属颗粒层（110）包括纳米金属颗粒（113）及中间混合物（111）。

Description

一种装置及制造方法
本申请要求于2015年8月27日提交中国专利局、申请号为201510535388.X、发明名称为“一种装置及制造方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及电路领域，尤其涉及一种电路装置及制造方法。
背景技术
图1A所示为现有技术中集成电路芯片及其部分封装结构的截面示例图。该结构包括集成电路芯片1A02、热界面材料层1A04及散热器1A06。集成电路芯片1A02于工作过程中产生的热通过芯片背面的热界面材料层1A04倒入散热器1A06，因而，热界面材料层1A04本身的导热能力对芯片散热有重要影响。现有热界面材料层包括银胶类材料。银胶类材料中混合金属银颗粒1A08以提高导热效果，但主要还是以银胶类材料形成的连续相为主。银胶类材料导热率较低，已很难满足大功率芯片的散热需求。
发明内容
本发明实施例提供一种装置及制造方法。该装置中，介于电路器件及散热片间的热界面材料具有较高导热率，大幅度提高了整体热通路的热导效能，能更好地满足大功耗电路器件的散热需求。
第一方面，本发明实施例提供了一种装置，包括：电路器件；散热片；及热界面材料层，与所述电路器件及所述散热片热耦合，包括：第一合金层，与所述电路器件热耦合；纳米金属颗粒层，与所述第一合金层热耦合，所述纳米金属颗粒层包括相互耦合的多个纳米金属颗粒及中间混合物，所述中间混合物填充于所述多个纳米金属颗粒之间；及第二合金层，与所述纳米金属颗粒层及所述散热片热耦合。
在第一方面的第一种可能的实现方式中，所述第一合金层与所述纳米金 属颗粒层的接触处形成烧结连续相结构，所述多个纳米金属颗粒之间的接触处形成烧结连续相结构，且所述第二合金层与所述纳米金属颗粒层的接触处形成烧结连续相结构。
结合第一方面，或者第一方面第一种可能的实现方式，在第二种可能的实现方式中，所述纳米金属颗粒包括银。
结合第一方面，或者第一方面第一至第二种任意一种可能的实现方式，在第三种可能的实现方式中，所述纳米金属颗粒的直径处于50-200纳米之间。
结合第一方面，或者第一方面第一至第三种任意一种可能的实现方式，在第四种可能的实现方式中，用于倒装芯片球栅格阵列结构。
结合第一方面，或者第一方面第一至第四种任意一种可能的实现方式，在第五种可能的实现方式中，第一合金层包括第一接着层和第一共烧结层，所述第一接着层与所述电路器件热耦合，所述第一共烧结层与所述纳米金属颗粒层耦合，且所述第一共烧结层与所述纳米金属颗粒层的接触处形成烧结连续相结构。
结合第一方面第五种可能的实现方式，在第六种可能的实现方式中，所述第一接着层包括以下材料中的任一种：钛、铬、镍或镍钒合金，所述第一共烧结层包括以下材料中的任一种：银、金或铜。
结合第一方面第五种可能的实现方式以及第六种可能的实现方式中的任意一种可能的实现方式，在第七种可能的实现方式中，所述第一合金层还包括第一缓冲层，位于所述第一接着层与所述第一共烧结层之间，所述第一缓冲层包括以下材料中的任一种：铝、铜、镍或镍钒合金。
结合第一方面，或者第一方面第一至第七种任意一种可能的实现方式，在第八种可能的实现方式中，所述第二合金层包括第二接着层和第二共烧结层，所述第二接着层与所述散热片热耦合，所述第二共烧结层与所述纳米金属颗粒层热耦合，且所述第二共烧结层与所述纳米金属颗粒层的接触处形成烧结连续相结构。
结合第一方面第八种可能的实现方式，在第九种可能的实现方式中，所述第二接着层包括以下材料中的任一种：钛、铬、镍或镍钒合金，所述第二共烧结层包括以下材料中的任一种：银、金或铜。
结合第一方面第八种可能的实现方式以及第九种可能的实现方式中的任意一种可能的实现方式，在第十种可能的实现方式中，所述第二合金层还包括第二缓冲层，位于所述第二接着层与所述第二共烧结层之间，所述第二缓冲层包括以下材料中的任一种：铝、铜、镍或镍钒合金。
结合第一方面，或者第一方面第一至第十种任意一种可能的实现方式，在第十一种可能的实现方式中，所述纳米金属颗粒的直径不大于1微米。
结合第一方面，或者第一方面第一至第十一种任意一种可能的实现方式，在第十二种可能的实现方式中，所述中间混合物包括以下材料中的任一种：空气或树脂。
结合第一方面，或者第一方面第一至第十二种任意一种可能的实现方式，在第十三种可能的实现方式中，所述电路器件包括集成电路管芯，所述集成电路管芯中的衬底与所述热界面材料层热耦合。
第二方面，本发明实施例提供了一种制造装置的方法，包括：生成第一合金层；由相互耦合的多个纳米金属颗粒与中间混合物生成纳米金属颗粒层，使所述中间混合物填充于所述多个纳米金属颗粒之间；及生成第二合金层，其中，使所述第一合金层与电路器件热耦合，使所述纳米金属颗粒层与所述第一合金层热耦合，并使所述第二合金层与所述纳米金属颗粒层及散热片热耦合。
在第二方面的第一种可能的实现方式中，使所述第一合金层与所述纳米金属颗粒层的接触处形成烧结连续相结构，使所述纳米金属颗粒之间的接触处形成烧结连续相结构，且使所述第二合金层与所述纳米金属颗粒层的接触处形成烧结连续相结构。
结合第二方面，或者第二方面第一种可能的实现方式，在第二种可能的实现方式中，所述纳米金属颗粒的直径不大于1微米。
结合第二方面，或者第二方面第一至第二种任意一种可能的实现方式，在第三种可能的实现方式中，所述中间混合物包括以下材料中的任一种：空气或树脂。
结合第二方面，或者第二方面第一至第三种任意一种可能的实现方式，在第四种可能的实现方式中，所述生成第一合金层包括：生成第一接着层和第一共烧结层，并使所述第一接着层与所述电路器件热耦合，使所述第一共 烧结层与所述纳米金属颗粒层耦合，且使所述第一共烧结层与所述纳米金属颗粒层的接触处形成烧结连续相结构。
结合第二方面，或者第二方面第一至第四种任意一种可能的实现方式，在第五种可能的实现方式中，所述生成第二合金层包括：生成第二接着层和第二共烧结层，并使所述第二接着层与所述散热片热耦合，使所述第二共烧结层与所述纳米金属颗粒层热耦合，且使所述第二共烧结层与所述纳米金属颗粒层的接触处形成烧结连续相结构。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1A是现有技术中包括装置的封装结构的截面示例图。
图1是本发明第一实施例的包括装置的封装结构的截面示例图。
图2包括图1中的热界面材料层的第一实施例的截面示例图。
图3是图2中的第一合金层的第一实施例的截面示例图。
图4是图2中的第一合金层的第二实施例的截面示例图。
图5是图2中的第二合金层的第一实施例的截面示例图。
图6是图2中第二合金层的第二实施例的截面示例图。
图7是本发明第二实施例的一种制造装置的方法的流程图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
图1是本发明第一实施例的包括装置的封装结构100的截面示例图。该 倒装芯片球栅格阵列封装结构包括焊球108，基板107，粘接胶106，金属凸块(BUMP)102，电路器件(如集成电路管芯)103，热界面材料层104及散热片105。集成电路管芯103通过金属凸块102与基板107耦合。金属凸块102由底部填充物101保护。散热片105通过粘接胶106固定在基板107上。热界面材料层104与集成电路管芯103及散热片105热耦合。本文中，热耦合包括不同层次，不同结构，或不同装置间有热传导的情形。更详细地，热界面材料层104可位于集成电路管芯103及散热片105之间。集成电路管芯103中的衬底与热界面材料层104热耦合。集成电路管芯103的热量通过热界面材料层104达到散热片105。
其中，集成电路管芯103、热界面材料层104及散热片105可作为一种装置的部分或全部组件，且该装置可用于但不限于如图所示的倒装芯片球栅格阵列封装结构。
图2包括图1中的热界面材料层104的第一实施例的截面示例图。热界面材料层104与管芯103及散热片105热耦合，包括第一合金层109、纳米金属颗粒层110及第二合金层112。
第一合金层109与集成电路管芯103及纳米金属颗粒层110热耦合。更具体地，如图所示，第一合金层109可位于集成电路管芯103之上，纳米金属颗粒层110之下。即，第一合金层109可位于集成电路管芯103与纳米金属颗粒层110之间。第一合金层109增加集成电路管芯103与纳米金属颗粒层110之间的接着强度。
纳米金属颗粒层110包括纳米金属颗粒及中间混合物。中间混合物包括但不限于以下材料中的任一种：空气或树脂。中间混合物用于填充于多个纳米金属颗粒之间，使多个纳米金属颗粒形成整体。纳米金属颗粒包括但不限于银。纳米金属颗粒的直径不大于1微米。在一个实施例中，纳米金属颗粒的直径处于50-200纳米之间。纳米金属颗粒层110热阻较低，形成较好的导热通路。
第二合金层112与纳米金属颗粒层110及散热片105热耦合。更具体地，如图所示，第二合金层112可位于纳米金属颗粒层110之上，散热片105之下。即，第二合金层112可位于纳米金属颗粒层110与散热片105之间。第二合金层112增加纳米金属颗粒层110与散热片105之间的接着 强度。
在一个实施例中，第一合金层109与纳米金属颗粒层110的接触处形成烧结连续相结构，纳米金属颗粒之间的接触处形成烧结连续相结构，且第二合金层112与纳米金属颗粒层110的接触处形成烧结连续相结构。本文中的烧结连续相结构包括但不限于：因金属颗粒产生烧结行为，金属颗粒接口附近的金属原子扩散至金属颗粒界面融合在一起，使得金属颗粒形成一个整体的结构。
图3是图2中第一合金层109的第一实施例的截面示例图。如图所示，第一合金层109包括第一接着层114和第一共烧结层115。本文中的共烧结层包括但不限于：在封装加工过程中产生的与热界面材料层互融的金属层，该金属层与热界面材料层中的颗粒共同烧结形成热流通路。第一接着层114与集成电路管芯103热耦合。第一共烧结层115与纳米金属颗粒层110热耦合。第一共烧结层115与纳米金属颗粒层110的接触处形成烧结连续相结构。具体地，第一接着层114可位于集成电路管芯103之上，第一共烧结层115可位于第一接着层114之上，纳米金属颗粒层110之下。第一接着层114包括但不限于以下材料中的任一种：钛、铬、镍或镍/钒。第一接着层114增加集成电路管芯103与第一共烧结层115之间的结合强度。第一共烧结层115包括但不限于以下材料中的任一种：银、金或铜。
图4是图2中第一合金层109的第二实施例的截面示例图。与图3相比，图4中的第一合金层109还包括第一缓冲层116，位于所述第一接着层114与第一共烧结层115之间。第一缓冲层116包括但不限于以下材料中的任一种：铝、铜或镍。第一缓冲层116在因热处理产生的形变中提供应力缓冲功能，降低集成电路管芯103与热界面材料层114间或热界面材料层114中间产生裂缝的风险，增加该装置的可靠性。
图5是图2中第二合金层112的第一实施例的截面示例图。如图所示，第二合金层112包括第二共烧结层118和第二接着层117。第二共烧结层118与纳米金属颗粒层110热耦合。第二共烧结层118与纳米金属颗粒层110的接触处形成烧结连续相结构。第二接着层117与散热片105热耦合。具体地，第二共烧结层118可位于纳米金属颗粒层110之上，第二接着层117可位于第二共烧结层118之上，散热片105之下。第二共烧结层118包括 但不限于以下材料中的任一种：银、金或铜。第二接着层117包括但不限于以下材料中的任一种：钛、铬、镍或镍/钒。第二接着层117增加第二共烧结层115与散热片105之间的结合强度。
图6是图2中第二合金层112的第二实施例的截面示例图。与图5相比，图6中的第二合金层112还包括第二缓冲层119，位于第二接着层117与第二共烧结层118之间。第二缓冲层119包括但不限于以下材料中的任一种：铝、铜、镍或镍/钒。第二缓冲层119在因热处理产生的形变中提供缓冲功能，降低热界面材料层与散热片105间或热界面材料层114中间产生裂缝的风险，增加该装置的可靠性。
综上，由于本发明实施例中的热界面材料层中不再包含银胶类材料中的高分子类较低热导材料，而是包含纳米金属颗粒，本发明实施例中的热界面材料具有较高导热率，大幅度提高了整体热通路的热导效能，能更好地满足大功耗芯片的散热需求。
图7是本发明第二实施例的一种制造装置的方法的流程图700。如图所示，在步骤702中，生成第一合金层。在步骤704中，由纳米金属颗粒与中间混合物生成纳米金属颗粒层。纳米金属颗粒的直径不大于1微米，例如，纳米金属颗粒的直径处于50-200纳米之间。中间混合物包括但不限于以下材料中的任一种：空气或树脂。在一个实施例中，纳米金属颗粒包括但不限于银。在步骤706中，生成第二合金层。在步骤708中，使第一合金层与纳米金属颗粒层及电路器件热耦合。在步骤710中，使第二合金层与纳米金属颗粒层及散热片热耦合。
在一个实施例中，使第一合金层与纳米金属颗粒层的接触处形成烧结连续相结构，使纳米金属颗粒之间的接触处形成烧结连续相结构，且使第二合金层与纳米金属颗粒层的接触处形成烧结连续相结构。
在一个实施例中，该方法可用于但不限于倒装芯片球栅格阵列结构。
在一个实施例中，生成第一合金层包括生成第一接着层和第一共烧结层，并使第一接着层与电路器件热耦合，使第一共烧结层与纳米金属颗粒层耦合，且使第一共烧结层与纳米金属颗粒层的接触处形成烧结连续相结构。第一接着层包括但不限于以下材料中的任一种：钛、铬、镍或镍/钒。第一共烧结层包括但不限于以下材料中的任一种：银、金或铜。在另一个实施例中， 生成第一合金层还包括在第一接着层与第一共烧结层之间生成第一缓冲层。第一缓冲层包括但不限于以下材料中的任一种：铝、铜、镍或镍/钒。
在一个实施例中，生成第二合金层包括生成第二接着层和第二共烧结层，并使第二接着层与散热片热耦合，使第二共烧结层与纳米金属颗粒层热耦合，且使所述第二共烧结层与所述纳米金属颗粒层的接触处形成烧结连续相结构。第二接着层包括但不限于以下材料中的任一种：钛、铬、镍或镍/钒。第二共烧结层包括但不限于以下材料中的任一种：银、金或铜。在另一个实施例中，生成第二合金层还包括在第二接着层与第二共烧结层之间生成第二缓冲层。第二缓冲层包括但不限于以下材料中的任一种：铝、铜、镍或镍/钒。
电路器件可包括集成电路管芯。使第一合金层与电路器件热耦合包括使第一合金层与集成电路管芯中的衬底热耦合。
以上所揭露的仅为本发明较佳实施例而已，当然不能以此来限定本发明之权利范围，因此依本发明权利要求所作的等同变化，仍属本发明所涵盖的范围。

Claims (19)

  1. 一种装置，其特征在于，包括：
    电路器件；
    散热片；及
    热界面材料层，与所述电路器件及所述散热片热耦合，包括：
    第一合金层，与所述电路器件热耦合；
    纳米金属颗粒层，与所述第一合金层热耦合，所述纳米金属颗粒层包括相互耦合的多个纳米金属颗粒及中间混合物，所述中间混合物填充于所述多个纳米金属颗粒之间；及
    第二合金层，与所述纳米金属颗粒层及所述散热片热耦合。
  2. 如权利要求1所述的装置，其特征在于，所述第一合金层与所述纳米金属颗粒层的接触处形成烧结连续相结构，所述多个纳米金属颗粒之间的接触处形成烧结连续相结构，且所述第二合金层与所述纳米金属颗粒层的接触处形成烧结连续相结构。
  3. 如权利要求1或2所述的装置，其特征在于，所述多个纳米金属颗粒包括银。
  4. 如权利要求1-3中任一项所述的装置，其特征在于，所述多个纳米金属颗粒的直径处于50-200纳米之间。
  5. 如权利要求1-4中任一项所述的装置，其特征在于，用于倒装芯片球栅格阵列结构。
  6. 如权利要求1-5中任一项所述的装置，其特征在于，第一合金层包括第一接着层和第一共烧结层，所述第一接着层与所述电路器件热耦合，所述第一共烧结层与所述纳米金属颗粒层耦合，且所述第一共烧结层与所述纳米金属颗粒层的接触处形成烧结连续相结构。
  7. 如权利要求6所述的装置，其特征在于，所述第一接着层包括以下材料中的任一种：钛、铬、镍或镍钒合金，所述第一共烧结层包括以下材料中的任一种：银、金或铜。
  8. 如权利要求6或7所述的装置，其特征在于，所述第一合金层还包括第一缓冲层，位于所述第一接着层与所述第一共烧结层之间，所述第一缓冲层包括以下材料中的任一种：铝、铜、镍或镍钒合金。
  9. 如权利要求1-8中任一项所述的装置，其特征在于，所述第二合金层包括第二接着层和第二共烧结层，所述第二接着层与所述散热片热耦合，所述第二共烧结层与所述纳米金属颗粒层热耦合，且所述第二共烧结层与所述纳米金属颗粒层的接触处形成烧结连续相结构。
  10. 如权利要求9所述的装置，其特征在于，所述第二接着层包括以下材料中的任一种：钛、铬、镍或镍钒合金，所述第二共烧结层包括以下材料中的任一种：银、金或铜。
  11. 如权利要求9或10所述的装置，其特征在于，所述第二合金层还包括第二缓冲层，位于所述第二接着层与所述第二共烧结层之间，所述第二缓冲层包括以下材料中的任一种：铝、铜、镍或镍钒合金。
  12. 如权利要求1-11中任一所述的装置，其特征在于，所述中间混合物包括以下材料中的任一种：空气或树脂。
  13. 如权利要求1-12中任一项所述的装置，其特征在于，所述电路器件包括集成电路管芯，所述集成电路管芯中的衬底与所述热界面材料层热耦合。
  14. 一种制造装置的方法，其特征在于，包括：
    生成第一合金层；
    由相互耦合的多个纳米金属颗粒与中间混合物生成纳米金属颗粒层，使所述中间混合物填充于所述多个纳米金属颗粒之间；及
    生成第二合金层，
    其中，使所述第一合金层与电路器件热耦合，使所述纳米金属颗粒层与所述第一合金层热耦合，并使所述第二合金层与所述纳米金属颗粒层及散热片热耦合。
  15. 如权利要求14所述的方法，其特征在于，还包括使所述第一合金层与所述纳米金属颗粒层的接触处形成烧结连续相结构，使所述纳米金属颗粒之间的接触处形成烧结连续相结构，且使所述第二合金层与所述纳米金属颗粒层的接触处形成烧结连续相结构。
  16. 如权利要求14或15所述的方法，其特征在于，所述多个纳米金属颗粒的直径不大于1微米。
  17. 如权利要求14-16中任一所述的方法，其特征在于，所述中间混合物包括以下材料中的任一种：空气或树脂。
  18. 如权利要求14-17中任一所述的方法，其特征在于，所述生成第一合金层包括：生成第一接着层和第一共烧结层，并使所述第一接着层与所述电路器件热耦合，使所述第一共烧结层与所述纳米金属颗粒层耦合，且使所述第一共烧结层与所述纳米金属颗粒层的接触处形成烧结连续相结构。
  19. 如权利要求14-18中任一所述的方法，其特征在于，所述生成第二合金层包括：生成第二接着层和第二共烧结层，并使所述第二接着层与所述散热片热耦合，使所述第二共烧结层与所述纳米金属颗粒层热耦合，且使所述第二共烧结层与所述纳米金属颗粒层的接触处形成烧结连续相结构。
PCT/CN2016/096373 2015-08-27 2016-08-23 一种装置及制造方法 Ceased WO2017032301A1 (zh)

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