WO2017036081A1 - 阵列基板、显示装置及其驱动方法 - Google Patents

阵列基板、显示装置及其驱动方法 Download PDF

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Publication number
WO2017036081A1
WO2017036081A1 PCT/CN2016/072123 CN2016072123W WO2017036081A1 WO 2017036081 A1 WO2017036081 A1 WO 2017036081A1 CN 2016072123 W CN2016072123 W CN 2016072123W WO 2017036081 A1 WO2017036081 A1 WO 2017036081A1
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Prior art keywords
pixel
thin film
row
array substrate
film transistor
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Ceased
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PCT/CN2016/072123
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English (en)
French (fr)
Inventor
王小元
王武
金在光
许卓
白雅杰
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BOE Technology Group Co Ltd
Chongqing BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Chongqing BOE Optoelectronics Technology Co Ltd
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Priority to US15/311,899 priority Critical patent/US10311811B2/en
Priority to EP16791294.8A priority patent/EP3343284A4/en
Publication of WO2017036081A1 publication Critical patent/WO2017036081A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3659—Control of matrices with row and column drivers using an active matrix the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes

Definitions

  • the present invention relates to an array substrate, a display device, and a driving method thereof, and more particularly to an array substrate having a two-line dot inversion mode, a display device, and a driving method thereof.
  • Inverting the polarity of the output signal on the data line can prevent the liquid crystal molecules of the liquid crystal display panel from aging and improve the display quality.
  • Common polarity reversal methods include: frame inversion, line inversion, column inversion, and dot inversion.
  • the dot inversion can be further divided into a line point inversion, a two line point inversion and a plus two line point inversion.
  • the bright pictures appearing in the picture mode of the one-line flashing mode are positive, which causes the liquid crystal capacitors to not have high-frequency polarity exchange in the vertical and horizontal directions, resulting in serious The picture flickers.
  • Two-line inversion can solve the flickering phenomenon that occurs in the picture mode of the one-line flashing mode.
  • the technical solution of the present invention is proposed in view of the above technical problems existing in the prior art.
  • the inversion mode of the two-line dot inversion can be provided to solve the problem of the flicker phenomenon of the one-line dot inversion under the specific display screen, without increasing the array substrate. Power consumption.
  • an array substrate comprising a plurality of gate lines extending in a first direction, a plurality of data lines extending in a second direction crossing the first direction, and along the first direction and The two directions are arranged as a plurality of pixel units of the array.
  • Each of the data lines is disposed in two columns of pixel units extending in the second direction and adjacent in the first direction And connected to a pixel unit located on one side of the data line or to a pixel unit located on the other side.
  • the data line switches the connection direction from one side to the other side thereof in cycles of two rows of pixel cells adjacent in the second direction, and the connection directions of the respective data lines in the same row of pixel cells are the same.
  • each of the gate lines may correspond to a row of pixel cells extending in the first direction.
  • each of the pixel units may include a pixel electrode connected to a drain of the thin film transistor, a gate electrode connected to a corresponding pixel unit through a gate of the thin film transistor, and a data line passing through the thin film transistor The source is connected to the corresponding pixel unit.
  • each of the two gate lines may correspond to a row of pixel cells extending in the first direction, and are respectively disposed on both sides of the row of pixel cells in the second direction.
  • each of the pixel units may include a first pixel electrode and a second pixel electrode, and a first thin film transistor and a second thin film transistor respectively corresponding to the first pixel electrode and the second pixel electrode, the first pixel The electrode and the second pixel electrode are respectively connected to drains of the first thin film transistor and the second thin film transistor.
  • Two gate lines corresponding to one row of pixel units may be respectively connected to respective gates of the first thin film transistor and the second thin film transistor in the row of pixel cells, and the data lines may pass through respective ones of the first thin film transistor and the second thin film transistor
  • the source is connected to the corresponding pixel unit.
  • the first pixel electrode and the second pixel electrode may be disposed in the pixel unit in the first direction.
  • one of two gate lines corresponding to one row of pixel cells may be connected to gates of respective first thin film transistors in the row of pixel cells, and two gates corresponding to one row of pixel cells Another gate line in the line may be connected to the gates of the respective second thin film transistors in the row of pixel cells.
  • the polarity of the output signal on each data line may remain unchanged within the same frame, and the polarity of the output signals on the two adjacent data lines in the first direction are opposite.
  • the polarity of the output signal on each data line may be inverted once between adjacent frames.
  • a display device comprising the array substrate according to any of the above embodiments is provided.
  • a method of driving an array substrate according to the present invention comprising: the polarity of an output signal on each data line remains unchanged in the same frame, and is adjacent in the first direction
  • the polarity of the output signals on the two data lines are opposite, such that the voltage applied to the pixel cells reverses polarity in a first direction with one pixel cell and two pixel cells in a second direction. Reverse polarity.
  • a reverse mode of two-line dot inversion can be provided to solve the problem of flickering phenomenon of a line point inversion under a specific display screen, without increasing the array.
  • the power consumption of the substrate is not limited to the embodiments of the present invention.
  • 1 is a schematic view showing an array substrate having a line dot inversion mode
  • FIG. 2 is a schematic view showing an array substrate of a double gate line structure having a line dot inversion mode
  • FIG. 3 is a schematic view showing an array substrate having a two-line dot inversion mode
  • FIG. 4 is a schematic view showing a case where a two-line dot inversion mode is applied to the array substrate shown in FIG. 1;
  • FIG. 5 is a schematic view showing a case where a two-line dot inversion mode is applied to the array substrate shown in FIG. 2;
  • FIG. 6 is a schematic view showing an array substrate according to an embodiment of the present invention.
  • FIG. 7 is a schematic view showing an array substrate according to another embodiment of the present invention.
  • FIG. 1 is a schematic view showing an array substrate having a line dot inversion mode.
  • the voltage applied to the pixel unit reverses the polarity in a row direction and a column direction with one pixel unit as a cycle.
  • the bright pictures appearing in the picture mode of the one-line flashing mode are positive, which causes the liquid crystal capacitors to not have high-frequency polarity exchange in the vertical and horizontal directions, resulting in serious The picture flickers.
  • Two-line inversion can solve the flickering phenomenon that occurs in the picture mode of the one-line flashing mode.
  • FIG. 2 is a schematic view showing an array substrate of a double gate line structure having a line dot inversion mode.
  • the so-called "double-gate line” structure means that each row of pixels is controlled by two gate lines to control the gate of the thin film transistor corresponding to the pixel, wherein one gate line controls the pixels of the odd-numbered columns, and the other gate line controls the even-numbered columns. Pixel.
  • double gate line For an array substrate having a "double gate line” structure controlled by a one-line dot inversion mode, since the polarities of pixels on both sides of each data line on the same row are alternately arranged in positive and negative, the data line is delayed. The effect of the pixel on each side of each data line on the same line is inconsistent, which affects the quality of the image display.
  • FIG. 3 is a schematic view showing an array substrate having a two-line dot inversion mode.
  • the voltage applied to the pixel unit reverses the polarity in a row direction by one pixel unit, and reverses the polarity in a column direction with two pixel units as a period.
  • the power consumption is increased.
  • FIG. 4 is a schematic view showing a case where a two-line dot inversion mode is applied to the array substrate shown in FIG. 1.
  • the pixel unit connected to the same data line includes pixel units of two polarities of positive polarity and negative polarity, so that it is necessary to make the polarity of the output signal on the same data line multiple times in the same frame. Turn, which greatly increases power consumption.
  • FIG. 3 is exemplified by an array substrate of a single gate line structure.
  • the two-line dot inversion mode shown in FIG. 3 can also be applied to the array substrate of the double gate line structure shown in FIG. 2.
  • FIG. 5 is a schematic view showing a case where the two-line dot inversion mode is applied to the array substrate shown in FIG. 2.
  • the array substrate of the double-gate line structure to which the two-line dot inversion is applied as shown in FIG. 5 also needs to be in the same frame, so that The polarity of the output signal on the same data line is inverted multiple times, which greatly increases power consumption.
  • FIG. 6 is a schematic view showing an array substrate according to an embodiment of the present invention.
  • an array substrate includes a plurality of gate lines Gn to Gn+5 extending in a first direction (for example, a row direction) in a second direction crossing the first direction (for example, A plurality of data lines Dn to Dn+7 extending in the column direction) and a plurality of pixel units arranged in an array in the first direction and the second direction.
  • each of the data lines is disposed between two columns of pixel units extending in the second direction and adjacent in the first direction, and connected to the pixel unit located on one side of the data line or connected to another a pixel unit on one side.
  • the data line Dn+3 is disposed between two columns of pixel cells extending in the column direction and adjacent in the row direction, and the data line Dn+3 is connected to the pixel cell located on the left or right side thereof.
  • the data line switches the connection direction from one side to the other side thereof in cycles of two rows of pixel cells adjacent in the second direction, and the connection directions of the respective data lines in the same row of pixel cells are the same.
  • the data line Dn+3 is connected to the pixel unit located on the right side thereof on the row corresponding to the gate lines Gn and Gn+1, corresponding to the gate lines Gn+2 and Gn+3.
  • the row is connected to the pixel cell on the left side thereof, and the row corresponding to the gate lines Gn+4 and Gn+5 is again connected to the pixel cell located on the right side thereof.
  • Each of the data lines Dn to Dn+7 has the same connection direction in the same row of pixel cells (for example, each row of pixel cells corresponding to each of the gate lines Gn to Gn+5).
  • each of the pixel units may include a pixel electrode and a thin film transistor.
  • the pixel electrode is connected to the drain of the thin film transistor, and each of the gate lines Gn to Gn+5 passes through the thin film crystal
  • the gate of the tube is connected to the corresponding row of pixel units, and the respective data lines Dn to Dn+7 are respectively connected to the corresponding pixel unit through the source of the thin film transistor.
  • each gate line corresponds to one row of pixel cells extending in the first direction (eg, the row direction), the present invention is not limited thereto.
  • FIG. 7 is a schematic view showing an array substrate according to another embodiment of the present invention.
  • Figure 7 shows an array substrate having a "double gate line" structure. Therefore, in the array substrate shown in FIG. 7, each pixel unit includes two adjacent pixels in the same row.
  • each of the two gate lines corresponds to a row of pixel units extending in a first direction (eg, a row direction), and is respectively disposed in the row of the pixel units in a second direction (eg, a column direction) On both sides.
  • the array substrate having the two-line dot inversion mode is particularly advantageous for an array substrate having a "double gate line” structure.
  • each pixel unit includes (corresponding to two pixels) a first pixel electrode and a second pixel electrode, and first thin film transistors and second corresponding to the first pixel electrode and the second pixel electrode, respectively
  • the thin film transistor, the first pixel electrode and the second pixel electrode are respectively connected to drains of the first thin film transistor and the second thin film transistor.
  • Two gate lines corresponding to one row of pixel cells are respectively connected to respective gates of the first thin film transistor and the second thin film transistor in the row of pixel cells.
  • the gate lines Gn-1 and Gn corresponding to the third row of pixel cells shown in FIG. 7 are respectively connected to the gates of the first thin film transistor and the second thin film transistor in the row of pixel cells.
  • the data line is connected to the corresponding pixel unit through a source of each of the first thin film transistor and the second thin film transistor.
  • the data line Dn is connected rightward to the first row of pixel units corresponding to the gate lines Gn-5 and Gn-4 through the respective sources of the respective first and second thin film transistors.
  • the third row of pixel cells connected to the left gate lines Gn-1 and Gn, and the gate lines Gn+1 and Gn+2
  • the fourth row of pixel cells are connected to the fifth row of pixel cells corresponding to the gate lines Gn+3 and Gn+4 and the sixth row of pixel cells corresponding to the gate lines Gn+5 and Gn+6.
  • one of the two gate lines corresponding to one row of pixel cells is connected to the gate of each of the first thin film transistors in the row of pixel cells, and two gate lines corresponding to one row of pixel cells Another gate line is connected to the gates of the respective second thin film transistors in the row of pixel cells.
  • the gate line Gn-1 corresponding to the third row of pixel cells shown in FIG. 7 is connected to the gate of the first thin film transistor in each pixel unit of the row, and corresponds to the third row of pixel cells shown in FIG.
  • the gate line Gn is connected to the gate of the second thin film transistor in each pixel unit of the row.
  • a method for driving an array substrate according to the present invention is provided.
  • the pixel unit connected to the same data line includes both positive polarity and negative polarity.
  • a pixel unit of a polarity so that the polarity of the output signal on the same data line needs to be inverted multiple times in the same frame, thereby greatly increasing power consumption.
  • the pixel units connected to the same data line are all pixel units of the same polarity, as shown in FIGS. 6 and 7. Therefore, when driving the array substrate according to the present invention, the polarity of the output signal on each data line remains unchanged in the same frame, and two adjacent data lines in the first direction (for example, the row direction) The output signals on the opposite polarity. For example, as shown in FIG. 6, at the Nth frame, the polarity of the output signal on the data line Dn is positive and remains unchanged, and the polarity of the output signal on the data line Dn+1 is negative and remains unchanged. .
  • the output signals on the same data line have the same polarity, and the polarity of the output signal on the data line is inverted only once between frames, thereby greatly reducing power consumption.
  • the present invention is not limited thereto.
  • the contemplated array substrate can include more rows and/or more columns of pixel cells and corresponding data and gate lines as desired.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal (AREA)

Abstract

一种阵列基板、显示装置及其驱动方法。所述阵列基板包括在第一方向上延伸的多条栅线（Gn…Gn+5）、在与第一方向交叉的第二方向上延伸的多条数据线（Dn…Dn+7）以及沿第一方向和第二方向排列为阵列的多个像素单元。每条数据线（Dn…Dn+7）设置在在第二方向上延伸并且在第一方向上相邻的两列像素单元之间，并且连接至位于该条数据线（Dn…Dn+7）一侧的像素单元或者连接至位于另一侧的像素单元。数据线（Dn…Dn+7）以在第二方向上相邻的两行像素单元为周期将连接方向从其一侧切换至其另一侧，并且各条数据线（Dn…Dn+7）在同一行像素单元的连接方向相同。

Description

阵列基板、显示装置及其驱动方法 技术领域
本发明涉及一种阵列基板、显示装置及其驱动方法，具体地，涉及具有二线点反转模式的阵列基板、显示装置及其驱动方法。
背景技术
使得数据线上的输出信号的极性反转可以防止液晶显示面板的液晶分子老化，改善显示品质。常见的极性反转方式包括：帧反转、行反转、列反转和点反转等。其中点反转又可以分为一线点反转、二线点反转和一加二线点反转等方式。
对于一线点反转而言，在一线点闪烁模式的画面模式下会出现亮的画面均是正极性，从而造成液晶电容在垂直和水平方向上均不能出现高频的极性交换，导致严重的画面闪烁现象。二线点反转可以解决一线点闪烁模式的画面模式下出现的画面闪烁现象。
此外，对于以一线点反转模式进行控制的具有“双栅线”结构的阵列基板而言，因为同一行上每条数据线两侧的像素的极性是正负交替排布的，受到数据线延迟的影响，会导致同一行上每条数据线两侧的像素的充电效果不一致，从而影响图像显示的质量。采用二线点反转模式可以有效地改善这种现象。
然而，将二线点反转的反转方式应用于根据现有技术的具有一线点反转模式的阵列基板时，会造成功耗增大的问题。
发明内容
针对现有技术中存在的上述技术问题，提出本发明的技术方案。根据本发明各实施例的阵列基板、显示装置及其驱动方法，可以提供二线点反转的反转方式以解决一线点反转在特定显示画面下出现的画面闪烁现象问题，同时不增加阵列基板的功耗。
根据本发明的一个方面，提供一种阵列基板，包括在第一方向上延伸的多条栅线、在与第一方向交叉的第二方向上延伸的多条数据线以及沿第一方向和第二方向排列为阵列的多个像素单元。每条数据线设置在在第二方向上延伸并且在第一方向上相邻的两列像素单元之 间，并且连接至位于该条数据线一侧的像素单元或者连接至位于另一侧的像素单元。数据线以在第二方向上相邻的两行像素单元为周期将连接方向从其一侧切换至其另一侧，并且各条数据线在同一行像素单元的连接方向相同。
根据本发明的实施例，每条栅线可以对应于在第一方向上延伸的一行像素单元。
根据本发明的实施例，每个像素单元可以包括像素电极和薄膜晶体管，像素电极连接至薄膜晶体管的漏极，栅线通过薄膜晶体管的栅极连接至对应的像素单元，并且数据线通过薄膜晶体管的源极连接至对应的像素单元。
根据本发明的实施例，每两条栅线可以对应于在第一方向上延伸的一行像素单元，并且分别设置在该行像素单元在第二方向上的两侧。
根据本发明的实施例，每个像素单元可以包括第一像素电极和第二像素电极，以及分别与第一像素电极和第二像素电极对应的第一薄膜晶体管和第二薄膜晶体管，第一像素电极和第二像素电极分别连接至第一薄膜晶体管和第二薄膜晶体管各自的漏极。与一行像素单元对应的两条栅线可以分别连接至该行像素单元中的第一薄膜晶体管和第二薄膜晶体管各自的栅极，并且数据线可以通过第一薄膜晶体管和第二薄膜晶体管各自的源极连接至对应的像素单元。
根据本发明的实施例，第一像素电极和第二像素电极可以沿第一方向设置在像素单元中。
根据本发明的实施例，与一行像素单元对应的两条栅线中的一条栅线可以连接至该行像素单元中的各个第一薄膜晶体管的栅极，并且与一行像素单元对应的两条栅线中的另一条栅线可以连接至该行像素单元中的各个第二薄膜晶体管的栅极。
根据本发明的实施例，每条数据线上的输出信号的极性可以在同一帧内保持不变，并且在第一方向上相邻的两条数据线上的输出信号的极性相反。
根据本发明的实施例，每条数据线上的输出信号的极性可以在相邻两帧之间反转一次。
根据本发明的另一个方面，提供一种显示装置，包括根据上述任一项实施例的阵列基板。
根据本发明的另一个方面，提供一种驱动根据本发明的阵列基板的方法，包括：每条数据线上的输出信号的极性在同一帧内保持不变，并且在第一方向上相邻的两条数据线上的输出信号的极性相反，使得施加至像素单元的电压在第一方向上以一个像素单元为周期反转极性，并且在第二方向上以两个像素单元为周期反转极性。
根据本发明各实施例的阵列基板、显示装置及其驱动方法，可以提供二线点反转的反转方式以解决一线点反转在特定显示画面下出现的画面闪烁现象问题，同时不会增加阵列基板的功耗。
附图说明
通过以下结合附图的详细描述，将更加清楚地理解以上和其它方面、特征和其它优点，其中：
图1是示出了具有一线点反转模式的阵列基板的示意图；
图2是示出了具有一线点反转模式的双栅线结构的阵列基板的示意图；
图3是示出了具有二线点反转模式的阵列基板的示意图；
图4是示出了将二线点反转模式应用于图1所示的阵列基板时的示意图；
图5是示出了将二线点反转模式应用于图2所示的阵列基板时的示意图；
图6是示出了根据本发明一个实施例的阵列基板的示意图；以及
图7是示出了根据本发明另一个实施例的阵列基板的示意图。
具体实施方式
下文中，将参照附图详细描述本发明构思的示例性实施例。
然而，本发明构思可按照许多不同形式例示，并且不应理解为限于本文阐述的特定实施例。此外，提供这些实施例是为了使得本公开将是彻底和完整的，并且将把本发明构思的范围完全传递给本领域技术人员。
为了清楚起见，在附图中可夸大示出元件的形状和尺寸。并且相同的附图标记将用于始终指代相同或相似的元件。
为了方便描述，本文中可使用诸如“在......下方”、“在......上 方”、“在......左侧”、“在......右侧”等的空间相对术语，以描述附图中所示的一个元件或特征与另一个(一些)元件或特征的关系。应该理解，空间相对术语旨在涵盖使用或操作中的装置的除图中所示的取向之外的不同取向。例如，如果图中的装置颠倒，则被描述为“在其它元件或特征下方”的元件将因此被取向为“在其它元件或特征上方”。这样，示例性术语“在......下方”可涵盖“在......下方”和“在......上方”这两个取向。装置可按照其它方式取向(旋转90度或位于其它取向)，并且本文所用的空间相对描述语将相应地解释。
除非另外限定，否则本文中使用的所有术语(包括技术和科学术语)具有与本发明所属领域的普通技术人员通常理解的含义相同的含义。还应该理解，除非本文中明确这样定义，否则诸如在通用词典中定义的那些术语应该被解释为具有与它们在相关技术和/或本说明书的上下文中的含义一致的含义，而不应该按照理想化地或过于正式的含义来解释它们。
图1是示出了具有一线点反转模式的阵列基板的示意图。如图1所示，施加至像素单元的电压在行方向上和列方向上均以一个像素单元为周期反转极性。对于一线点反转而言，在一线点闪烁模式的画面模式下会出现亮的画面均是正极性，从而造成液晶电容在垂直和水平方向上均不能出现高频的极性交换，导致严重的画面闪烁现象。二线点反转可以解决一线点闪烁模式的画面模式下出现的画面闪烁现象。
图2是示出了具有一线点反转模式的双栅线结构的阵列基板的示意图。所谓“双栅线”结构是指：每一行像素由两条栅线控制与该像素对应的薄膜晶体管的栅极，其中，一条栅线控制奇数列的像素，而另一条栅线控制偶数列的像素。对于以一线点反转模式进行控制的具有“双栅线”结构的阵列基板而言，因为同一行上每条数据线两侧的像素的极性是正负交替排布的，受到数据线延迟的影响，会导致同一行上每条数据线两侧的像素的充电效果不一致，从而影响图像显示的质量。
图3是示出了具有二线点反转模式的阵列基板的示意图。如图3所示，施加至像素单元的电压在行方向上以一个像素单元为周期反转极性，并且在列方向上以两个像素单元为周期反转极性。然而，当二线点反转方式应用于图1所示的阵列基板时，会造成功耗增大的问题。
图4是示出了将二线点反转模式应用于图1所示的阵列基板时的示意图。如图4所示，连接至同一数据线的像素单元包括了正极性和负极性两种极性的像素单元，因此需要在同一帧内，使得同一数据线上的输出信号的极性多次反转，从而大大增加功耗。
应当认识到，图3所示的二线点反转模式是以单栅线结构的阵列基板为例示出的。图3所示的二线点反转模式也可以应用于图2所示的双栅线结构的阵列基板。图5是示出了将二线点反转模式应用于图2所示的阵列基板时的示意图。
与图4所示的应用了二线点反转模式的单栅线结构的阵列基板类似，图5所示的应用了二线点反转的双栅线结构的阵列基板同样需要在同一帧内，使得同一数据线上的输出信号的极性多次反转，从而大大增加功耗。
图6是示出了根据本发明一个实施例的阵列基板的示意图。
参照图6，根据本发明一个实施例的阵列基板包括在第一方向(例如，行方向)上延伸的多条栅线Gn至Gn+5、在与第一方向交叉的第二方向(例如，列方向)上延伸的多条数据线Dn至Dn+7以及沿第一方向和第二方向排列为阵列的多个像素单元。
参照图6，每条数据线设置在在第二方向上延伸并且在第一方向上相邻的两列像素单元之间，并且连接至位于该条数据线一侧的像素单元或者连接至位于另一侧的像素单元。例如，数据线Dn+3设置在在列方向上延伸并且在行方向上相邻的两列像素单元之间，并且数据线Dn+3连接至位于其左侧或者右侧的像素单元。
参照图6，数据线以在第二方向上相邻的两行像素单元为周期将连接方向从其一侧切换至其另一侧，并且各条数据线在同一行像素单元的连接方向相同。例如，如图6中的虚线所示，数据线Dn+3在栅线Gn和Gn+1所对应的行连接至位于其右侧的像素单元，在栅线Gn+2和Gn+3所对应的行连接至位于其左侧的像素单元，并且在栅线Gn+4和Gn+5所对应的行再次连接至位于其右侧的像素单元。各条数据线Dn至Dn+7在同一行像素单元(例如，各条栅线Gn至Gn+5所分别对应的各行像素单元)的连接方向相同。
如图6所示，每个像素单元可以包括像素电极和薄膜晶体管。像素电极连接至薄膜晶体管的漏极，各条栅线Gn至Gn+5分别通过薄膜晶体 管的栅极连接至对应的各行像素单元，并且各条数据线Dn至Dn+7分别通过薄膜晶体管的源极连接至对应的像素单元。
虽然在图6中示出了每条栅线对应于在第一方向(例如，行方向)上延伸的一行像素单元，但本发明不限于此。
图7是示出了根据本发明另一个实施例的阵列基板的示意图。图7示出了具有“双栅线”结构的阵列基板。因此，在图7所示的阵列基板中，每个像素单元包括了在同一行中两个相邻的像素。
如图7所示，每两条栅线对应于在第一方向(例如，行方向)上延伸的一行像素单元，并且分别设置在该行像素单元在第二方向(例如，列方向)上的两侧。
如上所述，对于以一线点反转模式进行控制的具有“双栅线”结构的阵列基板而言，因为同一行上每条数据线两侧的像素的极性是正负交替排布的，受到数据线延迟的影响，会导致同一行上每条数据线两侧的像素的充电效果不一致，从而影响图像显示的质量。采用二线点反转模式可以有效地改善这种现象。因此，根据本发明的具有二线点反转模式的阵列基板对于具有“双栅线”结构的阵列基板特别有利。
如图7所示，每个像素单元包括(对应于两个像素的)第一像素电极和第二像素电极，以及分别与第一像素电极和第二像素电极对应的第一薄膜晶体管和第二薄膜晶体管，第一像素电极和第二像素电极分别连接至第一薄膜晶体管和第二薄膜晶体管各自的漏极。
与一行像素单元对应的两条栅线分别连接至该行像素单元中的第一薄膜晶体管和第二薄膜晶体管各自的栅极。例如，与图7所示的第三行像素单元对应的栅线Gn-1和Gn分别连接至该行像素单元中的第一薄膜晶体管和第二薄膜晶体管各自的栅极。
数据线通过第一薄膜晶体管和第二薄膜晶体管各自的源极连接至对应的像素单元。例如，如图7中的虚线所示，数据线Dn通过各个第一薄膜晶体管和第二薄膜晶体管各自的源极向右连接至栅线Gn-5和Gn-4所对应的第一行像素单元以及栅线Gn-3和Gn-2所对应的第二行像素单元、向左连接至栅线Gn-1和Gn所对应的第三行像素单元以及栅线Gn+1和Gn+2所对应的第四行像素单元、并且再次向右连接至栅线Gn+3和Gn+4所对应的第五行像素单元以及栅线Gn+5和Gn+6所对应的第六行像素单元。
如图7所示，与一行像素单元对应的两条栅线中的一条栅线连接至该行像素单元中的各个第一薄膜晶体管的栅极，并且与一行像素单元对应的两条栅线中的另一条栅线连接至该行像素单元中的各个第二薄膜晶体管的栅极。例如，与图7所示的第三行像素单元对应的栅线Gn-1连接至该行各个像素单元中的第一薄膜晶体管的栅极，而与图7所示的第三行像素单元对应的栅线Gn连接至该行各个像素单元中的第二薄膜晶体管的栅极。
根据本发明的实施例，提供一种用于驱动根据本发明的阵列基板的方法。
如图4和图5所示，当将二线点反转方式应用于图1和图2所示的现有技术的阵列基板时，连接至同一数据线的像素单元包括了正极性和负极性两种极性的像素单元，因此需要在同一帧内使得同一数据线上的输出信号的极性多次反转，从而大大增加功耗。
与之不同，当将二线点反转方式应用于根据本发明的阵列基板时，连接至同一数据线的像素单元均为极性相同的像素单元，如图6和图7所示。因此，在驱动根据本发明的阵列基板时，每条数据线上的输出信号的极性在同一帧内保持不变，并且在第一方向(例如，行方向)上相邻的两条数据线上的输出信号的极性相反。例如，如图6所示，在第N帧时，数据线Dn上的输出信号的极性为正并且保持不变，并且数据线Dn+1上的输出信号的极性为负并且保持不变。以此类推，直至数据线Dn+6上的输出信号的极性为正并且保持不变，并且数据线Dn+7上的输出信号的极性为负并且保持不变。此外，在第N+1帧时(图中未示出)，各条数据线上的输出信号的极性反转。数据线Dn上的输出信号的极性为负并且保持不变，并且数据线Dn+1上的输出信号的极性为正并且保持不变。以此类推，直至数据线Dn+6上的输出信号的极性为负并且保持不变，并且数据线Dn+7上的输出信号的极性为正并且保持不变。
根据本发明的驱动方法，在同一帧内，同一数据线上的输出信号极性相同，并且仅在各帧之间使得数据线上的输出信号的极性反转一次，从而可以大大降低功耗。
虽然在图6和图7的实施例中仅示出了6行×8列的像素单元的阵列基板以及与其对应的数据线和栅线，但本发明不限于此。根据本发明 构思的阵列基板可以根据需要包括更多行和/或更多列的像素单元以及与其对应的数据线和栅线。
虽然已经根据示例性实施例描述了结构、方法和系统，但是本领域普通技术人员应该容易认识到，许多对公开的实施例的修改都是可以的，并且因此，任何变形形式应该被认为落入本文公开的设备、方法和系统的精神和范围内。因此，本领域普通技术人员可在不脱离权利要求的精神和范围的情况下作出许多修改。

Claims (12)

  1. 一种阵列基板，包括在第一方向上延伸的多条栅线、在与第一方向交叉的第二方向上延伸的多条数据线以及沿第一方向和第二方向排列为阵列的多个像素单元，
    每条数据线设置在在第二方向上延伸并且在第一方向上相邻的两列像素单元之间，并且连接至位于该条数据线一侧的像素单元或者连接至位于另一侧的像素单元，
    其中，数据线以在第二方向上相邻的两行像素单元为周期将连接方向从其一侧切换至其另一侧，并且各条数据线在同一行像素单元的连接方向相同。
  2. 根据权利要求1所述的阵列基板，其中，每条栅线对应于在第一方向上延伸的一行像素单元。
  3. 根据权利要求2所述的阵列基板，其中，每个像素单元包括像素电极和薄膜晶体管，像素电极连接至薄膜晶体管的漏极，栅线通过薄膜晶体管的栅极连接至对应的像素单元，并且数据线通过薄膜晶体管的源极连接至对应的像素单元。
  4. 根据权利要求1所述的阵列基板，其中，每两条栅线对应于在第一方向上延伸的一行像素单元，并且分别设置在该行像素单元在第二方向上的两侧。
  5. 根据权利要求4所述的阵列基板，其中，每个像素单元包括第一像素电极和第二像素电极，以及分别与第一像素电极和第二像素电极对应的第一薄膜晶体管和第二薄膜晶体管，第一像素电极和第二像素电极分别连接至第一薄膜晶体管和第二薄膜晶体管各自的漏极，
    与一行像素单元对应的两条栅线分别连接至该行像素单元中的第一薄膜晶体管和第二薄膜晶体管各自的栅极，并且
    数据线通过第一薄膜晶体管和第二薄膜晶体管各自的源极连接至对应的像素单元。
  6. 根据权利要求5所述的阵列基板，其中，第一像素电极和第二像素电极沿第一方向设置在像素单元中。
  7. 根据权利要求5所述的阵列基板，其中，与一行像素单元对应的两条栅线中的一条栅线连接至该行像素单元中的各个第一薄膜晶体管 的栅极，并且与一行像素单元对应的两条栅线中的另一条栅线连接至该行像素单元中的各个第二薄膜晶体管的栅极。
  8. 根据权利要求1所述的阵列基板，其中，每条数据线上的输出信号的极性在同一帧内保持不变，并且在第一方向上相邻的两条数据线上的输出信号的极性相反。
  9. 根据权利要求8所述的阵列基板，其中，每条数据线上的输出信号的极性在相邻两帧之间反转一次。
  10. 一种显示装置，包括根据权利要求1-8中任一项所述的阵列基板。
  11. 一种驱动如权利要求1所述的阵列基板的方法，包括：
    每条数据线上的输出信号的极性在同一帧内保持不变，并且在第一方向上相邻的两条数据线上的输出信号的极性相反，使得施加至像素单元的电压在第一方向上以一个像素单元为周期反转极性，并且在第二方向上以两个像素单元为周期反转极性。
  12. 根据权利要求11所述的方法，其中，每条数据线上的输出信号的极性在相邻两帧之间反转一次。
PCT/CN2016/072123 2015-08-28 2016-01-26 阵列基板、显示装置及其驱动方法 Ceased WO2017036081A1 (zh)

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