WO2017041684A1 - 开关电源及其初级控制芯片和环路补偿装置 - Google Patents

开关电源及其初级控制芯片和环路补偿装置 Download PDF

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Publication number
WO2017041684A1
WO2017041684A1 PCT/CN2016/098124 CN2016098124W WO2017041684A1 WO 2017041684 A1 WO2017041684 A1 WO 2017041684A1 CN 2016098124 W CN2016098124 W CN 2016098124W WO 2017041684 A1 WO2017041684 A1 WO 2017041684A1
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Prior art keywords
power supply
loop compensation
output
switch
gate
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English (en)
French (fr)
Inventor
王文情
侯永军
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BYD Co Ltd
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BYD Co Ltd
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Priority to US15/756,330 priority Critical patent/US10389225B2/en
Priority to EP16843622.8A priority patent/EP3349342A4/en
Publication of WO2017041684A1 publication Critical patent/WO2017041684A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/14—Arrangements for reducing ripples from DC input or output
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
    • H02M1/4208—Arrangements for improving power factor of AC input
    • H02M1/4258—Arrangements for improving power factor of AC input using a single converter stage both for correction of AC input power factor and generation of a regulated and galvanically isolated DC output voltage
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
    • H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
    • H02M3/10—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/22—Conversion of DC power input into DC power output with intermediate conversion into AC
    • H02M3/24—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters
    • H02M3/28—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC
    • H02M3/325—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33507—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters
    • H02M3/33523—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters with galvanic isolation between input and output of both the power stage and the feedback loop
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0025—Arrangements for modifying reference values, feedback values or error values in the control loop of a converter

Definitions

  • the present invention relates to the field of charging power supply technologies, and in particular, to a loop compensation device for a switching power supply, a primary control chip having the loop compensation device, and a switching power supply.
  • FIG. 1 a typical flyback switching power supply application circuit diagram is shown in FIG. 1 , and feedback sampling of the output is usually implemented in the form of transformer auxiliary winding sampling feedback.
  • Figure 2 is a block diagram of the structure of the primary control chip in a typical switching power supply.
  • the constant voltage implementation of the system is to perform secondary voltage sampling through the auxiliary winding and provide the sampled output voltage to the error amplifier input, and perform error amplification with the reference voltage to finally realize the conduction to the external power switch. Pass time and working frequency control.
  • the compensation of the loop is mainly achieved by adding a compensation capacitor Cea at the output of the error amplifier.
  • this compensation method causes a problem that the loop cannot be stabilized and the output ripple is too large in the light load to no-load range.
  • the present invention aims to solve at least one of the technical problems in the related art to some extent.
  • the first object of the present invention is to provide a loop compensation device for a switching power supply, which solves the problem of large ripple of the output of the system by controlling the output of the error amplifier to ensure loop stability.
  • a second object of the present invention is to provide a primary control chip for a switching power supply.
  • a third object of the present invention is to provide a switching power supply.
  • a loop compensation apparatus for a switching power supply includes: an error amplifier, a first input end of the error amplifier and a primary control chip of the switching power supply An output of the sample-and-hold circuit is coupled, the second input of the error amplifier being coupled to the first reference voltage reference, wherein the error amplifier is configured to reference the sample-and-hold signal and the first reference voltage according to the sample-and-hold circuit a first reference voltage signal of the terminal to obtain an error amplification signal; a switching logic gate, an input end of the switching logic gate is connected to an output end of the error amplifier; a loop compensation capacitor, one end of the loop compensation capacitor and the Output phase of the switching logic gate Connecting, the other end of the loop compensation capacitor is grounded; a delay generating circuit, an output end of the delay generating circuit is connected to a control end of the switching logic gate, and the delay generating circuit is used in the switch Outputting an effective switch control signal within a preset time after the power switch of the power source
  • a loop compensation apparatus for a switching power supply by adding a switching logic gate at an output end of the error amplifier and controlling a delay generating circuit of the switching logic gate, such that the delay generating circuit is turned off after the power switching transistor is turned off
  • the effective switching control signal is output during the preset time to control the switching logic gate to be in an open state, so that the error amplification signal outputted by the error amplifier charges and discharges the loop compensation capacitor, so that the switching power supply realizes loop compensation, thereby outputting the error amplifier
  • the signal is controlled by a switching logic gate.
  • a second aspect of the present invention provides a primary control chip for a switching power supply including the above-described loop compensation device for a switching power supply.
  • the output signal of the error amplifier can be controlled by the switching logic gate, that is, the output of the error amplifier is only a short time after the power switch is turned off, that is, the output of the error amplifier.
  • the circuit compensation capacitor is charged and discharged to realize loop compensation, so that the loop stability under the condition of light and no-load of the switching power supply can be ensured, and the device can be ensured at a very low frequency without affecting the higher frequency operation of the switching power supply.
  • the output of the error amplifier can accurately reflect the actual situation of the secondary output voltage, solve the problem of large ripple of the switching power supply output, and ensure the loop stability.
  • embodiments of the present invention also provide a switching power supply that includes the primary control chip of the switching power supply described above.
  • the switching power supply of the embodiment of the invention can ensure the loop stability under light and no-load conditions, and can ensure that the output of the error amplifier can reflect the secondary in a very low frequency condition without affecting the operation of the higher frequency.
  • the actual situation of the output voltage solves the problem of large output ripple and ensures loop stability.
  • FIG. 1 is a circuit diagram of a typical flyback switching power supply application in the related art
  • FIG. 2 is a structural block diagram of a primary control chip of a switching power supply in the related art
  • FIG. 3 is a working waveform diagram of a typical flyback switching power supply in the related art
  • FIG. 4 is a block diagram of a loop compensation device for a switching power supply according to an embodiment of the present invention.
  • FIG. 5 is a circuit diagram of a loop compensation device for a switching power supply according to an embodiment of the present invention.
  • FIG. 6 is a circuit diagram of a loop compensation device for a switching power supply according to another embodiment of the present invention.
  • Figure 7 is a diagram showing the operation waveforms of a switching power supply according to an embodiment of the present invention.
  • the sampling method using the auxiliary winding of the transformer is intermittent sampling, that is, after the power switch tube is turned off, the voltage inside the auxiliary winding is sampled by the primary control chip, and the voltage on the auxiliary winding is only in the secondary degaussing time TDS.
  • the primary control chip can only sample the output voltage in the secondary degaussing time, while the feedback input of the error amplifier outside the sampling time will be maintained by the sample-and-hold circuit, that is, the error amplifier cannot track the output voltage in real time. The change.
  • the secondary degaussing time TDS (NS/NP) ⁇ (1/Vout) ⁇ Lp ⁇ Ip, where NS/NP is the secondary/primary turns ratio, Vout is the output voltage, and Lp is the primary inductance. Ip is the primary peak current.
  • the operating frequency of the system is generally low, and the primary peak current is relatively small.
  • the secondary degaussing time that is, the sampling time is very small relative to the working period of the system, which may cause the error amplifier to change.
  • the loop Far from keeping up with the rate of change of the output voltage, the loop will be difficult to stabilize, and the instability of the loop will introduce low frequency ripple, resulting in a large output ripple of the system.
  • the specific waveform is shown in Figure 3.
  • a loop compensation device for a switching power supply, a primary control chip and a switching power supply of a switching power supply having the loop compensation device according to an embodiment of the present invention will be described below with reference to the accompanying drawings.
  • a loop compensation apparatus for a switching power supply includes an error amplifier 10, a switching logic gate 20, a loop compensation capacitor Cea, and a delay generating circuit 30.
  • the first input end of the error amplifier 10 is connected to the output end of the sample and hold circuit, and the second input end of the error amplifier 10 is connected to the first reference voltage reference end, wherein the sample and hold circuit is used for the primary control chip in the switching power supply.
  • the output feedback terminal voltage is sample-and-hold, and the sample-and-hold signal VSH is output through its output terminal, the first reference voltage reference terminal provides a first reference voltage signal Vref, and the error amplifier 10 is used for sampling and holding according to the sample-and-hold circuit.
  • the signal VSH and the first reference voltage signal Vref of the first reference voltage reference end obtain the error amplification signal VEA, that is, the output feedback terminal voltage of the primary control chip in the switching power supply is sampled and held by the sample and hold circuit to obtain the sample and hold signal VSH.
  • the error amplifier 10 amplifies and outputs an error amount of the sample hold signal VSH and the first reference voltage signal Vref to be supplied to the back end constant voltage constant current control module to control The operating frequency and duty cycle of the power switch tube to control the switching power supply Voltage.
  • the input of the switching logic gate 20 is connected to the output of the error amplifier 10, one end of the loop compensation capacitor Cea is connected to the output of the switching logic gate 20, and the other end of the loop compensation capacitor Cea is grounded.
  • the output of the delay generating circuit 30 is The control terminal of the switch logic gate 20 is connected, and the delay generating circuit 30 is configured to output a valid switch control signal, for example, CT is "1", to control the switch logic gate 20 to be turned on within a preset time after the power switch of the switching power supply is turned off.
  • CT is "1”
  • the delay generating circuit 30 is further configured to output an invalid switch control signal, for example, CT is “0” outside the preset time after the power switch is turned off to control the switch logic gate 20 to be in an off state, so that the loop compensation capacitor is The charge and discharge path of Cea is turned off, and the output voltage of the error amplifier 10 is maintained, that is, the output voltage of the error amplifier 10 is the voltage of the error amplification signal VEA output from the error amplifier 10.
  • an invalid switch control signal for example, CT is “0” outside the preset time after the power switch is turned off to control the switch logic gate 20 to be in an off state, so that the loop compensation capacitor is The charge and discharge path of Cea is turned off, and the output voltage of the error amplifier 10 is maintained, that is, the output voltage of the error amplifier 10 is the voltage of the error amplification signal VEA output from the error amplifier 10.
  • the delay generating circuit 30 is mainly used to generate a periodic switching control signal CT, which is valid at the beginning of the cycle (the power switch is turned off), and the power switch is turned off. After a delay, the preset time and then jump to become invalid.
  • the switch control signal CT controls the switch logic gate 20 connected to the output terminal of the error amplifier 10.
  • the output VEA of the error amplifier 10 is connected to the loop compensation capacitor Cea during the effective time of the switch control signal CT, and the output voltage feedback of the error amplifier 10 is output.
  • the sample-and-hold signal VSH is compared and amplified with the first reference voltage signal Vref.
  • the switch control signal CT is outside the valid time (the CT is valid within the preset time after the power switch is turned off, that is, the period from the start of the power switch to the end of the preset time is the effective time, and the rest of the time is invalid), then the error amplifier 10 The output terminal is disconnected from the loop compensation capacitor Cea.
  • the circuit of the latter stage in the primary control chip such as a constant current constant voltage control module (ie, a pulse width modulation PWM & pulse frequency modulation PFM circuit), a logic control module, and an output drive module control the operation of the entire switching power supply according to the voltage of the loop compensation capacitor Cea. Frequency and power switch tube conduction time.
  • the delay generating circuit 30 generates an effective switching control signal under the control of the trigger signal SIN, wherein the trigger signal SIN may be an off signal of the power switch.
  • the SIN is a trigger signal of the CT, and is used to generate a start signal of the CT effective time. Since the CT delays and then becomes inactive after the power switch is turned off for a period of time, the trigger signal SIN of the delay generating circuit 30 is generated. Generally, it is the turn-off signal of the power switch tube.
  • the SIN can also be the turn-on signal or the degaussing signal of the power switch tube, such as the power switch in FIG.
  • the switch logic gate 20 specifically includes: The first inverter inv1, the first switching transistor M1 and the second switching transistor M2, the input end of the first inverter inv1 is connected to the output end of the delay generating circuit 30, the first end of the first switching transistor M1 and the first The first end of the second switch M2 is connected to the output end of the error amplifier 10, the second end of the first switch M1 is connected to the output end of the delay generating circuit 30, and the second end of the second switch M2 is The output end of the inverter inv1 is connected, and the third end of the first switch M1 and the third end of the second switch M2 are connected as the output end of the switch logic gate 20.
  • the first switch tube M1 and the second switch tube M2 are both MOS tubes.
  • the delay generating circuit 30 specifically includes: a first NMOS transistor MN1, a first capacitor C1, a Schmitt trigger 301, a first NOR gate nor1, and a second inverter inv2.
  • the gate of the first NMOS transistor MN1 serves as a trigger terminal of the delay generating circuit 30 to receive the trigger signal SIN, the drain of the first NMOS transistor MN1 is connected to the first current source I1, and the source of the first NMOS transistor MN1 is grounded;
  • a capacitor C1 is connected in parallel between the drain and the source of the first NMOS transistor MN1, and the input end of the Schmitt trigger 301 is connected to the drain of the first NMOS transistor MN1, and the first input terminal of the first NOR gate nor1 Connected to the output of the Schmitt trigger 301, the second input of the first NOR gate nor1 is connected to the gate of the first NMOS transistor MN1; the input of the second inverter inv2 is connected to the first NOR gate nor1
  • the delay generating circuit 30 specifically includes: a second NMOS transistor MN2, a second capacitor C2, a comparator 302, a second NOR gate nor2, and a third inverter. Inv3.
  • the gate of the second NMOS transistor MN2 serves as a trigger terminal of the delay generating circuit 30 to receive the trigger signal SIN, the drain of the second NMOS transistor MN2 is connected to the second current source I2, and the source of the second NMOS transistor MN2 is grounded;
  • the second capacitor C2 is connected in parallel between the drain and the source of the second NMOS transistor MN2, and the negative input terminal of the comparator 302 is connected to the drain of the second NMOS transistor MN2.
  • the gate of the second NMOS transistor MN2 is connected; the input terminal of the third inverter inv3 is connected to the output terminal of the second NOR gate nor2, and the output terminal of the third inverter inv3 serves as the output terminal of the delay generating circuit 30.
  • the secondary degaussing signal TDS as the trigger signal SIN as an example
  • the MN1 in the delay generating circuit 30 is turned on
  • the TDS is from '1' to '0'.
  • the preset time is determined according to the capacitance value of the first capacitor C1 and the current amplitude of the first current source I1, and the preset time and the capacitance of the first capacitor There is a positive correlation, and the preset time is inversely related to the current amplitude of the first current source.
  • FIG. 6 is another circuit implementation of a loop compensation apparatus for a switching power supply according to an embodiment of the present invention, in which a comparator 302 is used instead of the Schmitt trigger 301 of FIG.
  • a comparator 302 is used instead of the Schmitt trigger 301 of FIG.
  • VEA can follow the change of output voltage, which effectively promotes the stability of the switching power supply loop.
  • a loop compensation apparatus for a switching power supply by adding a switching logic gate at an output end of the error amplifier and controlling a delay generating circuit of the switching logic gate, such that the delay generating circuit is turned off after the power switching transistor is turned off
  • the effective switching control signal is output during the preset time to control the switching logic gate to be in an open state, so that the error amplification signal outputted by the error amplifier charges and discharges the loop compensation capacitor, so that the switching power supply realizes loop compensation, thereby outputting the error amplifier
  • the signal is controlled by the switching logic gate, that is, the loop compensation capacitor is charged and discharged only for a short period of time after the power switch is turned off, that is, the output of the error amplifier is preset to achieve loop compensation.
  • the loop compensation device for the switching power supply of the embodiment of the present invention is mainly for the loop stability under light and empty load conditions, and ensures that at a very low frequency, without affecting the higher frequency operation of the switching power supply.
  • the output of the error amplifier can accurately reflect the actual situation of the secondary output voltage, thereby solving the problem that the output ripple of the switching power supply is too large, and ensuring loop stability.
  • an embodiment of the present invention proposes a primary control chip for a switching power supply including the above-described loop compensation device for a switching power supply.
  • the output signal of the error amplifier can be controlled by the switching logic gate, that is, the output of the error amplifier is only a short time after the power switch is turned off, that is, the output of the error amplifier.
  • the circuit compensation capacitor is charged and discharged to realize loop compensation, so that the loop stability under the condition of light and no-load of the switching power supply can be ensured, and the device can be ensured at a very low frequency without affecting the higher frequency operation of the switching power supply.
  • the output of the error amplifier can accurately reflect the actual situation of the secondary output voltage, and solve the problem that the output ripple of the switching power supply is too large.
  • the test loop is stable.
  • embodiments of the present invention also provide a switching power supply that includes the primary control chip of the switching power supply described above.
  • the switching power supply of the embodiment of the invention can ensure the loop stability under light and no-load conditions, and can ensure that the output of the error amplifier can reflect the secondary in a very low frequency condition without affecting the operation of the higher frequency.
  • the actual situation of the output voltage solves the problem of large output ripple and ensures loop stability.
  • first and second are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated.
  • features defining “first” or “second” may include at least one of the features, either explicitly or implicitly.
  • the meaning of "a plurality” is at least two, such as two, three, etc., unless specifically defined otherwise.
  • the terms “installation”, “connected”, “connected”, “fixed” and the like shall be understood broadly, and may be either a fixed connection or a detachable connection, unless explicitly stated and defined otherwise. , or integrated; can be mechanical or electrical connection; can be directly connected, or indirectly connected through an intermediate medium, can be the internal communication of two elements or the interaction of two elements, unless otherwise specified Limited.
  • the specific meanings of the above terms in the present invention can be understood on a case-by-case basis.
  • the first feature "on” or “under” the second feature may be a direct contact of the first and second features, or the first and second features may be indirectly through an intermediate medium, unless otherwise explicitly stated and defined. contact.
  • the first feature "above”, “above” and “above” the second feature may be that the first feature is directly above or above the second feature, or merely that the first feature level is higher than the second feature.
  • the first feature “below”, “below” and “below” the second feature may be that the first feature is directly below or obliquely below the second feature, or merely that the first feature level is less than the second feature.

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Abstract

一种开关电源及其初级控制芯片和环路补偿装置，其中，环路补偿装置包括：误差放大器（10）；开关逻辑门（20），开关逻辑门（20）的输入端与误差放大器（10）的输出端相连；环路补偿电容（Cea），环路补偿电容（Cea）的一端与开关逻辑门（20）的输出端相连，环路补偿电容（Cea）的另一端接地；延时产生电路（30），延时产生电路（30）的输出端与开关逻辑门（20）的控制端相连，延时产生电路（30）用于在开关电源的功率开关管关断后的预设时间内输出有效开关控制信号以控制开关逻辑门（20）处于开通状态，以使误差放大器（10）输出的误差放大信号对环路补偿电容（Cea）进行充放电，该环路补偿装置能够解决开关电源输出纹波偏大的问题，保证环路稳定。

Description

开关电源及其初级控制芯片和环路补偿装置
相关申请的交叉引用
本申请要求中国专利申请号201510562897.1、申请日为2015年9月7日的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本发明涉及充电电源技术领域，特别涉及一种用于开关电源的环路补偿装置、一种具有该环路补偿装置的初级控制芯片以及一种开关电源。
背景技术
相关技术中，典型的反激式开关电源应用线路图如图1所示，通常采用变压器辅助绕组采样反馈的形式实现对输出的反馈采样。其中，图2为典型的开关电源中初级控制芯片的结构框图。
结合图1和图2，系统的恒压实现是通过辅助绕组进行次级电压采样并将采样到的输出电压提供给误差放大器输入，与基准电压进行误差放大，最终实现对外部功率开关管的导通时间与工作频率控制。而环路的补偿主要通过在误差放大器的输出端加补偿电容Cea来实现。但是，该补偿方式会带来在轻载到空载范围内环路无法稳定而导致输出纹波偏大的问题。
发明内容
本发明旨在至少在一定程度上解决相关技术中的技术问题之一。为此，本发明的第一个目的在于提出一种用于开关电源的环路补偿装置，通过对误差放大器的输出进行控制，解决系统输出纹波偏大的问题，保证环路稳定。
本发明的第二个目的在于提出一种开关电源的初级控制芯片。本发明的第三个目的在于提出一种开关电源。
为达到上述目的，本发明第一方面实施例提出的一种用于开关电源的环路补偿装置，包括：误差放大器,所述误差放大器的第一输入端与所述开关电源中初级控制芯片的采样保持电路的输出端相连，所述误差放大器的第二输入端与第一基准电压参考端相连，其中,所述误差放大器用于根据所述采样保持电路的采样保持信号和第一基准电压参考端的第一基准电压信号,得到误差放大信号；开关逻辑门，所述开关逻辑门的输入端与所述误差放大器的输出端相连；环路补偿电容，所述环路补偿电容的一端与所述开关逻辑门的输出端相 连，所述环路补偿电容的另一端接地；延时产生电路，所述延时产生电路的输出端与所述开关逻辑门的控制端相连，所述延时产生电路用于在所述开关电源的功率开关管关断后的预设时间内输出有效开关控制信号以控制所述开关逻辑门处于开通状态，以使所述误差放大器输出的误差放大信号对所述环路补偿电容进行充放电。
根据本发明实施例的用于开关电源的环路补偿装置，通过在误差放大器的输出端增加开关逻辑门以及控制开关逻辑门的延时产生电路，这样延时产生电路在功率开关管关断后的预设时间内输出有效开关控制信号以控制开关逻辑门处于开通状态，这样误差放大器输出的误差放大信号对环路补偿电容进行充放电，使得开关电源实现环路补偿，从而对误差放大器的输出信号通过开关逻辑门控制。
为达到上述目的，本发明第二方面实施例提出了一种开关电源的初级控制芯片，其包括上述的用于开关电源的环路补偿装置。
根据本发明实施例的开关电源的初级控制芯片，能够对误差放大器的输出信号通过开关逻辑门控制，即只在功率开关管关断后的一小段时间即预设时间内误差放大器的输出对环路补偿电容进行充放电，实现环路补偿，从而可针对开关电源轻空载情况下的环路稳定性，并在不影响开关电源较高频工作的前提下确保在很低频的情况下，使得误差放大器的输出能够比较真实反映次级输出电压的实际情况，解决开关电源输出纹波偏大的问题，保证环路稳定。
此外，本发明的实施例还提出了一种开关电源，其包括上述的开关电源的初级控制芯片。
本发明实施例的开关电源，针对轻空载情况下的环路稳定性，可在不影响较高频工作的前提下确保在很低频的情况下，使得误差放大器的输出能够比较真实反映次级输出电压的实际情况，解决输出纹波偏大的问题，保证环路稳定。
附图说明
图1为相关技术中一种典型的反激式开关电源应用线路图；
图2为相关技术中一种开关电源的初级控制芯片的结构框图；
图3为相关技术中一种典型的反激式开关电源的工作波形图；
图4为根据本发明一个实施例的用于开关电源的环路补偿装置的结框图；
图5为根据本发明一个具体实施例的用于开关电源的环路补偿装置的电路示意图；
图6为根据本发明另一个具体实施例的用于开关电源的环路补偿装置的电路示意图；以及
图7为根据本发明一个实施例的开关电源的工作波形图。
具体实施方式
下面详细描述本发明的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，旨在用于解释本发明，而不能理解为对本发明的限制。
本申请是基于发明人对以下问题的认识和研究作出的：
相关技术中，采用变压器辅助绕组采样的方式为间歇式采样，即功率开关管关断后，初级控制芯片内部通过对辅助绕组上电压进行采样，而辅助绕组上电压只有在次级消磁时间TDS内才能反映输出电压情况，因此初级控制芯片对输出电压的采样也只能在次级消磁时间内，而采样时间外误差放大器的反馈输入通过采样保持电路将保持，即误差放大器无法实时地跟踪输出电压的变化。其中，次级消磁时间TDS＝(NS/NP)·(1/Vout)·Lp·Ip，式中，NS/NP为次级/初级匝数比，Vout为输出电压，Lp为初级电感量，Ip为初级峰值电流。
在轻载到空载范围内，系统的工作频率一般都比较低，同时初级峰值电流比较小，此时次级消磁时间即采样时间相对于系统的工作周期非常小，从而会导致误差放大器的变化远远跟不上输出电压的变化速度，因此环路将很难稳定，而环路的不稳将引入低频纹波，导致系统的输出纹波偏大，具体波形如图3所示。
下面参照附图来描述根据本发明实施例提出的用于开关电源的环路补偿装置、具有该环路补偿装置的开关电源的初级控制芯片和开关电源。
如图4所示，根据本发明一个实施例提出的用于开关电源的环路补偿装置，包括：误差放大器10、开关逻辑门20、环路补偿电容Cea和延时产生电路30。
其中，误差放大器10的第一输入端与采样保持电路的输出端相连，误差放大器10的第二输入端与第一基准电压参考端相连，其中，采样保持电路用于对开关电源中初级控制芯片的输出反馈端电压进行采样保持，并通过其输出端输出采样保持信号VSH，第一基准电压参考端提供第一基准电压信号Vref,所述误差放大器10用于根据所述采样保持电路的采样保持信号VSH和第一基准电压参考端的第一基准电压信号Vref,得到误差放大信号VEA,也就是说,开关电源中初级控制芯片的输出反馈端电压经过采样保持电路的采样保持后得到采样保持信号VSH，通过误差放大器10与给定的基准电压做比较，误差放大器10将采样保持信号VSH与第一基准电压信号Vref的误差量进行放大并输出以提供给后端的恒压恒流控制模块，以控制功率开关管的工作频率与占空比，从而控制开关电源的输出电压。开关逻辑门20的输入端与误差放大器10的输出端相连，环路补偿电容Cea的一端与开关逻辑门20的输出端相连，环路补偿电容Cea的另一端接地。延时产生电路30的输出端与 开关逻辑门20的控制端相连，延时产生电路30用于在开关电源的功率开关管关断后的预设时间内输出有效开关控制信号例如CT为“1”以控制开关逻辑门20处于开通状态，以使误差放大器10输出的误差放大信号VEA对环路补偿电容Cea进行充放电，以实现开关电源进行环路补偿。
并且，延时产生电路30还用于在功率开关管关断后的预设时间外输出无效开关控制信号例如CT为“0”以控制开关逻辑门20处于断开状态，以使环路补偿电容Cea的充放电通路断开，误差放大器10的输出电压被保持,即此时误差放大器10的输出电压为误差放大器10输出的误差放大信号VEA的电压。
也就是说，在本发明的实施例中，延时产生电路30主要用于产生一个周期性的开关控制信号CT，CT在周期的开始(功率开关管关断)为有效，功率开关管关断后延时一段时间即预设时间再跳变成无效。开关控制信号CT对误差放大器10的输出端所接的开关逻辑门20进行控制，开关控制信号CT有效时间内误差放大器10的输出VEA接到环路补偿电容Cea上，误差放大器10对输出电压反馈的采样保持信号VSH与第一基准电压信号Vref进行比较放大，当VSH>Vref，则误差放大器10将对环路补偿电容Cea进行放电，环路补偿电容Cea上的电压下降；反之当VSH<Vref，则误差放大器10对环路补偿电容Cea进行充电，环路补偿电容Cea上的电压上升,另外当VSH＝Vref时，误差放大器10保持输出误差放大信号VEA的电压。开关控制信号CT有效时间外(功率开关管关断后的预设时间内CT有效即从功率开关管关断开始到预设时间结束的时段为有效时间，其余时间无效)，则误差放大器10的输出端与环路补偿电容Cea断开，此时由于环路补偿电容Cea的充放电通路被断开，环路补偿电容Cea上的电压值将被保持直到下个CT有效时间的来临，由此实现在功率开关管关断一段时间后误差放大器10的输出电压被保持。初级控制芯片中的后级的电路例如恒流恒压控制模块(即脉冲宽度调制PWM&脉冲频率调制PFM电路)、逻辑控制模块和输出驱动模块根据环路补偿电容Cea的电压控制整个开关电源的工作频率和功率开关管导通时间。
根据本发明的一个实施例，延时产生电路30在触发信号SIN的控制下产生有效开关控制信号，其中，触发信号SIN可以为功率开关管的关断信号。具体而言，SIN为CT的触发信号，用于产生CT有效时间的开始信号，由于CT在功率开关管关断后延时一段时间再跳变成无效，因此延时产生电路30的触发信号SIN一般为功率开关管的关断信号。其中，考虑到功率开关管的开启时间或次级消磁时间TDS比较短，在CT的有效时间内可以忽略，因此SIN也可以为功率开关管的开启信号或消磁信号，比如图2中的功率开关管的开启信号ON、关断信号OFF、驱动信号DRI、逻辑控制信号PUL或次级消磁信号TDS。
具体而言，在本发明的一个实施例中，如图5或图6所示，开关逻辑门20具体包括： 第一反相器inv1、第一开关管M1和第二开关管M2，第一反相器inv1的输入端与延时产生电路30的输出端相连，第一开关管M1的第一端和第二开关管M2的第一端相连后与误差放大器10的输出端相连，第一开关管M1的第二端与延时产生电路30的输出端相连，第二开关管M2的第二端与第一反相器inv1的输出端相连，第一开关管M1的第三端和第二开关管M2的第三端相连后作为开关逻辑门20的输出端。其中，第一开关管M1和第二开关管M2均为MOS管。
如图5所示，延时产生电路30具体包括：第一NMOS管MN1、第一电容C1、施密特触发器301、第一或非门nor1和第二反相器inv2。第一NMOS管MN1的栅极作为延时产生电路30的触发端以接收触发信号SIN，第一NMOS管MN1的漏极与第一电流源I1相连，第一NMOS管MN1的源极接地；第一电容C1并联在第一NMOS管MN1的漏极与源极之间，施密特触发器301的输入端与第一NMOS管MN1的漏极相连，第一或非门nor1的第一输入端与施密特触发器301的输出端相连，第一或非门nor1的第二输入端与第一NMOS管MN1的栅极相连；第二反相器inv2的输入端与第一或非门nor1的输出端相连，第二反相器inv2的输出端作为延时产生电路30的输出端。
根据本发明的另一个实施例，如图6所示，延时产生电路30具体包括：第二NMOS管MN2、第二电容C2、比较器302、第二或非门nor2和第三反相器inv3。第二NMOS管MN2的栅极作为延时产生电路30的触发端以接收触发信号SIN，第二NMOS管MN2的漏极与第二电流源I2相连，第二NMOS管MN2的源极接地；第二电容C2并联在第二NMOS管MN2的漏极与源极之间，比较器302的负输入端与第二NMOS管MN2的漏极相连，比较器302的正输入端与第二基准电压参考端相连，第二基准电压参考端提供第二基准电压信号Vref2，第二或非门nor2的第一输入端与比较器302的输出端相连，第二或非门nor2的第二输入端与第二NMOS管MN2的栅极相连；第三反相器inv3的输入端与第二或非门nor2的输出端相连，第三反相器inv3的输出端作为延时产生电路30的输出端。
其中，以次级消磁信号TDS作为触发信号SIN为例，当功率开关管关断后次级开始消磁，此时TDS＝‘1’，此时延时产生电路30中MN1导通，对电容C1进行复位，电容C1上的电压VC1＝‘0’，于是施密特触发器301输出‘1’,此时或非门nor1输出为‘0’，CT＝‘1’；次级消磁结束后，TDS由‘1’到‘0’，由于此时施密特触发器301输出仍为‘1’，因此CT保持‘1’，TDS＝‘0’，第一电流源I1对电容C1进行充电，电容C1上电压逐渐上升，当电容C1上的电压VC1上升到施密特触发器输出翻转，此时输出CT＝‘0’。在本发明的一个实施例中，可以通过调整电容C1和第一电流源I1来调整CT＝‘1’的时间，电容越大，电流越小，则延时时间越长，即CT的有效时间越长，即言，预设时间根据所述第一电容C1的容值和所述第一电流源I1的电流幅值确定，并且所述预设时间与所述第一电容的容值之 间呈正相关关系，所述预设时间与所述第一电流源的电流幅值呈反相关关系。CT＝‘1’时，开关逻辑门20中的开关管M1、M2导通，此时误差放大器10的输出接到环路补偿电容Cea上，误差放大器10将对输入的采样保持信号VSH与第一基准电压信号Vref进行正常的比较放大；一旦CT＝‘0’，开关逻辑门20中的开关管M1、M2关断，则误差放大器10的输出与环路补偿电容Cea断开，使得环路补偿电容Cea充放电回路断开，而由于环路补偿电容Cea充放电回路断开，因此环路补偿电容Cea将保持之前的比较放大值，并且环路补偿电容Cea上的电压实现对后级电路进行控制。
图6是本发明实施例的用于开关电源的环路补偿装置的另一种电路实现方案，采用比较器302来替代图5中的施密特触发器301。其中，SIN＝‘1’时电容C2被复位，比较器302输出＝‘1’，此时CT＝‘1’,当SIN＝‘0’，第二电流源I2对电容C2充电，一旦电容C2上的电压VC2超过Vref2,则比较器302翻转，CT＝‘0’。同样CT＝‘1’时，误差放大器10的输出接到环路补偿电容Cea上，反之CT＝‘0’时，则误差放大器10的输出与环路补偿电容Cea断开，环路补偿电容Cea上电压被保持直到下一个SIN＝‘1’的到来。
具体地，如图7所示，在CT＝‘1’的时间内，VEA随着输入信号的变化而变化，而CT＝‘0’的时间内(一个周期之内CT＝‘1’以外的时间)VEA保持不变。与图3对比，在较低的频率下，VEA比较能跟随输出电压的变化，从而有效促进开关电源环路的稳定性。
根据本发明实施例的用于开关电源的环路补偿装置，通过在误差放大器的输出端增加开关逻辑门以及控制开关逻辑门的延时产生电路，这样延时产生电路在功率开关管关断后的预设时间内输出有效开关控制信号以控制开关逻辑门处于开通状态，这样误差放大器输出的误差放大信号对环路补偿电容进行充放电，使得开关电源实现环路补偿，从而对误差放大器的输出信号通过开关逻辑门控制，即只在功率开关管关断后的一小段时间即预设时间内误差放大器的输出对环路补偿电容进行充放电，实现环路补偿。因此，本发明实施例的用于开关电源的环路补偿装置主要是针对轻空载情况下的环路稳定性，在不影响开关电源较高频工作的前提下确保在很低频的情况下，误差放大器的输出能够比较真实反映次级输出电压的实际情况，从而解决开关电源输出纹波偏大的问题，保证环路稳定。
此外，本发明的实施例提出了一种开关电源的初级控制芯片，其包括上述的用于开关电源的环路补偿装置。
根据本发明实施例的开关电源的初级控制芯片，能够对误差放大器的输出信号通过开关逻辑门控制，即只在功率开关管关断后的一小段时间即预设时间内误差放大器的输出对环路补偿电容进行充放电，实现环路补偿，从而可针对开关电源轻空载情况下的环路稳定性，并在不影响开关电源较高频工作的前提下确保在很低频的情况下，使得误差放大器的输出能够比较真实反映次级输出电压的实际情况，解决开关电源输出纹波偏大的问题，保 证环路稳定。
最后，本发明的实施例还提出了一种开关电源，其包括上述的开关电源的初级控制芯片。
本发明实施例的开关电源，针对轻空载情况下的环路稳定性，可在不影响较高频工作的前提下确保在很低频的情况下，使得误差放大器的输出能够比较真实反映次级输出电压的实际情况，解决输出纹波偏大的问题，保证环路稳定。
在本发明的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”“内”、“外”、“顺时针”、“逆时针”、“轴向”、“径向”、“周向”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。在本发明的描述中，“多个”的含义是至少两个，例如两个，三个等，除非另有明确具体的限定。
在本发明中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”、“固定”等术语应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或成一体；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系，除非另有明确的限定。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本发明中的具体含义。
在本发明中，除非另有明确的规定和限定，第一特征在第二特征“上”或“下”可以是第一和第二特征直接接触，或第一和第二特征通过中间媒介间接接触。而且，第一特征在第二特征“之上”、“上方”和“上面”可是第一特征在第二特征正上方或斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”可以是第一特征在第二特征正下方或斜下方，或仅仅表示第一特征水平高度小于第二特征。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本发明的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领 域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
尽管上面已经示出和描述了本发明的实施例，可以理解的是，上述实施例是示例性的，不能理解为对本发明的限制，本领域的普通技术人员在本发明的范围内可以对上述实施例进行变化、修改、替换和变型。

Claims (10)

  1. 一种用于开关电源的环路补偿装置，其特征在于，包括：
    误差放大器，所述误差放大器的第一输入端与所述开关电源中初级控制芯片的采样保持电路的输出端相连，所述误差放大器的第二输入端与第一基准电压参考端相连，其中,所述误差放大器用于根据所述采样保持电路的采样保持信号和第一基准电压参考端的第一基准电压信号,得到误差放大信号；
    开关逻辑门，所述开关逻辑门的输入端与所述误差放大器的输出端相连；
    环路补偿电容，所述环路补偿电容的一端与所述开关逻辑门的输出端相连，所述环路补偿电容的另一端接地；
    延时产生电路，所述延时产生电路的输出端与所述开关逻辑门的控制端相连，所述延时产生电路用于在所述开关电源的功率开关管关断后的预设时间内输出有效开关控制信号以控制所述开关逻辑门处于开通状态，以使所述误差放大器输出的误差放大信号对所述环路补偿电容进行充放电。
  2. 根据权利要求1所述的用于开关电源的环路补偿装置，其特征在于，所述延时产生电路还用于在所述功率开关管关断后的预设时间外输出无效开关控制信号以控制所述开关逻辑门处于断开状态，以使所述环路补偿电容的充放电通路断开，所述误差放大器的输出电压被保持。
  3. 根据权利要求1或2所述的用于开关电源的环路补偿装置，其特征在于，所述延时产生电路在触发信号的控制下产生所述有效开关控制信号，其中，所述触发信号为所述功率开关管的关断信号。
  4. 根据权利要求3所述的用于开关电源的环路补偿装置，其特征在于，所述开关逻辑门具体包括：
    第一反相器，所述第一反相器的输入端与所述延时产生电路的输出端相连；
    第一开关管和第二开关管，所述第一开关管的第一端和所述第二开关管的第一端相连后与所述误差放大器的输出端相连，所述第一开关管的第二端与所述延时产生电路的输出端相连，所述第二开关管的第二端与所述第一反相器的输出端相连，所述第一开关管的第三端和所述第二开关管的第三端相连后作为所述开关逻辑门的输出端。
  5. 根据权利要求3或4所述的用于开关电源的环路补偿装置，其特征在于，所述延时产生电路具体包括：
    第一NMOS管，所述第一NMOS管的栅极作为所述延时产生电路的触发端以接收所述触发信号，所述第一NMOS管的漏极与第一电流源相连，所述第一NMOS管的源极接地；
    第一电容，所述第一电容并联在所述第一NMOS管的漏极与源极之间；
    施密特触发器，所述施密特触发器的输入端与所述第一NMOS管的漏极相连；
    第一或非门，所述第一或非门的第一输入端与所述施密特触发器的输出端相连，所述第一或非门的第二输入端与所述第一NMOS管的栅极相连；
    第二反相器，所述第二反相器的输入端与所述第一或非门的输出端相连，所述第二反相器的输出端作为所述延时产生电路的输出端。
  6. 根据权利要求3或4所述的用于开关电源的环路补偿装置，其特征在于，所述延时产生电路具体包括：
    第二NMOS管，所述第二NMOS管的栅极作为所述延时产生电路的触发端以接收所述触发信号，所述第二NMOS管的漏极与第二电流源相连，所述第二NMOS管的源极接地；
    第二电容，所述第二电容并联在所述第二NMOS管的漏极与源极之间；
    比较器，所述比较器的负输入端与所述第二NMOS管的漏极相连，所述比较器的正输入端与第二基准电压参考端相连；
    第二或非门，所述第二或非门的第一输入端与所述比较器的输出端相连，所述第二或非门的第二输入端与所述第二NMOS管的栅极相连；
    第三反相器，所述第三反相器的输入端与所述第二或非门的输出端相连，所述第三反相器的输出端作为所述延时产生电路的输出端。
  7. 根据权利要求5所述的用于开关电源的环路补偿装置，其特征在于，所述预设时间根据所述第一电容的容值和所述第一电流源的电流幅值确定。
  8. 根据权利要求7所述的用于开关电源的环路补偿装置，其特征在于，所述预设时间与所述第一电容的容值之间呈正相关关系，所述预设时间与所述第一电流源的电流幅值呈反相关关系。
  9. 一种开关电源的初级控制芯片，其特征在于，包括根据权利要求1-8中任一项所述的用于开关电源的环路补偿装置。
  10. 一种开关电源，其特征在于，包括根据权利要求9所述的初级控制芯片。
PCT/CN2016/098124 2015-09-07 2016-09-05 开关电源及其初级控制芯片和环路补偿装置 Ceased WO2017041684A1 (zh)

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