WO2017045351A1 - 移位寄存器及其驱动方法、栅极驱动电路和显示装置 - Google Patents

移位寄存器及其驱动方法、栅极驱动电路和显示装置 Download PDF

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Publication number
WO2017045351A1
WO2017045351A1 PCT/CN2016/073841 CN2016073841W WO2017045351A1 WO 2017045351 A1 WO2017045351 A1 WO 2017045351A1 CN 2016073841 W CN2016073841 W CN 2016073841W WO 2017045351 A1 WO2017045351 A1 WO 2017045351A1
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Prior art keywords
shift register
output
pull
node
signal
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PCT/CN2016/073841
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English (en)
French (fr)
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王峥
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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Priority to JP2016569033A priority Critical patent/JP6966199B2/ja
Priority to KR1020177000879A priority patent/KR101913519B1/ko
Priority to US15/306,833 priority patent/US9953611B2/en
Priority to EP16784120.4A priority patent/EP3352160A4/en
Publication of WO2017045351A1 publication Critical patent/WO2017045351A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G09G2330/023—Power management, e.g. power saving using energy recovery or conservation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/08—Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared

Definitions

  • the invention belongs to the technical field of gate driving, and particularly relates to a shift register and a driving method thereof, a gate driving circuit and a display device.
  • the array substrate is one of important components of a display device (a liquid crystal display device, an organic light emitting diode display device, etc.).
  • the array substrate includes a plurality of gate lines, and the gate lines are circulated into the conduction signal.
  • a gate drive circuit that is, a circuit for driving each gate line is prepared in an array substrate.
  • the gate drive circuit typically consists of a plurality of cascaded shift registers, each of which is used to drive a gate line.
  • Figure 1 shows a prior art shift register consisting of a plurality of transistors, capacitors and the like.
  • the level of the pull-down node PD of the shift register is controlled by the second clock signal terminal CLKB through the transistor M; and the pull-down node PD is also connected to a plurality of other transistors, each of which has a certain parasitic capacitance and parasitic resistance. Wait.
  • the signal of the second clock signal terminal CLKB is to pull the level change of the pull-down node PD (such as from low to high)
  • a large power consumption is generated, and thereby a large delay is generated.
  • the signals of the second clock signal terminal CLKB of the plurality of shift registers are usually provided by the same port, so that the power consumption of each shift register is superimposed on each other, resulting in a serious signal delay of the second clock signal terminal CLKB, which affects Shows the effect and generates a lot of power and wastes energy.
  • the present invention provides a shift register capable of reducing delay and power consumption, a driving method thereof, a gate driving circuit, and a display device, in view of a problem of delay and power consumption in a shift register of an existing gate driving circuit.
  • a first aspect of the present invention provides a shift register including a pull-up node, a first pull-down node, a second pull-down node, a first clock signal terminal, a second clock signal terminal, a first signal terminal, and a second a signal terminal, a shutdown signal terminal, and an output terminal, and further comprising:
  • An input module configured to introduce a signal of an output end of the shift register of the previous stage into the pull-up node
  • An output module configured to introduce a signal of the first clock signal end to the output end according to a level of the pull-up node
  • a reset module configured to reset the pull-up node, the output end, and the first pull-down by using a signal of the shutdown signal terminal, the first signal terminal, and the second signal terminal under the control of the signal at the output end of the next-stage shift register a node, and a second pulldown node;
  • a constant voltage module configured to introduce a signal of the shutdown signal end to the first pulldown node and the second pulldown node according to the level of the pullup node;
  • a holding module configured to introduce signals of the first signal end and the second signal end into the first pull-down node and the second pull-down node respectively under the control of the second clock signal end, thereby introducing the signal of the turn-off signal end into the pull-up node and Output.
  • the input module comprises: a first transistor having a gate and a first pole connected to an output of the upper stage shift register, and a second pole connected to the pull-up node.
  • the output module comprises: a third transistor having a gate connected to the pull-up node, a first pole connected to the first clock signal end, and a second pole connected to the output end; and a storage capacitor, the first The pole is connected to the pull-up node and its second pole is connected to the output.
  • the reset module includes: a second transistor having a gate connected to an output end of the next stage shift register, a first pole connected to the pull-up node, and a second pole connected to the turn-off signal end; a fourth transistor having a gate connected to the output of the next stage shift register, a first pole connected to the output terminal, and a second pole connected to the off signal terminal; and a seventh transistor having a gate connected to the next stage shift register An output terminal having a first pole connected to the first signal terminal and a second pole connected to the first pull-down node; and an eighth transistor having a gate connected to the output end of the next-stage shift register, the first pole connection The second signal end, and the second pole thereof is connected to the second pull-down node.
  • the constant voltage module comprises: a ninth transistor having a gate connected to the pull-up node, a first pole connected to the first pull-down node, and a second pole connected to the off signal terminal; and a tenth transistor , the gate is connected to the pull-up node, and the first pole is connected to the second The node is pulled and its second pole is connected to the off signal terminal.
  • the holding module includes: a fifth transistor having a gate connected to the second clock signal end, a first pole connected to the first signal end, and a second pole connected to the first pull-down node; the sixth transistor a gate connected to the second clock signal end, a first pole connected to the second signal end, and a second pole connected to the second pull-down node; an eleventh transistor having a gate connected to the first pull-down node, the first The pole is connected to the pull-up node, and the second pole is connected to the off signal terminal; the twelfth transistor has a gate connected to the first pull-down node, a first pole connected to the output end, and a second pole connected to the off signal end a thirteenth transistor having a gate connected to the second pull-down node, a first pole connected to the pull-up node, and a second pole connected to the turn-off signal terminal; and a fourteenth transistor having a gate connected to the second pull-down node, Its first pole is connected to the output terminal, and
  • the parasitic resistance of the ninth transistor is smaller than the parasitic resistance of the fifth transistor; and the parasitic resistance of the tenth transistor is smaller than the parasitic resistance of the sixth transistor.
  • all of the transistors are N-type transistors.
  • all of the transistors are P-type transistors.
  • a second aspect of the present invention provides a gate driving circuit including a plurality of cascaded shift registers.
  • a third aspect of the invention provides a display device including an array substrate, and the array substrate includes the above-described gate driving circuit.
  • a fourth aspect of the present invention provides a driving method of the above shift register, comprising:
  • the signal of the output end of the shift register of the upper stage is introduced into the pull-up node by the input module;
  • the signal of the first clock signal end is introduced into the output end by the output module, so that the output end outputs an on signal;
  • the shutdown signal terminal, the first signal end, and the And a signal of the second signal end to reset the pull-up node, the output end, the first pull-down node, and the second pull-down node;
  • the signal of the shutdown signal terminal is introduced into the pull-up node and the output terminal by the holding module, so that the output terminal continuously outputs the shutdown signal.
  • the driving method of the shift register includes: setting the first clock signal terminal to a low level and the second clock signal terminal to a high level during a charging phase Level, the output of the shift register of the previous stage is high level, and the output end of the shift register of the next stage is low level; in the output stage, the first clock signal end is set to a high level, The clock signal terminal is low level, the output end of the shift register of the previous stage is low level, and the output end of the shift register of the next stage is low level; in the reset phase, the first clock signal is set The terminal is low, the second clock signal is high, the output of the shift register of the previous stage is low, and the output of the shift register of the next stage is high: during the hold phase, the setting is The output end of the shift register of the upper stage and the output end of the shift register of the next stage are at a low level; in the above step, the off signal end is continuously at a low level, and the first signal
  • the driving method of the shift register includes: setting the first clock signal terminal to a high level and the second clock signal terminal to a low level during a charging phase Level, the output of the shift register of the previous stage is low level, and the output end of the shift register of the next stage is high level; in the output stage, the first clock signal end is set to a low level, The clock signal terminal is at a high level, the output end of the shift register of the previous stage is a high level, and the output end of the shift register of the next stage is a high level; in the reset phase, the first clock signal is set The terminal is at a high level, the second clock signal terminal is at a low level, the output terminal of the previous stage shift register is at a high level, and the output terminal of the next stage shift register is at a low level: in the hold phase, setting The output end of the shift register of the upper stage and the output end of the shift register of the next stage are at a high level; in the hold phase, setting The output end of the shift register of the upper stage and the output end
  • the driving method of the shift register further includes: switching the first a step of the level of the signal terminal and the level of the second signal terminal, so that the first signal terminal and the second signal terminal are turned into a low level, and the low level is turned to a high level.
  • the number of transistors connected to the clock signal is small, so that the delay and the power consumption thereof are low; and the clock signal does not directly control the level of each node, but passes through the first signal end and the second A stable signal such as a signal terminal controls the level of each node, so that even if the delay of the clock signal has a small influence on the display effect, the shift register can be stably operated and the display effect can be improved.
  • FIG. 1 is a circuit diagram of a conventional shift register.
  • FIG. 2 is a circuit diagram of a shift register in accordance with an embodiment of the present invention.
  • FIG. 3 is a timing chart of driving of the shift register of FIG. 2.
  • FIG. 4 is a circuit diagram of a shift register according to another embodiment of the present invention.
  • FIG. 5 is a timing chart of driving of the shift register of FIG. 4.
  • FIG. 6 is a block diagram showing a partial structure of a gate driving circuit according to an embodiment of the present invention.
  • T1 first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; T8, eighth Transistor; T9, ninth transistor; T10, tenth transistor; T11, eleventh transistor; T12, twelfth transistor; T13, thirteenth transistor; T14, fourteenth transistor; M, transistor; C, storage capacitor Output(N-1), upper shift register output; Output(N+1), next shift register output; Output N, output: Vdd1, first signal terminal; Vdd2, second Signal terminal; Vss, shutdown signal terminal; CLK, first clock signal terminal; CLKB, second clock signal terminal; PU, pull-up node; PD1, first pull-down node; PD2, second pull-down node.
  • the embodiment provides a shift register including a pull-up node PU, a first pull-down node PD1, a second pull-down node PD2, a first clock signal terminal CLK, and a second clock signal.
  • the shift register also includes:
  • An input module configured to introduce a signal of an output terminal (N-1) of the shift register of the previous stage into the pull-up node PU;
  • An output module configured to introduce a signal of the first clock signal terminal CLK into the output terminal Output N according to the level of the pull-up node PU;
  • the reset module is configured to reset the signal of the shutdown signal terminal Vss, the first signal terminal Vdd1, and the second signal terminal Vdd2 under the control of the signal of the output terminal Output(N+1) of the next-stage shift register.
  • a constant voltage module configured to introduce a signal of the shutdown signal terminal Vss into the first pulldown node PD1 and the second pulldown node PD2 according to the level of the pullup node PU;
  • a holding module configured to introduce signals of the first signal terminal Vdd1 and the second signal terminal Vdd2 into the first pull-down node PD1 and the second pull-down node PD2 respectively under the control of the second clock signal terminal CLKB, thereby turning off the signal
  • the signal of the terminal Vss is introduced into the pull-up node PU and the output Output N.
  • the number of transistors connected to each clock signal is small, and thus the delay and power consumption thereof are low; and the clock signal does not directly control the level of each node, but passes through the first signal terminal Vdd1.
  • the stable signal of the second signal terminal Vdd2 controls the level of each node, and thus the clock signal has a small influence on the display effect even if there is a delay, which can ensure the stability of the shift register operation and improve the display effect.
  • the input module comprises: a first transistor T1 having a gate and a first pole connected to an output terminal Output(N-1) of the upper stage shift register, and a second pole connected to the pull-up node PU.
  • the output module comprises: a third transistor T3 having a gate connected to the pull-up node PU, a first pole connected to the first clock signal terminal CLK, and a second pole connected to the output terminal Output N; and a storage capacitor C having a first pole connected to the pull-up node PU and a second pole connected to the output Output N.
  • the reset module comprises:
  • the second transistor T2 has a gate connected to an output terminal Output(N+1) of the next stage shift register, a first pole connected to the pull-up node PU, and a second pole connected to the turn-off signal terminal Vss;
  • the fourth transistor T4 has a gate connected to an output terminal Output(N+1) of the next stage shift register, a first pole connected to the output terminal Output N, and a second pole connected to the off signal terminal Vss;
  • a seventh transistor T7 having a gate connected to an output terminal Output(N+1) of the next stage shift register, a first pole connected to the first signal terminal Vdd1, and a second pole connected to the first pull-down node PD1;
  • the eighth transistor T8 has a gate connected to the output terminal Output(N+1) of the next stage shift register, a first pole connected to the second signal terminal Vdd2, and a second pole connected to the second pull-down node PD2.
  • the constant pressure module comprises:
  • a ninth transistor T9 having a gate connected to the pull-up node PU, a first pole connected to the first pull-down node PD1, and a second pole connected to the turn-off signal terminal Vss;
  • the tenth transistor T10 has a gate connected to the pull-up node PU, a first pole connected to the second pull-down node PD2, and a second pole connected to the turn-off signal terminal Vss.
  • the retention module comprises:
  • the fifth transistor T5 has a gate connected to the second clock signal terminal CLKB, a first pole connected to the first signal terminal Vdd1, and a second pole connected to the first pull-down node PD1;
  • the sixth transistor T6 has a gate connected to the second clock signal terminal CLKB, a first pole connected to the second signal terminal Vdd2, and a second pole connected to the second pull-down node PD2;
  • the eleventh transistor T11 has a gate connected to the first pull-down node PD1, a first pole connected to the pull-up node PU, and a second pole connected to the turn-off signal terminal Vss;
  • the twelfth transistor T12 has a gate connected to the first pull-down node PD1, a first pole connected to the output terminal Output N, and a second pole connected to the off signal terminal Vss;
  • a thirteenth transistor T13 having a gate connected to the second pull-down node PD2, a first pole connected to the pull-up node PU, and a second pole connected to the turn-off signal terminal Vss;
  • the fourteenth transistor T14 has a gate connected to the second pull-down node PD2, and the first pole is connected It is connected to the output terminal Output N, and its second pole is connected to the shutdown signal terminal Vss.
  • the parasitic resistance of the ninth transistor T9 is smaller than the parasitic resistance of the fifth transistor T5; the parasitic resistance of the tenth transistor T10 is smaller than the parasitic resistance of the sixth transistor T6.
  • all of the transistors are N-type transistors (such as all N-type thin film transistors).
  • the embodiment further provides a driving method of the above shift register, which comprises the following steps:
  • the signal of the output terminal Output(N-1) of the previous stage shift register is introduced into the pull-up node PU through the input module;
  • the signal of the first clock signal terminal CLK is introduced into the output terminal Output N through the output module, so that the output terminal Output N outputs an on signal;
  • the pull-up node PU, the output terminal Output N, the first pull-down node PD1, and the signal of the shutdown signal terminal Vss, the first signal terminal Vdd1, and the second signal terminal Vdd2 are reset by the reset module.
  • the signal of the shutdown signal terminal Vss is introduced into the pull-up node PU and the output terminal Output N by the holding module, so that the output terminal Output N continuously outputs the shutdown signal.
  • the turn-off signal terminal Vss continues to be low, and one of the first signal terminal Vdd1 and the second signal terminal Vdd2 is high. The other is low.
  • the turn-off signal terminal Vss must always be in a low state (because the N-type transistor is turned off at a low level); and at any time, the first signal terminal Vdd1 and the second signal terminal Vdd2 It must be a state of "one high and one low.” Specifically, the first signal terminal Vdd1 is always at a high level, and the second signal terminal Vdd2 is always at a low level as an example to illustrate the embodiment, and other cases will be described later.
  • the driving method of the shift register at this time specifically includes:
  • the output terminal Output(N+1) of the next stage shift register is set to a low level, so the second transistor T2, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are all turned off; Therefore, the high level of the output terminal (N-1) of the shift register of the upper stage causes the first transistor T1 to be turned on, and the pull-up node PU becomes a high level, thereby causing the third transistor T3 and the ninth transistor T9.
  • the tenth transistor T10 is turned on, and the first pole (the left one pole) of the storage capacitor C is set to a high level; and the second pole (the right pole of the right side) of the storage capacitor C (which is the output terminal Output N) ) is set to a low level by the third transistor T3 at a low level of the first clock signal terminal CLK, so that the shift register outputs a shutdown signal (low level), and a certain level difference is generated across the storage capacitor C. .
  • the low level of the second signal terminal Vdd2 is introduced to the second pull-down node PD2 via the sixth transistor T6, and the low level of the turn-off signal terminal Vss is also passed.
  • the tenth transistor T10 is introduced to the second pull-down node PD2 to stabilize its low level.
  • the first pull-down node PD1 one end thereof is connected to the high level of the first signal terminal Vdd1 via the fifth transistor T5, and the other end thereof is connected to the low level of the turn-off signal terminal Vss via the ninth transistor T9, so at this time
  • the level of a pull-down node PD1 is determined by the voltage division of the ninth transistor T9 and the fifth transistor T5.
  • the parasitic resistance of the ninth transistor T9 is smaller than the parasitic resistance of the fifth transistor T5, the voltage division of the ninth transistor T9 is small, and the first pull-down node PD1 is closer to the level of the turn-off signal terminal Vss, which can be regarded as low. Level. It should be understood that when the first clock signal terminal CLK is at a low level and the second clock signal terminal CLKB is at a high level, the condition of the second pull-down node PD2 is similar, that is, the level of the second pull-down node PD2 is tenth. The voltage division of the transistor T10 and the sixth transistor T6 is determined.
  • the second pull-down node PD2 should also be at a low level in this state.
  • the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, and the fourteenth transistor T14 are all turned off, which does not affect the pull-up node PU, and ensures the stability of the circuit.
  • the output (Output (N-1) of the shift register of the previous stage becomes low.
  • the second clock signal terminal CLKB becomes a low level, so that the fifth transistor T5 and the sixth transistor T6 are turned off, and the signals of the first signal terminal Vdd1 and the second signal terminal Vdd2 can no longer enter the circuit, the first pull-down node
  • the PD1 and the second pull-down node PD2 maintain the low level of the turn-off signal terminal Vss, and the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, and the fourteenth transistor T14 also remain turned off, thereby pulling up the node.
  • PU floats and remains high.
  • the third transistor T3 remains turned on, and the high level of the first clock signal terminal CLK is introduced to the output terminal Output N, so that the output terminal Output N outputs an on signal (high level).
  • the level of the pull-up node PU is further increased, thereby more reliably keeping the third transistor T3 turned on, and stabilizing the output of the on-signal.
  • the output terminal Output(N+1) of the next stage shift register is at a high level, so that the second transistor T2, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned on, and thus the second The transistor T2 introduces a low level of the turn-off signal terminal Vss into the pull-up node PU, and the fourth transistor T4 introduces a low level of the turn-off signal terminal Vss to the output terminal Output N, so that the shift register stably outputs the turn-off signal (low Level) and reset the level across storage capacitor C.
  • the high level of the first signal terminal Vdd1 is introduced into the first pull-down node PD1 via the seventh transistor T7
  • the low level of the second signal terminal Vdd2 is introduced into the second pull-down node PD2 via the eighth transistor T8, and the eleventh transistor T11 And the twelfth transistor T12 is turned on to assist the second transistor T2 and the fourth transistor T4 to introduce the low level of the off signal terminal Vss into the pull-up node PU and the output terminal Output N, thereby functioning as a noise reduction.
  • the level of these two points is best controlled to achieve a stable output.
  • the second clock signal terminal CLKB is at a high level, so that the fifth transistor T5 and the sixth transistor T6 are also turned on to assist the seventh transistor T7 and the eighth transistor T8 to transmit signals, thereby improving circuit stability.
  • the low level of the shutdown signal terminal Vss is introduced into the two ends of the storage capacitor C through a plurality of different transistors, thereby ensuring the stability of the low level of the storage capacitor C at both ends. Qualitative, improved output.
  • the output terminal Output(N-1) of the upper shift register and the output terminal (N+1) of the shift register of the next stage are both low, so that the first transistor T1 and the second transistor T2, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are all turned off, and the pull-up node PU is kept at a low level, so that the ninth transistor T9 and the tenth transistor T10 are also turned off.
  • the second clock signal terminal CLKB switches between high and low levels.
  • the fifth transistor T5 is turned on, and the high level of the first signal terminal Vdd1 is introduced into the first pull-down node PD1, so that the eleventh transistor T11 and the twelfth transistor T12 are turned on.
  • the low level of the shutdown signal terminal Vss is introduced to both ends of the storage capacitor C, so that the shift register outputs a shutdown signal (low level).
  • the fifth transistor T5 is turned off, and the first pull-down node PD1 is floated.
  • the first pull-down node PD1 Due to the parasitic capacitance of various devices in the circuit, and because the signal of the second clock signal terminal CLKB is switched fast, the first pull-down node PD1 is still in a short time when the second clock signal terminal CLKB is at a low level. The high level that can turn on the eleventh transistor T11 and the twelfth transistor T12 is maintained, so that the shift register continues to output the off signal (low level).
  • a low-level signal is introduced to both ends of the storage capacitor C through the eleventh transistor T11 and the twelfth transistor T12, thereby functioning as a noise reduction and maximizing the output.
  • the driving method of the above shift register further comprises the step of switching the levels of the first signal terminal Vdd1 and the second signal terminal Vdd2, that is, the first signal terminal Vdd1 and the second signal terminal Vdd2 are originally high level. It changes to a low level, and the low level turns high.
  • the first pull-down node PD1 may be at a high level, and the second pull-down node PD2 is always maintained. Low level. That is, only with the first signal end
  • the eleventh transistor T11 and the twelfth transistor T12 corresponding to the Vdd1 are in an on state, and the thirteenth transistor T13 and the fourteenth transistor T14 corresponding to the second signal terminal Vdd2 (the second pull-down node PD2) are always off. Broken, actually in an "standby" state that is not working.
  • the structure corresponding to the first signal terminal Vdd1 and the second signal terminal Vdd2 is actually completely equivalent, so if the second signal terminal Vdd2 is at a high level and the first signal terminal Vdd1 is at a low level,
  • the present invention can be implemented in exactly the same way, except that the state of the first pull-down node PD1 is interchanged with the state of the second pull-down node PD2, and the states of the eleventh transistor T11 and the twelfth transistor T12 are the same as the tenth The states of the three transistors T13 and the fourteenth transistor T14 are interchanged.
  • the above switching can be performed at any time, in order to ensure the stability of the circuit and reduce the difficulty of switching, it is preferable to perform switching every time interval, for example, every several frames to hundreds of frames.
  • the specific time interval can be between 0.1 seconds and 10 seconds.
  • this embodiment provides a shift register.
  • the shift register has a structure similar to that of the shift register of the first embodiment, except that all of the transistors are P-type transistors.
  • the embodiment further provides a driving method for the above shift register, which includes:
  • the shutdown signal terminal Vss continues to be at a high level, and one of the first signal terminal Vdd1 and the second signal terminal Vdd2 is at a high level, and the other is a low level.
  • the embodiment provides a gate driving circuit including a plurality of cascaded shift registers.
  • a plurality of the above shift registers can be cascaded to form a gate driving circuit for driving the gate.
  • each shift register is connected to a gate line to provide a driving signal for the gate line.
  • the output of each shift register is also connected to its upper and lower stage shift registers as part of their inputs.
  • their respective inputs can be connected to separate signal terminals.
  • the first signal end, the second signal end, the first clock signal end, and the second clock signal end of the plurality of shift registers are respectively connected to the same port through wires, thereby providing signals for the plurality of shift registers by one port.
  • the output phase of each shift register (that is, when the output is turned on) is also the charging phase of the shift register of the next stage (that is, when the output signal of the shift register of the previous stage is output), and the two shifts at this time.
  • the need for registers to signal the first clock signal and the second clock signal is necessarily reversed. Therefore, the same clock signal terminals of adjacent shift registers can be respectively connected to different ports. Since the specific cascading mode of the shift register is known, it will not be described in detail herein.
  • the embodiment provides a display device including an array substrate, and the array substrate includes the above gate driving circuit.
  • the display device can be any product or component having a display function, such as a liquid crystal display panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a liquid crystal display panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.

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Abstract

一种移位寄存器及其驱动方法、栅极驱动电路和显示装置，其可解决现有栅极驱动电路移位寄存器中延迟和功耗大的问题。移位寄存器包括：输入模块，将上一级移位寄存器输出端（Output（N-1））信号引入上拉节点（PU）；输出模块，根据上拉节点（PU）电平，将第一时钟信号端（CLK）信号引入输出端（Output N）；重置模块，在下一级移位寄存器的输出端（Output（N+1））信号的控制下，用关断信号端（Vss）、第一信号端（Vdd1）、和第二信号端（Vdd2）信号重置上拉节点（PU）、输出端（Output N）、第一下拉节点（PD1）和第二下拉节点（PD2）；定压模块，根据上拉节点（PU）电平，将关断信号端（Vss）信号引入两个下拉节点（PD1、PD2）；保持模块，用于在第二时钟信号端（CLKB）控制下，将第一信号端（Vdd1）和第二信号端（Vdd2）信号分别引入两个下拉节点（PD1、PD2）。

Description

移位寄存器及其驱动方法、栅极驱动电路和显示装置 技术领域
本发明属于栅极驱动技术领域，具体涉及一种移位寄存器及其驱动方法、栅极驱动电路和显示装置。
背景技术
阵列基板是显示装置(液晶显示装置，有机发光二极管显示装置等)的重要部件之一。阵列基板中包括多条栅线，这些栅线中要轮流通入导通信号。为驱动栅线，一种现有方法是使用栅极驱动电路(GOA)，即将用于驱动各栅线的电路制备在阵列基板中。栅极驱动电路通常由多个级联的移位寄存器组成，每个移位寄存器用于驱动一条栅线。
图1示出了一种现有的移位寄存器，其由多个晶体管、电容等组成。从图1中可见，移位寄存器的下拉节点PD的电平由第二时钟信号端CLKB通过晶体管M控制；且下拉节点PD还连接多个其他晶体管，这些晶体管均有一定的寄生电容、寄生电阻等。由此，当第二时钟信号端CLKB的信号要拉动下拉节点PD的电平变化(如由低到高)时，会产生较大的功耗，并由此产生较大延迟(delay)。尤其是多个移位寄存器的第二时钟信号端CLKB的信号通常是由同一个端口提供的，这样各移位寄存器的功耗相互叠加，导致最终第二时钟信号端CLKB的信号延迟严重，影响显示效果，并产生很大功耗，浪费能量。
发明内容
针对现有的栅极驱动电路的移位寄存器中延迟和功耗大的问题，本发明提供一种可降低延迟和功耗的移位寄存器及其驱动方法、栅极驱动电路和显示装置。
本发明的第一方面提供了一种移位寄存器，其包括上拉节点、第一下拉节点、第二下拉节点、第一时钟信号端、第二时钟信号端、第一信号端、第二信号端、关断信号端、和输出端，并且其还包括：
输入模块，用于将上一级移位寄存器的输出端的信号引入上拉节点；
输出模块，用于根据上拉节点的电平，将第一时钟信号端的信号引入输出端；
重置模块；用于在下一级移位寄存器的输出端的信号的控制下，用关断信号端、第一信号端、和第二信号端的信号重置上拉节点、输出端、第一下拉节点、和第二下拉节点；
定压模块，用于根据上拉节点的电平，将关断信号端的信号引入第一下拉节点和第二下拉节点；以及
保持模块，用于在第二时钟信号端的控制下，将第一信号端和第二信号端的信号分别引入第一下拉节点和第二下拉节点，从而将关断信号端的信号引入上拉节点和输出端。
优选的是，所述输入模块包括：第一晶体管，其栅极和第一极连接上一级移位寄存器的输出端，并且其第二极连接上拉节点。
进一步优选的是，所述输出模块包括：第三晶体管，其栅极连接上拉节点，其第一极连接第一时钟信号端，并且其第二极连接输出端；以及存储电容，其第一极连接上拉节点，并且其第二极连接输出端。
进一步优选的是，所述重置模块包括：第二晶体管，其栅极连接下一级移位寄存器的输出端，其第一极连接上拉节点，并且其第二极连接关断信号端；第四晶体管，其栅极连接下一级移位寄存器输出端，其第一极连接输出端，并且其第二极连接关断信号端；第七晶体管，其栅极连接下一级移位寄存器的输出端，其第一极连接第一信号端，并且其第二极连接第一下拉节点；以及第八晶体管，其栅极连接下一级移位寄存器的输出端，其第一极连接第二信号端，并且其第二极连接第二下拉节点。
进一步优选的是，所述定压模块包括：第九晶体管，其栅极连接上拉节点，其第一极连接第一下拉节点，并且其第二极连接关断信号端；以及第十晶体管，其栅极连接上拉节点，其第一极连接第二下 拉节点，并且其第二极连接关断信号端。
进一步优选的是，所述保持模块包括：第五晶体管，其栅极连接第二时钟信号端，其第一极连接第一信号端，并且其第二极连接第一下拉节点；第六晶体管，其栅极连接第二时钟信号端，其第一极连接第二信号端，并且其第二极连接第二下拉节点；第十一晶体管，其栅极连接第一下拉节点，其第一极连接上拉节点，并且其第二极连接关断信号端；第十二晶体管，其栅极连接第一下拉节点，其第一极连接输出端，并且其第二极连接关断信号端；第十三晶体管，其栅极连接第二下拉节点，其第一极连接上拉节点，并且其第二极连接关断信号端；以及第十四晶体管，其栅极连接第二下拉节点，其第一极连接输出端，并且其第二极连接关断信号端。
进一步优选的是，所述第九晶体管的寄生电阻小于第五晶体管的寄生电阻；以及所述第十晶体管的寄生电阻小于第六晶体管的寄生电阻。
进一步优选的是，所有所述晶体管均为N型晶体管。
替代地，所有所述晶体管均为P型晶体管。
本发明的第二方面提供了一种栅极驱动电路，其包括多个级联的上述移位寄存器。
本发明的第三方面提供了一种显示装置，包括阵列基板，且所述阵列基板包括上述栅极驱动电路。
本发明的第四方面提供了一种上述移位寄存器的驱动方法，其包括：
在充电阶段，通过所述输入模块将上一级移位寄存器的输出端的信号引入上拉节点；
在输出阶段，通过所述输出模块将第一时钟信号端的信号引入输出端，使输出端输出导通信号；
在重置阶段，通过所述重置模块用关断信号端、第一信号端、 和第二信号端的信号来重置上拉节点、输出端、第一下拉节点、和第二下拉节点；以及
在保持阶段，通过所述保持模块将关断信号端的信号引入上拉节点和输出端，使输出端持续输出关断信号。
优选的是，在以上全部晶体管为N型晶体管的情况下，所述移位寄存器的驱动方法包括：在充电阶段，设置所述第一时钟信号端为低电平，第二时钟信号端为高电平，上一级移位寄存器的输出端为高电平，并且下一级移位寄存器的输出端为低电平；在输出阶段，设置所述第一时钟信号端为高电平，第二时钟信号端为低电平，上一级移位寄存器的输出端为低电平，并且下一级移位寄存器的输出端为低电平；在重置阶段，设置所述第一时钟信号端为低电平，第二时钟信号端为高电平，上一级移位寄存器的输出端为低电平，并且下一级移位寄存器的输出端为高电平：在保持阶段，设置所述上一级移位寄存器的输出端和下一级移位寄存器的输出端为低电平；在以上步骤中，所述关断信号端持续为低电平，所述第一信号端和第二信号端中的一个为高电平，另一个为低电平。
优选的是，在以上全部晶体管为P型晶体管的情况下，所述移位寄存器的驱动方法包括：在充电阶段，设置所述第一时钟信号端为高电平，第二时钟信号端为低电平，上一级移位寄存器的输出端为低电平，并且下一级移位寄存器的输出端为高电平；在输出阶段，设置所述第一时钟信号端为低电平，第二时钟信号端为高电平，上一级移位寄存器的输出端为高电平，并且下一级移位寄存器的输出端为高电平；在重置阶段，设置所述第一时钟信号端为高电平，第二时钟信号端为低电平，上一级移位寄存器的输出端为高电平，并且下一级移位寄存器的输出端为低电平：在保持阶段，设置所述上一级移位寄存器的输出端和下一级移位寄存器的输出端为高电平；在以上步骤中，所述关断信号端持续为高电平，所述第一信号端和第二信号端中的一个为高电平，另一个为低电平。
进一步优选的是，所述移位寄存器的驱动方法还包括：切换第 一信号端的电平和第二信号端的电平的步骤，以使第一信号端和第二信号端中原为高电平的变为低电平，原为低电平的变为高电平。
本发明的移位寄存器中，时钟信号所接的晶体管数量少，由此其延迟和能耗均低；且时钟信号并不直接控制各节点的电平，而是通过第一信号端、第二信号端等的稳定信号来控制各节点的电平，由此时钟信号即使有延迟对显示效果的影响也小，可保证移位寄存器运行稳定，改善显示效果。
附图说明
图1为现有的一种移位寄存器的电路图。
图2为本发明的一个实施例的移位寄存器的电路图。
图3为图2的移位寄存器的驱动时序图。
图4为本发明的另一实施例的移位寄存器的电路图。
图5为图4的移位寄存器的驱动时序图。
图6为本发明的一个实施例的栅极驱动电路的局部结构框图。
附图标记：T1、第一晶体管；T2、第二晶体管；T3、第三晶体管；T4、第四晶体管；T5、第五晶体管；T6、第六晶体管；T7、第七晶体管；T8、第八晶体管；T9、第九晶体管；T10、第十晶体管；T11、第十一晶体管；T12、第十二晶体管；T13、第十三晶体管；T14、第十四晶体管；M、晶体管；C、存储电容；Output(N-1)、上一级移位寄存器输出端；Output(N+1)、下一级移位寄存器输出端；Output N、输出端：Vdd1、第一信号端；Vdd2、第二信号端；Vss、关断信号端；CLK、第一时钟信号端；CLKB、第二时钟信号端；PU、上拉节点；PD1、第一下拉节点；PD2、第二下拉节点。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明作进一步详细描述。
第一实施例：
如图2和图3所示，本实施例提供一种移位寄存器，其包括上拉节点PU、第一下拉节点PD1、第二下拉节点PD2、第一时钟信号端CLK、第二时钟信号端CLKB、第一信号端Vdd1、第二信号端Vdd2、关断信号端Vss、和输出端Output N。该移位寄存器还包括：
输入模块，用于将上一级移位寄存器的输出端Output(N-1)的信号引入上拉节点PU；
输出模块，用于根据上拉节点PU的电平，将第一时钟信号端CLK的信号引入输出端Output N；
重置模块，用于在下一级移位寄存器的输出端Output(N+1)的信号的控制下，用关断信号端Vss、第一信号端Vdd1、和第二信号端Vdd2的信号重置上拉节点PU、输出端Output N、第一下拉节点PD1、和第二下拉节点PD2；
定压模块，用于根据上拉节点PU的电平，将关断信号端Vss的信号引入第一下拉节点PD1和第二下拉节点PD2；以及
保持模块，用于在第二时钟信号端CLKB的控制下，将第一信号端Vdd1和第二信号端Vdd2的信号分别引入第一下拉节点PD1和第二下拉节点PD2，从而将关断信号端Vss的信号引入上拉节点PU和输出端Output N。
本实施例的移位寄存器中，各时钟信号所接的晶体管数量少，由此其延迟和能耗均低；且时钟信号并不直接控制各节点的电平，而是通过第一信号端Vdd1、第二信号端Vdd2等的稳定的信号控制各节点的电平，由此时钟信号即使有延迟对显示效果的影响也小，可保证移位寄存器运行的稳定，改善显示效果。
优选的，输入模块包括：第一晶体管T1，其栅极和第一极连接上一级移位寄存器的输出端Output(N-1)，并且其第二极连接上拉节点PU。
更优选的，输出模块包括：第三晶体管T3，其栅极连接上拉节点PU，其第一极连接第一时钟信号端CLK，并且其第二极连接输出端 Output N；以及存储电容C，其第一极连接上拉节点PU，并且其第二极连接输出端Output N。
更优选的，重置模块包括：
第二晶体管T2，其栅极连接下一级移位寄存器的输出端Output(N+1)，其第一极连接上拉节点PU，其第二极连接关断信号端Vss；
第四晶体管T4，其栅极连接下一级移位寄存器的输出端Output(N+1)，其第一极连接输出端Output N，其第二极连接关断信号端Vss；
第七晶体管T7，其栅极连接下一级移位寄存器的输出端Output(N+1)，其第一极连接第一信号端Vdd1，其第二极连接第一下拉节点PD1；以及
第八晶体管T8，其栅极连接下一级移位寄存器的输出端Output(N+1)，其第一极连接第二信号端Vdd2，其第二极连接第二下拉节点PD2。
更优选的，定压模块包括：
第九晶体管T9，其栅极连接上拉节点PU，其第一极连接第一下拉节点PD1，其第二极连接关断信号端Vss；以及
第十晶体管T10，其栅极连接上拉节点PU，其第一极连接第二下拉节点PD2，其第二极连接关断信号端Vss。
更优选的，保持模块包括：
第五晶体管T5，其栅极连接第二时钟信号端CLKB，其第一极连接第一信号端Vdd1，其第二极连接第一下拉节点PD1；
第六晶体管T6，其栅极连接第二时钟信号端CLKB，其第一极连接第二信号端Vdd2，其第二极连接第二下拉节点PD2；
第十一晶体管T11，其栅极连接第一下拉节点PD1，其第一极连接上拉节点PU，其第二极连接关断信号端Vss；
第十二晶体管T12，其栅极连接第一下拉节点PD1，其第一极连接输出端Output N，其第二极连接关断信号端Vss；
第十三晶体管T13，其栅极连接第二下拉节点PD2，其第一极连接上拉节点PU，其第二极连接关断信号端Vss；以及
第十四晶体管T14，其栅极连接第二下拉节点PD2，其第一极连 接输出端Output N，其第二极连接关断信号端Vss。
更优选的，第九晶体管T9的寄生电阻小于第五晶体管T5的寄生电阻；第十晶体管T10的寄生电阻小于第六晶体管T6的寄生电阻。
更优选的，所有晶体管均为N型晶体管(如全部为N型薄膜晶体管)。
本实施例还提供一种上述移位寄存器的驱动方法，其包括如下步骤：
在充电阶段，通过输入模块将上一级移位寄存器的输出端Output(N-1)的信号引入上拉节点PU；
在输出阶段，通过输出模块将第一时钟信号端CLK的信号引入输出端Output N，使输出端Output N输出导通信号；
在重置阶段，通过重置模块用关断信号端Vss、第一信号端Vdd1、和第二信号端Vdd2的信号重置上拉节点PU、输出端Output N、第一下拉节点PD1、和第二下拉节点PD2；
在保持阶段，通过保持模块将关断信号端Vss的信号引入上拉节点PU和输出端Output N，使输出端Output N持续输出关断信号。
在一个示例中，对于以上所有晶体管均为N型晶体管的移位寄存器，关断信号端Vss持续为低电平，而第一信号端Vdd1和第二信号端Vdd2中的一个为高电平，另一个为低电平。
也就是说，在该示例中，关断信号端Vss必须一直处于低电平状态(因为N型晶体管在低电平时关断)；且在任意时刻，第一信号端Vdd1和第二信号端Vdd2必然是“一高一低”的状态。具体的，以第一信号端Vdd1一直为高电平，第二信号端Vdd2一直为低电平为例说明本实施例，而其他情况将后续说明。
如图3所示，此时移位寄存器的驱动方法具体包括：
S11，在充电阶段，设置第一时钟信号端CLK为低电平，第二时钟信号端CLKB为高电平，上一级移位寄存器的输出端Output(N-1)为高电平，并且下一级移位寄存器的输出端Output(N+1)为低电平。
本阶段中，下一级移位寄存器的输出端Output(N+1)被设置为低电平，故第二晶体管T2、第四晶体管T4、第七晶体管T7、第八晶体管T8均关断；由此上一级移位寄存器的输出端Output(N-1)的高电平使第一晶体管T1导通，上拉节点PU变为高电平，进而使第三晶体管T3、第九晶体管T9、第十晶体管T10导通，并将存储电容C的第一极(左侧一极)置为高电平；而存储电容C的第二极(右侧一极)(其为输出端Output N)则被第一时钟信号端CLK的低电平经第三晶体管T3置为低电平，从而移位寄存器输出关断信号(低电平)，且存储电容C两端产生一定的电平差。
同时，由于第二时钟信号端CLKB为高电平，故第二信号端Vdd2的低电平经第六晶体管T6被引入到第二下拉节点PD2，且关断信号端Vss的低电平也经过第十晶体管T10被引入到第二下拉节点PD2，以稳定其低电平。对于第一下拉节点PD1，其一端经过第五晶体管T5连接到第一信号端Vdd1的高电平，其另一端经第九晶体管T9连接到关断信号端Vss的低电平，故此时第一下拉节点PD1的电平由第九晶体管T9和第五晶体管T5的分压决定。由于第九晶体管T9的寄生电阻比第五晶体管T5的寄生电阻小，故第九晶体管T9的分压小，第一下拉节点PD1更接近关断信号端Vss的电平，可被视为低电平。应当理解，当第一时钟信号端CLK为低电平而第二时钟信号端CLKB为高电平时，第二下拉节点PD2的状况与此类似，即，第二下拉节点PD2的电平由第十晶体管T10和第六晶体管T6的分压决定。由于第十晶体管T10的寄生电阻比第六晶体管T6的寄生电阻小，故该状态下第二下拉节点PD2也应为低电平。这样，第十一晶体管T11、第十二晶体管T12、第十三晶体管T13、和第十四晶体管T14均关断，不对上拉节点PU造成影响，保证了电路稳定。
S12，在输出阶段，设置第一时钟信号端CLK为高电平，第二时钟信号端CLKB为低电平，上一级移位寄存器的输出端Output(N-1)为低电平，并且下一级移位寄存器的输出端Output(N+1)为低电平。
本阶段中，上一级移位寄存器的输出端Output(N-1)变为低电 平，从而第一晶体管T1关断。第二时钟信号端CLKB变为低电平，从而第五晶体管T5、第六晶体管T6关断，第一信号端Vdd1和第二信号端Vdd2的信号不再能进入电路中，第一下拉节点PD1和第二下拉节点PD2保持关断信号端Vss的低电平，第十一晶体管T11、第十二晶体管T12、第十三晶体管T13、第十四晶体管T14也保持关断，从而上拉节点PU浮接，保持高电平。这样，第三晶体管T3保持导通，将第一时钟信号端CLK的高电平引入输出端Output N，使输出端Output N输出导通信号(高电平)。
同时通过存储电容C的自举效应，上拉节点PU的电平进一步提高，从而更可靠的保持第三晶体管T3导通，稳定了导通信号的输出。
S13，在重置阶段，设置第一时钟信号端CLK为低电平，第二时钟信号端CLKB为高电平，上一级移位寄存器的输出端Output(N-1)为低电平，并且下一级移位寄存器的输出端Output(N+1)为高电平。
本阶段中，下一级移位寄存器的输出端Output(N+1)为高电平，使第二晶体管T2、第四晶体管T4、第七晶体管T7、第八晶体管T8导通，从而第二晶体管T2将关断信号端Vss的低电平引入上拉节点PU，第四晶体管T4将关断信号端Vss的低电平引入输出端Output N，使移位寄存器稳定地输出关断信号(低电平)，并将存储电容C两端的电平重置。
同时，第一信号端Vdd1的高电平经第七晶体管T7引入第一下拉节点PD1，第二信号端Vdd2的低电平经第八晶体管T8引入第二下拉节点PD2，第十一晶体管T11和第十二晶体管T12导通，以辅助第二晶体管T2和第四晶体管T4将关断信号端Vss的低电平引入上拉节点PU和输出端Output N，从而起到降噪的作用。最好地控制这两个点的电平，以获得稳定的输出效果。而且，此时第二时钟信号端CLKB为高电平，使第五晶体管T5、第六晶体管T6也导通，以辅助第七晶体管T7和第八晶体管T8传递信号，提高电路稳定性。
本阶段中，通过多个不同的晶体管将关断信号端Vss的低电平引入存储电容C两端，从而很好的保证了存储电容C两端低电平的稳 定性，改善了输出效果。
S14，在保持阶段，设置上一级移位寄存器的输出端Output(N-1)和下一级移位寄存器的输出端Output(N+1)为低电平。
本阶段中，上一级移位寄存器的输出端Output(N-1)和下一级移位寄存器的输出端Output(N+1)均为低电平，从而第一晶体管T1、第二晶体管T2、第四晶体管T4、第七晶体管T7、和第八晶体管T8均关断，上拉节点PU保持低电平，使第九晶体管T9和第十晶体管T10也关断。
同时，第二时钟信号端CLKB在高低电平间切换。当第二时钟信号端CLKB为高电平时，则第五晶体管T5导通，将第一信号端Vdd1的高电平引入第一下拉节点PD1，使第十一晶体管T11、第十二晶体管T12导通，将关断信号端Vss的低电平引入存储电容C两端，使移位寄存器输出关断信号(低电平)。当第二时钟信号端CLKB为低电平时，则第五晶体管T5关断，第一下拉节点PD1浮接。由于电路中各种器件的寄生电容的作用，且由于第二时钟信号端CLKB的信号切换很快，因此，在第二时钟信号端CLKB为低电平的短时间，第一下拉节点PD1仍保持可使第十一晶体管T11和第十二晶体管T12导通的高电平，进而使移位寄存器持续输出关断信号(低电平)。
在本阶段中，通过第十一晶体管T11和第十二晶体管T12将低电平信号引入存储电容C两端，从而起到降噪作用，并最大限度地稳定输出。
优选的，以上的移位寄存器的驱动方法还包括切换第一信号端Vdd1和第二信号端Vdd2的电平的步骤，也就是使第一信号端Vdd1和第二信号端Vdd2中原为高电平的变为低电平，原为低电平的变为高电平。
根据以上描述可知，在第一信号端Vdd1为高电平而第二信号端Vdd2为低电平的情况下，只有第一下拉节点PD1可能为高电平，而第二下拉节点PD2一直保持低电平。也就是说，只有与第一信号端 Vdd1对应的第十一晶体管T11和第十二晶体管T12会处于导通状态，而与第二信号端Vdd2(第二下拉节点PD2)对应的第十三晶体管T13和第十四晶体管T14则一直关断，实际处于不工作的“备用”状态。
从图3可见，第一信号端Vdd1和第二信号端Vdd2对应的结构实际是完全等价的，故若第二信号端Vdd2为高电平而第一信号端Vdd1为低电平，则也可按照完全相同的方法实现本发明，只是其中第一下拉节点PD1的状态会与第二下拉节点PD2的状态互换，而第十一晶体管T11、第十二晶体管T12的状态会与第十三晶体管T13、第十四晶体管T14的状态互换。
由此，为了轮流使用与第一信号端Vdd1和第二信号端Vdd2对应的晶体管以延长其使用寿命，故优选可每隔一段时间将第一信号端Vdd1和第二信号端Vdd2的状态切换一次。
当然，虽然以上切换在任意时刻进行都可，但为了保证电路的稳定以及降低切换的难度，故优选每间隔较长的时间才进行一次切换，例如每隔数帧至数百帧画面的时间进行一次切换，其具体时间间隔可在0.1秒～10秒之间。
第二实施例：
如图4、图5所示，本实施例提供一种移位寄存器。
具体的，该移位寄存器具有与第一实施例的移位寄存器相似的结构，区别在于其中所有的晶体管均为P型晶体管。
本实施例还提供一种上述移位寄存器的驱动方法，其包括：
S21，在充电阶段，设置第一时钟信号端CLK为高电平，第二时钟信号端CLKB为低电平，上一级移位寄存器的输出端Output(N-1)为低电平，并且下一级移位寄存器的输出端Output(N+1)为高电平；
S22，在输出阶段，设置第一时钟信号端CLK为低电平，第二时钟信号端CLKB为高电平，上一级移位寄存器的输出端Output(N-1)为高电平，并且下一级移位寄存器的输出端Output(N+1)为高电平；
S23，在重置阶段，第一时钟信号端CLK为高电平，第二时钟信号端CLKB为低电平，上一级移位寄存器的输出端Output(N-1)为高 电平，并且下一级移位寄存器的输出端Output(N+1)为低电平；以及
S24，在保持阶段，上一级移位寄存器的输出端Output(N-1)和下一级移位寄存器的输出端Output(N+1)均为高电平。
在以上步骤中，关断信号端Vss持续为高电平，第一信号端Vdd1和第二信号端Vdd2中的一个为高电平，另一个为低电平。
也就是说，由于P型晶体管与N型晶体管的导通信号和关断信号的状态正好相反，故在采用P型晶体管的移位寄存器中，所有端口提供的信号均应与采用N型晶体管的移位寄存器中的情况相反，这样即可保证移位寄存器的工作状态不变，因此其详细过程在此不再详细描述。
第三实施例：
如图6所示，本实施例提供一种栅极驱动电路，其包括多个级联的上述移位寄存器。
也就是说，可将多个上述移位寄存器级联，从而形成用于驱动栅极的栅极驱动电路。
具体的，每个移位寄存器的输出端连接一条栅线，从而为该栅线提供驱动信号。同时，每个移位寄存器的输出端还与其上一级和下一级的移位寄存器相连，以作为它们的输入的一部分。当然，对于整个电路中的第一个和最后一个移位寄存器，由于其没有上一级或下一级的移位寄存器，故它们的相应的输入端可连接单独的信号端。
而多个移位寄存器的第一信号端、第二信号端、第一时钟信号端、第二时钟信号端则可各分别通过引线连接同一端口，从而用一个端口为多个移位寄存器提供信号。其中，每个移位寄存器的输出阶段(即输出导通信号时)也就是其下一级移位寄存器的充电阶段(即上一级移位寄存器输出导通信号时)，此时两移位寄存器对第一时钟信号端和第二时钟信号端的信号的需求必然是相反的。因此，相邻移位寄存器的相同的时钟信号端可分别连接不同的端口。由于移位寄存器具体的级联方式是已知的，故在此不再详细描述。
第四实施例：
本实施例提供一种显示装置，其包括阵列基板，阵列基板包括上述栅极驱动电路。
具体的，该显示装置可为液晶显示面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (15)

  1. 一种移位寄存器，包括上拉节点、第一下拉节点、第二下拉节点、第一时钟信号端、第二时钟信号端、第一信号端、第二信号端、关断信号端、和输出端，其中所述移位寄存器还包括：
    输入模块，用于将上一级移位寄存器的输出端的信号引入所述上拉节点；
    输出模块，用于根据所述上拉节点的电平，将所述第一时钟信号端的信号引入所述输出端；
    重置模块，用于在下一级移位寄存器的输出端的信号的控制下，用所述关断信号端、所述第一信号端、和所述第二信号端的信号重置所述上拉节点、所述输出端、所述第一下拉节点、和所述第二下拉节点；
    定压模块，用于根据所述上拉节点的电平，将所述关断信号端的信号引入所述第一下拉节点和所述第二下拉节点；以及
    保持模块，用于在所述第二时钟信号端的控制下，将所述第一信号端和所述第二信号端的信号分别引入所述第一下拉节点和所述第二下拉节点，从而将所述关断信号端的信号引入所述上拉节点和所述输出端。
  2. 根据权利要求1所述的移位寄存器，其中，所述输入模块包括：
    第一晶体管，其栅极和第一极连接所述上一级移位寄存器的输出端，并且其第二极连接所述上拉节点。
  3. 根据权利要求1或2所述的移位寄存器，其中，所述输出模块包括：
    第三晶体管，其栅极连接所述上拉节点，其第一极连接所述第一时钟信号端，并且其第二极连接所述输出端；以及
    存储电容，其第一极连接所述上拉节点，并且其第二极连接所 述输出端。
  4. 根据权利要求1至3中任意一项所述的移位寄存器，其中，所述重置模块包括：
    第二晶体管，其栅极连接所述下一级移位寄存器的输出端，其第一极连接所述上拉节点，并且其第二极连接所述关断信号端；
    第四晶体管，其栅极连接所述下一级移位寄存器的输出端，其第一极连接所述输出端，并且其第二极连接所述关断信号端；
    第七晶体管，其栅极连接所述下一级移位寄存器的输出端，其第一极连接所述第一信号端，并且其第二极连接所述第一下拉节点；以及
    第八晶体管，其栅极连接所述下一级移位寄存器的输出端，其第一极连接所述第二信号端，并且其第二极连接所述第二下拉节点。
  5. 根据权利要求1至4中任意一项所述的移位寄存器，其中，所述定压模块包括：
    第九晶体管，其栅极连接所述上拉节点，其第一极连接所述第一下拉节点，并且其第二极连接所述关断信号端；以及
    第十晶体管，其栅极连接所述上拉节点，其第一极连接所述第二下拉节点，并且其第二极连接所述关断信号端。
  6. 根据权利要求5所述的移位寄存器，其中，所述保持模块包括：
    第五晶体管，其栅极连接所述第二时钟信号端，其第一极连接所述第一信号端，并且其第二极连接所述第一下拉节点；
    第六晶体管，其栅极连接所述第二时钟信号端，其第一极连接所述第二信号端，并且其第二极连接所述第二下拉节点；
    第十一晶体管，其栅极连接所述第一下拉节点，其第一极连接所述上拉节点，并且其第二极连接所述关断信号端；
    第十二晶体管，其栅极连接所述第一下拉节点，其第一极连接 所述输出端，并且其第二极连接所述关断信号端；
    第十三晶体管，其栅极连接所述第二下拉节点，其第一极连接所述上拉节点，并且其第二极连接所述关断信号端；以及
    第十四晶体管，其栅极连接所述第二下拉节点，其第一极连接所述输出端，并且其第二极连接所述关断信号端。
  7. 根据权利要求6所述的移位寄存器，其中，
    所述第九晶体管的寄生电阻小于所述第五晶体管的寄生电阻；以及
    所述第十晶体管的寄生电阻小于所述第六晶体管的寄生电阻。
  8. 根据权利要求7所述的移位寄存器，其中，
    所有所述晶体管均为N型晶体管。
  9. 根据权利要求7所述的移位寄存器，其中，
    所有所述晶体管均为P型晶体管。
  10. 一种栅极驱动电路，包括多个级联的移位寄存器，其中，
    所述移位寄存器为权利要求1至9中任意一项所述的移位寄存器。
  11. 一种显示装置，包括阵列基板，其中，
    所述阵列基板包括权利要求10所述的栅极驱动电路。
  12. 一种移位寄存器的驱动方法，其中，所述移位寄存器为权利要求1至9中任意一项所述的移位寄存器，所述移位寄存器的驱动方法包括：
    在充电阶段，通过所述输入模块将所述上一级移位寄存器的输出端的信号引入所述上拉节点；
    在输出阶段，通过所述输出模块将所述第一时钟信号端的信号 引入所述输出端，使所述输出端输出导通信号；
    在重置阶段，通过所述重置模块用所述关断信号端、所述第一信号端、和所述第二信号端的信号来重置所述上拉节点、所述输出端、所述第一下拉节点、和所述第二下拉节点；以及
    在保持阶段，通过所述保持模块将所述关断信号端的信号引入所述上拉节点和所述输出端，使所述输出端持续输出关断信号。
  13. 根据权利要求12所述的移位寄存器的驱动方法，其中，所述移位寄存器为权利要求8所述的移位寄存器，所述移位寄存器的驱动方法还包括：
    在充电阶段，设置所述第一时钟信号端为低电平，所述第二时钟信号端为高电平，所述上一级移位寄存器的输出端为高电平，并且所述下一级移位寄存器的输出端为低电平；
    在输出阶段，设置所述第一时钟信号端为高电平，所述第二时钟信号端为低电平，所述上一级移位寄存器的输出端为低电平，并且所述下一级移位寄存器的输出端为低电平；
    在重置阶段，设置所述第一时钟信号端为低电平，所述第二时钟信号端为高电平，所述上一级移位寄存器的输出端为低电平，并且所述下一级移位寄存器的输出端为高电平：
    在保持阶段，设置所述上一级移位寄存器的输出端和所述下一级移位寄存器的输出端为低电平；
    在以上步骤中，所述关断信号端持续为低电平，所述第一信号端和所述第二信号端中的一个为高电平，另一个为低电平。
  14. 根据权利要求12所述的移位寄存器的驱动方法，其中，所述移位寄存器为权利要求9所述的移位寄存器，所述移位寄存器的驱动方法还包括：
    在充电阶段，设置所述第一时钟信号端为高电平，所述第二时钟信号端为低电平，所述上一级移位寄存器的输出端为低电平，并且所述下一级移位寄存器的输出端为高电平；
    在输出阶段，设置所述第一时钟信号端为低电平，所述第二时钟信号端为高电平，所述上一级移位寄存器的输出端为高电平，并且所述下一级移位寄存器的输出端为高电平；
    在重置阶段，设置所述第一时钟信号端为高电平，所述第二时钟信号端为低电平，所述上一级移位寄存器的输出端为高电平，并且所述下一级移位寄存器的输出端为低电平：
    在保持阶段，设置所述上一级移位寄存器的输出端和所述下一级移位寄存器的输出端为高电平；
    在以上步骤中，所述关断信号端持续为高电平，所述第一信号端和所述第二信号端中的一个为高电平，另一个为低电平。
  15. 根据权利要求13或14所述的移位寄存器驱动方法，还包括：
    切换所述第一信号端的电平和所述第二信号端的电平的步骤，以使所述第一信号端和所述第二信号端中原为高电平的变为低电平，原为低电平的变为高电平。
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JP2018534715A (ja) 2018-11-22
EP3352160A4 (en) 2019-02-27
KR101913519B1 (ko) 2018-10-30
KR20170056503A (ko) 2017-05-23
US20170270892A1 (en) 2017-09-21
JP6966199B2 (ja) 2021-11-10
US9953611B2 (en) 2018-04-24
CN105118414A (zh) 2015-12-02
CN105118414B (zh) 2017-07-28

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