WO2017113759A1 - 电容感测电路 - Google Patents

电容感测电路 Download PDF

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Publication number
WO2017113759A1
WO2017113759A1 PCT/CN2016/090471 CN2016090471W WO2017113759A1 WO 2017113759 A1 WO2017113759 A1 WO 2017113759A1 CN 2016090471 W CN2016090471 W CN 2016090471W WO 2017113759 A1 WO2017113759 A1 WO 2017113759A1
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WIPO (PCT)
Prior art keywords
phase
noise
circuit
sensing circuit
capacitance sensing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2016/090471
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English (en)
French (fr)
Inventor
文亚南
梁颖思
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen Goodix Technology Co Ltd
Original Assignee
Shenzhen Huiding Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen Huiding Technology Co Ltd filed Critical Shenzhen Huiding Technology Co Ltd
Priority to EP16880556.2A priority Critical patent/EP3252579B1/en
Priority to KR1020177022550A priority patent/KR101964539B1/ko
Publication of WO2017113759A1 publication Critical patent/WO2017113759A1/zh
Priority to US15/657,588 priority patent/US10520533B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/0418—Control or interface arrangements specially adapted for digitisers for error correction or compensation, e.g. based on parallax, calibration or alignment
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G01R27/26—Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants ; Measuring impedance or related variables
    • G01R27/2605—Measuring capacitance
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/94—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00 characterised by the way in which the control signal is generated
    • H03K2217/96—Touch switches
    • H03K2217/9607—Capacitive touch switches
    • H03K2217/96071—Capacitive touch switches characterised by the detection principle
    • H03K2217/960725—Charge-transfer

Definitions

  • the present patent application belongs to the field of touch technologies, and in particular, to a capacitive sensing circuit that can generate an input signal according to a noise phase.
  • the operational interfaces of various electronic products have gradually become more humanized in recent years.
  • the user can directly operate on the screen with a finger or a stylus, input information/text/pattern, and save the trouble of using an input device such as a keyboard or a button.
  • the touch panel usually consists of an inductive panel and a display disposed behind the inductive panel. The electronic device judges the meaning of the touch according to the position touched by the user on the sensing panel and the picture presented by the display at the time, and performs the corresponding operation result.
  • Capacitive touch technology utilizes the amount of capacitance change of the capacitor to be tested in the circuit under test to interpret the touch event.
  • the existing capacitive touch technology can be divided into self-capacitance and mutual capacitance (Mutual).
  • -Capacitance the capacitive sensing circuit in the self-capacitive touch panel or the mutual capacitive touch panel can apply a periodic input signal to the circuit to be tested, and receive the output signal from the circuit to be tested, through the analytical output.
  • the phase or amplitude of the signal is used to calculate the amount of change in the capacitor to be tested in the circuit under test to determine the presence or absence of a touch event and the actual coordinate position.
  • the input signal has a specific frequency
  • the capacitive sensing circuit of the touch panel is close to the liquid crystal display module, the charging module, or other devices, it is susceptible to being received from the surrounding liquid crystal display module, the charging module, or other devices within the specific frequency. Electromagnetic interference.
  • the input signal of the capacitance sensing circuit and the signal of the liquid crystal display module, the charging module or other device are not subjected to any synchronization processing, so that the external electromagnetic wave interference causes the touch event of the capacitance sensing circuit to be interpreted. Negative impact. Therefore, there is a need for improvement in the prior art.
  • One technical problem to be solved by an embodiment of the present invention is to provide a capacitance sensing circuit that can generate an input signal according to a noise phase to improve the disadvantages of the prior art.
  • One embodiment of the present invention is implemented by a capacitive sensing circuit for sensing a capacitance to be tested of a circuit to be tested, the circuit to be tested receiving an input signal and generating an output signal, and the capacitive sensing circuit includes :
  • a capacitance determining circuit coupled to the circuit to be tested, for determining a capacitance of the capacitor to be tested according to the output signal
  • phase detecting unit configured to receive the noise and detect a first phase of the noise
  • phase calculation unit coupled to the phase detection unit for receiving the noise and the first phase, and calculating an optimal phase according to the noise and the first phase;
  • the first waveform generator is coupled to the phase calculation unit for generating the input signal according to the optimal phase.
  • the capacitance sensing circuit of an embodiment of the present invention generates an input signal related to the phase of the noise by using the input signal generator to reduce the energy related to the noise in the mixed output signal of the capacitance determining circuit, that is, reducing the noise to determine the capacitance to be measured. Impact to improve the performance of the overall capacitive sensing circuit.
  • FIG. 1 is a schematic diagram of a capacitance sensing circuit according to an embodiment of the present invention.
  • FIG. 2 is a schematic diagram of a phase calculation unit according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of an input signal generator according to an embodiment of the present invention.
  • phase calculation unit 4 is a schematic diagram of another phase calculation unit according to an embodiment of the present invention.
  • FIG. 5 to FIG. 9 are schematic diagrams of a phase detecting unit according to an embodiment of the present invention.
  • FIG. 10 is a schematic diagram of a capacitance judging circuit according to an embodiment of the present invention.
  • FIG. 11 is a waveform diagram of a plurality of signals provided by an embodiment of the present invention.
  • FIG. 12 is a schematic diagram of another capacitance determining circuit according to an embodiment of the present invention.
  • FIG. 13 is a schematic diagram of still another capacitance determining circuit according to an embodiment of the present invention.
  • FIG. 14 is a schematic diagram of still another phase calculation unit according to an embodiment of the present invention.
  • FIG. 15 is a schematic diagram of another input signal generator according to an embodiment of the present invention.
  • FIG. 16 is a schematic diagram of still another phase calculation unit according to an embodiment of the present invention.
  • FIG. 1 is a schematic diagram of a capacitance sensing circuit 10 according to an embodiment of the present invention.
  • the capacitance sensing circuit 10 includes a circuit under test 100, a capacitance determining circuit 102, and an input signal generator 104.
  • the circuit to be tested 100 is coupled to the input signal generator 104, and the capacitance determining circuit 102 is coupled to the circuit 100 to be tested.
  • the capacitance sensing circuit 10 inputs the input signal TX to the circuit under test 100, and the capacitance determining circuit 102 receives the output signal RX from the circuit under test 100, and calculates the phase or amplitude of the output signal RX to calculate the to-be-tested circuit 100 to be tested. The amount of change in the capacitance CUT.
  • the input signal generator 104 receives the noise N and generates an input signal TX based on the noise N.
  • the input signal generator 104 includes a phase detecting unit 140, a phase calculating unit 142, and a waveform generator 144.
  • the phase detecting unit 140 is configured to receive the noise N and detect the first phase ⁇ 1 of the noise N and the first frequency f1.
  • the phase calculating unit 142 is coupled to the phase detecting unit 140 for detecting according to the phase detecting unit 140. Calculating the best phase by measuring the first phase ⁇ 1 and the first frequency f1 And the best phase Transfer to waveform generator 144.
  • the waveform generator 144 is coupled to the phase detecting unit 140 and the phase calculating unit 142 for using the first phase ⁇ 1 and the optimal phase.
  • the input signal TX is generated.
  • FIG. 10 is a schematic diagram of the capacitance judging circuit 202.
  • Capacitance determination circuit 102 can be implemented using capacitance determination circuit 202.
  • the capacitance judging circuit 202 includes a mixer 120, an integrator 122, and a judging module 124.
  • the mixer 120 can include a multiplier MP for mixing the output signal RX with the local signal LO and producing an output signal V1, wherein the local signal LO is associated with the input signal TX.
  • the local signal LO is the input signal TX.
  • the integrator 122 integrates the output signal V1 (ie, filters out the high frequency portion of the mixed output signal), and the determining module 124 determines the capacitance CUT to be tested in the circuit under test 100 according to the mixed output signal VOUT of the integrator 122. The amount of change.
  • the phase calculation unit 142 can calculate the optimal phase by optimizing the algorithm.
  • n(t; ⁇ 1 ) represents a waveform function of noise N as a function of time when the phase of the noise N is the first phase ⁇ 1 ; and x(t; ⁇ 2 ) represents the phase of the input signal TX as the second phase When ⁇ 2 , the waveform of the input signal TX changes with time.
  • the phase calculation unit 142 receives the phase of the noise N from the phase detecting unit 140 as the first phase ⁇ 1
  • the waveform generator 144 is based on the optimum phase.
  • the generated input signal TX can minimize the energy related to the noise in the mixed output signal VOUT, that is, the influence of the noise N on determining the capacitance CUT to be tested is minimized to improve the performance of the capacitance sensing circuit 10.
  • the phase calculation unit may mix the noise N by using a plurality of local signals having different phases, generate a plurality of mixed wave output signals, and select the first local signal whose energy of the mixed output signal is the smallest, and the first The first local phase corresponding to a local signal is the optimal phase.
  • FIG. 2 is a schematic diagram of a phase calculating unit 242 according to an embodiment of the present invention.
  • the phase calculation unit 242 includes the mixers MX1 to MXK, the integrators IG1 to IGK, and the decision unit 210.
  • the mixers MX1 to MXK respectively mix the noise N with the local signals LO_1 to LO_K, and the local signals LO_1 to LO_K respectively have K. Different phases. For example, in one embodiment, the phase of the local signal LO_1 is 0, the phase of the local signal LO_2 is ⁇ /K, the phase of the local signal LO_3 is 2 ⁇ /K, and so on, and the phase of the local signal LO_K is (K) -1) ⁇ /K.
  • the integrators IG1 to IGK integrate the output signals of the mixers MX1 to MXK to generate the mixed output signals VMX1 to VMXK.
  • the decision unit 210 selects the mixed wave output signal VMXS having the smallest energy from the mixed wave output signals VMX1 to VMXK, wherein the local signal corresponding to the mixed wave output signal VMXS is the local signal LO_S, and the phase of the local signal LO_S is (S- 1) ⁇ /K. Therefore, the phase calculation unit 242 can output the optimal phase Is (S-1) ⁇ /K.
  • the number K of the mixers MX1 ⁇ MXK (or the integrators IG1 ⁇ IGK) is related to the resolution of the phase calculating unit 242, that is, when the number K is larger, the phase calculating unit 242 obtains the optimum phase (ie, (S-1) ⁇ / K) will be closer to the optimum phase calculated according to (Formula 1).
  • FIG. 3 is a schematic diagram of an input signal generator 304 according to an embodiment of the present invention.
  • the input signal generator 304 is similar to the input signal generator 104, so the same components follow the same symbols.
  • the input signal generator 304 includes a phase calculation unit 342 that includes a mixer 312 and a decision unit 310.
  • input signal generator 304 The operation of input signal generator 304 is illustrated below. Assume that the decision unit 310 starts with the best phase output. The optimum phase output by the waveform generator 144 according to the decision unit 310 After the input signal TX is generated, and the input signal TX is fed back to the mixer 312 (representing the waveform generator 144 coupled to the mixer 312), the mixer 312 is based on the optimum phase. The generated input signal TX mixes the noise N, and the decision unit 310 can calculate another optimal phase according to the mixed output signal VMO3 of the mixer 312.
  • Waveform generator 144 is then based on the optimal phase Generating the input signal TX, the mixer 312 will again be based on the optimal phase
  • the generated input signal TX is mixed with the noise N, so that the decision unit 310 can calculate another optimal phase. So iterating until the best phase calculated for the iteration The best phase calculated from the previous iteration The difference between the differences is less than a specific range, or the number of iterations is greater than a specific value. In this way, even if the noise N changes its phase due to a specific factor at different times, the input signal generator 304 can continuously track the phase of the noise N and correspondingly generate the input signal TX to reduce the noise N to determine the capacitance to be tested. The impact of the CUT to improve the performance of the overall capacitive sensing circuit.
  • FIG. 4 is a schematic diagram of a phase calculating unit 442 according to an embodiment of the present invention.
  • the phase calculation unit 442 includes a mixer 412, a decision unit 410, and a waveform generator 444. Similar to input signal generator 304, decision unit 410 initially generates phase ⁇ 2,0 , and waveform generator 444 generates local signal VLO to mixer 412 based on phase ⁇ 2,0 , which combines noise N with local The signal VLO is mixed and a mixed output signal VMO4 is generated, and the decision unit 410 generates another phase ⁇ 2,1 according to the mixed output signal VMO4.
  • the phase calculation unit 442 includes a waveform generator 444 for performing a recursive feedback operation.
  • the feedback source of the mixer 412 is the waveform generator 444; and in the input signal generator 304, the feedback source of the mixer 312 is the waveform generator 144.
  • the phase calculating unit 442 can continuously track the phase of the noise N and correspondingly generate the input signal TX to reduce the noise N pair to interpret the capacitance CUT to be tested. The effect of improving the performance of the overall capacitive sensing circuit.
  • the capacitance sensing circuit 10 generates the noise N by using the input signal generator 104.
  • the phase dependent input signal TX is used to reduce the energy associated with the noise in the mixed output signal VOUT in the capacitance determining circuit 102.
  • the present invention can further reduce the influence of the noise N on the interpretation of the capacitance CUT to be tested, so as to improve the performance of the overall capacitance sensing circuit.
  • phase detection unit is not limited.
  • FIG. 5 to FIG. 9. 5 to 9 are schematic diagrams of phase detecting units 540 to 940 according to an embodiment of the present invention.
  • the phase detecting unit 540 includes a diode, a capacitor, and a transistor.
  • the diode is configured to receive the noise N.
  • the first end of the capacitor is coupled to the diode, and the second end of the capacitor is coupled to the ground.
  • the transistor is coupled between the first end and the second end of the capacitor.
  • the phase detecting unit 640 is similar to the phase detecting unit 540, and is different from the phase detecting unit 540 in that the phase detecting unit 640 further includes operational amplifiers OP1 and OP2.
  • the negative input terminal of the operational amplifier OP1 and the operational amplifier OP2 (labeled with a "-" sign) is coupled to the output terminal of the operational amplifier OP2, and the positive input terminal of the operational amplifier OP2 (labeled with a "+” sign) is coupled to the diode and Between the capacitors, the positive input terminal of the operational amplifier OP1 (labeled with a "+” sign) is used to receive the noise N, and the transistor is coupled between the output terminal of the operational amplifier OP2 and the second end of the capacitor.
  • the phase detecting unit 740 includes a hysteresis comparator HCMP, which is a comparator with hysteresis protection, such as a Schmitt Trigger.
  • the negative input of the hysteresis comparator HCMP (labeled with a "-" sign) is used to receive the threshold voltage VTH, and the positive input terminal (labeled with a "+” sign) is used to receive the noise N.
  • the phase detecting unit 840 is similar to the phase detecting unit 740, and is different from the phase detecting unit 740 in that the phase detecting unit 840 replaces the hysteresis in the phase detecting unit 740 with an operational amplifier OP and a de-glitch 800.
  • the function of the comparator HCMP is similar to the phase detecting unit 740, and is different from the phase detecting unit 740 in that the phase detecting unit 840 replaces the hysteresis in the phase detecting unit 740 with an operational amplifier OP and a de-glitch 800.
  • the function of the comparator HCMP The function of the comparator HCMP.
  • the phase detecting unit 940 includes hysteresis comparators HCMP1 and HCMP2.
  • the positive input terminals of the hysteresis comparators HCMP1 and HCMP2 (labeled with "+") are used to receive the noise N.
  • the negative input terminals of the hysteresis comparators HCMP1 and HCMP2 (labeled with "-") receive the threshold voltages VTHp and VTHn, respectively.
  • the outputs of the hysteresis comparators HCMP1 and HCMP2 are coupled to an OR gate 900.
  • the phase detecting units 540 to 940 can detect the first phase ⁇ 1 of the noise N and the first frequency f1, and supply the first phase ⁇ 1 and the first frequency f1 to the waveform generator.
  • the input signal generator of the present invention can generate an input signal TX based on the phase of the noise N.
  • the manner in which the waveform generator 144 generates the input signal TX according to the optimal phase is not limited.
  • the waveform generator 144 can directly generate a phase difference from the parent signal to the optimum phase according to a parent signal.
  • Input signal TX; or waveform generator 144 can optimize phase It is also within the scope of the invention to convert to the delay time ⁇ t opt and to generate an input signal TX having a time difference of ⁇ t opt from the parent signal.
  • FIG. 11 is a waveform diagram of the mother signal SIN and the input signals TX1 and TX2.
  • the waveform generator 144 can directly generate the input signal TX1, wherein the phase difference between the input signal TX1 and the mother signal SIN is the optimal phase.
  • the waveform generator 144 can also optimize the phase.
  • the conversion becomes the delay time ⁇ t opt and the input signal TX2 is generated, wherein the time difference between the input signal TX2 and the mother signal SIN is the delay time ⁇ t opt , which is also within the scope of the present invention.
  • the phase calculation unit of this embodiment can be changed in accordance with the circuit configuration of the capacitance determination circuit.
  • the phase calculating units 242, 342, and 442 each include a mixer.
  • the capacitance judging circuit is not limited to including a mixer.
  • FIG. 12 is a schematic diagram of the capacitance judging circuit 302.
  • the capacitance determination circuit 302 includes a charge transfer circuit 320 and a determination module 324.
  • the charge transfer circuit 320 includes a switch S1, S2 and a capacitor C1.
  • the first end of the switch S1 is used to receive the output signal RX, the second end of the switch S1 is coupled to the first end of the capacitor C1, and the first end of the switch S2 is coupled. Connected to the first end of the capacitor C1, the second end of the switch S2 and the second end of the capacitor C1 are coupled to the ground.
  • the switch S1 is controlled by the control signal phi. By appropriately controlling the input signal TX and the control signal phi, the charge stored in the capacitor CUT to be tested can be transferred to the capacitor C1, and the switch S2 is used to reset or empty the capacitor. The charge of C1.
  • Capacitance judgment Circuit 402 includes a charge transfer circuit 420 and a decision module 424.
  • the charge transfer circuit 420 includes a switch S3 and an integration circuit 422.
  • the switch S3 is also controlled by the control signal phi.
  • the integration circuit 422 includes an amplifier Amp, a capacitor C2 and a switch S4.
  • the capacitor C2 and the switch S4 are coupled to the negative input terminal of the amplifier Amp ( Between the "-" sign and the output.
  • the phase calculating unit of the present embodiment may include at least one charge transfer circuit.
  • FIG. 14 is a schematic diagram of a phase calculation unit 542 according to an embodiment of the present invention.
  • the phase calculation unit 542 is similar in structure to the phase calculation unit 242 except that the phase calculation unit 542 replaces the mixers MX1 to MXK and the integrators IG1 to IGK in the phase calculation unit 242 by the charge transfer circuits CSC_1 to CSC_K.
  • the charge transfer circuits CSC_1 to CSC_K generate signals VO1 to VOK based on the noise N, and the decision unit 510 included in the phase calculation unit 542 calculates the optimum phase based on the signals VO1 to VOK.
  • the charge transfer circuits CSC_1 to CSC_K can be implemented by the circuit structure of the charge transfer circuit 320 or the charge transfer circuit 420, and the switch S1 or the switch S3 (not shown in FIG. 14) of the charge transfer circuits CSC_1 to CSC_K are respectively subjected to The control signals phi_1 ⁇ phi_K are controlled, and the first ends of the switches S1 or S3 in the CSC_1 ⁇ CSC_K are used to receive the noise N.
  • the operation principle of the phase calculation unit 542 is similar to that of the phase calculation unit 242, so it is briefly described as follows.
  • the control signals phi_1 to phi_K have K different phases, respectively.
  • the phase of the control signal phi_1 is 0, the phase of the control signal phi_2 is ⁇ /K, the phase of the control signal phi_3 is 2 ⁇ /K, and so on, and the phase of the control signal phi_K is (K-1) ) ⁇ / K.
  • the charge transfer circuits CSC_1 to CSC_K receive the noise N and generate signals VO1 to VOK in accordance with the control signals phi_1 to phi_K, respectively.
  • the decision unit 510 selects the signal VOS having the smallest energy from the signals VO1 VVOK, wherein the control signal corresponding to the signal VOS is the control signal phi_S, and the phase of the control signal phi_S is (S-1) ⁇ /K. Therefore, the phase calculation unit 542 can output the optimal phase Is (S-1) ⁇ /K.
  • FIG. 15 is respectively an input signal generator 604 according to an embodiment of the present invention.
  • Schematic diagram. Input signal generator 604 is similar in construction to input signal generator 304, so the same components follow the same symbols.
  • the input signal generator 604 includes a phase calculation unit 642 that includes a charge transfer circuit 612 and a decision unit 610.
  • the charge transfer circuit 612 can be implemented by the circuit structure of the charge transfer circuit 320 or the charge transfer circuit 420, wherein the switch S1 or the switch S3 of the charge transfer circuit 612 (not shown in FIG. 15) is controlled by the waveform generator 144.
  • the input signal TX, and the first end of the switch S1 or the switch S3 in the charge transfer circuit 612 is used to receive the noise N. That is, the input signal generator 604 replaces the mixer 312 in the input signal generator 304 by the charge transfer circuit 612. The rest of the operation principle is the same as that of the input signal generator 304, and details are not described herein again.
  • FIG. 16 is a schematic diagram of a phase calculation unit 742 according to an embodiment of the present invention.
  • the phase calculation unit 742 is similar in structure to the phase calculation unit 442, so the same components follow the same symbols.
  • the phase calculation unit 742 includes a charge transfer circuit 712, a decision unit 710, and a waveform generator 744.
  • the waveform generator 744 is used to generate the control signal phi.
  • the charge transfer circuit 712 can be implemented by the circuit structure of the charge transfer circuit 320 or the charge transfer circuit 420, wherein the switch S1 or the switch S3 of the charge transfer circuit 712 (not shown) 16) Controlled by the control signal phi generated by the waveform generator 744, the first end of the switch S1 or switch S3 of the charge transfer circuit 712 is used to receive the noise N. That is, the phase calculation unit 742 replaces the mixer 412 in the phase calculation unit 442 by the charge transfer circuit 712, and the phase calculation unit 742 replaces the local signal VLO in the phase calculation unit 442 with the control signal phi, and the remaining operation principle and phase calculation Unit 442 is the same and will not be described again here.
  • the capacitance sensing circuit of the embodiment uses an input signal generator to generate an input signal related to the phase of the noise, so as to reduce the energy related to the noise in the mixed-wave output signal in the capacitance determining circuit, that is, to reduce the noise.

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  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
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  • Measurement Of Resistance Or Impedance (AREA)
  • Amplifiers (AREA)
  • Electronic Switches (AREA)

Abstract

本发明一个实施例适用于触控技术领域，提供一种电容感测电路，用来感测待测电路的待测电容，包含：电容判断电路，耦接于待测电路，根据输出信号判断待测电容的电容大小；以及输入信号产生器，耦接于待测电路，根据噪声产生输入信号，输入信号产生器包含有：相位侦测单元，接收噪声并侦测噪声的第一相位；相位计算单元，耦接于相位侦测单元，接收噪声和第一相位，并根据噪声和第一相位计算最佳相位；以及第一波形产生器，耦接于相位计算单元，根据最佳相位产生输入信号。本发明一个实施例利用输入信号产生器产生与噪声相位相关的输入信号，以降低电容判断电路输出中相关于噪声的能量，即降低噪声对判断待测电容的影响，以提升整体电容感测电路的效能。

Description

电容感测电路 技术领域
本专利申请属于触控技术领域，尤其涉及一种可根据噪声相位产生输入信号的电容感测电路。
背景技术
随着科技日益进步，近年来各种电子产品的操作接口逐渐人性化。举例而言，透过触控面板，使用者可直接以手指或触控笔在屏幕上操作、输入信息/文字/图样，省去使用键盘或按键等输入设备的麻烦。实际上，触控面板通常系由感应面板和设置于感应面板后方的显示器组成。电子装置是根据用户在感应面板上所触碰的位置，以及当时显示器所呈现的画面，来判断该次触碰的意涵，并执行相对应的操作结果。
电容式触控技术利用感测待测电路中待测电容的电容变化量来判读触碰事件，现有的电容式触控技术可分为自容式(Self-Capacitance)和互容式(Mutual-Capacitance)两种，自容式触控面板或互容式触控面板中的电容感测电路可将周期性的输入信号施加于待测电路，并从待测电路接收输出信号，通过解析输出信号的相位或幅值来计算待测电路中待测电容的变化量，以判断触碰事件的产生与否和实际坐标位置。
然而，因输入信号具有特定频率，当触控面板的电容感测电路很靠近液晶显示模块、充电模块或其他装置时，在该特定频率内易受到来自周围液晶显示模块、充电模块或其他装置的电磁波干扰。在现有技术中，电容感测电路的输入信号与液晶显示模块、充电模块或其他装置的信号并未经过任何同步处理，而使得外来的电磁波干扰对电容感测电路进行触碰事件的判读造成负面影响。因此，现有技术有改善的必要。
发明内容
本发明一个实施例所要解决的一个技术问题在于提供一种可根据噪声相位产生输入信号的电容感测电路，以改善现有技术的缺点。
本发明一个实施例是这样实现的，一种电容感测电路，用来感测待测电路的待测电容，所述待测电路接收输入信号并产生输出信号，所述电容感测电路包含有：
电容判断电路，耦接于所述待测电路，用来根据所述输出信号判断所述待测电容的电容大小；以及
输入信号产生器，耦接于所述待测电路，用来根据噪声产生所述输入信号，所述输入信号产生器包含有：
相位侦测单元，用来接收所述噪声并侦测所述噪声的第一相位；
相位计算单元，耦接于所述相位侦测单元，用来接收所述噪声和所述第一相位，并根据所述噪声和所述第一相位计算最佳相位；以及
第一波形产生器，耦接于所述相位计算单元，用来根据所述最佳相位产生所述输入信号。
本发明一个实施例的电容感测电路利用输入信号产生器产生与噪声的相位相关的输入信号，以降低电容判断电路混波输出信号中相关于噪声的能量，即降低噪声对判断待测电容的影响，以提升整体电容感测电路的效能。
附图说明
图1是本发明一个实施例提供的电容感测电路的示意图；
图2是本发明一个实施例提供的相位计算单元的示意图；
图3是本发明一个实施例提供的输入信号产生器的示意图；
图4是本发明一个实施例提供的另一相位计算单元的示意图；
图5～图9是本发明一个实施例提供的相位侦测单元的示意图；
图10是本发明一个实施例提供的电容判断电路的示意图；
图11是本发明一个实施例提供的多个信号的波形图；
图12是本发明一个实施例提供的另一电容判断电路的示意图；
图13是本发明一个实施例提供的又一电容判断电路的示意图；
图14是本发明一个实施例提供的又一相位计算单元的示意图；
图15是本发明一个实施例提供的另一输入信号产生器的示意图；
图16是本发明一个实施例提供的又一相位计算单元的示意图。
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明部分实施例进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
请参考图1，图1为本发明一个实施例中电容感测电路10的示意图。电容感测电路10包含有待测电路100、电容判断电路102和输入信号产生器104。待测电路100耦接于输入信号产生器104，而电容判断电路102耦接于待测电路100。
电容感测电路10将输入信号TX输入至待测电路100，而电容判断电路102从待测电路100接收输出信号RX，通过解析输出信号RX的相位或幅值来计算待测电路100中待测电容CUT的变化量。输入信号产生器104接收噪声N，并根据噪声N产生输入信号TX，输入信号产生器104包含有相位侦测单元140、相位计算单元142和波形产生器144。相位侦测单元140用来接收噪声N并侦测噪声N的第一相位φ1和第一频率f1，相位计算单元142耦接于相位侦测单元140，用来根据相位侦测单元140所侦测的第一相位φ1和第一频率f1计算最佳相位
Figure PCTCN2016090471-appb-000001
并将最佳相位
Figure PCTCN2016090471-appb-000002
传送至波形产生器144。波形产生器144耦接于相位侦测单元140和相位计算单元142，用来根据第一相位φ1和最佳相位
Figure PCTCN2016090471-appb-000003
产 生输入信号TX。
对电容判断电路102简述如下。请参考图10，图10为电容判断电路202的示意图。电容判断电路102可利用电容判断电路202来实现。如图10所示，电容判断电路202包含混波器120、积分器122和判断模组124。混波器120可包含乘法器MP，用来将输出信号RX与本地信号LO进行混波，并产生输出信号V1，其中本地信号LO相关于输入信号TX。在一实施例中，本地信号LO即为输入信号TX。积分器122对输出信号V1进行积分(即将混波输出信号的高频部份滤除)，判断模组124即根据积分器122的混波输出信号VOUT判断待测电路100中待测电容CUT的变化量。
为了降低噪声N对判断待测电容CUT的影响，较佳地，相位计算单元142可通过优化算法以计算最佳相位
Figure PCTCN2016090471-appb-000004
Figure PCTCN2016090471-appb-000005
其中n(t；φ1)代表当噪声N的相位为第一相位φ1时，噪声N随时间变化的波形函数；而x(t；φ2)代表当输入信号TX的相位为第二相位φ2时，输入信号TX随时间变化的波形函数。换句话说，在相位计算单元142从相位侦测单元140接收到噪声N的相位为第一相位φ1的情况下，当最佳相位
Figure PCTCN2016090471-appb-000006
为根据(式1)所计算出的计算结果时，波形产生器144根据最佳相位
Figure PCTCN2016090471-appb-000007
所产生的输入信号TX可使得混波输出信号VOUT中相关于噪声的能量为最小，即将噪声N对判断待测电容CUT的影响降至最低，以提升电容感测电路10的效能。
另一方面，相位计算单元可利用具有不同相位的多个本地信号对噪声N进行混波，产生多个混波输出信号，并选取混波输出信号的能量为最小的第一本地信号，而第一本地信号所对应的第一本地相位即为最佳相位。具体来说，请参考图2，图2为本发明实施例中相位计算单元242的示意图。相位计算单元242包含混波器MX1～MXK、积分器IG1～IGK和决策单元210，混波器MX1～ MXK分别以本地信号LO_1～LO_K对噪声N进行混波，本地信号LO_1～LO_K分别具有K种不同的相位。举例来说，在一实施例中，本地信号LO_1的相位为0，本地信号LO_2的相位为π/K，本地信号LO_3的相位为2π/K，以此类推，本地信号LO_K的相位为(K-1)π/K。混波器MX1～MXK对噪声N进行混波后，积分器IG1～IGK分别对混波器MX1～MXK的输出信号进行积分而产生混波输出信号VMX1～VMXK。决策单元210自混波输出信号VMX1～VMXK中选择具有最小能量的混波输出信号VMXS，其中，对应于混波输出信号VMXS的本地信号为本地信号LO_S，且本地信号LO_S的相位为(S-1)π/K。因此，相位计算单元242可输出最佳相位
Figure PCTCN2016090471-appb-000008
为(S-1)π/K。其中，混波器MX1～MXK(或积分器IG1～IGK)的数量K相关于相位计算单元242的分辨率，也就是说，当数量K越大，相位计算单元242所得到最佳相位(即(S-1)π/K)就会越接近根据(式1)所计算出的最佳相位。
另外，相位计算单元也可利用递归式(Iterative)反馈的方式计算出最佳相位。请参考图3，图3为本发明实施例中输入信号产生器304的示意图，输入信号产生器304与输入信号产生器104类似，故相同组件沿用相同符号。与输入信号产生器104不同的是，输入信号产生器304包含相位计算单元342，相位计算单元342包含混波器312和决策单元310。
输入信号产生器304的工作原理说明如下。假设决策单元310开始时输出最佳相位
Figure PCTCN2016090471-appb-000009
在波形产生器144根据决策单元310输出的最佳相位
Figure PCTCN2016090471-appb-000010
产生输入信号TX，且输入信号TX被反馈至混波器312(代表波形产生器144耦接于混波器312)后，混波器312以根据最佳相位
Figure PCTCN2016090471-appb-000011
所产生的输入信号TX对噪声N进行混波，决策单元310即可根据混波器312的混波输出信号VMO3计算出另一最佳相位
Figure PCTCN2016090471-appb-000012
波形产生器144再根据最佳相位
Figure PCTCN2016090471-appb-000013
产生输入信号TX，混波器312再将根据最佳相位
Figure PCTCN2016090471-appb-000014
所产生的输入信号TX与噪声N进行混波，使 得决策单元310可计算出又一最佳相位
Figure PCTCN2016090471-appb-000015
如此迭代下去，直到当次迭代计算出的最佳相位
Figure PCTCN2016090471-appb-000016
与前一次迭代计算出的最佳相位
Figure PCTCN2016090471-appb-000017
之间的差距小于一特定范围，或是迭代次数大于一特定值时为止。如此一来，即使在不同时间噪声N因特定因素而造成其相位的变化，输入信号产生器304依然可不断地追踪噪声N的相位而相应产生输入信号TX，以降低噪声N对判读待测电容CUT的影响，以提升整体电容感测电路的效能。
除此之外，相位计算单元可还包含一波形产生器，以递归式反馈的方式计算出最佳相位。请参考图4，图4为本发明实施例中相位计算单元442的示意图。相位计算单元442包含有混波器412、决策单元410和波形产生器444。类似于输入信号产生器304，决策单元410开始时先产生相位φ2,0，波形产生器444根据相位φ2,0产生本地信号VLO至混波器412，混波器412将噪声N与本地信号VLO进行混波，并产生混波输出信号VMO4，决策单元410根据混波输出信号VMO4产生另一相位φ2,1。如此迭代下去，直到当次迭代计算出的最佳相位φ2,m与前一次迭代计算出的最佳相位φ2,m-1之间的差距小于一特定范围，或是迭代次数大于一特定值时为止。当迭代完成之后，决策单元410所输出的最终相位φ2,M即为最佳相位
Figure PCTCN2016090471-appb-000018
与输入信号产生器304不同的是，相位计算单元442包含波形产生器444而进行递归式反馈运算。换句话说，混波器412的反馈来源为波形产生器444；而于输入信号产生器304中，混波器312的反馈来源为波形产生器144。同样地，即使在不同时间，噪声N因特定因素而造成其相位的变化，相位计算单元442依然可不断地追踪噪声N的相位而相应产生输入信号TX，以降低噪声N对判读待测电容CUT的影响，以提升整体电容感测电路的效能。
由上述可知，电容感测电路10利用输入信号产生器104产生与噪声N的 相位相关的输入信号TX，以降低电容判断电路102中混波输出信号VOUT中相关于噪声的能量。相较于现有技术，本发明可进一步降低噪声N对判读待测电容CUT的影响，以提升整体电容感测电路的效能。
需注意的是，相位侦测单元的实现方式并未有所限，举例来说，请参考图5至图9。图5至图9分别为本发明实施例相位侦测单元540～940的示意图。
相位侦测单元540包含二极管、电容和晶体管。二极管用来接收噪声N，电容的第一端耦接于二极管，而电容的第二端耦接于接地端，晶体管耦接于电容的第一端与第二端之间。
相位侦测单元640与相位侦测单元540类似，与相位侦测单元540不同之处在于，相位侦测单元640还包含运算放大器OP1、OP2。运算放大器OP1和运算放大器OP2的负输入端(标示有「－」号)皆耦接于运算放大器OP2的输出端，运算放大器OP2的正输入端(标示有「+」号)耦接于二极管与电容之间，运算放大器OP1的正输入端(标示有「+」号)用来接收噪声N，而晶体管耦接于运算放大器OP2的输出端与电容的第二端之间。
相位侦测单元740包含迟滞比较器HCMP，迟滞比较器HCMP为具有迟滞保护的比较器，如史密特触发器(Schmitt Trigger)。迟滞比较器HCMP的负输入端(标示有「－」号)用来接收临界电压VTH，正输入端(标示有「+」号)用来接收噪声N。
相位侦测单元840与相位侦测单元740相似，与相位侦测单元740不同之处在于相位侦测单元840利用运算放大器OP和脉冲消除器(De-glitch)800取代相位侦测单元740中迟滞比较器HCMP的功能。
相位侦测单元940则包含迟滞比较器HCMP1、HCMP2。迟滞比较器HCMP1、HCMP2的正输入端(标示有「+」号)用来接收噪声N，迟滞比较器HCMP1、HCMP2的负输入端(标示有「－」号)分别接收临界电压VTHp、VTHn，迟滞比较器HCMP1、HCMP2的输出端耦接于或门(Or Gate)900。
简而言之，相位侦测单元540～940皆可侦测噪声N的第一相位φ1和第一 频率f1，并将第一相位φ1和第一频率f1提供给波形产生器，因此，本发明的输入信号产生器即可根据噪声N的相位产生输入信号TX。
需注意的是，前述实施例是用以说明本发明的概念，本领域技术人员当可据以做不同的修饰，而不限于此。举例来说，波形产生器144根据最佳相位产生输入信号TX的方式并未有所限，波形产生器144可根据一母信号直接产生与母信号之间具有相位差为最佳相位
Figure PCTCN2016090471-appb-000019
的输入信号TX；或是波形产生器144可将最佳相位
Figure PCTCN2016090471-appb-000020
转换成为延迟时间Δtopt，并产生与母信号具有时间差为延迟时间Δtopt的输入信号TX，亦属于本发明的范畴。
具体来说，请参考图11，图11为母信号SIN和输入信号TX1、TX2的波形图。波形产生器144可直接产生输入信号TX1，其中输入信号TX1与母信号SIN之间的相位差为最佳相位
Figure PCTCN2016090471-appb-000021
另一方面，波形产生器144亦可将最佳相位
Figure PCTCN2016090471-appb-000022
转换成为延迟时间Δtopt，并产生输入信号TX2，其中输入信号TX2与母信号SIN之间的时间差为延迟时间Δtopt，亦属于本发明的范畴。
本实施例的相位计算单元可对应电容判断电路的电路结构而据以变化。举例来说，为了对应包含有混波器的电容判断电路202，相位计算单元242、342、442皆包含有混波器。然而，电容判断电路不限于包含混波器，举例来说，请参考图12，图12为电容判断电路302的示意图。电容判断电路302包含电荷转移电路320和判断模块324。电荷转移电路320包含有开关S1、S2和电容C1，开关S1的第一端用来接收输出信号RX，开关S1的第二端耦接于电容C1的第一端，开关S2的第一端耦接于电容C1的第一端，开关S2的第二端和电容C1的第二端耦接于接地端。开关S1受控于控制信号phi，通过适当控制输入信号TX与控制信号phi，待测电容CUT所储存的电荷可转移至电容C1中，而开关S2用来重置(Reset)或清空储存于电容C1的电荷。
除此之外，请参考图13，图13为电容判断电路402的示意图。电容判断 电路402包含电荷转移电路420和判断模块424。电荷转移电路420含有开关S3和积分电路422，开关S3也受控于控制信号phi，积分电路422包含放大器Amp、电容C2和开关S4，电容C2和开关S4耦接于放大器Amp的负输入端(标示有「－」号)与输出端之间。通过适当控制输入信号TX与控制信号phi，待测电容CUT所储存的电荷可转移至电容C2中，而开关S4用来重置(Reset)或清空储存于电容C2的电荷。
为了对应包含有电荷转移电路的电容判断电路302、402，本实施例的相位计算单元可包含有至少一电荷转移电路。举例来说，请参考图14，图14为本发明实施例中相位计算单元542的示意图。相位计算单元542与相位计算单元242结构类似，不同之处在于，相位计算单元542利用电荷转移电路CSC_1～CSC_K取代相位计算单元242中的混波器MX1～MXK和积分器IG1～IGK。也就是说，电荷转移电路CSC_1～CSC_K根据噪声N产生信号VO1～VOK，相位计算单元542所包含的决策单元510根据信号VO1～VOK计算出最佳相位
Figure PCTCN2016090471-appb-000023
具体来说，电荷转移电路CSC_1～CSC_K可利用电荷转移电路320或电荷转移电路420的电路结构来实现，电荷转移电路CSC_1～CSC_K中的开关S1或开关S3(未绘示于图14)分别受控于控制信号phi_1～phi_K，且CSC_1～CSC_K中开关S1或开关S3的第一端用来接收噪声N。相位计算单元542的运作原理与相位计算单元242相似，故简述如下。控制信号phi_1～phi_K分别具有K种不同的相位。例如，在一实施例中，控制信号phi_1的相位为0，控制信号phi_2的相位为π/K，控制信号phi_3的相位为2π/K，以此类推，控制信号phi_K的相位为(K-1)π/K。电荷转移电路CSC_1～CSC_K接收噪声N并分别依照控制信号phi_1～phi_K产生信号VO1～VOK。决策单元510自信号VO1～VOK中选择具有最小能量的信号VOS，其中，对应于信号VOS的控制信号为控制信号phi_S，且控制信号phi_S的相位为(S-1)π/K。因此，相位计算单元542可输出最佳相位
Figure PCTCN2016090471-appb-000024
为(S-1)π/K。
另外，请参考图15，图15分别为本发明一个实施例中输入信号产生器604 的示意图。输入信号产生器604与输入信号产生器304结构类似，故相同组件沿用相同符号。与输入信号产生器304不同的是，输入信号产生器604包含相位计算单元642，相位计算单元642包含电荷转移电路612和决策单元610。电荷转移电路612可利用电荷转移电路320或电荷转移电路420的电路结构来实现，其中，电荷转移电路612的开关S1或开关S3(未绘示于图15)受控于波形产生器144所产生的输入信号TX，且电荷转移电路612中开关S1或开关S3的第一端用来接收噪声N。也就是说，输入信号产生器604利用电荷转移电路612取代输入信号产生器304中的混波器312，其余操作原理与输入信号产生器304相同，在此不再赘述。
另外，请参考图16，图16为本发明一个实施例中相位计算单元742的示意图。相位计算单元742与相位计算单元442结构类似，故相同组件沿用相同符号。与相位计算单元442不同的是，相位计算单元742包含电荷转移电路712、决策单元710和波形产生器744。波形产生器744用来产生控制信号phi，电荷转移电路712可利用电荷转移电路320或电荷转移电路420的电路结构来实现，其中，电荷转移电路712的开关S1或开关S3(未绘示于图16)受控于波形产生器744所产生的控制信号phi，电荷转移电路712的开关S1或开关S3的第一端用来接收噪声N。也就是说，相位计算单元742利用电荷转移电路712取代相位计算单元442中的混波器412，相位计算单元742利用控制信号phi取代相位计算单元442中的本地信号VLO，其余操作原理与相位计算单元442相同，于此不再赘述。
综上所述，本实施例的电容感测电路利用输入信号产生器产生与噪声的相位相关的输入信号，以降低电容判断电路中混波输出信号中相关于噪声的能量，即降低噪声对判断待测电容的影响，以提升整体电容感测电路的效能。
以上仅为本发明的部分较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (23)

  1. 一种电容感测电路，用来感测待测电路的待测电容，所述待测电路接收输入信号并产生输出信号，所述电容感测电路包括：
    电容判断电路，耦接于所述待测电路，用来根据所述输出信号判断所述待测电容的电容大小；以及
    输入信号产生器，耦接于所述待测电路，用来根据噪声产生所述输入信号，所述输入信号产生器包含有：
    相位侦测单元，用来接收所述噪声并侦测所述噪声的第一相位；
    相位计算单元，耦接于所述相位侦测单元，用来接收所述噪声和所述第一相位，并根据所述噪声和所述第一相位计算最佳相位；以及
    第一波形产生器，耦接于所述相位计算单元，用来根据所述最佳相位产生所述输入信号。
  2. 如权利要求1所述的电容感测电路，其中，所述相位侦测单元包含有：
    二极管；以及
    电容，其一端耦接于所述二极管，另一端耦接于接地端。
  3. 如权利要求1所述的电容感测电路，其中，所述相位侦测单元包含有至少一比较器，所述至少一比较器用来比较所述噪声与至少一临界电压。
  4. 如权利要求1所述的电容感测电路，其中，所述相位计算单元计算所述最佳相位为
    Figure PCTCN2016090471-appb-100001
    n(t；φ1)代表所述噪声的相位为所述第一相位φ1时的波形，x(t；φ2)代表所述输入信号的相位为第二相位φ2时的波形。
  5. 如权利要求1所述的电容感测电路，其中，所述相位计算单元包含多个混波器，所述多个混波器以多个本地信号对所述噪声进行混波，所述多个本地信号具有多个相位；
    所述相位计算单元根据多个混波输出信号计算所述最佳相位。
  6. 如权利要求1所述的电容感测电路，其中，所述相位计算单元包含一混波器。
  7. 如权利要求6所述的电容感测电路，其中，混波器耦接于所述第一波形产生器，根据所述输入信号和所述噪声产生混波输出信号；
    所述相位计算单元根据混波输出信号计算所述最佳相位。
  8. 如权利要求6所述的电容感测电路，其中，所述相位计算单元还包含第二波形产生器，所述第二波形产生器根据第三相位产生本地信号至混波器，混波器根据本地信号和所述噪声产生混波输出信号；
    所述相位计算单元根据混波器的混波输出信号计算所述最佳相位。
  9. 如权利要求8所述的电容感测电路，其中，所述相位计算单元还包含决策单元，所述决策单元用来产生所述第三相位。
  10. 如权利要求1所述的电容感测电路，其中，所述第一波形产生器耦接于所述相位计算单元和所述相位侦测单元，用来根据所述第一相位和所述最佳相位产生所述输入信号。
  11. 如权利要求1所述的电容感测电路，其中，所述相位侦测单元侦测所述噪声的第一频率，所述相位计算单元根据所述噪声的所述第一相位和所述第一频率计算所述最佳相位。
  12. 如权利要求1所述的电容感测电路，其中，所述相位计算单元包含多个电荷转移电路，所述多个电荷转移电路受控于多个控制信号，所述多个控制信号具有多个相位，所述多个电荷转移电路根据所述噪声产生多个电荷输出信号；
    所述相位计算单元根据多个电荷输出信号计算所述最佳相位。
  13. 如权利要求12所述的电容感测电路，其中，所述多个电荷转移电路中的电荷转移电路包含有：
    第一开关；以及
    第一电容，耦接于所述第一开关。
  14. 如权利要求13所述的电容感测电路，其中，所述第一电容耦接于接地 端。
  15. 如权利要求13所述的电容感测电路，其中，所述电荷转移电路还包含放大器，所述第一电容耦接于所述放大器的第一输入端和输出端之间。
  16. 如权利要求1所述的电容感测电路，其中，所述相位计算单元包含一电荷转移电路。
  17. 如权利要求16所述的电容感测电路，其中，所述电荷转移电路包含有：
    第二开关；以及
    第二电容，耦接于所述第二开关。
  18. 如权利要求17所述的电容感测电路，其中，所述第二电容耦接于接地端。
  19. 如权利要求17所述的电容感测电路，其中，所述电荷转移电路还包含有放大器，所述第二电容耦接于所述放大器的第一输入端和输出端之间。
  20. 如权利要求17所述的电容感测电路，其中，所述电荷转移电路耦接于所述第一波形产生器，所述电荷转移电路的所述第二开关受控于所述输入信号，所述电荷转移电路根据所述输入信号和所述噪声产生电荷输出信号；
    所述相位计算单元根据电荷输出信号计算所述最佳相位。
  21. 如权利要求17所述的电容感测电路，其中，所述相位计算单元还包含第三波形产生器，所述第三波形产生器根据第四相位产生控制信号至所述电荷转移电路，所述电荷转移电路的所述第二开关受控于所述控制信号，所述电荷转移电路根据所述控制信号和所述噪声产生电荷输出信号；
    所述相位计算单元根据电荷输出信号计算所述最佳相位。
  22. 如权利要求1所述的电容感测电路，其中，所述输入信号与一母信号之间具有相位差，所述相位差为所述最佳相位。
  23. 如权利要求1所述的电容感测电路，其中，所述第一波形产生器将所述最佳相位转换成为延迟时间，所述输入信号与母信号之间具有时间差，所述时间差为所述延迟时间。
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