WO2017123870A1 - Porteur amovible et procédé - Google Patents

Porteur amovible et procédé Download PDF

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Publication number
WO2017123870A1
WO2017123870A1 PCT/US2017/013336 US2017013336W WO2017123870A1 WO 2017123870 A1 WO2017123870 A1 WO 2017123870A1 US 2017013336 W US2017013336 W US 2017013336W WO 2017123870 A1 WO2017123870 A1 WO 2017123870A1
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WO
WIPO (PCT)
Prior art keywords
carrier
releasable
layer
conductive layer
tape
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2017/013336
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English (en)
Inventor
Sukianto Rusli
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chip Solutions LLC
Original Assignee
Chip Solutions LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US15/211,384 external-priority patent/US20170018448A1/en
Application filed by Chip Solutions LLC filed Critical Chip Solutions LLC
Publication of WO2017123870A1 publication Critical patent/WO2017123870A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7448—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support the bond interface between the auxiliary support and the wafer comprising two or more, e.g. multilayer adhesive or adhesive and release layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/479—Leadframes on or in insulating or insulated package substrates, interposers, or redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7412—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support the auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7424—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self-supporting substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/743—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/744—Details of chemical or physical process used for separating the auxiliary support from a device or a wafer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/019—Manufacture or treatment using temporary auxiliary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection

Definitions

  • the subject matter disclosed herein generally relates to the fabrication of semiconductor devices. More particularly, the subject matter relates to a releasable carrier and accompanying layering structures for the fabrication of semiconductor devices.
  • a carrier wafer may be laminated to dicing tape and known good die are placed face down.
  • the wafer may then be compression molded to encapsulate it and then the wafer carrier and tape may be removed.
  • the molding compound may then be used to carry the fan-out area and to protect the chip backside. Redistribution layers may be created on the exposed die faces, the I/O may be rerouted, solder balls may be placed, and the die may be singulated.
  • methods include slicing the wafer into individual die and then packaging them.
  • embedded circuits include a conductive circuit layer that is patterned onto a surface of a metal core base layer. A dielectric material is then layered onto the conductive circuit followed by the application of a thin layer of conductive layer. This foil is then etched to complete the circuit.
  • a method for making a semiconductor device comprises: providing a releasable carrier attached to a conductive layer; patterning a conductive circuit on a surface of the conductive layer; applying an insulative material at least partially covering the conductive circuit; releasing the releasable carrier from the conductive layer; and facilitating the releasing with an activating source.
  • a releasable carrier comprising: a supporting carrier; a carrier conductive layer; a releasable tape located between the supporting carrier and the carrier conductive layer, the releasable tape attaching the supporting carrier to the carrier conductive layer, wherein the releasable tape is configured to release the supporting carrier from the carrier conductive layer after being exposed to an activating source; and a thin conductive layer attached to the carrier conductive layer, the thin conductive layer creating a surface configured to receive a conductive circuit.
  • a method for fabricating a releasable carrier comprises: providing a supporting carrier; attaching a releasable tape to the supporting carrier; providing a first conductive layer and a second conductive layer attached to the first conductive layer; and attaching the first conductive layer to the releasable tape, wherein the releasable tape is configured to release the supporting carrier from the first conductive layer after being exposed to an activating source.
  • Figure 1 depicts a side cutaway view of a step of a fabrication process according to one embodiment
  • Figure 2 depicts a side cutaway view of another step of the fabrication process of Figure 1 according to one embodiment
  • Figure 3 depicts a side cutaway view of another step of the fabrication process of Figures 1 - 2 according to one embodiment
  • Figure 4 depicts a side cutaway view of another step of the fabrication process of Figures 1 - 3 according to one embodiment
  • Figure 5 depicts a side cutaway view of another step of the fabrication process of Figures 1 - 4 according to one embodiment
  • Figure 6 depicts a side cutaway view of another step of the fabrication process of Figures 1 - 5 according to one embodiment
  • Figure 7 depicts a side cutaway view of another step of the fabrication process of Figures 1 - 6 according to one embodiment
  • Figure 8 depicts a side cutaway view of another step of the fabrication process of Figures 1 - 7 according to one embodiment
  • Figure 9 depicts a side cutaway view of another step of the fabrication process of Figures 1 - 8 according to one embodiment
  • Figure 10 depicts a side cutaway view of another step of the fabrication process of Figures 1 - 9 according to one embodiment
  • Figure 11 depicts a side cutaway view of another step of the fabrication process of Figures 1 - 10 according to one embodiment
  • Figure 12 depicts a side cutaway view of another step of the fabrication process of Figures 1 - 11 according to one embodiment
  • Figure 13 depicts a side cutaway view of another step of a fabrication process according to one embodiment
  • Figure 14 depicts a side cutaway view of another step of the fabrication process of Figures 13 according to one embodiment
  • Figure 15 depicts a side cutaway view of another step of the fabrication process of Figures 13 - 14 according to one embodiment
  • Figure 16 depicts a side cutaway view of another step of the fabrication process of Figures 13 - 15 according to one embodiment
  • Figure 17 depicts a side cutaway view of an option for a build-up of layers in a fabrication process according to one embodiment
  • Figure 18 depicts an exploded view of layers of a carrier structure in accordance with one embodiment
  • Figure 19 depicts an exploded view of layers of another carrier structure in accordance with one embodiment
  • Figure 20 depicts a UV release film in accordance with one embodiment
  • Figure 21 depicts a thermal release film in accordance with one embodiment
  • Figure 22 depicts the thermal release film of Figure 21 after activation in accordance with one embodiment
  • Figure 23a depicts a side cutaway view of a step of a fabrication process in accordance with one embodiment
  • Figure 23b depicts a side cutaway view of another step of the fabrication process of Figure 23 a in accordance with one embodiment
  • Figure 23c depicts a side cutaway view of another step of the fabrication process of Figures 23a - 23b in accordance with one embodiment
  • Figure 23d depicts a side cutaway view of another step of the fabrication process of Figures 23a - 23c in accordance with one embodiment
  • Figure 24 depicts a side cutaway view of a system in package structure in accordance with one embodiment
  • Figure 25 depicts a thermal adhesive tape in accordance with one embodiment
  • Figure 26 depicts a double mold layering structure in accordance with one embodiment
  • Figure 27 depicts a interconnect joint layering structure in accordance with one embodiment
  • Figure 28 depicts another interconnect joint layering structure in accordance with one embodiment
  • Figure 29 depicts an exploded view of layers of another carrier structure in accordance with one embodiment.
  • Figure 30 depicts an exploded view of layers of another carrier structure in accordance with one embodiment.
  • FIG. 1 a fabrication process for the creation or fabrication of a semiconductor device 100 is shown.
  • the fabrication process is shown in Figure 1 to include a step of providing a releasable carrier 102 that is attached to conductive layers 101 to create a carrier structure 10.
  • the conductive layers 101 may include a combination of a carrier foil 128 and a thin foil 127.
  • the carrier foil 128 may be a thicker conductive layer and the thin foil 127 may be a thin conductive layer.
  • An adhesive layer 129 may be located between the carrier 102 and the conductive layers 101.
  • Embodiments of the releasable carrier 120 and the conductive layers 101 combination are shown in the exploded views provided by Figures 19 - 20.
  • Figure 18 shows a carrier structure 10a having a releasable carrier 120 that may be a metal or core carrier 120a.
  • Figure 19 shows a carrier structure 10b having a glass releasable carrier 120b.
  • Glass may be a preferred material for the releasable carrier 120 because it is extremely flat, thermally and dimensionally stable, and has a low coefficient of thermal expansion.
  • the releasable carrier 120 may be a glass carrier, a metal core carrier, a clad core carrier, a laminate carrier, an aluminum carrier, a copper carrier, or a stainless steel carrier, an organic reinforced core carrier a ceramic material or combinations thereof. These carrier materials are exemplary.
  • the releasable carrier 120 may have varying thicknesses and may extend over varying areas. It should be understood that the concepts described herein may be applicable to any panel size format (e.g. 500 mm x 500 mm). Further, the releasable carrier 120 may be a made from a material that is dimensionally stable, stiff and flat. These three characteristics may be particularly advantageous during the rest of the described fabrication process.
  • the releasable carrier 120 may be reused for a second fabrication process after being released in the manner described herein, the releasable carrier 120 may be fashioned in a thicker manner, as the reusability of the releasable carrier 120 may preclude the engineering need to reduce material cost as would be required for one-off carriers.
  • the adhesive layer 129 may be applied to one of the releasable carrier 120 or the conductive layers 101 in a first step. The other of the releasable carrier 120 or the conductive layers 101 may then be attached.
  • the adhesive layer 129 may include one or more layers such as a base with adhesive on one or both sides of the base (i.e. a double-sided tape).
  • the adhesive layer 129 may include a thermal sensitive adhesive 131 on one or both sides of a double-sided tape.
  • the thermal sensitive adhesive 131 may be configured to have a reduced adhesive capacity when exposed to high temperatures from, for example, a heat source. This may allow the thermal sensitive adhesive 131 to release when exposed to heat.
  • the activating heat source may be configured to raise the temperature of the thermal sensitive adhesive 131 to a temperature between 150 and 300°C.
  • the temperature of the thermal activating source may be set to 250°C with the release temperature of the thermal sensitive adhesive 131 being in the range of 180°C and 220°C.
  • FIG. 21 shows the thermal sensitive adhesive 131 prior to activation.
  • Figure 22 shows the thermal sensitive adhesive 131 after activation.
  • the thermal sensitive adhesive 131 may include a backing layer 131a.
  • a thermal release adhesive layer 131b may be layered above the backing layer 131a.
  • a substrate layer 131c may be attached to the thermal release adhesive layer 131b.
  • the substrate layer 131c may be any particular substrate such a release film liner.
  • the thermal release adhesive layer 131 may be activated by heat from a heat source to create the release.
  • the thermal release adhesive layer 131b may include expandable molecules that expand when exposed to increased temperatures. Such expansion may reduce the tendency for adhesion of the molecules to provide for the thermal release of the thermal sensitive adhesive 131.
  • the adhesive layer 129 may include a UV sensitive adhesive 132 on one or each side of a double-sided tape, as shown in Figure 19.
  • the UV sensitive adhesive 132 may be configured to have a reduced adhesive capacity when exposed to a UV light source. This may allow the UV sensitive adhesive 132 to release when exposed to the UV light source.
  • the UV light activation source (not shown) may be a UV light source generating irradiation energy between 20 mW/cm 2 and 40 mW/cm 2 .
  • it may be particularly advantageous to use a glass material for the releasable carrier 120. The transparent nature of glass may allow the UV sensitive adhesive to be exposed to the UV light activation source through the glass of the releasable carrier 120.
  • the UV sensitive adhesive 132 may include a polyolefin film layer 132a.
  • a UV curing acrylic adhesive layer 132b may be layered above the polyolefin film layer 132a.
  • a polyester film release liner 132c may be layered above the UV curing acrylic adhesive layer 132b.
  • the UV curing acrylic adhesive layer 132b may be the layer that is activated by the UV source to create the release from the liner layers 132a, 132c.
  • the thickness of the middle UV curing acrylic adhesive layer 132b may be thinner than the liner layers 132a, 132c.
  • the UV curing acrylic adhesive layer 132b may be 3 - 10 ⁇ , while the combination of the liner layers 132a, 132c may each be 60 - 100 ⁇ . In one embodiment, the UV curing acrylic adhesive layer 132b may be 8 ⁇ or 5 ⁇ while the liner layers 132a may be 80 ⁇ .
  • the double-sided tape may include two different adhesives, one on each side.
  • the double-sided tape may include a thermal sensitive adhesive on one side and a UV sensitive adhesive on the other.
  • the double-sided tape may include a UV sensitive adhesive on one side and a no-release adhesive on the other side.
  • a pressure sensitive adhesive may be applied to one side of the double-sided tape while the other side includes the UV sensitive adhesive or the thermal sensitive adhesive.
  • the conductive layers 101 may include both the carrier foil 128 and the thin foil 127.
  • the carrier foil 128 may be releasable from the thin foil 127 by mechanically pulling the carrier foil 128 from the thin foil 127 to expose the thin foil 127.
  • adhesives or a double-sided tape may be applied between the carrier foil 128 and the thin foil 127 which may release the carrier foil 128 from the thin foil 127 in a manner similar or the same as the releasable carrier 120 releases from the conductive layers 101 with the adhesive layer 129.
  • the carrier foil 128 may be a thicker layer than the thin foil 127.
  • the carrier foil 128 may be 50 ⁇ - 70 ⁇ .
  • the thin foil 127 may be between 1 ⁇ and 5 ⁇ . However, these thicknesses are exemplary and thicker or thinner layers may be appropriate in some embodiments.
  • the releasable carrier 120 includes a thermal barrier coating 142 applied to the releasable carrier 120 between the releaseable carrier 120 and the adhesive layer 129.
  • the thermal barrier coating 142 may be configured to prevent the loss of adhesion for the adhesive layer 129 as a result of elevated temperatures that might occur in other steps of the assembly processing (e.g. during reflow).
  • Figure 29 shows that a second barrier release coating 141 is applied to the carrier foil 128 between the carrier foil 128 and the adhesive layer 129.
  • Another barrier release coating (not shown) may be applied to an undersurface of the carrier as well to act as a thermal barrier at this location in the carrier structure.
  • a third thermal barrier coating 143 is applied to the top of the adhesive layer 129 between the adhesive layer 129 and the carrier foil 128.
  • the thermal barrier coatings 141, 142, 143 may be applied as a layer between any release interface in the carrier structure 10. Both sides of the adhesive layer 129 may include a thermal barrier coating.
  • the thermal barrier coatings 141, 142, 143 may be micron size fillers that may be applied to appropriate layers of the carrier structure 10 and more specifically the adhesive layer 129. These filler particles may be hollow ceramic insulative spheres in one embodiment.
  • the thermal barrier coatings 141, 142, 143 may be adjusted to the desired thickness to provide the necessary protection for the layers of the carrier structure 10 and the thermal sensitive adhesive 131 (or the UV, pressure sensitive, or other adhesives described above).
  • the thermal barrier coatings 141, 142, 143 may be applied by various methods such as thermal spray.
  • the thermal barrier material may be combined or mixed with an adhesive in a combined adhesive/barrier layer, rather than two separate layers.
  • a version of the adhesive layer 129 is shown including a double sided tape having a polyester base material layer 129a located between a thermal sensitive adhesive 131 and a pressure sensitive adhesive 150.
  • thermal barrier fillers 151 may include thermal barrier fillers 151 in a combined manner.
  • the thermal barrier fillers 151 may include thermal barrier fillers 151 in a combined manner.
  • the double sided tape further includes a first release liner 129b layered on top of the thermal release adhesive 131 and a second release liner 129c layered below the pressure sensitive adhesive 150.
  • release liners 129b, 129c may be utilized on any embodiment of the carrier structure 10 described herein and may be removed when applying the double sided tape to the carrier structure 10 during the fashioning of the carrier structure 10 prior to a circuit or semiconductor device fabrication process.
  • the releasable carrier 120 may be configured to release from the rest of the carrier structure 10 from the conductive layers 101 when exposed to an activating source, such as a UV source or a heat source as described herein above.
  • the activating source may require no physical contact with the releasable carrier 120 to activate the adhesive layer 129 and release the releasable carrier in a manner consistent with that described herein.
  • the activating source may be a non-mechanical activating source and may create a clean release such that the releasable carrier 120 is reusable for additional fabrication processes.
  • the releasable carrier 120 may include three release points: a first release point between the thin foil 127 and the carrier foil 128; a second release point between the carrier foil 128 and the adhesive layer 129 or releasable tape; and a third between the releasable carrier 120 and the adhesive layer 129 or releasable tape.
  • the carrier structures described herein may be used on any panel size or format, from wafer to large panel processes. Further the carrier structures described herein may be used on standard build up processes or sputtering methods. Further, the carrier structures may expand fan out wafer level packaging to sizes beyond the current 12" diameter standard. Moreover, the carrier structures may be capable for any panel size format including rectangular, square or circular. Further, the carrier structures and accompanying methods described herein may be compatible with wirebond, flip chip, integrated passive devices, conventional passives and multi-die structures.
  • Figure 2 shows another step in the fabrication process.
  • a substrate 155 may begin to be built upon the releasable carrier 120, as shown in Figures 3 - 6.
  • a conductive circuit 152 may be applied.
  • the conductive circuit 152 may include a plurality of die attach pads 105 and a plurality of traces 106.
  • the die attach pads 105 and the traces 106 may each be plated conductive elements.
  • the conductive circuit 152 may be applied atop the layer of the thin foil 127 while the releasable carrier 120 remains attached.
  • the conductive circuit 152 is not limited to these elements and may include any appropriate conductive elements, portions or the like.
  • the conductive circuit 152 may be a redistribution layer (RDL) and may be formed with RDL patterning with semi -additive plating.
  • RDL redistribution layer
  • the fourth step includes laminating the conductive circuit 152 with an insulative material 107 to encapsulate the conductive circuit 152.
  • the insulative material 107 may be a photo-imageable dielectric (PID) in one embodiment.
  • the insulative material 107 may be an ABF film.
  • the insulative material 107 may be a mold compound.
  • the insulative material may be any dielectric material used for creating substrate layers on conductive circuits for semiconductor and printed circuit board (PCB) processes.
  • the insulative material 107 may have an adjustable thickness depending on the embodiment.
  • the conductive circuit 152 may be referred to herein as an "embedded circuit.”
  • embedded means a process or product where a conductive circuit or layer is built in adjacent contact with a conductive layer, the conductive layer being etched away or otherwise removed to complete the conductive circuit of the substrate. Prior to etching, the thin foil sheet would short any circuit upon which the embedded substrate is built. In each of these "embedding" processes, the conductive layer is etched away to complete the functional conductive circuit.
  • the insulative material 107 (e.g. PID) may be patterned.
  • the patterning of the insulative material 107 may include one or more patterned structures 108 exposing a die attach pads 105 or patterned structures 109 exposing the thin conductive layer 127.
  • multi- tier openings may be defined in the insulative material 107.
  • the chip 112 (shown in Figure 6) may also be placed on this stage with solder balls or copper pillars connecting to the circuits 152 within the patterned structures 108. Alternatively, the chip 112 may be placed as shown in Figure 6.
  • the patterned structures 108, 109 may be filled with more conductive material, such as copper.
  • a plurality of copper plated filled vias 110 are shown filling the patterned structures 108.
  • the structures 110, 111 are each flush with the surface of the insulative material 107.
  • the completed substrate layer 155 has been defined above the layer of thin foil 127.
  • the substrate 155 includes a first surface 156 and a second surface 157. From here, it should be understood that multi-layer circuits may be fabricated above the substrate layer
  • each die attach location may be tested or viewed with a vision system to determine good known die attach locations. This vision testing may be accomplished before the conductive circuit 152 is etched or completed and while the thin foil layer 127 remains attached.
  • the insulative layer 107 may be comprised of PID material to facilitate the imaging at this stage prior to attachment of the semiconductor die 112. The imaging may determine whether the elements of the conductive circuit are ready for placement or are instead defective. It should be understood that the view shown in Figures 1 - 12 are for a single die attach location, but that the substrate may continue to the left and right (along with into and out of the page) relative to the cross section shown to provide for additional die attach locations.
  • a semiconductor die 112 may then be attached to the second surface 157 of the substrate layer 155.
  • the semiconductor die 112 may be a flip chip or any other type of die and may include interconnects 112a, 112b.
  • the interconnects 112a, 112b may be copper pillars or solder balls.
  • semiconductor die 112 may be completed using pick and place tools. However, other die attach techniques may be required depending on the die pitch design and corresponding registration requirement. Flux application by dipping may also be incorporated during the pick and place. Other flux dispensing methods are possible in the placement process as well. Reflow may include utilizing a non conveyorized convention oven for large panel processes.
  • the conductive circuit 152 may include a first element 160 having a first portion such as the structure 110 in physical contact with the semiconductor die 112 and at least substantially coplanar with the second surface 157 of the insulative material and the substrate 155.
  • the first element 160 may further include a second portion such as the structure 105 that is at least substantially co-planer with the first surface 156 of the substrate 155.
  • the first structure 110 and the second structure 105 may have different geometries.
  • the eighth step may include molding the die onto the substrate 155 and the carrier structure 10 with a mold compound 114. Mold sheets, powder or liquid molding compounds or systems may be used depending on the package requirements for the mold compound 114. Capilary underfill (CUF) is also an option rather than mold underfill (MUF).
  • CCF Capilary underfill
  • UMF mold underfill
  • the encapsulating the semiconductor die 112 may be a dielectric material instead of a mold material (e.g. ABF film), in other embodiments.
  • the semiconductor die 112 may be attached to the substrate 155 and encapsulated with the mold 114 before the releasable carrier 120 is removed from the substrate 155 and the conductive layers 101.
  • the next step may include releasing the releasable carrier 120 from the conductive layers 101 and the substrate 155.
  • the releasable carrier 120 may be removed by peeling.
  • the release of the releasable carrier 120 may be facilitated by an activating source as described hereinabove.
  • no mechanical peeling may be necessary if the level of adhesive is reduced to the point where the carrier 120 falls away from the conductive layers 101 and the substrate 155.
  • the carrier foil 128 may be released from the thin foil 127. This may be accomplished by peeling. Because the carrier foil 128 may be thin relative to the releasable carrier 120 and may not require release facilitation with an activating source like the releasable carrier 120.
  • the remaining thin foil 127 may be removed by etching to expose the embedded RLD circuits in the insulative material 107 in a tenth step in the fabrication process.
  • This etching may form an etched layer 158 of the thin foil 127 conductive material.
  • the etching may be a control etching process that may completed to form or complete the embedded circuits in the substrate layer 155.
  • the conductive circuit 152 may be formed as a result of the RDL circuit build up on the thin foil 127 which is then encapsulated by the insulative material such as a PID, an ABF film, prepreg, and mold compound.
  • the embedded RDL circuits including die pads may then be completely formed and exposed after the releasable carrier 120 has been removed and the thin foil 127 that remains below the dielectric layer is etched away, as shown in Figure 10.
  • the recessed embedded circuit 152 may form an opening for a ball grid array (BGA) ball attach process for completing the BGA ball grid array (BGA) ball attach process
  • the etched circuits may include solder ball attach locations 117 without solder masks for attachment to solder balls 118.
  • the etched circuits may include solder mask defined (SMD) BGA ball attach.
  • SMD solder mask defined
  • a solder mask material 119 may be applied in a manner creating a defined opening 120 for the solder balls 118.
  • the fabrication process described with respect to Figures 1 - 12 may be a hybrid assembly process, whereby the build-up and creation of the substrate 155 and the conductive circuit 152 are fabricated at the same time and location as the semiconductor die 112 is attached to the substrate 155. This process may create a completed semiconductor device 100 at the same time and in the same location.
  • the substrate fabrication and the assembly process steps of attaching the semiconductor die 112 may be seamless and may occur on the same manufacturing line or by a single manufacturer.
  • the carrier structure 10 may be utilized in other standard non-hybrid approaches as well.
  • the above steps described with respect to Figures 1 - 12 are an exemplary embodiment and that other fabrication processes which utilizes more, less or different steps are contemplated.
  • the carrier structure 10 may be utilized in the manner described in Figures 9 - 10 (e.g. using a thermal or UV adhesive) using a variety of different fabrication and packaging processes both before and after the release of the releasable carrier 120.
  • the concept of attaching the semiconductor die 112 prior to the underlying conductive circuit 152 being completed i.e. before etching and/or before additional layers of substrate are applied
  • the carrier structure 10 may be configured to allow for separation in a timely release sequence.
  • the concept allows for separation at certain predetermined or preplanned stages in an assembly or fabrication process.
  • the carrier structure 10 goes through RDL circuit patterning, dielectric build up, lamination and assembly (flip chip attach and molding).
  • the phase where the releasable carrier 120 is separated from the package is after the molding process of the semiconductor die 112.
  • the adhesive layer 129 or double sided tape is configured to maintain adhesion as the carrier goes through different processes, especially during heating steps such as reflow processes.
  • the semiconductor die 112 is attached to the embedded substrate 155.
  • the embedded substrate 155 has the first surface 156 and the second surface 157.
  • the embedded substrate 155 includes the insulator layer 107 and at least a portion of a conductive circuit 152 within the insulator layer 107.
  • the embedded substrate includes the etched layer 158 of the conductive etched thin foil 127.
  • the etched layer 158 may be attached to the conductive circuit 152.
  • the semiconductor die 112 is attached to the second surface 157 while the etched layer 158 of the conductive material is attached to the opposing first surface 156.
  • the method may include patterning a conductive circuit, such as the conductive circuit 152 on a conductive layer layer, such as the thin foil 127.
  • the method may include applying an insulator material, such as the insulative material 107, over the conductive circuit to create a substrate, such as the substrate 155, having a first surface and a second opposing surface, where the conductive layer layer is located on the first surface.
  • the method may include attaching a semiconductor die, such as the semiconductor die 112, to the second surface of the substrate.
  • the method may then include etching or removing the conductive layer layer to create a completed circuit.
  • the method may include providing a releasable carrier, such as the releasable carrier 120, attached directly or indirectly to the conductive layer layer, encapsulating the semiconductor die after the attaching the
  • Another embodiment may include a method for making a semiconductor device, such as the semiconductor device 100.
  • the method may include providing a releasable carrier, such as the releasable carrier 120, attached to a conductive layer, such as the thin foil
  • the method may include patterning a conductive circuit, such as the conductive circuit
  • the method may include applying an insulative material, such as the insulative material 107, at least partially covering the conductive circuit.
  • the method may include releasing the releasable carrier from the conductive layer and facilitating the releasing with an activating source. This facilitating may occur without the activating source making physical contact with the releasable carrier.
  • the method may include raising the temperature of an adhesive, such as the adhesive layer 129, located between the releasable carrier and the conductive layer, to a temperature between 150°C and 300°C.
  • the method may include attaching a semiconductor die, such as the semiconductor die 112, to at least portions of the conductive circuit.
  • the method may include encapsulating the semiconductor die before the releasing the releasable carrier.
  • the method may further include including activating the adhesive with the activating source to facilitate the releasing.
  • the method may further include applying thermal release adhesive on one or both sides of a double sided tape of the adhesive.
  • the method may alternatively or additionally include applying UV release on one or both sides of the double sided tape.
  • the method may include removing the carrier foil layer from the thin foil layer after the releasable carrier has been released.
  • the method may include reusing the releasable carrier for making a second semiconductor device.
  • the fabrication process may forgo steps 11 and 12 until after applying one or more additional substrate layers such as the second substrate layer 165 shown in Figures 13 - 14.
  • the semiconductor die 112 may be attached directly to the circuit pads at the structures 110 without removing the releasable carrier 120. If additional RDL layers are necessary, they may be formed by transfer process or by a build-up process after the releasable carrier 120 is removed as shown in Figures 13 - 16.
  • Figure 13 shows another carrier structure lOe similar or the same as the carrier structure 10.
  • an above plane circuit 204 may have already been applied adjacent or above the first surface 156, along with another insulative layer 121 which may include, for example, a thermal cure dielectric.
  • the carrier structure lOe may include an annular ring structure 166 patterned on the conductive layers 101a.
  • the thermal cure dielectric may be compressed, as shown in Figure 14.
  • the releasable carrier 120e of the carrier structure 10a has been removed, along with the carrier foil layer 128a, exposing the thin foil layer 129a, which has already been etched away.
  • Laser ablate has been used to remove portions of the insulative material and to expose the top pads 105 in the first substrate 155.
  • Vias 126 are filled with a conductive material in the step shown in Figure 16. It should be understood that following the step shown in Figure 16, additional layers may similarly applied.
  • build-up layers by transfer method without a releasable carrier may be applied as well.
  • Figures 23a, 23b, 23c and 23d show a process for above plane structures applied above the etched layer.
  • Figure 23a shows a step after the semiconductor die 112 has been encapsulated in the mold 114, after the carrier tape 128 has been removed but prior to the etching.
  • a photoresist pattern 201 has been applied adjacent to the thin foil layer 127 with a plurality of photoresist openings 202, prior to etching.
  • Figure 23c shows that above place circuits 203 may be plated on the thin foil layer 127. Once this occurs, etching the thin layer 127 may be accomplished to create the above plane circuits 204, as shown in Figure 23d.
  • above plane conductive circuits are contemplated including standard build up layering. For example, once the etched layer with above plane circuits has been applied, another standard build up layer may be applied. Once the encapsulating mold 114 has been applied about the semiconductor die 112 and hardens, the die may act as the structural support upon which to build additional layers in a standard build process.
  • package structure(s) with multiple active(s) and/or passive(s) combinations may be redistributed simultaneously.
  • a wirebond 300, a flipchip 301, an IDP 302 and a passive component 303 are shown packaged together in a system in package (SIP) arrangement 310.
  • SIP system in package
  • FIG. 17 another embodiment is illustrated.
  • multiple RDL layers are formed on an underlying carrier structure 10b, the same or similar to the carrier structures 10, 10a.
  • embedded features may be located proximate to the BGA pads formed on the thin releasable foil of the carrier in a first substrate layer 175a.
  • a second substrate layer 175b may be built upon the first substrate layer 175a using a standard build up process which results in at least some above plane conductive elements 176 which may be capture pads for receiving pillars or interconnects 191 of the semiconductor die 190.
  • a dashed line is shown between layers 175a and 175b to highlight the difference in layers. However, it should be understood that this dashed line is imaginary and simply shown to demonstrate that there are two separate layers. Again, the attachment of the semiconductor die 190 may occur when the releasable carrier 120 remains attached before release in this embodiment.
  • Figure 26 shows another embodiment of another semiconductor device 50 that is at least partially fabricated in a manner consistent with that described herein above.
  • This semiconductor device 50 includes a conductive circuit 352 and a first layer of insulative material 307 which is a first mold material.
  • a "mold" as described and used herein means a thermoplastic material having a substantial filler content. Additionally, a mold may mean a material having a substantial filler size as well.
  • a mold material is further configured to protect the encapsulated conductive circuits 352.
  • the first mold material 307 may encapsulate the conductive circuit 352 and may be configured to act as an electrical insulator and/or a dielectric.
  • the conductive circuit 352 may be an embedded circuit that may eventually be completed by etching a thin foil layer, as described hereinabove.
  • the first mold material and the encapsulated conductive circuit 352 may comprise a first substrate layer 355.
  • the semiconductor device 50 may further include a semiconductor die 312 encapsulated within a second mold material 314. In other embodiments, the semiconductor die may be encapsulated within the first semiconductor material 307 that has been used to encapsulate the conductive circuit 352.
  • semiconductor device 50 may be fabricated on a carrier structure 310 having a releasable carrier 320, an adhesive layer 329 and a releasable foil layer 301.
  • the substrate 355 may be built upon the releasable carrier, which may include the adhesive layer 329 which may be thermally or UV activated.
  • the semiconductor die 312 may be encapsulated with the second mold material 314 before the releasable carrier 320 has been removed or released from the substrate 355 and the package structure.
  • the first mold material 307 and the second mold material 314 may be a thermoplastic mold compound which is able to soften upon heating, and is capable of being hardened upon cooling. This softening and hardening may be repeatable for additional heat applications without compromising the integrity of the eventually hardened compound. This may be particularly advantageous for embodiments in the present invention, which may require additional heat applications for removing the releasable carrier 320, in the case that the adhesive layer 329 is a thermally releasable compound.
  • the first mold material 307 may not be mixed with thermosetting dielectric materials.
  • the first mold compound 307 may function in a similar manner to thermosetting dielectric materials such as ABF film and PID and other dielectric materials, but the first mold compound 307 may actually be a thermoplastic compound.
  • the first mold material 307 layer may also be thinner than the second mold material 314 layer, as the first mold material 307 is configured to function as a prepreg or dielectric encapsulate material.
  • the second mold material 314 may be different than the first mold material 307. It may be particularly advantageous in some fabrication processes for the first mold material 307 to have a lesser filler content than the second mold material 314. Similarly, the first mold material 307 may have a filler size that is less than the second mold material 314. By having a greater filler content and filler size than the first mold material 307, the second mold 314 material may prevent warpage and may be particularly advantageous. Having a lower filler content and filler size for the first mold material 307 may be desirable for achieving precise and thin fill dimensions necessary for creating substrate layers.
  • this double mold process may allow for packages with redistribution layers to be processed by the sole use of thermoplastic molding compounds and without the use of thermosetting dielectric materials, in one embodiment.
  • thermosetting mold compounds for the entire package structure resulting in less mismatch in material properties such as CTE, Tg, and resin rheology. This may allow the material and process adjustment to control warpage and other reliability concerns.
  • the double mold process may be incorporated into current assembly line infrastructures already designed to handle mold compound materials. In the case of a multi-layer package design, the package construction may require a combination of thermosetting and thermoplastic materials.
  • dielectric substrate layers may be applied below the first substrate layer 355 once the carrier assembly 310 has been removed and the thin foil has been etched in the manner described hereinabove.
  • the single substrate layer 355 adjacent to the semiconductor die 312 may be made with mold in the manner described herein, but additional layers may be built up in a standard build-up process using dielectric materials.
  • Another embodiment contemplated is a method of making a semiconductor device that includes providing a substrate, such as the substrate 355, that includes a first mold material, such as the first mold material 307, and a conductive circuit, such as the conductive circuit 352, in the first mold material.
  • the method may include providing a semiconductor die, such as the semiconductor die 312.
  • the method may include attaching the semiconductor die to the conductive circuit and encapsulating the semiconductor die with at least one of the first mold material or a second mold material, such as the second mold material 314.
  • the method may include preventing the mixing of the first mold material with thermosetting dielectric materials.
  • the method may include encapsulating the semiconductor die with the second mold material.
  • the method may include created an embedded the conductive circuit by etching a conductive layer or sheet.
  • the method may further include insulating an entire package structure of a semiconductor device by the sole use of one or more mold compounds.
  • the method may further include providing a thermally activated releasable carrier, such as the releasable carrier 320, building a substrate, such as the substrate 355, upon the thermally activated releasable carrier, attaching the conductive circuit before the thermally activated releasable carrier is removed from the substrate.
  • the method may include exposing the thermally activated releasable carrier to an appropriate temperature, and releasing the thermally activated releasable carrier.
  • FIG. 27 shows still another embodiment of a semiconductor device 400 having an interconnection joint structure 401. Shown is a semiconductor device 400 having a semiconductor die 412 at a stage in a fabrication process prior to encapsulation of the semiconductor die 412 with a mold.
  • the package shown may be resting on a carrier structure (not shown) in a manner consistent with the embodiments of the carrier structures described herein above.
  • a thin foil layer (not shown) may rest below a substrate 455 shown.
  • the substrate 455 may include a conductive circuit 452 and an insulative material 407.
  • the substrate may include a conductive circuit 452 and an insulative material 407.
  • the 455 may further include a first surface 456 that is adjacent to the conductive layer or other base and a second surface 457 that is proximate or facing the semiconductor die 412.
  • semiconductor die 412 is shown attached to the substrate above or proximate the second adjacent to the second surface 457.
  • the semiconductor device 400 may include the interconnect joint structure 401 in the substrate 455 creating a capture pad 405.
  • the interconnect joint structure 401 may include a copper layer 410 and an adjacent top nickel layer 411 and an adjacent bottom nickel layer 412.
  • the interconnect joint structure 401 may define a capture pad 405 which includes the first nickel layer 411 followed by the copper layer 410 and the second nickel layer 412.
  • This interconnect joint structure 401 may be found in a single layer of the insulative material 407 or a single applied layer of the substrate 455.
  • the semiconductor die 412 may be attached to the substrate 455 in this manner without a via.
  • the substrate 455 and the interconnect joint structure 401 may be formed using a build-up process. In another
  • a subtractive process may be utilized (i.e. with laser ablation of the insulative material, for example).
  • the nickel layers 411, 412 may be plated layers that are particularly configured to protect during solder or pillar attachment of the semiconductor die 412 when very thin insulative encapsulation layers are necessary.
  • the insulative layer 407 e.g. dielectric, PID or ABF film
  • SMD soldermask defined
  • the nickel layers 411, 412 may provide a barrier to prevent copper consumption by solder (Sn-Pb) during joint intermetallic formation using pillars 420 and solder balls (as shown in Figure 28).
  • An additional nickel layer 415 may be provided adjacent to the first surface 456.
  • This nickel layer 415 may function as an etch stop barrier during thin foil etching from a carrier structure as described hereinabove.
  • a copper layer 416 may be provided above the nickel layer 415.
  • the nickel layer 415 may control the integrity of fine line circuits (e.g. 2 ⁇ ) of the conductive circuit 452 from over etching and poor etching tolerances.
  • Other suitable plating materials are also contemplated other than nickel to provide a barrier, such as zink.
  • a semiconductor device 500 is shown having a semiconductor die 512 with solder balls 514.
  • This embodiment shows an interconnect joint structure 501 that may be applicable to instances when the semiconductor die 512 includes the solder balls 514 instead of the copper pillar 420, and where the insulator acts as a soldermask defined.
  • a single layering process including a first nickel layer 516 followed by a copper layer 518 and another nickel layer 520 are shown to create the interconnect 501.
  • the first nickel layer 516 may be applied to all of the conductive elements to act as an etch barrier, as shown.
  • Another embodiment includes a method for making a semiconductor device that includes providing a substrate, such as the substrate 455, and an insulative layer, such as the insulative layer 107 over the conductive circuit.
  • the method may include forming a capture pad, such as the capture pad 405, in the substrate including a first layer of nickel, such as the first nickel layer 411, a layer of copper over the first nickel layer, such as the layer of copper 412, and a second layer of nickel over the layer of copper, such as the second layer of nickel 411.
  • the method may include etching a layer of copper foil, such as the thin foil on a surface of the substrate.
  • the method may include including the first layer of nickel, the layer of copper, and the second layer of nickel within a single layer of the insulator.
  • the method may include providing a semiconductor die, such as the semiconductor die 512, and attaching the
  • the methd may include providing a nickel layer, such as the nickel layer 415, in the substrate to act as an etch stop barrier between the etched foil layer and the conductive circuit.
  • the method may include the semiconductor die including solder balls, such as the solder balls 514, and attaching the solder balls to at least one of the first and second layers of nickel.
  • a semiconductor device may be provided that includes a semiconductor die; and a substrate having a first surface and a second surface, wherein the semiconductor die is attached to the second surface, the substrate comprising a layer of insulative material and at least a portion of an embedded conductive circuit in the layer of insulative material, wherein the substrate includes an etched layer of a conductive material attached to the portion of the conductive circuit, the etched layer of the conductive material located on the first surface of the substrate.
  • the layer of insulative material may be a photo-imageable dielectric.
  • the layer of insulative material may be an ABF film.
  • the conductive circuit may include a first element including: a first portion in physical contact with the semiconductor die and at least substantially coplanar with the second surface of the substrate; and a second portion disposed on the first portion and at least substantially coplanar with the first surface of the substrate.
  • the first portion may have geometry different from the second portion.
  • the substrate may be built upon a releasable carrier having a layer of the conductive material.
  • the semiconductor die may be attached to the substrate and
  • a semiconductor device may be provided that includes a semiconductor die; and a substrate having a first surface and a second surface, wherein the semiconductor die is attached to the second surface, the substrate comprising a layer of insulative material and an embedded conductive circuit in the layer of insulative material, wherein the substrate includes an etched layer of a conductive material attached to the conductive circuit, wherein the layer of insulative material comprises a material selected from the group consisting of a photo-imageable dielectric and a ABF film.
  • the etched layer of the conductive material may be located on the first surface of the layer of insulative material.
  • the conductive circuit may include a first element including: a first portion in physical contact with the semiconductor die and at least substantially coplanar with the second surface of the substrate; and a second portion disposed on the first portion and at least substantially coplanar with the first surface of the substrate.
  • the first portion may have a geometry different from the second portion.
  • the substrate may be built upon a releasable carrier having a layer of the conductive material.
  • the semiconductor die may be attached to the substrate and encapsulated with a mold before the releasable carrier is removed from the substrate.
  • a method for making a semiconductor device includes patterning a conductive circuit on a conductive foil layer; applying an insulative material over the conductive circuit to create a substrate having a first surface and a second surface, wherein the conductive foil layer is located on the first surface; attaching a semiconductor die to the second surface of the substrate; and etching the conductive foil layer.
  • the insulative material may be a photo-imageable dielectric.
  • the insulative material may be an ABF film.
  • the method may further include providing a releasable carrier attached directly or indirectly to the conductive foil layer.
  • the method may further include encapsulating the semiconductor die after the attaching.
  • the method may include removing the releasable carrier from the conductive foil layer after the encapsulating.
  • a semiconductor device may be provided that includes a substrate comprising a conductive circuit and a first mold material encapsulating the conductive circuit, the first mold material configured to function as an electrical insulator; and a semiconductor die encapsulated with the first mold material or a second mold material.
  • the first mold material may be a thermoplastic mold compound.
  • the conductive circuit may be an entire circuit plane and the first mold material encapsulates the entire circuit plane.
  • the first mold material may not be mixed with thermosetting dielectric materials.
  • the semiconductor die may be encapsulated with the second mold material and not the first mold material.
  • the conductive circuit may be an embedded circuit.
  • the second mold material may have a filler content that is greater than the first mold material.
  • the second mold material may have a filler size that is greater than the first mold material.
  • the substrate may be built upon a thermally activated releasable carrier and the semiconductor die may be attached to the substrate and encapsulated with the at least one of the first mold material and the second mold material before the thermally activated releasable carrier is removed from the substrate.
  • a method for making a semiconductor device includes providing a substrate comprising a first mold material and a conductive circuit encapsulated in the first mold material; providing a
  • the semiconductor die attaching the semiconductor die to the conductive circuit; and encapsulating the semiconductor die with at least one of the first mold material or a second mold material.
  • the first mold material may be a thermoplastic mold compound.
  • the conductive circuit may include an entire circuit plane and the first mold material encapsulates the entire circuit plane.
  • the method may further include preventing the mixing of the first mold material with thermosetting dielectric materials.
  • the method may further include encapsulating the semiconductor die is with the second mold material and not the first mold material.
  • the method may further include embedding the conductive circuit into a layer of the first mold material.
  • the method may further include insulating an entire package structure of a semiconductor device by the sole use of the mold compound.
  • the second mold material may have a filler content that is greater than the first mold material and the second mold material may have a filler size that is greater than the first mold material.
  • the method may further include providing a thermally activated releasable carrier; building the substrate upon the thermally activated releasable carrier, where the semiconductor die is attached to the conductive circuit before the thermally activated releasable carrier is removed from the substrate; exposing the thermally activated releasable carrier to an appropriate temperature; and releasing the thermally activated releasable carrier.
  • a semiconductor device may be provided that includes a substrate comprising a conductive circuit and a first thermoplastic mold material encapsulating the conductive circuit; and a semiconductor die encapsulated with at least one of the first thermoplastic mold material or a second mold material.
  • the first thermoplastic mold material may have been at least partially remolded during the fabrication of the semiconductor device.
  • a semiconductor device may be provided that includes a semiconductor die; a substrate including a first surface and a second surface, the substrate comprising a conductive circuit and an insulative material over the conductive circuit, where the semiconductor die is attached to the second surface; and an interconnect joint structure in the substrate creating a capture pad including a middle copper layer, an adjacent top nickel layer, and an adjacent bottom nickel layer.
  • the conductive circuit may include an etched layer of conductive foil that is located on the first surface of the substrate.
  • the interconnect joint structure may be found in a single layer of the insulative material.
  • the semiconductor die may be attached to the substrate without a via.
  • the substrate and interconnect joint structure may be formed using a build-up process.
  • the substrate and interconnect joint structure may be formed using a subtractive process.
  • the insulative material may include a layer that is less than 12 ⁇ thick.
  • the substrate may further include an etched foil layer, and wherein the substrate further includes a nickel layer etch stop barrier between the conductive circuit and the etched foil layer.
  • the semiconductor die may further include solder bumps for attachment to the interconnect joint structure.
  • a semiconductor device may be provided that includes a semiconductor die; a substrate including a first and a second surface, the second surface attached to the semiconductor die, the substrate including a conductive circuit and an insulative material over the conductive circuit; and an interconnect joint structure in the substrate including a middle copper layer, an adjacent top nickel layer, and an adjacent bottom nickel layer, where the interconnect joint structure is found within a single layer of the insulative material.
  • the interconnect joint structure may create a capture pad.
  • the conductive circuit may include an etched layer of conductive foil that is located on the first surface of the substrate.
  • a method for making a semiconductor device includes providing a substrate including conductive circuit and an insulative material over the conductive circuit; and forming a capture pad in the substrate including a first layer of nickel, a layer of copper over the first layer of nickel, and a second layer of nickel over the layer of copper.
  • the method may include etching a layer of copper foil on a surface of the substrate.
  • the method may include including the first layer of nickel, the layer of copper, and the second layer of nickel within a single layer of the insulative material.
  • the method may include providing a semiconductor die and attaching the
  • the insulative material may be at least one of a photo-imagable dielectric and ABF film.
  • the insulative material may be less than 12 ⁇ thick.
  • the method may include providing a nickel layer in the substrate to act as an etch stop barrier between the etched foil layer and the conductive circuit.
  • the semiconductor die may include solder balls, and where the method may further include attaching the solder balls to at least one of the first and second layers of nickel.

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  • Laminated Bodies (AREA)

Abstract

La présente invention concerne un porteur amovible qui inclut un porteur de soutien, une couche conductrice porteuse, et un ruban amovible situé entre le porteur de soutien et la couche conductrice porteuse. Le ruban amovible fixe le porteur de soutien à la couche conductrice porteuse. Le ruban amovible sert à retirer le porteur de soutien de la couche conductrice porteuse après avoir été exposé à une source d'activation. Le porteur amovible inclut en outre une couche mince conductrice fixée à la couche conductrice porteuse, la couche mince conductrice créant une surface servant à recevoir un circuit conducteur. L'invention concerne en outre un procédé de fabrication du porteur amovible et un procédé de réalisation d'un dispositif semi-conducteur au moyen du porteur amovible.
PCT/US2017/013336 2016-01-14 2017-01-13 Porteur amovible et procédé Ceased WO2017123870A1 (fr)

Applications Claiming Priority (10)

Application Number Priority Date Filing Date Title
US201662388023P 2016-01-14 2016-01-14
US62/388,023 2016-01-14
US15/211,290 2016-07-15
US15/211,481 2016-07-15
US15/211,384 2016-07-15
US15/211,384 US20170018448A1 (en) 2015-07-15 2016-07-15 Semiconductor device and method
US15/211,631 2016-07-15
US15/211,481 US10332775B2 (en) 2015-07-15 2016-07-15 Releasable carrier and method
US15/211,290 US9941146B2 (en) 2015-07-15 2016-07-15 Semiconductor device and method
US15/211,631 US9847244B2 (en) 2015-07-15 2016-07-15 Semiconductor device and method

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Citations (5)

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Publication number Priority date Publication date Assignee Title
US6140702A (en) * 1996-05-31 2000-10-31 Texas Instruments Incorporated Plastic encapsulation for integrated circuits having plated copper top surface level interconnect
US7147740B2 (en) * 2002-05-17 2006-12-12 Semiconductor Energy Laboratory Co., Ltd. Method of transferring a laminate and method of manufacturing a semiconductor device
US7836586B2 (en) * 2008-08-21 2010-11-23 National Semiconductor Corporation Thin foil semiconductor package
US8176627B2 (en) * 2007-02-28 2012-05-15 Shinko Electric Industries Co., Ltd. Method of manufacturing wiring substrate and method of manufacturing electronic component device
WO2015073047A1 (fr) * 2013-11-18 2015-05-21 Empire Technology Development Llc Dispositif électronique flexible

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6140702A (en) * 1996-05-31 2000-10-31 Texas Instruments Incorporated Plastic encapsulation for integrated circuits having plated copper top surface level interconnect
US7147740B2 (en) * 2002-05-17 2006-12-12 Semiconductor Energy Laboratory Co., Ltd. Method of transferring a laminate and method of manufacturing a semiconductor device
US8176627B2 (en) * 2007-02-28 2012-05-15 Shinko Electric Industries Co., Ltd. Method of manufacturing wiring substrate and method of manufacturing electronic component device
US7836586B2 (en) * 2008-08-21 2010-11-23 National Semiconductor Corporation Thin foil semiconductor package
WO2015073047A1 (fr) * 2013-11-18 2015-05-21 Empire Technology Development Llc Dispositif électronique flexible

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