WO2017124440A1 - 超声成像的装置和方法 - Google Patents

超声成像的装置和方法 Download PDF

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Publication number
WO2017124440A1
WO2017124440A1 PCT/CN2016/071766 CN2016071766W WO2017124440A1 WO 2017124440 A1 WO2017124440 A1 WO 2017124440A1 CN 2016071766 W CN2016071766 W CN 2016071766W WO 2017124440 A1 WO2017124440 A1 WO 2017124440A1
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Prior art keywords
signal
digital
analog
chip
operable
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PCT/CN2016/071766
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English (en)
French (fr)
Inventor
曹培炎
张�林
张甲
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Shenzhen Genorivision Technology Co Ltd
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Shenzhen Genorivision Technology Co Ltd
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Priority to EP16885713.4A priority Critical patent/EP3407084A4/en
Priority to PCT/CN2016/071766 priority patent/WO2017124440A1/zh
Priority to US16/069,919 priority patent/US20190029645A1/en
Publication of WO2017124440A1 publication Critical patent/WO2017124440A1/zh
Anticipated expiration legal-status Critical
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    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
    • A61B8/00—Diagnosis using ultrasonic, sonic or infrasonic waves
    • A61B8/44—Constructional features of the ultrasonic, sonic or infrasonic diagnostic device
    • A61B8/4483—Constructional features of the ultrasonic, sonic or infrasonic diagnostic device characterised by features of the ultrasound transducer
    • A61B8/4494—Constructional features of the ultrasonic, sonic or infrasonic diagnostic device characterised by features of the ultrasound transducer characterised by the arrangement of the transducer elements
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/52—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S15/00
    • G01S7/52017—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S15/00 particularly adapted to short-range imaging
    • G01S7/52023—Details of receivers
    • G01S7/52025—Details of receivers for pulse systems
    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
    • A61B8/00—Diagnosis using ultrasonic, sonic or infrasonic waves
    • A61B8/46—Ultrasonic, sonic or infrasonic diagnostic devices with special arrangements for interfacing with the operator or the patient
    • A61B8/461—Displaying means of special interest
    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
    • A61B8/00—Diagnosis using ultrasonic, sonic or infrasonic waves
    • A61B8/52—Devices using data or image processing specially adapted for diagnosis using ultrasonic, sonic or infrasonic waves
    • A61B8/5207—Devices using data or image processing specially adapted for diagnosis using ultrasonic, sonic or infrasonic waves involving processing of raw data to produce diagnostic data, e.g. for generating an image
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B06—GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS IN GENERAL
    • B06B—METHODS OR APPARATUS FOR GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS OF INFRASONIC, SONIC, OR ULTRASONIC FREQUENCY, e.g. FOR PERFORMING MECHANICAL WORK IN GENERAL
    • B06B1/00—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency
    • B06B1/02—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency making use of electrical energy
    • B06B1/0207—Driving circuits
    • B06B1/0215—Driving circuits for generating pulses, e.g. bursts of oscillations, envelopes
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B06—GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS IN GENERAL
    • B06B—METHODS OR APPARATUS FOR GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS OF INFRASONIC, SONIC, OR ULTRASONIC FREQUENCY, e.g. FOR PERFORMING MECHANICAL WORK IN GENERAL
    • B06B1/00—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency
    • B06B1/02—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency making use of electrical energy
    • B06B1/06—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency making use of electrical energy operating with piezoelectric effect or with electrostriction
    • B06B1/0607—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency making use of electrical energy operating with piezoelectric effect or with electrostriction using multiple elements
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/52—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S15/00
    • G01S7/52017—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S15/00 particularly adapted to short-range imaging
    • G01S7/52096—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S15/00 particularly adapted to short-range imaging related to power management, e.g. saving power or prolonging life of electronic components
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00—Image analysis
    • G06T7/0002—Inspection of images, e.g. flaw detection
    • G06T7/0012—Biomedical image inspection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B06—GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS IN GENERAL
    • B06B—METHODS OR APPARATUS FOR GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS OF INFRASONIC, SONIC, OR ULTRASONIC FREQUENCY, e.g. FOR PERFORMING MECHANICAL WORK IN GENERAL
    • B06B2201/00—Indexing scheme associated with B06B1/0207 for details covered by B06B1/0207 but not provided for in any of its subgroups
    • B06B2201/40—Indexing scheme associated with B06B1/0207 for details covered by B06B1/0207 but not provided for in any of its subgroups with testing, calibrating, safety devices, built-in protection, construction details
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B06—GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS IN GENERAL
    • B06B—METHODS OR APPARATUS FOR GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS OF INFRASONIC, SONIC, OR ULTRASONIC FREQUENCY, e.g. FOR PERFORMING MECHANICAL WORK IN GENERAL
    • B06B2201/00—Indexing scheme associated with B06B1/0207 for details covered by B06B1/0207 but not provided for in any of its subgroups
    • B06B2201/70—Specific application
    • B06B2201/76—Medical, dental
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2207/00—Indexing scheme for image analysis or image enhancement
    • G06T2207/10—Image acquisition modality
    • G06T2207/10132—Ultrasound image
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2207/00—Indexing scheme for image analysis or image enhancement
    • G06T2207/30—Subject of image; Context of image processing
    • G06T2207/30004—Biomedical image processing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/28—Configurations of stacked chips the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

  • Embodiments of the present disclosure generally relate to digital imaging techniques and, more particularly, to methods and apparatus for ultrasound imaging.
  • Ultrasonic waves with a frequency above 20,000 Hz are called ultrasonic waves, referred to as ultrasound.
  • Ultrasound imaging is, for example, a method of examining and recording a disease in the form of a waveform, a curve, or an image by utilizing the difference in the physical properties of the ultrasound and the acoustic properties of the human organ tissue.
  • Medical high-frequency ultrasound is generated by a piezoelectric transducer on an ultrasound diagnostic device, also known as a probe, that converts electrical energy into ultrasonic energy to emit ultrasound. At the same time, it can accept the returned ultrasound and convert it into an electrical signal. This electrical signal is processed for ultrasound imaging.
  • Ultrasonic diagnostic equipment is not as expensive as CT or MRI equipment, and can obtain any cross-sectional image of the organ. It can also observe the movement of the moving organ, fast imaging, timely diagnosis, painlessness and danger, and non-invasive examination. Therefore, such devices have become popular in clinical applications and are an important part of medical imaging.
  • Existing ultrasound imaging devices have some limitations that limit the application of ultrasound imaging. For example, existing ultrasound imaging devices are relatively large in size and weight, and have high power consumption, which is not suitable for portable use.
  • example embodiments of the present disclosure provide apparatus and methods for ultrasound imaging.
  • an apparatus for ultrasound imaging comprising: a first chip operable to: receive an ultrasound signal, the ultrasound signal is an analog signal; and generate a digital signal representative of the ultrasound signal And a second chip operable to process the digital signal from the first chip for ultrasound imaging.
  • the first chip is stacked on the second chip to form a three-dimensional stacked chip package.
  • the second chip comprises a digital signal processor fabricated using an application specific integrated circuit process.
  • the first chip includes a plurality of signal channels, each of the signal channels including: a low noise amplifier operable to generate a first amplified signal by amplifying the ultrasonic signal; a variable gain amplifier The operation is to generate a second amplified signal by amplifying the first amplified signal; and an analog to digital converter operable to convert the second amplified signal into the digital signal.
  • the low noise amplifier comprises a differential current multiplexed low noise amplifying circuit comprising: a first branch comprising a series P-type MOS transistor and N a MOS transistor; a second branch comprising a series P-type MOS transistor and an N-type MOS transistor; and wherein the P-type MOS transistor and the N-type metal oxide A gate of the semiconductor transistor is coupled to the input capacitor to receive the differential input signal, and a drain of the P-type metal-oxide-semiconductor transistor and the N-type MOS transistor outputs the first amplified signal.
  • the analog to digital converter includes: a first stage converter operative to generate the converted first digital signal and the amplified first residual analog signal based on the second amplified signal; a second stage analog to digital converter of the voltage controlled oscillator operable to generate a second digital signal based on the first residual analog signal; and a digital calibration circuit operable to be based on the first digital signal and the The two digital signals generate the calibrated digital signals.
  • the first stage converter includes: a blinking analog to digital converter operative to generate the first digital signal based on the second amplified signal and a first reference signal; a digital to analog converter, Controlling to generate a first analog signal according to the first digital signal and the first reference signal; adding and subtracting, operable to generate a residual signal according to the second amplified signal and the first analog signal; And a residual amplifier operative to generate the first margin analog signal based on the margin signal.
  • the margin amplifier includes a charge pump based voltage multiplying circuit operable to store the pair of the margin signals during the first phase; and during the second phase The pair of the remaining amount signals are combined and output as the first margin analog signal.
  • the second stage analog to digital converter includes: a sample and hold circuit operable to sample and hold the first remaining analog signal to generate a sampled voltage signal; a voltage to current conversion circuit The operation is to convert the sampled voltage signal into a sampled current signal; the flow control oscillator is operable to generate an oscillating signal according to the sampled current signal; the bidirectional counter operable to count according to the oscillating signal; and adding and subtracting The device is operable to calculate the digital signal based on a count result from the bidirectional counter.
  • a portable ultrasonic detecting apparatus comprising: an ultrasonic transducer operable to generate an ultrasonic signal by detecting; the apparatus according to the above item operable to generate according to the ultrasonic signal a digital signal for ultrasound imaging; and a display device operable to image based on the digital signal.
  • a method for ultrasound imaging comprising: receiving an ultrasound signal using a first chip, the ultrasound signal being an analog signal; generating a number representing the ultrasound signal using the first chip Signaling; processing the digital digital signal from the first chip for ultrasound imaging with a second chip different from the first chip.
  • an imaging method for a portable ultrasonic detecting apparatus comprising: generating an ultrasonic signal using an ultrasonic transducer; using the apparatus according to the above item to generate an ultrasound for the ultrasonic signal according to the ultrasonic signal An imaged digital signal; and imaging based on the digital signal.
  • a method for producing an ultrasonic imaging apparatus comprising: providing a component included in the apparatus according to the above item.
  • FIG. 1 is a simplified block diagram of an environment in which some embodiments of the present disclosure may be implemented
  • FIG. 2 is a perspective view showing a chip stack of an apparatus for ultrasonic imaging according to an embodiment of the present disclosure
  • FIG. 3 is a block diagram showing an apparatus for ultrasound imaging, in accordance with one embodiment of the present disclosure.
  • FIG. 4 is a circuit diagram showing one example of the low noise amplifier of FIG. 3;
  • FIG. 5 is a block diagram showing one example of the analog to digital converter of FIG. 3;
  • Figure 6 is a detailed block diagram showing one example of the analog to digital converter of Figure 5;
  • FIG. 7 is a circuit diagram showing one example of the margin amplifier shown in FIG. 6;
  • FIG. 8 is a block diagram showing one example of the second-stage analog-to-digital converter shown in FIG. 6;
  • FIG. 9 is a flow chart illustrating a method in accordance with some embodiments of the present disclosure.
  • the term “comprise” and its various variants may be understood to mean an open term, which means “including but not limited to”.
  • the term “based on” can be understood to mean “based at least in part.”
  • the term “an embodiment” can be understood to mean “at least one embodiment.”
  • the term “another embodiment” may be understood to mean “at least one other embodiment.”
  • the term “logic” refers to a module such as a circuit device for certain functions at the time.
  • the terms “signal stream” and “data stream” may be used interchangeably for purposes of discussion. Other obvious features are included below Implied definition.
  • the ultrasonic signal acquisition and processing device includes a plurality of signal receiving channels, and the ultrasonic signals sequentially pass through a transducer, a low noise amplifier (LNA), a variable gain amplifier (VGA), an analog-to-digital converter (ADC) in each receiving channel, Digital beamformers, digital signal processing (DSP) and other circuits are output to the display processor for imaging.
  • LNA low noise amplifier
  • VGA variable gain amplifier
  • ADC analog-to-digital converter
  • DSP digital signal processing
  • a typical ultrasound imaging system typically contains 32 to 256 signal receiving channels.
  • the ultrasonic signal acquisition processing chip in the existing ultrasonic imaging apparatus is generally implemented to include at least three chips (ie, a gain amplifying chip, an analog-to-digital conversion chip, and a digital signal processing chip).
  • Gain amplification chips and analog-to-digital conversion chips are versatile general-purpose chips, and digital signal processing chips are usually implemented using field-programmable gate arrays (FPGAs).
  • FPGAs field-programmable gate arrays
  • FPGAs have the advantages of good versatility and ease of development.
  • the above three chips in the existing ultrasonic imaging apparatus are also generally disposed in the same plane on the same substrate, and are connected by electrical wiring. The advantage of this configuration is that the configuration is flexible, but the power consumption is large.
  • each channel of the analog front end consumes 75 milliwatts (mW) of power, with the LNA and VCA consuming 20 mW and the ADC consuming 55 mW.
  • the entire analog front end consumes a total of 4.8W.
  • the Xilinx FPGA in the digital signal processing module consumes 1.5W of power.
  • the entire solution consumes at least 6.3W of power. This power consumption makes the solution suitable only for grid-powered base station systems and not for portable ultrasound detectors.
  • the apparatus for ultrasonic imaging for example, after receiving the ultrasonic analog signal transmitted by the ultrasonic transducer, the analog front end chip in the apparatus amplifies and analog-digital converts the ultrasonic analog signal to A digital signal for ultrasound imaging is obtained. The digital signal is then transmitted to the Digital signal processing chip for digital signal processing. Image data suitable for display on a display device such as a liquid crystal display is finally obtained.
  • Embodiments of the present disclosure greatly reduce power consumption of an ultrasound device by dividing chip functionality, integrating the partitioned functions into two different chips, and redesigning the circuit structure, and enabling for use in accordance with some embodiments of the present disclosure
  • Ultrasound imaging devices can be adapted for portable ultrasound imaging devices.
  • FIG. 1 illustrates a simplified block diagram of an environment in which some embodiments of the present disclosure may be implemented.
  • Environment 100 includes an ultrasound transducer 102, a host 104, and a display 106.
  • the host 104 includes means for ultrasound imaging and other peripheral components.
  • the ultrasound transducer 102 can be used, for example, to transmit ultrasound waves to scan a human body, receive an echo signal and convert it into an analog electrical signal representative of the ultrasound signal.
  • the analog electrical signal is transmitted to a device in the host 104 for ultrasound imaging.
  • the apparatus for ultrasound imaging then processes the analog electrical signals, such as amplification, filtering, digital to analog conversion, digital signal processing (DSP), etc., to obtain image data suitable for display on display 106.
  • the display 106 is, for example, a liquid crystal display (LCD) that can display an image of, for example, human tissue upon receipt of image data.
  • LCD liquid crystal display
  • the ultrasonic transducer 102, the host 104, and the display 106 are shown as separate components in FIG. 1, it will be understood that these components can be integrated into one device.
  • the configuration shown in FIG. 1 is merely an example and is not intended to limit the scope of the disclosure.
  • the three components can be optionally separated and combined without departing from the scope of the present disclosure.
  • the chip stack 200 can be included, for example, in the host 102 shown in FIG. 1 for, for example, amplifying, converting, and processing an analog form of the ultrasonic signal from the ultrasonic transducer 102.
  • the chip stack 200 is implemented in the form of a three-dimensional (3D) chip stack including a first chip (analog front end chip) 202, a second chip (digital signal processing chip) 206, and a package substrate 210.
  • the package substrate 210 is used to support the second chip 206.
  • There are a plurality of electrical connection terminals on the package substrate 210 two rows of terminals are shown in FIG.
  • the first chip 202 is vertically integrated with the second chip 206 by a plurality of Copper Pillar Micro Bumps or similar techniques. High-throughput high-speed data between the two chips is transmitted through Micro Bumps to greatly reduce channel capacitance and power consumption.
  • the digital signal processing chip is electrically connected to the package substrate 210 by wire bonding.
  • the chip stack 200 is then packaged in a single device for use by the ultrasound imaging device.
  • the three-dimensional packaging technology can greatly reduce the parasitic capacitance of the signal transmission channel between the two chips, thereby effectively reducing the power consumption of a large amount of high-speed data transmission between the two chips.
  • the use of three-dimensional packaging technology can greatly reduce the package area of the overall solution, thereby reducing the end product, such as reducing the weight and volume of the portable ultrasonic detector.
  • Chip on Wafer on Substrate (CoWoS) packaging technology and F2F FlipStack CSP packaging technology can be used to vertically integrate multiple chips to reduce interconnection capacitance. And the package area.
  • FIG. 2 illustrates a three-dimensional stacking of the substrate 210 - the second chip 206 - the first chip 202, other three-dimensional stacking methods may be used.
  • power consumption of the ultrasound apparatus can be greatly reduced by redesigning the circuit, customizing the chip, and three-dimensionally stacking according to embodiments of the present disclosure.
  • the device may be part of the host 104 of Figure 1 and corresponds to the device shown in Figure 2.
  • the device includes a first chip 202 and a second chip 206.
  • the first chip 202 includes a plurality of channels 300, each of which includes a low noise amplifier (LNA) 302, a variable gain amplifier (VGA) 304, and an analog to digital converter (ADC) 306.
  • the low noise amplifier 302 receives the weak ultrasonic pulse feedback electrical signal from the ultrasonic transducer and amplifies it and transmits it to the variable gain amplifier 304.
  • the variable gain amplifier 304 is, for example, a programmable variable gain amplifier (PGA) or a voltage regulated variable gain amplifier (VCA).
  • PGA programmable variable gain amplifier
  • VCA voltage regulated variable gain amplifier
  • the analog signal is transmitted to analog to digital converter 306, which is converted to a digital signal via an analog to digital converter for further post processing by second chip 206.
  • the digital signal processing chip is composed of a large number of DSP modules, and the ultrasonic pulse feedback signal is amplified and digitized by the analog front end. Perform post-processing such as filtering, equalization, and noise reduction, and send the processing result to the operating system (OS) and user interface (UI) of the ultrasound probe for analysis and judgment by the instrument user.
  • OS operating system
  • UI user interface
  • the ultrasonic pulse feedback signal received by the ultrasonic transducer is typically weak to only a few millivolts (mV). If amplified to the desired input voltage level of the subsequent analog-to-digital converter (on the order of 100 mV), the amplifier circuit needs to provide a gain of at least 40 dB.
  • a low noise amplifying circuit can be placed at the input of the analog front end chip to ensure that the amplifying circuit does not simultaneously introduce and amplify too much circuit noise during the amplification of the desired signal. In this way, the adverse effect on the signal to noise ratio at the input of the analog to digital converter can be avoided.
  • the low-noise amplifier circuit on the one hand needs to provide enough gain for the input useful signal to suppress the noise of the subsequent circuit, and on the other hand, to ensure that it introduces as little noise as possible.
  • the input device of the low noise amplifier provides a large transconductance (gm), which may result in greater power consumption.
  • a single-ended current design is typically used. Only one input device (eg, an N-type metal-oxide-semiconductor transistor (NMOS)) provides a transconductance in a single-ended current design.
  • NMOS N-type metal-oxide-semiconductor transistor
  • the current multiplexed differential input low noise amplifying circuit 302 includes two branches, each of which is connected between Vdd and current source 410.
  • the first leg includes a P-type metal-oxide-semiconductor transistor (PMOS) 402 and an N-type metal-oxide-semiconductor transistor (NMOS) 404 connected in series.
  • the second branch includes PMOS 408 and NMOS 406 in series.
  • the gates of the PMOS and NMOS are each coupled to the input capacitor to receive the differential input signal, and the drains of the PMOS and NMOS output the first amplified signal.
  • the transconductance of the two input devices is simultaneously provided by a single-ended current, which significantly reduces the power consumption of the LNA.
  • the circuit provides twice the transconductance of conventional circuits while consuming the same current.
  • the low-noise amplifier circuit using current multiplexing can reduce the power consumption of half of the circuit while satisfying the same noise performance as the conventional low-noise amplifier circuit. Since ultrasound detectors usually require a large number of signal channels (such as 64 signal channels), each channel requires a low-noise amplifier circuit, thus reducing the low Half the power consumption of the noise amplifier circuit will significantly reduce the power consumption of the entire ultrasound probe.
  • the analog-to-digital converter in the existing ultrasonic imaging apparatus consumes more power consumption when performing analog-to-digital conversion, for example, the ADC of each channel consumes 50 mW. For a 64 channel device, this will consume a total of 3.2W. This power consumption is clearly unacceptable for battery powered portable ultrasound imaging equipment.
  • the signal sampling frequency of the ultrasonic detector is generally between 20 megahertz (MHz) and 60 MHz, and the accuracy of analog-to-digital conversion is required to be 12 bits or even 14 bits.
  • Flash ADC flash analog-to-digital converter
  • FIG. 5 a block diagram of one example of the analog to digital converter of Figure 3 is shown.
  • the analog to digital converter 306 of FIG. 5 is a mixed-structure analog-to-digital converter operating in a voltage domain and a time domain, including a first-stage converter 502, a second-stage analog-to-digital converter 504 based on a voltage controlled oscillator. And a digital calibration circuit 506.
  • the first stage converter 502 operates in a voltage domain and is operable to generate a converted first digital signal and an amplified first residual analog signal based on a second amplified signal from the variable gain amplifier 304, wherein the first digital signal To represent several bits of the higher bits of the digital bits of the ultrasound signal, such as the first 5 bits.
  • the second stage analog to digital converter 504 is, for example, a voltage controlled oscillator based analog to digital converter operating in the time domain, operable to generate a second digital signal based on the first residual analog signal, wherein the second digital signal is indicative The lower bits of the digital bits of the ultrasound signal, such as the last 9 bits.
  • the digital calibration circuit 506 is operable to generate a calibrated digital signal Dout based on the first digital signal and the second digital signal.
  • a first stage converter and a second stage analog to digital converter are provided.
  • a second stage analog to digital converter can use a voltage controlled oscillator (VCO) based analog to digital converter.
  • VCO voltage controlled oscillator
  • a voltage-controlled oscillator-based analog-to-digital converter enables high dynamic range analog-to-digital conversion of small signals.
  • a voltage-controlled oscillator based analog to digital converter can consume less power than an analog to digital converter of conventional voltage mode. This advantage is even more pronounced in small size production processes such as the 65 nm production process.
  • the voltage-controlled oscillator requires an input voltage level that is much smaller than that of a conventional voltage-mode analog-to-digital converter, so that the margin of the first-stage analog-to-digital conversion can be directly converted by the voltage-controlled oscillator without a large gain.
  • This makes it possible to reduce the requirements of the first-stage converter, for example, with an operating amplifier (Opamp) that consumes less power.
  • Opamp operating amplifier
  • the voltage controlled oscillator processes a small input signal, there is no need to leave a margin between the two-stage converters. As long as the counter of the voltage controlled oscillator count is sufficient to count the range, the first stage can be Errors are calibrated and corrected. This can further reduce the requirements for the first stage converter.
  • the ADC of FIG. 6 includes a first stage converter (shown in phantom) 502, a second stage analog to digital converter 504, and a digital calibration circuit 506. Similar to the block diagram of FIG. 5, the first stage converter 502 outputs the first 5 bits of digital bits to the digital calibration circuit 506, and the second stage analog to digital converter outputs the last 9 bits of digital bits to the digital calibration circuit 506.
  • the digital calibration circuit 506 calibrates and combines the digital bits of the two portions and outputs a bit combination Dout having a particular number of bits (e.g., 13 bits), with the extra bit being used for the margin of digital calibration.
  • the first stage converter 502 includes a blinking analog to digital converter 606, a digital to analog converter 608, an adder-subtractor 604, and a residual amplifier 602.
  • Flash ADC 606 is operable as a second amplified signal V in and a first reference signal V ref to generate a first digital signal (as described above before a digital bit 5) according to.
  • a flashing analog to digital converter is not suitable for conversions greater than 8 bits.
  • such a device is fast and has a simple circuit structure and thus can serve as a first-stage conversion. This is because, in the two-stage conversion according to an embodiment of the present disclosure, the first-stage conversion usually only needs to output the first few bits (for example, 5 bits).
  • the digital to analog converter 608 is operable to generate a first analog signal based on the first digital signal and the first reference signal Vref .
  • the adder-subtractor 604 then calculates a margin signal for generating the last 9-bit digital bits based on the second amplified signal V in and the first analog signal.
  • the margin signal is then amplified by a margin amplifier 602 to generate a first margin analog signal.
  • the second stage analog to digital converter 504 is, for example, a second stage analog to digital converter based on a voltage controlled oscillator that is less demanding for the residual signal and input voltage, as described above. For example, referring to FIG.
  • the second stage analog to digital converter 504 generates the last 9 bits of digital bits based on the first margin analog signal and the second reference signal Vref /8.
  • the second-stage analog-to-digital converter uses a voltage-controlled oscillator-based scheme and requires less input voltage, power consumption can be significantly reduced.
  • a voltage multiplying circuit can be used to amplify the residual signal.
  • Fig. 7 is a circuit diagram showing an example of the margin amplifier shown in Fig. 6.
  • the voltage multiplying circuit 602 is a switched capacitor circuit that implements signal processing by switching on and off of different phase switches.
  • V in — cm is, for example, the ground of AC.
  • FIG. 8 is a block diagram showing one example of the second-stage analog-to-digital converter shown in FIG. 6.
  • the second stage analog to digital converter 504 includes a sample and hold circuit 802, a voltage to current conversion circuit 804, a flow control oscillator 806, a bidirectional counter 808 and an adder-subtractor (shown in dashed box) 810, wherein the voltage to current conversion circuit 804 and flow control oscillator 806 constitute The voltage controlled oscillator described.
  • the sample and hold circuit 802 receives the first margin analog signal from the margin amplifier 602 and samples the first margin analog signal and holds it on the sampling capacitor in accordance with the control of the switching signal fs to generate a differential sample voltage signal.
  • the differentially sampled voltage signal is then input to a voltage to current conversion circuit 804.
  • the voltage to current conversion circuit 804 is a source degenerated differential input circuit that includes two branches coupled to a current source, each branch including an NMOS transistor and a resistor in series.
  • the gate of the NMOS transistor is coupled to a sample and hold circuit 802 to receive a differential sampled voltage signal.
  • the drain of the NMOS is coupled directly or indirectly to the current output of the voltage to current converter to provide a sampled current signal to the flow control oscillator 806.
  • a current regulated oscillator (CCO) 806 generates an oscillating signal based on the sampled current signal.
  • the oscillating frequency of the oscillating signal is proportional to the input control current such that the frequency difference between the two current regulating oscillators is proportional to the current signal of the differential input and is also proportional to the voltage signal of the differential input.
  • the bidirectional counter 808 counts based on the oscillating signal.
  • the oscillation frequencies of the two current-regulated oscillators are recorded by two bidirectional counters, respectively.
  • the adder-subtractor 810 then calculates a digital signal based on the count result from the bidirectional counter 808.
  • the adder-subtractor 810 subtracts the counts of the voltage signals representing the differential inputs to generate a count result proportional to the frequency difference between the two current-regulated oscillators, which is proportional to the input differential voltage.
  • Two digital signals The digital signal is then calibrated by digital calibration circuit 506 and combined with the first digital signal to generate a digital signal.
  • the digital signal is then processed by a DSP in the second chip 206 to generate image data for display by the display.
  • FIG. 9 shows a flow chart of a method in accordance with some embodiments of the present disclosure.
  • Method 900 can be implemented, for example, by the apparatus of Figures 2 and 3.
  • the ultrasound signal is received using the first chip 202.
  • the first chip 202 has a terminal connected to an external component to receive an analog electrical signal from the ultrasonic transducer representing the ultrasonic signal.
  • a digital signal representative of the ultrasound signal is generated using the first chip 202.
  • the first chip 202 has a plurality of channels 300, each of which includes an LNA 302, a VGA 304, and an ADC 306 for use in analog power representing ultrasonic signals.
  • the signal is subjected to low noise amplification, variable gain amplification, and analog to digital conversion to generate a digital signal representative of the ultrasonic signal.
  • the power consumption during ultrasound signal amplification and conversion can be greatly reduced, making the method suitable for portable ultrasound equipment.
  • the digital digital signal from the first chip is processed with a second chip 206 different from the first chip 202 for ultrasound imaging.
  • a second chip fabricated using application specific integrated circuit (ASIC) technology includes a digital signal processing (DSP) unit.
  • DSP digital signal processing
  • the second chip fabricated using ASIC technology can achieve more optimized circuit power consumption and Area and reduce the production cost of the chip.
  • the second chip 206 filters, equalizes and denoises the ultrasonic pulse feedback signal amplified and digitized by the analog front end, and sends the processing result to the operating system (OS) and user interface (UI) of the ultrasonic detector for the instrument.
  • OS operating system
  • UI user interface
  • embodiments of the present disclosure are directed to apparatus and methods for ultrasound imaging.
  • the device and method are particularly suitable for portable ultrasound imaging devices because of their low power consumption and small size.
  • embodiments of the present disclosure redesign and integrate them into two separate chips by decomposing the functions of the components in the ultrasound device, and then integrated into one package by 3D packaging technology. Internal to achieve power and area optimization.
  • embodiments of the present disclosure greatly reduce the power consumed by the analog front end by redesigning circuits in the analog front end chip, particularly low noise amplifiers and analog to digital converters, such that the ultrasound is used in accordance with embodiments of the present disclosure.
  • the imaged device can be applied to a portable ultrasound imaging device.

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Abstract

一种超声成像的装置，该装置包括第一芯片(202)和第二芯片(206)，第一芯片(202)接收超声信号并生成表示超声信号的数字信号，该超声信号是模拟信号；第二芯片(206)处理来自第一芯片(202)的数字信号用于超声成像。该装置能够减少超声成像装置的功耗。还公开了相应的超声成像的方法。

Description

超声成像的装置和方法 技术领域
本公开的实施例总体涉及数字成像技术，并且更具体而言，涉及用于超声成像的方法和设备。
背景技术
频率在2万赫兹以上的机械振动波称为超声波(ultrasonic wave)，简称超声(ultrasound)。超声成像例如是利用超声的物理特性和人体器官组织声学性质上的差异，以波形、曲线或图像的形式显示和记录，借以进行疾病诊断的检查方法。医用高频超声波由超声诊断仪上的压电换能器产生，这种换能器又称为探头，能将电能转换为超声能，从而发射超声波。同时，它也能接受返回的超声波并把它转换成电信号。该电信号经过处理后被用于超声成像。超声诊断设备不似CT或MRI设备那样昂贵，可获得器官的任意断面图像，还可观察运动器官的活动情况、成像快、诊断及时、无痛苦与危险、属于非损伤性检查。因此，这种设备在临床上应用已普及，是医学影像学中的重要组成部分。
现有的超声成像设备存在一些制约因素限制超声成像的应用领域的拓宽。例如，现有的超声成像设备体积和重量相对较大，功耗较高，不利于便携使用。
发明内容
总体而言，本公开的示例实施例提供用于超声成像的装置和方法。
根据本公开的第一方面，提供一种用于超声成像的装置，包括：第一芯片，可操作为：接收超声信号，所述超声信号是模拟信号；以及生成表示所述超声信号的数字信号；以及第二芯片，可操作为处理来自所述第一芯片的所述数字信号以用于超声成像。
在一些实施例中，所述第一芯片被堆叠在所述第二芯片上以形成三维堆叠芯片封装。
在一些实施例中，所述第二芯片包括使用专用集成电路工艺制作的数字信号处理器。
在一些实施例中，所述第一芯片包括多个信号通道，每个所述信号通道包括：低噪声放大器，可操作为通过放大所述超声信号生成第一放大信号；可变增益放大器，可操作为通过放大所述第一放大信号生成第二放大信号；以及模数转换器，可操作为将所述第二放大信号转换成所述数字信号。
在一些实施例中，所述低噪声放大器包括差分电流复用低噪声放大电路，所述差分电流复用低噪声放大电路包括：第一支路，包括串联的P型金属氧化物半导体晶体管和N型金属氧化物半导体晶体管；第二支路，包括串联的P型金属氧化物半导体晶体管和N型金属氧化物半导体晶体管；以及其中所述P型金属氧化物半导体晶体管和所述N型金属氧化物半导体晶体管的栅极均与输入电容器耦合以接收差分输入信号，以及所述P型金属氧化物半导体晶体管和所述N型金属氧化物半导体晶体管的漏极输出所述第一放大信号。
在一些实施例中，所述模数转换器包括：第一级转换器，可操作为根据所述第二放大信号生成经转换的第一数字信号和经放大的第一余量模拟信号；基于压控振荡器的第二级模数转换器，可操作为根据所述第一余量模拟信号生成第二数字信号；以及数字校准电路，可操作为根据所述第一数字信号和所述第二数字信号生成经校准的所述数字信号。
在一些实施例中，所述第一级转换器包括：闪烁型模数转换器，可操作为根据所述第二放大信号和第一参考信号生成所述第一数字信号；数模转换器，可操作为根据所述第一数字信号和所述第一参考信号生成第一模拟信号；加减法器，可操作为根据所述第二放大信号和所述第一模拟信号生成余量信号；以及余量放大器，可操作为根据所述余量信号生成所述第一余量模拟信号。
在一些实施例中，所述余量放大器包括基于电荷泵的电压倍增电路，所述电压倍增电路可操作为：在第一阶段期间存储成对的所述余量信号；以及在第二阶段期间将所述成对的所述余量信号组合地输出为所述第一余量模拟信号。
在一些实施例中，所述第二级模数转换器包括：采样保持电路，可操作为对所述第一余量模拟信号进行采样和保持以生成采样电压信号；电压到电流转换电路，可操作为将所述采样电压信号转换为采样电流信号；流控振荡器，可操作为根据所述采样电流信号生成振荡信号；双向计数器，可操作为根据所述振荡信号进行计数；以及加减法器，可操作为根据来自所述双向计数器的计数结果计算所述数字信号。
根据本公开的第二方面，提供一种便携式超声波检测设备，包括：超声波换能器，可操作为通过检测生成超声信号；根据上述项所述的装置，可操作为根据所述超声信号生成用于超声成像的数字信号；以及显示装置，可操作为根据所述数字信号进行成像。
根据本公开的第三方面，提供一种用于超声成像的方法，包括：利用第一芯片接收超声信号，所述超声信号是模拟信号；利用所述第一芯片生成表示所述超声信号的数字信号；利用不同于所述第一芯片的第二芯片处理来自所述第一芯片所述数字数字信号以用于超声成像。
根据本公开的第四方面，提供一种用于便携式超声波检测设备的成像方法，包括：利用超声波换能器生成超声信号；利用根据上述项所述的装置以根据所述超声信号生成用于超声成像的数字信号；以及根据所述数字信号进行成像。
根据本公开的第五方面，提供一种用于生产超声成像装置的方法，包括：提供根据上述项所述的装置中包含的部件。
可以理解，本部分并不旨在标识本公开的实施例的关键或重要特征，亦非旨在用于限制本公开的范围。本公开的其它特征将通过以下的描述变得容易理解。
附图说明
通过在所附附图中的本公开的一些实施例的更为详细的描述，本公开的以上和其它的优势、特征和目标将变得更为明显，其中：
图1是其中可以实施本公开的一些实施例的环境的简化框图；
图2是示出了根据本公开的一个实施例的用于超声成像的装置的芯片堆叠的立体图；
图3是示出了根据本公开的一个实施例的用于超声成像的装置的框图；
图4是示出了图3中的低噪声放大器的一个示例的电路图；
图5是示出了图3中的模数转换器的一个示例的框图；
图6是示出了图5中的模数转换器的一个示例的详细框图；
图7是示出了图6中所示的余量放大器的一个示例的电路图；
图8是示出了图6中所示的第二级模数转换器的一个示例的框图；以及
图9是示出了根据本公开的一些实施例的方法的流程图。
具体实施方式
现在将参考一些示例实施例描述本公开的原理。可以理解，这些实施例仅出于说明并且帮助本领域的技术人员理解和实施例本公开的目的而描述，而非建议对本公开的范围的任何限制。在此描述的本公开的内容可以以下文描述的方式之外的各种方式实施。
如本文中所述，术语“包括”及其各种变体可以被理解为开放式术语，其意味着“包括但不限于”。术语“基于”可以被理解为“至少部分地基于”。术语“一个实施例”可以被理解为“至少一个实施例”。术语“另一实施例”可以被理解为“至少一个其它实施例”。术语“逻辑”指代诸如用于是时候某些功能的电路装置之类的模块。此外，在本公开的文中，术语“信号流”和“数据流”可以出于方便讨论的目的而交换使用。在下文中包括其它的明显和 暗示的定义。
现有的超声成像设备中的超声信号采集处理装置是超声成像系统中的重要组成部分。超声信号采集处理装置包含多个信号接收通道，超声信号依次通过每个接收通道中的换能器、低噪声放大器(LNA)、可变增益放大器(VGA)、模拟-数字转换器(ADC)、数字波束成形器、数字信号处理(DSP)等电路，输出给显示处理器来实现成像。典型的超声成像系统通常包含32至256个信号接收通道。由于接收通道的数量较多，用分立元件构建这样的超声系统需要大量的单元电路(例如低噪声放大器、可变增益放大器、模数转换器等)，使得整个超声设备体积庞大且价格昂贵，并且产生相当大的功耗。
此外，现有的超声成像设备中的超声信号采集处理芯片通常被实现为包括至少三个芯片(即，增益放大芯片、模拟数字转换芯片和数字信号处理芯片)。增益放大芯片和模拟数字转换芯片均为多用途的通用芯片，而数字信号处理芯片通常使用现场可编程门阵列(FPGA)实现。FPGA具有通用性好、便于开发的优势。此外，现有的超声成像设备中的上述三个芯片也通常设置在同一个基板上的同一平面中，并且通过电接线连接。这样的配置优势在于配置灵活，但是功耗较大。
例如，在一种现有的64通道超声探测器中，模拟前端的每一通道消耗的功率为75毫瓦(mW)，其中LNA和VCA消耗20mW，ADC消耗55mW。对于64个信道而言，整个模拟前端一共消耗功率4.8W。数字信号处理模块中的Xilinx的FPGA消耗功率1.5W。整个方案一共至少消耗功率6.3W。这样的功耗使该方案只适合于电网供电的基站式系统，而不适合便携式的超声探测器。
为了解决目前存在的上述以及其他潜在问题，本公开的一些实施例涉及用于超声成像的装置和方法。在本公开的实施例中，用于超声成像的装置例如在接收到由超声换能器所发送的超声模拟信号之后，装置中的模拟前端芯片对该超声模拟信号进行放大和模数转换，以得到用于超声成像的数字信号。该数字信号继而被传输至被 数字信号处理芯片以进行数字信号处理。最终得到适于在诸如液晶显示器之类的显示装置上显示的图像数据。本公开的实施例通过划分芯片功能、将经划分的功能集成在两个不同芯片中、以及重新设计电路结构，极大地降低超声设备的功耗，并且使得根据本公开的一些实施例的用于超声成像的装置可以适用于便携式超声成像设备。
图1示出了其中可以实施本公开的一些实施例的环境的简化框图。环境100包括超声换能器102、主机104和显示器106。主机104包括用于超声成像的装置和其它一些外围部件。超声换能器102例如可以用于发射超声波来扫描人体，接收回声信号并且将其转换为表示超声信号的模拟电学信号。该模拟电学信号被传输至主机104中的用于超声成像的装置。用于超声成像的装置继而对该模拟电学信号进行处理，例如对其进行放大、滤波、数模转换、数字信号处理(DSP)等，以获得适于在显示器106上显示的图像数据。显示器106例如是液晶显示器(LCD)，其可以在接收到图像数据后显示例如人体组织的图像。
虽然在图1中示出超声换能器102、主机104和显示器106为分离的部件，但是可以理解这些部件可以被集成在一个设备中。图1中所示的配置仅是示例，而非旨在对本公开的范围的限制。可以将这三个部件可选地进行分离和组合而不脱离本公开的范围。
图2示出了根据本公开的一个实施例的用于超声成像的装置的芯片堆叠200的立体图。芯片堆叠200例如可以被包括在图1所示的主机102中，以用于将来自超声换能器102的模拟形式的超声信号进行例如放大、转换和处理。在此示例中，芯片堆叠200被实现为三维(3D)芯片堆叠的形式，其包括第一芯片(模拟前端芯片)202，第二芯片(数字信号处理芯片)206，和封装基板210。封装基板210用于支撑第二芯片206。在封装基板210上具有多个电连接端子(图2中示出为两排端子，可以使用其它布置)。在第二芯片206上具有相应的多个电连接端子208以用于在第二芯片206与外围电 路装置或显示器之间传输信号。第一芯片202通过多个铜柱微凸起(Copper Pillar Micro Bump)或相似技术以实现与第二芯片206的垂直集成。两个芯片之间的大通量高速数据通过微突起(Micro Bump)传输，以大量降低信道电容和功耗。数字信号处理芯片通过引线(Wire Bonding)与封装基板210电连接。该芯片堆叠200随后被封装在单一的装置以供超声成像设备使用。
在上述实施例中，三维封装技术可以极大降低两个芯片之间的信号传输通道的寄生电容，从而有效降低大量高速数据在两个芯片之间传输的功耗。此外，采用三维封装技术可以大量减小整体解决方案的封装面积，从而减小终端产品，例如降低便携式超声探测器的重量和体积。在实现中，基板上的晶片上芯片(Chip on Wafer on Substrate，CoWoS)封装技术以及F2F倒装堆叠(FlipStack)CSP封装技术等技术均可用来将多个芯片垂直集成在一起以降低互连电容以及封装面积。虽然图2示出了基板210-第二芯片206-第一芯片202的一种三维堆叠方式，但是可以使用其它三维堆叠方式。相比于上述的现有超声成像设备，根据本公开的实施例通过将电路重新设计、芯片定制集成和三维堆叠可以极大地降低超声设备的功耗。
参见图3，图3示出了根据本公开的一个实施例的用于超声成像的装置的框图。该装置可以是图1中的主机104中的一部分，并且与图2所示的装置对应。该装置包括第一芯片202和第二芯片206。第一芯片202包括多个通道300，每个通道300包括低噪声放大器(LNA)302、可变增益放大器(VGA)304和模数转换器(ADC)306。低噪声放大器302接收来自超声换能器的微弱超声脉冲反馈电信号，并且将其放大并且将其传输至可变增益放大器304。可变增益放大器304例如是可编程可变增益放大器(PGA)或电压调控可变增益放大器(VCA)。在经过可变增益放大器304进一步放大之后，模拟信号被传输至模数转换器306，经由模数转化器转化成数字信号，供第二芯片206做进一步后期处理。数字信号处理芯片由大量的DSP模块组成，对经模拟前端放大并数字化的超声脉冲反馈信号 进行滤波，均衡和降噪等后期处理，并将处理结果发送到超声探测器的操作系统(OS)和用户界面(UI)供仪器使用者分析判断。
超声换能器接收到的超声脉冲反馈信号强度一般微弱到只有毫伏(mV)量级。如果放大到后续的模数转换器的理想输入电压水平(约为100mV量级)，则放大电路需要提供至少40dB的增益。在一个实施例中，可以在模拟前端芯片的输入端布置低噪声放大电路，以便保证放大电路在放大期望信号的过程中不至于同时引入与放大太多的电路噪声。以此方式，可以避免对模数转换器输入端的信噪比的不利影响。该低噪声放大电路一方面要对输入有用信号提供足够增益，以压制后续电路的噪声，另一方面要保证自己引入尽量少的噪声。为实现上述两方面的设计要求，低噪声放大器的输入器件提供较大的跨导(gm)，这可能导致较大功耗。在现有的常规差分输入低噪声放大电路设计中，通常使用单端电流设计。单端电流设计中仅一个输入器件(例如N型金属氧化物半导体晶体管(NMOS))提供跨导。
参见图4，图4示出了图3中的低噪声放大器的一个示例的电路图。如图4所示，电流复用差分输入低噪声放大电路302包括两个支路，每个支路连接在Vdd和电流源410之间。第一支路包括串联的P型金属氧化物半导体晶体管(PMOS)402和N型金属氧化物半导体晶体管(NMOS)404。第二支路包括串联的PMOS 408和NMOS406。PMOS和NMOS的栅极均与输入电容器耦合以接收差分输入信号，以及PMOS和NMOS的漏极输出所述第一放大信号。在图4所示的实施例中，通过单端电流同时对两个输入器件(NMOS和PMOS)提供跨导，显著降低LNA的功耗。
通过电流复用，该电路实现了在消耗同样电流的情况下，提供了两倍于常规电路的跨导。换言之，采用电流复用的低噪声放大电路，在满足和常规低噪声放大电路同样的噪声性能基础上，能降低一半的电路功耗。由于超声探测器通常需要大量的信号通道(如64个信号通道)，每一通道都需要一个低噪声放大电路，因此减少低 噪声放大电路一半的功耗，将显著减小整个超声探测器的功耗。
如上所述，现有的超声探测器实现方案都采用流水线型模数转换器(Pipeline ADC)来完成模拟信号到数字信号的转换。因此，现有的超声成像设备中的模数转换器在进行模数转换时消耗了较多的功耗，例如每个通道的ADC消耗了50mW。对于64个通道的设备而言，这将一共消耗3.2W。该功率消耗对于以电池供电的便携式超声成像设备显然不能接受。此外，超声探测器的信号采样频率一般在20兆赫兹(MHz)到60MHz之间，模数转换的精度要求达到12比特甚至14比特。这样的高采样频率决定了积分型模数转换器(Integrating ADC)，逐次逼近型模数转换器(SAR ADC)和积分差分型模数转换器(Sigma-Delta ADC)无法满足超声探测器模数转换的速度要求。此外，闪烁型模数转换器(Flash ADC)虽然能够满足采用频率的要求，但是却无法实现大于8比特或以上精度的设计。
为解决上述问题，本发明的实施例提供一种新型的模数转换器，以满足例如便携式超声成像的设备所需。参见图5，图5示出了图3中的模数转换器的一个示例的框图。图5中的模数转换器306是一种工作在电压域与时域的混合结构模数转换器，其包括第一级转换器502、基于压控振荡器的第二级模数转换器504和数字校准电路506。第一级转换器502工作在电压域并且可操作为根据来自可变增益放大器304的第二放大信号生成经转换的第一数字信号和经放大的第一余量模拟信号，其中第一数字信号为表示超声信号的数字比特中的较高位的若干比特，例如前5比特。第二级模数转换器504例如是工作在时域的基于压控振荡器的模数转换器，其可操作为根据第一余量模拟信号生成第二数字信号，其中第二数字信号为表示超声信号的数字比特中的较低位的比特，例如后9比特。可以理解，上述数字比特(5比特和9比特)仅是用于示例而非旨在进行限制，可以使用其它数字比特组合。数字校准电路506可操作为根据第一数字信号和第二数字信号生成经校准的数字信号Dout。
通过使用图5所示的这种双级转换器的配置结构，可以灵活配 置第一级转换器和第二级模数转换器。例如，第二级模数转换器可以使用基于压控振荡器(VCO)的模数转换器。基于压控振荡器的模数转换器可以实现对小信号的高动态范围模数转换。相比于常规电压模式的模数转换器，基于压控振荡器的模数转换器可以消耗更少的功率。这个优点在小尺寸生产工艺(例如65nm生产工艺)中更为显著。
此外，压控振荡器要求的输入电压水平比常规电压模式模数转换器要小很多，使得第一级模数转换的余量不需要经过很大的增益就可以被压控振荡器直接转换。这使得可以降低第一级转换器的要求，例如可以采用功耗更小的运算放大器(Opamp)实现。此外，由于压控振荡器处理的是小输入信号，两级转换器之间不需要留有余量，只要保证对压控振荡器计数的计数器有足够的计数范围，就能对第一级的错误进行校准与更正。这可以进一步降低对第一级转换器的要求。
参见图6，图6示出了图5中的模数转换器的一个示例的更为具体的框图。图6中的ADC包括第一级转换器(以虚线框示出)502、第二级模数转换器504和数字校准电路506。与图5中的框图类似，第一级转换器502输出前5位的数字比特给数字校准电路506，并且第二级模数转换器输出后9位的数字比特给数字校准电路506。数字校准电路506对这两部分的数字比特进行校准和组合，并且输出具有特定位数(例如，13位)的比特组合Dout，而多余的一个比特被用着数字校准的余量。
在图6中，第一级转换器502包括闪烁型模数转换器606、数模转换器608、加减法器604和余量放大器602。闪烁型模数转换器606可操作为根据第二放大信号Vin和第一参考信号Vref生成第一数字信号(如上所述的前5位的数字比特)。如已知的，闪烁型模数转换器不适于大于8比特的转换。然而，这种器件的速度快，并且且电路结构简单，因此可以充当第一级转换。这是因为，在根据本公开实施例的两级转换中，第一级转换通常仅需输出前几位较少的比特 (例如，5比特)。
数模转换器608可操作为根据第一数字信号和第一参考信号Vref生成第一模拟信号。加减法器604继而根据第二放大信号Vin和第一模拟信号计算用于生成后9位数字比特的余量信号。余量信号随后被余量放大器602进行放大以生成第一余量模拟信号。第二级模数转换器504例如是基于压控振荡器的第二级模数转换器，其对于余量信号和输入电压要求较低，如上文所述。例如参见图6，第二级模数转换器504根据第一余量模拟信号和第二参考信号Vref/8来生成后9位的数字比特。如上所述，由于第二级模数转换器使用基于压控振荡器的方案，并且对于输入电压要求较低，因此可以显著降低功率消耗。
如上所述，压控振荡器要求的输入电压水平比常规电压模式模数转换器要小很多，使得第一级模数转换的余量不需要经过很大的增益就可以被压控振荡器直接转换。因此，在本公开的一个实施例中，可以使用一种电压倍增电路来放大余量信号。图7示出了图6中所示的余量放大器的一个示例的电路图。在此实施例中，电压倍增电路602是一个开关电容电路，其通过不同相位开关的通断来实现信号的处理。在图7中，Vin_cm例如为AC的地。在第一相位阶段期间，所有被标注为F1的开关闭合，所有被标注为F2的开关打开，将Vin+和Vin-分别存储于4个采样电容器上。在第二相位阶段期间，所有被标注为F1的开关打开，所有被标注为F2的开关闭合，使Vout-电压变为(Vin--Vin+)，而Vout+电压变为(Vin+-Vin-)，最终差分输出信号为2*(Vin+-Vin-)，实现了对输入差分信号的倍增。图7中所示的电压倍增电路具有结构简单和功耗小的优势，并且经增益放大的余量信号适于作为压控振荡器的输入。
图8是示出了图6中所示的第二级模数转换器的一个示例的框图。第二级模数转换器504包括采样保持电路802，电压到电流转换电路804，流控振荡器806，双向计数器808和加减法器(以虚线框示出)810，其中电压到电流转换电路804和流控振荡器806构成上 文描述的压控振荡器。
采样保持电路802接收来自余量放大器602的第一余量模拟信号，并且根据开关信号fs的控制对第一余量模拟信号采样并且保持在采样电容器上，以生成差分采样电压信号。差分采样电压信号随后被输入至电压到电流转换电路804。电压到电流转换电路804为源极负反馈(Source degenerated)的差分输入电路，其包括耦合至电流源的两个支路，每个支路包括串联的NMOS晶体管和电阻器。NMOS晶体管的栅极耦合至采样保持电路802以接收差分采样电压信号。NMOS的漏极直接或间接地耦合至电压到电流转换器的电流输出端以向流控振荡器806提供采样电流信号。
电流调控振荡器(CCO)806根据采样电流信号生成振荡信号。振荡信号的振荡频率正比于所输入的控制电流，使得两个电流调控振荡器的频率差正比于差分输入的电流信号，并且还正比于差分输入的电压信号。双向计数器808根据振荡信号进行计数。两个电流调控振荡器的振荡频率分别被两个双向计数器记录下来。加减法器810随后根据来自双向计数器808的计数结果计算数字信号。
更具体而言，加减法器810将表示差分输入的电压信号的计数相减，以生成正比于两个电流调控振荡器频率差的计数结果，该计数结果即为正比于输入差分电压的第二数字信号。该数字信号随后由数字校准电路506校准，并且与第一数字信号组合以生成数字信号。该数字信号随后由第二芯片206中的DSP处理以生成供显示器显示的图像数据。
图9示出了根据本公开的一些实施例的方法的流程图。方法900可以例如由图2和图3的装置实施。在步骤902中，利用第一芯片202接收超声信号。第一芯片202上具有与外部部件连接的端子以接收来自超声换能器的表示超声信号的模拟电信号。
在步骤904中，利用所述第一芯片202生成表示超声信号的数字信号。如上所述，第一芯片202中具有多个通道300，每个通道包括LNA 302、VGA 304和ADC 306以用于将表示超声信号的模拟电 信号进行低噪声放大、可变增益放大和模数转换，从而生成表示超声信号的数字信号。通过重新设计的LNA 302和ADC 306，可以极大地降低超声信号放大和转换过程中的功率消耗，使得该方法可以适用于便携式超声设备。
在步骤906中，利用不同于第一芯片202的第二芯片206处理来自第一芯片的数字数字信号以用于超声成像。在本公开的示例中，使用专用集成电路(ASIC)技术制造的第二芯片包括数字信号处理(DSP)单元。相比于传统的超声探测器解决方案多使用现场可编程门阵列(FPGA)芯片来实现超声探测所需要的数字信号处理功能，使用ASIC技术制造的第二芯片可以获得更加优化的电路功耗和面积，并降低芯片的生产成本。第二芯片206对经模拟前端放大并数字化的超声脉冲反馈信号进行滤波，均衡和降噪等后期处理，并将处理结果发送到超声探测器的操作系统(OS)和用户界面(UI)供仪器使用者分析判断。
总体而言，本公开的实施例涉及用于超声成像的装置和方法。该装置和方法因其功耗低、体积小，因此尤其适于便携式超声成像装置。相比于常规的超声成像的装置和方法，本公开的实施例通过将超声设备中部件的功能分解，将其重新设计并且集成在两个单独的芯片中，继而通过3D封装技术集成在一个封装内，以实现功耗和面积的最优化。此外，本公开的实施例通过重新设计模拟前端芯片中的电路，尤其是低噪声放大器和模数转换器，极大地降低了模拟前端所消耗的功率，使得根据本公开的实施例的用于超声成像的装置可以应用至便携式超声成像设备。
虽然本公开的设备被描述为包括单独的部件，但是可以理解这些部件中的至少一部分可以在一些实施例中被整体实施。虽然本公开的各种方面被示出和描述为框图、流程图或使用其它一些绘图表示，但是可以理解本文描述的框、设备、系统、技术或方法可以以非限制性的方式以硬件、软件、固件、专用电路或逻辑、通用硬件或控制器或其它计算设备或其一些组合实施。
此外，虽然操作以特定顺序描述，但是这不应被理解为要求这类操作以所示的顺序执行或是以顺序序列执行，或是要求所有所示的操作被执行以实现期望结果。在一些情形下，多任务或并行处理可以是有利的。类似地，虽然若干具体实现方式的细节在上面的讨论中被包含，但是这些不应被解释为对本公开的范围的任何限制，而是特征的描述仅是针对具体实施例。在分离的一些实施例中描述的某些特征也可以在单个实施例中组合地执行。相反对，在单个实施例中描述的各种特征也可以在多个实施例中分离地实施或是以任何合适的子组合的方式实施。
虽然本公开以具体结构特征和/或方法动作来描述，但是可以理解在所附权利要求书中限定的本公开并不必然限于上述具体特征或动作。而是，上述具体特征和动作仅公开为实施权利要求的示例形式。

Claims (21)

  1. 一种用于超声成像的装置，包括：
    第一芯片，可操作为：
    接收超声信号，所述超声信号是模拟信号；以及
    生成表示所述超声信号的数字信号；以及
    第二芯片，可操作为处理来自所述第一芯片的所述数字信号以用于超声成像。
  2. 根据权利要求1所述的装置，其中所述第一芯片被堆叠在所述第二芯片上以形成三维堆叠芯片封装。
  3. 根据权利要求1所述的装置，其中所述第二芯片包括使用专用集成电路工艺制作的数字信号处理器。
  4. 根据权利要求1所述的装置，其中所述第一芯片包括多个信号通道，每个所述信号通道包括：
    低噪声放大器，可操作为通过放大所述超声信号生成第一放大信号；
    可变增益放大器，可操作为通过放大所述第一放大信号生成第二放大信号；以及
    模数转换器，可操作为将所述第二放大信号转换成所述数字信号。
  5. 根据权利要求4所述的装置，其中所述低噪声放大器包括差分电流复用低噪声放大电路，所述差分电流复用低噪声放大电路包括：
    第一支路，包括串联的P型金属氧化物半导体晶体管和N型金属氧化物半导体晶体管；
    第二支路，包括串联的P型金属氧化物半导体晶体管和N型金属氧化物半导体晶体管；以及
    所述P型金属氧化物半导体晶体管和所述N型金属氧化物半导体晶体管的栅极均与输入电容器耦合以接收差分输入信号，以及所 述P型金属氧化物半导体晶体管和所述N型金属氧化物半导体晶体管的漏极输出所述第一放大信号。
  6. 根据权利要求4所述的装置，其中所述模数转换器包括：
    第一级转换器，可操作为根据所述第二放大信号生成经转换的第一数字信号和经放大的第一余量模拟信号；
    基于压控振荡器的第二级模数转换器，可操作为根据所述第一余量模拟信号生成第二数字信号；以及
    数字校准电路，可操作为根据所述第一数字信号和所述第二数字信号生成经校准的所述数字信号。
  7. 根据权利要求6所述的装置，其中所述第一级转换器包括：
    闪烁型模数转换器，可操作为根据所述第二放大信号和第一参考信号生成所述第一数字信号；
    数模转换器，可操作为根据所述第一数字信号和所述第一参考信号生成第一模拟信号；
    加减法器，可操作为根据所述第二放大信号和所述第一模拟信号生成余量信号；以及
    余量放大器，可操作为根据所述余量信号生成所述第一余量模拟信号。
  8. 根据权利要求7所述的装置，其中所述余量放大器包括基于电荷泵的电压倍增电路，所述电压倍增电路可操作为：
    在第一阶段期间存储成对的所述余量信号；以及
    在第二阶段期间将所述成对的所述余量信号组合地输出为所述第一余量模拟信号。
  9. 根据权利要求6所述的装置，其中所述第二级模数转换器包括：
    采样保持电路，可操作为对所述第一余量模拟信号进行采样和保持以生成采样电压信号；
    电压到电流转换电路，可操作为将所述采样电压信号转换为采样电流信号；
    流控振荡器，可操作为根据所述采样电流信号生成振荡信号；
    双向计数器，可操作为根据所述振荡信号进行计数；以及
    加减法器，可操作为根据来自所述双向计数器的计数结果计算所述第二数字信号。
  10. 一种便携式超声波检测设备，包括：
    超声波换能器，可操作为通过检测生成超声信号；
    根据权利要求1-9中任一项所述的装置，可操作为根据所述超声信号生成用于超声成像的数字信号；以及
    显示装置，可操作为根据所述数字信号进行成像。
  11. 一种用于超声成像的方法，包括：
    利用第一芯片接收超声信号，所述超声信号是模拟信号；
    利用所述第一芯片生成表示所述超声信号的数字信号；
    利用不同于所述第一芯片的第二芯片处理来自所述第一芯片的所述数字数字信号以用于超声成像。
  12. 根据权利要求11所述的方法，所述第一芯片被堆叠在所述第二芯片上以形成三维堆叠芯片封装。
  13. 根据权利要求11所述的方法，其中所述第二芯片包括使用专用集成电路工艺制作的数字信号处理器。
  14. 根据权利要求11所述的方法，其中所述第一芯片包括多个信号通道，每个所述信号通道包括低噪声放大器、可变增益放大器和模数转换器，利用所述第一芯片生成表示所述超声信号的数字信号包括：
    利用低噪声放大器放大所述超声信号生成第一放大信号；
    利用可变增益放大器放大所述第一放大信号生成第二放大信号；以及
    利用模数转换器将所述第二放大信号转换成所述数字信号。
  15. 根据权利要求14所述的方法，其中所述低噪声放大器包括差分电流复用低噪声放大电路，所述差分电流复用低噪声放大电路包括第一支路和第二支路，所述第一支路包括串联的P型金属氧化 物半导体晶体管和N型金属氧化物半导体晶体管，所述第二支路包括串联的P型金属氧化物半导体晶体管和N型金属氧化物半导体晶体管；
    生成所述第一放大信号包括：
    利用所述P型金属氧化物半导体晶体管和所述N型金属氧化物半导体晶体管的栅极接收差分输入信号，以及
    利用所述P型金属氧化物半导体晶体管和所述N型金属氧化物半导体晶体管的漏极输出所述第一放大信号。
  16. 根据权利要求14所述的方法，其中所述模数转换器包括第一级转换器、基于压控振荡器的第二级模数转换器和数字校准电路；
    将所述第二放大信号转换成所述数字信号包括：
    利用所述第一级转换器根据所述第二放大信号生成经转换的第一数字信号和经放大的第一余量模拟信号；
    利用所述第二级模数转换器根据所述第一余量模拟信号生成第二数字信号；以及
    利用所述数字校准电路根据所述第一数字信号和所述第二数字信号生成经校准的所述数字信号。
  17. 根据权利要求16所述的方法，其中所述第一级转换器包括闪烁型模数转换器、数模转换器、加减法器和余量放大器，
    生成所述第一数字信号包括：
    利用所述闪烁型模数转换器根据所述第二放大信号和第一参考信号生成所述第一数字信号；
    生成所述第一余量模拟信号包括：
    利用所述数模转换器根据所述第一数字信号和所述第一参考信号生成第一模拟信号；
    利用所述加减法器根据所述第二放大信号和所述第一模拟信号生成余量信号；以及
    利用所述余量放大器根据所述余量信号生成所述第一余量模拟信号。
  18. 根据权利要求17所述的方法，其中所述余量放大器包括基于电荷泵的电压倍增电路，生成所述第一余量模拟信号包括：
    利用所述电压倍增电路在第一阶段期间存储成对的所述余量信号；以及
    利用所述电压倍增电路在第二阶段期间将所述成对的所述余量信号组合地输出为所述第一余量模拟信号。
  19. 根据权利要求16所述的方法，其中所述第二级模数转换器包括采样保持电路、电压到电流转换电路、流控振荡器、双向计数器和加减法器，生成所述第二数字信号包括：
    利用所述采样保持电路对所述第一余量模拟信号进行采样和保持以生成采样电压信号；
    利用所述电压到电流转换电路将所述采样电压信号转换为采样电流信号；
    利用流控振荡器根据所述采样电流信号生成振荡信号；
    利用双向计数器根据所述振荡信号进行计数；以及
    利用加减法器根据来自所述双向计数器的计数结果计算所述第二数字信号。
  20. 一种用于便携式超声波检测设备的成像方法，包括：
    通过超声波换能生成超声信号；
    利用根据权利要求1-9中任一项所述的装置，基于所述超声信号生成用于超声成像的数字信号；以及
    根据所述数字信号进行成像。
  21. 一种用于生产超声成像装置的方法，包括：提供根据权利要求1-9中任一项所述的装置中包含的部件。
PCT/CN2016/071766 2016-01-22 2016-01-22 超声成像的装置和方法 Ceased WO2017124440A1 (zh)

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