WO2017137092A1

WO2017137092A1 - Submodule of a chain link converter

Info

Publication number: WO2017137092A1
Application number: PCT/EP2016/053026
Authority: WO
Inventors: Christopher Townsend; Alireza NAMI; Munaf Rahimo; Hector Zelaya De La Parra; Francisco Canales; Roberto ALVES; Torsten Nilsson
Original assignee: ABB Schweiz AG
Current assignee: ABB Schweiz AG
Priority date: 2016-02-12
Filing date: 2016-02-12
Publication date: 2017-08-17
Anticipated expiration: 2018-08-12
Also published as: CN108604877A; GB201812425D0; CN108604877B; GB2562420A; GB2562420B; DE112016006420T5

Abstract

The present disclosure relates to a submodule (3) for a chain link converter leg (2). The submodule comprises a first semiconductor structure (4a) forming first current path through the submodule, and a second semiconductor structure (4b), connected in parallel to the first semiconductor structure (4a), forming a second current path through the submodule. At least the first semiconductor structure (4a) comprises a DC capacitor (5), and at least the second semiconductor structure (4b) comprises a reverse-blocking arrangement (8). The submodule is configured for, when in a bypass mode, allow current to pass through the reverse-blocking arrangement.

Description

SUBMODULE OF A CHAIN LINK CONVERTER

TECHNICAL FIELD

The present disclosure relates to a submodule for a chain link converter leg for an electrical converter. BACKGROUND

Multilevel converters are found in many high power applications in which medium to high voltage levels are present in the system. By virtue of their design, multilevel converters share the system voltage, eliminating the need of series connection of devices. In particular, modular converters have become popular, where a number of cells, each containing a number of semiconductor switching elements and an energy storage element in the form of a Direct Current (DC) capacitor, are connected in series to form a variable voltage source. These converters can be used for Drive, High-Voltage Direct Current (HVDC) and Flexible Alternating Current, AC, Transmission Systems (FACTS) applications. Figure 1 depicts a typical three-phase chain-link converter in delta configuration, each phase leg constructed with series connections of full-bridge (also called H-bridge) cells (so called cascaded or chain-link connected cells). Figure 2 depicts a three-phase modular multi-level converter where each phase leg comprises an upper and a lower arm, each arm constructed with a series connections of half-bridges.

Total semiconductor loss is made up of both switching and conduction loss. In high power grid connected converters, the conduction loss is the dominant loss component. Conduction loss typically reduces as the number of semiconductor devices in the current path is reduced.

In FACTS applications, the voltage and current waveforms associated with each phase-leg are 90⁰ out of phase. This implies that when the current waveform is close to its peak, the majority of H-bridge cells are bypassed. If the number of devices in the current path during this time can be reduced then the total conduction loss, and hence total loss, will substantially decrease.

Theoretical modelling of future wide-bandgap semiconductors indicates that converter switching loss can be significantly reduced. However, modelling has also shown substitution of these devices into existing cell and topology designs will not significantly reduce conduction loss, and in many cases substitution actually increases conduction loss. Therefore, a new phase leg structure is required that exploits the benefit of increased switching frequencies to reduce conduction loss. EP 2 413 489 discloses a DC to AC converter circuit, in particular a half- bridge inverter for converting a DC to an AC voltage. The half-bridge inverter for converting a DC input voltage to provide an AC output voltage at an output terminal, comprising a first switching circuit connected to at least one input terminal and to the output terminal and configured to provide a high or a low voltage level at the output terminal. A second switching circuit is connected to the output terminal and configured to provide a connection to an intermediate voltage level, the intermediate voltage level being between the high and the low voltage level. The second switching circuit is further connected to the at least one input terminal allowing the second switching circuit to provide the high or the low voltage level at the output terminal.

The idea of EP 2 413 489 is to use two different semiconductor switches, Insulated-Gate Bipolar Transistor (IGBT) and Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) connected in parallel so that the IGBT conducts steady state current while the MOSFET performs the switching transitions in order to lower overall losses. Thus, the semiconductor silicon area is rather high and only unipolar output voltage is created.

SUMMARY

According to an aspect of the present invention, there is provided a

submodule for a chain link converter leg. The submodule comprises a first semiconductor structure forming a first current path through the submodule, and a second semiconductor structure, connected in parallel to the first semiconductor structure, forming a second current path through the submodule. At least the first semiconductor structure comprises a DC capacitor, and at least the second semiconductor structure comprises a reverse-blocking arrangement. The submodule is configured for, when in a bypass mode, allow current to pass through the reverse-blocking

arrangement.

According to another aspect of the present invention, there is provided a phase leg for a converter, the phase leg comprising a plurality of chain linked submodules of the present disclosure.

It is to be noted that any feature of any of the aspects may be applied to any other aspect, wherever appropriate. Likewise, any advantage of any of the aspects may apply to any of the other aspects. Other objectives, features and advantages of the enclosed embodiments will be apparent from the following detailed disclosure, from the attached dependent claims as well as from the drawings.

Generally, all terms used in the claims are to be interpreted according to their ordinary meaning in the technical field, unless explicitly defined otherwise herein. All references to "a/an/the element, apparatus, component, means, step, etc." are to be interpreted openly as referring to at least one instance of the element, apparatus, component, means, step, etc., unless explicitly stated otherwise. The steps of any method disclosed herein do not have to be performed in the exact order disclosed, unless explicitly stated. The use of "first", "second" etc. for different features/components of the present disclosure are only intended to distinguish the features/components from other similar features/components and not to impart any order or hierarchy to the features/components.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments will be described, by way of example, with reference to the accompanying drawings, in which: Fig l is a schematic illustration of a full-bridge delta connected converter according to prior art.

Fig 2 is a schematic illustration of a half-bridge modular multi-level converter according to prior art. Fig 3 is a schematic circuit diagram of a converter phase leg of embodiments of the present invention.

Fig 4 is a schematic circuit diagram of an embodiment of a submodule of the present invention.

Fig 5 is a schematic circuit diagram of another embodiment of a submodule of the present invention.

Fig 6 is a schematic circuit diagram of another embodiment of a submodule of the present invention.

Fig 7 is a schematic circuit diagram of another embodiment of a submodule of the present invention. DETAILED DESCRIPTION

Embodiments will now be described more fully hereinafter with reference to the accompanying drawings, in which certain embodiments are shown.

However, other embodiments in many different forms are possible within the scope of the present disclosure. Rather, the following embodiments are provided by way of example so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Like numbers refer to like elements throughout the description.

In the discussion herein, as an alternative to the three-quadrant device of IGBT and antiparallel diode, any other three-quadrant device may be used. Similarly, as an alternative to the four quadrant device of RBIGBT, any other four quadrant device may be used. It may also be mentioned that these devices may be wideband devices whereby the switching losses may be reduced. The proposed invention reduces conduction loss using a new submodule structure within a chain link converter. The proposed submodule and resulting phase leg are shown in figures 4 and 3, respectively.

Figure 3 illustrates part of a phase leg 2 of a converter 1. The phase leg 2 comprises a plurality of series connected (chain link), typically identical, submodules 3, which submodules are discussed in more detail with reference to figure 4.

Figure 4 illustrates an embodiment of a submodule 3 of the present invention. The submodule 3 comprises a first semiconductor structure 4a and a second semiconductor structure 4b. The first and second semiconductor structures 4 are connected in parallel to each other in the submodule 3. In accordance with the present invention, the first semiconductor structure 4a comprises a DC capacitor 5 as an energy storage unit, and the second semiconductor structure 4b comprises a reverse-blocking arrangement 8. In the embodiment of figure 4, the reverse-blocking arrangement is formed by two antiparallel Reverse Blocking IGBTs (RBIGBT), i.e. the two RBIGBTs are connected in parallel but arranged for allowing current in opposite directions in the reverse-blocking arrangement 8. Alternatively, each of the antiparallel RBIGBTs may be exchanged for a MOSFET with a series connected diode. In the example embodiment of figure 4, the first semiconductor structure 4a comprises a half-bridge cell with a DC capacitor 5 in parallel with a leg of an upper semiconductor switch and a first lower semiconductor switch.

Similarly, the second semiconductor structure 4b comprises a half-bridge cell with a DC capacitor 5 in parallel with a leg of an upper semiconductor switch and a second lower semiconductor switch. The half-bridge of the first semiconductor structure 4a is antiparallel to the half-bridge of the second semiconductor structure 4b (i.e. they form two opposite polarity half-bridges connected in parallel). The first semiconductor structure 4a forms a first current path through the submodule and is used to synthesize positive voltage, and the second semiconductor structure 4b forms a second current path through the submodule and is used to synthesize negative voltage. When the submodule 3 is bypassed each of the first and second lower

semiconductor switches (e.g. RBIGBTs) in each half-bridge is turned on to conduct half the current passed the submodule.

Alternatively, the first semiconductor structure 4a comprises a half-bridge cell with a DC capacitor 5 in parallel with a leg of an upper semiconductor switch and said second lower semiconductor switch. Consequently, the same lower semiconductor switch is shared between both the first 4a and second 4b semiconductor structures (not shown in figure 4).

The upper semiconductor switch in each half bridge, typically an IGBT 6 with antiparallel diode 7 (with opposite polarities in the two different half- bridges), is according to this topology capable of blocking 2.0 Udc. Each of the two reverse-blocking arrangements 8 is capable of blocking 1.0 Udc in both directions, hence the inclusion of the RBIGBTs.

The following will consider the current path and resulting conduction loss for each possible output voltage and current direction of the topology in figures 3 and 4. Note that positive current is defined as flowing from top to bottom in the figures.

+ve voltage, +ve current - current flows through one diode 7 rated at 2.0 Udc

+ve voltage, -ve current - current flows through one IGBT 6 rated at 2.0 Udc -ve voltage, -ve current - current flows through one diode 7 rated at 2.0 Udc

-ve voltage, +ve current - current flows through one IGBT 6 rated at 2.0 Udc bypass, +ve current - half the current flows through one RBIGBT (of the first semiconductor structure 4a) rated at 1.0 Udc, while the other half of the current flows through another RBIGBT (of the second semiconductor structure 4b) rated at 1.0 Udc. bypass, -ve current - half the current flows through one RBIGBT (of the first semiconductor structure 4a) rated at 1.0 Udc, while the other half of the current flows through another RBIGBT (of the second semiconductor structure 4b) rated at 1.0 Udc.

During the bypass mode, in the embodiment with two lower switches, both lower switches (the reverse-blocking arrangement 8 in each half bridge) is turned on to share current between the two parallel connected reverse- blocking arrangements. This reduces the silicon area required for these switches since their peak current is up to 50% lower than the phase-leg current.

As discussed herein, each RBIGBT in the lower switch position of each half bridge could alternatively be implemented with a series connection of

MOSFET and diode. This would allow increasing the area of the MOSFET to decrease the on-state resistance, resulting in the only significant conduction loss coming from the series connected diode. Thus, in some embodiments, the reverse blocking arrangement comprises two antiparallel RBIGBTs.

Alternatively, in some embodiments, the reverse blocking arrangement comprises two antiparallel sets of a MOSFET in series with a diode.

Use of RBIGBTs allows an up to 50% reduction in the number of

semiconductor switches in the current path during times when the current is at its peak value (during times when most submodules are in bypass mode). The total decrease in semiconductor loss which the proposed topology provides is dependent on the semiconductor technology and the on state voltage drop of the RBIGBTs. Each RBIGBT will have a lower on state voltage drop than a series connected IGBT and antiparallel diode. However the structure of the RBIGBT gives a higher on-state voltage drop than the equivalently optimised IGBT structure, typically by 30-40%. Given the above observations, the proposed submodule 3 of figure 4 could theoretically reduce converter conduction loss by approximately 30% in e.g. FACTS applications.

In some embodiments of the present invention, in accordance with figure 4, the first semiconductor structure 4a comprises a first half-bridge cell and the second semiconductor structure 4b comprises a second half-bridge cell which is antiparallel to the first half-bridge cell. In some embodiments, each of the first and second half-bridge cells comprises a DC capacitor 5 and a reverse- blocking arrangement 8. In some embodiments, the submodule 3 is configured for, when in the bypass mode, allow current to pass through both the reverse-blocking arrangements 8 of the first and second half-bridge cells. In some embodiments, only the second half-bridge cell 4b comprises a reverse-blocking arrangement 8. The reverse-blocking arrangement 8 is then shared between the first and second half-bridge cells.

Figures 5-7 discloses embodiments of the inventive submodule with full- bridge cells 9, which are alternative embodiments to the embodiment of figure 4, while the inventive concept is the same with a reverse-blocking arrangement 8 in the second semiconductor structure 4b.

An advantage with a full-bridge topology is that it is possible to design the commutation process such that the RBIGBTs do not incur switching loss, meaning their design can be optimized for conduction loss only.

Figure 5 shows an embodiment where the RBIGBTs are external to and connected in series with a full-bridge cell 9 in the second semiconductor structure 4b. The first semiconductor structure 4a comprises two full-bridge cells 9 in series, where each full-bridge cell comprises a DC capacitor 5 and two parallel legs, each with an upper and a lower semiconductor switch

(again, typically an IGBT 6 with antiparallel diode 7). Here, all switches are required to block 1.0 Udc.

As illustrated in figure 6, it is possible to move the RBIGBTs inside the full- bridge cell 9 of the second semiconductor structure 4b. Thus, each of the four switches (e.g. IGBT 6 with antiparallel diode 7) may be exchanged for antiparallel RBIGBTs in the full-bridge 9. However, this may not provide significant conduction loss reduction since the RBIGBTs must then each be rated to block 1.5 Udc.

As illustrated in figure 7, the full-bridge in the second semiconductor structure 4b may be removed, leaving only the reverse-blocking arrangement, here in the form of two sets of antiparallel RBIGBT pairs in series. To use two series connected reverse-blocking arrangements 8 may be preferred since it is proportional to the reverse blocking voltage and the total main loop voltage. It is the same number as the number of cells if the reverse blocking voltage of the RBIGBTs is the same as the blocking voltage of the IGBTS. The structure of figure 7, with a single or two series connected reverse-blocking

arrangements 8, may be the preferred full-bridge option in terms of minimising silicon area because the number of semiconductor switches is significantly reduced. However, with this topology, there is no possibility to create voltage from the current path of the second semiconductor structure 4b, implying that on average a higher number of submodules may need to be switched to utilize the current path of the first semiconductor structure 4a, which may increase conduction loss.

Thus, in some embodiments of the present invention, the first semiconductor structure 4a comprises at least one full-bridge cell. In some embodiments, the first semiconductor structure 4a comprises two series connected full- bridge cells (as in the embodiments of figures 5-7). Additionally or

alternatively, the second semiconductor structure 4b comprises a full-bridge cell (as in the embodiments of figures 5 or 6). In some embodiments, the reverse-blocking arrangement 8 is connected in series with the full-bridge cell in the second semiconductor structure 4b (as in the embodiment of figure 5). Alternatively, in some embodiments, the full-bridge cell comprises four reverse-blocking arrangements 8 (as in the embodiment of figure 6).

Additionally or alternatively, in some embodiments, the second

semiconductor structure 4b comprises two series connected reverse-blocking arrangements 8 (as in the embodiment of figure 7). The embodiment of figure 7 also represents that in some embodiments, the second

semiconductor structure 4b does not comprise neither a half-bridge nor a full-bridge cell, but only one, or a plurality of series connected, reverse- blocking arrangement(s) 8.

It is noted that the embodiments of the present invention represented by figures 3 and 4 differ structurally from the embodiments represented by figures 5-7, but the function is similar. The concept is the same either for a bypass or auxiliary bypass which contains the least number of devices in the conduction path.

Example - Commutation process The submodule embodiment of figure 4 does not require a specially designed commutation process to transition between switching states inside the submodule. This is due to the anti-parallel diode in the upper switch of each half-bridge which ensures a path for current to flow even when all IGBTs 6 and RBIGBTs are blocked. This means that a simple dead-time mechanism may be used during transitions. However, this is not the case for the full- bridge embodiments of figures 5-7, the commutation process of which will now be discussed with reference to figure 7.

During the previous control cycle, it is assumed current is flowing through the two series connected full-bridges of the first semiconductor structure 4a, and any parasitic inductance. In the next control cycle, the current will flow through the RBIGBTs of the second semiconductor structure 4b. The commutation process comprises the following steps:

1) The process begins at the completion of the previous control cycle. At this time, the current is flowing through the two series connected full-bridges of the first semiconductor structure 4a (the full-bridge cells 9 being controlled by the outer modulation scheme), while the RBIGBTs of the second semiconductor structure 4b are blocked.

2) At the beginning of the next control cycle, both the full-bridge cells 9 and the RBIGBTs are blocked. 3) Once both the first and the second current paths are blocked, the loop voltage is not capable of generating a loop current, and therefore the

RBIGBTs can be bypassed, i.e. turned on or opened. This causes the current to commutate between paths from the first current path of the first semiconductor structure 4a to the second current path (via the RBIGBTs) of the second semiconductor structure 4b.

Similarly, the process for current commutation in the opposite direction comprises the following steps: 1) The process again begins at the completion of the previous control cycle as in step 3) above.

2) At the beginning of the next control cycle the full-bridge cells 9 of the first semiconductor structure 4a are bypassed (thus activating/opening the two upper switches in the upper full-bridge 9 and the two lower switches in the lower full-bridge in figure 7).

3) The RBIGBTs are now blocked, causing the current to commutate to the first current path of the first semiconductor structure 4a. Note that the RBIGBTs may require a snubber to protect from overvoltage caused by any parasitic inductance during this transition. Snubbers will be less likely to be needed in the embodiment shown in Figure 5 due to the full-bridge cell 9 of the second semiconductor structure 4b which, when blocked, may drive the current to zero before the RBIGBTs are blocked.

4) Once the RBIGBTs have been blocked, normal operation can resume with the full-bridge cells 9 of the first semiconductor structure 4a being controlled by the outer modulation scheme.

Due to the commutation processes described above, at times when devices in the IGBT cells are blocking 1.0 Udc there are no switching transients on the RBIGBTs. This means there is no need to choose a device with higher reverse blocking voltage due to the issue of induced voltage from loop inductance. This could be important for wide-bandgap devices with fast switching speeds.

The present disclosure has mainly been described above with reference to a few embodiments. However, as is readily appreciated by a person skilled in the art, other embodiments than the ones disclosed above are equally possible within the scope of the present disclosure, as defined by the appended claims.

Claims

1. A submodule (3) for a chain link converter leg (2), the submodule comprising: a first semiconductor structure (4a) forming a first current path through the submodule; and a second semiconductor structure (4b), connected in parallel to the first semiconductor structure (4a), forming a second current path through the submodule; wherein at least the first semiconductor structure (4a) comprises a DC capacitor (5), and at least the second semiconductor structure (4b) comprises a reverse-blocking arrangement (8); wherein the submodule is configured for, when in a bypass mode, allow current to pass through the reverse-blocking arrangement.

2. The submodule of claim 1, wherein the reverse blocking arrangement comprises two antiparallel Reverse Blocking IGBTs, RBIGBTs.

3. The submodule of claim 1, wherein the reverse blocking arrangement comprises two antiparallel sets of a MOSFET in series with a diode.

4. The submodule of any preceding claim, wherein the first semiconductor structure (4a) comprises a first half-bridge cell and the second semiconductor structure (4b) comprises a second half-bridge cell which is antiparallel to the first half-bridge cell.

5. The submodule of claim 4, wherein each of the first and second half- bridge cells comprises a DC capacitor (5) and a reverse-blocking arrangement (8).

6. The submodule of claim 5, configured for, when in the bypass mode, allow current to pass through both the reverse-blocking arrangements (8) of the first and second half-bridge cells.

7. The submodule of any claim 1-3, wherein the first semiconductor structure (4a) comprises at least one full-bridge cell.

8. The submodule of claim 7, wherein the first semiconductor structure (4a) comprises two series connected full-bridge cells.

9. The submodule of claim 7 or 8, wherein the second semiconductor structure (4b) comprises a full-bridge cell.

10. The submodule of claim 9, wherein the reverse-blocking arrangement (8) is connected in series with the full-bridge cell in the second

semiconductor structure (4b).

11. The submodule of claim 9, wherein the full-bridge cell comprises four reverse-blocking arrangements (8).

12. The submodule of claim 7 or 8, wherein the second semiconductor structure (4b) comprises two series connected reverse-blocking arrangements (8).

13. A phase leg (2) for a converter (1), the phase leg comprising a plurality of chain linked submodules of any claim 1-12.