WO2017152355A1 - 一种显示方法及终端设备 - Google Patents

一种显示方法及终端设备 Download PDF

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Publication number
WO2017152355A1
WO2017152355A1 PCT/CN2016/075846 CN2016075846W WO2017152355A1 WO 2017152355 A1 WO2017152355 A1 WO 2017152355A1 CN 2016075846 W CN2016075846 W CN 2016075846W WO 2017152355 A1 WO2017152355 A1 WO 2017152355A1
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Prior art keywords
start time
vsync
duration
time
processing
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
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PCT/CN2016/075846
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English (en)
French (fr)
Inventor
赵京
于波
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Publication date
Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Priority to KR1020187028704A priority Critical patent/KR102137647B1/ko
Priority to PCT/CN2016/075846 priority patent/WO2017152355A1/zh
Priority to US16/083,027 priority patent/US10614772B2/en
Priority to JP2018547469A priority patent/JP6598408B2/ja
Priority to CN201680024976.XA priority patent/CN107533450B/zh
Priority to EP16893007.1A priority patent/EP3418879A4/en
Publication of WO2017152355A1 publication Critical patent/WO2017152355A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Definitions

  • the present application relates to the field of display systems, and in particular, to a display method and a terminal device.
  • the display panel included in the display system can be configured by using a liquid crystal display (LCD) or an organic light-emitting diode (OLED).
  • LCD liquid crystal display
  • OLED organic light-emitting diode
  • the display system In order to ensure smooth display of the terminal device and avoid frame loss or frame skipping, the display system usually adopts Vertical Synchronization (Vsync) technology.
  • Vsync Vertical Synchronization
  • the basic principle of the Vsync technology is: the display system generates a time every set time. The control signal is triggered by the Vsync period, which is the value of the Vsync period, for example, 16 milliseconds (ms).
  • the display system When triggered by a Vsync cycle, the display system begins to process the following three processes in parallel: application drawing, surfaceflinger synthesis, device display, wherein the raw data that needs to be synthesized in the surfaceflinger synthesis process is applied in the last Vsync cycle.
  • the drawing result of the drawing process, and the data that needs to be displayed in the device display process is the synthesized result after the surfaceflinger synthesis process in the last Vsync cycle.
  • the embodiment of the present application provides a display method and a terminal device, which are used to solve the end in the prior art.
  • the display system of the end device processes three processes in parallel during the Vsync cycle, causing a problem that the CPU power consumption of the terminal device is large.
  • an embodiment of the present application provides a display method, where the method is applicable to a display system of a terminal device, where the display system performs a device display process, an application drawing process, and a layer surfaceflinger in each Vsync cycle.
  • a synthesis process the method comprising the steps of:
  • the display system acquires a first processing duration of the first process performed by the display system in the Mth Vsync period, where the first process is an application drawing process or a surfaceflinger synthesis process, and the M is greater than or equal to 1. Integer
  • the display system starts to execute the display process at a start time of the device display process; the display system starts executing at the start time of the first process
  • the first process is described.
  • the display system delays execution of any one of the application drawing process and the surfaceflinger synthesis process, and reduces the display system of the terminal device in the first
  • the time of three processes is processed in parallel in M+1 Vsync cycles, and the power consumption of the CPU of the terminal device is reduced.
  • the start time of the device display flow in the M+1th Vsync period is the start time of the M+1 Vsync periods.
  • the display system determines, according to the first processing duration, a start time of the first process in the M+1th Vsync period, including:
  • the display system acquires a second processing duration of the display system to execute the device display process in the Mth Vsync period;
  • the display system Determining, according to the first processing duration and the second processing duration, the display system The start time of the first process in the M+1 Vsync cycles, the start time of the first process is equal to or after the first time, the first time is the distance from the device And displaying, at the time when the start time of the process passes the second processing duration, and the offset time of the start time of the first process from the start time of the M+1th Vsync cycle, and the first process The sum of the durations is less than or equal to the duration of the M+1th Vsync period.
  • the display system sets a start time of the first process in the M+1th Vsync period to be equal to the first time or after the first time, that is, in the display system. Performing the first process when or after the device display process is executed in the M+1th Vsync period, so that the display system can be guaranteed to serially execute the device display process and the first process. It is ensured that the display system does not process three processes in parallel in one Vsync cycle, further reducing the power consumption of the CPU of the terminal device.
  • the display system acquires a third processing duration of the second process performed by the display system in the Mth Vsync period, where the second process is in the application drawing process and the surfaceflinger synthesis process.
  • the display system starts executing the second process at a start time of the second process.
  • the display system also offsets the start time of the second flow in the M+1th Vsync period, so that the second flow is also delayed, and the display may be reduced.
  • the system processes the time of three processes in parallel, which reduces the power consumption of the CPU of the terminal device.
  • the start time of the first process in the M+1th Vsync period determined by the display system is different from the start time of the second process, so that not only To reduce the time during which the display system processes three processes in parallel in the M+1th Vsync period, it is also possible to reduce the display system to process the first process and the parallel process in the M+1th Vsync period.
  • the time of the second process further reduces the power consumption of the CPU of the terminal device.
  • the display system determines, according to the third processing duration, a start time of the second process in the M+1 Vsync cycles, including:
  • the display system acquires a second processing duration of the display system to execute the device display process in the Mth Vsync period;
  • the display system sets a start time of the second flow in the M+1th Vsync period to be equal to or after the second time, that is, in the display system. Performing the second process when or after the device display process is executed in the M+1th Vsync period, so that the display system can be guaranteed to serially execute the device display process and the second process. It is ensured that the display system does not process three processes in parallel in one Vsync cycle, further reducing the power consumption of the CPU of the terminal device.
  • the sum of the first processing duration, the second processing duration, and the third processing duration determined by the display system is less than or equal to the M+1th Vsync period
  • the duration between the start time of the first process and the start time of the second process is greater than or equal to the first processing duration or the third processing duration.
  • the duration between the start time of the first flow and the start time of the second flow in the M+1th Vsync period is greater than or equal to the first processing duration or the third processing
  • the duration is such that the display system performs three processes in series during the M+1th Vsync period, thereby minimizing the power consumption of the CPU of the terminal device.
  • the sum of the offset time of the start time of the first flow from the start time of the M+1th Vsync cycle and the first processing time is less than or equal to the Mth The difference between the duration of the +1 Vsync period and the first preset duration.
  • the required processing duration of the first process is greater than the first processing duration in the M+1th Vsync period, as long as the display system is actually in the M+1th Vsync
  • the duration of the required processing time of the first process minus the first processing duration is less than the first preset duration, and the display system may still end at the M+1th Vsync period. Executing the first flow before the end reduces the probability of occurrence of hysteresis in the display screen of the display system.
  • the sum of the offset time of the start of the second flow from the start time of the M+1th Vsync period and the third processing duration is less than or equal to the Mth The difference between the duration of +1 Vsync cycles and the second preset duration.
  • the required processing duration of the second flow is greater than the third processing duration in the M+1th Vsync period, as long as the display system is actually in the M+1th
  • the duration of the required processing time of the second process in the Vsync period minus the third processing duration is less than the second preset duration, and the display system can still be in the M+1th Vsync period.
  • Exceeding the execution of the second flow before the end the probability of occurrence of hysteresis on the display screen of the display system is reduced.
  • the display system is based on the above method, starting from the M+1th Vsync period, up to the first flow in each of the M+P-1 Vsync cycles After the start time is set to the start time of the device display flow of the corresponding Vsync cycle, that is, the start time of the first process is offset, and the display system sets the M+P Vsync cycle
  • the starting time of the first process is the starting time of the M+P Vsync periods
  • the start time of the process is set to the start time of the device display flow of the corresponding Vsync cycle, the start time of the first process is offset, and the first time in the M+11 Vsync cycle is performed.
  • the start time of the process is set to the start time of the M+11th Vsync cycle, and every 10 Vsync cycles thereafter, that is, the start time of the first process in the next Vsync cycle is set to the corresponding moment.
  • the starting time of the Vsync cycle is set to the start time of the device display flow of the corresponding Vsync cycle.
  • the display system offsets the start time of the first process in a plurality of consecutive Vsync cycles, and reduces the time during which the display system processes three processes in parallel in multiple Vsync cycles, and reduces the terminal device in The power consumption of the CPU during the entire display process.
  • the start time of the first flow of the P-1 Vsync cycles is continuously offset, the start time of the first flow in the M+P Vsync cycles is set to the first The starting time of the M+P Vsync periods can reduce the probability of occurrence of delayed display and frame dropping on the display screen of the display system.
  • the display system is based on the above method, starting from the M+1th Vsync period, up to the second flow in each of the M+Q-1 Vsync cycles After the start time is set to the start time of the device display flow of the corresponding Vsync cycle, that is, the start time of the second process is offset, and the display system sets the M+Q Vsync cycle
  • the starting time of the second process is the starting time of the M+Qth Vsync period, and the Q is a preset positive integer greater than 1.
  • the display system starts from the M+1th Vsync period and lasts for 20 Vsync periods, and the start time of the second flow in each Vsync period is set to the corresponding Vsync period.
  • the start time of the second process is offset, and the start time of the second process in the M+21 Vsync cycle is set to the M+th
  • the start time of the 21 Vsync cycles, followed by every 20 Vsync cycles, that is, the start time of the second flow in the next Vsync cycle is set as the start time of the corresponding Vsync cycle.
  • the display system offsets the start time of the first process in a plurality of consecutive Vsync cycles, and reduces the time during which the display system processes three processes in parallel in multiple Vsync cycles, and reduces the terminal device in The power consumption of the CPU during the entire display process.
  • the said M+Q Vsync cycles The start time of the second process is set to the start time of the M+Qth Vsync period, and the probability of occurrence of delayed display and frame loss on the display screen of the display system can be reduced.
  • the embodiment of the present invention provides a terminal device, where the terminal device has the function of implementing the behavior of the terminal device in the foregoing method, and the function may be implemented by using hardware or by executing corresponding software through hardware.
  • the hardware or software includes one or more modules corresponding to the functions described above.
  • the structure of the terminal device includes an acquisition unit, a processing unit, and an operation unit, and the units may perform corresponding functions in the above method examples.
  • the units may perform corresponding functions in the above method examples.
  • the structure of the terminal device includes a processor, a bus, a memory, and a display panel, and the processor, the memory, and the display panel are connected by using the bus, the processor Calling instructions in the memory to perform functions in the method design described above, the display panel, after the processor executes the device display flow in each Vsync cycle, displaying the processor to execute the device Displays the image generated by the process.
  • the display system of the terminal device acquires the first processing duration of the first process in the Mth Vsync period, determining the first in the M+1 Vsync period according to the first processing duration a start time of a process, where the first process is an application drawing process or a surfaceflinger synthesis process, and a start time of the first process in the M+1th Vsync cycle is after a start time of the device display process, And the sum of the offset time of the first time from the start time of the M+1th Vsync period and the first processing duration is less than or equal to the M+1th Vsync period.
  • the display system begins to execute the device display process at a start time of the device display flow, and starts executing at a start time of the first process The first process is described.
  • the display system delays execution of any one of the application drawing process and the surfaceflinger synthesis process, and reduces the display system of the terminal device in the M+
  • the processing time of three processes is paralleled in one Vsync cycle, and the power consumption of the CPU of the terminal device is reduced.
  • FIG. 1 is a schematic structural diagram of a display system according to an embodiment of the present invention.
  • FIG. 2 is a schematic flowchart of displaying a frame image according to an embodiment of the present invention
  • FIG. 3 is a schematic flow chart of displaying an image provided by the prior art
  • FIG. 4 is a schematic structural diagram of a terminal device according to an embodiment of the present disclosure.
  • FIG. 5 is a flowchart of a display method according to an embodiment of the present invention.
  • FIG. 6 is a flowchart of a display example according to an embodiment of the present invention.
  • FIG. 6B is a flowchart of a display example according to an embodiment of the present invention.
  • FIG. 7 is a flowchart of a display example according to an embodiment of the present invention.
  • FIG. 7B is a flowchart of a display example according to an embodiment of the present invention.
  • FIG. 8 is a flowchart of a display example according to an embodiment of the present invention.
  • FIG. 9 is a flowchart of a display example according to an embodiment of the present invention.
  • FIG. 10 is a flowchart of a display example according to an embodiment of the present invention.
  • FIG. 10B is a flowchart of a display example according to an embodiment of the present disclosure.
  • FIG. 11 is a schematic diagram of a display process of a frame dropping phenomenon according to an embodiment of the present disclosure.
  • FIG. 12 is a schematic diagram showing a display process of a delay display phenomenon according to an embodiment of the present invention.
  • FIG. 13 is a schematic diagram of a CPU frequency simulation of a terminal device according to an embodiment of the present invention.
  • FIG. 14 is a schematic structural diagram of a terminal device according to an embodiment of the present disclosure.
  • FIG. 15 is a schematic structural diagram of a terminal device according to an embodiment of the present invention.
  • the embodiment of the invention provides a display method and a terminal device, which are used to solve the problem that the display system of the terminal device in the prior art processes the three processes in the Vsync cycle in parallel, resulting in a large power consumption of the CPU of the terminal device.
  • the method and the device are based on the same inventive concept. Since the principles of the method and the device for solving the problem are similar, the implementation of the device and the method can be referred to each other, and the repeated description is not repeated.
  • the "terminal device” involved in the present invention is a device that has a built-in display system and can realize a human-computer interaction function, and the terminal device can be a computer, a mobile phone, a tablet computer, a point of sales (POS), or a vehicle-mounted computer.
  • POS point of sales
  • a mobile phone is taken as an example.
  • the display system is built in the terminal device and is used for presenting the interface UI, realizing human-computer interaction, processing the image, and displaying the display panel in the display system, wherein the display panel can be configured in the form of LCD or OLED. .
  • a layer composed of many pixels, is the basic unit that makes up an image.
  • a frame of image can be a layer, and it is also composed of multiple layers stacked up and down.
  • a layer is like a film containing elements such as text or graphics. The sheets are stacked one on another and combined to form the final result of the image.
  • the frame rate is usually the number of frames in which the image is displayed in 1 second. In the embodiment of the present invention, the frame rate is 1 second/Vsync period.
  • a display method provided by the embodiment of the present invention is applicable to the display system architecture shown in FIG. 1.
  • the control module 101, the application drawing module 102, and the surfaceflinger synthesis module 103, the memory 104, and the device are included.
  • the control module 101 sends a control signal to the application drawing module 102, the surfaceflinger synthesis module 103, and the device display module 105 in the display system to implement control of the above module, so that the application is painted.
  • the graph module 102, the surfaceflinger synthesis module 103, and the device display module 105 process image data;
  • the application drawing module 102 After receiving the control signal of the control module 101, the application drawing module 102 acquires to-be-displayed layer data of multiple applications (such as application 1 to application n) that the terminal device needs to display, and obtains according to the acquisition.
  • the plurality of layers to be displayed are subjected to a drawing process, a plurality of layers are generated, and the generated plurality of layers are sent to the memory 104;
  • the surfaceflinger synthesis module 103 After receiving the control signal of the control module 101, the surfaceflinger synthesis module 103 acquires the multiple layers from the memory 104, performs layer synthesis, generates a final image of a frame, and generates the generated image. The image is sent to the memory 104, wherein the surfaceflinger synthesis module 103 further includes a Hardware Compose (HWC) process in performing layer synthesis;
  • HWC Hardware Compose
  • the memory 104 is generally a buffer, stores a plurality of layers generated by the application drawing module 102, and stores an image generated by the surfaceflinger synthesis module 103;
  • the device display module 105 after receiving the control signal of the control module 101, acquire the image in the memory 104, and push the image to the display panel 106;
  • the display panel 106 is configured to directly display the image sent by the device display module 105.
  • the clock module 107 is configured to collect a clock signal to the control module 101 every predetermined duration (Vsync period), notify the control module 101 to trigger a Vsync cycle, generate a control signal, and generate a control signal. At the same time, it is sent to the application drawing module 102, the surfaceflinger synthesis module 103, and the device display module 105 to notify each module to execute the corresponding process.
  • Applying a drawing process acquiring a plurality of to-be-displayed layer data of a plurality of applications to be displayed, performing drawing processing on the plurality of to-be-displayed layer data, and generating a plurality of layers;
  • Surfaceflinger synthesis process performing surfaceflinger processing on multiple layers generated in the application drawing process, and HWC processing to generate a frame to be displayed;
  • Device display flow the image to be displayed generated by the above Surfaceflinger synthesis process
  • a device display process is performed to push the image to be displayed to the display panel.
  • the display system can execute an application drawing process, a surfaceflinger synthesis process, and a device display process in one Vsync cycle.
  • the display of one frame of image requires the above three processes, so one frame of image requires three Vsync cycles to display.
  • the display system processes the following three processes in parallel in each Vsync cycle: an application drawing process, a surfaceflinger synthesis process, and a device display process, wherein the raw data that needs to be synthesized in the surfaceflinger synthesis process is the last Vsync.
  • the three processes are simultaneously started, wherein the data of the first frame image is processed in the device display flow, and when the process is completed, the first frame image is displayed in the display panel; Processing the data of the second frame image in the surfaceflinger synthesis process; processing the data of the third frame image in the application drawing process;
  • the three processes are simultaneously started, and the data of the second frame image is processed in the device display flow, and when the processing is completed, the second frame image is displayed on the display panel;
  • the surfaceflinger process processes the data of the image of the third frame; and applies the data of the image of the fourth frame in the drawing process;
  • the three processes are simultaneously started, and the data of the third frame image is processed in the device display flow, and when the processing is completed, the third frame image is displayed in the display panel;
  • the surfaceflinger process processes the data of the image of the fourth frame; and applies the data of the image of the fifth frame in the drawing process;
  • the three processes are simultaneously started, and the data of the fourth frame image is processed in the device display flow, and when the processing is completed, the fourth frame image is displayed in the display panel;
  • the surfaceflinger process processes the data of the 5th frame image; the data of the 6th frame image is processed in the drawing flow.
  • the display panel usually displays the time of one frame of image, usually from the end of a Vsync cycle device display process to the end of the next Vsync cycle device display process, and the total duration is almost the same as the length of the Vsync cycle.
  • the display method in the embodiment of the present invention is applicable to a display device provided by the embodiment of the present invention, and is applicable to a display device that includes a display system and supports a Vsync technology, such as a computer, a mobile phone, a POS, or the like.
  • the next Vsync period is determined according to the first processing duration (the M+1th Vsync period)
  • the first process of the first process is the application drawing process or the surfaceflinger synthesis process, and the start time of the first process in the M+1th Vsync cycle is located in the device display process
  • the display system begins to execute the device display process at a start time of the device display process, and in the first process The first process begins at the beginning.
  • the display system delays execution of any one of the application drawing process and the surfaceflinger synthesis process, and reduces the display system of the terminal device in the M+
  • the processing time of three processes is paralleled in one Vsync cycle, and the power consumption of the CPU of the terminal device is reduced.
  • the embodiment of the present invention provides a display method and a terminal device, which are applicable to a terminal device, and the terminal device according to the embodiment of the present invention may be a computer, a mobile phone, a tablet computer, or a personal digital assistant (PDA). Point of Sales (POS), on-board computers and other equipment.
  • POS Point of Sales
  • FIG. 4 is a block diagram showing a part of the structure of the mobile phone 400 related to the embodiment of the present invention.
  • the mobile phone 400 includes: a radio frequency (RF) circuit 410, a power source 420, a processor 430, a memory 440, an input unit 450, and a display unit 460.
  • RF radio frequency
  • the structure of the handset shown in FIG. 4 does not constitute a limitation to the handset, and may include more or less components than those illustrated, or some components may be combined, or different components may be arranged.
  • the components of the mobile phone 400 will be specifically described below with reference to FIG. 4:
  • the RF circuit 410 can be used for receiving and transmitting signals during and after the transmission or reception of information, in particular, after receiving the downlink information of the base station, and processing it to the processor 430; in addition, transmitting the designed uplink data to the base station.
  • RF circuit 410 includes, but is not limited to, an antenna, at least one amplifier, a transceiver, a coupler, a Low Noise Amplifier (LNA), a duplexer, and the like.
  • LNA Low Noise Amplifier
  • RF circuitry 410 can also communicate with the network and other devices via wireless communication.
  • the wireless communication may use any communication standard or protocol, including but not limited to Global System of Mobile communication (GSM), General Packet Radio Service (GPRS), Code Division Multiple Access (Code). Division Multiple Access (CDMA), Wideband Code Division Multiple Access (WCDMA), Long Term Evolution (LTE), E-mail, Short Messaging Service (SMS), etc.
  • GSM Global System of Mobile communication
  • GPRS General Packet Radio
  • the memory 440 can be used to store software programs and modules, and the processor 430 executes various functional applications and data processing of the mobile phone 400 by running software programs and modules stored in the memory 440.
  • the memory 440 may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application required for at least one function (such as a sound playing function, an image playing function, etc.), and the like; the storage data area may be stored. Data (such as audio data, phone book, etc.) created according to the use of the mobile phone 400.
  • memory 440 can include high speed random access memory, and can also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other volatile solid state storage device.
  • the input unit 450 can be configured to receive input numeric or character information and to generate key signal inputs related to user settings and function control of the handset 400.
  • the input unit 450 may include a touch panel 451 and other input devices 452.
  • Touch panel 451 also known as touch screen, can be collected a touch operation on or near the user (such as a user using a finger, a stylus, or the like on the touch panel 451 or near the touch panel 451), and driving according to a preset program Connection device.
  • the touch panel 451 can include two parts: a touch detection device and a touch controller.
  • the touch detection device detects the touch orientation of the user, and detects a signal brought by the touch operation, and transmits the signal to the touch controller; the touch controller receives the touch information from the touch detection device, converts the touch information into contact coordinates, and sends the touch information.
  • the processor 430 is provided and can receive commands from the processor 430 and execute them.
  • the touch panel 451 can be implemented in various types such as resistive, capacitive, infrared, and surface acoustic waves.
  • the input unit 450 may also include other input devices 452.
  • other input devices 452 may include, but are not limited to, one or more of a physical keyboard, function keys (such as volume control buttons, switch buttons, etc.), trackballs, mice, joysticks, and the like.
  • the display unit 460 can be used to display information input by the user or information provided to the user and various menus of the mobile phone 400.
  • the display unit 460 is a display system of the mobile phone 400 for presenting the interface UI and realizing human-computer interaction.
  • the display unit 460 can include a display panel 461.
  • the display panel 461 can be configured in the form of an LCD, an OLED, or the like.
  • the touch panel 451 can cover the display panel 461. When the touch panel 451 detects a touch operation thereon or nearby, the touch panel 451 transmits to the processor 430 to determine the type of the touch event, and then the processor 430 according to the touch event. The type provides a corresponding visual output on display panel 461.
  • the touch panel 451 and the display panel 451 function as two separate components to implement the input and input functions of the mobile phone 400, in some embodiments, the touch panel 451 can be integrated with the display panel 461. The input and output functions of the mobile phone 400 are implemented.
  • the handset 400 can also include at least one type of sensor 470, such as a light sensor, motion sensor, and other sensors.
  • the light sensor may include an ambient light sensor and a proximity sensor, wherein the ambient light sensor may adjust the brightness of the display panel 461 according to the brightness of the ambient light, and the proximity sensor may close the display panel 461 when the mobile phone 400 moves to the ear. / or backlight.
  • the accelerometer sensor can detect the acceleration of each direction (usually three axes). When it is still, it can detect the magnitude and direction of gravity. It can be used to identify the posture of the mobile phone (such as horizontal and vertical).
  • Audio circuit 480, speaker 481, microphone 482 can provide an audio interface between the user and handset 400.
  • the audio circuit 480 can transmit the converted electrical data of the received audio data to the speaker 481 for conversion to the sound signal output by the speaker 481; on the other hand, the microphone 482 converts the collected sound signal into an electrical signal by the audio circuit 480. After receiving, it is converted into audio data, and then the audio data is output to the RF circuit 410 for transmission to, for example, another mobile phone, or the audio data is output to the memory 440 for further processing.
  • WiFi is a short-range wireless transmission technology
  • the mobile phone 400 can help users to send and receive emails, browse web pages, and access streaming media through the WiFi module 490, which provides wireless broadband Internet access for users.
  • FIG. 4 shows the WiFi module 490, it can be understood that it does not belong to the essential configuration of the mobile phone 400, and may be omitted as needed within the scope of not changing the essence of the invention.
  • Processor 430 is the control center of handset 400, which connects various portions of the entire handset using various interfaces and lines, by running or executing software programs and/or modules stored in memory 440, and recalling data stored in memory 440, The various functions and processing data of the mobile phone 400 are performed, thereby realizing various services based on the mobile phone.
  • the processor 430 may include one or more processing units; preferably, the processor 430 may integrate an application processor and a modem processor, where the application processor mainly processes an operating system, a user interface, an application, and the like.
  • the modem processor primarily handles wireless communications. It can be understood that the above modem processor may not be integrated into the processor 430.
  • the handset 400 also includes a power source 420 (e.g., a battery) that powers the various components.
  • a power source 420 e.g., a battery
  • the power source can be logically coupled to the processor 430 via a power management system to manage functions such as charging, discharging, and power consumption through the power management system.
  • the mobile phone 400 may further include a camera, a Bluetooth module, and the like, and details are not described herein.
  • a display method provided by an embodiment of the present invention where the method is used for a display system of a terminal device,
  • the display system is configured to execute a device display process, an application drawing process, and a layer surface flinger synthesis process in each Vsync cycle.
  • the terminal device may be a computer, a tablet computer, and a mobile phone as shown in FIG. 4, and the like.
  • the specific process of the method includes:
  • Step 501 The display system acquires a first processing duration of the first process performed by the display system in the Mth Vsync period, where the first process is an application drawing process or a surfaceflinger synthesis process, where the M is greater than or equal to A positive integer of 1.
  • the display system of the terminal device adopts the Vsync technology
  • the display system needs to process the application drawing process, the surfaceflinger synthesis process, and the device display process in parallel at the beginning of each Vsync cycle.
  • each process in a Vsync cycle should be completed before or at the end of the Vsync cycle.
  • the device display process only needs the display system to read. The data in the cache is taken and displayed in the display panel of the terminal device. Therefore, the process has a shorter processing time than the other two processes, generally several milliseconds, and the other two processes take a little longer.
  • Step 502 The display system determines, according to the first processing duration, a start time of the first process in the M+1th Vsync period, where the first time is in the M+1th Vsync period.
  • the start time of the process is after the start time of the device display process, and the start time of the first process is offset from the start time of the M+1th Vsync cycle by the first time
  • the sum of the processing durations is less than or equal to the duration of the M+1th Vsync period.
  • the start time of the device display flow in the M+1th Vsync period is the start time of the M+1 Vsync periods.
  • the start time of the first process in the M+1th Vsync period set by the display system is after the start time of the device display process, that is, the first The start time of the process is offset, so that the first process is delayed.
  • the display system Since the display system needs to delay execution of the first process in the M+1th Vsync period, the display system determines the start of the first process in the M+1th Vsync period. At the beginning time, it is also necessary to avoid the phenomenon that the display system has not executed the first process due to the end of the M+1th Vsync period, thereby causing hysteresis of the display screen. Therefore, when determining the start time of the first process in the M+1th Vsync period, it is necessary to estimate a processing duration of the first process performed by the display system in the current Vsync period.
  • the similarity between adjacent two frames of images is relatively high, and the data processed by the display system in the application drawing process in two adjacent Vsync cycles respectively belongs to the data in the adjacent two frames of images, and the same reason.
  • the data processed by the display system in the surfaceflinger synthesis process in the adjacent two Vsync cycles respectively belongs to the data in the adjacent two frames of images, and the data processed in the device display process in the adjacent two Vsync cycles respectively
  • the display system performs the processing duration of the application drawing process, the surfaceflinger synthesis process, and the device display process in the Mth Vsync cycle, respectively, with the display system in the Mth
  • the processing duration of executing the corresponding process in +1 Vsync cycles is similar.
  • the first processing duration of the first process in the Mth Vsync period is adopted, and the display system estimated by the display system is in the M+ The processing duration of the first process in one Vsync cycle.
  • the offset time of the start time of the first flow in the M+1th Vsync period determined by the display system from the start time of the M+1th Vsync cycle and the first processing time The sum is less than or equal to the duration of the M+1th Vsync period, and it is guaranteed that the display system may end the execution of the first process at the end of the M+1th Vsync period to avoid causing a display screen. Hysteresis.
  • the display system offsets the start time of the first process in the M+1th Vsync period, delaying execution of the first process, and reducing display of the terminal device.
  • the system processes the time of three processes in parallel in the M+1th Vsync period, and reduces the power consumption of the CPU of the terminal device.
  • the display system sets the start time of the surfaceflinger synthesis process in the M+1th Vsync period. After the device displays the time, the display system delays execution of the surfaceflinger synthesis process, as shown, reducing the time that the display system processes three processes in parallel in the M+1th Vsync cycle, and reduces the terminal device.
  • CPU power consumption is a surfaceflinger synthesis process shown in FIG. 6A
  • the first process when it is an application drawing process, it can also be reduced.
  • the display system processes the time of three processes in parallel in the M+1th Vsync period, and reduces the power consumption of the CPU of the terminal device.
  • the display system determines, according to the first processing duration, a start time of the first process in the M+1th Vsync period, including:
  • the display system acquires a second processing duration of the display system to execute the device display process in the Mth Vsync period;
  • a start time of the first process in the M+1th Vsync period is a time when the start time of the device display flow passes the second processing time, and the start time distance of the first flow
  • the sum of the offset duration of the start time of the M+1th Vsync period and the first processing duration is less than or equal to the duration of the M+1th Vsync period.
  • the display system needs to set the start time of the first flow in the M+1th Vsync period to be before: the first time or the first time
  • the start time of the first flow in the M+1th Vsync period may be set to be equal to the first time or after the first time .
  • the display system sets a start time of the first process in the M+1th Vsync period to be equal to the first time or after the first time, that is, in the display system. Performing the first process when or after the device display process is executed in the M+1th Vsync period, so that the display system can be guaranteed to serially execute the device display process and the first process. It is ensured that the display system does not process three processes in parallel in one Vsync cycle, further reducing the power consumption of the CPU of the terminal device.
  • FIG. 7A is a view showing a display example when the first process is a surfaceflinger synthesis process, where the display system executes a start time of a surfaceflinger synthesis process in an M+1th Vsync cycle, where the display system executes After the device shows that the process is completed, that is, the display system serially executes the device display process and the surfaceflinger synthesis process, ensuring that the display system does not process in parallel in the M+1th Vsync cycle.
  • Three processes reduce the power consumption of the CPU of the terminal device.
  • FIG. 7B is a display example diagram when the first process is an application drawing process, and the display system executes a start time of an application drawing process in an M+1th Vsync cycle, where the display system executes After the device shows that the process is completed, that is, the display system serially executes the device display process and the application drawing process, ensuring that the display system does not process in parallel in the M+1th Vsync period.
  • Three processes reduce the power consumption of the CPU of the terminal device.
  • the start time of the first process in the M+1th Vsync period is that the display system performs the first process of the first process in the Mth Vsync period.
  • the processing duration is estimated to be that the display system actually performs the processing duration of the first process in the M+1th Vsync period, but since the display system is actually in the M+1th Vsync period Performing the required processing duration of the first process may have an error with the first processing duration, if the display system actually performs the first process in the M+1th Vsync period
  • the processing duration is greater than the first processing duration, and the starting time of the first flow in the M+1th Vsync period is offset from the starting time of the M+1th Vsync period.
  • the sum of the first processing durations is equal to the duration of the M+1th Vsync period, so that the display system cannot perform the first process in the M+1th Vsync period, thereby causing the The display system displays a hysteresis.
  • the start time of the first flow determined by the display system is offset from the start time of the M+1th Vsync period.
  • the sum of the duration and the first processing duration is less than or equal to the difference between the duration of the M+1th Vsync period and the first preset duration.
  • the display system is configured to perform the first processing time length in the M+1th Vsync period, and the duration difference of the first processing duration is less than the first preset duration, the display system
  • the execution of the first process may be ended before the end of the M+1th Vsync period, which reduces the probability of occurrence of hysteresis in the display screen of the display system.
  • Step 503 In the M+1th Vsync period, the display system starts to execute the display process at a start time of the device display process; the display system is at a start time of the first process The execution of the first process begins.
  • the display system is in the M+1th Vsync period.
  • the device display process begins.
  • the starting time of the second process in the M+1th Vsync period may also be the starting time of the M+1 Vsync periods, where the second process is an application drawing process and Other processes in the surfaceflinger synthesis process other than the first process, that is, the display system starts to execute the second process and the device display process at the beginning of the M+1th Vsync cycle. Because the display system performs the display of the application drawing process and the surfaceflinger synthesis process, the power consumption of the CPU of the terminal device is high, and the display system performs the device display with respect to the above two processes. The process power consumption is low.
  • the first process is delayed in the M+1th Vsync period of the display system, and the execution is started at the start time of the M+1th Vsync cycle.
  • the second process and the device display process can not only reduce the time for the display system to process three processes in parallel in the M+1th Vsync period, but also reduce the display system in the M+1th Vsync period. The time during which the first process and the second process are processed in parallel further reduces the power consumption of the CPU of the terminal device.
  • the display system may also delay execution of the second process.
  • the method further includes:
  • the display system acquires a third processing duration of the second process performed by the display system in the Mth Vsync period, where the second process is in addition to the first process in the application drawing process and the surfaceflinger synthesis process.
  • Other processes ;
  • the display system starts executing the second process at a start time of the second process.
  • the display system is also configured to pass the third process of the second process of the Mth Vsync cycle when determining a start time of the second process in the M+1th Vsync period.
  • the duration of processing of the second flow in the M+1th Vsync period of the display system estimated by the display system.
  • the display system also offsets the start time of the second flow in the M+1th Vsync period, so that the second flow is also delayed, and the display may be reduced.
  • the system processes the time of three processes in parallel, which reduces the power consumption of the CPU of the terminal device.
  • the first process is a surfaceflinger synthesis process
  • the second process is an application drawing process.
  • the display system passes the first process and the The start time offset of the second process reduces the time during which the display system processes the three processes in parallel in the M+1th Vsync period, and reduces the power consumption of the CPU of the terminal device.
  • the start time of the first process in the M+1th Vsync period determined by the display system is different from the start time of the second process, as shown in FIG. Not only can the time for the display system to process three processes in parallel in the M+1th Vsync period, but also reduce the display system to process the first process in parallel in the M+1th Vsync period.
  • the time of the second process further reduces the power consumption of the CPU of the terminal device.
  • the display system determines, according to the third processing duration, a start time of the second process in the M+1 Vsync periods, including:
  • the display system acquires a second processing duration of the display system to execute the device display process in the Mth Vsync period;
  • the display system needs to set the start time of the second flow in the M+1th Vsync period to be before: the second time or the first time After the second time, it is necessary to determine the sum of the offset duration of the second flow from the start time of the M+1th Vsync cycle and the third processing duration and the M+1th a relationship between the duration of the Vsync period and the sum of the offset duration from the start time of the M+1th Vsync period and the third processing duration is less than or equal to the
  • the start time of the second process in the M+1th Vsync period may be set equal to the second time or after the second time .
  • the display system sets a start time of the second flow in the M+1th Vsync period to be equal to or after the second time, that is, in the display system. Performing the second process when or after the device display process is executed in the M+1th Vsync period, so that the display system can be guaranteed to serially execute the device display process and the second process. It is ensured that the display system does not process three processes in parallel in one Vsync cycle, further reducing the power consumption of the CPU of the terminal device.
  • the first process is a surfaceflinger synthesis process
  • the second process is an application drawing process
  • the display system is in the M+1th Vsync cycle.
  • the display system may be in a certain period of time after the current Vsync cycle ends executing the device display process
  • three processes are executed in parallel with the conventional display system, and the power consumption of the CPU of the terminal device is reduced.
  • the offset time of the start time of the second flow determined by the display system from the start time of the M+1th Vsync period and the third process The sum of the durations is less than or equal to the difference between the duration of the M+1th Vsync period and the second preset duration. In this way, even if the required processing duration of the second flow is greater than the third processing duration in the M+1th Vsync period, as long as the display system is actually in the M+1th
  • the duration of the required processing time of the second process in the Vsync period minus the third processing duration is less than the second preset duration, and the display system can still be in the M+1th Vsync period.
  • Exceeding the execution of the second flow before the end the probability of occurrence of hysteresis on the display screen of the display system is reduced.
  • the second preset duration may be the same as the first preset duration, or may be different, which is not limited by the embodiment of the present invention.
  • the sum of the first processing duration, the second processing duration, and the third processing duration determined by the display system is less than or equal to a duration of the M+1th Vsync period
  • the duration between the start time of the first process and the start time of the second process is greater than or equal to the first processing duration or the third processing duration.
  • the display system sequentially executes the device display process, the first process, and the second process; if the first process is a surfaceflinger synthesis process and the second process is an application drawing process, the display process is as shown in FIG. 10A; If the first process is an application drawing process and the second process is a surfaceflinger synthesis process, the display process is as shown in FIG. 10B;
  • the display system sequentially executes a device display process, the second process, and the first process;
  • the process is a surfaceflinger synthesis process
  • the second process is an application drawing process
  • the display process is as shown in FIG. 10B; if the first process is an application drawing process and the second process is a surfaceflinger synthesis process, the display process is as shown in FIG. 10A.
  • the display system when the sum of the first processing duration, the second processing duration, and the third processing duration determined by the display system is less than or equal to the duration of the M+1th Vsync period, The duration between the start time of the first process and the start time of the second process in the M+1th Vsync period is greater than or equal to the first processing duration or the third processing duration.
  • the display system performs three processes serially in the M+1th Vsync period, thereby minimizing the power consumption of the CPU of the terminal device.
  • the display system may set a third preset duration, and the display system determines that the sum of the first processing duration, the second processing duration, and the third processing duration is less than Or when the difference between the duration of the M+1th Vsync period and the third preset duration is set, the start time of the first flow in the M+1th Vsync period and the first The duration between the start times of the two processes is greater than or equal to the first processing duration or the third processing duration.
  • the display system may offset a start time of the first process in each Vsync cycle, reduce a time in which the display system processes three processes in parallel in each Vsync cycle, and decrease the terminal.
  • the power consumption of the CPU during the entire display process similarly, the display system may further offset the start time of the second process in each Vsync cycle, reducing the display in each Vsync cycle.
  • the system processes the time of the three processes in parallel to reduce the CPU power consumption of the terminal device during the entire display process; further, the display system sets the start time of the first process in each Vsync cycle and the The starting time of the second process is set to different times, reducing the time during which the display system processes the first process and the second process in parallel in each Vsync cycle, further reducing the CPU of the terminal device. Power consumption; further, if the display system sets the start time of the first process and the second process in each Vsync cycle The duration between the start time is greater than or equal to the first processing duration or the third processing duration, so that the display system can sequentially perform three processes in each Vsync cycle, which can minimize the terminal.
  • the display system can shift the start time of the first process in each Vsync cycle, a delay display or a frame dropping phenomenon may occur. Since the display system needs to synthesize data in the surfaceflinger synthesis process in the current Vsync cycle as the drawing result of the application drawing process in the last Vsync cycle, the data to be displayed in the device display process is the surfaceflinger synthesis process in the last Vsync cycle. After the synthesis results.
  • the surfaceflinger synthesis process in a certain Vsync cycle is synthesized too slowly, and at the end of the Vsync cycle, the surfaceflinger synthesis process Not yet completed, and the application drawing process is normal or too fast.
  • the synthesis result of the surfaceflinger synthesis process of the previous cycle cannot be displayed, which will lead to delay display and frame dropping. .
  • the display system offsets the start time of the surfaceflinger synthesis process in the mth Vsync cycle according to the processing duration of the surfaceflinger process in the previous Vsync cycle; as shown in the figure, the device in the Vsync cycle displays the processing process When the data of one frame is processed and completed, the first frame image is displayed in the display panel; the data of the second frame is processed in the surfaceflinger synthesis process; and the data of the third frame is processed by the drawing process;
  • the display system still offsets the start time of the surfaceflinger synthesis process in the m+1th Vsync cycle according to the processing duration of the surfaceflinger process in the mth Vsync cycle; as shown in the figure, the device display in the Vsync cycle Processing the data of the second frame in the process, and when the processing is completed, the second frame image is displayed in the display panel; the data of the third frame is processed in the surfaceflinger synthesis process; and the data of the fourth frame is processed by the drawing; wherein, due to the surfaceflinger synthesis The processing time of the process is long, resulting in the surfaceflinger synthesis process not being processed at the end of the m+1th Vsync cycle;
  • the display system continues to process according to the surfaceflinger process in the m+1th Vsync cycle
  • the duration offsets the start time of the surfaceflinger synthesis process in the m+2 Vsync cycle; as shown in the figure, the surfaceflinger synthesis process starts in the m+1th Vsync cycle at the start execution time of the device display flow.
  • the third frame cannot be displayed, so that the second frame image is still displayed in the display panel; after the surfaceflinger synthesis process started in the m+1 Vsync cycles, the surfaceflinger synthesis of the Vsync cycle is started.
  • a process processing the data of the fourth frame in the surfaceflinger synthesis process; and applying the data of the fifth frame by the drawing;
  • the display system continues to shift the start time of the surfaceflinger synthesis process in the m+3 Vsync cycles according to the processing duration of the surfaceflinger process in the m+2 Vsync cycles; as shown in the figure, the Vsync cycle
  • the data of the fourth frame is processed, and when the processing is completed, the fourth frame image is displayed in the display panel; the data of the fifth frame is processed in the surfaceflinger synthesis flow; and the data of the sixth frame is processed by the application drawing.
  • the second frame image of two Vsync cycles is continuously displayed in the display panel, and the fourth frame is directly displayed, and the third frame is not displayed, so that the frame dropping phenomenon occurs. .
  • the display system offsets the start time of the surfaceflinger synthesis process in the mth Vsync cycle according to the processing duration of the surfaceflinger process in the previous Vsync cycle; as shown in the figure, the device display flow in the Vsync cycle displays When the data of one frame is processed and completed, the image of the first frame is displayed on the display panel, the data of the second frame is processed in the surfaceflinger synthesis process, and the data of the third frame is processed by the drawing process;
  • the display system still offsets the start time of the surfaceflinger synthesis process in the m+1th Vsync cycle according to the processing duration of the surfaceflinger process in the mth Vsync cycle; as shown in the figure, the device display in the Vsync cycle
  • the device display in the Vsync cycle
  • the data of the second frame is displayed in the process and the processing is completed
  • the second frame image is displayed in the display panel
  • the data of the third frame is processed in the surfaceflinger synthesis process. Since there is no image update subsequently, there is no data processing in the application drawing process; Due to the long processing time of the surfaceflinger synthesis process, the surfaceflinger synthesis process is not processed at the end of the m+1th Vsync cycle;
  • the display system continues to offset the start time of the surfaceflinger synthesis process in the m+2 Vsync cycles according to the processing duration of the surfaceflinger process in the m+1th Vsync cycle; as shown in the figure, due to the device display process The surfaceflinger synthesis process started in the m+1th Vsync cycle at the start of execution time has not been executed yet. Therefore, the third frame cannot be displayed, so that the second frame image is still displayed in the display panel, at m+1.
  • the surfaceflinger synthesis process of the Vsync cycle is started, but since the application drawing process does not process data in the m+1 Vsync cycle, the surfaceflinger synthesis process of the Vsync cycle has no data. Processing; the application drawing process in this Vsync cycle continues without data processing;
  • the m+1th Vsync cycle In the surfaceflinger synthesis process, the generated data is not overwritten.
  • the data of the third frame is processed in the device display flow, and when the processing is completed, the third frame image is displayed on the display panel.
  • the third frame image is displayed, so that the third frame image has a delayed display phenomenon.
  • the display system offsets the start time of the surfaceflinger synthesis process in each Vsync cycle, the surfaceflinger synthesis process in a Vsync cycle may be longer than the surfaceflinger synthesis process in the previous Vsync cycle, then the subsequent occurrence occurs.
  • the probability of delay display and frame loss is high.
  • the display system will shift the start time of the surfaceflinger synthesis process after continuously setting a Vsync cycle, and then the next Vsync.
  • the start time of the surfaceflinger synthesis process in the cycle is set to the start time of the Vsync cycle, so that the start time of the surfaceflinger synthesis process in the Vsync cycle is not offset;
  • the display system sets the start time of the application drawing process in the next Vsync cycle to the start time of the Vsync cycle after continuously setting a Vsync period to offset the start time of the application drawing process. Make the start time of the surfaceflinger synthesis process in the Vsync cycle not Offset.
  • the display system sets the start time of the first flow in the M+P Vsync cycles to be the start time of the M+P Vsync cycles, where the P is preset. a positive integer greater than 1;
  • the display system sets a start time of the second flow in the M+Qth Vsync period as a start time of the M+Qth Vsync period, where the Q is a preset positive integer greater than 1. .
  • the P and the Q may be the same number, such as 10, 20, etc., and may be set to different numbers, which is not limited by the present invention.
  • the frequency of the CPU of the terminal device can directly reflect the working performance and power consumption of the CPU. Therefore, in the embodiment of the present invention, by simulating the frequency of the CPU, it is determined that the drawing process is applied to the application in each Vsync cycle. After at least one process in the surfaceflinger synthesis process sets the corresponding offset, whether the power consumption and performance of the CPU can be reduced. See Figure 13:
  • the next Vsync is determined according to the first processing duration.
  • the start time of the first process in the period (the M+1th Vsync period), the first process is an application drawing process or a surfaceflinger synthesis process, and the first part in the M+1th Vsync period
  • the start time of the process is after the start time of the device display process, and the start time of the first process is offset from the start time of the M+1th Vsync cycle and the first processing time
  • the sum is less than or equal to the duration of the M+1th Vsync period; in the M+1th Vsync period, the display system begins to execute the device display process at the beginning of the device display flow And executing the first process at the beginning of the first process.
  • the display system delays execution of any one of the application drawing process and the surfaceflinger synthesis process, and reduces the display system of the terminal device in the M+
  • the processing time of three processes is paralleled in one Vsync cycle, and the power consumption of the CPU of the terminal device is reduced.
  • the embodiment of the present invention further provides a terminal device, which is configured to execute a device display process, an application drawing process, and a surfaceflinger synthesis process in a Vsync cycle.
  • the terminal device is used. 1400 includes: an obtaining unit 1401, a processing unit 1402, and an operating unit 1403, where
  • the obtaining unit 1401 is configured to obtain a first processing duration of the first process performed by the running unit 1403 in the Mth Vsync period, where the first process is an application drawing process or a surfaceflinger synthesis process, where the M is greater than or equal to 1. Positive integer
  • the processing unit 1402 is configured to determine, according to the first processing duration, an M+1th Vsync period. a start time of the first process, in the M+1th Vsync period, a start time of the first process is after a start time of the device display process, and the first process The sum of the offset time from the start time of the M+1th Vsync period and the first processing duration is less than or equal to the duration of the M+1th Vsync period;
  • the running unit 1403 is configured to start executing the display process at a start time of the device display process in the M+1th Vsync cycle, and start executing the first process at a start time of the first process A process.
  • a start time of the device display process in the M+1th Vsync period is a start time of the M+1 Vsync periods.
  • the obtaining unit 1401 is further configured to acquire, by the running unit 1403, a second processing duration of the device display process in the Mth Vsync period;
  • the processing unit 1402 is specifically configured to: determine, according to the first processing duration and the second processing duration, a start time of the first process in the M+1th Vsync period, where the a start time of a process is equal to or after the first time, the first time is a time when the start time of the device display flow passes the second processing time, and the first time The sum of the offset duration from the start time of the M+1th Vsync period and the first processing duration is less than or equal to the duration of the M+1th Vsync period.
  • the obtaining unit 1401 is further configured to acquire, by the running unit 1403, a third processing duration of the second process in the Mth Vsync period, where the second process is an application drawing process and a surfaceflinger synthesis.
  • the second process is an application drawing process and a surfaceflinger synthesis.
  • the processing unit 1402 is further configured to determine, according to the third processing duration, a start time of the second process in the M+1 Vsync periods, where the M+1 Vsync cycles are a starting time of the second flow is after a start time of the device display flow, and an offset time of the start time of the second flow from a start time of the M+1th Vsync cycle is The sum of the third processing durations is less than or equal to the duration of the M+1th Vsync period;
  • the running unit 1403 is further configured to start executing the second process at a start time of the second process in the M+1th Vsync cycle.
  • the obtaining unit 1401 is further configured to acquire, by the running unit 1403, a second processing duration of the device display process in the Mth Vsync period;
  • the processing unit 1402 is specifically configured to: determine, according to the second processing duration and the third processing duration, a start time of the second process in the M+1th Vsync period, where the The start time of the second process is equal to or after the second time, the second time is a time when the start time of the device display flow passes the second processing time, and the second time The sum of the offset duration from the start time of the M+1th Vsync period and the third processing duration is less than or equal to the duration of the M+1th Vsync period.
  • processing unit 1402 is further configured to:
  • the duration between the start time of the first process and the start time of the second process is greater than or equal to the first processing duration or the third processing duration.
  • the sum of the offset time of the start time of the first process from the start time of the M+1th Vsync period and the first processing duration is less than or equal to the M+1th The difference between the duration of the Vsync period and the first preset duration.
  • the sum of the offset time from the start time of the M+1th Vsync period and the third processing duration is less than or equal to the M+1th The difference between the duration of the Vsync period and the second preset duration.
  • processing unit 1402 is further configured to:
  • the start time of the first flow in the M+P Vsync cycle is set as the start time of the M+P Vsync cycles, and the P is a preset positive integer greater than 1.
  • processing unit 1402 is further configured to:
  • the start time of the second flow in the M+Qth Vsync period is set as the start time of the M+Qth Vsync cycle, and the Q is a preset positive integer greater than 1.
  • the terminal device determines the M+1 Vsync period according to the first processing time length.
  • the first process is an application drawing process or a surfaceflinger synthesis process, and the start time of the first process in the M+1th Vsync cycle is at the beginning of the device display process.
  • the sum of the offset time of the start time of the first flow from the start time of the M+1th Vsync period and the first processing time is less than or equal to the M+1th The duration of the Vsync cycle; in the M+1th Vsync cycle, the terminal device starts executing the device display process at the beginning of the device display flow, and at the start time of the first process The execution of the first process begins. In this way, in the M+1th Vsync period, the display system delays execution of any one of the application drawing process and the surfaceflinger synthesis process, and reduces the terminal device in the M+1th Vsync. The time of processing three processes in parallel during the cycle reduces the power consumption of the CPU of the terminal device.
  • the division of the unit in the embodiment of the present invention is schematic, and is only a logical function division, and the actual implementation may have another division manner.
  • the functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.
  • the integrated unit if implemented in the form of a software functional unit and sold or used as a standalone product, may be stored in a computer readable storage medium.
  • the instructions include a plurality of instructions for causing a terminal device (which may be a personal computer, a cell phone, or a network device, etc.) or a processor to perform all or part of the steps of the methods described in various embodiments of the present application.
  • the foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like, and the program code can be stored. Medium.
  • the embodiment of the present invention further provides a terminal device, where the terminal device For performing the device display process, the application drawing process, and the layer surface flinger synthesis process in a vertical synchronous Vsync cycle, as shown in FIG. 15, the terminal device 1500 includes: a processor 1501, a bus 1502, a memory 1503, and a display panel 1504. among them,
  • the processor 1501, the memory 1503, and the display panel 1504 are connected by the bus 1502; the bus 1502 may be a peripheral component interconnect (PCI) bus or an extended industry standard structure (extended industry) Standard architecture, referred to as EISA) bus.
  • PCI peripheral component interconnect
  • EISA extended industry standard structure
  • the bus can be divided into an address bus, a data bus, a control bus, and the like. For ease of representation, only one thick line is shown in Figure 15, but it does not mean that there is only one bus or one type of bus.
  • the processor 1501 is configured to implement the display method as shown in FIG. 5:
  • the display flow is started at a start time of the device display flow; and the first flow is started at a start time of the first flow.
  • a start time of the device display process in the M+1th Vsync period is a start time of the M+1 Vsync periods.
  • the processor 1501 determines, according to the first processing duration, a start time of the first process in the M+1th Vsync period, including:
  • a start time of the first process in a period, where a start time of the first process is equal to or after the first time, the first time is a start from a flow of the device display a time when the second processing time is passed, and a sum of an offset time of the start time of the first flow from a start time of the M+1th Vsync cycle and the first processing time is less than or It is equal to the duration of the M+1th Vsync period.
  • the processor 1501 is further configured to:
  • the second process is started at the start time of the second process.
  • determining, according to the third processing duration, a start time of the second process in the M+1 Vsync periods including:
  • the processor 1501 determines the first processing duration and the second processing time
  • the sum of the length of the third processing time and the duration of the M+1th Vsync period is less than or equal to the duration between the start time of the first flow and the start time of the second flow Is greater than or equal to the first processing duration or the third processing duration.
  • the sum of the offset time of the start time of the first process from the start time of the M+1th Vsync period and the first processing duration is less than or equal to the M+1th The difference between the duration of the Vsync period and the first preset duration.
  • the sum of the offset time from the start time of the M+1th Vsync period and the third processing duration is less than or equal to the M+1th The difference between the duration of the Vsync period and the second preset duration.
  • the processor 1501 is further configured to:
  • the start time of the first flow in the M+P Vsync cycle is set as the start time of the M+P Vsync cycles, and the P is a preset positive integer greater than 1.
  • the processor 1501 is further configured to:
  • the start time of the second flow in the M+Qth Vsync period is set as the start time of the M+Qth Vsync cycle, and the Q is a preset positive integer greater than 1.
  • the display panel 1504 is configured to display, after the processor performs the device display process in each Vsync cycle, the processor to execute an image generated by the device display process, and the display panel 1504 may adopt an LCD, OLED and other forms are set.
  • the display system of the terminal device acquires the first processing duration of the first process in the Mth Vsync period, according to the Determining a start time of the first process in the M+1th Vsync period, where the first process is an application drawing process or a surfaceflinger synthesis process, where the M+1 Vsync period is
  • the start time of the first process is after the start time of the device display process, and the start time of the first process is offset from the start time of the M+1th Vsync cycle by the first time
  • the sum of the processing durations is less than or equal to the duration of the M+1th Vsync period; in the M+1th Vsync period, the display system starts executing the device at the beginning of the device display flow Display the process and start at the beginning of the first process The first process is described.
  • the display system delays execution of any one of the application drawing process and the surfaceflinger synthesis process, and reduces the display system of the terminal device in the M+
  • the processing time of three processes is paralleled in one Vsync cycle, and the power consumption of the CPU of the terminal device is reduced.
  • embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) including computer usable program code.
  • computer-usable storage media including but not limited to disk storage, CD-ROM, optical storage, etc.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device.
  • the instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.

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Abstract

一种显示方法及终端设备，用以解决现有技术中终端设备的显示系统在Vsync周期内，并行处理三个流程，造成终端设备的CPU功耗较大的问题。该方法为：终端设备的显示系统根据第M个Vsync周期内第一流程的第一处理时长，确定第M+1个Vsync周期内所述第一流程的起始时刻，使所述显示系统在开始执行器件显示流程之后再开始执行所述第一流程。这样，所述显示系统使第M+1个Vsync周期内第一流程延迟执行，减少了所述显示系统在所述第M+1个Vsync周期内并行处理三个流程的时间，降低了终端设备的CPU的功耗。

Description

一种显示方法及终端设备 技术领域
本申请涉及显示系统技术领域，尤其涉及一种显示方法及终端设备。
背景技术
目前的多种终端设备，例如计算机、手机、平板电脑、销售终端(Point of Sales，POS)或车载电脑等，均含有内置的显示系统，用于呈现用户界面(User Interface，UI)，实现人机交互，显示系统中包括的显示面板，可以采用液晶显示器(Liquid Crystal Display，LCD)、有机发光二极管(Organic Light-Emitting Diode，OLED)等形式来配置。
为了保证终端设备显示流畅，避免出现丢帧或跳帧等情况，显示系统通常采用垂直同步(Vertical Synchronization，Vsync)技术，Vsync技术的基本原理为：所述显示系统每隔设定时长，生成一个控制信号，使Vsync周期触发，所述设定时长即为Vsync周期的取值，例如16毫秒(ms)。在一个Vsync周期触发时，所述显示系统开始并行处理以下三个流程：应用绘图、图层(surfaceflinger)合成、器件显示，其中，surfaceflinger合成流程中需要合成的原始数据为上个Vsync周期内应用绘图流程的绘图结果，而器件显示流程中需要显示的数据为上个Vsync周期内surfaceflinger合成流程后的合成结果。
然而，终端设备的显示系统在应用传统的Vsync技术时，每个Vsync周期触发时，需要所述显示系统并行处理应用绘图、surfaceflinger合成，以及器件显示三个流程，造成终端设备的中央处理器(Central Processing Unit，CPU)的瞬时功耗较大，进而导致所述CPU的频率过高，降低了所述CPU的工作性能。
发明内容
本申请实施例提供了一种显示方法及终端设备，用以解决现有技术中终 端设备的显示系统在Vsync周期内，并行处理三个流程，造成终端设备的CPU功耗较大的问题。
第一方面，本申请实施例提供了一种显示方法，所述方法适用于终端设备的显示系统，其中，所述显示系统在每个Vsync周期内执行器件显示流程、应用绘图流程以及图层surfaceflinger合成流程，所述方法包括以下步骤：
所述显示系统获取所述显示系统在第M个Vsync周期内执行第一流程的第一处理时长，所述第一流程为应用绘图流程或surfaceflinger合成流程，所述M为大于或等于1的正整数；
所述显示系统根据所述第一处理时长，确定第M+1个Vsync周期内的所述第一流程的起始时刻，所述第M+1个Vsync周期内，所述第一流程的起始时刻位于所述器件显示流程的起始时刻之后，且所述第一流程的起始时刻距离所述第M+1个Vsync周期的起始时刻的偏移时长与所述第一处理时长之和小于或等于所述第M+1个Vsync周期的时长；
在所述第M+1个Vsync周期中，所述显示系统在所述器件显示流程的起始时刻开始执行所述显示流程；所述显示系统在所述第一流程的起始时刻开始执行所述第一流程。
采用上述方法，在所述第M+1个Vsync周期内，所述显示系统使应用绘图流程、surfaceflinger合成流程中的任一个流程，延迟执行，减少了所述终端设备的显示系统在所述第M+1个Vsync周期内并行处理三个流程的时间，降低终端设备的CPU的功耗。
在一个可能的设计中，所述第M+1个Vsync周期内所述器件显示流程的起始时刻为所述M+1个Vsync周期的起始时刻。
在一个可能的设计中，所述显示系统根据所述第一处理时长，确定所述第M+1个Vsync周期内的所述第一流程的起始时刻，包括：
所述显示系统获取所述显示系统在所述第M个Vsync周期内执行所述器件显示流程的第二处理时长；
所述显示系统根据所述第一处理时长和所述第二处理时长，确定所述第 M+1个Vsync周期内的所述第一流程的起始时刻，所述第一流程的起始时刻等于第一时刻或位于所述第一时刻之后，所述第一时刻为距离所述器件显示流程的起始时刻经过所述第二处理时长的时刻，且所述第一流程的起始时刻距离所述第M+1个Vsync周期的起始时刻的偏移时长与所述第一处理时长之和小于或等于所述第M+1个Vsync周期的时长。
通过上述方法，所述显示系统将所述第M+1个Vsync周期内的所述第一流程的起始时刻设置为等于第一时刻或位于所述第一时刻之后，即在所述显示系统在所述第M+1个Vsync周期内执行完所述器件显示流程时或之后开始执行所述第一流程，这样，可以保证所述显示系统串行执行器件显示流程和所述第一流程，保证了所述显示系统不会在一个Vsync周期内并行处理三个流程，进一步降低了终端设备的CPU的功耗。
在一个可能的设计中，所述显示系统获取所述显示系统在所述第M个Vsync周期内执行第二流程的第三处理时长，所述第二流程为应用绘图流程和surfaceflinger合成流程中除所述第一流程以外的其他流程；
所述显示系统根据所述第三处理时长，确定所述M+1个Vsync周期内的所述第二流程的起始时刻，所述第M+1个Vsync周期内所述第二流程的起始时刻位于所述器件显示流程的起始时刻之后，且所述第二流程的起始时刻距离所述第M+1个Vsync周期的起始时刻的偏移时长与所述第三处理时长之和小于或等于所述第M+1个Vsync周期的时长；
在所述第M+1个Vsync周期中，所述显示系统在所述第二流程的起始时刻开始执行所述第二流程。
通过上述方法，所述显示系统也将在所述第M+1个Vsync周期内的所述第二流程的起始时刻偏移，使所述第二流程也延迟执行，也可以减少所述显示系统在所述第M+1个Vsync周期内，并行处理三个流程的时间，降低了终端设备的CPU的功耗。
在一个可能的设计中，所述显示系统确定的所述第M+1个Vsync周期内的所述第一流程的起始时刻与所述第二流程的起始时刻不同，这样，不仅可 以减少所述显示系统在第M+1个Vsync周期内，并行处理三个流程的时间，还可能减少所述显示系统在第M+1个Vsync周期内，并行处理所述第一流程和第二流程的时间，进一步降低了所述终端设备的CPU的功耗。
在一个可能的设计中，所述显示系统根据所述第三处理时长，确定所述M+1个Vsync周期内的所述第二流程的起始时刻，包括：
所述显示系统获取所述显示系统在所述第M个Vsync周期内执行所述器件显示流程的第二处理时长；
所述显示系统根据所述第二处理时长和所述第三处理时长，确定所述第M+1个Vsync周期内的所述第二流程的起始时刻，所述第二流程的起始时刻等于第二时刻或位于所述第二时刻之后，所述第二时刻为距离所述器件显示流程的起始时刻经过所述第二处理时长的时刻，且所述第二流程的起始时刻距离所述第M+1个Vsync周期的起始时刻的偏移时长与所述第三处理时长之和小于或等于所述第M+1个Vsync周期的时长。
通过上述方法，所述显示系统将所述第M+1个Vsync周期内的所述第二流程的起始时刻设置为等于第二时刻或位于所述第二时刻之后，即在所述显示系统在所述第M+1个Vsync周期内执行完所述器件显示流程时或之后开始执行所述第二流程，这样，可以保证所述显示系统串行执行器件显示流程和所述第二流程，保证了所述显示系统不会在一个Vsync周期内并行处理三个流程，进一步降低了终端设备的CPU的功耗。
在一个可能的设计中，当所述显示系统确定的所述第一处理时长、所述第二处理时长以及所述第三处理时长的和，小于或等于所述第M+1个Vsync周期的时长时，所述第一流程的起始时刻与所述第二流程的起始时刻之间的时长，大于或等于所述第一处理时长或所述第三处理时长。
通过以上方法，在所述显示系统确定的所述第一处理时长、所述第二处理时长以及所述第三处理时长的和小于或等于所述第M+1个Vsync周期的时长时，设置所述第M+1个Vsync周期内所述第一流程的起始时刻和所述第二流程的起始时刻之间的时长，大于或等于所述第一处理时长或所述第三处理 时长，这样，所述显示系统在所述第M+1个Vsync周期内，串行执行三个流程，最大限度降低了所述终端设备的CPU的功耗。
在一个可能的设计中，所述第一流程的起始时刻距离所述第M+1个Vsync周期的起始时刻的偏移时长与所述第一处理时长之和小于或等于所述第M+1个Vsync周期的时长与第一预设时长的差。
这样，即使在所述第M+1个Vsync周期内执行所述第一流程的所需处理时长大于所述第一处理时长情况下，只要所述显示系统实际在所述第M+1个Vsync周期内执行所述第一流程的所需处理时长减去所述第一处理时长的时长差小于所述第一预设时长，所述显示系统仍然可以在所述第M+1个Vsync周期结束前结束执行所述第一流程，降低了所述显示系统显示画面发生迟滞现象的概率。
在一个可能的设计中，所述第二流程的起始时刻距离所述第M+1个Vsync周期的起始时刻的偏移时长与所述第三处理时长之和小于或等于所述第M+1个Vsync周期的时长与第二预设时长的差。
这样，即使在所述第M+1个Vsync周期内执行所述第二流程的所需处理时长大于所述第三处理时长的情况下，只要所述显示系统实际在所述第M+1个Vsync周期内执行所述第二流程的所需处理时长减去所述第三处理时长的时长差小于所述第二预设时长，所述显示系统仍然可以在所述第M+1个Vsync周期结束前结束执行所述第二流程，降低了所述显示系统显示画面发生迟滞现象的概率。
在一个可能的设计中，所述显示系统基于上述方法，从第M+1个Vsync周期开始，直到第M+P-1个Vsync周期中的每个Vsync周期内的所述第一流程的起始时刻均设置为相应Vsync周期的器件显示流程的起始时刻之后，即对所述第一流程的起始时刻进行偏移，且所述显示系统设置第M+P个Vsync周期内的所述第一流程的起始时刻为所述第M+P个Vsync周期的起始时刻，所述P为预设的大于1的正整数。例如，P＝11时，所述显示系统从第M+1个Vsync周期开始，持续10个Vsync周期，在每个Vsync周期内的所述第一 流程的起始时刻均设置为相应Vsync周期的器件显示流程的起始时刻之后，即对所述第一流程的起始时刻进行偏移，并将第M+11个Vsync周期内所述第一流程的起始时刻设置为所述第M+11个Vsync周期的起始时刻，后续每隔10个Vsync周期，即对下一个Vsync周期内所述第一流程的起始时刻设置为所述相应Vsync周期的起始时刻。
这样，所述显示系统将连续多个Vsync周期内的所述第一流程的起始时刻偏移，减少多个Vsync周期内所述显示系统并行处理三个流程的时间，降低所述终端设备在整个显示过程中CPU的功耗。同时，在持续将P-1个Vsync周期所述第一流程的起始时刻偏移后，将所述第M+P个Vsync周期内的所述第一流程的起始时刻设置为所述第M+P个Vsync周期的起始时刻，可以降低所述显示系统显示画面出现延迟显示和丢帧的现象的概率。
在一个可能的设计中，所述显示系统基于上述方法，从第M+1个Vsync周期开始，直到第M+Q-1个Vsync周期中的每个Vsync周期内的所述第二流程的起始时刻均设置为相应Vsync周期的器件显示流程的起始时刻之后，即对所述第二流程的起始时刻进行偏移，且所述显示系统设置第M+Q个Vsync周期内的所述第二流程的起始时刻为所述第M+Q个Vsync周期的起始时刻，所述Q为预设的大于1的正整数。例如，P＝21时，所述显示系统从第M+1个Vsync周期开始，持续20个Vsync周期，在每个Vsync周期内的所述第二流程的起始时刻均设置为相应Vsync周期的器件显示流程的起始时刻之后，即对所述第二流程的起始时刻进行偏移，并将第M+21个Vsync周期内所述第二流程的起始时刻设置为所述第M+21个Vsync周期的起始时刻，后续每隔20个Vsync周期，即对下一个Vsync周期内所述第二流程的起始时刻设置为所述相应Vsync周期的起始时刻。
这样，所述显示系统将连续多个Vsync周期内的所述第一流程的起始时刻偏移，减少多个Vsync周期内所述显示系统并行处理三个流程的时间，降低所述终端设备在整个显示过程中CPU的功耗。同时，在持续将Q-1个Vsync周期所述第二流程的起始时刻偏移后，将所述第M+Q个Vsync周期内的所述 第二流程的起始时刻设置为所述第M+Q个Vsync周期的起始时刻，可以降低所述显示系统显示画面出现延迟显示和丢帧的现象的概率。
另一方面，本发明实施例提供一种终端设备，所述终端设备具有实现上述方法实施例中终端设备行为的功能，所述功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。所述硬件或软件包括一个或多个与上述功能相对应的模块。
在一种可能的设计中，终端设备的结构中包括获取单元、处理单元，以及运行单元，这些单元可以执行上述方法示例中的相应功能，具体参见方法示例中的详细描述，不作赘述。
在另一种可能的设计中，所述终端设备的结构中包括处理器、总线、存储器以及显示面板，所述处理器、所述存储器和所述显示面板通过所述总线连接，所述处理器调用所述存储器中的指令，执行上述方法设计中的功能，所述显示面板，用于所述处理器在每个Vsync周期内执行所述器件显示流程后，显示所述处理器执行所述器件显示流程生成的图像。
本发明实施例中，终端设备的显示系统获取在第M个Vsync周期内执行第一流程的第一处理时长后，根据所述第一处理时长确定第M+1个Vsync周期内的所述第一流程的起始时刻，所述第一流程为应用绘图流程或surfaceflinger合成流程，所述第M+1个Vsync周期内所述第一流程的起始时刻位于器件显示流程的起始时刻之后，且所述第一流程的起始时刻距离所述第M+1个Vsync周期的起始时刻的偏移时长与所述第一处理时长之和小于或等于所述第M+1个Vsync周期的时长；在所述第M+1个Vsync周期中，所述显示系统在所述器件显示流程的起始时刻开始执行所述器件显示流程，并在所述第一流程的起始时刻开始执行所述第一流程。这样，在所述第M+1个Vsync周期内，所述显示系统使应用绘图流程、surfaceflinger合成流程中的任一个流程，延迟执行，减少了所述终端设备的显示系统在所述第M+1个Vsync周期内并行处理三个流程的时间，降低终端设备的CPU的功耗。
附图说明
图1为本发明实施例提供的一种显示系统的架构示意图；
图2为本发明实施例提供的显示一帧图像的流程示意图；
图3为现有技术提供的一种显示图像的流程示意图；
图4为本发明实施例提供的一种终端设备结构示意图；
图5为本发明实施例提供的一种显示方法的流程图；
图6A为本发明实施例提供的一种显示示例流程图；
图6B为本发明实施例提供的一种显示示例流程图；
图7A为本发明实施例提供的一种显示示例流程图；
图7B为本发明实施例提供的一种显示示例流程图；
图8为本发明实施例提供的一种显示示例流程图；
图9为本发明实施例提供的一种显示示例流程图；
图10A为本发明实施例提供的一种显示示例流程图；
图10B为本发明实施例提供的一种显示示例流程图；
图11为本发明实施例提供的一种出现丢帧现象的显示流程示意图；
图12为本发明实施例提供的一种出现延迟显示现象的显示流程示意图；
图13为本发明实施例提供的一种终端设备的CPU频率仿真图；
图14为本发明实施例提供的一种终端设备的结构示意图；
图15为本发明实施例提供的一种终端设备的结构示意图。
具体实施方式
为了使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明作进一步地详细描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本发明保护的范围。
本发明实施例提供一种显示方法及终端设备，用以解决现有技术中终端设备的显示系统在Vsync周期并行处理三个流程，造成终端设备的CPU功耗较大的问题。其中，方法和装置是基于同一发明构思的，由于方法及装置解决问题的原理相似，因此装置与方法的实施可以相互参见，重复之处不再赘述。
以下，对本申请中的部分用户进行解释说明，以便与本领域技术人员理解。
本发明涉及的“终端设备”，为含有内置的显示系统，可以实现人机交互功能的设备，该终端设备可以为计算机、手机、平板电脑、销售终端(Point of Sales，POS)或车载电脑等，在本申请中，仅以手机为例。
显示系统，内置于终端设备中，用于呈现界面UI，实现人机交互，可以对图像进行处理，并显示于显示系统中的显示面板，其中，该显示面板可以采用LCD、OLED等形式来配置。
图层，由许多像素组成，是构成图像的基本单元。一帧图像可以是一个图层，也为多个图层通过上下叠加的方式组成。图层就象是含有文字或图形等元素的胶片，一张张按顺序叠放在一起，组合起来形成图像的最终效果。
帧率，通常为1秒内显示图像的帧数，在本发明实施例中，帧率＝1秒/Vsync周期的时长。
另外，需要理解的是，在本申请的描述中，“第一”、“第二”等词汇，仅用于区分描述的目的，而不能理解为指示或暗示相对重要性，也不能理解为指示或暗示顺序。
本发明实施例提供的一种显示方法，适用于如图1所示的显示系统架构，在该显示系统架构中，包括控制模块101、应用绘图模块102、以及surfaceflinger合成模块103、存储器104、器件显示模块105、显示面板106，以及时钟模块107，其中，
控制模块101向显示系统中的应用绘图模块102、surfaceflinger合成模块103以及器件显示模块105发送控制信号，实现对上述模块的控制，使应用绘 图模块102、surfaceflinger合成模块103以及器件显示模块105处理图像数据；
所述应用绘图模块102在接收到所述控制模块101的控制信号后，获取所述终端设备需要显示的多个应用(如图中应用1至应用n)的待显示图层数据，并根据获取的多个待显示图层数据进行绘图处理，生成多个图层，并将生成的多个图层发送至所述存储器104；
所述surfaceflinger合成模块103在接收到所述控制模块101的控制信号后，从所述存储器104中获取所述多个图层，并进行图层合成，生成一帧最终的图像，并将生成的图像发送至所述存储器104，其中，所述surfaceflinger合成模块103在进行图层合成中，还包括硬件合成(Hardware Compose，HWC)过程；
所述存储器104，通常为缓存器，存储所述应用绘图模块102生成的多个图层，以及存储所述surfaceflinger合成模块103生成的图像；
所述器件显示模块105，在接收到所述控制模块101的控制信号后，获取所述存储器104中的所述图像，并将所述图像推送至所述显示面板106；
所述显示面板106，用于直接显示所述器件显示模块105发送过来的所述图像；
所述时钟模块107，用于统计时钟，每隔设定时长(Vsync周期)，向所述控制模块101发送时钟信号，通知所述控制模块101触发一个Vsync周期，生产控制信号，并将控制信号同时发送给应用绘图模块102、surfaceflinger合成模块103以及器件显示模块105，通知各模块执行对应的流程。
因此，传统的，通过如图1所示的显示系统，实现显示图像的流程，如图2所示，包括：
应用绘图流程：获取需要显示的多个应用的多个待显示图层数据，对所述多个待显示图层数据进行绘图处理，生成多个图层；
surfaceflinger合成流程：对所述应用绘图流程中生成的多个图层进行surfaceflinger处理，以及HWC处理，生成一帧待显示的图像；
器件显示流程：将上述Surfaceflinger合成流程生成的所述待显示的图像 进行器件显示处理，将所述待显示的图像推送至显示面板。
根据上述对显示系统和显示图像的流程的描述可知，在一个Vsync周期内，显示系统可以执行一次应用绘图流程、surfaceflinger合成流程和器件显示流程。而一帧图像的显示则需要以上三个流程处理，因此，一帧图像需要3个Vsync周期才能显示。为了避免显示图像过慢，所述显示系统在每个Vsync周期并行处理以下三个流程：应用绘图流程、surfaceflinger合成流程、器件显示流程，其中，surfaceflinger合成流程中需要合成的原始数据为上个Vsync周期内应用绘图流程的绘图结果，而器件显示流程中需要显示的数据为上个Vsync周期内surfaceflinger合成流程后的合成结果，且传统的，以上三个流程在一个Vsync周期触发时，同时开始执行，如图3所示：
在第m个Vsync周期的起始时刻，同时启动所述三个流程，其中，在器件显示流程中处理第1帧图像的数据，在处理完成时，所述显示面板中显示第1帧图像；在surfaceflinger合成流程中处理第2帧图像的数据；在应用绘图流程中处理第3帧图像的数据；
在第m+1个Vsync周期的起始时刻，同时启动所述三个流程，在器件显示流程中处理第2帧图像的数据，在完成处理时，所述显示面板中显示第2帧图像；surfaceflinger流程处理第3帧图像的数据；应用绘图流程中处理第4帧图像的数据；
在第m+2个Vsync周期的起始时刻，同时启动所述三个流程，在器件显示流程中处理第3帧图像的数据，在完成处理时，所述显示面板中显示第3帧图像；surfaceflinger流程处理第4帧图像的数据；应用绘图流程中处理第5帧图像的数据；
在第m+3个Vsync周期的起始时刻，同时启动所述三个流程，在器件显示流程中处理第4帧图像的数据，在完成处理时，所述显示面板中显示第4帧图像；surfaceflinger流程处理第5帧图像的数据；应用绘图流程中处理第6帧图像的数据。
由于器件显示流程只需要读取缓存中的数据，并显示到所述显示面板中， 因此，每个Vsync周期中该流程的处理时长较固定，一般为几毫秒。因此显示面板通常显示一帧图像的时间，通常是从一个Vsync周期器件显示流程结束至下一个Vsync周期器件显示流程结束，总时长与Vsync周期的长度几乎相同。
本发明实施例中的显示方法，适用于各种包含显示系统，且支持Vsync技术的终端设备，例如计算机、手机、POS等屏幕显示图像时，均可以采用本发明实施例提供的显示方法。
采用本发明技术方案，终端设备的显示系统获取在第M个Vsync周期内执行第一流程的第一处理时长后，根据所述第一处理时长确定下一个Vsync周期(第M+1个Vsync周期)内的所述第一流程的起始时刻，所述第一流程为应用绘图流程或surfaceflinger合成流程，所述第M+1个Vsync周期内所述第一流程的起始时刻位于器件显示流程的起始时刻之后，且所述第一流程的起始时刻距离所述第M+1个Vsync周期的起始时刻的偏移时长与所述第一处理时长之和小于或等于所述第M+1个Vsync周期的时长；在所述第M+1个Vsync周期中，所述显示系统在所述器件显示流程的起始时刻开始执行所述器件显示流程，并在所述第一流程的起始时刻开始执行所述第一流程。这样，在所述第M+1个Vsync周期内，所述显示系统使应用绘图流程、surfaceflinger合成流程中的任一个流程，延迟执行，减少了所述终端设备的显示系统在所述第M+1个Vsync周期内并行处理三个流程的时间，降低终端设备的CPU的功耗。
本发明实施例提供了一种显示方法及终端设备，适用于终端设备中，本发明实施例涉及的所述终端设备可以为计算机、手机、平板电脑、个人数字助理(Personal Digital Assistant，PDA)、销售终端(Point of Sales，POS)、车载电脑等设备。
以终端设备为手机为例，图4示出的是与本发明实施例相关的手机400的部分结构的框图。参考图4，手机400包括：射频(Radio Frequency，RF)电路410、电源420、处理器430、存储器440、输入单元450、显示单元460、 传感器470、音频电路480、以及无线保真(wireless fidelity，WiFi)模块490等部件。本领域技术人员可以理解，图4中示出的手机结构并不构成对手机的限定，可以包括比图示更多或更少的部件，或者组合某些部件，或者不同的部件布置。
下面结合图4对手机400的各个构成部件进行具体的介绍：
RF电路410可用于收发信息或通话过程中，信号的接收和发送，特别地，将基站的下行信息接收后，给处理器430处理；另外，将设计上行的数据发送给基站。通常，RF电路410包括但不限于天线、至少一个放大器、收发信机、耦合器、低噪声放大器(Low Noise Amplifier，LNA)、双工器等。此外，RF电路410还可以通过无线通信与网络和其他设备通信。所述无线通信可以使用任一通信标准或协议，包括但不限于全球移动通讯系统(Global System of Mobile communication，GSM)、通用分组无线服务(General Packet Radio Service，GPRS)、码分多址(Code Division Multiple Access，CDMA)、宽带码分多址(Wideband Code Division Multiple Access，WCDMA)、长期演进(Long Term Evolution，LTE)、电子邮件、短消息服务(Short Messaging Service，SMS)等。
存储器440可用于存储软件程序以及模块，处理器430通过运行存储在存储器440的软件程序以及模块，从而执行手机400的各种功能应用以及数据处理。存储器440可主要包括存储程序区和存储数据区，其中，存储程序区可存储操作系统、至少一个功能所需的应用程序(比如声音播放功能、图象播放功能等)等；存储数据区可存储根据手机400的使用所创建的数据(比如音频数据、电话本等)等。此外，存储器440可以包括高速随机存取存储器，还可以包括非易失性存储器，例如至少一个磁盘存储器件、闪存器件、或其他易失性固态存储器件。
输入单元450可用于接收输入的数字或字符信息，以及产生与手机400的用户设置以及功能控制有关的键信号输入。具体地，输入单元450可包括触控面板451以及其他输入设备452。触控面板451，也称为触摸屏，可收集 用户在其上或附近的触摸操作(比如用户使用手指、触笔等任何适合的物体或附件在触控面板451上或在触控面板451附近的操作)，并根据预先设定的程式驱动相应的连接装置。可选的，触控面板451可包括触摸检测装置和触摸控制器两个部分。其中，触摸检测装置检测用户的触摸方位，并检测触摸操作带来的信号，将信号传送给触摸控制器；触摸控制器从触摸检测装置上接收触摸信息，并将它转换成触点坐标，再送给处理器430，并能接收处理器430发来的命令并加以执行。此外，可以采用电阻式、电容式、红外线以及表面声波等多种类型实现触控面板451。除了触控面板451，输入单元450还可以包括其他输入设备452。具体地，其他输入设备452可以包括但不限于物理键盘、功能键(比如音量控制按键、开关按键等)、轨迹球、鼠标、操作杆等中的一种或多种。
显示单元460可用于显示由用户输入的信息或提供给用户的信息以及手机400的各种菜单，所述显示单元460即为手机400的显示系统，用于呈现界面UI，实现人机交互。显示单元460可包括显示面板461，可选的，可以采用LCD、OLED等形式来配置显示面板461。进一步的，触控面板451可覆盖显示面板461，当触控面板451检测到在其上或附近的触摸操作后，传送给处理器430以确定触摸事件的类型，随后处理器430根据触摸事件的类型在显示面板461上提供相应的视觉输出。虽然在图4中，触控面板451与显示面板451是作为两个独立的部件来实现手机400的输入和输入功能，但是在某些实施例中，可以将触控面板451与显示面板461集成而实现手机400的输入和输出功能。
手机400还可包括至少一种传感器470，比如光传感器、运动传感器以及其他传感器。具体地，光传感器可包括环境光传感器及接近传感器，其中，环境光传感器可根据环境光线的明暗来调节显示面板461的亮度，接近传感器可在手机400移动到耳边时，关闭显示面板461和/或背光。作为运动传感器的一种，加速计传感器可检测各个方向上(一般为三轴)加速度的大小，静止时可检测出重力的大小及方向，可用于识别手机姿态的应用(比如横竖 屏切换、相关游戏、磁力计姿态校准)、振动识别相关功能(比如计步器、敲击)等；至于手机400还可配置的陀螺仪、气压计、湿度计、温度计、红外线传感器等其他传感器，在此不再赘述。
音频电路480、扬声器481，麦克风482可提供用户与手机400之间的音频接口。音频电路480可将接收到的音频数据转换后的电信号，传输到扬声器481，由扬声器481转换为声音信号输出；另一方面，麦克风482将收集的声音信号转换为电信号，由音频电路480接收后转换为音频数据，再将音频数据输出至RF电路410以发送给比如另一手机，或者将音频数据输出至存储器440以便进一步处理。
WiFi属于短距离无线传输技术，手机400通过WiFi模块490可以帮助用户收发电子邮件、浏览网页和访问流式媒体等，它为用户提供了无线的宽带互联网访问。虽然图4示出了WiFi模块490，但是可以理解的是，其并不属于手机400的必须构成，完全可以根据需要在不改变发明的本质的范围内而省略。
处理器430是手机400的控制中心，利用各种接口和线路连接整个手机的各个部分，通过运行或执行存储在存储器440内的软件程序和/或模块，以及调用存储在存储器440内的数据，执行手机400的各种功能和处理数据，从而实现基于手机的多种业务。可选的，处理器430可包括一个或多个处理单元；优选的，处理器430可集成应用处理器和调制解调处理器，其中，应用处理器主要处理操作系统、用户界面和应用程序等，调制解调处理器主要处理无线通信。可以理解的是，上述调制解调处理器也可以不集成到处理器430中。
手机400还包括给各个部件供电的电源420(比如电池)，优选的，电源可以通过电源管理系统与处理器430逻辑相连，从而通过电源管理系统实现管理充电、放电、以及功耗等功能。
尽管未示出，手机400还可以包括摄像头、蓝牙模块等，在此不再赘述。
本发明实施例提供的一种显示方法，该方法用于终端设备的显示系统， 所述显示系统用于在每个Vsync周期内执行器件显示流程、应用绘图流程以及图层surfaceflinger合成流程，所述终端设备可以为计算机、平板电脑，以及如图4所示的手机等，参阅图图5所示，该方法的具体流程包括：
步骤501：所述显示系统获取所述显示系统在第M个Vsync周期内执行第一流程的第一处理时长，所述第一流程为应用绘图流程或surfaceflinger合成流程，所述M为大于或等于1的正整数。
传统的，终端设备的显示系统采用Vsync技术时，在每个Vsync周期的起始时刻，所述显示系统需要并行处理应用绘图流程、surfaceflinger合成流程以及器件显示流程。通常情况下，为了避免显示画面的迟滞，在一个Vsync周期内的每个流程均应该在该Vsync周期结束之前或结束时完成，由于以上三个流程中，器件显示流程只需要所述显示系统读取缓存中的数据，并显示到所述终端设备的显示面板中，因此，该流程相对于另外两个流程，处理时长较短，一般为几毫秒，而另外两个流程耗时稍长。
步骤502：所述显示系统根据所述第一处理时长，确定第M+1个Vsync周期内的所述第一流程的起始时刻，所述第M+1个Vsync周期内，所述第一流程的起始时刻位于所述器件显示流程的起始时刻之后，且所述第一流程的起始时刻距离所述第M+1个Vsync周期的起始时刻的偏移时长与所述第一处理时长之和小于或等于所述第M+1个Vsync周期的时长。
其中，所述第M+1个Vsync周期内所述器件显示流程的起始时刻为所述M+1个Vsync周期的起始时刻。且由于在步骤502中，所述显示系统设置的所述第M+1个Vsync周期内的所述第一流程的起始时刻位于所述器件显示流程的起始时刻之后，即将所述第一流程的起始时刻偏移，使所述第一流程被延迟执行。
由于所述显示系统需要将所述第M+1个Vsync周期内的所述第一流程延迟执行，在所述显示系统确定所述第M+1个Vsync周期内的所述第一流程的起始时刻时，还需要尽量避免出现由于所述第M+1个Vsync周期结束，所述显示系统还没有执行完所述第一流程，进而造成显示画面的迟滞的现象，因 此，在确定所述第M+1个Vsync周期内的所述第一流程的起始时刻时，需要估计在所述当前Vsync周期内所述显示系统执行所述第一流程的处理时长。而通常情况下，相邻两帧图像的相似度较高，而所述显示系统分别在相邻两个Vsync周期内的应用绘图流程中处理的数据属于相邻两帧图像中的数据，同理，所述显示系统分别在相邻两个Vsync周期内的surfaceflinger合成流程中处理的数据属于相邻两帧图像中的数据，分别在相邻两个Vsync周期内的器件显示流程中处理的数据也属于相邻两帧图像中的数据，因此，所述显示系统在第M个Vsync周期内执行应用绘图流程、surfaceflinger合成流程和器件显示流程的处理时长，分别与所述显示系统在所述第M+1个Vsync周期内执行相应的流程的处理时长相似。
基于以上结论，在本发明实施例中，是通过第M个Vsync周期内的所述第一流程的所述第一处理时长，作为所述显示系统估计的所述显示系统在所述第M+1个Vsync周期内所述第一流程的处理时长。
所述显示系统确定的所述第M+1个Vsync周期内所述第一流程的起始时刻距离所述第M+1个Vsync周期的起始时刻的偏移时长与所述第一处理时长之和小于或等于所述第M+1个Vsync周期的时长，保证在所述第M+1个Vsync周期结束时，预计所述显示系统可以结束执行所述第一流程，避免造成显示画面的迟滞。
通过步骤502，所述显示系统将在所述第M+1个Vsync周期内的所述第一流程的起始时刻偏移，使所述第一流程延迟执行，减少了所述终端设备的显示系统在所述第M+1个Vsync周期内并行处理三个流程的时间，降低终端设备的CPU的功耗。例如图6A所示的当所述第一流程为surfaceflinger合成流程时的显示示例图，所述显示系统设置所述第M+1个Vsync周期内，所述surfaceflinger合成流程的起始时刻位于所述器件显示时刻之后，所述显示系统延迟执行所述surfaceflinger合成流程，如图所示，减少了所述显示系统在第M+1个Vsync周期内，并行处理三个流程的时间，降低了终端设备的CPU的功耗。同理，如图6B所示的当所述第一流程为应用绘图流程时，也可以减少 所述显示系统在第M+1个Vsync周期内，并行处理三个流程的时间，降低了终端设备的CPU的功耗。
可选的，所述显示系统根据所述第一处理时长，确定所述第M+1个Vsync周期内的所述第一流程的起始时刻，包括：
所述显示系统获取所述显示系统在所述第M个Vsync周期内执行所述器件显示流程的第二处理时长；
所述显示系统根据所述第一处理时长和所述第二处理时长，确定所述第M+1个Vsync周期内的所述第一流程的起始时刻，所述第一流程的起始时刻等于第一时刻或位于所述第一时刻之后，所述第一时刻为距离所述器件显示流程的起始时刻经过所述第二处理时长的时刻，且所述第一流程的起始时刻距离所述第M+1个Vsync周期的起始时刻的偏移时长与所述第一处理时长之和小于或等于所述第M+1个Vsync周期的时长。
所述显示系统为了避免显示画面迟滞，需要在将所述第M+1个Vsync周期内的所述第一流程的起始时刻设置为以下时刻之前：等于所述第一时刻或位于所述第一时刻之后，需要判断所述第一流程的起始时刻距离所述第M+1个Vsync周期的起始时刻的偏移时长与所述第一处理时长之和与所述第M+1个Vsync周期的时长的关系，在判定所述第一流程的起始时刻距离所述第M+1个Vsync周期的起始时刻的偏移时长与所述第一处理时长之和小于或等于所述第M+1个Vsync周期的时长时，即可以将所述第M+1个Vsync周期内的所述第一流程的起始时刻设置为等于所述第一时刻或位于所述第一时刻之后。
通过上述方法，所述显示系统将所述第M+1个Vsync周期内的所述第一流程的起始时刻设置为等于第一时刻或位于所述第一时刻之后，即在所述显示系统在所述第M+1个Vsync周期内执行完所述器件显示流程时或之后开始执行所述第一流程，这样，可以保证所述显示系统串行执行器件显示流程和所述第一流程，保证了所述显示系统不会在一个Vsync周期内并行处理三个流程，进一步降低了终端设备的CPU的功耗。
图7A所示的当所述第一流程为surfaceflinger合成流程时的显示示例图，所述显示系统在第M+1个Vsync周期内执行surfaceflinger合成流程的起始时刻，在所述显示系统执行所述器件显示流程完成的时刻之后，即所述显示系统串行执行所述器件显示流程和所述surfaceflinger合成流程，保证了所述显示系统不会在所述第M+1个Vsync周期内并行处理三个流程，降低了终端设备的CPU的功耗。
图7B所示的当所述第一流程为应用绘图流程时的显示示例图，所述显示系统在第M+1个Vsync周期内执行应用绘图流程的起始时刻，在所述显示系统执行所述器件显示流程完成的时刻之后，即所述显示系统串行执行所述器件显示流程和所述应用绘图流程，保证了所述显示系统不会在所述第M+1个Vsync周期内并行处理三个流程，降低了终端设备的CPU的功耗。
由以上论述可知，所述第M+1个Vsync周期内的所述第一流程的起始时刻是所述显示系统将所述第M个Vsync周期内执行所述第一流程的所述第一处理时长，估计为所述显示系统实际在所述第M+1个Vsync周期内执行所述第一流程的处理时长，但是，由于所述显示系统实际在所述第M+1个Vsync周期内执行所述第一流程的所需的处理时长，可能与所述第一处理时长存在误差，若所述显示系统实际在所述第M+1个Vsync周期内执行所述第一流程的所需处理时长大于所述第一处理时长，而所述第M+1个Vsync周期内所述第一流程的起始时刻距离所述第M+1个Vsync周期的起始时刻的偏移时长与所述第一处理时长之和等于所述第M+1个Vsync周期的时长，这样，所述显示系统在所述第M+1个Vsync周期就无法执行完所述第一流程，进而导致所述显示系统显示画面迟滞现象。
因此，可选的，为了降低由于上述原因出现的显示画面迟滞现象，所述显示系统确定的所述第一流程的起始时刻距离所述第M+1个Vsync周期的起始时刻的偏移时长与所述第一处理时长之和小于或等于所述第M+1个Vsync周期的时长与第一预设时长的差。这样，即使在所述第M+1个Vsync周期内执行所述第一流程的所需处理时长大于所述第一处理时长的情况下，只要所 述显示系统实际在所述第M+1个Vsync周期内执行所述第一流程的所需处理时长减去所述第一处理时长的时长差小于所述第一预设时长，所述显示系统仍然可以在所述第M+1个Vsync周期结束前结束执行所述第一流程，降低了所述显示系统显示画面发生迟滞现象的概率。
步骤503：在所述第M+1个Vsync周期中，所述显示系统在所述器件显示流程的起始时刻开始执行所述显示流程；所述显示系统在所述第一流程的起始时刻开始执行所述第一流程。
由于所述第M+1个Vsync周期内所述器件显示流程的起始时刻为所述M+1个Vsync周期的起始时刻，因此，所述显示系统在所述第M+1个Vsync周期的起始时刻，即开始执行所述器件显示流程。
可选的，所述第M+1个Vsync周期内所述第二流程的起始时刻，也可以为所述M+1个Vsync周期的起始时刻，所述第二流程为应用绘图流程和surfaceflinger合成流程中除所述第一流程以外的其他流程，即所述显示系统在所述第M+1个Vsync周期的起始时刻，同时开始执行所述第二流程和所述器件显示流程。由于所述显示系统执行所述显示所述应用绘图流程和surfaceflinger合成流程，都会导致所述终端设备的CPU的功耗较高，而相对于上述两个流程，所述显示系统执行所述器件显示流程功耗较低，所以，所述显示系统所述第M+1个Vsync周期内将所述第一流程延迟执行，在所述第M+1个Vsync周期的起始时刻同时开始执行所述第二流程和所述器件显示流程，不仅可以减少所述显示系统在第M+1个Vsync周期内，并行处理三个流程的时间，还可以减少所述显示系统在第M+1个Vsync周期内，并行处理所述第一流程和第二流程的时间，进一步降低了所述终端设备的CPU的功耗。
可选的，所述显示系统也可以延迟执行所述第二流程，具体的，所述方法还包括：
所述显示系统获取所述显示系统在所述第M个Vsync周期内执行第二流程的第三处理时长，所述第二流程为应用绘图流程和surfaceflinger合成流程中除所述第一流程以外的其他流程；
所述显示系统根据所述第三处理时长，确定所述M+1个Vsync周期内的所述第二流程的起始时刻，所述第M+1个Vsync周期内所述第二流程的起始时刻位于所述器件显示流程的起始时刻之后，且所述第二流程的起始时刻距离所述第M+1个Vsync周期的起始时刻的偏移时长与所述第三处理时长之和小于或等于所述第M+1个Vsync周期的时长；
在所述第M+1个Vsync周期中，所述显示系统在所述第二流程的起始时刻开始执行所述第二流程。
所述显示系统确定所述第M+1个Vsync周期的所述第二流程的起始时刻与在步骤502中，确定所述第M+1个Vsync周期的所述第一流程的起始时刻的过程和原理相同，在此不再赘述。
其中，所述显示系统在确定所述第M+1个Vsync周期内的所述第二流程的起始时刻时，也是通过所述第M个Vsync周期所述第二流程的所述第三处理时长，作为所述显示系统估计的所述显示系统在所述第M+1个Vsync周期内的所述第二流程的处理时长。
通过上述方法，所述显示系统也将在所述第M+1个Vsync周期内的所述第二流程的起始时刻偏移，使所述第二流程也延迟执行，也可以减少所述显示系统在所述第M+1个Vsync周期内，并行处理三个流程的时间，降低了终端设备的CPU的功耗。在如图8所示的显示示例图中，所述第一流程为surfaceflinger合成流程，所述第二流程为应用绘图流程，如图所示，所述显示系统通过对所述第一流程和所述第二流程的起始时刻偏移，减少所述显示系统在所述第M+1个Vsync周期内，并行处理三个流程的时间，降低了终端设备的CPU的功耗。
可选的，所述显示系统确定的所述第M+1个Vsync周期内的所述第一流程的起始时刻与所述第二流程的起始时刻不同，如图8所示，这样，不仅可以减少所述显示系统在第M+1个Vsync周期内，并行处理三个流程的时间，还可能减少所述显示系统在第M+1个Vsync周期内，并行处理所述第一流程和第二流程的时间，进一步降低了所述终端设备的CPU的功耗。
可选的，所述显示系统根据所述第三处理时长，确定所述M+1个Vsync周期内的所述第二流程的起始时刻，包括：
所述显示系统获取所述显示系统在所述第M个Vsync周期内执行所述器件显示流程的第二处理时长；
所述显示系统根据所述第二处理时长和所述第三处理时长，确定所述第M+1个Vsync周期内的所述第二流程的起始时刻，所述第二流程的起始时刻等于第二时刻或位于所述第二时刻之后，所述第二时刻为距离所述器件显示流程的起始时刻经过所述第二处理时长的时刻，且所述第二流程的起始时刻距离所述第M+1个Vsync周期的起始时刻的偏移时长与所述第三处理时长之和小于或等于所述第M+1个Vsync周期的时长。
所述显示系统为了避免显示画面迟滞，需要在将所述第M+1个Vsync周期内的所述第二流程的起始时刻设置为以下时刻之前：等于所述第二时刻或位于所述第二时刻之后，需要判断所述第二流程的起始时刻距离所述第M+1个Vsync周期的起始时刻的偏移时长与所述第三处理时长之和与所述第M+1个Vsync周期的时长的关系，在判定所述第二流程的起始时刻距离所述第M+1个Vsync周期的起始时刻的偏移时长与所述第三处理时长之和小于或等于所述第M+1个Vsync周期的时长时，即可以将所述第M+1个Vsync周期内的所述第二流程的起始时刻设置为等于所述第二时刻或位于所述第二时刻之后。
通过上述方法，所述显示系统将所述第M+1个Vsync周期内的所述第二流程的起始时刻设置为等于第二时刻或位于所述第二时刻之后，即在所述显示系统在所述第M+1个Vsync周期内执行完所述器件显示流程时或之后开始执行所述第二流程，这样，可以保证所述显示系统串行执行器件显示流程和所述第二流程，保证了所述显示系统不会在一个Vsync周期内并行处理三个流程，进一步降低了终端设备的CPU的功耗。
如图9所示的显示示例图中，所述第一流程为surfaceflinger合成流程，所述第二流程为应用绘图流程，所述显示系统在所述第M+1个Vsync周期内 执行应用绘图流程和surfaceflinger合成流程的时刻，在所述显示系统执行所述器件显示流程完成的时刻之后，那么所述显示系统可能在所述当前Vsync周期结束执行器件显示流程后的某段时间内，并行所述第一流程和所述第二流程这两个流程，相对于传统的所述显示系统并行执行三个流程，降低了所述终端设备的CPU的功耗。
为了降低显示画面迟滞现象，可选的，所述显示系统确定的所述第二流程的起始时刻距离所述第M+1个Vsync周期的起始时刻的偏移时长与所述第三处理时长之和小于或等于所述第M+1个Vsync周期的时长与第二预设时长的差。这样，即使在所述第M+1个Vsync周期内执行所述第二流程的所需处理时长大于所述第三处理时长的情况下，只要所述显示系统实际在所述第M+1个Vsync周期内执行所述第二流程的所需处理时长减去所述第三处理时长的时长差小于所述第二预设时长，所述显示系统仍然可以在所述第M+1个Vsync周期结束前结束执行所述第二流程，降低了所述显示系统显示画面发生迟滞现象的概率。
可选的，所述第二预设时长与上述所述第一预设时长可以相同，也可以不同，本发明实施例对此不在限定。
可选的，当所述显示系统确定的所述第一处理时长、所述第二处理时长以及所述第三处理时长的和，小于或等于所述第M+1个Vsync周期的时长时，所述第一流程的起始时刻与所述第二流程的起始时刻之间的时长，大于或等于所述第一处理时长或所述第三处理时长。
其中，当所述第一流程的起始时刻与所述第二流程的起始时刻之间的时长，大于或等于所述第一处理时长时，那么，在所述第M+1个Vsync周期内，所述显示系统依次执行器件显示流程、所述第一流程、所述第二流程；若第一流程为surfaceflinger合成流程、第二流程为应用绘图流程，则显示流程如图10A所示；若第一流程为应用绘图流程，第二流程为surfaceflinger合成流程，则显示流程如图10B所示；
当所述第一流程的起始时刻与所述第二流程的起始时刻之间的时长，大 于或等于所述第三处理时长时，那么，在所述第M+1个Vsync周期内，所述显示系统依次执行器件显示流程、所述第二流程、所述第一流程；若第一流程为surfaceflinger合成流程、第二流程为应用绘图流程，则显示流程如图10B所示；若第一流程为应用绘图流程，第二流程为surfaceflinger合成流程，则显示流程如图10A所示。
通过以上方法，在所述显示系统确定的所述第一处理时长、所述第二处理时长以及所述第三处理时长的和小于或等于所述第M+1个Vsync周期的时长时，设置所述第M+1个Vsync周期内所述第一流程的起始时刻和所述第二流程的起始时刻之间的时长，大于或等于所述第一处理时长或所述第三处理时长，这样，如图10A和图10B所示，所述显示系统在所述第M+1个Vsync周期内，串行执行三个流程，最大限度降低了所述终端设备的CPU的功耗。
可选的，为了避免画面迟滞，所述显示系统可以设置第三预设时长，所述显示系统在确定所述第一处理时长、所述第二处理时长以及所述第三处理时长的和小于或等于所述第M+1个Vsync周期的时长与所述第三预设时长的差时，再设置所述第M+1个Vsync周期内所述第一流程的起始时刻和所述第二流程的起始时刻之间的时长，大于或等于所述第一处理时长或所述第三处理时长。
可选的，所述显示系统可以将每个Vsync周期内的所述第一流程的起始时刻偏移，减少每个Vsync周期内所述显示系统并行处理三个流程的时间，降低所述终端设备在整个显示过程中CPU的功耗；同理，进一步的，所述显示系统还可以将每个Vsync周期内所述第二流程的起始时刻偏移，减少每个Vsync周期内所述显示系统并行处理三个流程的时间，降低所述终端设备在整个显示过程中的CPU功耗；更进一步的，所述显示系统将每个Vsync周期内所述第一流程的起始时刻和所述第二流程的起始时刻设置为不同时刻，减少所述显示系统在每个Vsync周期并行处理所述第一流程和所述第二流程的时间，更进一步的降低了所述终端设备的CPU的功耗；再进一步的，若所述显示系统设置每个Vsync周期内所述第一流程的起始时刻和所述第二流程的起 始时刻之间的时长，大于或等于所述第一处理时长或所述第三处理时长，使所述显示系统可以在每个Vsync周期均依次执行三个流程，可以最大限度地降低所述终端设备在整个显示过程中的CPU功耗。
若所述显示系统可以将每个Vsync周期内的所述第一流程的起始时刻偏移，可能会出现延迟显示或丢帧现象。由于所述显示系统在当前Vsync周期内的surfaceflinger合成流程中需要合成的数据为上个Vsync周期内应用绘图流程的绘图结果，而器件显示流程中需要显示的数据为上个Vsync周期内surfaceflinger合成流程后的合成结果。在所述显示系统将每个Vsync周期内的surfaceflinger合成流程的起始时刻偏移的情况下，在某一个Vsync周期内的surfaceflinger合成流程合成过慢，在该Vsync周期结束时，该surfaceflinger合成流程还未完成，而应用绘图流程正常进行或过快，在下一个Vsync周期的器件显示流程中，不能显示上一周期的surfaceflinger合成流程的合成结果，此时就会导致出现延迟显示和丢帧的现象。
例如图11所示的显示系统的显示流程中出现的丢帧现象：
所述显示系统根据前一个Vsync周期内surfaceflinger流程的处理时长，将第m个Vsync周期内的surfaceflinger合成流程的起始时刻偏移；如图所示，该Vsync周期内的器件显示流程中处理第1帧的数据并处理完成时，所述显示面板中显示第1帧图像；surfaceflinger合成流程中处理第2帧的数据；应用绘图流程处理第3帧的数据；
所述显示系统仍根据第m个Vsync周期内surfaceflinger流程的处理时长，将第m+1个Vsync周期内的surfaceflinger合成流程的起始时刻偏移；如图所示，该Vsync周期内的器件显示流程中处理第2帧的数据，并处理完成时，所述显示面板中显示第2帧图像；surfaceflinger合成流程中处理第3帧的数据；应用绘图处理第4帧的数据；其中，由于surfaceflinger合成流程的处理时间较长，导致在第m+1个Vsync周期结束时，surfaceflinger合成流程未处理完成；
所述显示系统继续根据第m+1个Vsync周期内surfaceflinger流程的处理 时长，将第m+2个Vsync周期内的surfaceflinger合成流程的起始时刻偏移；如图所示，由于器件显示流程的起始执行时刻第m+1个Vsync周期内开始的surfaceflinger合成流程还未执行完，因此，无法显示第3帧，这样，所述显示面板中仍显示第2帧图像；在m+1个Vsync周期内开始的surfaceflinger合成流程执行完后，开启本Vsync周期的surfaceflinger合成流程；该surfaceflinger合成流程中处理第4帧的数据；应用绘图处理第5帧的数据；
所述显示系统继续根据第m+2个Vsync周期内surfaceflinger流程的处理时长，将第m+3个Vsync周期内的surfaceflinger合成流程的起始时刻偏移；如图所示，该Vsync周期内的器件显示流程中处理第4帧的数据，并处理完成时，所述显示面板中显示第4帧图像；surfaceflinger合成流程中处理第5帧的数据；应用绘图处理第6帧的数据。
如图所示，根据以上流程的描述，所述显示面板中连续显示了两个Vsync周期第2帧图像，后续直接显示第4帧，而未显示第3帧的，因此发生了丢帧的现象。
又例如图12所示的显示系统的显示流程中出现的延迟显示现象：
所述显示系统根据前一个Vsync周期内surfaceflinger流程的处理时长，将第m个Vsync周期内的surfaceflinger合成流程的起始时刻偏移；如图所示，该Vsync周期内的器件显示流程中显示第1帧的数据并处理完成时，所述显示面板中显示第1帧图像，surfaceflinger合成流程中处理第2帧的数据，应用绘图流程处理第3帧的数据；
所述显示系统仍根据第m个Vsync周期内surfaceflinger流程的处理时长，将第m+1个Vsync周期内的surfaceflinger合成流程的起始时刻偏移；如图所示，该Vsync周期内的器件显示流程中显示第2帧的数据并处理完成时，所述显示面板中显示第2帧图像，surfaceflinger合成流程中处理第3帧的数据，由于后续没有图像更新，应用绘图处理没有数据处理；其中，由于surfaceflinger合成流程的处理时间较长，导致在第m+1个Vsync周期结束时，surfaceflinger合成流程未处理完成；
所述显示系统继续根据第m+1个Vsync周期内surfaceflinger流程的处理时长，将第m+2个Vsync周期内的surfaceflinger合成流程的起始时刻偏移；如图所示，由于器件显示流程的起始执行时刻第m+1个Vsync周期内开始的surfaceflinger合成流程还未执行完，因此，无法显示第3帧，这样，所述显示面板中显示的仍显示第2帧图像，在m+1个Vsync周期内开始的surfaceflinger合成流程执行完后，开启本Vsync周期的surfaceflinger合成流程，但是由于在m+1个Vsync周期内应用绘图流程没有处理数据，因此本Vsync周期的surfaceflinger合成流程也没有数据处理；本Vsync周期内应用绘图流程继续不进行数据处理；
在第m+3个Vsync周期内，由于第m+1个Vsync周期内的surfaceflinger合成流程已经执行完成，且第m+2周期内的surfaceflinger合成流程没有数据处理，因此第m+1个Vsync周期内的surfaceflinger合成流程，生成的数据没有被覆盖掉，本Vsync周期内，器件显示流程中处理第3帧的数据，并处理完成时，所述显示面板中显示第3帧图像。
如图所示，根据以上流程的描述，所述显示面板中连续显示了两个Vsync周期第2帧图像后，才显示第3帧图像，因此第3帧图像发生了延迟显示现象。
若所述显示系统将每个Vsync周期内的surfaceflinger合成流程的起始时刻均偏移，某一个Vsync周期内surfaceflinger合成流程可能会比上一个Vsync周期内surfaceflinger合成流程执行时间长，那么，后续发生延迟显示和丢帧的概率较高，为了尽量避免出现上述延迟显示和丢帧的现象，所述显示系统在持续设定个Vsync周期将surfaceflinger合成流程的起始时刻偏移后，将下一个Vsync周期内的surfaceflinger合成流程的起始时刻设置为该Vsync周期的起始时刻，使该Vsync周期内的surfaceflinger合成流程的起始时刻不偏移；
同理，所述显示系统在持续设定个Vsync周期将应用绘图流程的起始时刻偏移后，将下一个Vsync周期内的应用绘图流程的起始时刻设置为该Vsync周期的起始时刻，使该Vsync周期内的surfaceflinger合成流程的起始时刻不 偏移。
综上所述，所述显示系统设置第M+P个Vsync周期内的所述第一流程的起始时刻为所述第M+P个Vsync周期的起始时刻，所述P为预设的大于1的正整数；以及
所述显示系统设置第M+Q个Vsync周期内的所述第二流程的起始时刻为所述第M+Q个Vsync周期的起始时刻，所述Q为预设的大于1的正整数。
其中，所述P和所述Q可以为相同的数目，如10、20等，也可以设置为不同的数目，本发明对此不作限定。
所述终端设备的CPU的频率，可以直接体现所述CPU的工作性能和功耗，因此，在本发明实施例中，通过仿真所述CPU的频率，确定在每个Vsync周期内针对应用绘图流程、surfaceflinger合成流程中的至少一个流程设置对应的偏移量后，是否可以降低所述CPU的功耗和工作性能。参阅图13所示：
当所述终端设备的显示系统在运行程序Process0时，采用传统的Vsync技术，在每个Vsync周期的起始时刻，开始并行处理应用绘图、surfaceflinger合成、器件显示三个流程，那么，所述显示系统在运行程序Process0的过程中每个时刻的所述CPU的频率，如图中上面的仿真结果1中cpufreq所示；
当所述终端设备的显示系统在运行同样的程序Process0，但将每个Vsync周期的中的surfaceflinger合成流程的起始时刻偏移，使该流程延迟执行，而另外两个流程则在每个Vsync周期的起始时刻开始执行，那么，所述显示系统在运行程序Process0的过程中每个时刻的所述CPU的频率，如图中下面的仿真结果2中cpufreq所示；
根据以上两个仿真结果，统计所述终端设备的CPU负荷，如表1所示：
表1 所述终端设备的CPU负荷统计
系统负荷 低频数量 中频数量 高频数量
仿真结果1 若干 43 8
仿真结果2 若干 42 2
由表1可知，在所述终端设备显示内容不变(显示内容的帧率不变)的情况下，在仿真结果2中的高频数量明显低于仿真结果1中的高频数量，显然，所述终端设备的显示系统将每个Vsync周期内的surfaceflinger合成流程的起始时刻偏移，使该流程延迟执行，可以明显降低所述终端设备的CPU的频率，降低系统的负荷，即降低所述CPU的功耗和工作性能，具有显著的效果。
综上所述，采用本发明实施例提供的显示方法，终端设备的显示系统获取在第M个Vsync周期内执行第一流程的第一处理时长后，根据所述第一处理时长确定下一个Vsync周期(第M+1个Vsync周期)内的所述第一流程的起始时刻，所述第一流程为应用绘图流程或surfaceflinger合成流程，所述第M+1个Vsync周期内所述第一流程的起始时刻位于器件显示流程的起始时刻之后，且所述第一流程的起始时刻距离所述第M+1个Vsync周期的起始时刻的偏移时长与所述第一处理时长之和小于或等于所述第M+1个Vsync周期的时长；在所述第M+1个Vsync周期中，所述显示系统在所述器件显示流程的起始时刻开始执行所述器件显示流程，并在所述第一流程的起始时刻开始执行所述第一流程。这样，在所述第M+1个Vsync周期内，所述显示系统使应用绘图流程、surfaceflinger合成流程中的任一个流程，延迟执行，减少了所述终端设备的显示系统在所述第M+1个Vsync周期内并行处理三个流程的时间，降低终端设备的CPU的功耗。
基于以上实施例，本发明实施例还提供了一种终端设备，所述终端设备用于在一个Vsync周期内执行器件显示流程、应用绘图流程以及surfaceflinger合成流程，参阅图14所示，该终端设备1400包括：获取单元1401、处理单元1402，以及运行单元1403，其中，
获取单元1401，用于获取运行单元1403在第M个Vsync周期内执行第一流程的第一处理时长，所述第一流程为应用绘图流程或surfaceflinger合成流程，所述M为大于或等于1的正整数；
处理单元1402，用于根据所述第一处理时长，确定第M+1个Vsync周期 内的所述第一流程的起始时刻，所述第M+1个Vsync周期内，所述第一流程的起始时刻位于所述器件显示流程的起始时刻之后，且所述第一流程的起始时刻距离所述第M+1个Vsync周期的起始时刻的偏移时长与所述第一处理时长之和小于或等于所述第M+1个Vsync周期的时长；
运行单元1403，用于在所述第M+1个Vsync周期中，在所述器件显示流程的起始时刻开始执行所述显示流程；在所述第一流程的起始时刻开始执行所述第一流程。
可选的，所述第M+1个Vsync周期内所述器件显示流程的起始时刻为所述M+1个Vsync周期的起始时刻。
可选的，所述获取单元1401，还用于获取所述运行单元1403在所述第M个Vsync周期内执行所述器件显示流程的第二处理时长；
所述处理单元1402，具体用于：根据所述第一处理时长和所述第二处理时长，确定所述第M+1个Vsync周期内的所述第一流程的起始时刻，所述第一流程的起始时刻等于第一时刻或位于所述第一时刻之后，所述第一时刻为距离所述器件显示流程的起始时刻经过所述第二处理时长的时刻，且所述第一流程的起始时刻距离所述第M+1个Vsync周期的起始时刻的偏移时长与所述第一处理时长之和小于或等于所述第M+1个Vsync周期的时长。
可选的，所述获取单元1401，还用于获取所述运行单元1403在所述第M个Vsync周期内执行第二流程的第三处理时长，所述第二流程为应用绘图流程和surfaceflinger合成流程中除所述第一流程以外的其他流程；
所述处理单元1402，还用于根据所述第三处理时长，确定所述M+1个Vsync周期内的所述第二流程的起始时刻，所述第M+1个Vsync周期内所述第二流程的起始时刻位于所述器件显示流程的起始时刻之后，且所述第二流程的起始时刻距离所述第M+1个Vsync周期的起始时刻的偏移时长与所述第三处理时长之和小于或等于所述第M+1个Vsync周期的时长；
所述运行单元1403，还用于在所述第M+1个Vsync周期中，在所述第二流程的起始时刻开始执行所述第二流程。
可选的，所述获取单元1401，还用于获取所述运行单元1403在所述第M个Vsync周期内执行所述器件显示流程的第二处理时长；
所述处理单元1402，具体用于：根据所述第二处理时长和所述第三处理时长，确定所述第M+1个Vsync周期内的所述第二流程的起始时刻，所述第二流程的起始时刻等于第二时刻或位于所述第二时刻之后，所述第二时刻为距离所述器件显示流程的起始时刻经过所述第二处理时长的时刻，且所述第二流程的起始时刻距离所述第M+1个Vsync周期的起始时刻的偏移时长与所述第三处理时长之和小于或等于所述第M+1个Vsync周期的时长。
可选的，所述处理单元1402还用于：
当确定的所述第一处理时长、所述第二处理时长以及所述第三处理时长的和，小于或等于所述第M+1个Vsync周期的时长时，设置所述第M+1个Vsync周期内的所述第一流程的起始时刻和所述第二流程的起始时刻满足以下条件：
所述第一流程的起始时刻与所述第二流程的起始时刻之间的时长，大于或等于所述第一处理时长或所述第三处理时长。
可选的，所述第一流程的起始时刻距离所述第M+1个Vsync周期的起始时刻的偏移时长与所述第一处理时长之和小于或等于所述第M+1个Vsync周期的时长与第一预设时长的差。
可选的，所述第二流程的起始时刻距离所述第M+1个Vsync周期的起始时刻的偏移时长与所述第三处理时长之和小于或等于所述第M+1个Vsync周期的时长与第二预设时长的差。
可选的，所述处理单元1402，还用于：
设置第M+P个Vsync周期内的所述第一流程的起始时刻为所述第M+P个Vsync周期的起始时刻，所述P为预设的大于1的正整数。
可选的，所述处理单元1402，还用于：
设置第M+Q个Vsync周期内的所述第二流程的起始时刻为所述第M+Q个Vsync周期的起始时刻，所述Q为预设的大于1的正整数。
采用本发明实施例提供的终端设备，所述终端设备获取在第M个Vsync周期内执行第一流程的第一处理时长后，根据所述第一处理时长确定第M+1个Vsync周期内的所述第一流程的起始时刻，所述第一流程为应用绘图流程或surfaceflinger合成流程，所述第M+1个Vsync周期内所述第一流程的起始时刻位于器件显示流程的起始时刻之后，且所述第一流程的起始时刻距离所述第M+1个Vsync周期的起始时刻的偏移时长与所述第一处理时长之和小于或等于所述第M+1个Vsync周期的时长；在所述第M+1个Vsync周期中，所述终端设备在所述器件显示流程的起始时刻开始执行所述器件显示流程，并在所述第一流程的起始时刻开始执行所述第一流程。这样，在所述第M+1个Vsync周期内，所述显示系统使应用绘图流程、surfaceflinger合成流程中的任一个流程，延迟执行，减少了所述终端设备在所述第M+1个Vsync周期内并行处理三个流程的时间，降低终端设备的CPU的功耗。
需要说明的是，本发明实施例中对单元的划分是示意性的，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式。在本申请的实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台终端设备(可以是个人计算机，手机，或者网络设备等)或处理器(processor)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read-Only Memory，简称ROM)、随机存取存储器(Random Access Memory，简称RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
基于以上实施例，本发明实施例还提供了一种终端设备，所述终端设备 用于在一个垂直同步Vsync周期内执行器件显示流程、应用绘图流程以及图层surfaceflinger合成流程，参阅图15所示，该终端设备1500包括：处理器1501、总线1502、存储器1503以及显示面板1504，其中，
所述处理器1501、所述存储器1503以及所述显示面板1504通过所述总线1502连接；总线1502可以是外设部件互连标准(peripheral component interconnect，简称PCI)总线或扩展工业标准结构(extended industry standard architecture，简称EISA)总线等。所述总线可以分为地址总线、数据总线、控制总线等。为便于表示，图15中仅用一条粗线表示，但并不表示仅有一根总线或一种类型的总线。
所述处理器1501，用于实现如图5所示的显示方法：包括：
获取所述处理器1501在第M个Vsync周期内执行第一流程的第一处理时长，所述第一流程为应用绘图流程或surfaceflinger合成流程，所述M为大于或等于1的正整数；
根据所述第一处理时长，确定第M+1个Vsync周期内的所述第一流程的起始时刻，所述第M+1个Vsync周期内，所述第一流程的起始时刻位于所述器件显示流程的起始时刻之后，且所述第一流程的起始时刻距离所述第M+1个Vsync周期的起始时刻的偏移时长与所述第一处理时长之和小于或等于所述第M+1个Vsync周期的时长；
在所述第M+1个Vsync周期中，在所述器件显示流程的起始时刻开始执行所述显示流程；在所述第一流程的起始时刻开始执行所述第一流程。
可选的，所述第M+1个Vsync周期内所述器件显示流程的起始时刻为所述M+1个Vsync周期的起始时刻。
可选的，所述处理器1501根据所述第一处理时长，确定所述第M+1个Vsync周期内的所述第一流程的起始时刻，包括：
获取所述处理器1501在所述第M个Vsync周期内执行所述器件显示流程的第二处理时长；
根据所述第一处理时长和所述第二处理时长，确定所述第M+1个Vsync 周期内的所述第一流程的起始时刻，所述第一流程的起始时刻等于第一时刻或位于所述第一时刻之后，所述第一时刻为距离所述器件显示流程的起始时刻经过所述第二处理时长的时刻，且所述第一流程的起始时刻距离所述第M+1个Vsync周期的起始时刻的偏移时长与所述第一处理时长之和小于或等于所述第M+1个Vsync周期的时长。
可选的，所述处理器1501还用于：
获取所述处理器1501在所述第M个Vsync周期内执行第二流程的第三处理时长，所述第二流程为应用绘图流程和surfaceflinger合成流程中除所述第一流程以外的其他流程；
根据所述第三处理时长，确定所述M+1个Vsync周期内的所述第二流程的起始时刻，所述第M+1个Vsync周期内所述第二流程的起始时刻位于所述器件显示流程的起始时刻之后，且所述第二流程的起始时刻距离所述第M+1个Vsync周期的起始时刻的偏移时长与所述第三处理时长之和小于或等于所述第M+1个Vsync周期的时长；
在所述第M+1个Vsync周期中，在所述第二流程的起始时刻开始执行所述第二流程。
可选的，根据所述第三处理时长，确定所述M+1个Vsync周期内的所述第二流程的起始时刻，包括：
获取所述处理器1501在所述第M个Vsync周期内执行所述器件显示流程的第二处理时长；
根据所述第二处理时长和所述第三处理时长，确定所述第M+1个Vsync周期内的所述第二流程的起始时刻，所述第二流程的起始时刻等于第二时刻或位于所述第二时刻之后，所述第二时刻为距离所述器件显示流程的起始时刻经过所述第二处理时长的时刻，且所述第二流程的起始时刻距离所述第M+1个Vsync周期的起始时刻的偏移时长与所述第三处理时长之和小于或等于所述第M+1个Vsync周期的时长。
可选的，当所述处理器1501确定的所述第一处理时长、所述第二处理时 长以及所述第三处理时长的和，小于或等于所述第M+1个Vsync周期的时长时，所述第一流程的起始时刻与所述第二流程的起始时刻之间的时长，大于或等于所述第一处理时长或所述第三处理时长。
可选的，所述第一流程的起始时刻距离所述第M+1个Vsync周期的起始时刻的偏移时长与所述第一处理时长之和小于或等于所述第M+1个Vsync周期的时长与第一预设时长的差。
可选的，所述第二流程的起始时刻距离所述第M+1个Vsync周期的起始时刻的偏移时长与所述第三处理时长之和小于或等于所述第M+1个Vsync周期的时长与第二预设时长的差。
可选的，所述处理器1501还用于：
设置第M+P个Vsync周期内的所述第一流程的起始时刻为所述第M+P个Vsync周期的起始时刻，所述P为预设的大于1的正整数。
可选的，所述处理器1501还用于：
设置第M+Q个Vsync周期内的所述第二流程的起始时刻为所述第M+Q个Vsync周期的起始时刻，所述Q为预设的大于1的正整数。
所述显示面板1504，用于所述处理器在每个Vsync周期内执行所述器件显示流程后，显示所述处理器执行所述器件显示流程生成的图像，所述显示面板1504可以采用LCD、OLED等形式来设置。
综上所述，通过本发明实施例中提供的一种显示方法及终端设备，所述终端设备的显示系统获取在第M个Vsync周期内执行第一流程的第一处理时长后，根据所述第一处理时长确定第M+1个Vsync周期内的所述第一流程的起始时刻，所述第一流程为应用绘图流程或surfaceflinger合成流程，所述第M+1个Vsync周期内所述第一流程的起始时刻位于器件显示流程的起始时刻之后，且所述第一流程的起始时刻距离所述第M+1个Vsync周期的起始时刻的偏移时长与所述第一处理时长之和小于或等于所述第M+1个Vsync周期的时长；在所述第M+1个Vsync周期中，所述显示系统在所述器件显示流程的起始时刻开始执行所述器件显示流程，并在所述第一流程的起始时刻开始执 行所述第一流程。这样，在所述第M+1个Vsync周期内，所述显示系统使应用绘图流程、surfaceflinger合成流程中的任一个流程，延迟执行，减少了所述终端设备的显示系统在所述第M+1个Vsync周期内并行处理三个流程的时间，降低终端设备的CPU的功耗。
本领域内的技术人员应明白，本发明的实施例可提供为方法、系统、或计算机程序产品。因此，本发明可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本发明可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本发明是参照根据本发明实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
尽管已描述了本发明的优选实施例，但本领域内的技术人员一旦得知了 基本创造性概念，则可对这些实施例做出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本发明范围的所有变更和修改。
显然，本领域的技术人员可以对本发明实施例进行各种改动和变型而不脱离本发明实施例的精神和范围。这样，倘若本发明实施例的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (21)

  1. 一种显示方法，其特征在于，所述方法用于终端设备的显示系统，所述显示系统用于在一个垂直同步Vsync周期内执行器件显示流程、应用绘图流程以及图层surfaceflinger合成流程，所述方法包括：
    所述显示系统获取所述显示系统在第M个Vsync周期内执行第一流程的第一处理时长，所述第一流程为应用绘图流程或surfaceflinger合成流程，所述M为大于或等于1的正整数；
    所述显示系统根据所述第一处理时长，确定第M+1个Vsync周期内的所述第一流程的起始时刻，所述第M+1个Vsync周期内，所述第一流程的起始时刻位于所述器件显示流程的起始时刻之后，且所述第一流程的起始时刻距离所述第M+1个Vsync周期的起始时刻的偏移时长与所述第一处理时长之和小于或等于所述第M+1个Vsync周期的时长；
    在所述第M+1个Vsync周期中，所述显示系统在所述器件显示流程的起始时刻开始执行所述显示流程；所述显示系统在所述第一流程的起始时刻开始执行所述第一流程。
  2. 如权利要求1所述的方法，其特征在于，所述第M+1个Vsync周期内所述器件显示流程的起始时刻为所述M+1个Vsync周期的起始时刻。
  3. 如权利要求1或2所述的方法，其特征在于，所述显示系统根据所述第一处理时长，确定所述第M+1个Vsync周期内的所述第一流程的起始时刻，包括：
    所述显示系统获取所述显示系统在所述第M个Vsync周期内执行所述器件显示流程的第二处理时长；
    所述显示系统根据所述第一处理时长和所述第二处理时长，确定所述第M+1个Vsync周期内的所述第一流程的起始时刻，所述第一流程的起始时刻等于第一时刻或位于所述第一时刻之后，所述第一时刻为距离所述器件显示流程的起始时刻经过所述第二处理时长的时刻，且所述第一流程的起始时刻 距离所述第M+1个Vsync周期的起始时刻的偏移时长与所述第一处理时长之和小于或等于所述第M+1个Vsync周期的时长。
  4. 如权利要求1-3任一项所述的方法，其特征在于，所述方法还包括：
    所述显示系统获取所述显示系统在所述第M个Vsync周期内执行第二流程的第三处理时长，所述第二流程为应用绘图流程和surfaceflinger合成流程中除所述第一流程以外的其他流程；
    所述显示系统根据所述第三处理时长，确定所述M+1个Vsync周期内的所述第二流程的起始时刻，所述第M+1个Vsync周期内所述第二流程的起始时刻位于所述器件显示流程的起始时刻之后，且所述第二流程的起始时刻距离所述第M+1个Vsync周期的起始时刻的偏移时长与所述第三处理时长之和小于或等于所述第M+1个Vsync周期的时长；
    在所述第M+1个Vsync周期中，所述显示系统在所述第二流程的起始时刻开始执行所述第二流程。
  5. 如权利要求4所述的方法，其特征在于，所述显示系统根据所述第三处理时长，确定所述M+1个Vsync周期内的所述第二流程的起始时刻，包括：
    所述显示系统获取所述显示系统在所述第M个Vsync周期内执行所述器件显示流程的第二处理时长；
    所述显示系统根据所述第二处理时长和所述第三处理时长，确定所述第M+1个Vsync周期内的所述第二流程的起始时刻，所述第二流程的起始时刻等于第二时刻或位于所述第二时刻之后，所述第二时刻为距离所述器件显示流程的起始时刻经过所述第二处理时长的时刻，且所述第二流程的起始时刻距离所述第M+1个Vsync周期的起始时刻的偏移时长与所述第三处理时长之和小于或等于所述第M+1个Vsync周期的时长。
  6. 如权利要求4或5所述的方法，其特征在于，当所述显示系统确定的所述第一处理时长、所述第二处理时长以及所述第三处理时长的和，小于或等于所述第M+1个Vsync周期的时长时，所述第一流程的起始时刻与所述第二流程的起始时刻之间的时长，大于或等于所述第一处理时长或所述第三处 理时长。
  7. 如权利要求1-6任一项所述的方法，其特征在于，所述第一流程的起始时刻距离所述第M+1个Vsync周期的起始时刻的偏移时长与所述第一处理时长之和小于或等于所述第M+1个Vsync周期的时长与第一预设时长的差。
  8. 如权利要求4-6任一项所述的方法，其特征在于，所述第二流程的起始时刻距离所述第M+1个Vsync周期的起始时刻的偏移时长与所述第三处理时长之和小于或等于所述第M+1个Vsync周期的时长与第二预设时长的差。
  9. 如权利要求1-8任一项所述的方法，其特征在于，所述方法还包括：
    所述显示系统设置第M+P个Vsync周期内的所述第一流程的起始时刻为所述第M+P个Vsync周期的起始时刻，所述P为预设的大于1的正整数。
  10. 如权利要求4-6,8任一项所述的方法，其特征在于，所述方法还包括：
    所述显示系统设置第M+Q个Vsync周期内的所述第二流程的起始时刻为所述第M+Q个Vsync周期的起始时刻，所述Q为预设的大于1的正整数。
  11. 一种终端设备，其特征在于，所述终端设备用于在一个垂直同步Vsync周期内执行器件显示流程、应用绘图流程以及图层surfaceflinger合成流程，所述终端设备包括：
    获取单元，用于获取运行单元在第M个Vsync周期内执行第一流程的第一处理时长，所述第一流程为应用绘图流程或surfaceflinger合成流程，所述M为大于或等于1的正整数；
    处理单元，用于根据所述第一处理时长，确定第M+1个Vsync周期内的所述第一流程的起始时刻，所述第M+1个Vsync周期内，所述第一流程的起始时刻位于所述器件显示流程的起始时刻之后，且所述第一流程的起始时刻距离所述第M+1个Vsync周期的起始时刻的偏移时长与所述第一处理时长之和小于或等于所述第M+1个Vsync周期的时长；
    运行单元，用于在所述第M+1个Vsync周期中，在所述器件显示流程的起始时刻开始执行所述显示流程；在所述第一流程的起始时刻开始执行所述第一流程。
  12. 如权利要求11所述的终端设备，其特征在于，所述第M+1个Vsync周期内所述器件显示流程的起始时刻为所述M+1个Vsync周期的起始时刻。
  13. 如权利要求11或12所述的终端设备，其特征在于，
    所述获取单元，还用于获取所述运行单元在所述第M个Vsync周期内执行所述器件显示流程的第二处理时长；
    所述处理单元，具体用于：根据所述第一处理时长和所述第二处理时长，确定所述第M+1个Vsync周期内的所述第一流程的起始时刻，所述第一流程的起始时刻等于第一时刻或位于所述第一时刻之后，所述第一时刻为距离所述器件显示流程的起始时刻经过所述第二处理时长的时刻，且所述第一流程的起始时刻距离所述第M+1个Vsync周期的起始时刻的偏移时长与所述第一处理时长之和小于或等于所述第M+1个Vsync周期的时长。
  14. 如权利要求11-13任一项所述的终端设备，其特征在于，
    所述获取单元，还用于获取所述运行单元在所述第M个Vsync周期内执行第二流程的第三处理时长，所述第二流程为应用绘图流程和surfaceflinger合成流程中除所述第一流程以外的其他流程；
    所述处理单元，还用于根据所述第三处理时长，确定所述M+1个Vsync周期内的所述第二流程的起始时刻，所述第M+1个Vsync周期内所述第二流程的起始时刻位于所述器件显示流程的起始时刻之后，且所述第二流程的起始时刻距离所述第M+1个Vsync周期的起始时刻的偏移时长与所述第三处理时长之和小于或等于所述第M+1个Vsync周期的时长；
    所述运行单元，还用于在所述第M+1个Vsync周期中，在所述第二流程的起始时刻开始执行所述第二流程。
  15. 如权利要求14所述的终端设备，其特征在于，
    所述获取单元，还用于获取所述运行单元在所述第M个Vsync周期内执行所述器件显示流程的第二处理时长；
    所述处理单元，具体用于：根据所述第二处理时长和所述第三处理时长，确定所述第M+1个Vsync周期内的所述第二流程的起始时刻，所述第二流程 的起始时刻等于第二时刻或位于所述第二时刻之后，所述第二时刻为距离所述器件显示流程的起始时刻经过所述第二处理时长的时刻，且所述第二流程的起始时刻距离所述第M+1个Vsync周期的起始时刻的偏移时长与所述第三处理时长之和小于或等于所述第M+1个Vsync周期的时长。
  16. 如权利要求14或15所述的终端设备，其特征在于，所述处理单元还用于：
    当确定的所述第一处理时长、所述第二处理时长以及所述第三处理时长的和，小于或等于所述第M+1个Vsync周期的时长时，设置所述第M+1个Vsync周期内的所述第一流程的起始时刻和所述第二流程的起始时刻满足以下条件：
    所述第一流程的起始时刻与所述第二流程的起始时刻之间的时长，大于或等于所述第一处理时长或所述第三处理时长。
  17. 如权利要求11-16任一项所述的终端设备，其特征在于，所述第一流程的起始时刻距离所述第M+1个Vsync周期的起始时刻的偏移时长与所述第一处理时长之和小于或等于所述第M+1个Vsync周期的时长与第一预设时长的差。
  18. 如权利要求14-16任一项所述的终端设备，其特征在于，所述第二流程的起始时刻距离所述第M+1个Vsync周期的起始时刻的偏移时长与所述第三处理时长之和小于或等于所述第M+1个Vsync周期的时长与第二预设时长的差。
  19. 如权利要求11-18任一项所述的终端设备，其特征在于，所述处理单元，还用于：
    设置第M+P个Vsync周期内的所述第一流程的起始时刻为所述第M+P个Vsync周期的起始时刻，所述P为预设的大于1的正整数。
  20. 如权利要求14-16,18任一项所述的终端设备，其特征在于，所述处理单元，还用于：
    设置第M+Q个Vsync周期内的所述第二流程的起始时刻为所述第M+Q 个Vsync周期的起始时刻，所述Q为预设的大于1的正整数。
  21. 一种终端设备，其特征在于，所述终端设备用于在一个垂直同步Vsync周期内执行器件显示流程、应用绘图流程以及图层surfaceflinger合成流程，所述终端设备包括：处理器、总线、存储器以及显示面板，所述处理器、所述存储器以及所述显示面板通过所述总线连接；
    所述处理器调用所述存储器中的指令，执行如权利要求1-10任一项所述的方法；
    所述显示面板，用于所述处理器在每个Vsync周期内执行所述器件显示流程后，显示所述处理器执行所述器件显示流程生成的图像。
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