WO2017152412A1 - 支持多时钟域时钟传递的设备和方法 - Google Patents

支持多时钟域时钟传递的设备和方法 Download PDF

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Publication number
WO2017152412A1
WO2017152412A1 PCT/CN2016/076106 CN2016076106W WO2017152412A1 WO 2017152412 A1 WO2017152412 A1 WO 2017152412A1 CN 2016076106 W CN2016076106 W CN 2016076106W WO 2017152412 A1 WO2017152412 A1 WO 2017152412A1
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Prior art keywords
clock
ith
difference information
phase
filter
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PCT/CN2016/076106
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English (en)
French (fr)
Inventor
王锦辉
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Priority to CN201680001517.XA priority Critical patent/CN107925559B/zh
Priority to CN202010404363.7A priority patent/CN111934803B/zh
Priority to EP16893063.4A priority patent/EP3404866B1/en
Priority to PCT/CN2016/076106 priority patent/WO2017152412A1/zh
Publication of WO2017152412A1 publication Critical patent/WO2017152412A1/zh
Priority to US16/107,300 priority patent/US10250377B2/en
Anticipated expiration legal-status Critical
Priority to US16/265,617 priority patent/US10476657B2/en
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0644—External master-clock
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H04L7/0087—Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/22—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/06—Speed or phase control by synchronisation signals the synchronisation signals differing from the information signals in amplitude, polarity or frequency or length
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H04J3/0688—Change of the master or reference, e.g. take-over or failure of the master
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H04J3/0691—Synchronisation in a TDM node
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H04J3/0697—Synchronisation in a packet node

Definitions

  • the present application relates to the field of communication technologies, and in particular, to an apparatus and method for supporting multiple clock domains clock transmission.
  • the original fixed network service is carried by a Synchronous Digital Hierarchy (SDH) device.
  • the newly created mobile service is carried by an Internet Protocol (IP) device.
  • IP Internet Protocol
  • SDH Synchronous Digital Hierarchy
  • IP Internet Protocol
  • LTE-A Long Term Evolution-Advanced
  • LTE-A Long Term Evolution-Advanced
  • LTE-A Long Term Evolution-Advanced
  • the mobile service requires hybrid service bearer equipment to carry synchronous Ethernet and 1588v2 clocks, which can be obtained from the Global Navigation Satellite System (GNSS). Get frequency synchronization and time synchronization.
  • GNSS Global Navigation Satellite System
  • hybrid service bearer equipment may also need to support the evolution to a more accurate synchronization network in the future.
  • Different sync networks may have different precisions and different clock sources.
  • the hybrid service bearer can only transmit the data of multiple different services to the corresponding device separately, and cannot simultaneously transmit the clock signals generated by the clock sources of multiple different services.
  • the demand for network devices to support multiple different clock domains is becoming more and more common.
  • the International Telecommunication Union Telecommunication Standardization Sector (ITU-T) defines reference models for various synchronous network devices, but does not define how to use the same device to simultaneously carry clock signals of multiple different clock domains.
  • the embodiments of the present application provide an apparatus and method for supporting multi-clock domain clock transmission, which can simultaneously support clock transmission of multiple different clock domains by using the same device.
  • a device that supports multi-clock domain clock delivery comprises: N phase frequency detectors, N filters, N clock reconstructors and N clock domain interfaces.
  • the N is an integer greater than or equal to 2.
  • the N clock domain interfaces and the N The phase frequency detector, the N filters, and the N clock reconstructors are in one-to-one correspondence.
  • the N phase frequency detectors are respectively connected to N clock sources, and at least two clock sources of the N clock sources are different.
  • the i-th phase frequency detector in the N phase frequency detectors is configured to receive a clock signal generated by a clock source connected to the ith phase frequency detector, and determine an ith between the common clock signal and the clock signal Phase difference information, and transmitting the ith phase difference information to an ith filter of the N filters corresponding to the ith phase frequency detector.
  • the ith filter is configured to receive the ith phase difference information sent by the ith phase frequency detector, convert the ith phase difference information into an ith frequency difference information, and reconstruct the N clocks
  • the ith clock reconstructor corresponding to the ith filter transmits the ith frequency difference information.
  • the ith clock reconstructor is configured to receive the ith frequency difference information sent by the ith filter, and reconstruct an ith network timing clock in the device according to the common clock signal and the ith frequency difference information. And transmitting the ith network timing clock to the i-th clock domain interface of the N clock domain interfaces.
  • i is an integer and satisfies 1 ⁇ i ⁇ N.
  • the internal clock signal is still transmitted internally by the device, but is reconstructed by the clock at each clock source interface.
  • the clock signals of different clock domains are reconstructed and sent to other clock domain interfaces of the clock domain to further implement network level clock synchronization.
  • the above device realizes clock transmission in multiple clock domains by extracting the difference between the clock signal of different clock sources and the common clock.
  • the device supporting the multi-clock domain clock transmission in the embodiment of the present application obtains the phase difference information between the clock signal generated by the clock source of each clock domain and the common clock signal through the phase frequency detector, and then the phase difference is passed through the filter. The value information is converted into the frequency difference information, and finally the clock signal of the clock domain required by the clock reconstructor is synthesized and applied to the clock domain interface of each clock domain, thereby flexibly adapting multiple different clock domains to realize a single device. It also supports multi-clock domain clock transmission. It does not need to add or replace devices, and can flexibly meet the needs of users.
  • the N phase frequency detectors can be a dual D digital phase detector or a time-to-digital converter (TDC).
  • TDC time-to-digital converter
  • the N filters may be composed of a digital filtering module and a conversion module, respectively.
  • the digital filtering module can adopt a universal 7-order finite impulse response (Finite Impulse Response, FIR) Filter module.
  • FIR Finite Impulse Response
  • the N clock reconstructors may be a Direct Digital Frequency Synthesis (DDS) or a Number Controlled Oscillator (NCO).
  • DDS Direct Digital Frequency Synthesis
  • NCO Number Controlled Oscillator
  • phase difference information and the frequency difference information may be encapsulated into a Layer 2 Ethernet message.
  • the device further includes: an (N+1) phase frequency detector and an external synchronization interface, wherein the (N+1) phase frequency detector passes the The sync interface is connected to an external clock source.
  • the N+1th phase frequency detector is configured to receive a clock signal generated by the external clock source, determine an N+1th phase difference information between the clock signal generated by the external clock source and the common clock signal, and The jth filter of the N filters transmits the N+1th phase difference information.
  • the jth filter is configured to receive the (N+1)th phase difference information sent by the (N+1)th phase frequency detector, and convert the N+1th phase difference information into the N+1th frequency difference information. And transmitting the (N+1)th frequency difference information to the jth clock reconstructor corresponding to the jth filter among the N clock reconstructors.
  • the jth clock reconstructor is configured to receive the N+1th frequency difference information sent by the jth filter, and reconstruct the Nth in the device according to the common clock signal and the (N+1)th frequency difference information. +1 a network timing clock, and transmitting the N+1th network timing clock to a jth clock domain interface of the N clock domain interfaces.
  • j is an integer and satisfies 1 ⁇ j ⁇ N.
  • the device can receive and reconstruct the clock signal from the external synchronization interface while supporting the clock signal transmission of multiple different clock domains, and ensure that each clock domain interface of the device can receive the clock signal of the external synchronization interface as needed.
  • each clock domain interface can use the clock signal of the external synchronization interface as its own network timing clock, thereby improving the accuracy of the clock signal in the device. .
  • the device further includes: an (N+1)th clock reconstructor.
  • the kth filter of the N filters is further configured to send the kth frequency difference information generated by the kth filter to the (N+1)th clock reconstructor.
  • the N+1th clock reconstructor is configured to receive the kth frequency difference value sent by the kth filter And, according to the kth frequency difference information, reconstructing a kth network timing clock in the device, and transmitting the kth network timing clock to the external synchronization interface.
  • k is an integer and satisfies 1 ⁇ k ⁇ N.
  • the clock signals from multiple different clock domains can be transmitted not only in the various clock domain interfaces of the device, but also can be transmitted to other devices connected to the device through the external synchronization interface, thereby implementing the internal clock of the device. Signal performance test.
  • the device further includes: an input selector.
  • the i-th phase frequency detector is specifically used for:
  • the i-th phase difference information is transmitted to the input selector.
  • the input selector is configured to receive the ith phase difference information sent by the ith phase frequency detector, and based on the correspondence between the ith phase frequency detector and the ith filter, to the ith filter Sending the i-th phase difference information.
  • the input selector is further configured to:
  • the clock sources of the N clock domain interfaces correspond to the M types of services, selecting M phase difference information, the M phase difference information, and the phase difference information sent by the N phase frequency detectors
  • the M types of services are in one-to-one correspondence, and based on the correspondence between the N phase discriminators and the N filters, corresponding phase difference information is transmitted to each of the N filters, where M is an integer less than N.
  • the N services corresponding to the N clock domain interfaces include the same service
  • the same service is divided into one type of service, so the N services include the M types of services.
  • the input selector can perform source selection operation on the phase difference information of the clock sources from the N services, and select M phase difference information corresponding to the M services from the N phase difference information corresponding to the N services.
  • the same kind of traffic in N services tracks the optimal clock source in this category.
  • the input selector may be implemented in the device by using a software of a Central Processing Unit (CPU) or by Field-Programmable Gate Array (FPGA) hardware. This embodiment of the present application does not limit this.
  • CPU Central Processing Unit
  • FPGA Field-Programmable Gate Array
  • the device further includes: an output selector.
  • the ith filter is specifically used to:
  • the ith frequency difference information is transmitted to the output selector.
  • the output selector is configured to receive the ith frequency difference information sent by the ith filter, and send the ith clock reconstructor to the ith clock reconstructor based on a correspondence between the ith filter and the ith clock reconstructor The i-th frequency difference information.
  • the output selector may be implemented in the device by using the software of the CPU of the central processing unit or the hardware of the field programmable gate array (FPGA), which is not limited by the embodiment of the present application.
  • FPGA field programmable gate array
  • the device further includes:
  • a common clock generator for generating the common clock signal before determining the ith phase difference information between the common clock signal and the clock signal, and focusing on the ith phase frequency detector and the ith clock
  • the constructor sends the common clock signal.
  • a method for supporting multi-clock domain clock delivery comprising:
  • the ith phase discriminator in the N phase frequency detectors receives a clock signal generated by a clock source connected to the ith phase frequency detector, and determines an ith phase difference between the common clock signal and the clock signal Value information, and transmitting the ith phase difference information to an ith filter of the N filters corresponding to the ith phase frequency detector.
  • the ith filter receives the ith phase difference information sent by the ith phase frequency detector, converts the ith phase difference information into ith frequency difference information, and sends the ith phase difference information to the N clock reconstructors.
  • the ith clock reconstructor corresponding to the ith filter transmits the ith frequency difference information.
  • the ith clock reconstructor receives the ith frequency difference information sent by the ith filter, and reconstructs an ith network timing clock in the device according to the common clock signal and the ith frequency difference information, and The i-th network timing clock is sent to the i-th clock domain interface of the N clock domain interfaces.
  • the N is an integer greater than or equal to 2, and the N clock domain interfaces are respectively corresponding to the N phase frequency detectors, the N filters, and the N clock reconstructors.
  • the frequency phase detectors are respectively connected to the N clock sources, and at least two of the N clock sources are different, and the i is an integer and satisfies 1 ⁇ i ⁇ N.
  • the method further includes:
  • the N+1th phase frequency detector receives the clock signal generated by the external clock source, determines the N+1th phase difference information between the clock signal generated by the external clock source and the common clock signal, and The jth filter of the N filters transmits the N+1th phase difference information.
  • the jth filter receives the N+1th phase difference information sent by the (N+1)th phase frequency detector, and converts the N+1th phase difference information into the N+1th frequency difference information, And transmitting the (N+1)th frequency difference information to the jth clock reconstructor corresponding to the jth filter in the N clock reconstructors.
  • the jth clock reconstructor receives the N+1th frequency difference information sent by the jth filter, and reconstructs the N+ in the device according to the common clock signal and the (N+1)th frequency difference information. 1 a network timing clock, and transmitting the (N+1)th network timing clock to a jth clock domain interface of the N clock domain interfaces.
  • the N+1th phase frequency detector is connected to the external clock source through an external synchronization interface, where j is an integer and satisfies 1 ⁇ j ⁇ N.
  • the method further includes:
  • the kth filter of the N filters transmits the kth frequency difference information generated by the kth filter to the (N+1)th clock reconstructor.
  • the N+1th clock reconstructor receives the kth frequency difference information sent by the kth filter, and reconstructs a kth network timing clock in the device according to the kth frequency difference information, and
  • the external synchronization interface transmits the kth network timing clock, where k is an integer and satisfies 1 ⁇ k ⁇ N.
  • the ith filter corresponding to the ith phase frequency detector is sent to the N filters
  • the i-th phase difference information includes:
  • the ith phase frequency detector sends the ith phase difference information to the input selector.
  • the input selector receives the ith phase difference information sent by the ith phase frequency detector, and sends the ith filter to the ith filter based on the correspondence between the ith phase frequency detector and the ith filter The i-th phase difference information.
  • the input selector receives the ith phase difference information sent by the ith phase frequency detector
  • the method also includes:
  • the input selector selects M phase difference information from the phase difference information sent by the N phase frequency detectors, and the M phase differences
  • the value information is in one-to-one correspondence with the M types of services.
  • Transmitting the ith phase difference value information to the ith filter includes:
  • Corresponding phase difference information is transmitted to each of the N filters based on the correspondence between the N phase discriminators and the N filters.
  • the ith clock reconstructor corresponding to the ith filter in the N clock reconstructors is sent
  • the ith frequency difference information includes:
  • the ith filter transmits the ith frequency difference information to an output selector.
  • the output selector receives the ith frequency difference information sent by the ith filter, and sends the ith to the ith clock reconstructor based on the correspondence between the ith filter and the ith clock reconstructor Frequency difference information.
  • the method before the determining the ith phase difference information between the common clock signal and the clock signal, the method further includes :
  • the common clock generator generates the common clock signal and transmits the common clock signal to the ith phase discriminator and the ith clock reconstructor.
  • the method of the second aspect may be performed by the apparatus of the first aspect or any of the possible implementations of the first aspect.
  • a computer readable medium for storing a computer program comprising instructions for performing the method of any of the second aspect or any of the possible implementations of the second aspect.
  • FIG. 1 is a schematic diagram of an application scenario of an embodiment of the present application.
  • FIG. 2 is a schematic block diagram of an apparatus for supporting multi-clock domain clock delivery provided by an embodiment of the present application.
  • FIG. 3 is a schematic diagram of another apparatus for supporting multi-clock domain clock transmission provided by an embodiment of the present application; FIG. block diagram.
  • FIG. 4 is a schematic block diagram of another apparatus for supporting multi-clock domain clock delivery according to an embodiment of the present application.
  • FIG. 5 is a schematic block diagram of a method for supporting multi-clock domain clock delivery provided by an embodiment of the present application.
  • Embodiments of the present application are applicable to various communication systems. Therefore, the application scenario of the technical solution provided by the embodiment of the present application is not limited to a specific communication system.
  • the communication system used in the application scenario of the technical solution may be a Global System of Mobile communication (GSM) system, a Code Division Multiple Access (CDMA) system, or a Wideband Code Division Multiple Access (Wideband Code Division Multiple Access).
  • GSM Global System of Mobile communication
  • CDMA Code Division Multiple Access
  • Wideband Code Division Multiple Access Wideband Code Division Multiple Access
  • WCDMA Wideband Code Division Multiple Access
  • GPRS General Packet Radio Service
  • LTE Long Term Evolution
  • FDD Frequency Division Duplex
  • TDD Time Division duplex
  • UMTS Universal Mobile Telecommunication System
  • the device in the embodiment of the present application may be a network device, or may be a terminal device, and may be other transmission nodes, which is not limited in this embodiment of the present application.
  • the network device may include a base station and a base station controller.
  • the base station may be a device for communicating with the terminal device.
  • the base station may be a base station (Base Transceiver Station, BTS) in the GSM system or CDMA, or may be a base station (Node B, NB) in the WCDMA system, or may be an evolved base station (Evolutional Node B in the LTE system).
  • BTS Base Transceiver Station
  • Node B, NB base station
  • Evolutional Node B in the LTE system
  • eNB or eNodeB evolved base station
  • the base station may be a relay station, an access point, an in-vehicle device, or a network side device in a future 5G network.
  • the base station controller can schedule traffic between the base stations through the transmission node.
  • the transport node may be an Ethernet switch, an IP router, a Packet Transport Network (PTN), a Microwave device, or an Optical Transport Network (OTN).
  • the terminal device can refer to an access terminal, a user equipment (User Equipment, UE), a subscriber unit, a subscriber station, a mobile station, a mobile station, and a far end. Square station, remote terminal, mobile device, user terminal, terminal, wireless communication device, user agent or user device.
  • the access terminal may be a cellular phone, a cordless phone, a Session Initiation Protocol (SIP) phone, a Wireless Local Loop (WLL) station, a Personal Digital Assistant (PDA), with wireless communication.
  • PLMN Public Land Mobile Network
  • FIG. 1 is a schematic diagram of an application scenario of an embodiment of the present application.
  • the application scenarios shown in FIG. 1 include clock source A, clock source B, device A, device B, device C, device D, and device E.
  • the clock source A and the clock source B are clock sources of two different services.
  • the clock source of device A is clock source A.
  • the clock source of device B is clock source B.
  • the service data packets carried by the device A and the device B are simultaneously delivered to the device C.
  • the device C then transmits the service data packet of the device A to the device D, and the service data packet of the device B is transmitted to the device E.
  • the architecture carries two different services, namely two synchronous networks, so device C can be called a hybrid service bearer.
  • FIG. 1 only exemplarily shows an application scenario including two clock sources.
  • the system may further include more clock sources and more devices, which is not limited in this embodiment of the present application.
  • FIG. 2 is a schematic block diagram of an apparatus 100 for supporting multi-clock domain clock delivery provided by an embodiment of the present application, and the apparatus 100 may correspond to the hybrid service carrying apparatus C in FIG. 1 .
  • the device 100 includes: N clock domain interfaces (including a first clock domain interface 101 to an Nth clock domain interface 102), and N phase frequency detectors (including a first phase frequency detector 103 to an Nth frequency detector).
  • the phaser 104 N filters (including the first filter 105 to the Nth filter 106), and N clock reconstructors (including the first clock reconstructor 107 to the Nth clock reconstructor 108).
  • the N is an integer greater than or equal to 2.
  • the N clock domain interfaces are respectively in one-to-one correspondence with the N phase frequency detectors, the N filters, and the N clock reconstructors.
  • the N phase frequency detectors are respectively connected to N clock sources, and at least two clock sources of the N clock sources are different.
  • the i-th phase frequency detector in the N phase frequency detectors is configured to receive a clock signal generated by a clock source connected to the ith phase frequency detector, and determine an ith between the common clock signal and the clock signal Phase difference information, and transmitting the ith phase difference information to an ith filter of the N filters corresponding to the ith phase frequency detector.
  • common clock signal described above may be generated by a common clock generator for transmission to various phase frequency detectors and respective clock reconstructors within device 100 over the bus.
  • common clock signal there is one and only one common clock signal in one device.
  • the ith filter is configured to receive the ith phase difference information sent by the ith phase frequency detector, convert the ith phase difference information into an ith frequency difference information, and reconstruct the N clocks
  • the ith clock reconstructor corresponding to the ith filter transmits the ith frequency difference information.
  • the ith clock reconstructor is configured to receive the ith frequency difference information sent by the ith filter, and reconstruct an ith network timing clock in the device according to the common clock signal and the ith frequency difference information. And transmitting the ith network timing clock to the i-th clock domain interface of the N clock domain interfaces.
  • i is an integer and satisfies 1 ⁇ i ⁇ N.
  • the N clock domain interfaces of the device are respectively in one-to-one correspondence with N phase frequency detectors, N filters, and N clock reconstructors inside the device.
  • the first clock domain interface 101 corresponds to the first phase frequency detector 103
  • the first filter 105 corresponds to the first clock reconstructor 107
  • the Nth clock domain interface 102 corresponds to the Nth phase frequency detector 104.
  • the Nth filter 106 and the Nth clock reconstructor 108 can independently process clock signals from N clock domain interfaces.
  • the N phase frequency detectors are respectively connected to the N clock sources, and at least two of the N clock sources are different.
  • one clock domain interface has only one clock source, and one clock source can be connected to multiple clock domain interfaces at the same time to provide a clock signal. Therefore, the clock signals from the N clock domain interfaces in the embodiment of the present application may be all different, or may be partially the same, that is, the same clock signal is from the same clock source, which is not limited in this embodiment of the present application.
  • each of the N phase discriminators can receive a common clock signal and a clock signal generated by a clock source of a clock domain interface corresponding to each of the phase frequency detectors. And determining phase difference information between the common clock signal and a clock signal generated by a clock source of the clock domain interface corresponding to each of the phase frequency detectors, so that the N phase frequency detectors can determine N Phase difference information.
  • the N phase frequency detectors respectively send corresponding phase difference information to the respective corresponding filters, and after the N filters receive the respective phase difference information, respectively convert the phase difference information into frequency difference information. And then sent to their respective clock reconstructors. After the N clock reconstructors receive the respective frequency difference information, they can use the common clock signal and the received frequency difference. The value information is used to reconstruct the network timing clocks of the corresponding clock domain interfaces, and finally send them to the corresponding clock domain interfaces.
  • the above network timing clock should be understood as the same frequency signal after the clock signal of the clock source is filtered.
  • the purpose of the network element timing itself is to filter the reference source input from an interface and distribute it to other interfaces in the clock domain to achieve network level synchronization.
  • the embodiment of the present application first calculates phase difference information between a clock signal and a common clock signal from different clock domains, and converts the phase difference information into frequency difference information. Then, at each clock source interface, the clock reconstructor reconstructs the clock signal of the required clock domain according to the common clock signal. After receiving the clock signals of a plurality of different clock sources, the internal clock signal is still transmitted by the device, but the clock signals of different clock domains are reconstructed by the clock reconstructor at each clock source interface, and then sent separately. Other clock domain interfaces of the clock domain are further implemented to implement network level clock synchronization. The above device realizes clock transmission in multiple clock domains by extracting the difference between the clock signal of different clock sources and the common clock.
  • the device supporting the multi-clock domain clock transmission in the embodiment of the present application acquires the phase difference information between the clock signal generated by the clock source of each clock domain interface and the common clock signal through the phase frequency detector, and then passes the phase through the filter.
  • the difference information is converted into frequency difference information, and finally the clock signal of the clock domain required by the clock reconstructor is synthesized and applied to the clock domain interface of each clock domain, thereby flexibly adapting multiple different clock domains to achieve a single
  • the device supports multi-clock domain clock transmission at the same time. It does not need to add or replace devices, and can flexibly meet the needs of users.
  • the clock signals of the above N clock domains are also transmitted independently of each other.
  • the transmission of the clock signals of the N clock domains may be serial or parallel, which is not limited in the embodiment of the present application.
  • the phase frequency detector can compare the phases of the rising edge (ie, the first clock edge) of the two clock signals through the logic circuit to obtain the phase difference signal, and then obtain the phase difference signal.
  • the phase difference signal is sample-quantized by the high-frequency clock signal to obtain phase difference information and output, and the phase difference information is a digital quantity.
  • a Phase Frequency Detector may be a dual D digital phase detector or a Time-to-Digital Converter (TDC).
  • the filter is mainly composed of a digital filter module and a conversion module.
  • the digital filtering module can adopt a universal 7-order Finite Impulse Response (FIR) filtering module.
  • the filter takes the phase difference information as an input, and the digital filter module performs low on the phase difference information After filtering, the converted phase difference information is integrated by the conversion module to obtain frequency difference information.
  • the final filter takes this frequency difference information as an output.
  • the filter may be an Ethernet Equipment Clock (EEC) filter, a Synchronous Digital Hierarchy Equipment Clock (SEC) filter, or an optical transport network device clock (Optical Transport). Network Equipment Clock, OEC) filter, determined by the type of business.
  • the filter can be implemented by a digital signal processing (DSP) using a common Finite Impulse Response (FIR) structure. This embodiment of the present application does not limit this.
  • the clock reconstructor can be a Direct Digital Frequency Synthesis (DDS) or a Number Controlled Oscillator (NCO). This embodiment of the present application does not limit this.
  • DDS Direct Digital Frequency Synthesis
  • NCO Number Controlled Oscillator
  • the phase difference information and the frequency difference information may be encapsulated in a message for transmission.
  • the packet may be an Ethernet packet, or may be a packet encapsulated by a High-Level Data Link (HDLC) or a Generic Framing Procedure (GFP).
  • the phase difference information and the frequency difference information may be encapsulated in a packet carrying a virtual local area network (VLAN) label or a multi-protocol label switching (MPLS) label. This is not limited.
  • VLAN virtual local area network
  • MPLS multi-protocol label switching
  • the encapsulation of the phase difference information and the frequency difference information may be a two-layer encapsulation or a three-layer encapsulation, which is not limited in this embodiment of the present application. Whether to use a two-layer package or a three-layer package depends on the forwarding technology. If Layer 2 forwarding is used, a Layer 2 encapsulation is required. If Layer 3 forwarding is used, a Layer 3 encapsulation is required. It should be understood that the "layer” herein refers to the hierarchy in the Transmission Control Protocol/Internet Protocol (TCP/IP), the second layer is the data link layer, and the third layer is the network layer. Layered message forwarding, different addressing modes, the second layer is addressed by Media Access Control (MAC) address, and the third layer is addressed by Internet Protocol (IP) address.
  • TCP/IP Transmission Control Protocol/Internet Protocol
  • MAC Media Access Control
  • IP Internet Protocol
  • the encapsulation of the phase difference information and the frequency difference information may also adopt a frame structure in a Time Division Multiplexing (TDM) mode, and a frame structure in an Asynchronous Transfer Mode (ATM).
  • TDM Time Division Multiplexing
  • ATM Asynchronous Transfer Mode
  • VC-4 virtual container 4
  • OTN optical transport network
  • GFP GFP
  • STM Synchronous Transfer Mode
  • the internal system of the above device can be implemented by inserting a plurality of boards on a common backplane. Management and configuration channels are also required between different boards.
  • 100M Ethernet or 1G Ethernet is often used to implement communication within the device.
  • the transmission path of the phase difference information and the frequency difference information is a system bus, which may include, but is not limited to, a Fast Ethernet (FE)/Gigabit Ethernet (GE) interface in the system.
  • FE Fast Ethernet
  • GE gigabit Ethernet
  • a common form such as a local bus, an Inter-Integrated Circuit (I2C) bus, a Serial Peripheral Interface (SPI) bus, and a High Level Data Link Control (HDLC) bus. This embodiment of the present application does not limit this.
  • the device further includes: an N+1th phase frequency detector and an external synchronization interface, wherein the (N+1) phase frequency detector passes the external synchronization interface and an external clock source connection.
  • the external synchronization interface is a device interface that does not carry a service and only carries a clock signal. If the interface is connected to a high-precision clock source, the interface can be used as a signal of the network timing clock of the internal clock domain of the device. If the interface is connected to the test device, the interface can be used to extract a certain The clock signal of the clock domain observes the performance of the clock signal.
  • the external clock source is to be understood as a clock source connected to the external synchronization interface.
  • the clock source may be one of the above-mentioned N clock sources, or may be other clock sources, which is not limited in this embodiment of the present application.
  • the N+1th phase frequency detector is configured to receive a clock signal generated by the external clock source, determine an N+1th phase difference information between the clock signal generated by the external clock source and the common clock signal, and The jth filter of the N filters transmits the N+1th phase difference information.
  • the jth filter is configured to receive the (N+1)th phase difference information sent by the (N+1)th phase frequency detector, and convert the N+1th phase difference information into the N+1th frequency difference information. And transmitting the (N+1)th frequency difference information to the jth clock reconstructor corresponding to the jth filter among the N clock reconstructors.
  • the jth clock reconstructor is configured to receive the N+1th frequency difference information sent by the jth filter, and reconstruct the Nth in the device according to the common clock signal and the (N+1)th frequency difference information. +1 a network timing clock, and transmitting the N+1th network timing clock to a jth clock domain interface of the N clock domain interfaces.
  • j is an integer and satisfies 1 ⁇ j ⁇ N.
  • j and i may be equal or not equal, which is not limited by the embodiment of the present application.
  • the device further includes an N+1th phase frequency detector and an external synchronization interface, and can transmit a clock signal from the external synchronization interface.
  • the N+1 phase frequency detector receives a clock signal generated by an external clock source connected to the external synchronization interface, and determines an N+1th phase difference between the clock signal generated by the clock source of the external synchronization interface and the common clock signal.
  • the value information is sent to the jth filter of the above N filters.
  • the jth filter converts the (N+1)th phase difference information into the (N+1)th frequency difference information, and sends the (N+1)th frequency difference information to the Nth clock reconstructor and the jth filter Corresponding jth clock reconstructor, the jth clock reconstructor can reconstruct a network timing clock of the external synchronization interface in the device, and send it to the N clock domain interfaces and the jth clock reconstructor Corresponding clock domain interface.
  • the (N+1) phase frequency detector can transmit phase difference information according to the needs of the clock domain interface.
  • Any clock synchronization of the synchronous network may acquire the clock signal of the external synchronization source through the external synchronization interface, so any filter can process the phase difference information between the clock source of the external synchronization interface and the common clock.
  • the N+1 phase frequency detector can transmit the generated N+1th phase difference information to the corresponding filter according to the needs of the clock domain interface.
  • the device can receive and reconstruct the clock signal from the external synchronization interface while supporting the clock signal transmission of multiple different clock domains, and ensure that each clock domain interface of the device can receive the clock signal of the external synchronization interface as needed.
  • each clock domain interface can use the clock signal of the external synchronization interface as its own network timing clock, thereby improving the accuracy of the clock signal in the device. .
  • the device further includes: an N+1th clock reconstructor.
  • the kth filter of the N filters is further configured to send the kth frequency difference information generated by the kth filter to the (N+1)th clock reconstructor.
  • the N+1th clock reconstructor is configured to receive the kth frequency difference information sent by the kth filter, and reconstruct a kth network timing clock in the device according to the kth frequency difference information, and The external synchronization interface transmits the kth network timing clock.
  • k is an integer and satisfies 1 ⁇ k ⁇ N.
  • k and i may be equal or unequal, and k and j may be equal or not equal, which is not limited in the embodiment of the present application.
  • the user can be used to test the performance of the clock signal inside the device as needed. Specifically, when the device is docked with another device, it is necessary to test the performance of the clock signal inside the device. Alternatively, connect the device directly using a test device (for example, a meter). Then, The device needs to output a clock signal from a multi-clock domain inside the device through an external synchronization interface, or output any one of the clock signals according to the needs of the user. After learning the network timing clock of which clock domain interface is tested, the device sends the filter corresponding to the tested clock domain interface (ie, the kth filter) to the N+1th clock reconstructor.
  • a test device for example, a meter
  • the kth frequency difference information between the tested clock domain interface and the common clock signal, the corresponding kth network timing clock is reconstructed by the N+1th clock reconstructor, and sent to the external synchronization interface .
  • the above-mentioned docking device or test device can obtain different clock signals of the device through the external synchronization interface, and test the performance of the clock signal inside the device.
  • test device or the docking device may select a clock source of a specific clock domain interface of the N clock domain interfaces as required, or sequentially connect each clock domain interface of the N clock domain interfaces.
  • the clock source is tested, and the embodiment of the present application does not limit this.
  • clock signals from multiple different clock domains can be transmitted not only in the various clock domain interfaces of the device, but also can be transmitted to other devices connected to the device through the external synchronization interface, thereby implementing the device. Test of internal clock signal performance.
  • the device further includes an input selector 109.
  • the i-th phase frequency detector is specifically used for:
  • the i-th phase difference information is transmitted to the input selector.
  • the input selector is configured to receive the ith phase difference information sent by the ith phase frequency detector, and based on the correspondence between the ith phase frequency detector and the ith filter, to the ith filter Sending the i-th phase difference information.
  • the input selector 109 is further configured to:
  • the clock sources of the N clock domain interfaces correspond to the M types of services, selecting M phase difference information, the M phase difference information, and the phase difference information sent by the N phase frequency detectors
  • the M types of services are in one-to-one correspondence, and based on the correspondence between the N phase discriminators and the N filters, corresponding phase difference information is transmitted to each of the N filters, where M is an integer less than N.
  • the clock domain interfaces of the same service may be included in the N clock domain interfaces, that is, the N services corresponding to the N clock domain interfaces are partially the same.
  • the same service among the N services is divided into one type of service, and the N services include M types of services. Therefore, the input selector is required to perform source selection operation on the phase difference information of the clock sources from the N services, and N corresponding to N services.
  • the M phase difference information corresponding to the M types of services is selected in the phase difference information, so that the same type of services in the N services track the optimal clock source in the category.
  • M phase difference information may be selected from the N phase difference information.
  • the input selector can automatically perform source selection according to the SSM, and the source selection operation can be performed according to a source selection protocol, such as an SSM protocol, where The SSM protocol can be any version of ITU-T G.8264.
  • the input selector can also manually select the source according to the user's instruction, which is not limited in this embodiment of the present application.
  • the input selector selects M phase difference information and corresponds one-to-one with the M services, that is, the clock domain interfaces of the same service in the N clock domain interfaces use the same selected by the input selector. Phase difference information corresponding to the clock source. Then, the input selector transmits corresponding phase difference information to each of the N filters based on the correspondence between the M phase difference information and the N filters.
  • the input selector can be processed according to the requirements of the upper layer protocol.
  • the phase frequency detector will carry the identification information of the corresponding filter in the phase difference information, and is configured into the input selector, and the input selector can be configured according to
  • the phase difference information is used to determine a correspondence between the phase frequency detector and the filter.
  • the identification information is only used to distinguish the respective filters, and may be an identifier, a port number, and the like of the filter corresponding to the phase frequency detector, which is not limited in this embodiment of the present application.
  • the above input selector can be implemented in the device by software of a Central Processing Unit (CPU) or by Field-Programmable Gate Array (FPGA) hardware. This embodiment of the present application does not limit this.
  • CPU Central Processing Unit
  • FPGA Field-Programmable Gate Array
  • the device further includes an output selector 110.
  • the ith filter is specifically used to:
  • the ith frequency difference information is transmitted to the output selector.
  • the output selector is configured to receive the ith frequency difference information sent by the ith filter, and send the ith clock reconstructor to the ith clock reconstructor based on a correspondence between the ith filter and the ith clock reconstructor The i-th frequency difference information.
  • the output selector may transmit the frequency difference information to the N clock reconstructors by any means of broadcast, multicast, or unicast.
  • the output selector can construct a carrier frequency
  • the multicast message of the difference information is sent to each clock reconstructor.
  • the output selector may also send the corresponding frequency difference information to the clock reconstructor corresponding to the service that needs to transmit the clock according to the setting of the user, which is not limited in this embodiment of the present application.
  • the output selector may also be configured to send the N+1 frequency difference information corresponding to the clock signal to be measured to the N+1th clock reconstructor.
  • the frequency difference information sent by the output selector is encapsulated in a packet, and the packet can carry a source address and a destination address.
  • the text body can be forwarded.
  • the device has a device dedicated to message exchange. By adding different addresses to the respective frequency difference information, the packet switching device can be used for forwarding. In this way, the output selector can forward each frequency difference information to each clock reconstructor according to the corresponding relationship.
  • the device 100 further includes:
  • a common clock generator for generating the common clock signal before determining the ith phase difference information between the common clock signal and the clock signal, and focusing on the ith phase frequency detector and the ith clock
  • the constructor sends the common clock signal.
  • the common clock signal is generated by a common clock generator and transmitted over the bus to each phase frequency detector and to each clock reconstructor, with one and only one common clock signal in one device.
  • the common clock signal can be implemented using a universal phase locked loop technique.
  • the device 100 further includes:
  • a system bus configured to connect the N phase frequency detectors, the N filters, the N clock reconstructors, and the N clock domain interfaces, and bidirectionally transmit the phase difference determined by the N phase frequency detectors Value information and frequency difference information converted by the N filters.
  • connection referred to in this embodiment and subsequent embodiments is understood to be an electrical connection, not a direct connection, which may be indirectly connected through a third party device.
  • the device supporting the multi-clock domain clock transmission in the embodiment of the present application acquires the phase difference information between the clock signal generated by the clock source of each clock domain interface and the common clock signal through the phase frequency detector, and then passes the phase through the filter.
  • the difference information is converted into frequency difference information, and finally reconstructed by clock
  • the clock signal of the clock domain required by the device is combined and applied to the clock domain interface of each clock domain, thereby flexibly adapting multiple different clock domains, so that a single device can simultaneously support multi-clock domain clock transmission without adding or replacing.
  • the device is flexible enough to meet the needs of users.
  • FIG. 4 is a schematic block diagram of another apparatus 200 for supporting multi-clock domain clock delivery provided by an embodiment of the present application.
  • the device 200 can correspond to the hybrid service carrying device C in FIG. 1 and can be understood as a specific implementation of the device 100 in FIG. 2 or FIG. As shown in FIG. 4, the device 200 includes:
  • An Ethernet physical layer network (ETY) clock domain interface is configured to send a clock signal generated by a clock source that synchronizes an Ethernet line clock to the first phase frequency detector PFD.
  • EY Ethernet physical layer network
  • a clock domain interface of the Synchronous Transport Module level N (STM-N) is used to send a clock signal generated by a clock source of the synchronous digital system SDH line clock to the second PFD.
  • the first PFD is configured to determine first phase difference information between the common clock signal and the clock signal of the synchronized Ethernet line clock, and send the first phase difference information to the Ethernet device clock EEC filtering module.
  • the second PFD is configured to determine second phase difference information between the common clock signal and the clock signal of the SDH line clock, and send the second phase difference information to the synchronous digital system device clock SEC filtering module.
  • An EEC filtering module configured to perform low-pass filtering on the first phase difference information, and convert the first phase difference information into a first frequency difference information between the common clock signal and a network timing clock of the ETY clock domain interface, and The first frequency difference information is transmitted to the first DDS.
  • the EEC filtering module is configured to perform low-pass filtering conforming to the standard ITU-T G.8262 for the first phase difference information.
  • An SEC filtering module configured to perform low-pass filtering on the second phase difference information, and convert the second phase difference information into a second frequency difference information between the common clock and a network timing clock of the STM-N clock domain interface, And transmitting the second frequency difference information to the second DDS.
  • the SEC filtering module is configured to perform low-pass filtering conforming to standard ITU-T G.813 for the second phase difference information.
  • a first direct digital frequency synthesizer DDS configured to receive first frequency difference information sent by the EEC filtering module, and reconstruct a network timing clock of the ETY clock domain interface according to the common clock signal and the first frequency difference information, and Send to the ETY clock domain interface, apply to the corresponding service flow interface.
  • a second DDS configured to receive second frequency difference information sent by the SEC filtering module, and reconstruct a network timing clock of the STM-N clock domain interface according to the common clock signal and the second frequency difference information, and send the network timing clock to the STM -N clock domain interface, applied to the corresponding service flow interface.
  • first DDS and the second DDS are one specific implementation of the clock reconstructor in FIG. 2 or FIG. 3 above.
  • the device supporting the multi-clock domain clock transmission in the embodiment of the present application acquires the phase difference information between the clock signal generated by the clock source of each clock domain interface and the common clock signal through the phase frequency detector, and then passes the phase through the filter.
  • the difference information is converted into frequency difference information, and finally the clock signal of the clock domain required by the clock reconstructor is synthesized and applied to the clock domain interface of each clock domain, thereby flexibly adapting multiple different clock domains to achieve a single
  • the device supports multi-clock domain clock transmission at the same time. It does not need to add or replace devices, and can flexibly meet the needs of users.
  • the device 200 further includes: a common clock generator for generating a common clock signal, and transmitting the common clock signal to the first PFD, the second PFD, and the first DDS and the second DDS through the bus. .
  • a common clock signal is shared within the device 200.
  • the foregoing apparatus 200 further includes: a third PFD and an external synchronization interface.
  • the common clock generator is further configured to send a common clock signal to the third PFD.
  • the third PFD is configured to determine third phase difference information between the common clock signal and a clock signal of the external synchronization interface, and send the third phase difference information to an EEC filtering module or an SEC filtering module.
  • the clock signal of the external synchronization interface can be processed by the SEC filtering module or by the EEC filtering module, and the device can determine which filtering module to send the clock signal of the external synchronization interface according to the needs of the service.
  • the EEC filtering module may be further configured to perform low-pass filtering on the third phase difference information, and convert the third phase difference information into The third frequency difference information between the common clock and the network timing clock of the ETY clock domain interface, and the third frequency difference information is sent to the first DDS.
  • the EEC filtering module is configured to perform low-pass filtering conforming to the standard ITU-T G.8262 for the third phase difference information.
  • the first DDS can also be used to receive third frequency difference information sent by the EEC filtering module.
  • the network timing clock of the external synchronization interface is reconstructed according to the common clock signal and the third frequency difference information, and is applied to the corresponding service flow interface.
  • the SEC filtering module may be further configured to perform low-pass filtering on the third phase difference information, and convert the third phase difference information into a common clock.
  • the third frequency difference information between the network timing clocks that are interfaced with the STM-N clock domain, and the third frequency difference information is sent to the second DDS.
  • the SEC filtering module is configured to perform low-pass filtering conforming to standard ITU-T G.813 for the third phase difference information.
  • the second DDS may be further configured to receive the third frequency difference information sent by the SEC filtering module, and reconstruct a network timing clock of the external synchronization interface according to the common clock signal and the third frequency difference information, and apply the corresponding to the corresponding Business flow interface.
  • the foregoing apparatus 200 further includes: a third DDS.
  • the common clock generator is further configured to send a common clock signal to the third DDS.
  • the EEC filtering module is further configured to send the first frequency difference information to the third DDS.
  • the SEC filtering module is further configured to send second frequency difference information to the third DDS.
  • the third DDS is configured to receive the first frequency difference information sent by the EEC filtering module or the second frequency difference information sent by the SEC filtering module, according to the first frequency difference information or the second frequency difference information and the common clock signal, The network timing clock corresponding to the clock domain interface is reconstructed and sent to the external synchronization interface.
  • the above device 200 further includes: an input selector.
  • the first PFD is specifically configured to send the first phase difference information to the input selector.
  • the second PFD is specifically configured to send the second phase difference information to the input selector.
  • the third PFD is specifically configured to send the third phase difference value information to the input selector.
  • the input selector is configured to receive the first phase difference information, the second phase difference information, and the third phase difference information, and respectively send the first phase difference information to an Ethernet device clock EEC filtering module.
  • the second phase difference information is sent to the synchronous digital system device clock SEC filtering module, and the third phase difference information is sent to the SEC filtering module or the EEC filtering module.
  • the above device 200 further includes: an output selector.
  • the EEC filtering module is specifically configured to send the first frequency difference information or the third frequency difference information to the output selector.
  • the SEC filtering module is specifically configured to send the second frequency difference information or the third frequency difference information Give this output selector.
  • the output selector is configured to receive the first frequency difference information, the second frequency difference information, and the third frequency difference information, and respectively send the first frequency difference information to the first DDS, and send the second frequency difference information To the second DDS, the third frequency difference information is sent to the first DDS or the second DDS as needed.
  • the output selector may also send the first frequency difference information or the second frequency difference information to the third DDS for other devices (eg, test equipment) to measure the performance of the internal clock signal of the device through the external synchronization interface.
  • devices eg, test equipment
  • the apparatus for supporting multi-clock domain clock transmission in the embodiment of the present application is described in detail above with reference to FIG. 1 to FIG. 4 .
  • the method for supporting multi-clock domain clock transmission in the embodiment of the present application is described below with reference to FIG. 5 .
  • FIG. 5 illustrates a schematic diagram of a method 300 of supporting multi-clock domain clock delivery, which may be performed by device 100 or device 200 described above, in accordance with an embodiment of the present application. As shown in FIG. 5, the method 300 includes:
  • the i-th phase frequency detector in the N phase frequency detectors receives a clock signal generated by a clock source connected to the ith phase frequency detector, and determines an ith between the common clock signal and the clock signal. Phase difference information, and transmitting the ith phase difference information to an ith filter of the N filters corresponding to the ith phase frequency detector.
  • the ith filter receives the ith phase difference information sent by the ith phase frequency detector, converts the ith phase difference information into an ith frequency difference information, and reconstructs the N clocks.
  • the ith clock reconstructor corresponding to the ith filter transmits the ith frequency difference information.
  • the ith clock reconstructor receives the ith frequency difference information sent by the ith filter, and reconstructs an ith network timing clock in the device according to the common clock signal and the ith frequency difference information. And transmitting the ith network timing clock to the i-th clock domain interface of the N clock domain interfaces.
  • the N is an integer greater than or equal to 2, and the N clock domain interfaces are respectively corresponding to the N phase frequency detectors, the N filters, and the N clock reconstructors.
  • the frequency phase detectors are respectively connected to the N clock sources, and at least two of the N clock sources are different, and the i is an integer and satisfies 1 ⁇ i ⁇ N.
  • the method further includes:
  • the N+1th phase frequency detector receives the clock signal generated by the external clock source, determines the N+1th phase difference information between the clock signal generated by the external clock source and the common clock signal, and goes to the N
  • the jth filter in the filter transmits the (N+1)th phase difference information.
  • the jth filter receives the N+1th phase difference information sent by the (N+1)th phase frequency detector, and converts the N+1th phase difference information into the N+1th frequency difference information, And transmitting the (N+1)th frequency difference information to the jth clock reconstructor corresponding to the jth filter in the N clock reconstructors.
  • the jth clock reconstructor receives the N+1th frequency difference information sent by the jth filter, and reconstructs the N+ in the device according to the common clock signal and the (N+1)th frequency difference information. 1 a network timing clock, and transmitting the (N+1)th network timing clock to a jth clock domain interface of the N clock domain interfaces.
  • the N+1th phase frequency detector is connected to the external clock source through an external synchronization interface, where j is an integer and satisfies 1 ⁇ j ⁇ N.
  • the device can receive and reconstruct the clock signal from the external synchronization interface while supporting the clock signal transmission of multiple different clock domains, and ensure that each clock domain interface of the device can receive the clock signal of the external synchronization interface as needed.
  • each clock domain interface can use the clock signal of the external synchronization interface as its own network timing clock, thereby improving the accuracy of the clock signal in the device. .
  • the method further includes:
  • the kth filter of the N filters transmits the kth frequency difference information generated by the kth filter to the (N+1)th clock reconstructor.
  • the N+1th clock reconstructor receives the kth frequency difference information sent by the kth filter, and reconstructs a kth network timing clock in the device according to the kth frequency difference information, and
  • the external synchronization interface transmits the kth network timing clock, where k is an integer and satisfies 1 ⁇ k ⁇ N.
  • the kth filter may further transmit the kth frequency difference information to the (N+1)th clock reconstructor in addition to the kth frequency difference information to the kth clock reconstructor.
  • clock signals from multiple different clock domains can be transmitted not only in the various clock domain interfaces of the device, but also can be transmitted to other devices connected to the device through the external synchronization interface, thereby testing the performance of the internal clock signal of the device.
  • the ith phase difference information is sent to the ith filter corresponding to the ith phase frequency detector in the N filters, including:
  • the ith phase frequency detector sends the ith phase difference information to the input selector.
  • the input selector receives the ith phase difference information sent by the ith phase frequency detector, and sends the ith filter to the ith filter based on the correspondence between the ith phase frequency detector and the ith filter The The i-th phase difference information.
  • the method further includes:
  • the input selector selects M phase difference information from the phase difference information sent by the N phase frequency detectors, and the M phase differences
  • the value information is in one-to-one correspondence with the M types of services.
  • Transmitting the ith phase difference value information to the ith filter includes:
  • Corresponding phase difference information is transmitted to each of the N filters based on the correspondence between the N phase discriminators and the N filters.
  • the ith frequency difference information is sent to the ith clock reconstructor corresponding to the ith filter in the N clock reconstructors, including:
  • the ith filter transmits the ith frequency difference information to an output selector.
  • the output selector receives the ith frequency difference information sent by the ith filter, and sends the ith to the ith clock reconstructor based on the correspondence between the ith filter and the ith clock reconstructor Frequency difference information.
  • the method before determining the ith phase difference information between the common clock signal and the clock signal, the method further includes:
  • the common clock generator generates the common clock signal and transmits the common clock signal to the ith phase discriminator and the ith clock reconstructor.
  • the phase difference information between the clock signal generated by the clock source of each clock domain interface and the common clock signal is obtained by the phase frequency detector, and then the phase is passed through the filter.
  • the difference information is converted into frequency difference information, and finally the clock signal of the clock domain required by the clock reconstructor is synthesized and applied to the clock domain interface of each clock domain, thereby flexibly adapting multiple different clock domains to achieve a single
  • the device supports multi-clock domain clock transmission at the same time. It does not need to add or replace devices, and can flexibly meet the needs of users.
  • the size of the sequence numbers of the foregoing processes does not mean the order of execution sequence, and the order of execution of each process should be determined by its function and internal logic, and should not be applied to the embodiment of the present application.
  • the implementation process constitutes any limitation.
  • the disclosed apparatus and method may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, or an electrical, mechanical or other form of connection.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the embodiments of the present application.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.
  • the integrated unit if implemented in the form of a software functional unit and sold or used as a standalone product, may be stored in a computer readable storage medium.
  • a computer readable storage medium including instructions for causing a computer device (which may be a personal computer, server, or network device, etc.) to execute the present invention. All or part of the steps of the methods described in the various embodiments are applied.
  • the foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like, which can store program codes. .

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Abstract

一种支持多时钟域时钟传递的设备和方法。该设备包括：N个鉴频鉴相器、N个滤波器、N个时钟重构器和N个时钟域接口，其中，所述N为大于或等于2的整数，所述N个时钟域接口分别与所述N个鉴频鉴相器、所述N个滤波器以及所述N个时钟重构器一一对应，所述N个鉴频鉴相器分别与N个时钟源连接，且该N个时钟源中的至少两个时钟源不相同。上述设备通过对公共时钟信号、数字化的相位差值信息以及频率差值信息的传递，能够重构出多个不同的时钟信号，并应用到各个时钟域的时钟域接口，从而灵活适配多个不同的时钟域，实现单个设备同时支持多时钟域的时钟传递，不需要新增或者更换设备，能够灵活地满足用户的需求。

Description

支持多时钟域时钟传递的设备和方法 技术领域
本申请涉及通信技术领域，更具体地，涉及一种支持多时钟域(Multiple clock domains)时钟传递的设备和方法。
背景技术
在网络演进过程中，例如，在城域网网改演进过程中，原先的固网业务由同步数字体系(Synchronous Digital Hierarchy，SDH)设备承载。新建的移动业务则由互联网协议(Internet Protocol，IP)设备承载。这两种业务可能在相当长的时间内共存，因此需要混合业务承载设备同时承载多种业务。SDH业务本身要求混合业务承载设备建设自上而下的频率同步网。移动业务在长期演进的演进(Long Term Evolution-Advanced，LTE-A)时代要求混合业务承载设备具备承载同步以太网和1588v2时钟的能力，能够从全球导航卫星系统(Global Navigation Satellite System，GNSS)中获取频率同步和时间同步。此外，混合业务承载设备未来可能还需要支持演进到更高精度的同步网。不同的同步网可能具备不同的精度和不同的时钟源。目前，混合业务承载设备只能将多种不同的业务的数据分别传递给对应的设备，不能同时传递多种不同业务的时钟源产生的时钟信号。随着无线技术和固网技术的演进，网络设备支持多个不同时钟域同步的诉求越来越普遍。
国际电信联盟远程通信标准化部门(International Telecommunication Union Telecommunication Standardization Sector，ITU-T)定义了各种同步网设备的参考模型，但并未定义如何用同一台设备同时承载多个不同时钟域的时钟信号。
发明内容
有鉴于此，本申请实施例提供了一种支持多时钟域时钟传递的设备和方法，能够利用同一设备同时支持多种不同时钟域的时钟传递。
第一方面，提供了一种支持多时钟域时钟传递的设备。该设备包括：N个鉴频鉴相器、N个滤波器，N个时钟重构器和N个时钟域接口。
其中，该N为大于或等于2的整数。该N个时钟域接口分别与该N个 鉴频鉴相器、该N个滤波器以及该N个时钟重构器一一对应。该N个鉴频鉴相器分别与N个时钟源连接，且该N个时钟源中的至少两个时钟源不相同。
该N个鉴频鉴相器中的第i鉴频鉴相器用于接收与该第i鉴频鉴相器连接的时钟源产生的时钟信号，确定公共时钟信号与该时钟信号之间的第i相位差值信息，并且向该N个滤波器中与该第i鉴频鉴相器对应的第i滤波器发送该第i相位差值信息。
该第i滤波器用于接收该第i鉴频鉴相器发送的该第i相位差值信息，将该第i相位差值信息转化为第i频率差值信息，并且向该N个时钟重构器中与该第i滤波器对应的第i时钟重构器发送该第i频率差值信息。
该第i时钟重构器用于接收该第i滤波器发送的该第i频率差值信息，根据该公共时钟信号和该第i频率差值信息，在该设备内重构第i网络定时时钟，并且向该N个时钟域接口中的第i时钟域接口发送该第i网络定时时钟。
其中，该i为整数且满足1≤i≤N。
这样，由于一个设备内部只支持一种时钟信号的传递，在接收到多个不同时钟源的时钟信号后，该设备内部传递的仍是公共时钟信号，只是在各个时钟源接口处由时钟重构器重构出了不同时钟域的时钟信号，再分别发送给本时钟域的其他时钟域接口，进一步实现网络级别的时钟同步。上述设备通过提取不同时钟源的时钟信号和公共时钟之间的差异实现了多时钟域的时钟传递。
本申请实施例的支持多时钟域时钟传递的设备，通过鉴频鉴相器获取各个时钟域的时钟源产生的时钟信号和公共时钟信号之间的相位差值信息，再通过滤波器将相位差值信息转化为频率差值信息，最终通过时钟重构器合成所需要的时钟域的时钟信号，并应用到各个时钟域的时钟域接口，从而灵活适配多个不同的时钟域，实现单个设备同时支持多时钟域时钟传递，不需要新增或更换设备，能够灵活地满足用户的需求。
可选地，该N个鉴频鉴相器可以为双D数字鉴相器或者时域数字转换器(Time-to-Digital Converter，TDC)。
可选地，该N个滤波器可以分别由数字滤波模块和转换模块构成。其中数字滤波模块可以采用通用的7阶有限冲击响应(Finite Impulse Response， FIR)滤波模块。
可选地，该N个时钟重构器可以为直接数字频率合成器(Direct Digital frequency Synthesis，DDS)或数字控制振荡器(Number Controlled Oscillator，NCO)。
可选地，该相位差值信息和频率差值信息可以封装成二层以太报文传递。
在第一方面的第一种可能的实现方式中，该设备还包括：第N+1个鉴频鉴相器和外同步接口，其中，该第N+1个鉴频鉴相器通过该外同步接口与外部时钟源连接。
该第N+1个鉴频鉴相器用于接收该外部时钟源产生的时钟信号，确定该外部时钟源产生的时钟信号与该公共时钟信号之间的第N+1相位差值信息，并且向该N个滤波器中的第j滤波器发送该第N+1相位差值信息。
该第j滤波器用于接收该第N+1个鉴频鉴相器发送的该第N+1相位差值信息，将该第N+1相位差值信息转化为第N+1频率差值信息，并且向该N个时钟重构器中与该第j滤波器对应的第j时钟重构器发送该第N+1频率差值信息。
该第j时钟重构器用于接收该第j滤波器发送的该第N+1频率差值信息，根据该公共时钟信号和该第N+1频率差值信息，在该设备内重构第N+1网络定时时钟，并且向该N个时钟域接口中的第j时钟域接口发送该第N+1网络定时时钟。
其中，该j为整数且满足1≤j≤N。
这样，该设备可以在支持多个不同时钟域的时钟信号传递的同时，接收并重构来自外同步接口的时钟信号，确保该设备的各个时钟域接口能够根据需要接收到外同步接口的时钟信号。若外同步接口的时钟信号与各个时钟域接口的时钟信号相比精度更高，则各个时钟域接口可以将外同步接口的时钟信号作为自身的网络定时时钟，从而提高该设备内时钟信号的精度。
结合第一方面的上述可能的实现方式，在第一方面的第二种可能的实现方式中，该设备还包括：第N+1个时钟重构器。
该N个滤波器中的第k滤波器还用于向该第N+1个时钟重构器发送该第k滤波器产生的第k频率差值信息。
该第N+1个时钟重构器用于接收该第k滤波器发送的该第k频率差值 信息，根据该第k频率差值信息，在该设备内重构第k网络定时时钟，并且向该外同步接口发送该第k网络定时时钟。
其中，该k为整数且满足1≤k≤N。
通过本申请实施例的设备，来自多个不同时钟域的时钟信号不仅可以在设备的各个时钟域接口传递，而且可以通过外同步接口传递到其它与该设备相连的设备，从而实现对设备内部时钟信号的性能测试。
结合第一方面的上述可能的实现方式，在第一方面的第三种可能的实现方式中，该设备还包括：输入选择器。
该第i鉴频鉴相器具体用于：
向该输入选择器发送该第i相位差值信息。
该输入选择器用于接收该第i鉴频鉴相器发送的该第i相位差值信息，并且基于该第i鉴频鉴相器与该第i滤波器的对应关系，向该第i滤波器发送该第i相位差值信息。
结合第一方面的上述可能的实现方式，在第一方面的第四种可能的实现方式中，该输入选择器还用于：
当该N个时钟域接口的时钟源对应M种业务时，从该N个鉴频鉴相器发送的相位差值信息中，选择M个相位差值信息，该M个相位差值信息与该M种业务一一对应，并且基于该N个鉴频鉴相器与该N个滤波器的对应关系，向该N个滤波器中的每个滤波器发送对应的相位差值信息，其中，该M为小于N的整数。
具体地，若N个时钟域接口对应的N个业务中包括相同业务时，将相同业务划分为一种业务，故设该N个业务包括M种业务。输入选择器可以对来自N个业务的时钟源的相位差值信息进行选源操作，从N个业务对应的N个相位差值信息中选择出M种业务对应的M个相位差值信息，使N个业务中相同种类的业务都跟踪该种类中最优的时钟源。
可选地，上述输入选择器在该设备中既可以通过中央处理器(Central Processing Unit，CPU)的软件来实现，也可以通过现场可编程门阵列(Field-Programmable Gate Array，FPGA)硬件来实现，本申请实施例对此不作限定。
结合第一方面的上述可能的实现方式，在第一方面的第五种可能的实现方式中，该设备还包括：输出选择器。
该第i滤波器具体用于：
向该输出选择器发送该第i频率差值信息。
该输出选择器用于接收该第i滤波器发送的该第i频率差值信息，并且基于该第i滤波器与该第i时钟重构器的对应关系，向该第i时钟重构器发送该第i频率差值信息。
可选地，上述输出选择器在该设备中既可以通过中央处理器CPU的软件来实现，也可以通过现场可编程门阵列FPGA硬件来实现，本申请实施例对此不作限定。
结合第一方面的上述可能的实现方式，在第一方面的第六种可能的实现方式中，该设备还包括：
公共时钟产生器，用于在该确定公共时钟信号与该时钟信号之间的第i相位差值信息之前，产生该公共时钟信号，并且向该第i鉴频鉴相器和该第i时钟重构器发送该公共时钟信号。
第二方面，提供了一种支持多时钟域时钟传递的方法，该方法包括：
N个鉴频鉴相器中的第i鉴频鉴相器接收与该第i鉴频鉴相器连接的时钟源产生的时钟信号，确定公共时钟信号与该时钟信号之间的第i相位差值信息，并且向N个滤波器中与该第i鉴频鉴相器对应的第i滤波器发送该第i相位差值信息。
该第i滤波器接收该第i鉴频鉴相器发送的该第i相位差值信息，将该第i相位差值信息转化为第i频率差值信息，并且向N个时钟重构器中与该第i滤波器对应的第i时钟重构器发送该第i频率差值信息。
该第i时钟重构器接收该第i滤波器发送的该第i频率差值信息，根据该公共时钟信号和该第i频率差值信息，在该设备内重构第i网络定时时钟，并且向N个时钟域接口中的第i时钟域接口发送该第i网络定时时钟。
其中，该N为大于或等于2的整数，该N个时钟域接口分别与该N个鉴频鉴相器、该N个滤波器以及该N个时钟重构器一一对应，该N个鉴频鉴相器分别与N个时钟源连接，且该N个时钟源中的至少两个时钟源不相同，该i为整数且满足1≤i≤N。
在第二方面的第一种可能的实现方式中，该方法还包括：
第N+1个鉴频鉴相器接收外部时钟源产生的时钟信号，确定该外部时钟源产生的时钟信号与该公共时钟信号之间的第N+1相位差值信息，并且向该 N个滤波器中的第j滤波器发送该第N+1相位差值信息。
该第j滤波器接收该第N+1个鉴频鉴相器发送的该第N+1相位差值信息，将该第N+1相位差值信息转化为第N+1频率差值信息，并且向该N个时钟重构器中与该第j滤波器对应的第j时钟重构器发送该第N+1频率差值信息。
该第j时钟重构器接收该第j滤波器发送的该第N+1频率差值信息，根据该公共时钟信号和该第N+1频率差值信息，在该设备内重构第N+1网络定时时钟，并且向该N个时钟域接口中的第j时钟域接口发送该第N+1网络定时时钟。
其中，该第N+1个鉴频鉴相器通过外同步接口与该外部时钟源连接，该j为整数且满足1≤j≤N。
结合第二方面的上述可能的实现方式，在第二方面的第二种可能的实现方式中，该方法还包括：
该N个滤波器中的第k滤波器向第N+1个时钟重构器发送该第k滤波器产生的第k频率差值信息。
该第N+1个时钟重构器接收该第k滤波器发送的该第k频率差值信息，根据该第k频率差值信息，在该设备内重构第k网络定时时钟，并且向该外同步接口发送该第k网络定时时钟，其中，该k为整数且满足1≤k≤N。
结合第二方面的上述可能的实现方式，在第二方面的第三种可能的实现方式中，该向该N个滤波器中与该第i鉴频鉴相器对应的第i滤波器发送该第i相位差值信息，包括：
该第i鉴频鉴相器向输入选择器发送该第i相位差值信息。
该输入选择器接收该第i鉴频鉴相器发送的该第i相位差值信息，并且基于该第i鉴频鉴相器与该第i滤波器的对应关系，向该第i滤波器发送该第i相位差值信息。
结合第二方面的上述可能的实现方式，在第二方面的第四种可能的实现方式中，在该输入选择器接收该第i鉴频鉴相器发送的该第i相位差值信息之后，该方法还包括：
当该N个时钟域接口的时钟源对应M种业务时，该输入选择器从该N个鉴频鉴相器发送的相位差值信息中，选择M个相位差值信息，该M个相位差值信息与该M种业务一一对应。
该向该第i滤波器发送该第i相位差值信息，包括：
基于该N个鉴频鉴相器与该N个滤波器的对应关系，向该N个滤波器中的每个滤波器发送对应的相位差值信息。
其中，该M为小于该N的整数。
结合第二方面的上述可能的实现方式，在第二方面的第五种可能的实现方式中，该向该N个时钟重构器中与该第i滤波器对应的第i时钟重构器发送该第i频率差值信息，包括：
该第i滤波器向输出选择器发送该第i频率差值信息。
该输出选择器接收该第i滤波器发送的第i频率差值信息，并且基于该第i滤波器与该第i时钟重构器的对应关系，向该第i时钟重构器发送该第i频率差值信息。
结合第二方面的上述可能的实现方式，在第二方面的第六种可能的实现方式中，在该确定公共时钟信号与该时钟信号之间的第i相位差值信息之前，该方法还包括：
公共时钟产生器产生该公共时钟信号，并且向该第i鉴频鉴相器和该第i时钟重构器发送该公共时钟信号。
该第二方面中的方法可以由上述第一方面或第一方面的任意可能的实现方式中的设备执行。
第三方面，提供了一种计算机可读介质，用于存储计算机程序，该计算机程序包括用于执行第二方面或第二方面的任意可能的实现方式中的方法的指令。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对本申请实施例中所需要使用的附图作简单地介绍，显而易见地，下面所描述的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例的应用场景示意图。
图2是本申请实施例提供的支持多时钟域时钟传递的设备的示意性框图。
图3是本申请实施例提供的另一支持多时钟域时钟传递的设备的示意性 框图。
图4是本申请实施例提供的另一支持多时钟域时钟传递的设备的示意性框图。
图5是本申请实施例提供的支持多时钟域时钟传递的方法的示意性框图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚地描述。显然，所描述的实施例是本申请的一部分实施例，而不是全部实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动的前提下可以获得的其他实施例。
本申请实施例可应用于各种通信系统。因此，本申请实施例提供的技术方案的应用场景不限制于特定通信系统。技术方案的应用场景采用的通信系统可以是全球移动通讯(Global System of Mobile communication，GSM)系统、码分多址(Code Division Multiple Access，CDMA)系统、宽带码分多址(Wideband Code Division Multiple Access，WCDMA)系统、通用分组无线业务(General Packet Radio Service，GPRS)、长期演进(Long Term Evolution，LTE)系统、LTE频分双工(Frequency Division Duplex，FDD)系统、LTE时分双工(Time Division Duplex，TDD)或者通用移动通信系统(Universal Mobile Telecommunication System，UMTS)。
本申请实施例中的设备可以是网络设备，也可以是终端设备，还可以是其他传输节点，本申请实施例对此不做限定。其中，网络设备可以包括基站和基站控制器。基站可以是用于与终端设备进行通信的设备。例如，基站可以是GSM系统或CDMA中的基站(Base Transceiver Station，BTS)，也可以是WCDMA系统中的基站(Node B，NB)，还可以是LTE系统中的演进型基站(Evolutional Node B，eNB或eNodeB)。或者，基站可以为中继站、接入点、车载设备或者未来5G网络中的网络侧设备。基站控制器可以通过传输节点调度基站之间的业务。传输节点可以是以太交换机、IP路由器、分组传送网(Packet Transport Network，PTN)、微波(Microwave)设备或光传送网(Optical Transport Network，OTN)。终端设备可以指接入终端、用户设备(User Equipment，UE)、用户单元、用户站、移动站、移动台、远 方站、远程终端、移动设备、用户终端、终端、无线通信设备、用户代理或用户装置。接入终端可以是蜂窝电话、无绳电话、会话启动协议(Session Initiation Protocol，SIP)电话、无线本地环路(Wireless Local Loop，WLL)站、个人数字处理(Personal Digital Assistant，PDA)、具有无线通信功能的手持设备、计算设备或连接到无线调制解调器的其它处理设备、车载设备、可穿戴设备、未来5G网络中的终端设备或者未来演进的公共陆地移动网络(Public Land Mobile Network，PLMN)中的终端设备等。
图1示出了本申请实施例的应用场景示意图。如图1所示的应用场景包括时钟源A、时钟源B、设备A、设备B、设备C、设备D和设备E。其中，时钟源A和时钟源B分别为两种不同业务的时钟源。设备A的时钟源为时钟源A。设备B的时钟源为时钟源B。设备A和设备B各自承载的业务数据包同时传递到设备C，设备C再将设备A的业务数据包传递到设备D，将设备B的业务数据包传递到设备E。该架构承载了两种不同的业务，即两种同步网，因此设备C可以称为混合业务承载设备。
应理解，图1仅示例性地示出了包括两种时钟源的应用场景。可选地，该系统还可以包括更多的时钟源和更多的设备，本申请实施例对此不做限定。
图2示出了本申请实施例提供的支持多时钟域时钟传递的设备100的示意性框图，该设备100可以对应于图1中的混合业务承载设备C。该设备100包括：N个时钟域接口(包括第一时钟域接口101至第N时钟域接口102)、N个鉴频鉴相器(包括第一鉴频鉴相器103至第N鉴频鉴相器104)、N个滤波器(包括第一滤波器105至第N滤波器106)，和N个时钟重构器(包括第一时钟重构器107至第N时钟重构器108)。
其中，该N为大于或等于2的整数。该N个时钟域接口分别与该N个鉴频鉴相器、该N个滤波器以及该N个时钟重构器一一对应。该N个鉴频鉴相器分别与N个时钟源连接，且该N个时钟源中的至少两个时钟源不相同。
该N个鉴频鉴相器中的第i鉴频鉴相器用于接收与该第i鉴频鉴相器连接的时钟源产生的时钟信号，确定公共时钟信号与该时钟信号之间的第i相位差值信息，并且向该N个滤波器中与该第i鉴频鉴相器对应的第i滤波器发送该第i相位差值信息。
应理解，上述公共时钟信号可以由公共时钟产生器产生，通过总线发送给设备100内的各个鉴频鉴相器和各个时钟重构器。此外，一个设备内有且只有一个公共时钟信号。
该第i滤波器用于接收该第i鉴频鉴相器发送的该第i相位差值信息，将该第i相位差值信息转化为第i频率差值信息，并且向该N个时钟重构器中与该第i滤波器对应的第i时钟重构器发送该第i频率差值信息。
该第i时钟重构器用于接收该第i滤波器发送的该第i频率差值信息，根据该公共时钟信号和该第i频率差值信息，在该设备内重构第i网络定时时钟，并且向该N个时钟域接口中的第i时钟域接口发送该第i网络定时时钟。
其中，上述i为整数且满足1≤i≤N。
具体地，该设备的N个时钟域接口分别与该设备内部的N个鉴频鉴相器、N个滤波器和N个时钟重构器一一对应。例如，第一时钟域接口101对应第一鉴频鉴相器103、第一滤波器105、第一时钟重构器107，依次类推，第N时钟域接口102对应第N鉴频鉴相器104、第N滤波器106、第N时钟重构器108。它们可以分别独立地处理来自N个时钟域接口的时钟信号。N个鉴频鉴相器分别与N个时钟源连接，且该N个时钟源中的至少两个时钟源不相同。这里，应理解，一个时钟域接口只有一个时钟源，而一个时钟源可以同时与多个时钟域接口相连，为其提供时钟信号。因此，本申请实施例的来自N个时钟域接口的时钟信号可以是全部不相同的，也可以有一部分相同，即相同的时钟信号来自同一个时钟源，本申请实施例对此不作限定。
上述i为整数且满足1≤i≤N，即N个鉴频鉴相器、N个滤波器，N个时钟重构器和N个时钟域接口中的每一个都可以用于执行上述操作。具体而言，N个鉴频鉴相器中的每个鉴频鉴相器都可以分别接收到公共时钟信号和与该每个鉴频鉴相器对应的时钟域接口的时钟源产生的时钟信号，再确定该公共时钟信号与该每个鉴频鉴相器对应的时钟域接口的时钟源产生的时钟信号之间的相位差值信息，这样，N个鉴频鉴相器可以确定出N个相位差值信息。然后，N个鉴频鉴相器分别向各自对应的滤波器发送对应的相位差值信息，N个滤波器接收到各自的相位差值信息之后，分别将相位差值信息转化为频率差值信息，再分别发送给各自对应的时钟重构器。N个时钟重构器收到各自的频率差值信息之后，就可以根据公共时钟信号和接收到的频率差 值信息，分别重构各自对应的时钟域接口的网络定时时钟，最终发送给各自对应的时钟域接口。
上述网络定时时钟应理解为时钟源的时钟信号经过滤波处理后的同频信号。网元定时本身的目的，就是把从某个接口输入的参考源滤波后，分发到本时钟域的其他接口去，从而实现网络级别的同步。
由于一个设备内部只支持一种时钟信号的传递，因此本申请实施例先计算来自不同时钟域的时钟信号与公共时钟信号之间的相位差值信息，将相位差值信息转化为频率差值信息，然后在各个时钟源接口处由时钟重构器根据公共时钟信号重构出需要的时钟域的时钟信号。在接收到多个不同时钟源的时钟信号后，该设备内部传递的仍是公共时钟信号，只是在各个时钟源接口处由时钟重构器重构出了不同时钟域的时钟信号，再分别发送给本时钟域的其他时钟域接口，进一步实现网络级别的时钟同步。上述设备通过提取不同时钟源的时钟信号和公共时钟之间的差异实现了多时钟域的时钟传递。
本申请实施例的支持多时钟域时钟传递的设备，通过鉴频鉴相器获取各个时钟域接口的时钟源产生的时钟信号和公共时钟信号之间的相位差值信息，再通过滤波器将相位差值信息转化为频率差值信息，最终通过时钟重构器合成所需要的时钟域的时钟信号，并应用到各个时钟域的时钟域接口，从而灵活适配多个不同的时钟域，实现单个设备同时支持多时钟域时钟传递，不需要新增或更换设备，能够灵活地满足用户的需求。
应理解，在本申请实施例中，因为各个器件之间是相互独立的，所以上述N个时钟域的时钟信号也是相互独立地传递。对于N个时钟域的时钟信号的传递，可以是串行的，也可以是并行的，本申请实施例不作限定。
在具体实现中，鉴频鉴相器接收到两个时钟信号之后，可以将两个同频时钟信号通过逻辑电路比对上升沿(即第一个时钟沿)相位，得到相位差值信号，再通过高频时钟信号对相位差信号进行采样量化，得到相位差值信息并输出，该相位差值信息是一个数字量。可选地，鉴频鉴相器(Phase Frequency Detector，PFD)可以采用双D数字鉴相器或者时域数字转换器(Time-to-Digital Converter，TDC)。
滤波器主要是由数字滤波模块和转换模块构成。其中数字滤波模块可以采用通用的7阶有限冲击响应(Finite Impulse Response，FIR)滤波模块。滤波器将相位差值信息作为输入，由数字滤波模块对该相位差值信息执行低 通滤波，再由转换模块将滤波后的相位差值信息进行积分，得到频率差值信息。最终滤波器将该频率差值信息作为输出。应理解，滤波器中间的所有处理都是数字处理。在本申请实施例中，滤波器可以为以太网设备时钟(Ethernet Equipment Clock，EEC)滤波器、同步数字体系设备时钟(Synchronous Digital Hierarchy Equipment Clock，SEC)滤波器或光传送网设备时钟(Optical Transport Network Equipment Clock，OEC)滤波器，由业务种类决定。此外，滤波器可以利用常见的有限冲击响应(Finite Impulse Response，FIR)结构，通过数字信号处理(Digital Signal Processing，DSP)实现。本申请实施例对此不作限定。
时钟重构器可以为直接数字频率合成器(Direct Digital frequency Synthesis，DDS)或数字控制振荡器(Number Controlled Oscillator，NCO)。本申请实施例对此不作限定。
可选地，可以将相位差值信息和频率差值信息封装在报文中进行传递。该报文可以是以太报文，还可以是采用高级数据链路(High-Level Data Link，HDLC)或通用成帧规程(Generic Framing Procedure，GFP)等封装的报文。此外，也可以将相位差值信息和频率差值信息封装在携带虚拟局域网(Virtual Local Area Network，VLAN)标签或多协议标记交换(Multiprotocol Label Switching，MPLS)标签等报文中，本申请实施例对此不作限定。
可选地，对相位差值信息和频率差值信息的封装，可以采用二层封装，也可以采用三层封装，本申请实施例对此不作限定。具体采用二层封装还是三层封装，取决于转发技术。如果采用二层转发，就要采用二层封装；如果选用三层转发，就要采用三层封装。应理解，这里的“层”指的是传输控制协议/互联网协议(Transmission Control Protocol/Internet Protocol，TCP/IP协议)中的层次，二层为数据链路层，三层为网络层，对于不同层次的报文转发，寻址方式不同，二层是通过媒体访问控制(Media Access Control，MAC)地址寻址，三层是通过互联网协议(Internet Protocol，IP)地址寻址。
可选地，对相位差值信息和频率差值信息的封装，还可以采用时分复用模式(Testing Data Management，TDM)中的帧结构、异步传输模式(Asynchronous Transfer Mode，ATM)中的帧结构、虚拟封装4(Virtual Containers-4，VC-4)、光传送网(Optical Transport Network，OTN)中的帧结构、GFP帧、同步转移模式(Synchronous Transfer Mode，STM)帧中的 任意一种，本申请实施例对此不作限定。
应理解，上述设备的内部系统可以由多块板卡插在一个共同的背板上实现。不同的板卡之间也需要管理、配置的通道。目前经常使用100M的以太网或者1G的以太网来实现设备内的通信。
还应理解，相位差值信息和频率差值信息的传输路径为系统总线，可以包括但不局限于系统内的快速以太网(Fast Ethernet，FE)/千兆以太网(Gigabit Ethernet，GE)接口、本地总线、内置集成电路(Inter-Integrated Circuit，I2C)总线、串行外设接口(Serial Peripheral Interface，SPI)总线、高级数据链路控制(Highlevel Data Link Control，HDLC)总线等常见形式。本申请实施例对此也不作限定。
作为一个可选的实施例，该设备还包括：第N+1个鉴频鉴相器和外同步接口，其中，该第N+1个鉴频鉴相器通过该外同步接口与外部时钟源连接。
应理解，外同步接口是一种不携带业务，仅携带时钟信号的设备接口。该接口如果和高精度时钟源对接，则可以用于将该高精度时钟源的时钟信号作为设备内部时钟域的网络定时时钟的信号；该接口如果和测试设备对接，则可以用于引出某个时钟域的时钟信号，观测该时钟信号的性能。这里，外部时钟源应理解为与外同步接口连接的时钟源，该时钟源可以是上述的N个时钟源中的一个时钟源，也可以是其他时钟源，本申请实施例对此不作限定。
该第N+1个鉴频鉴相器用于接收该外部时钟源产生的时钟信号，确定该外部时钟源产生的时钟信号与该公共时钟信号之间的第N+1相位差值信息，并且向该N个滤波器中的第j滤波器发送该第N+1相位差值信息。
该第j滤波器用于接收该第N+1个鉴频鉴相器发送的该第N+1相位差值信息，将该第N+1相位差值信息转化为第N+1频率差值信息，并且向该N个时钟重构器中与该第j滤波器对应的第j时钟重构器发送该第N+1频率差值信息。
该第j时钟重构器用于接收该第j滤波器发送的该第N+1频率差值信息，根据该公共时钟信号和该第N+1频率差值信息，在该设备内重构第N+1网络定时时钟，并且向该N个时钟域接口中的第j时钟域接口发送该第N+1网络定时时钟。
其中，该j为整数且满足1≤j≤N。
这里，j和i可以相等，也可以不相等，本申请实施例对此不作限定。
具体地，该设备还包括第N+1个鉴频鉴相器和外同步接口，可以传递来自外同步接口的时钟信号。第N+1鉴频鉴相器接收与外同步接口连接的外部时钟源产生的时钟信号，确定该外同步接口的时钟源产生的时钟信号与该公共时钟信号之间的第N+1相位差值信息，并将其发送给上述N个滤波器中的第j滤波器。该第j滤波器将该第N+1相位差值信息转化为第N+1频率差值信息，将第N+1频率差值信息发送给N个时钟重构器中与该第j滤波器对应的第j时钟重构器，该第j时钟重构器可以在设备内重构外同步接口的网络定时时钟，并且将其发送给该N个时钟域接口中与该第j时钟重构器对应的时钟域接口。
应理解，第N+1鉴频鉴相器是可以根据时钟域接口的需要发送相位差值信息的。任何同步网的时钟同步，都可能要通过外同步接口获取外部同步源的时钟信号，故任一个滤波器都可以处理外同步接口的时钟源与公共时钟之间的相位差值信息。第N+1鉴频鉴相器可以根据时钟域接口的需要，将产生的第N+1相位差值信息发送给对应的滤波器。
这样，该设备可以在支持多个不同时钟域的时钟信号传递的同时，接收并重构来自外同步接口的时钟信号，确保该设备的各个时钟域接口能够根据需要接收到外同步接口的时钟信号。若外同步接口的时钟信号与各个时钟域接口的时钟信号相比精度更高，则各个时钟域接口可以将外同步接口的时钟信号作为自身的网络定时时钟，从而提高该设备内时钟信号的精度。
作为一个可选的实施例，该设备还包括：第N+1个时钟重构器。
该N个滤波器中的第k滤波器还用于向该第N+1个时钟重构器发送该第k滤波器产生的第k频率差值信息。
该第N+1个时钟重构器用于接收该第k滤波器发送的该第k频率差值信息，根据该第k频率差值信息，在该设备内重构第k网络定时时钟，并且向该外同步接口发送该第k网络定时时钟。
其中，该k为整数且满足1≤k≤N。
这里，k和i可以相等，也可以不相等，k和j可以相等，也可以不相等，本申请实施例对此不作限定。
在该实施例中，用户可以用于根据需要测试该设备内部的时钟信号的性能。具体地，当该设备与另一设备对接时，就需要测试该设备内部的时钟信号的性能。或者，直接采用某个测试设备(例如，仪表)连接该设备。那么， 该设备需要通过外同步接口输出该设备内部来自多时钟域的时钟信号，或者根据用户的需要输出其中任意一种时钟信号。该设备在获知被测试的是哪一个时钟域接口的网络定时时钟之后，会通过与被测试的时钟域接口对应的滤波器(即第k滤波器)向第N+1个时钟重构器发送被测试的时钟域接口与公共时钟信号之间的第k频率差值信息，由第N+1个时钟重构器重构出对应的第k网络定时时钟，并将其发送给该外同步接口。上述对接设备或测试设备就可以通过该外同步接口获取该设备的不同时钟信号，对该设备内部的时钟信号的性能进行测试。
应理解，测试设备或者对接设备可以根据需要来选择对上述N个时钟域接口中具体某个时钟域接口的时钟源进行测试，也可以依次对上述N个时钟域接口中的每一个时钟域接口的时钟源进行测试，本申请实施例对此不作限定。
因此，通过本申请实施例的设备，来自多个不同时钟域的时钟信号不仅可以在设备的各个时钟域接口传递，而且可以通过外同步接口传递到其它与该设备相连的设备，从而实现对设备内部时钟信号性能的测试。
作为一个可选的实施例，如图3所示，该设备还包括：输入选择器109。
该第i鉴频鉴相器具体用于：
向该输入选择器发送该第i相位差值信息。
该输入选择器用于接收该第i鉴频鉴相器发送的该第i相位差值信息，并且基于该第i鉴频鉴相器与该第i滤波器的对应关系，向该第i滤波器发送该第i相位差值信息。
作为一个可选的实施例，该输入选择器109还用于：
当该N个时钟域接口的时钟源对应M种业务时，从该N个鉴频鉴相器发送的相位差值信息中，选择M个相位差值信息，该M个相位差值信息与该M种业务一一对应，并且基于该N个鉴频鉴相器与该N个滤波器的对应关系，向该N个滤波器中的每个滤波器发送对应的相位差值信息，其中，该M为小于N的整数。
具体地，N个时钟域接口中可以包括相同业务的时钟域接口，即N个时钟域接口对应的N个业务有部分是相同的。将该N个业务中相同的业务划分为一种业务，设该N个业务包括M种业务。因此需要输入选择器对来自N个业务的时钟源的相位差值信息进行选源操作，从N个业务对应的N个 相位差值信息中选择出M种业务对应的M个相位差值信息，使N个业务中相同种类的业务都跟踪该种类中最优的时钟源。
在该输入选择器接收到N个时钟源对应的N个相位差值信息之后，可以从该N个相位差值信息中选择出M个相位差值信息。若该N个相位差值信息分别携带同步状态信息(Synchronization Status Message，SSM)，那么该输入选择器可以根据SSM自动进行选源，选源操作可以根据选源协议来执行，例如SSM协议，其中该SSM协议可以是ITU-T G.8264的任意版本。若该N个相位差值信息没有携带同步状态信息，该输入选择器也可以根据用户的指令手动进行选源，本申请实施例对此不作限定。
在选源操作结束之后，输入选择器会选择出M个相位差值信息，与M种业务一一对应，即N个时钟域接口中相同业务的时钟域接口都使用该输入选择器选择的同一时钟源对应的相位差值信息。然后，该输入选择器基于该M个相位差值信息与该N个滤波器的对应关系，分别向N个滤波器中的每个滤波器发送对应的相位差值信息。
在具体实现中，输入选择器可以根据上层协议要求来处理，例如鉴频鉴相器会在相位差值信息中携带对应滤波器的标识信息，配置到输入选择器中，输入选择器就可以根据相位差值信息来确定鉴频鉴相器与滤波器之间的对应关系。该标识信息仅用于区分出各个滤波器，可以是鉴频鉴相器对应的滤波器的标识符、端口号等，本申请实施例对此不作限定。
应理解，上述输入选择器在该设备中既可以通过中央处理器(Central Processing Unit，CPU)的软件来实现，也可以通过现场可编程门阵列(Field-Programmable Gate Array，FPGA)硬件来实现，本申请实施例对此不作限定。
作为一个可选的实施例，如图3所示，该设备还包括：输出选择器110。
该第i滤波器具体用于：
向该输出选择器发送该第i频率差值信息。
该输出选择器用于接收该第i滤波器发送的该第i频率差值信息，并且基于该第i滤波器与该第i时钟重构器的对应关系，向该第i时钟重构器发送该第i频率差值信息。
具体地，该输出选择器可以通过广播、组播或者单播任一方式向N个时钟重构器传递上述频率差值信息。可选地，该输出选择器可以构建携带频率 差值信息的多播报文发送给各个时钟重构器。可选地，该输出选择器还可以根据用户的设置，仅向需要传递时钟的业务对应的时钟重构器发送对应的频率差值信息，本申请实施例对此不作限定。
此外，若需要通过外同步接口测量该设备内部时钟信号的性能，该输出选择器还可以用于向第N+1时钟重构器发送需要测量的时钟信号对应的第N+1频率差值信息。
在具体实现中，输出选择器发出的频率差值信息是封装在一个报文中的，该报文可以携带源地址和目的地址。报文本身可以被转发。该设备内有专门负责报文交换的器件。将各个频率差值信息前面加上不同的地址，就可以通过报文交换器件实现转发。这样，输出选择器可以将各个频率差值信息根据对应关系转发给各个时钟重构器。
应理解，上述输出选择器在该设备中既可以通过中央处理器(Central Processing Unit，CPU)的软件来实现，也可以通过现场可编程门阵列(Field-Programmable Gate Array，FPGA)硬件来实现，本申请实施例对此不作限定。
作为一个可选的实施例，该设备100还包括：
公共时钟产生器，用于在该确定公共时钟信号与该时钟信号之间的第i相位差值信息之前，产生该公共时钟信号，并且向该第i鉴频鉴相器和该第i时钟重构器发送该公共时钟信号。
应理解，公共时钟信号由公共时钟产生器产生并通过总线发送给各个鉴频鉴相器和各个时钟重构器，一个设备中有且只有一个公共时钟信号。可选地，公共时钟信号可以采用通用的锁相环技术实现。
可选地，该设备100还包括：
系统总线，用于连接该N个鉴频鉴相器、该N个滤波器、该N个时钟重构器和N个时钟域接口，并且双向传递该N个鉴频鉴相器确定的相位差值信息和该N个滤波器转化的频率差值信息。
本实施例及后续实施例中涉及的“连接”应理解为是一种电性连接，并非直接的相连，这种连接可通过第三方器件间接实现相连。
本申请实施例的支持多时钟域时钟传递的设备，通过鉴频鉴相器获取各个时钟域接口的时钟源产生的时钟信号和公共时钟信号之间的相位差值信息，再通过滤波器将相位差值信息转化为频率差值信息，最终通过时钟重构 器合成所需要的时钟域的时钟信号，并应用到各个时钟域的时钟域接口，从而灵活适配多个不同的时钟域，实现单个设备同时支持多时钟域时钟传递，不需要新增或更换设备，能够灵活地满足用户的需求。
图4示出了本申请实施例提供的另一支持多时钟域时钟传递的设备200的示意性框图。该设备200可以对应于图1中的混合业务承载设备C，且该设备200可以理解为图2或图3中设备100的一种具体实施方式。如图4所示，该设备200包括：
以太网物理层网络(Ethernet Physical Layer Network，ETY)时钟域接口，用于向第一鉴频鉴相器PFD发送同步以太线路时钟的时钟源产生的时钟信号。
N级同步传输模块(Synchronous Transport Module level N，STM-N)时钟域接口，用于向第二PFD发送同步数字体系SDH线路时钟的时钟源产生的时钟信号。
第一PFD，用于确定公共时钟信号与同步以太线路时钟的时钟信号之间的第一相位差值信息，并将该第一相位差值信息发送给以太网设备时钟EEC滤波模块。
第二PFD，用于确定公共时钟信号与SDH线路时钟的时钟信号之间的第二相位差值信息，并将该第二相位差值信息发送给同步数字体系设备时钟SEC滤波模块。
EEC滤波模块，用于对第一相位差值信息执行低通滤波，将第一相位差值信息转化为公共时钟信号与ETY时钟域接口的网络定时时钟之间的第一频率差值信息，并将第一频率差值信息发送给第一DDS。优选的，上述EEC滤波模块，用于对第一相位差值信息执行符合标准ITU-T G.8262的低通滤波。
SEC滤波模块，用于对第二相位差值信息执行低通滤波，将第二相位差值信息转化为公共时钟与STM-N时钟域接口的网络定时时钟之间的第二频率差值信息，并将第二频率差值信息发送给第二DDS。优选的，上述SEC滤波模块，用于对第二相位差值信息执行符合标准ITU-T G.813的低通滤波。
第一直接数字频率合成器DDS，用于接收EEC滤波模块发送的第一频率差值信息，根据公共时钟信号和该第一频率差值信息，重构出ETY时钟域接口的网络定时时钟，并发送给ETY时钟域接口，应用到对应的业务流 接口。
第二DDS，用于接收SEC滤波模块发送的第二频率差值信息，根据公共时钟信号和该第二频率差值信息，重构出STM-N时钟域接口的网络定时时钟，并发送给STM-N时钟域接口，应用到对应的业务流接口。
应理解，第一DDS和第二DDS为上述图2或图3中时钟重构器的一种具体实施方式。
本申请实施例的支持多时钟域时钟传递的设备，通过鉴频鉴相器获取各个时钟域接口的时钟源产生的时钟信号和公共时钟信号之间的相位差值信息，再通过滤波器将相位差值信息转化为频率差值信息，最终通过时钟重构器合成所需要的时钟域的时钟信号，并应用到各个时钟域的时钟域接口，从而灵活适配多个不同的时钟域，实现单个设备同时支持多时钟域时钟传递，不需要新增或更换设备，能够灵活地满足用户的需求。
作为一个可选的实施例，上述设备200还包括：公共时钟产生器，用于产生公共时钟信号，并且通过总线向第一PFD、第二PFD和第一DDS、第二DDS发送该公共时钟信号。该设备200内共享一个公共时钟信号。
作为一个可选的实施例，上述设备200还包括：第三PFD和外同步接口。
该公共时钟产生器还用于向该第三PFD发送公共时钟信号。
该第三PFD用于确定该公共时钟信号与该外同步接口的时钟信号之间的第三相位差值信息，并将该第三相位差值信息发送给EEC滤波模块或SEC滤波模块。
应理解，外同步接口的时钟信号既可以由SEC滤波模块处理，也可以由EEC滤波模块处理，该设备可以根据业务的需要来确定将外同步接口的时钟信号发送给哪一个滤波模块。
若外同步接口的时钟信号为同步以太线路时钟的时钟源产生的时钟信号，该EEC滤波模块还可以用于对第三相位差值信息执行低通滤波，将该第三相位差值信息转化为公共时钟与ETY时钟域接口的网络定时时钟之间的第三频率差值信息，并将第三频率差值信息发送给第一DDS。优选的，上述EEC滤波模块，用于对第三相位差值信息执行符合标准ITU-T G.8262的低通滤波。
该第一DDS还可以用于接收EEC滤波模块发送的第三频率差值信息， 根据公共时钟信号和该第三频率差值信息，重构出该外同步接口的网络定时时钟，应用到对应的业务流接口。
若外同步接口的时钟信号为SDH线路时钟的时钟源产生的时钟信号，该SEC滤波模块还可以用于对第三相位差值信息执行低通滤波，将第三相位差值信息转化为公共时钟与STM-N时钟域接口的网络定时时钟之间的第三频率差值信息，并将第三频率差值信息发送给第二DDS。优选的，上述SEC滤波模块，用于对第三相位差值信息执行符合标准ITU-T G.813的低通滤波。
该第二DDS还可以用于接收SEC滤波模块发送的第三频率差值信息，根据公共时钟信号和该第三频率差值信息，重构出该外同步接口的网络定时时钟，应用到对应的业务流接口。
作为一个可选的实施例，上述设备200还包括：第三DDS。
该公共时钟产生器还用于向该第三DDS发送公共时钟信号。
该EEC滤波模块还用于向该第三DDS发送第一频率差值信息。
该SEC滤波模块还用于向该第三DDS发送第二频率差值信息。
该第三DDS用于接收EEC滤波模块发送的第一频率差值信息或SEC滤波模块发送的第二频率差值信息，根据第一频率差值信息或第二频率差值信息以及公共时钟信号，重构出对应时钟域接口的网络定时时钟，并发送给外同步接口。
作为一个可选的实施例，上述设备200还包括：输入选择器。
该第一PFD具体用于将上述第一相位差值信息发送给该输入选择器。
该第二PFD具体用于将上述第二相位差值信息发送给该输入选择器。
该第三PFD具体用于将上述第三相位差值信息发送给该输入选择器。
该输入选择器用于接收该第一相位差值信息、该第二相位差值信息和该第三相位差值信息，并分别将该第一相位差值信息发送给以太网设备时钟EEC滤波模块，将该第二相位差值信息发送给同步数字体系设备时钟SEC滤波模块，将该第三相位差值信息发送给SEC滤波模块或EEC滤波模块。
作为一个可选的实施例，上述设备200还包括：输出选择器。
该EEC滤波模块具体用于将第一频率差值信息或第三频率差值信息发送给该输出选择器。
该SEC滤波模块具体用于将第二频率差值信息或第三频率差值信息发 送给该输出选择器。
该输出选择器用于接收第一频率差值信息、第二频率差值信息和第三频率差值信息，并分别将第一频率差值信息发送给第一DDS，将第二频率差值信息发送给第二DDS，将第三频率差值信息根据需要发送给第一DDS或第二DDS。
该输出选择器也可以将第一频率差值信息或第二频率差值信息发送给第三DDS，用于其他设备(例如测试设备)通过外同步接口测量该设备内部时钟信号的性能。
上文中结合图1至图4详细描述了本申请实施例的支持多时钟域时钟传递的设备，下面结合图5描述本申请实施例的支持多时钟域时钟传递的方法。
图5示出了根据本申请实施例的支持多时钟域时钟传递的方法300的示意图，该方法300可以由上述的设备100或设备200执行。如图5所示，该方法300包括：
S310，N个鉴频鉴相器中的第i鉴频鉴相器接收与该第i鉴频鉴相器连接的时钟源产生的时钟信号，确定公共时钟信号与该时钟信号之间的第i相位差值信息，并且向N个滤波器中与该第i鉴频鉴相器对应的第i滤波器发送该第i相位差值信息。
S320，该第i滤波器接收该第i鉴频鉴相器发送的该第i相位差值信息，将该第i相位差值信息转化为第i频率差值信息，并且向N个时钟重构器中与该第i滤波器对应的第i时钟重构器发送该第i频率差值信息。
S330，该第i时钟重构器接收该第i滤波器发送的该第i频率差值信息，根据该公共时钟信号和该第i频率差值信息，在该设备内重构第i网络定时时钟，并且向N个时钟域接口中的第i时钟域接口发送该第i网络定时时钟。
其中，该N为大于或等于2的整数，该N个时钟域接口分别与该N个鉴频鉴相器、该N个滤波器以及该N个时钟重构器一一对应，该N个鉴频鉴相器分别与N个时钟源连接，且该N个时钟源中的至少两个时钟源不相同，该i为整数且满足1≤i≤N。
作为一个可选的实施例，该方法还包括：
第N+1个鉴频鉴相器接收外部时钟源产生的时钟信号，确定该外部时钟源产生的时钟信号与该公共时钟信号之间的第N+1相位差值信息，并且向该N个滤波器中的第j滤波器发送该第N+1相位差值信息。
该第j滤波器接收该第N+1个鉴频鉴相器发送的该第N+1相位差值信息，将该第N+1相位差值信息转化为第N+1频率差值信息，并且向该N个时钟重构器中与该第j滤波器对应的第j时钟重构器发送该第N+1频率差值信息。
该第j时钟重构器接收该第j滤波器发送的该第N+1频率差值信息，根据该公共时钟信号和该第N+1频率差值信息，在该设备内重构第N+1网络定时时钟，并且向该N个时钟域接口中的第j时钟域接口发送该第N+1网络定时时钟。
其中，该第N+1个鉴频鉴相器通过外同步接口与该外部时钟源连接，该j为整数且满足1≤j≤N。
这样，该设备可以在支持多个不同时钟域的时钟信号传递的同时，接收并重构来自外同步接口的时钟信号，确保该设备的各个时钟域接口能够根据需要接收到外同步接口的时钟信号。若外同步接口的时钟信号与各个时钟域接口的时钟信号相比精度更高，则各个时钟域接口可以将外同步接口的时钟信号作为自身的网络定时时钟，从而提高该设备内时钟信号的精度。
作为一个可选的实施例，该方法还包括：
该N个滤波器中的第k滤波器向第N+1个时钟重构器发送该第k滤波器产生的第k频率差值信息。
该第N+1个时钟重构器接收该第k滤波器发送的该第k频率差值信息，根据该第k频率差值信息，在该设备内重构第k网络定时时钟，并且向该外同步接口发送该第k网络定时时钟，其中，该k为整数且满足1≤k≤N。
具体地，第k滤波器在向第k时钟重构器发送第k频率差值信息之外，还可以向第N+1时钟重构器发送第k频率差值信息。这样，来自多个不同时钟域的时钟信号不仅可以在该设备的各个时钟域接口传递，而且可以通过外同步接口传递到其它与该设备相连的设备，从而实现对设备内部时钟信号性能的测试。
作为一个可选的实施例，向该N个滤波器中与该第i鉴频鉴相器对应的第i滤波器发送该第i相位差值信息，包括：
该第i鉴频鉴相器向输入选择器发送该第i相位差值信息。
该输入选择器接收该第i鉴频鉴相器发送的该第i相位差值信息，并且基于该第i鉴频鉴相器与该第i滤波器的对应关系，向该第i滤波器发送该 第i相位差值信息。
作为一个可选的实施例，在该输入选择器接收该第i鉴频鉴相器发送的该第i相位差值信息之后，该方法还包括：
当该N个时钟域接口的时钟源对应M种业务时，该输入选择器从该N个鉴频鉴相器发送的相位差值信息中，选择M个相位差值信息，该M个相位差值信息与该M种业务一一对应。
该向该第i滤波器发送该第i相位差值信息，包括：
基于该N个鉴频鉴相器与该N个滤波器的对应关系，向该N个滤波器中的每个滤波器发送对应的相位差值信息。
其中，该M为小于该N的整数。
作为一个可选的实施例，向该N个时钟重构器中与该第i滤波器对应的第i时钟重构器发送该第i频率差值信息，包括：
该第i滤波器向输出选择器发送该第i频率差值信息。
该输出选择器接收该第i滤波器发送的第i频率差值信息，并且基于该第i滤波器与该第i时钟重构器的对应关系，向该第i时钟重构器发送该第i频率差值信息。
作为一个可选的实施例，在确定公共时钟信号与该时钟信号之间的第i相位差值信息之前，该方法还包括：
公共时钟产生器产生该公共时钟信号，并且向该第i鉴频鉴相器和该第i时钟重构器发送该公共时钟信号。
本申请实施例的支持多时钟域时钟传递的方法，通过鉴频鉴相器获取各个时钟域接口的时钟源产生的时钟信号和公共时钟信号之间的相位差值信息，再通过滤波器将相位差值信息转化为频率差值信息，最终通过时钟重构器合成所需要的时钟域的时钟信号，并应用到各个时钟域的时钟域接口，从而灵活适配多个不同的时钟域，实现单个设备同时支持多时钟域时钟传递，不需要新增或更换设备，能够灵活地满足用户的需求。
应理解，说明书中提到的“一个实施例”或“一实施例”意味着与实施例有关的特定特征、结构或特性包括在本申请的至少一个实施例中。因此，在整个说明书各处出现的“在一个实施例中”或“在一实施例中”未必一定指相同的实施例。此外，这些特定的特征、结构或特性可以任意适合的方式结合在一个或多个实施例中。
应理解，在本申请的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
本领域普通技术人员可以意识到，结合本文中所公开的实施例中描述的各方法步骤和单元，能够以电子硬件、计算机软件或者二者的结合来实现，为了清楚地说明硬件和软件的可互换性，在上述说明中已经按照功能一般性地描述了各实施例的步骤及组成。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。本领域普通技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
所属领域的技术人员可以清楚地了解到，为了描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口、装置或单元的间接耦合或通信连接，也可以是电的，机械的或其它的形式连接。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本申请实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以是两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分，或者该技术方 案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到各种等效的修改或替换，这些修改或替换都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (14)

  1. 一种支持多时钟域时钟传递的设备，其特征在于，包括：N个鉴频鉴相器、N个滤波器，N个时钟重构器和N个时钟域接口，
    其中，所述N为大于或等于2的整数，所述N个时钟域接口分别与所述N个鉴频鉴相器、所述N个滤波器以及所述N个时钟重构器一一对应，所述N个鉴频鉴相器分别与N个时钟源连接，且所述N个时钟源中的至少两个时钟源不相同；
    所述N个鉴频鉴相器中的第i鉴频鉴相器用于接收与所述第i鉴频鉴相器连接的时钟源产生的时钟信号，确定公共时钟信号与所述时钟信号之间的第i相位差值信息，并且向所述N个滤波器中与所述第i鉴频鉴相器对应的第i滤波器发送所述第i相位差值信息；
    所述第i滤波器用于接收所述第i鉴频鉴相器发送的所述第i相位差值信息，将所述第i相位差值信息转化为第i频率差值信息，并且向所述N个时钟重构器中与所述第i滤波器对应的第i时钟重构器发送所述第i频率差值信息；
    所述第i时钟重构器用于接收所述第i滤波器发送的所述第i频率差值信息，根据所述公共时钟信号和所述第i频率差值信息，在所述设备内重构第i网络定时时钟，并且向所述N个时钟域接口中的第i时钟域接口发送所述第i网络定时时钟；
    其中，所述i为整数且满足1≤i≤N。
  2. 根据权利要求1所述的设备，其特征在于，所述设备还包括：第N+1个鉴频鉴相器和外同步接口，其中，所述第N+1个鉴频鉴相器通过所述外同步接口与外部时钟源连接，
    所述第N+1个鉴频鉴相器用于接收所述外部时钟源产生的时钟信号，确定所述外部时钟源产生的时钟信号与所述公共时钟信号之间的第N+1相位差值信息，并且向所述N个滤波器中的第j滤波器发送所述第N+1相位差值信息；
    所述第j滤波器用于接收所述第N+1个鉴频鉴相器发送的所述第N+1相位差值信息，将所述第N+1相位差值信息转化为第N+1频率差值信息，并且向所述N个时钟重构器中与所述第j滤波器对应的第j时钟重构器发送所述第N+1频率差值信息；
    所述第j时钟重构器用于接收所述第j滤波器发送的所述第N+1频率差值信息，根据所述公共时钟信号和所述第N+1频率差值信息，在所述设备内重构第N+1网络定时时钟，并且向所述N个时钟域接口中的第j时钟域接口发送所述第N+1网络定时时钟；
    其中，所述j为整数且满足1≤j≤N。
  3. 根据权利要求2所述的设备，其特征在于，所述设备还包括：第N+1个时钟重构器，
    所述N个滤波器中的第k滤波器还用于向所述第N+1个时钟重构器发送所述第k滤波器产生的第k频率差值信息；
    所述第N+1个时钟重构器用于接收所述第k滤波器发送的所述第k频率差值信息，根据所述第k频率差值信息，在所述设备内重构第k网络定时时钟，并且向所述外同步接口发送所述第k网络定时时钟；
    其中，所述k为整数且满足1≤k≤N。
  4. 根据权利要求1至3中任一项所述的设备，其特征在于，所述设备还包括：输入选择器，
    所述第i鉴频鉴相器具体用于：
    向所述输入选择器发送所述第i相位差值信息；
    所述输入选择器用于接收所述第i鉴频鉴相器发送的所述第i相位差值信息，并且基于所述第i鉴频鉴相器与所述第i滤波器的对应关系，向所述第i滤波器发送所述第i相位差值信息。
  5. 根据权利要求4所述的设备，其特征在于，所述输入选择器还用于：
    当所述N个时钟域接口的时钟源对应M种业务时，从所述N个鉴频鉴相器发送的相位差值信息中，选择M个相位差值信息，所述M个相位差值信息与所述M种业务一一对应，并且基于所述N个鉴频鉴相器与所述N个滤波器的对应关系，向所述N个滤波器中的每个滤波器发送对应的相位差值信息，其中，所述M为小于所述N的整数。
  6. 根据权利要求1至5中任一项所述的设备，其特征在于，所述设备还包括：输出选择器，
    所述第i滤波器具体用于：
    向所述输出选择器发送所述第i频率差值信息；
    所述输出选择器用于接收所述第i滤波器发送的所述第i频率差值信息， 并且基于所述第i滤波器与所述第i时钟重构器的对应关系，向所述第i时钟重构器发送所述第i频率差值信息。
  7. 根据权利要求1至6中任一项所述的设备，其特征在于，所述设备还包括：
    公共时钟产生器，用于在所述确定公共时钟信号与所述时钟信号之间的第i相位差值信息之前，产生所述公共时钟信号，并且向所述第i鉴频鉴相器和所述第i时钟重构器发送所述公共时钟信号。
  8. 一种支持多时钟域时钟传递的方法，其特征在于，包括：
    N个鉴频鉴相器中的第i鉴频鉴相器接收与所述第i鉴频鉴相器连接的时钟源产生的时钟信号，确定公共时钟信号与所述时钟信号之间的第i相位差值信息，并且向N个滤波器中与所述第i鉴频鉴相器对应的第i滤波器发送所述第i相位差值信息；
    所述第i滤波器接收所述第i鉴频鉴相器发送的所述第i相位差值信息，将所述第i相位差值信息转化为第i频率差值信息，并且向N个时钟重构器中与所述第i滤波器对应的第i时钟重构器发送所述第i频率差值信息；
    所述第i时钟重构器接收所述第i滤波器发送的所述第i频率差值信息，根据所述公共时钟信号和所述第i频率差值信息，在所述设备内重构第i网络定时时钟，并且向N个时钟域接口中的第i时钟域接口发送所述第i网络定时时钟；
    其中，所述N为大于或等于2的整数，所述N个时钟域接口分别与所述N个鉴频鉴相器、所述N个滤波器以及所述N个时钟重构器一一对应，所述N个鉴频鉴相器分别与N个时钟源连接，且所述N个时钟源中的至少两个时钟源不相同，所述i为整数且满足1≤i≤N。
  9. 根据权利要求8所述的方法，其特征在于，所述方法还包括：
    第N+1个鉴频鉴相器接收外部时钟源产生的时钟信号，确定所述外部时钟源产生的时钟信号与所述公共时钟信号之间的第N+1相位差值信息，并且向所述N个滤波器中的第j滤波器发送所述第N+1相位差值信息；
    所述第j滤波器接收所述第N+1个鉴频鉴相器发送的所述第N+1相位差值信息，将所述第N+1相位差值信息转化为第N+1频率差值信息，并且向所述N个时钟重构器中与所述第j滤波器对应的第j时钟重构器发送所述第N+1频率差值信息；
    所述第j时钟重构器接收所述第j滤波器发送的所述第N+1频率差值信息，根据所述公共时钟信号和所述第N+1频率差值信息，在所述设备内重构第N+1网络定时时钟，并且向所述N个时钟域接口中的第j时钟域接口发送所述第N+1网络定时时钟；
    其中，所述第N+1个鉴频鉴相器通过外同步接口与所述外部时钟源连接，所述j为整数且满足1≤j≤N。
  10. 根据权利要求9所述的方法，其特征在于，所述方法还包括：
    所述N个滤波器中的第k滤波器向第N+1个时钟重构器发送所述第k滤波器产生的第k频率差值信息；
    所述第N+1个时钟重构器接收所述第k滤波器发送的所述第k频率差值信息，根据所述第k频率差值信息，在所述设备内重构第k网络定时时钟，并且向所述外同步接口发送所述第k网络定时时钟，其中，所述k为整数且满足1≤k≤N。
  11. 根据权利要求8至10中任一项所述的方法，其特征在于，所述向所述N个滤波器中与所述第i鉴频鉴相器对应的第i滤波器发送所述第i相位差值信息，包括：
    所述第i鉴频鉴相器向输入选择器发送所述第i相位差值信息；
    所述输入选择器接收所述第i鉴频鉴相器发送的所述第i相位差值信息，并且基于所述第i鉴频鉴相器与所述第i滤波器的对应关系，向所述第i滤波器发送所述第i相位差值信息。
  12. 根据权利要求11所述的方法，其特征在于，在所述输入选择器接收所述第i鉴频鉴相器发送的所述第i相位差值信息之后，所述方法还包括：
    当所述N个时钟域接口的时钟源对应M种业务时，所述输入选择器从所述N个鉴频鉴相器发送的相位差值信息中，选择M个相位差值信息，所述M个相位差值信息与所述M种业务一一对应；
    所述向所述第i滤波器发送所述第i相位差值信息，包括：
    基于所述N个鉴频鉴相器与所述N个滤波器的对应关系，向所述N个滤波器中的每个滤波器发送对应的相位差值信息；
    其中，所述M为小于所述N的整数。
  13. 根据权利要求8至12中任一项所述的方法，其特征在于，所述向所述N个时钟重构器中与所述第i滤波器对应的第i时钟重构器发送所述第 i频率差值信息，包括：
    所述第i滤波器向输出选择器发送所述第i频率差值信息；
    所述输出选择器接收所述第i滤波器发送的第i频率差值信息，并且基于所述第i滤波器与所述第i时钟重构器的对应关系，向所述第i时钟重构器发送所述第i频率差值信息。
  14. 根据权利要求8至13中任一项所述的方法，其特征在于，在所述确定公共时钟信号与所述时钟信号之间的第i相位差值信息之前，所述方法还包括：
    公共时钟产生器产生所述公共时钟信号，并且向所述第i鉴频鉴相器和所述第i时钟重构器发送所述公共时钟信号。
PCT/CN2016/076106 2016-03-11 2016-03-11 支持多时钟域时钟传递的设备和方法 Ceased WO2017152412A1 (zh)

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