WO2017157244A1 - Oled显示面板以及oled显示面板的制造方法 - Google Patents

Oled显示面板以及oled显示面板的制造方法 Download PDF

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Publication number
WO2017157244A1
WO2017157244A1 PCT/CN2017/076181 CN2017076181W WO2017157244A1 WO 2017157244 A1 WO2017157244 A1 WO 2017157244A1 CN 2017076181 W CN2017076181 W CN 2017076181W WO 2017157244 A1 WO2017157244 A1 WO 2017157244A1
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Prior art keywords
insulating layer
storage capacitor
switching transistor
interlayer insulating
driving transistor
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Ceased
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PCT/CN2017/076181
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English (en)
French (fr)
Inventor
张婷婷
黄秀颀
胡思明
朱晖
朱涛
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kunshan New Flat Panel Display Technology Center Co Ltd
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Kunshan New Flat Panel Display Technology Center Co Ltd
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Priority to KR1020187017859A priority Critical patent/KR102123502B1/ko
Priority to EP17765786.3A priority patent/EP3432359B1/en
Priority to JP2018527181A priority patent/JP6616900B2/ja
Priority to US15/779,410 priority patent/US10446445B2/en
Publication of WO2017157244A1 publication Critical patent/WO2017157244A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H10D86/443—Interconnections, e.g. scanning lines adapted for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an OLED display panel and a method of fabricating the OLED display panel.
  • OLED organic light emitting diode
  • FIG. 1 is a pixel circuit diagram of a conventional OLED display panel.
  • the most basic pixel circuit includes a switching transistor T1, a driving transistor T2 and a storage capacitor Cs, and a gate of the switching transistor T1 is connected to a scan line Sn, the switch
  • the source of the transistor T1 is connected to the data line Dm
  • the drain of the switching transistor T1 the gate of the driving transistor T2 and the first plate of the storage capacitor Cs are connected to the node N1
  • the second plate of the storage capacitor Cs is connected to the first power source VDD
  • the drain of the driving transistor T2 is connected to the anode of the organic light emitting diode OLED
  • the cathode of the organic light emitting diode OLED is connected to the second power source VSS.
  • the switching transistor T1 When the switching transistor T1 is turned on by the scan line Sn, the data voltage supplied from the data line Dm is stored to the storage capacitor Cs via the switching transistor T1, thereby controlling the driving transistor T2 to generate a current to drive the organic light emitting diode OLED to emit light. .
  • the resolution of a conventional OLED display panel is generally below 250 PPI (PPI indicates the number of pixels per inch, and the higher the PPI value, the higher the pixel density of the display), the higher resolution is not satisfied.
  • PPI indicates the number of pixels per inch, and the higher the PPI value, the higher the pixel density of the display
  • the pursuit of the rate display is because the improvement of the resolution requires the same layer spacing, such as the distance between adjacent data lines to be reduced.
  • Data line crosstalk refers to the coupling between two data lines.
  • the mutual inductance and mutual capacitance between the two data lines cause noise on the data lines.
  • a short circuit of a data line means that two data lines are connected to each other, so that the pixel electrode cannot receive a normal signal and is defective. Under the same process conditions, the closer the distance between the two data lines, the greater the probability of a short circuit between each other.
  • An object of the present invention is to solve the problem of low resolution of a conventional organic light emitting display.
  • Another object of the present invention is to eliminate crosstalk and short circuit between data lines of an organic light emitting display.
  • the present invention provides an OLED display panel including scan lines, data lines, and power lines formed on a substrate, the scan lines and data lines defining a plurality of pixel groups arranged in a matrix manner.
  • Each sub-pixel has two sub-pixels.
  • the two sub-pixels in the same pixel group are connected to the same power line and are arranged along the power line.
  • the data lines connected to the two sub-pixels in the same pixel group are located on different structural layers.
  • two sub-pixels in each pixel group are a first sub-pixel and a second sub-pixel, respectively, the first sub-pixel includes a first storage capacitor, and the second The subpixel includes a second storage capacitor.
  • an upper plate of the first storage capacitor and an upper plate of the second storage capacitor are located on different structural layers.
  • the first sub-pixel further includes a first switching transistor and a first driving transistor
  • the second sub-pixel further includes a second switching transistor and a second driving transistor.
  • a source of the first switching transistor is connected to the first data line
  • a source of the second switching transistor is connected to the second data line
  • the first data line, the second data line and the power line are parallel to each other
  • the scan line And the power line are perpendicular to each other
  • the first data line and the second data line, the first storage capacitor and the second storage capacitor, the first switching transistor and the second switching transistor, the first The drive transistor and the second drive transistor are both mirror symmetrical along the power line.
  • the method specifically includes:
  • a silicon island formed on the substrate to serve as an active layer of the first switching transistor, the first driving transistor, the second switching transistor, and the second driving transistor;
  • the first via hole for turning on a drain of the first switching transistor and a first storage capacitor a plate and a drain of the second switching transistor and a lower plate of the second storage capacitor;
  • a patterned first metal layer is formed on the gate insulating layer to serve as a scan line, a lower plate of the first storage capacitor, a lower plate of the second storage capacitor, a gate of the first switching transistor, and a gate a gate of the driving transistor, a gate of the second switching transistor, and a gate of the second driving transistor;
  • first interlayer insulating layer is formed on the gate insulating layer and the patterned first metal layer, and the second via hole is used to turn on the first layer a data line and a source of the first switching transistor;
  • a patterned second metal layer is formed on the first interlayer insulating layer for serving as the first data line, a source of the first switching transistor, and an upper plate of the second storage capacitor;
  • a patterned third metal layer is formed on the second interlayer insulating layer to serve as a second data line, a source of the second switching transistor, and an upper plate of the first storage capacitor;
  • the fourth via hole is used for conducting a source and a drain of the first driving transistor, a source and a drain of the second driving transistor, a power supply line, an upper plate of the first storage capacitor, and an upper plate of the second storage capacitor;
  • a patterned fourth metal layer is formed on the third interlayer insulating layer to serve as a source and a drain of the first driving transistor, a source and a drain of the second driving transistor, and a power supply line;
  • the passivation insulating layer is formed on the third interlayer insulating layer and the patterned fourth metal layer, wherein the contact hole is used to turn on the drain of the first driving transistor a pole and an anode of the first organic light emitting diode, a drain of the second driving transistor, and a second organic light emitting diode anode.
  • an opening is further included, the opening penetrating the second interlayer insulating layer and facing the lower plate of the first storage capacitor.
  • the upper plate of the first storage capacitor and the upper plate of the second storage capacitor are located on the same structural layer.
  • the method specifically includes:
  • a silicon island formed on the substrate to serve as an active layer of the first switching transistor, the first driving transistor, the second switching transistor, and the second driving transistor;
  • the first via hole for turning on a drain of the first switching transistor and a first storage capacitor a plate and a drain of the second switching transistor and a lower plate of the second storage capacitor;
  • a patterned first metal layer is formed on the gate insulating layer to serve as a scan line, a lower plate of the first storage capacitor, a lower plate of the second storage capacitor, a gate of the first switching transistor, and a gate a gate of the driving transistor, a gate of the second switching transistor, and a gate of the second driving transistor;
  • first interlayer insulating layer is formed on the gate insulating layer and the patterned first metal layer, and the second via hole is used to turn on the first layer a data line and a source of the first switching transistor;
  • a patterned second metal layer formed on the first interlayer insulating layer for serving as the first data line, a source of the first switching transistor, an upper plate of the first storage capacitor, and a second storage The upper plate of the capacitor;
  • a patterned third metal layer is formed on the second interlayer insulating layer for serving as a source of the second data line and the second switching transistor;
  • the fourth via hole is used for conducting a source and a drain of the first driving transistor, a source and a drain of the second driving transistor, a power supply line, an upper plate of the first storage capacitor, and an upper plate of the second storage capacitor;
  • a patterned fourth metal layer is formed on the third interlayer insulating layer to serve as a source and a drain of the first driving transistor, a source and a drain of the second driving transistor, and a power supply line;
  • the passivation insulating layer is formed on the third interlayer insulating layer and the patterned fourth metal layer, wherein the contact hole is used to turn on the drain of the first driving transistor
  • the pole is coupled to the anode of the first organic light emitting diode and the drain of the second driving transistor and the anode of the second organic light emitting diode.
  • the invention also provides a method for manufacturing an OLED display panel, comprising:
  • each pixel group has two sub-pixels, and two sub-pixels in the same pixel group are connected to the same power line and are arranged along the power line, and the data lines connected to the two sub-pixels in the same pixel group are located in different structural layers. on.
  • the two sub-pixels in each pixel group are respectively a first sub-pixel and a second sub-pixel, and the first sub-pixel includes a first storage capacitor.
  • the second sub-pixel includes a second storage capacitor, and an upper plate of the first storage capacitor and an upper plate of the second storage capacitor are located on different structural layers, and are formed by two processes.
  • the first sub-pixel further includes a first switching transistor and a first driving transistor
  • the second sub-pixel further includes a second switching transistor and a second driving a transistor
  • a source of the first switching transistor is connected to the first data line
  • a source of the second switching transistor is connected to the second data line
  • the first data line, the second data line and the power line are parallel to each other
  • the scan line and the power line are perpendicular to each other, and the first data line and the second data line, the first storage capacitor and the second storage capacitor, the first switching transistor and the second switching transistor, Both the first driving transistor and the second driving transistor are mirror symmetrical along the power line.
  • the OLED display panel is specifically formed by the following steps:
  • the patterned first metal layer is formed on the gate insulating layer, and is used as a scan line, a lower plate of the first storage capacitor, and a lower plate of the second storage capacitor a gate of the first switching transistor, a gate of the first driving transistor, a gate of the second switching transistor, and a gate of the second driving transistor;
  • first interlayer insulating layer formed on the gate insulating layer and the patterned first metal layer, and a second via hole for conducting the a first data line and a source of the first switching transistor;
  • the patterned third metal layer being formed on the second interlayer insulating layer for serving as a second data line, a source of the second switching transistor, and a first storage capacitor
  • a third interlayer insulating layer and a fourth via hole Forming a third interlayer insulating layer and a fourth via hole, wherein the third interlayer insulating layer is formed on the second interlayer insulating layer and the patterned third metal layer, wherein the fourth via hole is used for guiding Passing through a source and a drain of the first driving transistor, a source and a drain of the second driving transistor, a power supply line, an upper plate of the first storage capacitor, and an upper plate of the second storage capacitor;
  • the passivation insulating layer is formed on the third interlayer insulating layer and the patterned fourth metal layer, wherein the contact hole is used to turn on the drain of the first driving transistor
  • the pole is coupled to the anode of the first organic light emitting diode and the drain of the second driving transistor and the anode of the second organic light emitting diode.
  • the second interlayer insulation is formed After the layer, an opening is formed through the second interlayer insulating layer, the opening being opposite to the lower plate of the first storage capacitor.
  • the upper plate of the first storage capacitor and the upper plate of the second storage capacitor are located on the same structural layer, and are formed by one process.
  • the OLED display panel is specifically formed by the following steps:
  • the patterned first metal layer is formed on the gate insulating layer, and is used as a scan line, a lower plate of the first storage capacitor, and a lower plate of the second storage capacitor a gate of the first switching transistor, a gate of the first driving transistor, a gate of the second switching transistor, and a gate of the second driving transistor;
  • first interlayer insulating layer formed on the gate insulating layer and the patterned first metal layer, and a second via hole for conducting the a first data line and a source of the first switching transistor;
  • the patterned third metal layer is formed on the second interlayer insulating layer for serving as a source of the second data line and the second switching transistor;
  • a scan line, a data line and a power line VDD are included, and the scan line and the data line define a plurality of pixel groups arranged in a matrix, and each pixel group has two sub-pixels therein.
  • Two sub-pixels in the same pixel group are connected to the same power supply line VDD and arranged along the power supply line VDD, and the data lines respectively connected to the two sub-pixels in the same pixel group are located on different structural layers (ie, data connected by two sub-pixels respectively) Lines are not on the same floor).
  • the present invention since the present invention sets data lines corresponding to two sub-pixels in the same pixel group on different structural layers, the distance between adjacent data lines of the same layer is increased without reducing the pixel area. Doubled, so that the data lines not adjacent to each other are separated by the interlayer insulating layer, which can effectively reduce the probability of short circuit between the data lines, and greatly eliminate the crosstalk between the data lines in use, which not only improves The yield of the product is improved, and the picture quality of the product is improved.
  • the pixel area can be reduced based on the existing equipment and process conditions, the PPI of the OLED display panel is improved, and the OLED display panel is improved. Resolution.
  • the upper plate of the first storage capacitor and the upper plate of the second storage capacitor are located on different structural layers, and are formed by two processes, such as an upper plate of the first data line and the second storage capacitor. Formed together, and the second data line is formed together with the upper plate of the first storage capacitor, that is, the first data line and the upper plate of the first storage capacitor are not in the same layer, and the second data line and the second storage capacitor are The upper plates are not in the same layer, thereby facilitating the reduction of the spacing between the data lines of the same layer and the upper plates of the storage capacitors, which can further reduce the pixel area and improve the PPI of the OLED display panel.
  • 1 is a pixel circuit diagram of a conventional OLED display panel
  • FIG. 2a is a schematic plan view showing a pixel group of an OLED display panel forming a silicon island according to Embodiment 1 of the present invention
  • FIG. 2b is a schematic cross-sectional view showing a first sub-pixel of an OLED display panel after forming a silicon island according to Embodiment 1 of the present invention
  • 2c is a schematic cross-sectional view showing a second sub-pixel of an OLED display panel after forming a silicon island according to Embodiment 1 of the present invention
  • 3a is a schematic plan view showing a pixel group of an OLED display panel forming a first through hole according to Embodiment 1 of the present invention
  • FIG. 3b is a cross-sectional view showing the first sub-pixel of the OLED display panel after forming the first via hole according to the first embodiment of the present invention
  • 3c is a cross-sectional view showing the second sub-pixel of the OLED display panel after forming the first via hole in the first embodiment of the present invention
  • FIG. 4a is a schematic plan view showing a pixel group of an OLED display panel after forming a first metal layer according to Embodiment 1 of the present invention
  • 4b is a cross-sectional view showing the first sub-pixel of the OLED display panel after forming the first metal layer in the first embodiment of the present invention
  • 4c is a schematic cross-sectional view showing a second sub-pixel of an OLED display panel after forming a first metal layer according to Embodiment 1 of the present invention
  • FIG. 5a is a schematic plan view showing a pixel group of a OLED display panel forming a second through hole according to Embodiment 1 of the present invention
  • FIG. 5b is a cross-sectional view showing the first sub-pixel of the OLED display panel after forming the second via hole according to the first embodiment of the present invention
  • 5c is a schematic cross-sectional view showing a second sub-pixel of the OLED display panel after forming a second via hole according to the first embodiment of the present invention
  • FIG. 6 is a schematic plan view showing a pixel group of an OLED display panel after forming a second metal layer according to Embodiment 1 of the present invention.
  • 6b is a schematic cross-sectional view showing a first sub-pixel of an OLED display panel after forming a second metal layer according to Embodiment 1 of the present invention
  • 6c is a second sub-pixel of the OLED display panel after forming the second metal layer in the first embodiment of the present invention Schematic diagram of the section;
  • FIG. 7 is a schematic plan view showing a pixel group of an OLED display panel after forming a third through hole according to Embodiment 1 of the present invention.
  • FIG. 7b is a cross-sectional view showing the first sub-pixel of the OLED display panel forming a third via hole according to the first embodiment of the present invention.
  • Figure 7c is a cross-sectional view showing the second sub-pixel of the OLED display panel in the first embodiment of the present invention.
  • FIG. 8 is a schematic plan view showing a pixel group of an OLED display panel after forming a third metal layer according to Embodiment 1 of the present invention.
  • FIG. 8b is a cross-sectional view showing the first sub-pixel of the OLED display panel after forming a third metal layer according to the first embodiment of the present invention.
  • 8c is a cross-sectional view showing a second sub-pixel of the OLED display panel in the first embodiment of the present invention after forming a third metal layer;
  • FIG. 9 is a schematic plan view showing a pixel group of an OLED display panel forming a fourth via hole according to Embodiment 1 of the present invention.
  • 9b is a cross-sectional view showing the first sub-pixel of the OLED display panel after forming a fourth via hole according to the first embodiment of the present invention.
  • 9c is a cross-sectional view showing a second sub-pixel of the OLED display panel after forming a fourth via hole according to the first embodiment of the present invention.
  • 10a is a schematic plan view showing a pixel group of an OLED display panel after forming a fourth metal layer according to Embodiment 1 of the present invention
  • FIG. 10b is a cross-sectional view showing the first sub-pixel of the OLED display panel in the first embodiment of the present invention after forming a fourth metal layer;
  • 10c is a schematic cross-sectional view showing a second sub-pixel of the OLED display panel after forming a fourth metal layer according to Embodiment 1 of the present invention
  • FIG. 11 is a schematic plan view showing a pixel group of an OLED display panel after forming a contact hole according to Embodiment 1 of the present invention.
  • FIG. 11b is a cross-sectional view showing the first sub-pixel of the OLED display panel after forming a contact hole according to the first embodiment of the present invention.
  • Figure 11c is a cross-sectional view showing the second sub-pixel of the OLED display panel after forming a contact hole in the first embodiment of the present invention
  • FIG. 12 is a schematic plan view showing a pixel group of an OLED display panel after forming an anode according to Embodiment 1 of the present invention.
  • 12b is a cross-sectional view showing the first sub-pixel of the OLED display panel after forming an anode according to the first embodiment of the present invention
  • 12c is a cross-sectional view showing the second sub-pixel of the OLED display panel after forming an anode according to the first embodiment of the present invention
  • FIG. 13a is a schematic plan view showing a pixel group of an OLED display panel after forming a silicon island according to Embodiment 2 of the present invention
  • 13b is a cross-sectional view showing a first sub-pixel of an OLED display panel after forming a silicon island according to Embodiment 2 of the present invention
  • 13c is a cross-sectional view showing a second sub-pixel of an OLED display panel after forming a silicon island according to Embodiment 2 of the present invention.
  • FIG. 14a is a schematic plan view showing a pixel group of an OLED display panel forming a first through hole according to Embodiment 2 of the present invention
  • FIG. 14b is a cross-sectional view showing the first sub-pixel of the OLED display panel in the first embodiment of the present invention.
  • 14c is a cross-sectional view showing the second sub-pixel of the OLED display panel in the first embodiment of the present invention.
  • 15a is a schematic plan view showing a pixel group of an OLED display panel after forming a first metal layer according to Embodiment 2 of the present invention
  • 15b is a cross-sectional view showing the first sub-pixel of the OLED display panel in the first embodiment of the present invention after forming the first metal layer;
  • Figure 15c is a cross-sectional view showing the second sub-pixel of the OLED display panel in the second embodiment of the present invention after forming the first metal layer;
  • FIG. 16 is a schematic plan view showing a pixel group of an OLED display panel in a second through hole according to Embodiment 2 of the present invention.
  • 16b is a second sub-pixel of the OLED display panel in the second embodiment of the present invention Schematic diagram of the section;
  • 16c is a cross-sectional view showing the second sub-pixel of the OLED display panel in the second embodiment of the present invention.
  • 17a is a schematic plan view showing a pixel group of an OLED display panel forming a second metal layer according to Embodiment 2 of the present invention.
  • 17b is a cross-sectional view showing the first sub-pixel of the OLED display panel after forming the second metal layer in the second embodiment of the present invention
  • Figure 17c is a cross-sectional view showing the second sub-pixel of the OLED display panel in the second embodiment of the present invention after forming a second metal layer;
  • FIG. 18 is a schematic plan view showing a pixel group of a OLED display panel in a second through hole according to Embodiment 2 of the present invention.
  • FIG. 18b is a cross-sectional view showing the first sub-pixel of the OLED display panel in the second embodiment of the present invention.
  • 18c is a cross-sectional view showing a second sub-pixel of the OLED display panel in the second embodiment of the present invention.
  • 19a is a schematic plan view showing a pixel group of an OLED display panel forming a third metal layer according to Embodiment 2 of the present invention.
  • 19b is a cross-sectional view showing the first sub-pixel of the OLED display panel in the second embodiment of the present invention after forming a third metal layer;
  • 19c is a cross-sectional view showing the second sub-pixel of the OLED display panel in the second embodiment of the present invention after forming a third metal layer;
  • 20a is a schematic plan view showing a pixel group of an OLED display panel forming a fourth through hole according to Embodiment 2 of the present invention.
  • Figure 20b is a cross-sectional view showing the first sub-pixel of the OLED display panel in the second embodiment of the present invention.
  • Figure 20c is a cross-sectional view showing the second sub-pixel of the OLED display panel in the second embodiment of the present invention.
  • 21a is a schematic plan view showing a pixel group of an OLED display panel after forming a fourth metal layer according to Embodiment 2 of the present invention.
  • FIG. 21b is a cross-sectional view showing the first sub-pixel of the OLED display panel in the second embodiment of the present invention after forming a fourth metal layer;
  • 21c is a cross-sectional view showing a second sub-pixel of the OLED display panel in the second embodiment of the present invention after forming a fourth metal layer;
  • 22a is a schematic plan view showing a pixel group of an OLED display panel after forming a contact hole according to Embodiment 2 of the present invention
  • Figure 22b is a cross-sectional view showing the first sub-pixel of the OLED display panel after forming a contact hole in the second embodiment of the present invention
  • Figure 22c is a cross-sectional view showing the second sub-pixel of the OLED display panel in the second embodiment of the present invention after forming a contact hole;
  • 23a is a schematic plan view showing a pixel group of an OLED display panel forming an anode according to Embodiment 2 of the present invention.
  • 23b is a cross-sectional view showing the first sub-pixel of the OLED display panel in the second embodiment of the present invention after forming an anode;
  • Figure 23c is a cross-sectional view showing the second sub-pixel of the OLED display panel in the second embodiment of the present invention.
  • a first switching transistor -T11 a gate of the first switching transistor -G11; a source of the first switching transistor -S11; a drain of the first switching transistor -D11;
  • a first driving transistor -T12 a gate of the first driving transistor -G12; a source of the first driving transistor -S12; a drain of the first driving transistor -D12;
  • a second switching transistor -T21 a gate of the second switching transistor -G21; a source of the second switching transistor -S21; a drain of the second switching transistor -D21;
  • a second driving transistor -T22 a gate of the second driving transistor -G22; a source of the second driving transistor -S22; a drain of the second driving transistor -D22;
  • a first storage capacitor -C1 a lower plate of the first storage capacitor -C1-1; an upper plate of the first storage capacitor -C1-2;
  • a second storage capacitor -C2 a lower plate of the second storage capacitor - C2-1; an upper plate of the second storage capacitor - C2-2;
  • the first segment of the silicon island is -111-1; the second segment of the silicon island is -111-2; the third segment of the silicon island is -112-1; the fourth segment of the silicon island is -112-2; the fifth segment of the silicon island -113; the sixth paragraph of the silicon island -114;
  • a second interlayer insulating layer -160 a third via hole -160a-2; an opening -160b;
  • An anode-221 of the first organic light emitting diode an anode-222 of the second organic light emitting diode.
  • the core idea of the present invention is to provide an OLED display panel including a scan line, a data line, and a power line VDD, and the scan line and the data line define a plurality of arrays arranged in a matrix manner.
  • a pixel group having two sub-pixels in each pixel group, two sub-pixels in the same pixel group are connected to the same power line VDD and arranged along the power line VDD, and the data lines respectively connected to the two sub-pixels in the same pixel group are located.
  • the probability of a short circuit between the lines, and the crosstalk between the data lines can be largely eliminated.
  • the pixel area can be reduced based on existing equipment and process conditions, and the PPI of the OLED display panel is improved, thereby improving the resolution of the OLED display panel. rate.
  • FIG. 12a is a schematic plan view of a pixel group of an OLED display panel according to Embodiment 1 of the present invention, which reflects the structure of two sub-pixels
  • FIG. 12b is a cross-sectional view of the first sub-pixel of FIG. 12a
  • Figure 12c is a cross-sectional view of the second sub-pixel of Figure 12a.
  • the main structure of the OLED display panel of the present embodiment includes scan lines, data lines, and power lines formed on the substrate 100, the scan lines and data lines defining a matrix arrangement. a plurality of pixel groups each having two sub-pixels, two sub-pixels in the same pixel group being connected to the same power supply line VDD and mirrored along the power supply line VDD, and data connected by two sub-pixels in the same pixel group
  • the lines are on different structural layers.
  • the present embodiment will respectively refer to two sub-pixels arranged up and down in a direction parallel to the plane of the paper as a first sub-pixel and a second sub-pixel, respectively, wherein the lower side is located on the lower side.
  • the sub-pixel is referred to as a first sub-pixel
  • the sub-pixel located on the upper side is referred to as a second sub-pixel
  • the data line connected to the source of the switching transistor of the first sub-pixel is referred to as a first data line D1
  • a second sub-pixel The data line to which the source of the switching transistor of the pixel is connected is referred to as a second data line D2.
  • the first data line D1 is located below the second interlayer insulating layer 160 (specifically between the first interlayer insulating layer 140 and the second layer). Between the insulating layers 160, the first data line D1 is connected to the source S11 of the first switching transistor through a through hole (here, the second through hole -140a-1) penetrating through the first interlayer insulating layer 140; The second data line D2 is located above the second interlayer insulating layer 160 (specifically between the second interlayer insulating layer 160 and the third interlayer insulating layer 180), and the second data line D2 passes through the first The via holes of the interlayer insulating layer 140 and the second interlayer insulating layer -160 (herein referred to as the third via holes 160a-2) are connected to the source-S21 of the second switching transistor; that is, the first data lines D1 and The two data lines D2 are respectively located on two sides of the second inter
  • Line D2 is connected to the source of the switching transistor through vias of different depths.
  • an interlayer insulating layer here specifically refers to the second Interlayer insulation layer 160
  • the data lines corresponding to the two sub-pixels in the same pixel group are disposed on different structural layers (the distance between adjacent data lines of the same layer is increased), it is not necessarily limited by existing equipment and process conditions. , to reduce the pixel area and improve the PPI of the OLED display panel.
  • the first sub-pixel includes a first switching transistor T11, The first driving transistor T12 and the first storage capacitor C1.
  • the first switching transistor T11 includes a gate G11, a source S11, a drain D11, and an active layer 111-1 (ie, a first segment of a silicon island).
  • the first driving transistor T12 includes a gate G12, a source S12, a drain D12, and an active layer 111-2 (ie, a second segment of the silicon island).
  • the first storage capacitor C1 includes a first plate (ie, a lower plate C1-1), a second plate (ie, an upper plate C1-2), and a lower plate C1-1 and an upper plate C1- A first interlayer insulating layer 140 between the two.
  • the gate G11 of the first switching transistor T11 is connected to the scan line Sn (the two are actually integrated structures), and the source S11 of the first switching transistor T11 is connected to the first data line D1 (both actual The upper switching structure T11, the drain D11 of the first switching transistor T11, the first plate of the first storage capacitor C1 (ie, the lower plate C1-1), and the gate G12 of the first driving transistor T12 are connected.
  • the source S12 of the first driving transistor T12 and the second plate of the first storage capacitor C1 are both connected to the power line VDD, and the drain D12 and the first of the first driving transistor T12 An anode 221 of an organic light emitting diode is connected.
  • the scan line Sn is used to provide an on or off voltage to the first switching transistor T11, and the first driving transistor T12 is configured to control the first data line D1 to supply a data voltage to the first organic light emitting diode.
  • the second sub-pixel includes a second switching transistor T21, a second driving transistor T22, and a second storage capacitor C2.
  • the second switching transistor T21 includes a gate G21, a source S21, a drain D21, and an active layer 112-1 (ie, a third segment of the silicon island).
  • the second driving transistor T22 includes a gate G22, a source S22, a drain D22, and an active layer 112-2 (ie, a fourth segment of the silicon island).
  • the second storage capacitor C2 includes a first plate (ie, a lower plate C2-1), a second plate (ie, an upper plate C2-2), and a lower plate C2-1 and an upper plate C2-.
  • the gate G21 of the second switching transistor T21 is connected to the scan line Sn (the two are actually integrated structures), and the source S21 of the second switching transistor T21 is connected to the second data line D2 (both actual The upper switching structure T21, the drain D21 of the second switching transistor T21, the first plate of the second storage capacitor C2 (ie, the lower plate C2-1), and the gate G22 of the second driving transistor T22 are connected.
  • the source S22 of the second driving transistor T22 and the second plate of the second storage capacitor C2 are both connected to the power line VDD, and the drain D22 and the second of the second driving transistor T22
  • the anode 222 of the two organic light emitting diodes is connected.
  • the scan line Sn is for supplying an on or off voltage to the second switching transistor T21, and the second driving transistor T22 is for controlling the second data line D2 to supply a data voltage to the second organic light emitting diode.
  • the first data line D1, the second data line D2 and the power line VDD are parallel to each other, the scan line Sn is perpendicular to the power line VDD, and the first data line D1 And the second data line D2 is mirror symmetrical along the power line VDD.
  • the first storage capacitor C1 and the second storage capacitor C2 are mirror-symmetrical along the power line VDD
  • the first switching transistor T11 and the second switching transistor T21 are mirror-symmetrical along the power line VDD
  • the first driving transistor T12 and The second driving transistor T22 is mirror symmetrical along the power supply line VDD.
  • the lower plate C1-1 of the first storage capacitor C1 and the lower plate C2-1 of the second storage capacitor C2 are both rectangular and have the same area and are mirror-symmetrical along the power line VDD.
  • the upper plate C1-2 of the first storage capacitor C1 and the upper plate C2-2 of the second storage capacitor C2 are both rectangular and have the same area and are mirror-symmetrical along the power line VDD.
  • the OLED display panel further includes a silicon island formed on the substrate 100 to serve as a first switching transistor T11, a first driving transistor T12, and a second An active layer of the switching transistor T21 and the second driving transistor T22.
  • the OLED display panel further includes a gate insulating layer 120 and first via holes 120a-1, 120a-2.
  • the gate insulating layer 120 is formed on the substrate 100 and the silicon island.
  • the first via hole 120a-1, 120a-2 penetrates the gate insulating layer 120, and the first via hole 120a-1 is used to turn on the drain D11 of the first switching transistor T11 and the first storage capacitor.
  • the lower plate C1-1 of C1 is used to turn on the drain D21 of the second switching transistor T21 and the lower plate C2-1 of the second storage capacitor C2.
  • the OLED display panel further includes a patterned first metal layer, and the patterned first metal layer is formed on the gate insulating layer 120 for use as a first
  • the OLED display panel further includes a first interlayer insulating layer 140 and a second via hole 140a-1, and the first interlayer insulating layer 140 is formed on the gate insulating layer.
  • the second via hole 140a-1 is configured to turn on the first data line D1 and the source S11 of the first switching transistor T11.
  • the OLED display panel further includes a graphic second gold.
  • a patterned second metal layer is formed on the first interlayer insulating layer 140 to serve as a first data line D1, a source S11 of the first switching transistor T11, and a second storage capacitor C2.
  • the second electrode ie, the upper plate C2-2).
  • the OLED display panel further includes a second interlayer insulating layer 160 and a third via hole 160a-2, and the second interlayer insulating layer 160 is formed on the first layer.
  • the third via hole 160a-2 is used to turn on the second data line D2 and the source S21 of the second switching transistor T21 on the insulating layer 140 and the patterned second metal layer.
  • the OLED display panel further includes an opening 160b penetrating the second interlayer insulating layer 160 and facing the lower plate C1-1 of the first storage capacitor C1.
  • the OLED display panel further includes a patterned third metal layer, the patterned third metal layer is formed on the second interlayer insulating layer 160, and The opening 160b serves as the second data line D2, the source S21 of the second switching transistor T21, and the second electrode of the first storage capacitor C1 (ie, the upper plate C1-2).
  • the OLED display panel further includes a third interlayer insulating layer 180 and fourth via holes 180a, 180a-1, 180a-2, 180a-3, and 180a-4.
  • a third interlayer insulating layer 180 is formed on the second interlayer insulating layer 160 and the patterned third metal layer, and the fourth via holes 180a, 180a-1, 180a-2, 180a-3, 180a- 4 for turning on the source and drain of the first driving transistor T12, the source and drain of the second driving transistor T22, the power supply line VDD, the upper plate C1-2 of the first storage capacitor C1, and the second storage capacitor Upper plate C2-2 of C2.
  • the OLED display panel further includes a patterned fourth metal layer, and the patterned fourth metal layer is formed on the third interlayer insulating layer 180.
  • the OLED display panel further includes a passivation insulating layer 200 and contact holes 200a-1, 200a-2, and the passivation insulating layer 200 is formed in the third interlayer insulating layer.
  • the contact hole 200a-1 is used to turn on the drain of the first driving transistor T12 and the anode 221 of the first organic light emitting diode, the contact hole 200a-2
  • the anode 222 for turning on the drain of the second driving transistor T22 and the second organic light emitting diode.
  • the photolithography process referred to in the present invention includes a photoresist coating, a mask, an exposure, an etching, and a photoresist stripping process, and the photoresist is A positive photoresist is taken as an example.
  • FIG. 2a is a schematic plan view of a pixel group of an OLED display panel after forming a silicon island according to the first embodiment of the present invention
  • FIG. 2b is a schematic cross-sectional view of the first sub-pixel of the OLED display panel after forming a silicon island according to the first embodiment of the present invention
  • 2c is a schematic cross-sectional view of the second sub-pixel of the OLED display panel in the first embodiment of the present invention after forming a silicon island.
  • the substrate 100 is generally a transparent substrate.
  • the transparent substrate may be a rigid substrate or a flexible substrate, such as a transparent glass substrate or a transparent plastic substrate.
  • the shape of the transparent substrate may be a flat surface, a curved surface or other irregular shapes. It should be understood that the material and shape of the transparent substrate are not limited herein.
  • a silicon island is formed on the substrate 100.
  • the specific process for forming a silicon island includes: forming an amorphous silicon layer (a-Si) on the substrate 100 by a chemical vapor deposition (CVD) process; and excimer laser annealing (ELA) on the amorphous silicon layer.
  • a process such as solid phase crystallization (SPC) or metal induced crystallization (MIC), which is converted into a polysilicon layer (P-Si); a first photolithography process is performed to pattern the polysilicon layer to form a silicon island.
  • the silicon island is used as an active layer of the first switching transistor T11, an active layer of the first driving transistor T12, an active layer of the second switching transistor T21, and an active layer of the second driving transistor T22.
  • the silicon islands correspond to respective source and drain positions of the first switching transistor T11, the first driving transistor T12, the second switching transistor T21, and the second driving transistor T22.
  • the silicon island includes a first segment 111-1, a second segment 111-2, a third segment 112-1, a fourth segment 112-2, and a fifth segment 113.
  • the above six parts are substantially strip-shaped, and the first segment 111-1, the second segment 111-2, the third segment 112-1, the fourth segment 112-2, and the fifth segment 113 are along the X The direction extends while the sixth section 114 extends in the Y direction.
  • the first segment 111-1 and the third segment 112-1 are independent strip structures, and the first segment 111-1 is used as an active layer of the first switching transistor T11 in the first sub-pixel, and the third segment 112 is used.
  • the fifth segment 113 is located between the second segment 111-2 and the fourth segment 112-2, the second segment 111-2 and the fourth segment 112-2 are mirror-symmetrical, and the sixth segment 114 is connected to the second segment 111-2.
  • the shape of the silicon island may be appropriately changed.
  • the active layers of the first driving transistor T12 and the second driving transistor T22 may also have the same two opening directions.
  • the "U" type structure ie, the first driving transistor T12 and the second driving transistor T22 do not share the active layer, and the present invention does not limit the specific shape of the silicon island.
  • a buffer layer 101 is formed on the substrate 100, and the buffer layer 101 is made of, for example, silicon nitride or silicon oxide.
  • a second photolithography process is performed to ion implant a predetermined region of the silicon island, as shown by a broken line in FIG. 2a, this embodiment is for the first switching transistor
  • the drain region of T11 and the drain region of the second switching transistor T21 are ion-implanted to make their conduction performance better.
  • FIG. 3a is a schematic plan view showing a pixel group of the OLED display panel forming a first via hole in the first embodiment of the present invention
  • FIG. 3b is a schematic view of the first sub-pixel of the OLED display panel in the first embodiment of the present invention
  • FIG. 3c is a cross-sectional view showing the second sub-pixel of the OLED display panel in the first embodiment of the present invention after the first via hole is formed.
  • a gate insulating layer 120 is formed on the silicon island and the uncovered buffer layer 101 by a chemical vapor deposition (CVD) process, and a third photolithography process is performed.
  • a first via hole 120a-1, 120a-2 is defined in the gate insulating layer 120, and the first via hole 120a-1 is located at one end of the first segment 111-1 of the silicon island for connecting the first formed first a drain D11 of the switching transistor T11 and a lower plate C1-1 of the first storage capacitor C1, the first via hole 120a-2 being located at one end of the third segment 112-1 of the silicon island for connection subsequent formation
  • the material used for the gate insulating layer 120 is, for example, an oxide, a nitride or an oxynitride.
  • the gate insulating layer 120 may also be made of other insulating materials, which is not limited in the present invention.
  • FIG. 4a is a schematic plan view showing a first metal layer (fourth lithography process) of a pixel group of an OLED display panel according to Embodiment 1 of the present invention, and FIG. 4b is a first sub-layer of the OLED display panel in Embodiment 1 of the present invention; FIG. 4 is a schematic cross-sectional view showing a second sub-pixel of the OLED display panel in the first embodiment of the present invention after the first metal layer is formed.
  • a first metal layer is formed on the gate insulating layer 120 by a sputtering or evaporation process, and a fourth photolithography process is performed to pattern the first metal layer.
  • a gate G11 of the first switching transistor T11, a gate G12 of the first driving transistor T12, a gate G21 of the second switching transistor T21, a gate G22 of the second driving transistor T22, a scan line Sn, and a first storage capacitor respectively
  • the first metal layer may be a single layer film of a metal or an alloy such as Cr, W, Ti, Ta, Mo, Al, Cu, or a composite film composed of a plurality of metal thin films.
  • the first electrode (ie, the lower plate) C1-1 of the first storage capacitor C1 and the first electrode (ie, the lower plate) C2-1 of the second storage capacitor C2 are symmetric.
  • the distribution preferably, is both rectangular in shape and of the same area.
  • the drain D11 of the first switching transistor T11 and the lower plate C1-1 of the first storage capacitor C1 are connected through a first via 120a-1, and the second switching transistor T21
  • the drain D21 and the lower plate C2-1 of the second storage capacitor C2 are connected through the first via 120a-2.
  • the gate G12 of the first driving transistor T12 and the lower plate C1-1 of the first storage capacitor C1 are actually integrated (as shown in FIG. 4a), but the first driving is explained below for convenience.
  • the structural characteristics of the transistor T12 and the first storage capacitor C1 are not integrated into each other in FIG. 4b; similarly, the gate G22 of the second driving transistor T22 and the lower plate C2- of the second storage capacitor C2 1 is actually an integral structure (as shown in Fig. 4a), but in order to facilitate the following description of the respective structural characteristics of the second driving transistor T22 and the second storage capacitor C2, the two are not integrated in Fig. 4c.
  • FIG. 5 is a schematic plan view showing a second via hole (fifth photolithography process) of a pixel group of the OLED display panel according to the first embodiment of the present invention
  • FIG. 5b is a first view of the OLED display panel in the first embodiment of the present invention
  • FIG. 5 is a cross-sectional view showing a second sub-pixel of the OLED display panel in the first embodiment of the present invention.
  • a first interlayer insulating layer 140 is formed by a chemical vapor deposition (CVD) process, and a fifth photolithography process is performed, in which the first interlayer insulating layer 140 and the gate insulating layer are formed.
  • the second via hole 140a-1 is disposed in the source of the first switching transistor T11, and is configured to turn on the subsequently formed first data line D1 and the first switching transistor T11. Source S11. Specifically, the second through hole 140a-1 is located at the other end of the first segment 111-1 of the silicon island, and the second through hole 140a-1 penetrates above the first segment 111-1 First interlayer insulating layer 140 and gate Edge layer 120.
  • the material used for the first interlayer insulating layer 140 is, for example, an oxide, a nitride or an oxynitride.
  • the first interlayer insulating layer 140 may also be made of other insulating materials. This is not a limitation.
  • FIG. 6a is a schematic plan view showing a second metal layer (sixth lithography process) of a pixel group of an OLED display panel according to Embodiment 1 of the present invention
  • FIG. 6b is a first view of the OLED display panel in Embodiment 1 of the present invention
  • FIG. 6 is a schematic cross-sectional view showing a second metal layer of the OLED display panel in the first embodiment of the present invention after forming a second metal layer.
  • a second metal layer is formed on the first interlayer insulating layer 140 by a sputtering or evaporation process, and a sixth photolithography process is performed to pattern the second metal layer.
  • a source S11 of the first switching transistor T11, and a second electrode of the second storage capacitor C2 ie, the upper plate C2-2.
  • the second metal layer may be a single layer film of a metal or an alloy such as Cr, W, Ti, Ta, Mo, Al, Cu, or a composite film composed of a plurality of metal thin films. Referring to FIG.
  • the first data line D1 and the upper plate C2-2 of the second storage capacitor C2 are parallel to each other, and the first data line D1 and the source of the first switching transistor T11 are parallel.
  • the pole S11 is actually a unitary structure
  • the upper plate C2-2 of the second storage capacitor C2 has a rectangular shape
  • the upper plate C2-2 of the second storage capacitor C2 is located at the lower plate of the second storage capacitor C2.
  • the second storage capacitor C2 has been formed so far, which is composed of the lower plate C2-1, the upper plate C2-2, and the first interlayer insulating layer 140 located therebetween.
  • FIG. 7a is a schematic plan view showing a third via hole (seventh lithography process) of a pixel group of an OLED display panel according to Embodiment 1 of the present invention
  • FIG. 7b is a first sub-layer of the OLED display panel in Embodiment 1 of the present invention
  • FIG. 7 is a schematic cross-sectional view showing a second sub-pixel of the OLED display panel in the first embodiment of the present invention.
  • a second interlayer insulating layer 160 is formed by a chemical vapor deposition (CVD) method, and a seventh photolithography process is performed, in the second interlayer insulating layer 160, first.
  • a third via hole 160a-2 is defined in the interlayer insulating layer 140 and the gate insulating layer 120, and the third via hole 160a-2 is located at a source position of the second switching transistor T21 for turning on the subsequently formed second data. Line D2 and source S21 of the second switching transistor T21.
  • the third through hole 160a-2 is located at the other end of the third segment 112-1 of the silicon island, that is, the third through hole 160a-2 extends through the third segment 112 of the silicon island.
  • the second interlayer insulating layer 160 over the -1, a first interlayer insulating layer 140, and a gate insulating layer 120.
  • the The material used for the second interlayer insulating layer 160 is, for example, an oxide, a nitride or an oxynitride.
  • the second interlayer insulating layer 160 may also be made of other insulating materials, which is not limited in the present invention.
  • an eighth photolithography process is performed, in the second interlayer insulating layer 160.
  • the dielectric layer of C1 and the second storage capacitor C2 has the same thickness, that is, the first storage capacitor C1 and the second storage capacitor C2 are both made of the first interlayer insulating layer 140 as a dielectric layer.
  • the present invention does not limit the order in which the third through holes 160a-2 and the openings 160b are formed.
  • the openings 160b may be formed before the third through holes 160a-2 are formed.
  • the step of forming the opening 160b is not essential, and the capacitance values of the first storage capacitor C1 and the second storage capacitor C2 may be the same by other means such as increasing the area of the first storage capacitor.
  • FIG. 8a is a plan view showing a third metal layer (ninth lithography process) of a pixel group of an OLED display panel according to Embodiment 1 of the present invention
  • FIG. 8b is a first view of the OLED display panel in Embodiment 1 of the present invention
  • FIG. 8c is a schematic cross-sectional view showing a second sub-pixel of the OLED display panel in the first embodiment of the present invention after forming a third metal layer.
  • a third metal layer is formed on the second interlayer insulating layer 160 by a sputtering or evaporation process, and a ninth photolithography process is performed to pattern the third metal layer.
  • the source S21 of the second switching transistor T21, and the second electrode of the first storage capacitor C1 ie, the upper plate C1-2.
  • the first data line D1 and the upper plate C1-2 of the first storage capacitor C1 are not in the same layer (ie, located in different structural layers), and the second data line D2 and the second storage capacitor C2 are The upper plate C2-2 is not in the same layer (ie, located in different structural layers), thereby facilitating the reduction of the same layer spacing (here, the spacing between the data lines of the same layer and the upper plates of the storage capacitor), thereby reducing the pixel area.
  • the third metal layer may be a single layer film of a metal or an alloy such as Cr, W, Ti, Ta, Mo, Al, Cu, or a composite film composed of a plurality of metal thin films.
  • the second electrode of the first storage capacitor C1 ie, the upper plate C1-2
  • the second electrode of the second storage capacitor C2 ie, the upper plate C2-2
  • the distribution preferably, is both rectangular in shape.
  • the second data line D2 and the upper plate C1-2 of the first storage capacitor C1 are parallel to each other.
  • the second data line D2 and the source S21 of the second switching transistor T21 are actually a unitary structure, and the upper plate C1-2 of the first storage capacitor C1 is located directly above the lower plate C1-1.
  • the lower plate C1-1 of the first storage capacitor C1 and the lower plate C2-1 of the second storage capacitor C2 have the same area
  • the upper plate C1-2 and the second storage capacitor C2 of the first storage capacitor C1 are upper.
  • Plate C2-2 has the same area.
  • FIG. 9a is a schematic plan view showing a fourth via hole (tenth lithography process) of a pixel group of an OLED display panel according to Embodiment 1 of the present invention
  • FIG. 9b is a first sub-layer of the OLED display panel in Embodiment 1 of the present invention
  • FIG. 9 is a cross-sectional view showing a second sub-pixel of the OLED display panel in the first embodiment of the present invention.
  • a third interlayer insulating layer 180 is formed by a chemical vapor deposition (CVD) method, and a ninth photolithography process is performed, and a third interlayer insulating layer 180 is opened.
  • CVD chemical vapor deposition
  • via holes 180a, 180a-1, 180a-2, 180a-3, 180a-4 for turning on the source and drain of the first driving transistor T12, the source and drain of the second driving transistor T22, and the power supply The line VDD, the upper plate C1-2 of the first storage capacitor C1, and the upper plate C2-2 of the second storage capacitor C2.
  • the fourth via hole 180a is located at a source position of the first driving transistor T12 and the second driving transistor T22, and penetrates the gate insulating layer 120 over the fifth segment 113 (ie, the active layer 113) of the silicon island, The first interlayer insulating layer 140, the second interlayer insulating layer 160, and the third interlayer insulating layer 180.
  • the fourth via hole 180a-1 is located at a drain position of the first driving transistor T12, and penetrates the gate insulating layer 120 and the first layer above the second segment 111-2 of the silicon island (ie, the active layer 111-2).
  • the insulating layer 140, the second interlayer insulating layer 160, and the third interlayer insulating layer 180 is located at a source position of the first driving transistor T12 and the second driving transistor T22, and penetrates the gate insulating layer 120 over the fifth segment 113 (ie, the active layer 113) of the silicon island, The first interlayer insulating layer 140, the second interlayer insulating layer 160, and the third interlayer
  • the fourth via hole 180a-2 is located at a drain position of the second driving transistor T22, and penetrates the gate insulating layer 120 and the first layer above the fourth segment 112-2 of the silicon island (ie, the active layer 112-2).
  • the fourth via hole 180a-3 is located above the first storage capacitor C1 and penetrates the third interlayer insulating layer 180 above the upper plate C1-2 of the first storage capacitor C1.
  • the fourth via hole 180a-4 is located above the second storage capacitor C2 and penetrates the second interlayer insulating layer 160 and the third interlayer insulating layer 180 above the upper plate C2-2 of the second storage capacitor C2.
  • the material used for the third interlayer insulating layer 180 is, for example, an oxide, a nitride or an oxynitride.
  • the third interlayer insulating layer 180 may also be made of other insulating materials. This is not a limitation.
  • FIG. 10 is a plan view showing a first sub-pixel shape of an OLED display panel in the first embodiment of the present invention, in which a pixel group of the OLED display panel is formed into a fourth metal layer.
  • FIG. 10c is a schematic cross-sectional view showing a fourth sub-pixel of the OLED display panel in the first embodiment of the present invention after forming a fourth metal layer.
  • a fourth metal layer is formed on the third interlayer insulating layer 180 by a sputtering or evaporation process, and an eleventh photolithography process is performed to pattern the fourth metal.
  • the layer forms a source S12 and a drain D12 of the first driving transistor T12, a source S22 and a drain D22 of the second driving transistor T22, and a power supply line VDD.
  • the fourth metal layer may be a single layer film of a metal or an alloy such as Cr, W, Ti, Ta, Mo, Al, Cu, or a composite film composed of a plurality of metal thin films. Referring to FIG.
  • the fourth metal layer is located above the first storage capacitor C1 and the second storage capacitor C2, and the source of the power line VDD and the first driving transistor T12 S12, the source S22 of the second driving transistor T22 is actually an integrated structure, more specifically, the first driving transistor T12 and the second driving transistor T22 share the source, and the drain D12 and the first driving transistor T12
  • the drain D22 of the second driving transistor T22 is mirror-symmetrical along the power line VDD.
  • the first storage capacitor C1 and the second storage capacitor C2 are also mirror-symmetrical along the power line VDD.
  • FIG. 11 is a schematic plan view showing a pixel group of a OLED display panel forming a contact hole in the first embodiment of the present invention
  • FIG. 11b is a cross-sectional view showing a first sub-pixel of the OLED display panel in the first embodiment of the present invention
  • 11c is a schematic cross-sectional view of the second sub-pixel of the OLED display panel in the first embodiment of the present invention after forming a contact hole.
  • a passivation insulating layer 200 is formed on the power line VDD and the third interlayer insulating layer 180 not covered by the power line VDD by a chemical vapor deposition (CVD) method, and is performed.
  • CVD chemical vapor deposition
  • contact holes 200a-1, 200a-2 are formed in the passivation insulating layer 200, and the contact holes 200a-1, 200a-2 are located in the first driving transistor T12 and the second
  • the drain position of the driving transistor T22 is specifically a passivation insulating layer 200 penetrating the drains of the first driving transistor T12 and the second driving transistor T22.
  • the material used for the passivation insulating layer 200 is, for example, an oxide, a nitride or an oxynitride.
  • the passivation insulating layer 200 may also be made of other insulating materials. limit.
  • an electrode layer is formed on the passivation insulating layer 170 by a sputtering or evaporation process, and a thirteenth photolithography process is performed to pattern the electrode layer to Forming an anode 221 of the first organic light emitting diode and an anode 222 of the second organic light emitting diode, the anode 221 of the first organic light emitting diode passing through the contact hole 200a-1 and the drain of the first driving transistor T12
  • the anode 222 of the second organic light emitting diode is electrically connected to the drain D22 of the second driving transistor T22 through the contact hole 200a-2.
  • the electrode layer may be one or more selected from the group consisting of indium tin oxide, zinc oxide, indium zinc oxide, silver, gold or aluminum.
  • the source S12 of the first driving transistor T12 is electrically connected to the active layer 112-1 through the fourth via 180a, and the source S12 of the first driving transistor T12. Electrical connection is made between the power line VDD and the second electrode of the first storage capacitor C1 (ie, the upper plate C1-2) through the fourth through hole 180a-3.
  • the source S22 of the second driving transistor T22 is electrically connected to the active layer 112-2 through the fourth via 180a, and the source S22 of the second driving transistor T22. Electrical connection is made to the second electrode of the power line VDD and the second storage capacitor C2 (ie, the upper plate C2-2) through the fourth through hole 180a-4.
  • the pixel defining layer may be formed by a conventional process, and then the light emitting layer and the cathode may be formed by a conventional process to complete the OLED device preparation. , will not repeat them here.
  • the two sub-pixels are grouped and arranged according to the power line VDD, and the data lines respectively connected to the two sub-pixels in the same pixel group are located on different structural layers.
  • the distance between adjacent data lines of the same layer can be doubled without reducing the pixel area, so that the adjacent data lines of different layers are separated by the interlayer insulating layer, thereby effectively reducing the data lines.
  • the probability of a short circuit occurs, and the crosstalk between the data lines is greatly eliminated in use, which not only improves the yield of the product, but also improves the picture quality of the product.
  • the pixel area can be reduced based on existing equipment and process conditions, the PPI of the OLED display panel is improved, and the resolution of the OLED display panel is improved. rate.
  • the first data line D1 and the upper plate C1-2 of the first storage capacitor C1 are not in the same layer, and the second data line D2 and the upper plate C2-2 of the second storage capacitor C2 are not in the same layer.
  • the first data line D1 and the upper plate C2-2 of the second storage capacitor C2 are formed together, and the second data line D2 is formed together with the upper plate C1-2 of the first storage capacitor C1. It is beneficial to reduce the distance between the data lines of the same layer and the upper plates of the storage capacitors, thereby reducing the pixel area, improving the PPI of the OLED display panel, and improving the resolution of the OLED display panel.
  • the upper plate C1-2 of the first storage capacitor C1 and the upper plate C2-2 of the second storage capacitor C2 are integrated structures, and are formed by one process.
  • the first data line D1, the second data line D2, and the power supply line VDD are parallel to each other, the scan line Sn and the power supply line VDD are perpendicular to each other, and the first The data line D1 and the second data line D2 are mirror-symmetrical along the power line VDD.
  • the first storage capacitor C1 and the second storage capacitor C2 are mirror-symmetrical along the power line VDD.
  • the first switching transistor T11 and the second switching transistor T21 are along the mirror.
  • the power line VDD is mirror-symmetrical
  • the first driving transistor T12 and the second driving transistor T22 are mirror-symmetrical along the power line VDD.
  • the upper plate C1-2 of the first storage capacitor C1 and the upper plate C2-2 of the second storage capacitor C2 are of a unitary structure and are rectangular, and the first storage capacitor C1
  • the lower plate C1-1 of the lower plate C1-1 and the second storage capacitor C2 are also rectangular.
  • FIG. 13a is a schematic plan view showing a pixel group of a OLED display panel in the second embodiment of the present invention
  • FIG. 13b is a schematic cross-sectional view showing a first sub-pixel of the OLED display panel in the second embodiment of the present invention
  • 13c is a schematic cross-sectional view of the second sub-pixel of the OLED display panel in the second embodiment of the present invention after forming a silicon island.
  • a substrate 100 is provided.
  • a silicon island is formed on the substrate 100.
  • the silicon island is used as an active layer of the first switching transistor T11, an active layer of the first driving transistor T12, an active layer of the second switching transistor T21, and an active layer of the second driving transistor T22.
  • the buffer layer 101 is formed on the substrate 100 before the silicon island is formed on the substrate 100.
  • a second photolithography process is performed to perform ion implantation on a predetermined region of the silicon island.
  • FIG. 14 is a schematic plan view showing a first sub-pixel of a OLED display panel in a first through-hole of the OLED display panel according to Embodiment 2 of the present invention
  • FIG. 14c is a cross-sectional view showing the second sub-pixel of the OLED display panel in the second embodiment of the present invention after the first via hole is formed.
  • a chemical vapor deposition (CVD) process is employed on the silicon islands and A gate insulating layer 120 is formed on the uncovered buffer layer 101, and a third photolithography process is performed to open the first via holes 120a-1, 120a-2 in the gate insulating layer 120.
  • CVD chemical vapor deposition
  • Figure 15a is a plan view showing a first pixel of the OLED display panel in the second embodiment of the present invention after the first metal layer is formed in the second embodiment of the present invention.
  • FIG. 15c is a cross-sectional view showing the second sub-pixel of the OLED display panel in the second embodiment of the present invention after the first metal layer is formed.
  • a first metal layer is formed on the gate insulating layer 120 by a sputtering or evaporation process, and a fourth photolithography process is performed to pattern the first metal layer to form respectively.
  • Figure 16a is a plan view showing a second through hole of a pixel group of the OLED display panel in the second embodiment of the present invention
  • Figure 16b is a second sub-pixel of the OLED display panel in the second embodiment of the present invention
  • FIG. 16c is a cross-sectional view showing the second sub-pixel of the OLED display panel in the second embodiment of the present invention.
  • a first interlayer insulating layer 140 is formed by a chemical vapor deposition (CVD) process, and a fifth photolithography process is performed, in which the first interlayer insulating layer 140 and the gate insulating layer are formed.
  • the second via hole 140a-1 is disposed in the source of the first switching transistor T11, and is configured to turn on the subsequently formed first data line D1 and the first switching transistor T11. Source S11.
  • Figure 17a is a plan view showing a second metal layer of a pixel group of the OLED display panel in the second embodiment of the present invention
  • Figure 17b is a second sub-pixel of the OLED display panel in the second embodiment of the present invention
  • FIG. 17c is a cross-sectional view showing the second sub-pixel of the OLED display panel in the second embodiment of the present invention after forming a second metal layer.
  • a second metal layer is formed on the first interlayer insulating layer 140 by a sputtering or evaporation process, and a sixth photolithography process is performed to pattern the second metal layer.
  • a first data line D1 a source S11 of the first switching transistor T11, a second electrode of the first storage capacitor C1 (ie, the upper plate C1-2), and a second electrode of the second storage capacitor C2 (ie, the upper electrode) Plate C2-2).
  • the difference between this embodiment and the first embodiment is that the upper plate C1-2 of the first storage capacitor C1 and the upper plate C2-2 of the second storage capacitor C2 are integrated structures and formed by one process. Since the upper plates of the first storage capacitor C1 and the second storage capacitor C2 are simultaneously formed, there is no need to additionally form an opening to ensure that the capacitance values of one storage capacitor C1 and the second storage capacitor C2 are equal, compared to the scheme of the first embodiment. It simplifies the process and reduces costs.
  • FIG. 18 is a schematic plan view showing a pixel group of the OLED display panel forming a third via hole according to the second embodiment of the present invention
  • FIG. 18b is a schematic view showing the first sub-pixel of the OLED display panel in the second embodiment of the present invention
  • FIG. 18c is a cross-sectional view showing the second sub-pixel of the OLED display panel in the second embodiment of the present invention.
  • a second interlayer insulating layer 160 is formed by a chemical vapor deposition (CVD) method, and a seventh photolithography process is performed, in the second interlayer insulating layer 160, first.
  • a third via hole 160a-2 is defined in the interlayer insulating layer 140 and the gate insulating layer 120, and the third via hole 160a-2 is located at a source position of the second switching transistor T21 for turning on the subsequently formed second data. Line D2 and source S21 of the second switching transistor T21.
  • Figure 19a is a plan view showing a third metal layer of a pixel group of an OLED display panel in the second embodiment of the present invention
  • Figure 19b is a schematic view of the first sub-pixel of the OLED display panel in the second embodiment of the present invention
  • FIG. 19c is a cross-sectional view showing the second sub-pixel of the OLED display panel in the second embodiment of the present invention after forming a third metal layer.
  • a third metal layer is formed on the second interlayer insulating layer 160 by a sputtering or evaporation process, and an eighth photolithography process is performed to pattern the third metal layer.
  • an eighth photolithography process is performed to pattern the third metal layer.
  • the second data line D2 and the source S21 of the second switching transistor T21 are integrated.
  • FIG. 20 is a schematic plan view showing a pixel group of the OLED display panel after forming a fourth via hole according to the second embodiment of the present invention
  • FIG. 20b is a second sub-pixel of the OLED display panel of the second embodiment of the present invention
  • FIG. 20c is a cross-sectional view showing the second sub-pixel of the OLED display panel in the second embodiment of the present invention.
  • a third interlayer insulating layer 180 is formed by a chemical vapor deposition (CVD) method, and an eighth photolithography process is performed to open a third interlayer insulating layer 180.
  • CVD chemical vapor deposition
  • eight photolithography process is performed to open a third interlayer insulating layer 180.
  • Four via holes 180a, 180a-1, 180a-2, 180a-3, 180a-4 for turning on the first driving transistor T12 The source and the drain, the source and the drain of the second driving transistor T22, the power supply line VDD, the upper plate C1-2 of the first storage capacitor C1, and the upper plate C2-2 of the second storage capacitor C2.
  • FIG. 21a is a plan view showing a fourth metal layer of a pixel group of an OLED display panel in the second embodiment of the present invention
  • FIG. 21b is a second sub-pixel of the OLED display panel in the second embodiment of the present invention
  • FIG. 21c is a cross-sectional view showing the second sub-pixel of the OLED display panel in the second embodiment of the present invention after forming a fourth metal layer.
  • a fourth metal layer is formed on the third interlayer insulating layer 180 by a sputtering or evaporation process, and a tenth photolithography process is performed to pattern the fourth metal layer.
  • the source S12 and the drain D12 of the first driving transistor T12, the source S22 and the drain D22 of the second driving transistor T22, and the power supply line VDD are formed.
  • Figure 22a is a plan view showing a pixel group of the OLED display panel in the second embodiment of the present invention
  • Figure 22b is a schematic cross-sectional view showing the first sub-pixel of the OLED display panel in the second embodiment of the present invention
  • 22c is a schematic cross-sectional view of the second sub-pixel of the OLED display panel in the second embodiment of the present invention after the contact hole is formed.
  • a passivation insulating layer 200 is formed on the power supply line VDD and the third interlayer insulating layer 180 not covered by the power supply line VDD by a chemical vapor deposition (CVD) method, and is performed.
  • CVD chemical vapor deposition
  • a contact hole 200a is formed in the passivation insulating layer 200, and the contact hole 200a is located at a drain position of the first driving transistor T12 and the second driving transistor T22, specifically The passivation insulating layer 200 over the drains of the first driving transistor T12 and the second driving transistor T22 is described.
  • FIG. 23a is a schematic plan view showing a pixel group of an OLED display panel in which an anode is formed in an embodiment of the present invention
  • FIG. 23b is a cross-sectional view of the first sub-pixel of the OLED display panel in the second embodiment of the present invention.
  • an electrode layer is formed on the passivation insulating layer 200 by a sputtering or evaporation process, and a twelfth photolithography process is performed to pattern the electrode layer to form a first An anode 221 of the organic light emitting diode and an anode 222 of the second organic light emitting diode, the anode 221 of the first organic light emitting diode is electrically connected to the drain D12 of the first driving transistor T12 through the contact hole 200a, the first An anode 222 of the second organic light emitting diode passes through the contact hole 200a and the second driving crystal The drain D22 of the tube T22 is electrically connected.
  • the pixel defining layer may be formed by a conventional process, and then the light emitting layer and the cathode may be formed by a conventional process to complete the OLED device preparation. , will not repeat them here.
  • the two sub-pixels are grouped and arranged according to the power line VDD, and the data lines connected to the two sub-pixels in the same pixel group are located on different structural layers.
  • the distance between adjacent data lines of the same layer can be doubled without reducing the pixel area, so that the adjacent data lines of different layers are separated by the interlayer insulating layer, thereby effectively reducing the data lines.
  • the probability of a short circuit occurs, and the crosstalk between the data lines is greatly eliminated in use, which not only improves the yield of the product, but also improves the picture quality of the product.
  • the pixel area can be reduced based on existing equipment and process conditions, the PPI of the OLED display panel is improved, and the resolution of the OLED display panel is improved. rate.
  • the upper plate C1-2 of the first storage capacitor C1 and the upper plate C2-2 of the second storage capacitor C2 are formed by one process, which simplifies the manufacturing process and reduces the cost.

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Abstract

提供了一种OLED显示面板以及OLED显示面板的制造方法，包括扫描线（Sn）、数据线（D1，D2）和电源线（VDD），扫描线（Sn）和数据线（D1，D2）定义了以矩阵方式排列的多个像素组，每个像素组内具有两个子像素，同一像素组内的两个子像素连接同一电源线（VDD）并沿该电源线（VDD）镜像排列，且同一像素组内的两个子像素各自连接的数据线（D1，D2）位于不同结构层上。一方面，可有效减少数据线（D1，D2）之间发生短路的几率，且大幅度消除数据线（D1，D2）之间的串扰；另一方面，也可基于现有设备和工艺条件缩小像素面积，提升OLED显示面板的PPI，提高OLED显示面板的分辨率。

Description

OLED显示面板以及OLED显示面板的制造方法 技术领域
本发明涉及显示器技术领域，特别涉及一种OLED显示面板以及OLED显示面板的制造方法。
背景技术
随着信息社会的发展，人们对显示设备的需求日益增长。为了满足这种要求，各种平板显示装置如薄膜晶体管液晶显示器(TFT-LCD)、等离子体显示器(PDP)、有机发光二极管(OLED)显示器都得到了迅猛的发展。在这些平板显示装置当中，OLED显示器由于具有主动发光、对比度高、响应速度快、轻薄等诸多优点，正在逐步占据平板显示的主导地位。目前，OLED显示器已经广泛应用于手机、电视、电脑以及智能手表等各种高性能显示领域中。
图1为传统的OLED显示面板的像素电路图。如图1所示，在现有的OLED显示面板中，最基本的像素电路包括开关晶体管T1、驱动晶体管T2和存储电容Cs，所述开关晶体管T1的栅极与扫描线Sn连接，所述开关晶体管T1的源极与数据线Dm连接，所述开关晶体管T1的漏极、驱动晶体管T2的栅极和存储电容Cs的第一极板均连接于节点N1，所述驱动晶体管T2的源极和存储电容Cs的第二极板均与第一电源VDD连接，所述驱动晶体管T2的漏极与所述有机发光二极管OLED的阳极连接，所述有机发光二极管OLED的阴极与第二电源VSS连接。通过扫描线Sn打开所述开关晶体管T1时，数据线Dm提供的数据电压经由所述开关晶体管T1存储到存储电容Cs，从而控制所述驱动晶体管T2产生电流，以驱动所述有机发光二极管OLED发光。
随着生活水平的不断提高和生产力水平的日益改进，市场对高清晰、高分辨率产品的追求也越来越迫切。然而，传统的OLED显示面板的分辨率一般在250PPI以下(PPI表示每英寸所拥有的像素数目，PPI数值越高，代表显示器能够以越高的像素密度显示图像)，已经无法满足人们对于高分辨率显示器的追求。这是因为分辨率的提高要求同层间距比如相邻数据线之间的距离缩小，然而目前的OLED中相邻的像素单元的数据线通常设置在同一结构层上，基于现 有的工艺条件(比如光刻机的曝光限制)，很难进一步缩小相邻数据线之间的距离，从而导致OLED显示面板的分辨率难以提高。除了光刻机的曝光限制之外，数据线串扰和数据线短路也是生产高分辨率的OLED必须解决的技术难题。数据线串扰是指两条数据线之间的耦合，两条数据线之间的互感和互容会引起数据线出现噪声，研究表明，两条数据线上电流强度相同时，两条数据线间的距离越近，彼此之间的串扰效应越明显。数据线短路是指两条数据线之间彼此相连，使像素电极无法接收到正常信号而产生不良。在相同工艺条件下，两条数据线间的距离越近，彼此之间发生短路的几率越大。
发明内容
本发明的目的在于解决现有的有机发光显示器的分辨率低的问题。
本发明的另一目的在于消除有机发光显示器的数据线之间的串扰和短路现象。
为解决上述技术问题，本发明提供一种OLED显示面板，包括形成于一基板上的扫描线、数据线和电源线，所述扫描线和数据线定义了以矩阵方式排列的多个像素组，每个像素组内具有两个子像素，同一像素组内的两个子像素连接同一电源线并沿该电源线镜像排列，且同一像素组内的两个子像素各自连接的数据线位于不同结构层上。
可选的，在所述的OLED显示面板中，每个像素组内的两个子像素分别为第一子像素和第二子像素，所述第一子像素包括第一存储电容，所述第二子像素包括第二存储电容。
可选的，在所述的OLED显示面板中，所述第一存储电容的上极板和第二存储电容的上极板位于不同结构层上。
可选的，在所述的OLED显示面板中，所述第一子像素还包括第一开关晶体管和第一驱动晶体管，所述第二子像素还包括第二开关晶体管和第二驱动晶体管，所述第一开关晶体管的源极连接第一数据线，所述第二开关晶体管的源极连接第二数据线，所述第一数据线、第二数据线和电源线相互平行，所述扫描线与所述电源线相互垂直，并且，所述第一数据线和第二数据线、所述第一存储电容和第二存储电容、所述第一开关晶体管和第二开关晶体管、所述第一 驱动晶体管和第二驱动晶体管均沿所述电源线镜像对称。
可选的，在所述的OLED显示面板中，具体包括：
硅岛，形成于所述基板上，用以作为所述第一开关晶体管、第一驱动晶体管、第二开关晶体管以及第二驱动晶体管的有源层；
栅绝缘层和第一通孔，所述栅绝缘层形成于所述基板和硅岛上，所述第一通孔用于导通所述第一开关晶体管的漏极和第一存储电容的下极板以及所述第二开关晶体管的漏极和所述第二存储电容的下极板；
图形化的第一金属层，形成于所述栅绝缘层上，用以作为扫描线、第一存储电容的下极板、第二存储电容的下极板、第一开关晶体管的栅极、第一驱动晶体管的栅极、第二开关晶体管的栅极和第二驱动晶体管的栅极；
第一层间绝缘层和第二通孔，所述第一层间绝缘层形成于所述栅绝缘层以及图形化的第一金属层上，所述第二通孔用于导通所述第一数据线和第一开关晶体管的源极；
图形化的第二金属层，形成于所述第一层间绝缘层上，用以作为所述第一数据线、第一开关晶体管的源极和第二存储电容的上极板；
第二层间绝缘层和第三通孔，所述第二层间绝缘层形成于所述第一层间绝缘层以及图形化的第二金属层上，所述第三通孔用于导通第二数据线和第二开关晶体管的源极；
图形化的第三金属层，形成于所述第二层间绝缘层上，用以作为第二数据线、第二开关晶体管的源极和第一存储电容的上极板；
第三层间绝缘层和第四通孔，所述第三层间绝缘层形成于所述第二层间绝缘层以及图形化的第三金属层上，所述第四通孔用于导通第一驱动晶体管的源极和漏极、第二驱动晶体管的源极和漏极、电源线、第一存储电容的上极板以及第二存储电容的上极板；
图形化的第四金属层，形成于所述第三层间绝缘层上，用以作为第一驱动晶体管的源极和漏极、第二驱动晶体管的源极和漏极、电源线；
钝化绝缘层和接触孔，所述钝化绝缘层形成于所述第三层间绝缘层以及图形化的第四金属层上，所述接触孔用于导通所述第一驱动晶体管的漏极与第一有机发光二极管的阳极、所述第二驱动晶体管的漏极与第二有机发光二极管的 阳极。
可选的，在所述的OLED显示面板中，还包括一开口，所述开口贯穿所述第二层间绝缘层并正对所述第一存储电容的下极板。
可选的，在所述的OLED显示面板中，所述第一存储电容的上极板和第二存储电容的上极板位于相同结构层上。
可选的，在所述的OLED显示面板中，具体包括：
硅岛，形成于所述基板上，用以作为所述第一开关晶体管、第一驱动晶体管、第二开关晶体管以及第二驱动晶体管的有源层；
栅绝缘层和第一通孔，所述栅绝缘层形成于所述基板和硅岛上，所述第一通孔用于导通所述第一开关晶体管的漏极和第一存储电容的下极板以及所述第二开关晶体管的漏极和所述第二存储电容的下极板；
图形化的第一金属层，形成于所述栅绝缘层上，用以作为扫描线、第一存储电容的下极板、第二存储电容的下极板、第一开关晶体管的栅极、第一驱动晶体管的栅极、第二开关晶体管的栅极和第二驱动晶体管的栅极；
第一层间绝缘层和第二通孔，所述第一层间绝缘层形成于所述栅绝缘层以及图形化的第一金属层上，所述第二通孔用于导通所述第一数据线和第一开关晶体管的源极；
图形化的第二金属层，形成于所述第一层间绝缘层上，用以作为所述第一数据线、第一开关晶体管的源极、第一存储电容的上极板和第二存储电容的上极板；
第二层间绝缘层和第三通孔，所述第二层间绝缘层形成于所述第一层间绝缘层以及图形化的第二金属层上，所述第三通孔用于导通第二数据线和第二开关晶体管的源极；
图形化的第三金属层，形成于所述第二层间绝缘层上，用以作为第二数据线和第二开关晶体管的源极；
第三层间绝缘层和第四通孔，所述第三层间绝缘层形成于所述第二层间绝缘层以及图形化的第三金属层上，所述第四通孔用于导通第一驱动晶体管的源极和漏极、第二驱动晶体管的源极和漏极、电源线、第一存储电容的上极板以及第二存储电容的上极板；
图形化的第四金属层，形成于所述第三层间绝缘层上，用以作为第一驱动晶体管的源极和漏极、第二驱动晶体管的源极和漏极、电源线；
钝化绝缘层和接触孔，所述钝化绝缘层形成于所述第三层间绝缘层以及图形化的第四金属层上，所述接触孔用于导通所述第一驱动晶体管的漏极与第一有机发光二极管的阳极以及所述第二驱动晶体管的漏极与第二有机发光二极管的阳极。
本发明还提供一种OLED显示面板的制造方法，包括：
在一基板上形成扫描线、数据线、电源线、由所述扫描线和数据线定义的以矩阵方式排列的多个像素组；
其中，每个像素组内具有两个子像素，同一像素组内的两个子像素连接同一电源线并沿该电源线镜像排列，且同一像素组内的两个子像素各自连接的数据线位于不同结构层上。
可选的，在所述的OLED显示面板的制造方法中，每个像素组内的两个子像素分别为第一子像素和第二子像素，所述第一子像素包括第一存储电容，所述第二子像素包括第二存储电容，所述第一存储电容的上极板和第二存储电容的上极板位于不同结构层上，通过两次工艺形成。
可选的，在所述的OLED显示面板的制造方法中，所述第一子像素还包括第一开关晶体管和第一驱动晶体管，所述第二子像素还包括第二开关晶体管和第二驱动晶体管，所述第一开关晶体管的源极连接第一数据线，所述第二开关晶体管的源极连接第二数据线，所述第一数据线、第二数据线和电源线相互平行，所述扫描线与所述电源线相互垂直，并且，所述第一数据线和第二数据线、所述第一存储电容和第二存储电容、所述第一开关晶体管和第二开关晶体管、所述第一驱动晶体管和第二驱动晶体管均沿所述电源线镜像对称。
可选的，在所述的OLED显示面板的制造方法中，所述OLED显示面板具体通过如下步骤形成：
形成硅岛，所述硅岛用以作为所述第一开关晶体管、第一驱动晶体管、第二开关晶体管以及第二驱动晶体管的有源层；
形成栅绝缘层和第一通孔，所述栅绝缘层形成于所述基板和硅岛上，所述第一通孔用于导通所述第一开关晶体管的漏极和第一存储电容的下极板以及所 述第二开关晶体管的漏极和所述第二存储电容的下极板；
形成图形化的第一金属层，所述图形化的第一金属层形成于所述栅绝缘层上，用以作为扫描线、第一存储电容的下极板、第二存储电容的下极板、第一开关晶体管的栅极、第一驱动晶体管的栅极、第二开关晶体管的栅极和第二驱动晶体管的栅极；
形成第一层间绝缘层和第二通孔，所述第一层间绝缘层形成于所述栅绝缘层以及图形化的第一金属层上，所述第二通孔用于导通所述第一数据线和第一开关晶体管的源极；
形成图形化的第二金属层，所述图形化的第二金属层形成于所述第一层间绝缘层上，用以作为所述第一数据线、第一开关晶体管的源极和第二存储电容的上极板；
形成第二层间绝缘层和第三通孔，所述第二层间绝缘层形成于所述第一层间绝缘层以及图形化的第二金属层上，所述第三通孔用于导通第二数据线和第二开关晶体管的源极；
形成图形化的第三金属层，所述图形化的第三金属层形成于所述第二层间绝缘层上，用以作为第二数据线、第二开关晶体管的源极和第一存储电容的上极板；
形成第三层间绝缘层和第四通孔，所述第三层间绝缘层形成于所述第二层间绝缘层以及图形化的第三金属层上，所述第四通孔用于导通第一驱动晶体管的源极和漏极、第二驱动晶体管的源极和漏极、电源线、第一存储电容的上极板以及第二存储电容的上极板；
形成图形化的第四金属层，所述图形化的第四金属层形成于所述第三层间绝缘层上，用以作为第一驱动晶体管的源极和漏极、第二驱动晶体管的源极和漏极、电源线；
钝化绝缘层和接触孔，所述钝化绝缘层形成于所述第三层间绝缘层以及图形化的第四金属层上，所述接触孔用于导通所述第一驱动晶体管的漏极与第一有机发光二极管的阳极以及所述第二驱动晶体管的漏极与第二有机发光二极管的阳极。
可选的，在所述的OLED显示面板的制造方法中，形成所述第二层间绝缘 层之后，还形成一贯穿所述第二层间绝缘层的开口，所述开口正对所述第一存储电容的下极板。
可选的，在所述的OLED显示面板的制造方法中，所述第一存储电容的上极板和第二存储电容的上极板位于同一结构层上，通过一次工艺形成。
可选的，在所述的OLED显示面板的制造方法中，所述OLED显示面板具体通过如下步骤形成：
形成硅岛，所述硅岛形成于所述基板上，用以作为所述第一开关晶体管、第一驱动晶体管、第二开关晶体管以及第二驱动晶体管的有源层；
形成栅绝缘层和第一通孔，所述栅绝缘层形成于所述基板和硅岛上，所述第一通孔用于导通所述第一开关晶体管的漏极和第一存储电容的下极板以及所述第二开关晶体管的漏极和所述第二存储电容的下极板；
形成图形化的第一金属层，所述图形化的第一金属层形成于所述栅绝缘层上，用以作为扫描线、第一存储电容的下极板、第二存储电容的下极板、第一开关晶体管的栅极、第一驱动晶体管的栅极、第二开关晶体管的栅极和第二驱动晶体管的栅极；
形成第一层间绝缘层和第二通孔，所述第一层间绝缘层形成于所述栅绝缘层以及图形化的第一金属层上，所述第二通孔用于导通所述第一数据线和第一开关晶体管的源极；
形成图形化的第二金属层，所述图形化的第二金属层形成于所述第一层间绝缘层上，用以作为所述第一数据线、第一开关晶体管的源极、第一存储电容的上极板和第二存储电容的上极板；
形成第二层间绝缘层和第三通孔，所述第二层间绝缘层形成于所述第一层间绝缘层以及图形化的第二金属层上，所述第三通孔用于导通第二数据线和第二开关晶体管的源极；
形成图形化的第三金属层，所述图形化的第三金属层形成于所述第二层间绝缘层上，用以作为第二数据线和第二开关晶体管的源极；
形成第三层间绝缘层和第四通孔，所述第三层间绝缘层形成于所述第二层间绝缘层以及图形化的第三金属层上，所述第四通孔用于导通第一驱动晶体管的源极和漏极、第二驱动晶体管的源极和漏极、电源线、第一存储电容的上极 板以及第二存储电容的上极板；
形成图形化的第四金属层，所述图形化的第四金属层形成于所述第三层间绝缘层上，用以作为第一驱动晶体管的源极和漏极、第二驱动晶体管的源极和漏极、电源线；
形成钝化绝缘层和接触孔，所述钝化绝缘层形成于所述第三层间绝缘层以及图形化的第四金属层上，所述接触孔用于导通所述第一驱动晶体管的漏极与第一有机发光二极管的阳极以及所述第二驱动晶体管的漏极与第二有机发光二极管的阳极。
在本发明提供的OLED显示面板中，包括扫描线、数据线和电源线VDD，所述扫描线和数据线定义了以矩阵方式排列的多个像素组，每个像素组内具有两个子像素，同一像素组内的两个子像素连接同一电源线VDD并沿该电源线VDD镜像排列，且同一像素组内的两个子像素各自连接的数据线位于不同结构层上(即两个子像素各自连接的数据线不在同一层)。一方面，由于本发明将同一像素组内两个子像素对应连接的数据线设置在不同的结构层上，在不缩小像素面积的情况下，使同层相邻的数据线之间的距离增加了一倍，使不在同一层相邻的数据线之间由层间绝缘层隔离，可有效减少数据线之间发生短路的几率，且在使用中大幅度消除了数据线之间的串扰，不但提高了产品的成品率，而且提升了产品的画面品质。另一方面，由于同一像素组内两个子像素对应连接的数据线设置在不同的结构层上，也可基于现有设备和工艺条件缩小像素面积，提升OLED显示面板的PPI，提高OLED显示面板的分辨率。
进一步的，所述第一存储电容的上极板和第二存储电容的上极板位于不同结构层上，通过两次工艺形成，比如所述第一数据线和第二存储电容的上极板一并形成，而第二数据线和第一存储电容的上极板一并形成，即第一数据线和第一存储电容的上极板不在同一层，第二数据线和第二存储电容的上极板不在同一层，由此，有利于缩小同层的数据线和存储电容上极板的间距，可进一步缩小像素面积，提升OLED显示面板的PPI。
附图说明
图1是传统的OLED显示面板的像素电路图；
图2a是本发明实施例一中OLED显示面板的一个像素组形成硅岛后的平面示意图；
图2b是本发明实施例一中OLED显示面板的第一子像素形成硅岛后的剖面示意图；
图2c是本发明实施例一中OLED显示面板的第二子像素形成硅岛后的剖面示意图；
图3a是本发明实施例一中OLED显示面板的一个像素组形成第一通孔后的平面示意图；
图3b是本发明实施例一中OLED显示面板的第一子像素形成第一通孔后的剖面示意图；
图3c是本发明实施例一中OLED显示面板的第二子像素形成第一通孔后的剖面示意图；
图4a是本发明实施例一中OLED显示面板的一个像素组形成第一金属层后的平面示意图；
图4b是本发明实施例一中OLED显示面板的第一子像素形成第一金属层后的剖面示意图；
图4c是本发明实施例一中OLED显示面板的第二子像素形成第一金属层后的剖面示意图；
图5a是本发明实施例一中OLED显示面板的一个像素组形成第二通孔后的平面示意图；
图5b是本发明实施例一中OLED显示面板的第一子像素形成第二通孔后的剖面示意图；
图5c是本发明实施例一中OLED显示面板的第二子像素形成第二通孔后的剖面示意图；
图6a是本发明实施例一中OLED显示面板的一个像素组形成第二金属层后的平面示意图；
图6b是本发明实施例一中OLED显示面板的第一子像素形成第二金属层后的剖面示意图；
图6c是本发明实施例一中OLED显示面板的第二子像素形成第二金属层后 的剖面示意图；
图7a是本发明实施例一中OLED显示面板的一个像素组形成第三通孔后的平面示意图；
图7b是本发明实施例一中OLED显示面板的第一子像素形成第三通孔后的剖面示意图；
图7c是本发明实施例一中OLED显示面板的第二子像素形成第三通孔后的剖面示意图；
图8a是本发明实施例一中OLED显示面板的一个像素组形成第三金属层后的平面示意图；
图8b是本发明实施例一中OLED显示面板的第一子像素形成第三金属层后的剖面示意图；
图8c是本发明实施例一中OLED显示面板的第二子像素形成第三金属层后的剖面示意图；
图9a是本发明实施例一中OLED显示面板的一个像素组形成第四通孔后的平面示意图；
图9b是本发明实施例一中OLED显示面板的第一子像素形成第四通孔后的剖面示意图；
图9c是本发明实施例一中OLED显示面板的第二子像素形成第四通孔后的剖面示意图；
图10a是本发明实施例一中OLED显示面板的一个像素组形成第四金属层后的平面示意图；
图10b是本发明实施例一中OLED显示面板的第一子像素形成第四金属层后的剖面示意图；
图10c是本发明实施例一中OLED显示面板的第二子像素形成第四金属层后的剖面示意图；
图11a是本发明实施例一中OLED显示面板的一个像素组形成接触孔后的平面示意图；
图11b是本发明实施例一中OLED显示面板的第一子像素形成接触孔后的剖面示意图；
图11c是本发明实施例一中OLED显示面板的第二子像素形成接触孔后的剖面示意图；
图12a是本发明实施例一中OLED显示面板的一个像素组形成阳极后的平面示意图；
图12b是本发明实施例一中OLED显示面板的第一子像素形成阳极后的剖面示意图；
图12c是本发明实施例一中OLED显示面板的第二子像素形成阳极后的剖面示意图；
图13a是本发明实施例二中OLED显示面板的一个像素组形成硅岛后的平面示意图；
图13b是本发明实施例二中OLED显示面板的第一子像素形成硅岛后的剖面示意图；
图13c是本发明实施例二中OLED显示面板的第二子像素形成硅岛后的剖面示意图；
图14a是本发明实施例二中OLED显示面板的一个像素组形成第一通孔后的平面示意图；
图14b是本发明实施例二中OLED显示面板的第一子像素形成第一通孔后的剖面示意图；
图14c是本发明实施例二中OLED显示面板的第二子像素形成第一通孔后的剖面示意图；
图15a是本发明实施例二中OLED显示面板的一个像素组形成第一金属层后的平面示意图；
图15b是本发明实施例二中OLED显示面板的第一子像素形成第一金属层后的剖面示意图；
图15c是本发明实施例二中OLED显示面板的第二子像素形成第一金属层后的剖面示意图；
图16a是本发明实施例二中OLED显示面板的一个像素组形成第二通孔后的平面示意图；
图16b是本发明实施例二中OLED显示面板的第一子像素形成第二通孔后 的剖面示意图；
图16c是本发明实施例二中OLED显示面板的第二子像素形成第二通孔后的剖面示意图；
图17a是本发明实施例二中OLED显示面板的一个像素组形成第二金属层后的平面示意图；
图17b是本发明实施例二中OLED显示面板的第一子像素形成第二金属层后的剖面示意图；
图17c是本发明实施例二中OLED显示面板的第二子像素形成第二金属层后的剖面示意图；
图18a是本发明实施例二中OLED显示面板的一个像素组形成第三通孔后的平面示意图；
图18b是本发明实施例二中OLED显示面板的第一子像素形成第三通孔后的剖面示意图；
图18c是本发明实施例二中OLED显示面板的第二子像素形成第三通孔后的剖面示意图；
图19a是本发明实施例二中OLED显示面板的一个像素组形成第三金属层后的平面示意图；
图19b是本发明实施例二中OLED显示面板的第一子像素形成第三金属层后的剖面示意图；
图19c是本发明实施例二中OLED显示面板的第二子像素形成第三金属层后的剖面示意图；
图20a是本发明实施例二中OLED显示面板的一个像素组形成第四通孔后的平面示意图；
图20b是本发明实施例二中OLED显示面板的第一子像素形成第四通孔后的剖面示意图；
图20c是本发明实施例二中OLED显示面板的第二子像素形成第四通孔后的剖面示意图；
图21a是本发明实施例二中OLED显示面板的一个像素组形成第四金属层后的平面示意图；
图21b是本发明实施例二中OLED显示面板的第一子像素形成第四金属层后的剖面示意图；
图21c是本发明实施例二中OLED显示面板的第二子像素形成第四金属层后的剖面示意图；
图22a是本发明实施例二中OLED显示面板的一个像素组形成接触孔后的平面示意图；
图22b是本发明实施例二中OLED显示面板的第一子像素形成接触孔后的剖面示意图；
图22c是本发明实施例二中OLED显示面板的第二子像素形成接触孔后的剖面示意图；
图23a是本发明实施例二中OLED显示面板的一个像素组形成阳极后的平面示意图；
图23b是本发明实施例二中OLED显示面板的第一子像素形成阳极后的剖面示意图；
图23c是本发明实施例二中OLED显示面板的第二子像素形成阳极后的剖面示意图；
附图标记说明：
第一开关晶体管-T11；第一开关晶体管的栅极-G11；第一开关晶体管的源极-S11；第一开关晶体管的漏极-D11；
第一驱动晶体管-T12；第一驱动晶体管的栅极-G12；第一驱动晶体管的源极-S12；第一驱动晶体管的漏极-D12；
第二开关晶体管-T21；第二开关晶体管的栅极-G21；第二开关晶体管的源极-S21；第二开关晶体管的漏极-D21；
第二驱动晶体管-T22；第二驱动晶体管的栅极-G22；第二驱动晶体管的源极-S22；第二驱动晶体管的漏极-D22；
第一存储电容-C1；第一存储电容的下极板-C1-1；第一存储电容的上极板-C1-2；
第二存储电容-C2；第二存储电容的下极板-C2-1；第二存储电容的上极板-C2-2；
第一数据线-D1；第二数据线-D2；扫描线-Sn；电源线-VDD；
基板-100；缓冲层-101；
硅岛的第一段-111-1；硅岛的第二段-111-2；硅岛的第三段-112-1；硅岛的第四段-112-2；硅岛的第五段-113；硅岛的第六段-114；
栅绝缘层-120；第一通孔-120a-1、120a-2；
第一层间绝缘层-140；第二通孔-140a-1；
第二层间绝缘层-160；第三通孔-160a-2；开口-160b；
第三层间绝缘层-180；第四通孔-180a、180a-1、180a-2、180a-3、180a-4；
钝化绝缘层-200；接触孔-200a-1、200a-2；
第一有机发光二极管的阳极-221；第二有机发光二极管的阳极-222。
具体实施方式
本发明的核心思想在于，提供一种OLED显示面板及其制造方法，所述OLED显示面板包括扫描线、数据线和电源线VDD，所述扫描线和数据线定义了以矩阵方式排列的多个像素组，每个像素组内具有两个子像素，同一像素组内的两个子像素连接同一电源线VDD并沿该电源线VDD镜像排列，且同一像素组内的两个子像素各自连接的数据线位于不同结构层上。如此一来，在不缩小像素面积的情况下，可使同层相邻的数据线之间的距离增加一倍，使不同层相邻的数据线之间由层间绝缘层隔离，有效减少数据线之间发生短路的几率，且可大幅度消除数据线之间的串扰。另外，由于同一像素组内两个子像素对应连接的数据线设置在不同的结构层上，也可基于现有设备和工艺条件缩小像素面积，提升OLED显示面板的PPI，进而提高OLED显示面板的分辨率。
以下结合附图和具体实施例对本发明提出的OLED显示面板以及OLED显示面板的制造方法作进一步详细说明。根据下面说明和权利要求书，本发明的优点和特征将更清楚。需说明的是，附图中各层薄膜厚度和区域大小形状不反映OLED显示面板的真实比例，目的只是示意性的说明本发明内容。
实施例一
图12a是本发明实施例一中OLED显示面板的一个像素组的平面示意图，所反映的是两个子像素的结构，图12b是图12a中第一子像素的剖面示意图， 图12c是图12a中第二子像素的剖面示意图。
如图12a、12b、12c所示，本实施例的OLED显示面板的主体结构包括形成在基板100上的扫描线、数据线和电源线，所述扫描线和数据线定义了以矩阵方式排列的多个像素组，每个像素组内具有两个子像素，同一像素组内的两个子像素连接同一电源线VDD并沿该电源线VDD镜像排列，且同一像素组内的两个子像素各自连接的数据线位于不同结构层上。为便于说明本实施例的技术方案，如图12a所示，本实施例将沿平行于纸面方向上下排列的两个子像素分别称为第一子像素和第二子像素，其中，位于下侧的子像素称为第一子像素，位于上侧的子像素称为第二子像素，与第一子像素的开关晶体管的源极连接的数据线称为第一数据线D1，与第二子像素的开关晶体管的源极连接的数据线称为第二数据线D2。
继续参考图12a、12b、12c，并结合2a至图11c所示，所述第一数据线D1位于第二层间绝缘层160下方(具体是在第一层间绝缘层140与第二层间绝缘层160之间)，所述第一数据线D1通过贯穿第一层间绝缘层140的通孔(这里是指第二通孔-140a-1)与第一开关晶体管的源极S11连接；所述第二数据线D2位于第二层间绝缘层160上方(具体是在第二层间绝缘层160与第三层间绝缘层180之间)，所述第二数据线D2通过贯穿第一层间绝缘层140和第二层间绝缘层-160的通孔(这里是指第三通孔160a-2)与第二开关晶体管的源极-S21连接；即，第一数据线D1和第二数据线D2分别位于第二层间绝缘层160的两侧，第一数据线D1和第二数据线D2之间间隔设置一第二层间绝缘层160，第一数据线D1和第二数据线D2通过不同深度的通孔与开关晶体管的源极连接。如此，在不缩小像素面积的情况下，使同层相邻的数据线之间的距离增加了一倍，不同层相邻的数据线之间则由层间绝缘层(这里具体是指第二层间绝缘层160)隔离，在生产中可有效减少数据线之间发生短路的几率，且在使用中大幅度消除了数据线之间的串扰，不但提高了产品的成品率，而且提升了产品的画面品质。当然，由于同一像素组内两个子像素对应连接的数据线设置在不同的结构层上(同层相邻的数据线之间的距离得以增大)，因此不必受限于现有设备和工艺条件，得以缩小像素面积，提升OLED显示面板的PPI。
具体的，如图12a和图12b所示，所述第一子像素包括第一开关晶体管T11、 第一驱动晶体管T12和第一存储电容C1。所述第一开关晶体管T11包括栅极G11、源极S11、漏极D11、有源层111-1(即硅岛的第一段)。所述第一驱动晶体管T12包括栅极G12、源极S12、漏极D12、有源层111-2(即硅岛的第二段)。所述第一存储电容C1包括第一极板(即下极板C1-1)、第二极板(即上极板C1-2)以及形成于下极板C1-1和上极板C1-2之间的第一层间绝缘层140。其中，所述第一开关晶体管T11的栅极G11与扫描线Sn连接(二者实际上为一体结构)，所述第一开关晶体管T11的源极S11与第一数据线D1连接(二者实际上为一体结构)，所述第一开关晶体管T11的漏极D11、第一存储电容C1的第一极板(即下极板C1-1)、第一驱动晶体管T12的栅极G12连接，所述第一驱动晶体管T12的源极S12和第一存储电容C1的第二极板(即上极板C1-2)均与电源线VDD连接，所述第一驱动晶体管T12的漏极D12与第一有机发光二极管的阳极221连接。所述扫描线Sn用于向第一开关晶体管T11提供开启或关断电压，所述第一驱动晶体管T12用于控制第一数据线D1向第一有机发光二极管提供数据电压。
具体的，如图12a和图12c所示，所述第二子像素包括第二开关晶体管T21、第二驱动晶体管T22和第二存储电容C2。所述第二开关晶体管T21包括栅极G21、源极S21、漏极D21、有源层112-1(即硅岛的第三段)。所述第二驱动晶体管T22包括栅极G22、源极S22、漏极D22、有源层112-2(即硅岛的第四段)。所述第二存储电容C2包括第一极板(即下极板C2-1)、第二极板(即上极板C2-2)以及形成于下极板C2-1和上极板C2-2之间的第一层间绝缘层140。其中，所述第二开关晶体管T21的栅极G21与扫描线Sn连接(二者实际上为一体结构)，所述第二开关晶体管T21的源极S21与第二数据线D2连接(二者实际上为一体结构)，所述第二开关晶体管T21的漏极D21、第二存储电容C2的第一极板(即下极板C2-1)、第二驱动晶体管T22的栅极G22连接，所述第二驱动晶体管T22的源极S22和第二存储电容C2的第二极板(即上极板C2-2)均与电源线VDD连接，所述第二驱动晶体管T22的漏极D22与第二有机发光二极管的阳极222连接。所述扫描线Sn用于向第二开关晶体管T21提供开启或关断电压，所述第二驱动晶体管T22用于控制第二数据线D2向第二有机发光二极管提供数据电压。
继续参考图10a、11a、12a，所述第一数据线D1、第二数据线D2和电源线VDD相互平行，扫描线Sn则与所述电源线VDD相互垂直，且所述第一数据线D1和第二数据线D2沿电源线VDD镜像对称。同时，所述第一存储电容C1和第二存储电容C2沿电源线VDD镜像对称，所述第一开关晶体管T11和第二开关晶体管T21沿电源线VDD镜像对称，所述第一驱动晶体管T12和第二驱动晶体管T22沿电源线VDD镜像对称。具体的，本实施例中，所述第一存储电容C1的下极板C1-1和第二存储电容C2的下极板C2-1均为长方形且面积相同并沿电源线VDD镜像对称，所述第一存储电容C1的上极板C1-2和第二存储电容C2的上极板C2-2均为长方形且面积相同并沿电源线VDD镜像对称。
重点参考图2a、2b、2c所示，所述OLED显示面板还包括硅岛，所述硅岛形成于所述基板100上，用以作为第一开关晶体管T11、第一驱动晶体管T12、第二开关晶体管T21以及第二驱动晶体管T22的有源层。
重点参考图3a、3b、3c所示，所述OLED显示面板还包括栅绝缘层120以及第一通孔120a-1、120a-2，所述栅绝缘层120形成于所述基板100和硅岛上，所述第一通孔120a-1、120a-2贯穿所述栅绝缘层120，所述第一通孔120a-1用于导通第一开关晶体管T11的漏极D11和第一存储电容C1的下极板C1-1，所述第一通孔120a-2用于导通第二开关晶体管T21的漏极D21和第二存储电容C2的下极板C2-1。
重点参考图4a、4b、4c所示，所述OLED显示面板还包括图形化的第一金属层，所述图形化的第一金属层形成于所述栅绝缘层120上，用以作为第一开关晶体管T11的栅极G11、第一驱动晶体管T12的栅极G12、第二开关晶体管T21的栅极G21、第二驱动晶体管T22的栅极G22、扫描线Sn、第一存储电容C1的第一电极(即下极板)C1-1和第二存储电容C2的第一电极(即下极板)C2-1。
重点参考图5a、5b、5c所示，所述OLED显示面板还包括第一层间绝缘层140以及第二通孔140a-1，所述第一层间绝缘层140形成于所述栅绝缘层120以及图形化的第一金属层上，所述第二通孔140a-1用于导通第一数据线D1和第一开关晶体管T11的源极S11。
重点参考图6a、6b、6c所示，所述OLED显示面板还包括图形化的第二金 属层，所述图形化的第二金属层形成于所述第一层间绝缘层140上，用以作为第一数据线D1、第一开关晶体管T11的源极S11和第二存储电容C2的第二电极(即上极板C2-2)。
重点参考图7a、7b、7c所示，所述OLED显示面板还包括第二层间绝缘层160以及第三通孔160a-2，所述第二层间绝缘层160形成于所述第一层间绝缘层140以及图形化的第二金属层上，所述第三通孔160a-2用于导通第二数据线D2和第二开关晶体管T21的源极S21。进一步的，所述OLED显示面板还包括开口160b，所述开口160b贯穿所述第二层间绝缘层160并正对所述第一存储电容C1的下极板C1-1。
重点参考图8a、8b、8c所示，所述OLED显示面板还包括图形化的第三金属层，所述图形化的第三金属层形成于所述第二层间绝缘层160上以及所述开口160b，用以作为第二数据线D2、第二开关晶体管T21的源极S21和第一存储电容C1的第二电极(即上极板C1-2)。
重点参考图9a、9b、9c所示，所述OLED显示面板还包括第三层间绝缘层180以及第四通孔180a、180a-1、180a-2、180a-3、180a-4，所述第三层间绝缘层180形成于所述第二层间绝缘层160以及图形化的第三金属层上，所述第四通孔180a、180a-1、180a-2、180a-3、180a-4用于导通第一驱动晶体管T12的源极和漏极、第二驱动晶体管T22的源极和漏极、电源线VDD、第一存储电容C1的上极板C1-2以及第二存储电容C2的上极板C2-2。
重点参考图10a、10b、10c所示，所述OLED显示面板还包括图形化的第四金属层，所述图形化的第四金属层形成于所述第三层间绝缘层180上，用以作为第一驱动晶体管T12的源极S12和漏极D12、第二驱动晶体管T22的源极S22和漏极D22、电源线VDD。
重点参考图11a、11b、11c所示，所述OLED显示面板还包括钝化绝缘层200以及接触孔200a-1、200a-2，所述钝化绝缘层200形成于所述第三层间绝缘层180以及图形化的第四金属层上，所述接触孔200a-1用于导通所述第一驱动晶体管T12的漏极与第一有机发光二极管的阳极221，所述接触孔200a-2用于导通所述第二驱动晶体管T22的漏极与第二有机发光二极管的阳极222。
以下结合本发明OLED显示面板实施例一制造过程的平面俯视图和剖面示 意图，进一步说明本实施例的技术方案，在以下说明中，本发明所称的光刻工艺包括光刻胶涂覆、掩模、曝光、刻蚀和光刻胶剥离等工艺，光刻胶以正性光刻胶为例。
图2a是本发明实施例一中OLED显示面板的一个像素组形成硅岛后的平面示意图，图2b是本发明实施例一中OLED显示面板的第一子像素形成硅岛后的剖面示意图，图2c是本发明实施例一中OLED显示面板的第二子像素形成硅岛后的剖面示意图。
首先，如图2a、2b、2c所示，提供一基板100。所述基板100通常为透明基板，具体的，所述透明基板可为硬质基板或可挠式基板，例如透明玻璃基板或透明塑料基板。所述透明基板的形状可为平面、曲面或其他不规则形状。应理解的是，所述透明基板的材质以及形状在此不做限制。
接着，继续参考图2a、2b、2c所示，在所述基板100上形成硅岛。其中，形成硅岛的具体过程包括：采用化学气相沉积(CVD)工艺在所述基板100上形成一非晶硅层(a-Si)；对所述非晶硅层采用准分子激光退火(ELA)、固相晶化(SPC)或金属诱导结晶(MIC)等工艺方法，将其转化成多晶硅层(P-Si)；进行第一道光刻工艺，图形化所述多晶硅层形成硅岛。所述硅岛用以作为第一开关晶体管T11的有源层、第一驱动晶体管T12的有源层、第二开关晶体管T21的有源层以及第二驱动晶体管T22的有源层。具体而言，所述硅岛对应于所述第一开关晶体管T11、第一驱动晶体管T12、第二开关晶体管T21和第二驱动晶体管T22各自的源极和漏极位置。
重点参考图2a所示，本实施例中，所述硅岛包括第一段111-1、第二段111-2、第三段112-1、第四段112-2、第五段113以及第六段114，上述六部分均大致呈条状，且上述第一段111-1、第二段111-2、第三段112-1、第四段112-2、第五段113沿X方向延伸，而所述第六段114沿Y方向延伸。其中，第一段111-1和第三段112-1为独立的条状结构，第一段111-1用以作为第一子像素中第一开关晶体管T11的有源层，第三段112-1用以作为第二子像素中第二开关晶体管T21的有源层，并且，第一段111-1和第三段112-1镜像对称。第五段113位于第二段111-2和第四段112-2之间，所述第二段111-2和第四段112-2镜像对称，第六段114连接第二段111-2、第四段112-2、第五段113的一端以形成“山” 字形结构，第二段111-2、第四段112-2、第五段113、第六段114共同作为第一驱动晶体管T12和第二驱动晶体管T22的有源层(即第五段113为两个驱动晶体管所共用)。应当认识到，在本发明其它实施例中，所述硅岛的形状可以做一些适当的变化，例如，第一驱动晶体管T12和第二驱动晶体管T22的有源层还可以是两个开口方向相同的“U”型结构(即第一驱动晶体管T12和第二驱动晶体管T22并不共用有源层)，本发明并不限制硅岛的具体形状。
优选的，如图2b和图2c所示，在基板100上形成硅岛之前，先在所述基板100上形成缓冲层101，所述缓冲层101采用的材料例如为氮化硅或氧化硅。在基板100上形成硅岛之后，进行第二道光刻工艺，以对所述硅岛的预定区域进行离子注入，如图2a中虚线框所示，本实施例是对所述第一开关晶体管T11的漏极区域和第二开关晶体管T21的漏极区域进行离子注入，以使其导通性能更好。
图3a是本发明实施例一中OLED显示面板的一个像素组形成第一通孔后的平面示意图，图3b是本发明实施例一中OLED显示面板的第一子像素形成第一通孔后的剖面示意图，图3c是本发明实施例一中OLED显示面板的第二子像素形成第一通孔后的剖面示意图。
如图3a、3b、3c所示，采用化学气相沉积(CVD)工艺在所述硅岛和未被覆盖的缓冲层101上形成栅绝缘层120，并进行第三道光刻工艺，在所述栅绝缘层120中开设第一通孔120a-1、120a-2，所述第一通孔120a-1位于所述硅岛的第一段111-1的一端，用于连接后续形成的第一开关晶体管T11的漏极D11和第一存储电容C1的下极板C1-1，所述第一通孔120a-2位于所述硅岛的第三段112-1的一端，用于连接后续形成的第二开关晶体管T21的漏极D21和第二存储电容C2的下极板C2-1。本实施例中，所述栅绝缘层120采用的材料例如为氧化物、氮化物或氧氮化合物，当然，所述栅绝缘层120亦可采用其它绝缘材料，本发明对此并不予限制。
图4a是本发明实施例一中OLED显示面板的一个像素组形成第一金属层(第四道光刻工艺)后的平面示意图，图4b是本发明实施例一中OLED显示面板的第一子像素形成第一金属层后的剖面示意图，图4c是本发明实施例一中OLED显示面板的第二子像素形成第一金属层后的剖面示意图。
接着，如图4a、4b、4c所示，采用溅射或蒸发工艺在所述栅绝缘层120上形成第一金属层，并进行第四道光刻工艺，图形化所述第一金属层，分别形成第一开关晶体管T11的栅极G11、第一驱动晶体管T12的栅极G12、第二开关晶体管T21的栅极G21、第二驱动晶体管T22的栅极G22、扫描线Sn、第一存储电容C1的第一电极(即下极板)C1-1和第二存储电容C2的第一电极(即下极板)C2-1。所述第一金属层可以采用Cr、W、Ti、Ta、Mo、Al、Cu等金属或合金的单层膜，也可以采用由多层金属薄膜构成的复合薄膜。
重点参考图4a所示，本实施例中，第一存储电容C1的第一电极(即下极板)C1-1和第二存储电容C2的第一电极(即下极板)C2-1对称分布，优选的，二者的形状均为长方形且面积相同。如图4b和图4c所示，所述第一开关晶体管T11的漏极D11与第一存储电容C1的下极板C1-1通过第一通孔120a-1连接，所述第二开关晶体管T21的漏极D21与第二存储电容C2的下极板C2-1通过第一通孔120a-2连接。需要说明的是，所述第一驱动晶体管T12的栅极G12与第一存储电容C1的下极板C1-1实际上是一体结构(如图4a所示)，但为了便于下文说明第一驱动晶体管T12和第一存储电容C1各自的结构特性，在图4b中二者未连成一体；同理，所述第二驱动晶体管T22的栅极G22与第二存储电容C2的下极板C2-1实际上也是一体结构(如图4a所示)，但为了便于下文说明第二驱动晶体管T22和第二存储电容C2各自的结构特性，在图4c中二者未连成一体。
图5a是本发明实施例一中OLED显示面板的一个像素组形成第二通孔(第五道光刻工艺)后的平面示意图，图5b是本发明实施例一中OLED显示面板的第一子像素形成第二通孔后的剖面示意图，图5c是本发明实施例一中OLED显示面板的第二子像素形成第二通孔后的剖面示意图。
如图5a、5b、5c所示，采用化学气相沉积(CVD)工艺形成第一层间绝缘层140，并进行第五道光刻工艺，在所述第一层间绝缘层140和栅绝缘层120中开设第二通孔140a-1，所述第二通孔140a-1位于第一开关晶体管T11的源极位置，用于导通后续形成的第一数据线D1和第一开关晶体管T11的源极S11。具体而言，所述第二通孔140a-1位于所述硅岛的第一段111-1的另一端，并且，所述第二通孔140a-1贯穿所述第一段111-1上方的第一层间绝缘层140和栅绝 缘层120。本实施例中，所述第一层间绝缘层140采用的材料例如为氧化物、氮化物或氧氮化合物，当然，所述第一层间绝缘层140亦可采用其它绝缘材料，本发明对此并不予限制。
图6a是本发明实施例一中OLED显示面板的一个像素组形成第二金属层(第六道光刻工艺)后的平面示意图，图6b是本发明实施例一中OLED显示面板的第一子像素形成第二金属层后的剖面示意图，图6c是本发明实施例一中OLED显示面板的第二子像素形成第二金属层后的剖面示意图。
如图6a、6b、6c所示，采用溅射或蒸发工艺在所述第一层间绝缘层140上形成第二金属层，并进行第六道光刻工艺，图形化所述第二金属层，以形成第一数据线D1、第一开关晶体管T11的源极S11和第二存储电容C2的第二电极(即上极板C2-2)。所述第二金属层可以采用Cr、W、Ti、Ta、Mo、Al、Cu等金属或合金的单层膜，也可以采用由多层金属薄膜构成的复合薄膜。重点参考图6a所示，本实施例中，所述第一数据线D1与第二存储电容C2的上极板C2-2相互平行，所述第一数据线D1和第一开关晶体管T11的源极S11实际上是一体结构，第二存储电容C2的上极板C2-2的形状为长方形，且所述第二存储电容C2的上极板C2-2位于第二存储电容C2的下极板C2-1的正上方，至此，第二存储电容C2已经形成，其由下极板C2-1、上极板C2-2以及位于二者之间的第一层间绝缘层140共同构成。
图7a是本发明实施例一中OLED显示面板的一个像素组形成第三通孔(第七道光刻工艺)后的平面示意图，图7b是本发明实施例一中OLED显示面板的第一子像素形成第三通孔后的剖面示意图，图7c是本发明实施例一中OLED显示面板的第二子像素形成第三通孔后的剖面示意图。
如图7a、7b、7c所示，采用化学气相沉积(CVD)的方法形成第二层间绝缘层160，并进行第七道光刻工艺，在所述第二层间绝缘层160、第一层间绝缘层140和栅绝缘层120中开设第三通孔160a-2，所述第三通孔160a-2位于第二开关晶体管T21的源极位置，用于导通后续形成的第二数据线D2和第二开关晶体管T21的源极S21。具体而言，所述第三通孔160a-2位于所述硅岛的第三段112-1的另一端，即，所述第三通孔160a-2贯穿所述硅岛的第三段112-1上方的第二层间绝缘层160、第一层间绝缘层140和栅绝缘层120。本实施例中，所述 第二层间绝缘层160采用的材料例如为氧化物、氮化物或氧氮化合物，当然，所述第二层间绝缘层160亦可采用其它绝缘材料，本发明对此并不予限制。
优选方案中，为了使第一存储电容C1和第二存储电容C2的电容值相同，形成第三通孔160a-2之后，进行第八道光刻工艺，在所述第二层间绝缘层160中形成正对第一存储电容C1的下极板C1-1的开口160b，即去除第一存储电容C1的下极板C1-1上方的第二层间绝缘层160，以使第一存储电容C1和第二存储电容C2的介质层厚度相同，也就是说，使第一存储电容C1和第二存储电容C2均采用第一层间绝缘层140作为介质层。可以理解的是，本发明并不限定第三通孔160a-2和开口160b形成顺序，在本发明其它实施例中也可在形成第三通孔160a-2之前形成该开口160b。进一步的，该形成开口160b的步骤并不是必须的，亦可采用其它方式例如增大第一存储电容的极板面积等方式使第一存储电容C1和第二存储电容C2的电容值相同。
图8a是本发明实施例一中OLED显示面板的一个像素组形成第三金属层(第九道光刻工艺)后的平面示意图，图8b是本发明实施例一中OLED显示面板的第一子像素形成第三金属层后的剖面示意图，图8c是本发明实施例一中OLED显示面板的第二子像素形成第三金属层后的剖面示意图。
如图8a、8b、8c所示，采用溅射或蒸发工艺在所述第二层间绝缘层160上形成第三金属层，并进行第九道光刻工艺，图形化所述第三金属层，以形成第二数据线D2、第二开关晶体管T21的源极S21和第一存储电容C1的第二电极(即上极板C1-2)。本实施例中，所述第一数据线D1和第一存储电容C1的上极板C1-2不在同一层(即位于不同结构层)，所述第二数据线D2和第二存储电容C2的上极板C2-2不在同一层(即位于不同结构层)，由此，有利于缩小同层间距(这里是指同层的数据线和存储电容上极板的间距)，进而缩小像素面积，提升OLED显示面板的PPI，提高OLED显示面板的分辨率。所述第三金属层可以采用Cr、W、Ti、Ta、Mo、Al、Cu等金属或合金的单层膜，也可以采用由多层金属薄膜构成的复合薄膜。重点参考图8a所示，本实施例中，第一存储电容C1的第二电极(即上极板C1-2)和第二存储电容C2的第二电极(即上极板C2-2)对称分布，优选的，二者的形状均为长方形。重点参考图8b和图8c所示，所述第二数据线D2与第一存储电容C1的上极板C1-2相互平行，所述第 二数据线D2和第二开关晶体管T21的源极S21实际上是一体结构，且所述第一存储电容C1的上极板C1-2位于其下极板C1-1的正上方。并且，第一存储电容C1的下极板C1-1和第二存储电容C2的下极板C2-1面积相同，第一存储电容C1的上极板C1-2和第二存储电容C2的上极板C2-2面积相同。
图9a是本发明实施例一中OLED显示面板的一个像素组形成第四通孔(第十道光刻工艺)后的平面示意图，图9b是本发明实施例一中OLED显示面板的第一子像素形成第四通孔后的剖面示意图，图9c是本发明实施例一中OLED显示面板的第二子像素形成第四通孔后的剖面示意图。
如图9a、9b、9c所示，采用化学气相沉积(CVD)的方法形成第三层间绝缘层180，并进行第九道光刻工艺，在所述第三层间绝缘层180中开设第四通孔180a、180a-1、180a-2、180a-3、180a-4，用于导通第一驱动晶体管T12的源极和漏极、第二驱动晶体管T22的源极和漏极、电源线VDD、第一存储电容C1的上极板C1-2以及第二存储电容C2的上极板C2-2。
具体而言，所述第四通孔180a位于第一驱动晶体管T12和第二驱动晶体管T22的源极位置，贯穿硅岛的第五段113(即有源层113)上方的栅绝缘层120、第一层间绝缘层140、第二层间绝缘层160和第三层间绝缘层180。所述第四通孔180a-1位于第一驱动晶体管T12的漏极位置，贯穿硅岛的第二段111-2(即有源层111-2)上方的栅绝缘层120、第一层间绝缘层140、第二层间绝缘层160和第三层间绝缘层180。所述第四通孔180a-2位于第二驱动晶体管T22的漏极位置，贯穿硅岛的第四段112-2(即有源层112-2)上方的栅绝缘层120、第一层间绝缘层140、第二层间绝缘层160和第三层间绝缘层180。所述第四通孔180a-3位于第一存储电容C1上方，贯穿第一存储电容C1的上极板C1-2上方的第三层间绝缘层180。所述第四通孔180a-4位于第二存储电容C2上方，贯穿第二存储电容C2的上极板C2-2上方的第二层间绝缘层160和第三层间绝缘层180。本实施例中，所述第三层间绝缘层180采用的材料例如为氧化物、氮化物或氧氮化合物，当然，所述第三层间绝缘层180亦可采用其它绝缘材料，本发明对此并不予限制。
图10a是本发明实施例一中OLED显示面板的一个像素组形成第四金属层后的平面示意图，图10b是本发明实施例一中OLED显示面板的第一子像素形 成第四金属层后的剖面示意图，图10c是本发明实施例一中OLED显示面板的第二子像素形成第四金属层后的剖面示意图。
如图10a、10b、10c所示，采用溅射或蒸发工艺在所述第三层间绝缘层180上形成第四金属层，并进行第十一道光刻工艺，图形化所述第四金属层，以形成第一驱动晶体管T12的源极S12和漏极D12、第二驱动晶体管T22的源极S22和漏极D22、电源线VDD。所述第四金属层可以采用Cr、W、Ti、Ta、Mo、Al、Cu等金属或合金的单层膜，也可以采用由多层金属薄膜构成的复合薄膜。重点参考图10a所示，本实施例中，所述第四金属层位于所述第一存储电容C1和第二存储电容C2上方，并且，所述电源线VDD、第一驱动晶体管T12的源极S12、第二驱动晶体管T22的源极S22实际上是一体结构，更具体地说，第一驱动晶体管T12和第二驱动晶体管T22共用源极，并且，第一驱动晶体管T12的漏极D12与第二驱动晶体管T22的漏极D22沿电源线VDD镜像对称，同样，第一存储电容C1和第二存储电容C2也沿电源线VDD镜像对称。
图11a是本发明实施例一中OLED显示面板的一个像素组形成接触孔后的平面示意图，图11b是本发明实施例一中OLED显示面板的第一子像素形成接触孔后的剖面示意图，图11c是本发明实施例一中OLED显示面板的第二子像素形成接触孔后的剖面示意图。
如图11a、11b、11c所示，采用化学气相沉积(CVD)的方法在所述电源线VDD以及未被电源线VDD覆盖的第三层间绝缘层180上形成钝化绝缘层200，并进行第十二道光刻工艺，在所述钝化绝缘层200中形成接触孔200a-1、200a-2，所述接触孔200a-1、200a-2位于所述第一驱动晶体管T12和第二驱动晶体管T22的漏极位置，具体是贯穿所述第一驱动晶体管T12和第二驱动晶体管T22的漏极上方的钝化绝缘层200。本实施例中，所述钝化绝缘层200采用的材料例如为氧化物、氮化物或氧氮化合物，当然，所述钝化绝缘层200亦可采用其它绝缘材料，本发明对此并不予限制。
接着，如图12a、12b、12c所示，采用溅射或蒸发工艺在所述钝化绝缘层170上形成一电极层，并进行第十三道光刻工艺，图形化所述电极层，以形成第一有机发光二极管的阳极221和第二有机发光二极管的阳极222，所述第一有机发光二极管的阳极221通过所述接触孔200a-1与第一驱动晶体管T12的漏极 D12电性连接，所述第二有机发光二极管的阳极222通过所述接触孔200a-2与第二驱动晶体管T22的漏极D22电性连接。所述电极层可以采用氧化铟锡、氧化锌、氧化铟锌、银、金或铝中的一种或多种。
继续参考图12b所示，所述第一驱动晶体管T12的源极S12通过所述第四通孔180a与其有源层112-1实现电性连接，同时所述第一驱动晶体管T12的源极S12通过所述第四通孔180a-3与所述电源线VDD和第一存储电容C1的第二电极(即上极板C1-2)实现电性连接。
继续参考图12c所示，所述第二驱动晶体管T22的源极S22通过所述第四通孔180a与其有源层112-2实现电性连接，同时所述第二驱动晶体管T22的源极S22通过所述第四通孔180a-4与所述电源线VDD和第二存储电容C2的第二电极(即上极板C2-2)实现电性连接。
进一步的，形成第一有机发光二极管的阳极221和第二有机发光二极管的阳极222之后，还可采用常规工艺形成像素限定层，后续还可采用常规工艺形成发光层和阴极，以完成OLED器件制备，在此不再赘述。
综上，在本实施例所述的OLED显示面板中，两个子像素为一组，并根据电源线VDD镜像排列，且同一像素组内的两个子像素各自连接的数据线位于不同结构层上。可在不缩小像素面积的情况下，使同层相邻的数据线之间的距离增加了一倍，使不同层相邻的数据线之间由层间绝缘层隔离，有效减少数据线之间发生短路的几率，且在使用中大幅度消除了数据线之间的串扰，不但提高了产品的成品率，而且提升了产品的画面品质。再者，由于同一像素组内两个子像素对应连接的数据线设置在不同的结构层上，也可基于现有设备和工艺条件缩小像素面积，提升OLED显示面板的PPI，提高OLED显示面板的分辨率。此外，本实施例中第一数据线D1和第一存储电容C1的上极板C1-2不在同一层，第二数据线D2和第二存储电容C2的上极板C2-2不在同一层，比如所述第一数据线D1和第二存储电容C2的上极板C2-2一并形成，而第二数据线D2和第一存储电容C1的上极板C1-2一并形成，由此，有利于缩小同层的数据线和存储电容上极板的间距，进而缩小像素面积，提升OLED显示面板的PPI，提高OLED显示面板的分辨率。
实施例二
本实施例中，第一存储电容C1的上极板C1-2和第二存储电容C2的上极板C2-2是一体结构，通过一次工艺形成。
如图19a、20a、21a所示，所述第一数据线D1、第二数据线D2和电源线VDD相互平行，所述扫描线Sn与所述电源线VDD相互垂直，并且，所述第一数据线D1和第二数据线D2沿电源线VDD镜像对称，所述第一存储电容C1和第二存储电容C2沿电源线VDD镜像对称，所述第一开关晶体管T11和第二开关晶体管T21沿电源线VDD镜像对称，所述第一驱动晶体管T12和第二驱动晶体管T22沿电源线VDD镜像对称。
具体的，本实施例中，所述第一存储电容C1的上极板C1-2和第二存储电容C2的上极板C2-2是一体结构且为长方形，所述第一存储电容C1的下极板C1-1和第二存储电容C2的下极板C2-1亦为长方形。
以下结合本发明TFT-LCD阵列基板实施例一制造过程的平面俯视图和剖面示意图，进一步说明本实施例的技术方案。
图13a是本发明实施例二中OLED显示面板的一个像素组形成硅岛后的平面示意图，图13b是本发明实施例二中OLED显示面板的第一子像素形成硅岛后的剖面示意图，图13c是本发明实施例二中OLED显示面板的第二子像素形成硅岛后的剖面示意图。
如图13a、13b、13c所示，提供一基板100。接着，在所述基板100上形成硅岛。所述硅岛用以作为第一开关晶体管T11的有源层、第一驱动晶体管T12的有源层、第二开关晶体管T21的有源层以及第二驱动晶体管T22的有源层。本实施例中，在基板100上形成硅岛之前，先在所述基板100上形成缓冲层101。优选的，在基板100上形成硅岛之后，进行第二道光刻工艺，以对所述硅岛的预定区域进行离子注入。
图14a是本发明实施例二中OLED显示面板的一个像素组形成第一通孔后的平面示意图，图14b是本发明实施例二中OLED显示面板的第一子像素形成第一通孔后的剖面示意图，图14c是本发明实施例二中OLED显示面板的第二子像素形成第一通孔后的剖面示意图。
如图14a、14b、14c所示，采用化学气相沉积(CVD)工艺在所述硅岛和 未被覆盖的缓冲层101上形成栅绝缘层120，并进行第三道光刻工艺，在所述栅绝缘层120中开设第一通孔120a-1、120a-2。
图15a是本发明实施例二中OLED显示面板的一个像素组形成第一金属层后的平面示意图，图15b是本发明实施例二中OLED显示面板的第一子像素形成第一金属层后的剖面示意图，图15c是本发明实施例二中OLED显示面板的第二子像素形成第一金属层后的剖面示意图。
如图15a、15b、15c所示，采用溅射或蒸发工艺在所述栅绝缘层120上形成第一金属层，并进行第四道光刻工艺，图形化所述第一金属层，分别形成第一开关晶体管T11的栅极G11、第一驱动晶体管T12的栅极G12、第二开关晶体管T21的栅极G21、第二驱动晶体管T22的栅极G22、扫描线Sn、第一存储电容C1的第一电极(即下极板)C1-1和第二存储电容C2的第一电极(即下极板)C2-1。
图16a是本发明实施例二中OLED显示面板的一个像素组形成第二通孔后的平面示意图，图16b是本发明实施例二中OLED显示面板的第一子像素形成第二通孔后的剖面示意图，图16c是本发明实施例二中OLED显示面板的第二子像素形成第二通孔后的剖面示意图。
如图16a、16b、16c所示，采用化学气相沉积(CVD)工艺形成第一层间绝缘层140，并进行第五道光刻工艺，在所述第一层间绝缘层140和栅绝缘层120中开设第二通孔140a-1，所述第二通孔140a-1位于第一开关晶体管T11的源极位置，用于导通后续形成的第一数据线D1和第一开关晶体管T11的源极S11。
图17a是本发明实施例二中OLED显示面板的一个像素组形成第二金属层后的平面示意图，图17b是本发明实施例二中OLED显示面板的第一子像素形成第二金属层后的剖面示意图，图17c是本发明实施例二中OLED显示面板的第二子像素形成第二金属层后的剖面示意图。
如图17a、17b、17c所示，采用溅射或蒸发工艺在所述第一层间绝缘层140上形成第二金属层，并进行第六道光刻工艺，图形化所述第二金属层，以形成第一数据线D1、第一开关晶体管T11的源极S11、第一存储电容C1的第二电极(即上极板C1-2)和第二存储电容C2的第二电极(即上极板C2-2)。
重点参考图17a所示，本实施例与实施例一区别在于，第一存储电容C1的上极板C1-2和第二存储电容C2的上极板C2-2是一体结构，通过一次工艺形成，由于同时形成了第一存储电容C1和第二存储电容C2的上极板，无需额外形成开口以确保一存储电容C1和第二存储电容C2的电容值相等，相比于实施例一的方案可简化工艺，降低成本。
图18a是本发明实施例二中OLED显示面板的一个像素组形成第三通孔后的平面示意图，图18b是本发明实施例二中OLED显示面板的第一子像素形成第三通孔后的剖面示意图，图18c是本发明实施例二中OLED显示面板的第二子像素形成第三通孔后的剖面示意图。
如图18a、18b、18c所示，采用化学气相沉积(CVD)的方法形成第二层间绝缘层160，并进行第七道光刻工艺，在所述第二层间绝缘层160、第一层间绝缘层140和栅绝缘层120中开设第三通孔160a-2，所述第三通孔160a-2位于第二开关晶体管T21的源极位置，用于导通后续形成的第二数据线D2和第二开关晶体管T21的源极S21。
图19a是本发明实施例二中OLED显示面板的一个像素组形成第三金属层后的平面示意图，图19b是本发明实施例二中OLED显示面板的第一子像素形成第三金属层后的剖面示意图，图19c是本发明实施例二中OLED显示面板的第二子像素形成第三金属层后的剖面示意图。
如图19a、19b、19c所示，采用溅射或蒸发工艺在所述第二层间绝缘层160上形成第三金属层，并进行第八道光刻工艺，图形化所述第三金属层，以形成第二数据线D2以及第二开关晶体管T21的源极S21，本实施例中，所述第二数据线D2与第二开关晶体管T21的源极S21为一体结构。
图20a是本发明实施例二中OLED显示面板的一个像素组形成第四通孔后的平面示意图，图20b是本发明实施例二中OLED显示面板的第一子像素形成第四通孔后的剖面示意图，图20c是本发明实施例二中OLED显示面板的第二子像素形成第四通孔后的剖面示意图。
如图20a、20b、20c所示，采用化学气相沉积(CVD)的方法形成第三层间绝缘层180，并进行第八道光刻工艺，在所述第三层间绝缘层180中开设第四通孔180a、180a-1、180a-2、180a-3、180a-4，用于导通第一驱动晶体管T12的 源极和漏极、第二驱动晶体管T22的源极和漏极、电源线VDD、第一存储电容C1的上极板C1-2以及第二存储电容C2的上极板C2-2。
图21a是本发明实施例二中OLED显示面板的一个像素组形成第四金属层后的平面示意图，图21b是本发明实施例二中OLED显示面板的第一子像素形成第四金属层后的剖面示意图，图21c是本发明实施例二中OLED显示面板的第二子像素形成第四金属层后的剖面示意图。
如图21a、21b、21c所示，采用溅射或蒸发工艺在所述第三层间绝缘层180上形成第四金属层，并进行第十道光刻工艺，图形化所述第四金属层，以形成第一驱动晶体管T12的源极S12和漏极D12、第二驱动晶体管T22的源极S22和漏极D22、电源线VDD。
图22a是本发明实施例二中OLED显示面板的一个像素组形成接触孔后的平面示意图，图22b是本发明实施例二中OLED显示面板的第一子像素形成接触孔后的剖面示意图，图22c是本发明实施例二中OLED显示面板的第二子像素形成接触孔后的剖面示意图。
如图22a、22b、22c所示，采用化学气相沉积(CVD)的方法在所述电源线VDD以及未被电源线VDD覆盖的第三层间绝缘层180上形成钝化绝缘层200，并进行第十一道光刻工艺，在所述钝化绝缘层200中形成接触孔200a，所述接触孔200a位于所述第一驱动晶体管T12和第二驱动晶体管T22的漏极位置，具体是贯穿所述第一驱动晶体管T12和第二驱动晶体管T22的漏极上方的钝化绝缘层200。
图23a是本发明实施例二中OLED显示面板的一个像素组形成阳极后的平面示意图，图23b是本发明实施例二中OLED显示面板的第一子像素形成阳极后的剖面示意图，图23c是本发明实施例二中OLED显示面板的第二子像素形成阳极后的剖面示意图。
如图23a、23b、23c所示，采用溅射或蒸发工艺在所述钝化绝缘层200上形成一电极层，并进行第十二道光刻工艺，图形化所述电极层，以形成第一有机发光二极管的阳极221和第二有机发光二极管的阳极222，所述第一有机发光二极管的阳极221通过所述接触孔200a与第一驱动晶体管T12的漏极D12电性连接，所述第二有机发光二极管的阳极222通过所述接触孔200a与第二驱动晶体 管T22的漏极D22电性连接。
进一步的，形成第一有机发光二极管的阳极221和第二有机发光二极管的阳极222之后，还可采用常规工艺形成像素限定层，后续还可采用常规工艺形成发光层和阴极，以完成OLED器件制备，在此不再赘述。
综上，在实施例二所述的OLED显示面板中，两个子像素为一组，并根据电源线VDD镜像排列，且同一像素组内的两个子像素各自连接的数据线位于不同结构层上。可在不缩小像素面积的情况下，使同层相邻的数据线之间的距离增加了一倍，使不同层相邻的数据线之间由层间绝缘层隔离，有效减少数据线之间发生短路的几率，且在使用中大幅度消除了数据线之间的串扰，不但提高了产品的成品率，而且提升了产品的画面品质。再者，由于同一像素组内两个子像素对应连接的数据线设置在不同的结构层上，也可基于现有设备和工艺条件缩小像素面积，提升OLED显示面板的PPI，提高OLED显示面板的分辨率。同时，所述第一存储电容C1的上极板C1-2和第二存储电容C2的上极板C2-2通过一次工艺形成，可简化制作工艺，降低成本。
需要说明的是，本说明书中各个实施例采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分互相参见即可。对于实施例公开的结构而言，由于与实施例公开的方法相对应，所以描述的比较简单，相关之处参见方法部分说明即可。
上述描述仅是对本发明较佳实施例的描述，并非对本发明范围的任何限定，本发明领域的普通技术人员根据上述揭示内容做的任何变更、修饰，均属于权利要求书的保护范围。

Claims (16)

  1. 一种OLED显示面板，其特征在于，包括形成于一基板上的扫描线、数据线和电源线，所述扫描线和数据线定义了以矩阵方式排列的多个像素组，每个像素组内具有两个子像素，同一像素组内的两个子像素连接同一电源线并沿该电源线镜像排列，且同一像素组内的两个子像素各自连接的数据线位于不同结构层上。
  2. 如权利要求1所述的OLED显示面板，其特征在于，每个像素组内的两个子像素分别为第一子像素和第二子像素，所述第一子像素包括第一存储电容，所述第二子像素包括第二存储电容，所述第一存储电容的上极板和第二存储电容的上极板位于不同结构层上。
  3. 如权利要求2所述的OLED显示面板，其特征在于，所述第一子像素还包括第一开关晶体管和第一驱动晶体管，所述第二子像素还包括第二开关晶体管和第二驱动晶体管，所述第一开关晶体管的源极连接第一数据线，所述第二开关晶体管的源极连接第二数据线，所述第一数据线、第二数据线和电源线相互平行，所述扫描线与所述电源线相互垂直，并且，所述第一数据线和第二数据线、所述第一存储电容和第二存储电容、所述第一开关晶体管和第二开关晶体管、所述第一驱动晶体管和第二驱动晶体管均沿所述电源线镜像对称。
  4. 如权利要求3所述的OLED显示面板，其特征在于，所述OLED显示面板具体包括：
    硅岛，形成于所述基板上，用以作为所述第一开关晶体管、第一驱动晶体管、第二开关晶体管以及第二驱动晶体管的有源层；
    栅绝缘层和第一通孔，所述栅绝缘层形成于所述基板和硅岛上，所述第一通孔用于导通所述第一开关晶体管的漏极和第一存储电容的下极板以及所述第二开关晶体管的漏极和所述第二存储电容的下极板；
    图形化的第一金属层，形成于所述栅绝缘层上，用以作为扫描线、第一存储电容的下极板、第二存储电容的下极板、第一开关晶体管的栅极、第一驱动晶体管的栅极、第二开关晶体管的栅极和第二驱动晶体管的栅极；
    第一层间绝缘层和第二通孔，所述第一层间绝缘层形成于所述栅绝缘层以 及图形化的第一金属层上，所述第二通孔用于导通所述第一数据线和第一开关晶体管的源极；
    图形化的第二金属层，形成于所述第一层间绝缘层上，用以作为所述第一数据线、第一开关晶体管的源极和第二存储电容的上极板；
    第二层间绝缘层和第三通孔，所述第二层间绝缘层形成于所述第一层间绝缘层以及图形化的第二金属层上，所述第三通孔用于导通第二数据线和第二开关晶体管的源极；
    图形化的第三金属层，形成于所述第二层间绝缘层上，用以作为第二数据线、第二开关晶体管的源极和第一存储电容的上极板；
    第三层间绝缘层和第四通孔，所述第三层间绝缘层形成于所述第二层间绝缘层以及图形化的第三金属层上，所述第四通孔用于导通第一驱动晶体管的源极和漏极、第二驱动晶体管的源极和漏极、电源线、第一存储电容的上极板以及第二存储电容的上极板；
    图形化的第四金属层，形成于所述第三层间绝缘层上，用以作为第一驱动晶体管的源极和漏极、第二驱动晶体管的源极和漏极、电源线；
    钝化绝缘层和接触孔，所述钝化绝缘层形成于所述第三层间绝缘层以及图形化的第四金属层上，所述接触孔用于导通所述第一驱动晶体管的漏极与第一有机发光二极管的阳极、所述第二驱动晶体管的漏极与第二有机发光二极管的阳极。
  5. 如权利要求4所述的OLED显示面板，其特征在于，所述OLED显示面板还包括一开口，所述开口贯穿所述第二层间绝缘层并正对所述第一存储电容的下极板。
  6. 如权利要求1所述的OLED显示面板，其特征在于，每个像素组内的两个子像素分别为第一子像素和第二子像素，所述第一子像素包括第一存储电容，所述第二子像素包括第二存储电容，所述第一存储电容的上极板和第二存储电容的上极板位于相同结构层上。
  7. 如权利要求6所述的OLED显示面板，其特征在于，所述第一子像素还包括第一开关晶体管和第一驱动晶体管，所述第二子像素还包括第二开关晶体管和第二驱动晶体管，所述第一开关晶体管的源极连接第一数据线，所述第 二开关晶体管的源极连接第二数据线，所述第一数据线、第二数据线和电源线相互平行，所述扫描线与所述电源线相互垂直，并且，所述第一数据线和第二数据线、所述第一存储电容和第二存储电容、所述第一开关晶体管和第二开关晶体管、所述第一驱动晶体管和第二驱动晶体管均沿所述电源线镜像对称。
  8. 如权利要求7所述的OLED显示面板，其特征在于，所述OLED显示面板包括：
    硅岛，形成于所述基板上，用以作为所述第一开关晶体管、第一驱动晶体管、第二开关晶体管以及第二驱动晶体管的有源层；
    栅绝缘层和第一通孔，所述栅绝缘层形成于所述基板和硅岛上，所述第一通孔用于导通所述第一开关晶体管的漏极和第一存储电容的下极板以及所述第二开关晶体管的漏极和所述第二存储电容的下极板；
    图形化的第一金属层，形成于所述栅绝缘层上，用以作为扫描线、第一存储电容的下极板、第二存储电容的下极板、第一开关晶体管的栅极、第一驱动晶体管的栅极、第二开关晶体管的栅极和第二驱动晶体管的栅极；
    第一层间绝缘层和第二通孔，所述第一层间绝缘层形成于所述栅绝缘层以及图形化的第一金属层上，所述第二通孔用于导通所述第一数据线和第一开关晶体管的源极；
    图形化的第二金属层，形成于所述第一层间绝缘层上，用以作为所述第一数据线、第一开关晶体管的源极、第一存储电容的上极板和第二存储电容的上极板；
    第二层间绝缘层和第三通孔，所述第二层间绝缘层形成于所述第一层间绝缘层以及图形化的第二金属层上，所述第三通孔用于导通第二数据线和第二开关晶体管的源极；
    图形化的第三金属层，形成于所述第二层间绝缘层上，用以作为第二数据线和第二开关晶体管的源极；
    第三层间绝缘层和第四通孔，所述第三层间绝缘层形成于所述第二层间绝缘层以及图形化的第三金属层上，所述第四通孔用于导通第一驱动晶体管的源极和漏极、第二驱动晶体管的源极和漏极、电源线、第一存储电容的上极板以及第二存储电容的上极板；
    图形化的第四金属层，形成于所述第三层间绝缘层上，用以作为第一驱动晶体管的源极和漏极、第二驱动晶体管的源极和漏极、电源线；
    钝化绝缘层和接触孔，所述钝化绝缘层形成于所述第三层间绝缘层以及图形化的第四金属层上，所述接触孔用于导通所述第一驱动晶体管的漏极与第一有机发光二极管的阳极以及所述第二驱动晶体管的漏极与第二有机发光二极管的阳极。
  9. 一种OLED显示面板的制造方法，其特征在于，包括：
    在一基板上形成扫描线、数据线、电源线、由所述扫描线和数据线定义的以矩阵方式排列的多个像素组；
    其中，每个像素组内具有两个子像素，同一像素组内的两个子像素连接同一电源线并沿该电源线镜像排列，且同一像素组内的两个子像素各自连接的数据线位于不同结构层上。
  10. 如权利要求9所述的OLED显示面板的制造方法，其特征在于，每个像素组内的两个子像素分别为第一子像素和第二子像素，所述第一子像素包括第一存储电容，所述第二子像素包括第二存储电容，所述第一存储电容的上极板和第二存储电容的上极板位于不同结构层上。
  11. 如权利要求10所述的OLED显示面板，其特征在于，所述第一子像素还包括第一开关晶体管和第一驱动晶体管，所述第二子像素还包括第二开关晶体管和第二驱动晶体管，所述第一开关晶体管的源极连接第一数据线，所述第二开关晶体管的源极连接第二数据线，所述第一数据线、第二数据线和电源线相互平行，所述扫描线与所述电源线相互垂直，并且，所述第一数据线和第二数据线、所述第一存储电容和第二存储电容、所述第一开关晶体管和第二开关晶体管、所述第一驱动晶体管和第二驱动晶体管均沿所述电源线镜像对称。
  12. 如权利要求11所述的OLED显示面板的制造方法，其特征在于，所述OLED显示面板通过如下步骤形成：
    形成硅岛，所述硅岛用以作为所述第一开关晶体管、第一驱动晶体管、第二开关晶体管以及第二驱动晶体管的有源层；
    形成栅绝缘层和第一通孔，所述栅绝缘层形成于所述基板和硅岛上，所述 第一通孔用于导通所述第一开关晶体管的漏极和第一存储电容的下极板以及所述第二开关晶体管的漏极和所述第二存储电容的下极板；
    形成图形化的第一金属层，所述图形化的第一金属层形成于所述栅绝缘层上，用以作为扫描线、第一存储电容的下极板、第二存储电容的下极板、第一开关晶体管的栅极、第一驱动晶体管的栅极、第二开关晶体管的栅极和第二驱动晶体管的栅极；
    形成第一层间绝缘层和第二通孔，所述第一层间绝缘层形成于所述栅绝缘层以及图形化的第一金属层上，所述第二通孔用于导通所述第一数据线和第一开关晶体管的源极；
    形成图形化的第二金属层，所述图形化的第二金属层形成于所述第一层间绝缘层上，用以作为所述第一数据线、第一开关晶体管的源极和第二存储电容的上极板；
    形成第二层间绝缘层和第三通孔，所述第二层间绝缘层形成于所述第一层间绝缘层以及图形化的第二金属层上，所述第三通孔用于导通第二数据线和第二开关晶体管的源极；
    形成图形化的第三金属层，所述图形化的第三金属层形成于所述第二层间绝缘层上，用以作为第二数据线、第二开关晶体管的源极和第一存储电容的上极板；
    形成第三层间绝缘层和第四通孔，所述第三层间绝缘层形成于所述第二层间绝缘层以及图形化的第三金属层上，所述第四通孔用于导通第一驱动晶体管的源极和漏极、第二驱动晶体管的源极和漏极、电源线、第一存储电容的上极板以及第二存储电容的上极板；
    形成图形化的第四金属层，所述图形化的第四金属层形成于所述第三层间绝缘层上，用以作为第一驱动晶体管的源极和漏极、第二驱动晶体管的源极和漏极、电源线；
    钝化绝缘层和接触孔，所述钝化绝缘层形成于所述第三层间绝缘层以及图形化的第四金属层上，所述接触孔用于导通所述第一驱动晶体管的漏极与第一有机发光二极管的阳极以及所述第二驱动晶体管的漏极与第二有机发光二极管的阳极。
  13. 如权利要求12所述的OLED显示面板的制造方法，其特征在于，形成所述第二层间绝缘层之后，还形成一贯穿所述第二层间绝缘层的开口，所述开口正对所述第一存储电容的下极板。
  14. 如权利要求9所述的OLED显示面板的制造方法，其特征在于，每个像素组内的两个子像素分别为第一子像素和第二子像素，所述第一子像素包括第一存储电容，所述第二子像素包括第二存储电容，所述第一存储电容的上极板和第二存储电容的上极板位于相同结构层上。
  15. 如权利要求14所述的OLED显示面板的制造方法，其特征在于，所述第一子像素还包括第一开关晶体管和第一驱动晶体管，所述第二子像素还包括第二开关晶体管和第二驱动晶体管，所述第一开关晶体管的源极连接第一数据线，所述第二开关晶体管的源极连接第二数据线，所述第一数据线、第二数据线和电源线相互平行，所述扫描线与所述电源线相互垂直，并且，所述第一数据线和第二数据线、所述第一存储电容和第二存储电容、所述第一开关晶体管和第二开关晶体管、所述第一驱动晶体管和第二驱动晶体管均沿所述电源线镜像对称。
  16. 如权利要求15所述的OLED显示面板的制造方法，其特征在于，所述OLED显示面板通过如下步骤形成：
    形成硅岛，所述硅岛形成于所述基板上，用以作为所述第一开关晶体管、第一驱动晶体管、第二开关晶体管以及第二驱动晶体管的有源层；
    形成栅绝缘层和第一通孔，所述栅绝缘层形成于所述基板和硅岛上，所述第一通孔用于导通所述第一开关晶体管的漏极和第一存储电容的下极板以及所述第二开关晶体管的漏极和所述第二存储电容的下极板；
    形成图形化的第一金属层，所述图形化的第一金属层形成于所述栅绝缘层上，用以作为扫描线、第一存储电容的下极板、第二存储电容的下极板、第一开关晶体管的栅极、第一驱动晶体管的栅极、第二开关晶体管的栅极和第二驱动晶体管的栅极；
    形成第一层间绝缘层和第二通孔，所述第一层间绝缘层形成于所述栅绝缘层以及图形化的第一金属层上，所述第二通孔用于导通所述第一数据线和第一开关晶体管的源极；
    形成图形化的第二金属层，所述图形化的第二金属层形成于所述第一层间绝缘层上，用以作为所述第一数据线、第一开关晶体管的源极、第一存储电容的上极板和第二存储电容的上极板；
    形成第二层间绝缘层和第三通孔，所述第二层间绝缘层形成于所述第一层间绝缘层以及图形化的第二金属层上，所述第三通孔用于导通第二数据线和第二开关晶体管的源极；
    形成图形化的第三金属层，所述图形化的第三金属层形成于所述第二层间绝缘层上，用以作为第二数据线和第二开关晶体管的源极；
    形成第三层间绝缘层和第四通孔，所述第三层间绝缘层形成于所述第二层间绝缘层以及图形化的第三金属层上，所述第四通孔用于导通第一驱动晶体管的源极和漏极、第二驱动晶体管的源极和漏极、电源线、第一存储电容的上极板以及第二存储电容的上极板；
    形成图形化的第四金属层，所述图形化的第四金属层形成于所述第三层间绝缘层上，用以作为第一驱动晶体管的源极和漏极、第二驱动晶体管的源极和漏极、电源线；
    形成钝化绝缘层和接触孔，所述钝化绝缘层形成于所述第三层间绝缘层以及图形化的第四金属层上，所述接触孔用于导通所述第一驱动晶体管的漏极与第一有机发光二极管的阳极以及所述第二驱动晶体管的漏极与第二有机发光二极管的阳极。
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US20180350680A1 (en) 2018-12-06
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TWI634656B (zh) 2018-09-01

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