WO2017197581A1 - 一种时间数字转换器及数字锁相环 - Google Patents

一种时间数字转换器及数字锁相环 Download PDF

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Publication number
WO2017197581A1
WO2017197581A1 PCT/CN2016/082334 CN2016082334W WO2017197581A1 WO 2017197581 A1 WO2017197581 A1 WO 2017197581A1 CN 2016082334 W CN2016082334 W CN 2016082334W WO 2017197581 A1 WO2017197581 A1 WO 2017197581A1
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Prior art keywords
delay
conversion circuit
time
stage
digital converter
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Ceased
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PCT/CN2016/082334
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English (en)
French (fr)
Inventor
严皓
黄家乐
卢磊
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Priority to CN201680003024.XA priority Critical patent/CN107836082A/zh
Priority to JP2017520929A priority patent/JP6594420B2/ja
Priority to EP16856464.9A priority patent/EP3273601A4/en
Priority to PCT/CN2016/082334 priority patent/WO2017197581A1/zh
Priority to KR1020177012598A priority patent/KR20170140150A/ko
Priority to US15/685,447 priority patent/US10230383B2/en
Publication of WO2017197581A1 publication Critical patent/WO2017197581A1/zh
Anticipated expiration legal-status Critical
Priority to US16/256,477 priority patent/US10693481B2/en
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
    • G—PHYSICS
    • G04—HOROLOGY
    • G04F—TIME-INTERVAL MEASURING
    • G04F10/00—Apparatus for measuring unknown time intervals by electric means
    • G04F10/005—Time-to-digital converters [TDC]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/1205—Multiplexed conversion systems
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/50—Analogue/digital converters with intermediate conversion to time interval
    • H03M1/502—Analogue/digital converters with intermediate conversion to time interval using tapped delay lines
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/50—All digital phase-locked loop

Definitions

  • the present application relates to the field of circuit technologies, and in particular, to a time-to-digital converter and a digital phase locked loop.
  • Time-to-Digital Converter converts time signals to digital signals by sampling and quantizing time intervals.
  • Time-to-digital converters are widely used in space exploration, high-energy physics, test equipment, etc. In recent years, time-to-digital converters have been greatly promoted as key modules in digital phase-locked loops (DPLLs).
  • DPLLs digital phase-locked loops
  • the time-to-digital converter structure in the digital phase-locked loop includes a reference clock signal input terminal and a sampling clock signal input terminal, and the reference clock signal is input after passing through multiple stages of the same delay.
  • the first stage delayer After the first stage delayer outputs a delay signal with a delay time t (t is the accuracy of the time-to-digital converter), the delay signal output by the first-stage retarder is input to the second-stage retarder, and a delay time is obtained.
  • the delayed signal of 2 times t, and so on, the delayed signal obtained by the i-1th stage delay is input to the i-th stage delayer to obtain a delayed signal with a delay time i times t.
  • the sampling clock signal samples the series of delayed signals obtained above to obtain a series of output signals.
  • the dynamic range of the time-to-digital converter is t ⁇ i. If the time-to-digital converter needs to obtain a large dynamic range while keeping t constant, it is necessary to increase the number of stages of the delay unit; As a result, the number of time-to-digital converters becomes larger, so that the area and power consumption of the time-to-digital converter are correspondingly increased.
  • the present application provides a time to digital converter and a digital phase locked loop to reduce time to digital converter area and power consumption while maintaining the dynamic range of the time to digital converter.
  • an embodiment of the present invention provides a time-to-digital converter including a series-connected N-stage conversion circuit, N ⁇ 2, and N is an integer; each stage conversion circuit includes a first delay unit and an arbiter; wherein, a first delayer in the first-stage conversion circuit is configured to receive the reference signal, and an input end of the first delay device in each stage of the conversion circuit except the first-stage conversion circuit is coupled to the first delay device in the previous-stage conversion circuit An output end, and an output end of the first delay device in each stage of the conversion circuit is configured to output a delay signal of the stage conversion circuit; an arbiter in each stage conversion circuit is configured to receive a sampling clock of the stage conversion circuit and the stage conversion circuit Delay signal and compare the samples a clock and the delay signal to obtain an output signal of the stage conversion circuit; the sampling clock of each stage conversion circuit is derived from a clock signal; in the N-stage conversion circuit, a first delay in at least two stages of conversion circuits The delay time of the time converter is different; the output
  • the delay time of the first delay device in the at least two-stage conversion circuit of the N-stage conversion circuit is different, the nonlinearity of the output of the time digital converter is ensured, and the circuit level can be effectively reduced in the case of a large dynamic range. Number, reducing circuit area and power consumption.
  • the first delay unit in each of the conversion circuits includes at least one first delay unit circuit; the at least two-stage conversion circuit The number of first delay unit circuits included in each of the first delays is different.
  • the sampling clock of each of the conversion circuits is the clock signal.
  • the each stage conversion circuit further includes a second delay unit; the second delay unit in the first stage conversion circuit is configured to receive the clock a signal, an input of the second delay in each stage of the conversion circuit except the first stage conversion circuit is coupled to an output of the second delay unit in the previous stage conversion circuit, and a second delay in each stage of the conversion circuit The output of the converter is used to output the sampling clock of the stage conversion circuit.
  • the second delay time of the second delay device in each stage of the conversion circuit is less than the The first delay time of a delay.
  • the first delay unit in each of the conversion circuits includes at least one first delay unit circuit a second delay unit in the stage conversion circuit includes at least one second delay unit circuit; the number of second delay unit circuits in the second delay unit in each stage conversion circuit is equal to the number in the stage conversion circuit The number of first delay unit circuits in a delay; and the number of first delay unit circuits included in each of the at least two stage conversion circuits is different.
  • the third delay time of the second delay unit circuit in the second delay device in each of the conversion circuits is less than A fourth delay time of the first delay unit circuit of the first delay in the stage conversion circuit.
  • the each stage conversion circuit further includes a synchronization trigger;
  • the same The step flip flop is used to sample the output signal generated by the stage conversion circuit to synchronize the output signal of the N stage conversion circuit.
  • the N-level conversion circuit at least one level conversion circuit
  • the arbiter is an arbiter or trigger.
  • the trigger is a D flip-flop.
  • the delay time of the first delay device in each level conversion circuit is not less than The delay time of the first delay in the previous stage conversion circuit.
  • the delay time of the first delay device in the first-stage conversion circuit is a time unit;
  • the reference signal is another clock signal.
  • the binary number is a thermometer code.
  • the embodiment of the present invention further provides a digital phase locked loop, including the first aspect or the first to thirteenth possible ones of the first aspect, the reference The signal is a reference clock signal of the digital phase locked loop, and the clock signal is a frequency divided signal of an output signal of the digital phase locked loop.
  • FIG. 1 is a schematic structural diagram of a time-to-digital converter according to an embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of a first delay device according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of another time-to-digital converter according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a time-to-digital converter of a 7-stage conversion circuit according to an embodiment of the present invention
  • FIG. 5 is a schematic structural diagram of a nonlinear output delay chain according to an embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of two different nonlinear output delay chains according to an embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of a device according to an embodiment of the present invention.
  • the time-to-digital converter includes an N-stage conversion circuit, N ⁇ 2, and N is an integer.
  • the first delay in the first stage conversion circuit is configured to receive the reference signal ref, and the input of the first delay stage in each stage of the conversion circuit except the first stage conversion circuit is coupled to the first delay in the previous stage conversion circuit
  • the output of the first delay of each stage of the conversion circuit is used to output a delay signal of the stage conversion circuit, and the reference signal may be a clock.
  • An arbiter in each stage of the conversion circuit is configured to receive a sampling clock of the stage conversion circuit and a delay signal of the stage conversion circuit, and compare the sampling clock and the delay signal to obtain an output signal of the stage conversion circuit.
  • the arbiter may include a comparator or flip-flop for implementing a comparison of input signals of the second input and the third input, wherein a common form of the flip-flop is a D flip-flop.
  • the sampling clock of each stage of the conversion circuit is derived from the clock signal clk.
  • the comparator or the trigger can realize the comparison function.
  • the delay times of the corresponding N first delay devices are T1, T2, T3, ..., Tn, respectively, wherein the delay time of the first delay device in the at least two-stage conversion circuit is different;
  • the output signals Q1 to Qn of the time-to-digital converter are non-linear binary numbers formed by the output signals of the N-stage conversion circuit, and the binary numbers are used to indicate a time difference between the clock signal and the reference signal.
  • Q1 to Qn may specifically be a thermometer code.
  • the indication accuracy of the output signal corresponding to each stage of the conversion circuit in the binary number is determined by the delay time of the first delay unit in the stage conversion circuit.
  • a predetermined number of first delay unit circuits are disposed in the delay in the time-to-digital converter, and the delay time t1 of each first delay unit circuit is the same, assuming the first delay unit circuit
  • the delay time t1 is a unit of time.
  • the first delay unit in each stage of the conversion circuit includes at least one first delay unit circuit, and if the plurality of first delay unit circuits are included in the same delay unit, the plurality of first delay unit circuits are connected in series; The number of first delay unit circuits included in each of the at least two-stage conversion circuits is different.
  • the delay time t1 of the first unit delay circuit can be set to 20 ps, and the number of stages of the time-to-digital converter circuit is 7 steps. , wherein the number of the first delay unit circuits set in the first stage to the seventh stage of the corresponding stage is 1, 1, 2, 4, 8, 16, 32, respectively.
  • a first delay corresponding to a series of delay are 2 0 t1,2 1 t1,2 2 t1,2 3 t1,2 4 t1,2 5 t1,2 6 t1, to achieve an output of 2 codeword index.
  • the time-to-digital converter For higher-order codewords, such as Q7, although there is a larger error than the two-way time interval obtained by the conventional time-to-digital converter, that is, the lower the accuracy, the larger the time interval corresponding to the bit codeword, but At this time, the time-to-digital converter has reduced the area and power consumption of the conventional time-to-digital converter. If the time interval of the two clock signals is relatively short, the time-to-digital converter provided in this embodiment also ensures the accuracy at low input intervals.
  • time-to-digital converter in this embodiment uses the same number of first delay unit circuits as the number of delays of the conventional time-to-digital converter, only seven stages of conversion circuits are required, and only seven arbiters are required. Therefore, the number of arbiters is reduced, and the area and power consumption of the time-to-digital converter are effectively reduced.
  • the delay time t1 of the unit delay circuit is set to 10 ps, and the time-to-digital converter circuit is provided with an 8-level conversion circuit, corresponding to The number of first delay unit circuits provided in a series of first retarders is set to 1, 1, 2, 4, 8, 16, 32, 64, respectively.
  • the delays of the corresponding series of first delays are respectively 2 0 t1, 2 1 t1, 2 2 t1, 2 3 t1, 2 4 t1, 2 5 t1, 2 6 t1, 2 7 t1.
  • the output digital signals Q1 to Q8 are 11111110.
  • the time interval of the two clock signals is between 640 ps and 1280 ps. It can be seen that the accuracy of the digital converter increases with time, and the time provided by this embodiment
  • the digitizer can reduce the number of stages of the circuit while ensuring the dynamic range of the time-to-digital converter as much as possible, reducing the area and power consumption of the time-to-digital converter.
  • time-to-digital converter provided in the above embodiment has omitted some of the delay signals, it is also possible to determine the time interval of the two signals while ensuring the dynamic range of the time-to-digital converter as much as possible, compared with the conventional time-to-digital converter. Moreover, the number of stages of the time-to-digital converter and the number of delay unit circuits in each delay can be flexibly set according to the specific time interval of the two signals.
  • the number of the time-to-digital converter conversion circuit stages and the number of the first delay unit circuits in each of the delay units are only schematic, and may be specifically designed according to actual conditions, such as increasing or decreasing the number of stages of the conversion circuit, Delaying the reference signal ref in turn Signals are square, cubic, or other irregular relationships of natural numbers. For example, if the number of the first delay unit circuits set in the series of first delays is set to 1, 3, 5, 7, ..., respectively, the cumulative delay of the output of the corresponding stages is 1, 4, 9, 16... .
  • the time-to-digital converter circuit provided in this embodiment includes an N-stage conversion circuit, N ⁇ 2, and N is an integer, and each stage conversion circuit includes a first delay unit and an arbiter.
  • the first delay unit of the conversion circuit is provided with a predetermined number of first delay unit circuits, and each of the at least two stages of conversion circuits includes a different number of first delay unit circuits. Since the N-stage conversion circuits have the same first delay unit circuit, ensuring the stability of the delay ratio of each stage of the conversion circuit and the accuracy of the delay time, the number of the first delay unit circuits in each of the first delays can be advanced as needed Setting, therefore, it can effectively reduce the number of circuit stages, reduce circuit area and power consumption for large dynamic range.
  • the accuracy of the above-described time-to-digital converter is limited by the first unit delay circuit, and is at least the delay of a first delay unit circuit.
  • FIG. 3 is a schematic structural diagram of another time-to-digital converter according to an embodiment of the present invention.
  • the time digitizer differs in that each stage of the conversion circuit further includes a second delay unit, and the second delay unit of the first stage conversion circuit is configured to receive the clock signal clk, and each stage of the conversion except the first stage conversion circuit An input of the second delay in the circuit is coupled to an output of the second delay in the previous stage conversion circuit, and an output of the second delay in each stage of the conversion circuit is used to output a sample of the stage conversion circuit clock.
  • a predetermined number of second delay unit circuits are disposed in the second retarder, and the second delay unit circuits are connected in series.
  • the second delay time of the second delay in each stage of the conversion circuit is less than the first delay time of the first delay in the stage conversion circuit.
  • the binary signal output from the output signals Q1 to Qn of the time-to-digital converter provided in this embodiment and the indication precision of the output signal corresponding to each stage of the conversion circuit are delayed by the delay time of the first delay in the stage conversion circuit and the second delay The difference in delay time is determined.
  • the first delay unit circuit and the first stage in the same stage conversion circuit The number of the two delay unit circuits is the same, and it is ensured that the third delay time of the second delay unit circuit is smaller than the fourth delay time of the first delay unit circuit.
  • t1 is the fourth delay time of the first delay unit circuit
  • t2 is the third delay time of the second delay unit circuit.
  • the first delay unit in the first stage conversion circuit is provided with one.
  • the first delay unit circuit, the corresponding second delay of the stage is also provided with a second delay unit circuit, and the remaining N-1 level conversion
  • the first delay unit in the circuit is respectively provided with n1, n2, ..., nx first delay unit circuits
  • the second delay unit circuit disposed in the second delay unit of the corresponding one-stage conversion circuit is also in the same stage
  • the number of first delay unit circuits provided in the first delay is the same.
  • the arbiter for performing two-way signal comparison in the embodiment corresponding to FIG. 3 may include any one of a comparator or a flip-flop, in addition to a synchronous flip-flop.
  • the synchronous triggers of the stages scan the output of the arbiters of each stage by synchronous clocks to ensure that the output signals of the stages are synchronized.
  • the above-mentioned synchronous trigger is similar to the one used by the arbiter, and can also be a simple D flip-flop or other architectural trigger.
  • the reason why the synchronization trigger is added is that the time-to-digital converter provided in this embodiment passes both the clock signals through the delay device, so that the delayed clock signal is not synchronized in the time domain, so a unified clock is required to synchronously output the levels.
  • the synchronous clock is provided by an external circuit.
  • the time interval of two clock signals is 1270 ps.
  • the conventional time-to-digital converter requires a 64-level conversion circuit, and the time number provided in FIG. 1 is used.
  • the converter only needs a 7-stage conversion circuit, but the problem with the time-to-digital converter provided in Figure 1 is that the minimum precision is the delay time of the first delay unit circuit.
  • the time-to-digital converter provided in the embodiment based on the time-to-digital converter provided in FIG. 1, introduces a second delay unit circuit, which also ensures the time number.
  • the converter only needs 7-level conversion circuit, but the accuracy of the time-to-digital converter is t1-t2.
  • t1 and t2 can be arbitrarily selected, only t1 is greater than t2, so the time-to-digital converter in this embodiment Get more flexible accuracy.
  • the conversion circuits of each stage include the same number of first delay unit circuits and second delay unit circuits, thereby ensuring integral nonlinearity/differential nonlinearity (INL/DNL) of the time-to-digital converter circuit.
  • the time-to-digital converter provided in this embodiment further improves the accuracy of the time-to-digital converter compared to the time-to-digital converter provided in FIG. 1, and reduces the accuracy of the time-to-digital converter while reducing the accuracy.
  • the number of circuit stages of the time-to-digital converter reduces the time-to-digital converter area and power consumption.
  • the present invention also provides a nonlinear output delay chain.
  • 5 is a schematic structural diagram of a nonlinear output delay chain.
  • the nonlinear output delay chain includes N delays, N ⁇ 2, and N is an integer, and the delay includes an input.
  • a predetermined number of delay unit circuits are provided in the delay, and the delay unit circuits are connected in series.
  • a plurality of delay unit circuits are connected in series to form a sub-delay chain in the current delay, and the signal input end of the sub-delay chain is connected to the input of the current delay. Connection for receiving signals received from the current delay.
  • the signal is transmitted to the sub-delay chain through the input of the current delay, and is output from the signal output of the sub-delay chain after a delay of some columns.
  • the signal output end of the sub-delay chain is connected to the output of the current delay, and the output of the current delayer receives the delayed signal output from the output of the sub-delay chain signal, and then transmits it to the next adjacent delay device to enter Next delay.
  • the Nth delay unit receives the delayed signal from the output of the N-1th delay unit, and after delay processing, outputs the delay from the output of the Nth delay, ending the delay of the current secondary signal, and the signal processing is the same as the above process. , will not repeat them here.
  • the time-to-digital converters provided in Figures 3 and 4 in this embodiment include at least two non-linear output delay chains, see Figure 6 for a non-linear output delay chain including a first delay unit circuit and The nonlinear output delay chain of the second delay unit circuit, the only difference between the two non-linear output delay chains is the difference in the delay unit circuit provided in the delay. And corresponding to the time-to-digital converter provided in FIG. 4, in the same-stage conversion circuit, the number of the first delay unit circuits is the same as the number of the second delay unit circuits.
  • the fourth delay time t1 of the first delay unit circuit is greater than the third delay time t2 of the second delay unit circuit, and preferably, the fourth delay time t1 and the second delay of the first delay unit circuit
  • the third delay time t2 of the unit circuit is smaller than the ratio t1-t2 because the first delay unit circuit and the second delay unit circuit are used when the time-to-digital converters of FIGS. 4 and 5 are thus used.
  • the smaller the time difference the higher the accuracy of the time-to-digital converter, so that the number of circuit stages of the time-to-digital converter can be reduced while ensuring the accuracy of the time-to-digital converter, and the area of the time-to-digital converter used. Power consumption has been reduced.
  • non-linear output delay chain is not limited to the above two types, and the number of delay units included in the nonlinear output delay chain and the delay unit circuit replacing different delay times can be changed to obtain the nonlinear delay chain required in the actual situation.
  • the examples are no longer listed.
  • the present invention further provides an embodiment of a device. See FIG. 7 is a schematic structural diagram of a device.
  • the device includes a signal generating system and a time-to-digital converter, and the signal generating system and The time to digital converters are connected.
  • the signal generating system is configured to generate two signals and pass the two signals through the signal generating system output end, and the two signal output ends are respectively connected to the two signal input ends of the time digital converter.
  • the time-to-digital converter provided in the device includes an N-stage conversion circuit, N ⁇ 2, and N is an integer.
  • the time to digital converter can use any of the time digital converters provided in FIG. 1 or 3. After the two clock signals generated by the signal generating system are input to the time-to-digital converter, the time interval of the two signals can be obtained according to the code output by the time digital converter.
  • the time-to-digital converter or device provided in this embodiment can be applied to various types including digital phase-locked loops. Use the scene.
  • the reference signal is a reference clock signal of the digital phase locked loop
  • the clock signal is a frequency divided signal of an output signal of the digital phase locked loop.
  • the digital phase locked loop compares the reference clock signal and the divided signal with a time to digital converter to ensure locking.
  • the function of a digital phase-locked loop including a time-to-digital converter causes the time interval of the two input signals of the time-to-digital converter to be continuously reduced, and when the digital phase-locked loop is locked, the time interval of the two input signals is 1 LSB ( Within the least significant digit).
  • the time-to-digital converter when the input time interval is relatively large, as long as the codeword outputted by the time digital converter can correctly guide the adjustment direction of the digital phase-locked loop, the normal locking of the loop can be performed, and the time number is not required.
  • the converter provides a code word for the linear output. Therefore, the time-to-digital converter provided in this embodiment can be well applied to the digital phase-locked loop without affecting the system operation.

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Abstract

本申请提供了一种时间数字转换器及数字锁相环，包括N级转换电路，N≥2，且N为整数，其中，每级转换电路包括第一延迟器和仲裁器；且每级转换电路的第一延迟器的输出端输出该级转换电路的延迟信号；每级转换电路的仲裁器接收该级转换电路的采样时钟和延迟信号并进行比较，以得到该级转换电路的输出信号。N级转换电路的输出信号形成非线性的二进制数，指示时钟信号与参考信号之间的时间差。由于N级转换电路的第一延迟器中均有相同的第一延迟单元电路，确保各级转换电路延迟比例的稳定和延迟时间的精确性，每个第一延迟器中的第一延迟单元电路的数量可以灵活设置，因此对于大动态范围的情况下可以有效的减少电路级数，降低电路面积和功耗。

Description

一种时间数字转换器及数字锁相环 技术领域
本申请涉及电路技术领域，尤其涉及一种时间数字转换器及数字锁相环。
背景技术
时间数字转换器(TDC，Time-to-Digital Converter)通过对时间间隔进行采样和量化，实现时间信号到数字信号的转换。时间数字转换器被广泛用于太空探测、高能物理、测试设备等领域，近年来，时间数字转换器更是作为数字锁相环(DPLL)中的关键模块，得到极大的推广。
数字锁相环中的时间数字转换器结构包括参考时钟信号输入端和采样时钟信号输入端，参考时钟信号输入后会经过多级相同的延迟器。经过第一级延迟器会输出一个延迟时长为t的延迟信号(t为时间数字转换器的精度)，第一级延迟器输出的延迟信号会输入到第二级延迟器，得到一个延迟时长为2倍t的延迟信号，依次类推，第i-1级延迟器获得的延迟信号会输入到第i级延迟器，得到一个延迟时长为i倍t的延迟信号。采样时钟信号分别对上述获得的一系列延迟信号进行采样，获得一系列输出信号。其中时间数字转换器的动态范为t×i,如果保持t不变的情况下，时间数字转换器要获得大的动态范围，则需要增加延迟器的级数；但是延迟器级数的增加直接导致时间数字转换器级数的变大，使得时间数字转换器的面积、功耗都相应增大。
发明内容
本申请提供了一种时间数字转换器及数字锁相环，以在维持时间数字转换器的动态范围的情况下减小时间数字转换器面积和功耗。
第一方面，本发明实施例提供了一种时间数字转换器，包括串联的N级转换电路，N≥2，且N为整数；每级转换电路包括第一延迟器和仲裁器；其中，第一级转换电路中的第一延迟器用于接收参考信号，除第一级转换电路外的每级转换电路中的第一延迟器的输入端耦合至前一级转换电路中的第一延迟器的输出端，且每级转换电路中的第一延迟器的输出端用于输出该级转换电路的延迟信号；每级转换电路中的仲裁器用于接收该级转换电路的采样时钟和该级转换电路的延迟信号，并比较所述采样 时钟和所述延迟信号以得到该级转换电路的输出信号；所述每级转换电路的采样时钟均来源于时钟信号；在所述N级转换电路中，至少两级转换电路中的第一延迟器的延迟时间不同；所述时间数字转换器的输出信号是所述N级转换电路的输出信号所形成非线性的二进制数，该二进制数用于指示所述时钟信号与所述参考信号之间的时间差。采用本实现方式由于N级转换电路至少两级转换电路中的第一延迟器的延迟时间不同，确保所述时间数字转换器输出的非线性，在大动态范围的情况下可以有效的减少电路级数，降低电路面积和功耗。
结合第一方面的实现方式，在第一方面第一种可能的实现方式中，所述每级转换电路中的第一延迟器中包括至少一个第一延迟单元电路；所述至少两级转换电路中每个第一延迟器所包括的第一延迟单元电路的数量不同。
结合第一方面或第一方面第一种可能的实现方式，在第一方面第二种可能的实现方式中，所述每级转换电路的采样时钟均是所述时钟信号。
结合第一方面的实现方式，在第一方面第三种可能的实现方式中，所述每级转换电路还包括第二延迟器；第一级转换电路中的第二延迟器用于接收所述时钟信号，除第一级转换电路外的每级转换电路中的第二延迟器的输入端耦合至前一级转换电路中的第二延迟器的输出端，且每级转换电路中的第二延迟器的输出端用于输出该级转换电路的采样时钟。
结合第一方面第三种可能的实现方式，在第一方面第四种可能的实现方式中，所述每级转换电路中的第二延迟器的第二延迟时间小于该级转换电路中的第一延迟器的第一延迟时间。
结合第一方面第三种或第四种可能的实现方式，在第一方面第五种可能的实现方式中，所述每级转换电路中的第一延迟器中包括至少一个第一延迟单元电路，该级转换电路中的第二延迟器中包括至少一个第二延迟单元电路；所述每级转换电路中的第二延迟器中的第二延迟单元电路的数量等于该级转换电路中的第一延迟器中的第一延迟单元电路的数量；且所述至少两级转换电路中每个第一延迟器所包括的第一延迟单元电路的数量不同。
结合第一方面第五种可能的实现方式，在第一方面第六种可能的实现方式中，所述每级转换电路中的第二延迟器中的第二延迟单元电路的第三延迟时间小于该级转换电路中的第一延迟器中的第一延迟单元电路的第四延迟时间。
结合第一方面第三至六种可能的实现方式其中任意一种，在第一方面第七种可能的实现方式中，所述每级转换电路还包括同步触发器；所述每级转换电路中的所述同 步触发器用于采样该级转换电路所产生的输出信号以同步所述N级转换电路的输出信号。
结合第一方面或第一方面第一至七种可能的实现方式其中任意一种，在第一方面第八种可能的实现方式中，在所述N级转换电路中，至少一级转换电路中的仲裁器是一个仲裁器或触发器。
结合第一方面第八种可能的实现方式，在第一方面第九种可能的实现方式中，所述触发器是D触发器。
结合第一方面或第一方面第一至九种可能的实现方式其中任意一种，在第一方面第十种可能的实现方式中，每级转换电路中的第一延迟器的延迟时间不小于前一级转换电路中的第一延迟器的延迟时间。
结合第一方面第十种可能的实现方式，在第一方面第十一种可能的实现方式中，所述第一级转换电路中的第一延迟器的延迟时间是一个时间单位；所述第j级转换电路中的第一延迟器的延迟时间是2j-2个时间单位，j＝2，3，……N。
结合第一方面或第一方面第一至十一种可能的实现方式其中任意一种，在第一方面第十二种可能的实现方式中，所述参考信号是另一时钟信号。
结合第一方面或第一方面第一至十二种可能的实现方式其中任意一种，在第一方面第十三种可能的实现方式中，所述二进制数是温度计码。
第二方面，本发明实施例还提供了一种数字锁相环，其特征在于，包括如第一方面或第一方面第一至十三种可能的任意一种时间数字转换器，所述参考信号是所述数字锁相环的参考时钟信号，所述时钟信号是所述数字锁相环的输出信号的分频信号。
附图说明
为了更清楚地说明本申请的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，对于本领域普通技术人员而言，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例提供的一种时间数字转换器的结构示意图；
图2为本发明实施例提供的第一延迟器的结构示意图；
图3为本发明实施例提供的另一种时间数字转换器的结构示意图；
图4为本发明实施例提供的一种7级转换电路的时间数字转换器的结构示意图；
图5为本发明实施例提供的一种非线性输出延迟链结构示意图；
图6为本发明实施例提供的两种不同的非线性输出延迟链的结构示意图；
图7为本发明实施例提供的一种设备的结构示意图。
具体实施方式
参见图1，为一种时间数字转换器的结构示意图，如图1所示，所述时间数字转换器包括N级转换电路，N≥2，且N为整数。第一级转换电路中的第一延迟器用于接收参考信号ref，除第一级转换电路外的每级转换电路中的第一延迟器的输入端耦合至前一级转换电路中的第一延迟器的输出端，且每级转换电路中的第一延迟器的输出端用于输出该级转换电路的延迟信号，所述参考信号可以是一个时钟。
每级转换电路中的仲裁器用于接收该级转换电路的采样时钟和该级转换电路的延迟信号，并比较所述采样时钟和所述延迟信号以得到该级转换电路的输出信号。例如，所述仲裁器可以包括比较器或触发器(Flip-Flop)，用于实现第二输入端和第三输入端的输入信号的比较，其中触发器的常见形式是D触发器。所述每级转换电路的采样时钟均来源于时钟信号clk。其中比较器或触发器均可实现比较的功能。
在所述N级转换电路中，对应的N个所述第一延迟器的延迟时间分别为T1、T2、T3……Tn，其中至少两级转换电路中的第一延迟器的延迟时间不同；所述时间数字转换器的输出信号Q1至Qn是所述N级转换电路的输出信号所形成非线性的二进制数，该二进制数用于指示所述时钟信号与所述参考信号之间的时间差，Q1至Qn具体可以是温度计码。其中，所述二进制数中与每级转换电路对应的输出信号的指示精度由该级转换电路中第一延迟器的延迟时间决定。
如图2所示，所述时间数字转换器中的延迟器中设置有预定数量的第一延迟单元电路，且每个第一延迟单元电路的延迟时间t1是相同的，假设第一延迟单元电路的延迟时间t1是一个时间单位。所述每级转换电路中的第一延迟器中包括至少一个第一延迟单元电路，同一延迟器中如果包含有多个第一延迟单元电路，则多个第一延迟单元电路是串联连接的；所述至少两级转换电路中每个第一延迟器所包括的第一延迟单元电路的数量不同。
对本实施例图1的时间数字转换器，假设参考信号ref和时钟信号clk的时间间隔为1270ps，可以设置第一单元延迟电路的延迟时间t1为20ps,时间数字转换器电路的级数为7级，其中从第1级到第7级转换电路，对应的一些列第一延迟器中设置的第一延迟单元电路个数分别为1,1,2,4,8,16,32。对应的一系列第一延迟器的延迟分别 为20t1，21t1，22t1，23t1，24t1，25t1，26t1，实现了2的指数的输出码字。此时对应输出的一系列的第一时钟的延迟信号相应延迟20ps，40ps，120ps……640ps，1280ps。相应地，输出的数字信号Q1至Q7为1111110，因此可以判断两路时钟信号的时间间隔为640ps至1280ps之间，即1280ps-640ps＝640ps，因此Q1至Q7中的每一个码字随对应的时间间隔(Tres)是不同的，因此本实施例提供的码字输出是非线性的。对于更高位的码字，如Q7而言，虽然相比传统的时间数字转换器获得的两路时间间隔存在更大的误差，即精度越低，该位码字对应的时间间隔越大，但是此时的时间数字转换器相比常用的时间数字转换器的面积和功耗都得到了降低。如果上述两路时钟信号时间间隔比较短时，本实施例提供的时间数字转换器同样保证低输入间隔时的精度。
本实施例中的时间数字转换器虽然使用的第一延迟单元电路的个数与常用的时间数字转换器的延迟器个数相同，但是只需要7级转换电路，对应的只需要7个仲裁器，因此减少了仲裁器的个数，有效的降低了时间数字转换器的面积和功耗。
仍然以参考信号ref和时钟信号clk的时间间隔为1270ps为例，假设此时将时间数字转换器的精度调整为10ps，对用的常用的时间数字转换器，则每个延迟器的延迟时间为10ps,则需要128级的转换电路，可想而知，此时的时间数字转换器要设置有128个仲裁器，对应的电路的面积和功耗是非常大的。如果采用本实施例图1的时间数字转换器，因为要保证时间数字转换器的精度为10ps，因此设置单元延迟电路的延迟时间t1为10ps,时间数字转换器电路设置8级转换电路，对应的一系列第一延迟器中设置的第一延迟单元电路的个数分别设置为1，1，2，4，8，16，32，64。对应的一系列第一延迟器的延迟分别为20t1，21t1，22t1，23t1，24t1，25t1，26t1，27t1。此时，输出的数字信号Q1至Q8为11111110，此时可以判断两路时钟信号的时间间隔为640ps至1280ps之间，可以看出随着时间数字转换器精度的提高，本实施例提供的时间数字转换器可以在尽可能保证时间数字转换器动态范围的同时降低电路的级数，降低了时间数字转换器的面积和功耗。
上述实施例中提供的时间数字转换器虽然略去了部分的延迟信号，但是相比常用的时间数字转换器同样可以在尽可能保证时间数字转换器动态范围的同时判断两路信号的时间间隔，而且可以根据两路信号的具体时间间隔可以对时间数字转换器的级数和每个延迟器中的延迟单元电路的个数灵活设定。当然上述时间数字转换器转换电路级数和每个延迟器中的第一延迟单元电路的个数设定只是示意性的，可以根据实际情况具体设计，比如可以增加或减少转换电路的级数、将参考信号ref依次延迟后的 信号呈自然数的平方、立方或其他不规则关系。例如，一系列第一延迟器中设置的第一延迟单元电路的个数分别设置为1,3,5,7……，则对应各级输出的累计延迟是1,4,9,16……。
由上述实施例可见，本实施例提供的一种时间数字转换器电路，包括N级转换电路，N≥2，且N为整数，所述每级转换电路包括第一延迟器和仲裁器，所述转换电路的第一延迟器中设置有预定数量的第一延迟单元电路，所述至少两级转换电路中每个第一延迟器所包括的第一延迟单元电路的数量不同。由于N级转换电路均有相同的第一延迟单元电路，确保各级转换电路延迟比例的稳定和延迟时间的精确性，每个第一延迟器中的第一延迟单元电路的数量可以根据需要预先设置，因此对于大动态范围的情况下可以有效的减少电路级数，降低电路面积和功耗。
但是上述时间数字转换器的精度受到第一单元延迟电路的限制，最小为一个第一延迟单元电路的延迟。
与本发明提供的一种时间数字转换器实施例相对应，参见图3，为本发明实施例提供的另外一种时间数字转换器的结构示意图，所述时间数字转换器与图1中提供的时间数字转换器不同的是，每级转换电路中还包括第二延迟器，第一级转换电路中的第二延迟器用于接收所述时钟信号clk，除第一级转换电路外的每级转换电路中的第二延迟器的输入端耦合至前一级转换电路中的第二延迟器的输出端，且每级转换电路中的第二延迟器的输出端用于输出该级转换电路的采样时钟。
所述第二延迟器中设置有预定数量的第二延迟单元电路，且所述第二延迟单元电路串联连接。所述每级转换电路中的第二延迟器的第二延迟时间小于该级转换电路中的第一延迟器的第一延迟时间。本实施例中提供的时间数字转换器的输出信号Q1至Qn输出的二进制数与每级转换电路对应的输出信号的指示精度由该级转换电路中第一延迟器的延迟时间和第二延迟器的延迟时间的差值决定。
优选地，为了保证每级转换电路中的第二延迟器的第二延迟时间小于该级转换电路中的第一延迟器的第一延迟时间，同一级转换电路中的第一延迟单元电路和第二延迟单元电路的数量相同，而且要保证所述第二延迟单元电路的第三延迟时间小于所述第一延迟单元电路的第四延迟时间。
图3中，t1为第一延迟单元电路的第四延迟时间，t2为第二延迟单元电路的第三延迟时间，在本实施例中为第一级转换电路中的第一延迟器设置有一个第一延迟单元电路，对应的该级的第二延迟器也设置了一个第二延迟单元电路，剩余的N-1级转换 电路中第一延迟器中分别设置有n1、n2……nx个第一延迟单元电路，对应的同一级转换电路中的第二延迟器中设置的第二延迟单元电路也与该级转换电路中的第一延迟器中设置的第一延迟单元电路的个数相同。
进一步的，还与图1中提供的时间数字转换器不同的，图3提供的时间数字转换器的每级仲裁器或触发器之后还可增加同步触发器。因此，图3对应的实施例中用于进行两路信号比较的仲裁器可包括比较器或触发器中的任一种，此外再加上同步触发器。所述各级同步触发器通过同步时钟采样各级仲裁器的输出，保证各级输出信号同步。上述同步触发器与仲裁器所使用的触发器类似，也可以是简单的D触发器或其他架构的触发器。增加该同步触发器的原因，在于本实施例提供的时间数字转换器，两路时钟信号均经过延迟器，导致延迟后的时钟信号时域上不同步，因此需要统一的时钟将各级同步输出，其中同步时钟由外部电路提供。
在本实施例中仍以两路时钟信号时间间隔为1270ps为例，在时间数字转换器精度为20ps的前提下，传统的时间数字转换器需要64级转换电路，而使用图1提供的时间数字转换器则只需要7级转换电路即可，但是图1提供的的时间数字转换器出现的问题就是，精度最小是一个第一延迟单元电路的延迟时间。在该实施例中，可参见图4，在本实施例中提供的时间数字转换器，在图1提供的时间数字转换器的基础上，引入了第二延迟单元电路，同样保证所述时间数字转换器只需要7级的转换电路，但是所述时间数字转换器的精度为t1-t2，理论上t1和t2可以任意取值，只需t1大于t2，因此本实施例中的时间数字转换器可以获得更灵活的精度。而且各级的转换电路均包含有相同数量的第一延迟单元电路和第二延迟单元电路，因此可以保证时间数字转换器电路的积分非线性/差分非线性(INL/DNL)。
由上述实施例可见，本实施例提供的时间数字转换器相比图1中提供的时间数字转换器，进一步提高了时间数字转换器的精度，而且在保证时间数字转换器精度的同时，减少了时间数字转换器的电路级数，从而使得时间数字转换器面积和功耗都得到了降低。
与上述实施例提供的时间数字转换器实施例相对应，本发明还提供了一种非线性输出延迟链。参见图5，为一种非线性输出延迟链的结构示意图，如图5所示，所述非线性输出延迟链包括N个延迟器，N≥2，且N为整数，所述延迟器包括输入端和输出端，第j-1个延迟器的输出端与第j个延迟器的输入端相连，j＝2,3……N。所述延迟器中设置有预定数量的延迟单元电路，所述延迟单元电路串联连接。
参见图5中的下方对于其中一级延迟器的放大图，多个延迟单元电路串联后在当前延迟器内形成一个子延迟链，所述子延迟链的信号输入端与当前延迟的输入端相连接，用于接收来自当前延迟器接收的信号。所述信号通过当前延迟器的输入端传输进入子延迟链后，经过一些列的延迟处理，从子延迟链的信号输出端输出。所述子延迟链的信号输出端与当前延迟器的输出端相连接，当前延迟器的输出端接收来自子延迟链信号输出端输出的延迟信号，然后传输给下一个相邻的延迟器，进入下一个延迟器。只有第N个延迟单元接收来自第N-1个延迟单元输出的延迟信号，经延迟处理后，从第N个延迟器的输出端输出，结束当前次信号的延迟，信号的处理与上述过程相同，在此不再赘述。
在本实施例中的图3和图4中提供的时间数字转换器，至少包含有两种非线性输出延迟链，参见图6为包含有第一延迟单元电路的非线性输出延迟链和包含有第二延迟单元电路的非线性输出延迟链，两种非线性输出延迟链唯一的不同就在于设置在延迟器中的延迟单元电路的不同。且对应图4提供的时间数字转换器，同一级转换电路中，第一延迟单元电路的个数与第二延迟单元电路的个数是相同的。所述第一延迟单元电路的第四延迟时间t1大于所述第二延迟单元电路的第三延迟时间t2，优选的，所述第一延迟单元电路的第四延迟时间t1与所述第二延迟单元电路的第三延迟时间t2相差比t1-t2较小，因为这样运用在图4和图5中的时间数字转换器的时候，所述第一延迟单元电路与所述第二延迟单元电路的时间差越小，所述时间数字转换器的精度越高，这样就可以在保证时间数字转换器精度高的同时，减小时间数字转换器的电路级数，对用的时间数字转换器的面积和功耗都得到了减小。当然所述非线性输出延迟链不限于上述两种，可以改变非线性输出延迟链中包含的延迟单元个数和替换不同延迟时间的延迟单元电路，获得实际情况中需要的非线性延迟链，具体例子不再列举。
本发明还提供了一种设备的实施例，参见图7所示为一种设备的结构示意图，如图7所示，所述设备包括信号发生系统和时间数字转换器，所述信号发生系统与所述时间数字转换器相连接。其中所述信号发生系统用于生成两路信号并将两路信号通过该信号发生系统输出端，两个信号输出端分别与时间数字转换器的两个信号输入端相连接。所述设备中设置的时间数字转换器包括有N级的转换电路，N≥2，且N为整数。所述时间数字转换器可以使用图1或图3提供的任一时间数字转换器。所述信号发生系统生成的两路时钟信号输入到时间数字转换器后，可以根据时间数字转换器输出的码子，获得两路信号的时间间隔。
本实施例提供的时间数字转换器或设备可适用于包括数字锁相环在内的各类应 用场景。所述参考信号是所述数字锁相环的参考时钟信号，所述时钟信号是所述数字锁相环的输出信号的分频信号。数字锁相环通过时间数字转换器实现比较参考时钟信号和所述分频信号以保证锁定。例如，包括时间数字转换器的数字锁相环的作用使得该时间数字转换器的两路输入信号的时间间隔在不断缩小，而在数字锁相环锁定时，两路输入信号时间间隔在1LSB(最低有效位)内。因此对于时间数字转换器，在输入时间间隔比较大时，只要保证时间数字转换器输出的码字能够正确引导数字锁相环的调节方向，即可使得环路的正常锁定，不需要该时间数字转换器提供线性输出的码字。因此本实施例提供的时间数字转换器可以很好的适用于数字锁相环，不会影响系统工作。
本说明书中各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。诸如“第一”和“第二”等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。此外，本发明实施例中涉及的“连接”应被理解为是一种通信连接或电性连接，其不仅包括直接通过导线或数据线连接，也包括通过其他元件间接连接，其含义类似于耦合或偶接。以上所述的本发明实施方式并不构成对本发明保护范围的限定。

Claims (15)

  1. 一种时间数字转换器，其特征在于，包括串联的N级转换电路，N≥2，且N为整数；
    每级转换电路包括第一延迟器和仲裁器；其中，
    第一级转换电路中的第一延迟器用于接收参考信号，除第一级转换电路外的每级转换电路中的第一延迟器的输入端耦合至前一级转换电路中的第一延迟器的输出端，且每级转换电路中的第一延迟器的输出端用于输出该级转换电路的延迟信号；
    每级转换电路中的仲裁器用于接收该级转换电路的采样时钟和该级转换电路的延迟信号，并比较所述采样时钟和所述延迟信号以得到该级转换电路的输出信号；所述每级转换电路的采样时钟均来源于时钟信号；
    在所述N级转换电路中，至少两级转换电路中的第一延迟器的延迟时间不同；所述时间数字转换器的输出信号是所述N级转换电路的输出信号所形成非线性的二进制数，该二进制数用于指示所述时钟信号与所述参考信号之间的时间差。
  2. 根据权利要求1所述的时间数字转换器，其特征在于，所述每级转换电路中的第一延迟器中包括至少一个第一延迟单元电路；所述至少两级转换电路中每个第一延迟器所包括的第一延迟单元电路的数量不同。
  3. 根据权利要求1或2所述的时间数字转换器，其特征在于，所述每级转换电路的采样时钟均是所述时钟信号。
  4. 根据权利要求1所述的时间数字转换器，其特征在于，所述每级转换电路还包括第二延迟器；
    第一级转换电路中的第二延迟器用于接收所述时钟信号，除第一级转换电路外的每级转换电路中的第二延迟器的输入端耦合至前一级转换电路中的第二延迟器的输出端，且每级转换电路中的第二延迟器的输出端用于输出该级转换电路的采样时钟。
  5. 根据权利要求4所述的时间数字转换器，其特征在于，所述每级转换电 路中的第二延迟器的第二延迟时间小于该级转换电路中的第一延迟器的第一延迟时间。
  6. 根据权利要求4或5所述的时间数字转换器，其特征在于，所述每级转换电路中的第一延迟器中包括至少一个第一延迟单元电路，该级转换电路中的第二延迟器中包括至少一个第二延迟单元电路；
    所述每级转换电路中的第二延迟器中的第二延迟单元电路的数量等于该级转换电路中的第一延迟器中的第一延迟单元电路的数量；且
    所述至少两级转换电路中每个第一延迟器所包括的第一延迟单元电路的数量不同。
  7. 根据权利要求6所述的时间数字转换器，其特征在于，所述每级转换电路中的第二延迟器中的第二延迟单元电路的第三延迟时间小于该级转换电路中的第一延迟器中的第一延迟单元电路的第四延迟时间。
  8. 根据权利要求4-7中任一项所述的时间数字转换器，其特征在于，所述每级转换电路还包括同步触发器；
    所述每级转换电路中的所述同步触发器用于采样该级转换电路所产生的输出信号以同步所述N级转换电路的输出信号。
  9. 根据权利要求1-8中任一项所述的时间数字转换器，其特征在于，在所述N级转换电路中，至少一级转换电路中的仲裁器是一个仲裁器或触发器。
  10. 根据权利要求9所述的时间数字转换器，其特征在于，所述触发器是D触发器。
  11. 根据权利要求1-10中任一项所述的时间数字转换器，其特征在于，每级转换电路中的第一延迟器的延迟时间不小于前一级转换电路中的第一延迟器的延迟时间。
  12. 根据权利要求11所述的时间数字转换器，其特征在于，所述第一级转换电路中的第一延迟器的延迟时间是一个时间单位；
    所述第j级转换电路中的第一延迟器的延迟时间是2j-2个时间单位，j＝2，3，……N。
  13. 根据权利要求1-12中任一项所述的时间数字转换器，其特征在于，所述参考信号是另一时钟信号。
  14. 根据权利要求1-13中任一项所述的时间数字转换器，其特征在于，所述二进制数是温度计码。
  15. 一种数字锁相环，其特征在于，包括如权利要求1至14任一项所述的时间数字转换器，所述参考信号是所述数字锁相环的参考时钟信号，所述时钟信号是所述数字锁相环的输出信号的分频信号。
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