WO2017202158A1 - 转发数据的方法和设备 - Google Patents

转发数据的方法和设备 Download PDF

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Publication number
WO2017202158A1
WO2017202158A1 PCT/CN2017/080893 CN2017080893W WO2017202158A1 WO 2017202158 A1 WO2017202158 A1 WO 2017202158A1 CN 2017080893 W CN2017080893 W CN 2017080893W WO 2017202158 A1 WO2017202158 A1 WO 2017202158A1
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WIPO (PCT)
Prior art keywords
data unit
logical
port
sequence stream
unit sequence
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PCT/CN2017/080893
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English (en)
French (fr)
Inventor
钟其文
张小俊
徐小飞
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Publication date
Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Priority to EP17802004.6A priority Critical patent/EP3447974B1/en
Publication of WO2017202158A1 publication Critical patent/WO2017202158A1/zh
Priority to US16/201,411 priority patent/US10951512B2/en
Anticipated expiration legal-status Critical
Priority to US17/200,555 priority patent/US20210203588A1/en
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/12—Shortest path evaluation
    • H04L45/125—Shortest path evaluation based on throughput or bandwidth
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
    • H04J3/1605—Fixed allocated frame structures
    • H04J3/1652—Optical Transport Network [OTN]
    • H04J3/1658—Optical Transport Network [OTN] carrying packets or ATM cells
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/12—Shortest path evaluation
    • H04L45/121—Shortest path evaluation by minimising delays
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
    • H04Q11/0005—Switch and router aspects
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J2203/00—Aspects of optical multiplex systems other than those covered by H04J14/05 and H04J14/07
    • H04J2203/0001—Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
    • H04J2203/0073—Services, e.g. multimedia, GOS, QOS
    • H04J2203/0082—Interaction of SDH with non-ATM protocols
    • H04J2203/0085—Support of Ethernet
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L2007/045—Fill bit or bits, idle words

Definitions

  • the present application relates to the field of communications and, more particularly, to a method and apparatus for forwarding data.
  • packet data forwarding is generally performed on a packet-by-packet basis by a packet device (or a forwarding device). Specifically, the packet device performs table lookup based on information such as a destination address and a tag included in the packet data unit (or referred to as a message), and determines a forwarding behavior of the packet data. For example, a packet device Ethernet switch in Ethernet determines a port based on a Medium Access Control (MAC) address lookup table. For example, Multi-Protocol Label Switching (MPLS) determines the processing and forwarding behavior of packets based on MPLS packet labels. Fibre Channel (FC) switches, InfiniBand switches, Internet Protocol (IP) routers, etc. also have similar packet data forwarding mechanisms. The size, scale, and inconsistency of lookup tables in various network systems are time-consuming and difficult to look up.
  • MPLS Multi-Protocol Label Switching
  • the simplest Ethernet exchange complies with the 802.1d standard, and the source MAC address and the destination MAC address in the packets that meet the integrity requirements after the CRC check are required to be identified.
  • the source MAC address is learned to maintain a lookup table of the correspondence between the learned destination MAC address and the egress port (that is, the forwarding destination port).
  • the destination MAC address of the packets arriving on all the ingress ports is matched and matched, and the outbound port is obtained. Then, the packet data unit buffer queue of the corresponding egress port is queued, and waiting to be sent out from the egress port.
  • Ethernet 802.1q standard further introduces more tags to distinguish different services and flows, and introduces other ways to maintain the forwarding decision lookup table to support more flexible forwarding decisions, but the mechanism remains unchanged.
  • Fibre Channel switches, InfiniBand switches, IP routers, etc. are similar in general.
  • the mechanism for forwarding the decision information, such as the destination address, the label, and the like, and forwarding the packet data unit on a packet-by-packet basis makes the forwarding delay of the entire packet data larger.
  • packets arriving from each ingress port are both bursty and uncertain.
  • buffering and queuing are necessary.
  • the number of packets sent from an egress port is relatively small, which is far lower than the service capability of the egress port, and the egress port has idle or transmits idle padding information, resulting in Port service capability and waste of outbound port bandwidth.
  • the service capacity and bandwidth utilization of the outbound port reach a certain ratio, for example, 95%.
  • the most effective measure is to maintain a certain service packet buffer queue length for each outgoing port. Therefore, the exchange of packet data by existing packet devices is generally described as store-and-forward.
  • the present application provides a method and device for forwarding data, which can improve service throughput and reduce data forwarding delay.
  • the present application provides a method for forwarding data, including: acquiring, by a first logical ingress port, a first data unit sequence stream, where the first data unit sequence stream includes at least one first data unit; Determining, by the mapping relationship between the at least one logical ingress port and the at least one logical egress port, a first logical egress port corresponding to the first logical ingress port, where the at least one logical ingress port includes the first logical ingress port; Describe the number of idle cells in the first data unit sequence stream, such that the adjusted rate of the first data unit sequence stream matches the rate of the first logical out port; sending the adjustment through the first logical out port The first sequence of data units after the stream.
  • the first logical ingress port may correspond to at least one physical inbound interface or at least one time slot of the at least one physical inbound interface, where the first logical egress port may correspond to at least one physical outbound interface or at least one physical inbound interface.
  • One time slot may correspond to
  • the first data unit sequence stream may further include at least one idle unit.
  • the method and apparatus for forwarding data of the present application can be based on a variety of network technologies and protocols.
  • a logical port is provided based on a plurality of network physical interfaces, the logical port is independent of the specific form of the physical interface; secondly, it is independent of the protocol type of the data unit being forwarded, and the data may be various protocols, and does not need to be
  • the fields in the data unit are parsed for a specific protocol.
  • the data unit sequence stream is forwarded through a direct mapping relationship between logical ports, and the rate matching between the data unit sequence stream and the downstream outbound port is implemented by adjusting the number of idle units, thereby effectively reducing the forwarding pressure of the forwarding device, and effectively Improve the service throughput of the forwarding device, reduce the forwarding delay of data, and adapt to the delay-sensitive large-bandwidth service.
  • the mapping relationship between the at least one logical ingress port and the at least one logical egress port may include at least one of the following mapping relationships: one of the at least one logical ingress port and the at least one logical egress port a one-to-one mapping relationship of one of the logical out ports; a one-to-many mapping relationship between one of the at least one logical in port and the plurality of logical out ports of the at least one logical out port; A many-to-one mapping relationship between a plurality of logical ingress ports and at least one logical out port of the at least one logical ingress port.
  • the logical ingress port and the logical egress port can form a one-to-one, one-to-many, many-to-one, and many-to-many mapping relationship.
  • the physical interface corresponding to each of the logical ingress port and the logical out port of the at least one logical egress port is the following type Interface: optical transport network OTN interface, flexible optical transport network FlexOTN interface, Ethernet interface, flexible Ethernet FlexE interface, universal public wireless interface CPRI, synchronous digital system SDH interface, Fibre Channel FC interface or unlimited bandwidth InfiniBand interface.
  • the at least one first data unit includes at least one of the following data units: an OTN data unit, a FlexOTN data unit, an Ethernet packet data unit, a FlexE packet data unit, CPRI data unit, synchronous digital system SDH data unit, FC data unit and InfiniBand Data unit.
  • the physical interfaces corresponding to the at least two logical ingress ports respectively are an optical transport network OTN interface, and flexible optical transmission At least two of a network FlexOTN interface, an Ethernet interface, a flexible Ethernet FlexE interface, a universal public wireless interface CPRI, a synchronous digital system SDH interface, a Fibre Channel FC interface, and an infinite bandwidth InfiniBand interface; and/or when at least one logical outgoing port
  • the physical interfaces corresponding to at least two logical egress ports are an optical transport network OTN interface, a flexible optical transport network FlexOTN interface, an Ethernet interface, a flexible Ethernet FlexE interface, and a general public radio interface CPRI. At least two of the synchronous digital system SDH interface, the Fibre Channel FC interface, and the infinite bandwidth InfiniBand interface.
  • the adjusting the number of idle cells in the first data unit sequence stream includes: when the first data unit sequence stream includes an idle unit, adding or Reducing the number of free cells in the first data unit sequence stream; increasing the number of free cells in the first data unit sequence stream when the first data unit sequence stream does not include an idle unit. So that the data unit sequence stream received by the first logical ingress port includes both the first data unit and the idle unit, or the data unit sequence stream received by the first logical input port includes only the first In the case where a data unit does not include an idle unit, rate matching of the data unit sequence stream received by the first logical ingress port can be performed.
  • a total bandwidth of the at least one first data unit in the first data unit sequence stream is less than or equal to a saturation bandwidth of the first logical in port, and is smaller than Or equal to the saturation bandwidth of the first logical out port.
  • the first data unit sequence stream is an encoded data unit sequence stream
  • the adjusting the number of idle units in the first data unit sequence stream includes: Decoding the first data unit sequence stream; adjusting the number of idle bytes in the decoded first data unit sequence stream, such that the adjusted first data unit sequence stream rate and the first logical output port are Rate matching; encoding the adjusted first data unit sequence stream; sending the adjusted first data unit sequence stream by using the first logical output port, including: sending by using the first logical output port The adjusted and encoded first sequence of data unit streams.
  • the encoding may be 64/66B encoding, 8/10B encoding, 512/513B encoding or 512/514B encoding; correspondingly, the decoding may be 64/66B decoding, 8/10B decoding, 512/513B decoding or 512/514B decoding. .
  • the first data unit sequence stream is an encoded data unit sequence stream
  • the adjusting the number of idle units in the first data unit sequence stream includes: Adjusting the number of encoded idle symbols in the first data unit sequence stream such that the adjusted rate of the first data unit sequence stream matches the rate of the first logical out port.
  • the method further includes: acquiring, by the second logical ingress port, a second data unit sequence stream, where the second data unit sequence stream includes at least one second data unit, Each of the at least one second data unit includes forwarding decision reference information in each of the at least one second data unit; and determining, according to the forwarding decision reference information, each second data unit of the at least one second data unit a second logical output port; the second data unit is cached in a buffer queue of the corresponding second logical output port; and the second logical unit is sent through the second logical output port The second data unit.
  • the forwarding decision reference information may include a destination address, a forwarding label, and the like.
  • the present application further provides an apparatus for forwarding data, where the apparatus includes a first logical ingress port, a first logical egress port, a mapping relationship control module, and a rate matching module, where the first logical ingress port is used for Obtaining a first data unit sequence stream, where the first data unit sequence stream includes at least one first data unit; the mapping relationship control module is configured to perform, according to the preconfigured at least one logical in port and the at least one logical out port a mapping relationship, the first logical ingress port corresponding to the first logical ingress port is determined, the at least one logical ingress port includes the first logical ingress port, and the rate matching module is configured to adjust the first data unit
  • the number of idle cells in the sequence stream is such that the rate of the adjusted first data unit sequence stream matches the rate of the first logical out port; the first logical out port is configured to send the adjusted A stream of data unit sequences.
  • the corresponding module is used to complete the method for forwarding data in the first aspect of the present application
  • mapping relationship between the pre-configured multiple logical ingress ports and the multiple logical egress ports may be updated according to the valid time period of the logical ingress port and the logical egress port.
  • the first data unit may or may not include padding.
  • 1 is a schematic diagram showing the structure of an Ethernet packet data unit sequence stream.
  • FIG. 2 is a schematic diagram of a conventional packet data forwarding process.
  • FIG. 3 is a schematic diagram of a method of forwarding data according to an embodiment of the present application.
  • FC frame 4 is a schematic structural diagram of an FC frame.
  • FIG. 5 is a schematic diagram of a mapping relationship between a logical ingress port and a logical egress port according to an embodiment of the present application.
  • FIG. 6 is a schematic diagram of rate matching by adjusting the number of idle cells according to an embodiment of the present application.
  • FIG. 7 is a schematic diagram of adjusting an idle unit in several embodiments of the present application.
  • FIG. 8 is a schematic diagram of a manner of performing rate matching according to an embodiment of the present application.
  • FIG. 9 is a schematic diagram of a manner of performing rate matching according to another embodiment of the present application.
  • FIG. 10 is a schematic diagram of a method for forwarding data according to another embodiment of the present application.
  • FIG. 11 is a schematic block diagram of an apparatus for forwarding data according to an embodiment of the present application.
  • a component can be, but is not limited to being, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, and/or a computer.
  • an application running on a computing device and a computing device can be a component.
  • One or more components can reside within a process and/or execution thread, and the components can be located on one computer and/or distributed between two or more computers.
  • these components can execute from various computer readable media having various data structures stored thereon.
  • a component may, for example, be based on signals having one or more data packets (eg, data from two components interacting with another component between the local system, the distributed system, and/or the network, such as the Internet interacting with other systems) Communicate through local and/or remote processes.
  • data packets eg, data from two components interacting with another component between the local system, the distributed system, and/or the network, such as the Internet interacting with other systems
  • OTN Optical Transport Network
  • Flexible OTN Flexible Optical Network
  • Ethernet Ethernet
  • FlexE Flexible Ethernet
  • CPRI Common Public Radio Interface
  • SDH Synchronous Digital Hierarchy
  • FC Fibre Channel
  • InfiniBand network and the like are not limited in this embodiment of the present application.
  • a plurality of data units having substantial contents constitute a data unit sequence stream, and the data unit sequence stream may include an idle (IDLE) unit or may not include idle. unit.
  • the free cells may also have different forms depending on the network.
  • the idle unit may be an idle symbol or an idle byte, and may also be an Inter-Packet Gap (IPG).
  • IPG Inter-Packet Gap
  • the data unit is an Ethernet packet data unit, an idle unit that can be inserted between the Ethernet packet data unit and the Ethernet packet data unit, and the idle unit can be an idle symbol or an idle byte.
  • FIG. 1 is a schematic diagram showing the structure of a packet data unit sequence stream of Ethernet.
  • the ports of the Ethernet packet device (including the in port and the egress port) transmit data from left to right over time.
  • the idle unit (usually the idle symbol formed by encoding the idle byte) is always transmitted; when there is an Ethernet packet data unit for transmission, the Ethernet is transmitted.
  • Packet data unit (usually also after encoding).
  • the Ethernet packet data unit is simplified for writing packet data units for the sake of brevity.
  • Case A is that the Ethernet port does not transmit an Ethernet packet data unit for a certain period of time, and continuously transmits idle units to maintain the normal transmission and reception status of hardware on both sides of the Ethernet port.
  • Case B is that another Ethernet packet data unit needs to be transmitted in another period of time, and then the Ethernet packet data unit and the idle unit form a packet data unit sequence stream.
  • the figure mainly shows the packet data unit n-1, the packet data unit n and the packet data unit n+1, and the idle unit between each packet data unit.
  • the Ethernet packet data unit usually has a variable length within a certain range.
  • the idle unit between the two Ethernet packet data units usually includes at least 12 bytes, and the length is not limited.
  • the minimum number of bytes required for an idle cell can vary. For example, the minimum number of idle cells allowed by the receiving side of 10 Gigabit Ethernet (10GE) is 5; the minimum interframe free cell allowed by the receiving side of 100 Gigabit Ethernet (100GE) The number of bytes is 1.
  • Ethernet packet data unit A typical package of Ethernet packet data units is shown in Figure 1, with an 8-bit tuple (or byte) as the basic unit.
  • An Ethernet packet data unit first contains the first 7 bytes of the preamble "0x55 0x55 0x55 0x55 0x55 0x550x55 0x55", and the 1-byte frame start delimiter field sfd (Start-of-Frame Delimiter, SFD) "0xD5".
  • sfd Start-of-Frame Delimiter
  • a 6-byte length destination MAC address a 6-byte length source MAC address
  • a 2-byte length packet type/length information a minimum length of 46 bytes of packet payload information and padding information bytes (load When it is less than 46 bytes, it is padded to 46 bytes with padding (Pad/Padding, PAD).
  • a 4-byte frame check byte such as a Cyclic Redundancy Code (CRC) check, is used to verify the integrity of the packet.
  • CRC Cyclic Redundancy Code
  • the first byte in the free unit after the Ethernet packet data unit is used as a control byte, specifically an End-of-Frame Delimiter (EFD).
  • EDD End-of-Frame Delimiter
  • an Ethernet port usually appears as a logical concept for data, called a logical port or simply a port.
  • An Ethernet physical interface appears as a concept on a hardware, called a physical interface or simply an interface.
  • an Ethernet port is tagged with a MAC address.
  • the rate of the Ethernet port is determined based on the rate of the Ethernet physical interface.
  • the maximum bandwidth of an Ethernet port corresponds to the bandwidth of an Ethernet physical interface, such as 10 Mbps, 100 Mbps, 1000 Mbps (1 Gbps), 10 Gbps, 40 Gbps, 100 Gbps, and 400 Gbps Ethernet physical interfaces.
  • Ethernet has gained widespread adoption and significant growth over the past quite a while.
  • Ethernet port rate With 10 times improvement, it has evolved from 10 Mbps to 100 Mbps, 1000 Mbps (1 Gbps), 10 Gbps, 40 Gbps, 100 Gbps, and 400 Gbps.
  • the bandwidth growth required by mainstream applications does not exhibit such a 10-fold growth feature, such as 50 Gbps, 75 Gbps, 200 Gbps, and the like.
  • the industry wants to provide support for Ethernet ports (virtual connections) for bandwidths such as 50Gbps, 60Gbps, 75Gbps, 200Gbps and 150Gbps.
  • flexible bandwidth ports which can use one or several Ethernet physical interfaces together, for example, two 40GE ports and two 10GE ports use one 100G physical interface together; Flexible rate adjustments are made to changes in demand, such as from 200 Gbps to 330 Gbps, or 50 Gbps to 20 Gbps to increase port efficiency or extend its lifecycle.
  • Flexible rate adjustments are made to changes in demand, such as from 200 Gbps to 330 Gbps, or 50 Gbps to 20 Gbps to increase port efficiency or extend its lifecycle.
  • they can be bundled in cascade to support stacking of logical port rates (for example, bundling two 100GE physical interface stacks to support 200GE logical ports).
  • the bandwidth resources obtained by the flexible stacking of the physical interfaces can be pooled, and the bandwidth is allocated to a specific Ethernet logical port according to the granularity (for example, 5G is a granularity), and several Ethernet virtual connection pairs are cascaded. Efficient sharing of physical link groups.
  • FlexE supports sub-rate, channelization, and inverse multiplexing for Ethernet services.
  • FlexE can support the transmission of 250G Ethernet traffic (MAC code stream) using 3 existing 100GE physical interfaces.
  • FlexE can support the transmission of 200G Ethernet services using two existing 100GE Physical Medium Dependent (PMD).
  • PMD Physical Medium Dependent
  • FlexE can support several logical ports to use one or more physical interfaces together, which can support multiplexing multiple low-rate Ethernet services into high-speed flexible Ethernet.
  • Ethernet is used as a service interface in the access network and the metropolitan area network
  • the FlexE technology of the service aggregation function based on the Ethernet technology can seamlessly connect with the Ethernet interface of the underlying service network.
  • the introduction of these FlexE sub-rate, channelization and inverse multiplexing functions greatly expands the application of Ethernet, enhances the flexibility of Ethernet applications, and makes Ethernet technology gradually penetrate into the transmission network.
  • FlexE provides a viable evolution path for the virtualization of Ethernet physical links.
  • Flexible Ethernet requires several virtual Ethernet data connections on a cascaded set of physical interfaces. For example, four 100GE physical interfaces are cascaded and support several logical ports. When the bandwidth of some logical ports is reduced, the bandwidth of the other logical ports is increased, and the total amount of bandwidth reduction is equal to the total amount of bandwidth increase. The bandwidth of several logical ports is flexibly adjusted and used together. 100GE physical interfaces.
  • FlexE constructs a fixed frame format for physical interface transmission and performs time division multiplexing (TDM) slot division.
  • TDM time division multiplexing
  • FlexE's TDM slot division granularity is 66 bits, which can correspond to a 64/66b coded block.
  • a FlexE frame consists of 8 lines, the first 66b block position of each line is the FlexE overhead area, and the overhead area is the payload area for slot division, with a granularity of 66 bits, corresponding to 20x1023 66-bit bearer space, 100GE interface
  • the bandwidth is divided into 20 time slots, and the bandwidth of each time slot is about 5 Gbps.
  • a plurality of physical interfaces may be bundled in cascade, and all time slots of the plurality of physical interfaces may be combined to carry one Ethernet logical port. For example, 10GE requires two time slots, 25GE requires 5 time slots, and so on.
  • the 66b coded block still visible in the logical port is transmitted in sequence, and each logical port corresponds to one MAC, and the corresponding Ethernet packet is transmitted.
  • the start of the message and the identification of the idle IDLE padding are the same as for the legacy Ethernet.
  • the packet device has M Ethernet ingress ports (Ethernet ingress port 1, Ethernet in port 2, ..., Ethernet ingress port M), and each Ethernet in port corresponds to its own packet.
  • the data unit forwards the decision module.
  • the M Ethernet ingress ports correspond to M packet data unit forwarding decision modules (packet data unit forwarding decision module 1, packet data unit forwarding decision module 2, ..., packet data unit forwarding decision module M).
  • the packet device has N Ethernet egress ports (Ethernet egress port 1, Ethernet egress port 2, ..., Ethernet egress port N), and each Ethernet egress port corresponds to a respective packet data unit queuing buffer module.
  • the N Ethernet egress ports correspond to N packet data unit queuing buffer modules (packet data unit queuing buffer module 1, packet data unit queuing buffer module 2, ..., packet data unit queuing buffer module N).
  • Ethernet ingress port in Figure 2 is a logical concept.
  • an Ethernet ingress port can correspond to one or more physical interfaces because no physical interface is divided into time slots.
  • an Ethernet ingress port can correspond to one or more physical interfaces.
  • an Ethernet ingress port can correspond to one or more time slots of one or more physical interfaces.
  • the packet data unit forwarding decision module of the corresponding Ethernet ingress port needs to identify each packet data unit MAC address, by looking up the table for the packet data unit. The destination MAC address is matched to obtain the Ethernet outgoing port. Then, the packet data unit is buffer-queued through the packet data unit queuing buffer module corresponding to the found Ethernet egress port, and waits for the output from the Ethernet egress port to be sent.
  • Table lookup and data buffering can consume huge hardware resources, making packet devices costly and limited in scale. Moreover, the uncertainty of data buffering and table lookup can lead to high latency of uncertainty, making it difficult for packet devices to adapt to some delay-sensitive applications.
  • the embodiment of the present application provides a method for forwarding data, including: acquiring a first data unit sequence stream by using a first logical ingress port, where the first data unit sequence stream includes at least one first data unit; Determining, by the pre-configured mapping relationship between the at least one logical ingress port and the at least one logical egress port, a first logical egress port corresponding to the first logical ingress port, where the at least one logical ingress port includes the first logical ingress port Adjusting the number of idle cells in the first data unit sequence stream such that the rate of the adjusted first data unit sequence stream matches the rate of the first logical out port; sending through the first logical out port The adjusted sequence of first data unit streams.
  • the first logical ingress port corresponds to at least one physical inbound interface or at least one physical inbound interface
  • the first logical egress port corresponds to at least one physical outbound interface or at least one physical outbound interface. Gap.
  • the division of the logical ingress port and/or the logical egress port may be divided according to the bandwidth required by the service. The specific division manner may refer to the existing standard, which is not limited in this embodiment of the present application.
  • the logical ingress port and the logical out port are logical ports.
  • FlexE divides the time slots of the physical interfaces of the Ethernet. For example, 100GE divides 20 time slots of 5G bandwidth, and several (for example, m) 100GEs can be cascaded into one FlexE group (FlexE Group). 20*m time slots. These time slots can be arbitrarily combined into several logical ports of different sizes, and the bandwidth of each logical port is an integer multiple of 5G bandwidth.
  • a logical port can correspond to a traditional Ethernet physical interface.
  • a logical port can also correspond to a traditional multiple Ethernet physical interface.
  • a logical port can also be composed of corresponding time slots, for example, a combination of at least one time slot of an Ethernet physical interface, or a combination of multiple time slots from multiple Ethernet physical interfaces.
  • FIG. 3 is a schematic diagram of a method of forwarding data according to an embodiment of the present application.
  • a plurality of logical ports are shown in FIG. 3.
  • the first logical ingress port corresponds to some slots of the FlexE inbound interface group 1 (at least one physical interface)
  • the first logical outgoing port corresponds to certain time slots of the FlexE outgoing interface group 2 (at least one physical interface).
  • the first logical ingress port receives the first data unit sequence stream and forwards directly to the first logical egress port without interpretation of the content.
  • Each FlexE inbound interface group in the figure may correspond to one or more logical ingress ports, and each FlexE outbound interface group may correspond to one or more logical outbound ports; each Ethernet inbound interface may correspond to one logical ingress port. Each Ethernet outbound interface can correspond to a logical outgoing port.
  • the figure shows only the case of the Ethernet interface and the FlexE interface group. The method of the embodiment of the present application can also be applied to scenarios including other types of interfaces.
  • the logical ingress port and the logical egress port except the first logical ingress port and the first logical egress port shown in FIG. 3 are similar to the forwarding process of the data unit sequence stream, and are not described herein again.
  • FIG. 3 the number of logical ingress ports and logical outbound ports shown in FIG. 3 is merely illustrative, and the method of the embodiment of the present application is adapted to the case where there is at least one logical in port and at least one logical out port.
  • the embodiment of the present application can support not only one-to-one data forwarding, but also multiple logical ingress ports corresponding to one logical egress port in the embodiment of the present application.
  • the total bandwidth of the multiple logical ingress ports is required to be equal to the bandwidth of the logical egress port, that is, the bandwidth of the downstream pipe is equal to the total bandwidth of the upstream pipe.
  • Multiple logical ingress ports corresponding to one logical egress port can be considered as aggregation of data.
  • one logical ingress port may correspond to multiple logical egress ports. At this time, the data unit sequence stream received by one logical in port is directly copied to the corresponding multiple logical output ports. That is, the method in the embodiment of the present application can support one-to-many (multicast) forwarding and many-to-one (aggregation) forwarding.
  • the mapping relationship between the at least one logical ingress port and the at least one logical egress port comprises at least one of the following mapping relationships: one of the at least one logical ingress port and the at least one logical egress port a one-to-one mapping relationship of one of the logical out ports; a one-to-many mapping relationship between one of the at least one logical in port and the plurality of logical out ports of the at least one logical out port; A many-to-one mapping relationship between a plurality of logical ingress ports and at least one logical out port of the at least one logical ingress port.
  • the physical interfaces corresponding to the at least two logical ingress ports respectively are an optical transport network OTN interface, and a flexible optical transport network FlexOTN interface.
  • a logical port is provided based on a plurality of network physical interfaces, the logical port is independent of the specific form of the physical interface; secondly, it is independent of the protocol type of the data unit being forwarded, and the data may be various protocols, and does not need to be The fields in the data unit are parsed for a specific protocol.
  • the type of the physical interface corresponding to the first logical ingress port and the type of the physical interface corresponding to the first logical egress port may be the same or different, which is not limited in this embodiment of the present application.
  • each of the at least one logical in port and the to The physical interface corresponding to each logical out port of one logical out port is the following types of interfaces: optical transport network OTN interface, flexible optical transport network FlexOTN interface, Ethernet interface, flexible Ethernet FlexE interface, universal public wireless interface CPRI Synchronous digital system SDH interface, Fibre Channel FC interface or unlimited bandwidth InfiniBand interface.
  • the interface types of the multiple physical interfaces may be the same, but the embodiment of the present application is This is not limited.
  • the forwarding device receives the data unit sequence stream through the logical ingress port.
  • the first data unit sequence stream includes at least one first data unit.
  • the first data unit can also be understood as a service data unit or message.
  • the at least one first data unit may comprise at least one of the following data units: an OTN data unit, a FlexOTN data unit, an Ethernet packet data unit, a FlexE packet data unit, a CPRI data unit, a synchronous digital hierarchy SDH data unit, an FC Data unit and InfiniBand data unit.
  • the first data unit may include padding or may not include padding, and whether padding is included is related to the type of the first data unit.
  • the stream of data unit sequences received from different interface types and from different networks may include at least one free unit in addition to the data unit.
  • the data unit sequence stream and the data units it includes and the free units that may be included are described in detail below by way of example.
  • the data unit sequence stream received through the Ethernet interface, the FlexE interface, the FC interface, and the InfiniBand interface includes both data units and idle units.
  • the idle unit in the embodiment of the present application may also be referred to as idle information, such as Ethernet, and is not limited to the data format on the Media Independent Inteface (MII) after decoding.
  • MII Media Independent Inteface
  • the first data unit sequence stream may be a stream of encoded data unit sequences. That is, at least one first data unit in the first data unit sequence stream may be an encoded data unit. Further, since the data unit sequence stream includes both the data unit and the idle unit, the at least one data unit and the accompanying free unit included in the data unit sequence stream may be encoded.
  • the encoding here may be 64/66B encoding, 8/10B encoding, 512/513B encoding or 512/514B encoding. Among them, one symbol of 64/66B code corresponds to 8 bytes of original data, and one symbol of 8/10B code corresponds to 1 byte of original data.
  • the first data unit in the first data unit sequence stream received through the Ethernet interface may include 64/66B starting at 0x33 or 0x78 with 0b10 as the synchronization header.
  • the control code block, the 64/66B data code block with 0b01 as the synchronization header, and the type with 0b10 as the synchronization header are 0x87, 0x99, 0xAA, 0xB4, 0xCC, 0xD2, 0xA1 or 0xFF (in turn, the end character is in the 8-byte code).
  • the 64/66B end control code block at positions 1 to 8 in the block.
  • the 8/10B encoded data unit is similar to the 64/66B encoded data unit, and 1 byte is encoded as 10 bits.
  • the first data unit may include an 8/10B start control code block, a data code block, and 8/. 10B ends the control code block.
  • the first data unit sequence stream may include control information indicating the start, end, end of the data unit, or the presence and persistence of the idle unit.
  • At least one of the first data units in the first stream of data unit sequences may also be unencoded.
  • data units or idle units of the first data unit sequence stream may also be indicated within the chip or computer system in other manners such as pointers and memory addresses.
  • the sequence of data unit received through the logical port on the FlexE interface is similar to the sequence of data units received through the Ethernet interface (also a logical port), including packet data units under the Ethernet protocol and idle units under the Ethernet protocol. I will not repeat them here.
  • the data unit sequence stream of the FC received through the FC interface includes the FC data unit and the idle unit under the FC protocol.
  • the InfiniBand data unit sequence stream received through the InfiniBand interface includes InfiniBand packet data units and idle units under the InfiniBand network protocol.
  • FC and InfiniBand are packet network protocol technologies based on statistical multiplexing technology.
  • the data units of FC and InfiniBand are similar to the packet data units of Ethernet.
  • the free cells between the data units of the FC and InfiniBand are also similar to the free cells of the Ethernet.
  • the data unit sequence stream of the FC is taken as an example for detailed description.
  • the data unit in the data unit sequence stream of the FC is an FC frame, and the free unit is a Fill Word (4 bytes).
  • 4 bytes are one word (Word)
  • the length of the FC frame is an integer multiple of 4 bytes.
  • the FC data unit sequence stream generally requires at least 2 Fill Words or at least 6 service primitives between FC frames (at least 4 of which are Fill Words).
  • the FC frame that is not encoded has a structure as shown in FIG.
  • the FC frame usually starts with a 4-byte Start Of Frame (SOF), followed by the frame content, and ends with a 4-byte End Of Frame (EOF).
  • SOF Start Of Frame
  • EEF End Of Frame
  • the frame content portion includes a 24-byte frame header, a data field, and a 4-byte Cyclic Redundancy Check (CRC).
  • CRC Cyclic Redundancy Check
  • the frame content may further include an extended header.
  • the data segment is an integer multiple of 4 bytes, and is usually 0 to 2112 bytes.
  • the idle unit For a data unit sequence stream of a 64/66B encoded FC, the idle unit may be referred to as an idle code block, and the typical idle code block corresponds to two Fill Words, and the idle code block of the FC is consistent with the idle code block of the Ethernet.
  • FC service primitives including Fill Word, can be combined in 64/66B to obtain a code block sequence consistent with Ethernet 64/66B encoding. The situation is similar when using 8/10B encoding.
  • the data unit sequence stream received through the OTN interface, FlexOTN interface, CPRI or SDH interface only includes data units of the corresponding format, and does not include idle units.
  • the following is an example of a CPRI data unit.
  • the CPRI technology has a variety of different rate options, as follows:
  • CPRI line bit rate option 4 3072.0 Mbit/s, 8B/10B line coding (5 x 491.52 x 10/8 Mbit/s)
  • CPRI line bit rate option 7A 8110.08 Mbit/s, 64B/66B line coding (16 x 491.52 x 66/64 Mbit/s)
  • the basic frame is in bytes and has a fixed frame length.
  • CPRI basic frame of rate option 1 it includes a total of 16 words, 1 byte per word, the first word of 16 words is a control word, indicating the beginning of the basic frame, and the remaining 15 words are data word.
  • CPRI basic frames of rate option 2 it consists of a total of 16 words, 2 bytes per word.
  • the CPRI basic frame for rate option 7/7A includes a total of 16 words, 16 words per word. Therefore, the length of the basic frame is an integer of 8 bytes, which can be an integer number of 64/66B coded blocks.
  • the basic frames of 256 CPRIs constitute a CPRI superframe.
  • the first word of the CPRI superframe is the sync header control word, which can represent the beginning of the CPRI superframe.
  • the length of the selected rate option CPRI superframe is fixed so that the frame start, duration, and end of frame of the CPRI superframe can be determined.
  • the control word (synchronization word) of the first basic frame of the CPRI superframe The first 8 bytes and the next 8 bytes are respectively encoded as a sync header of 0b10, a 64/66B control code block of type 0xFF, and a 64/66B control code block of type 0b10 with a sync header of 0x78, which can implement CPRI.
  • the rest of the data is encoded as a data block with a sync header of 0b01. It can be seen that the data unit sequence stream of the CPRI interface is consistent with the format of the data unit of the Ethernet and the data unit of the FC described above.
  • the main difference between the CPRI data unit sequence stream and the Ethernet data unit sequence stream and the FC data unit sequence stream is that there is no idle code between the data units in the CPRI data unit sequence stream.
  • the OTN data unit is taken as an example for brief description.
  • the data unit of the OTN is an OTU-k frame, which is a fixed-size frame structure.
  • the 6-byte overhead FAS is a fixed sequence, similar to the preamble sequence in Ethernet.
  • the data unit of the OTN is identical to the data unit of the Ethernet, the data unit of the FC, and the data unit of the CPRI described above.
  • one data unit of the embodiment of the present application may correspond to one data frame, or may correspond to a larger number of data frames, and even an infinite number of data frames propagating on the logical port may be regarded as one data unit.
  • the data frame herein may refer to an FC frame, a CPRI superframe or an OTU-k frame in the foregoing.
  • Ethernet whether it is Ethernet, FlexE, FC, and InfiniBand, which are closer to the data unit in the form of a message, or a data unit closer to the frame format such as OTN, FlexOTN, CPRI, and SDH, all have similar formats.
  • the location of the start, end, and end of the data unit can be determined by various identifiers.
  • the protocol type of the data unit sequence stream received by the logical ingress port of the embodiment of the present application is not necessarily the same as the type of the physical interface corresponding to the logical in port.
  • the data unit of the data unit sequence stream received by the logical ingress port corresponding to the physical interface of the OTN may be an Ethernet protocol, which is only an example, and is not limited to the embodiment of the present application. .
  • the first logical egress port corresponding to the first logical ingress port that receives the first data unit sequence stream is determined by the mapping relationship between the pre-configured at least one logical ingress port and the at least one logical egress port.
  • the implementation of the mapping relationship between the at least one logical ingress port and the at least one logical egress port may be a configuration table or a device that is solidified into the forwarding device.
  • the mapping relationship may be modified or replaced by a network administrator, which is not limited in this embodiment of the present application.
  • mapping relationship can be stored and used in a network management computer system in the form of a table.
  • mapping relationship of the embodiment of the present application is different from the correspondence between the destination address (for example, the destination MAC address) and the outgoing port of the existing solution.
  • the mapping relationship in the embodiment of the present application directly includes the relationship between the logical ingress port and the logical out port, so there is no need to perform data unit integrity verification, such as CRC check, and the content of the data unit is not required to be interpreted, and the purpose is not required.
  • the lookup table processing of the address, the logical out port is exclusive with respect to the logical ingress port and is pre-configured, so the data unit in the stream of data unit sequences arriving from the logical in port does not need to look up, queue and cache one by one, directly from the logic
  • the outgoing port is sent.
  • the data received by the logical ingress port in the embodiment of the present application may be grouped and identified in other devices upstream of the forwarding device, or may be grouped together by other means. This is not limited.
  • FIG. 5 is a schematic diagram of a mapping relationship between a logical ingress port and a logical egress port according to an embodiment of the present application.
  • Figure 5 shows three physical interface groups, physical interface A, physical interface B, and physical interface C.
  • the type of the physical interface in the physical interface group can be the type mentioned in the foregoing.
  • the physical interface group B can be a standard Ethernet interface
  • the physical interface group A can be a FlexE interface group
  • the physical interface group C can be a FlexOTN interface group.
  • Logical ingress port A.1 and logical ingress port A.6 correspond to certain time slots of the physical interface group A. For details, see Table 2.
  • the logical outbound port B.1 corresponds to the entire physical interface group B.
  • the logical outgoing port C.2 corresponds to some time slots of the physical interface C group. For details, see Table 4. It is also possible to assign a data unit sequence stream identifier to each logical port in Tables 2 to 4 to distinguish the data unit sequence stream.
  • Table 5 shows the mapping between logical ingress ports and logical outbound ports.
  • the logical ingress port A.1 corresponds to the logical egress port C.
  • the logical ingress port A.6 corresponds to the logical outbound port B.1, which belongs to the method for forwarding data in the embodiment of the present application described above.
  • Table 5 also shows that the data unit sequence stream received by the logical ingress port A.2 not shown in FIG. 5 needs to be stored and forwarded by data unit table. The specific switching manner will be described in detail below.
  • the configuration table is simple and easy to maintain. It is usually configured by the NMS or automatically configured by the protocol.
  • the configuration table mainly includes the time slot of the interface group corresponding to the logical port and the logical port mapping relationship (Table 2 to Table 4); and the port-to-port mapping configuration without delay forwarding. (table 5).
  • Table 2 to Table 4 the logical port mapping relationship
  • table 5 the port-to-port mapping configuration without delay forwarding.
  • the above mapping relationship is short and concise, and can be considered as abstract tables, which may not actually exist in the form of a table. These mapping relationships are generally stored in the management system.
  • the data plane has been solidified into the hardware configuration of the device, which circumvents and reduces the maintenance of the large-scale lookup table and the lookup of the large-scale entry items by the forwarding device according to the protocol address and label. No table forwarding is implemented.
  • the mapping relationship between the pre-configured at least one logical ingress port and the at least one logical egress port may be updated according to the valid time period of the logical ingress port and the logical egress port, that is, when the logical ingress port and the logical out of the system
  • the corresponding device such as a controller
  • the logical port may be a unidirectional logical port or a bidirectional logical port
  • the first data unit sequence stream may be a unidirectional data unit sequence stream or a bidirectional data unit sequence stream. This example does not limit this.
  • a logical port is a combination of time slots combined by a set of (at least one) physical interfaces, related to the clock rate of the physical interface. Therefore, the rate of a logical port on a physical interface group is determined by the rate of its corresponding physical interface. When the clock of the physical interface is deviated, the logical port inherits the deviation.
  • Ethernet's asynchronous communication physical interface allows for clock frequency differences of plus or minus 100ppm (of which 1ppm is one in ten thousand) to reduce equipment requirements.
  • the physical interface of two nominal 10G bandwidths may be one ten thousandth greater than the nominal value, one less than one ten thousandth of the nominal value, respectively 10G*(1+0.0001) and 10G* (1-0.0001).
  • the actual clock rate between logical ports inherits the difference between the positive and negative 100 ppm clock frequencies of the physical interface.
  • the logical ingress port and the logical egress port are logical ports that are cascaded by five 5G slots, except for the flexible Ethernet division slot and the management slot. In extreme cases, the labels on two different physical interface groups.
  • the actual bandwidth of the same logical port is called 25G*(20460/20461)*(1+0.0001) and 25G*(20460/20461)*(1-0.0001). At this time, if data is forwarded through the logical ingress port and the logical out port, rate matching is required.
  • the rates of the logical ingress ports and their corresponding logical egress ports may be unequal, in other words, the transmission rate of the data unit sequence stream at the first logical ingress port and the data unit sequence stream are at the first logical egress port.
  • the transmission rates may be unequal.
  • the number of idle cells in the first data unit sequence stream is adjusted, so that the rate of the adjusted first data unit sequence stream matches the rate of the first logical out port.
  • the data unit sequence stream includes both a data unit and an idle unit as an example. Distinguishing the first data unit sequence stream received from the first logical ingress port, distinguishing the data unit from the idle unit, and performing necessary addition and deletion on the number of idle units to match the bandwidth difference of the logical out port to implement the data unit sequence stream The rate matches between the two logical ports.
  • all of the free cells in the first stream of data unit sequences may be deleted, and an appropriate number of free cells may be reinserted as needed at the first logical port.
  • the idle unit can also be inserted or deleted as needed in real time.
  • the data is always forwarded in the form of a stream, and the idle list The insertion or deletion of the meta is also done in real time with the stream.
  • the transmission rate of the first logical ingress port and the transmission rate of the first logical egress port are not significantly different, it is possible that the number of idle cells in the first data unit sequence stream at the first logical egress port is quite a period of time The number of free cells in the first data unit sequence stream at the first logical in port is equal.
  • the embodiment of the present application also allows to insert a free unit by cutting off consecutive data units.
  • the simple method is to insert a new type of idle unit at the cutoff; or use an existing idle unit (for example, idle byte or idle symbol), but insert the idle unit and the first data unit sequence stream at the cutoff
  • the types of free cells in are not the same. In this way, the receiving end can judge by the type of the idle unit that it is a continuation of the previous data unit, not a new data unit.
  • the same free unit can be used instead of the free unit that appears after the end of the previous packet and before the start of the next packet.
  • FIG. 6 is a schematic diagram of rate matching by adjusting the number of idle cells according to an embodiment of the present application.
  • the data unit sequence stream includes an idle cell group n-1, a packet data unit n-1, an idle cell group n, a packet data unit n, The idle cell group n+1 and the packet data unit n+1. Since the rate of its corresponding logical ingress port is less than the rate of the logical out port, the number of free cells in the idle cell group n is increased when rate matching is performed in (B). (C) in FIG.
  • 6 is a received stream of data unit sequences including an idle data unit n-1, a packet data unit n-1, an idle unit group n, a packet data unit n, an idle unit group n+1, and a packet.
  • Data unit n+1 Since the rate of its corresponding logical ingress port is smaller than the rate of the logical out port, and the difference in rate is large, when rate matching is performed in (D), the continuous packet data unit n is cut off and the idle unit is inserted.
  • the cache depth is only 1500 * 0.0002; even 9.6k long frame, the cache depth requirement is less than 2 bytes. Compared to the data width of more than 4 bytes used by 10GE and 100GE, such cache requirements are negligible. Therefore, the method for forwarding packet data in the embodiment of the present application may be referred to as delay-free efficient forwarding.
  • FIG. 7 is a schematic diagram of adjusting an idle unit in several embodiments of the present application.
  • (A) to (C) in Fig. 7 show an Ethernet system based on an 8/10B code block.
  • (D) to (F) in Fig. 7 show an Ethernet system based on a 64/66B code block.
  • the functions corresponding to the first functional area are physical interface technology and time slot division, including ingress port receiving data and descrambling code (corresponding to 64/ only).
  • the function corresponding to the first function area as a whole corresponds to acquiring the first data unit sequence stream through the first logical in port as described in the foregoing; the function corresponding to the second function area
  • the method mainly includes adjusting an idle unit (addition or deletion of idle bytes or idle symbols), and the function corresponding to the second functional area as a whole corresponds to adjusting the idle unit in the first data unit sequence stream described in the foregoing.
  • the number of the adjusted first data unit sequence stream is matched with the rate of the first logical out port; the function corresponding to the third functional area is logic Serial port distinguishing technology, including logical port matching interface time slot, scrambling code (corresponding to 64/66B code block system only) and outgoing port sending data, etc., the function corresponding to the third functional area corresponds to the above-mentioned pass through
  • the first logical output port sends the adjusted first data unit sequence stream.
  • the mapping relationship is usually solidified to the hardware configuration of the device. Therefore, the mapping between the plurality of logical ingress ports and the plurality of logical egress ports is not implemented in the example, and the first logical output corresponding to the first logical ingress port is determined. Port this process.
  • the adjustment idle unit may be performed without decoding and re-encoding after receiving the original data unit sequence stream, and adjusting the idle unit to increase or delete the idle symbol, for example, (A) and (D in FIG. 7) ). Adjusting the idle unit may also be performed in the case of decoding and re-encoding the received data unit sequence stream. At this time, the idle unit is adjusted to be an addition or deletion of the idle byte, for example, (B) and (C) in FIG. (E) and (F). Among them, (B) and (E) decoding and re-encoding in FIG. 7 are performed on the physical interface; (C) and (F) decoding and re-encoding in FIG. 7 are performed on the logical port.
  • the step may include: Decoding the first data unit sequence stream; adjusting the number of idle bytes in the decoded first data unit sequence stream, so that the adjusted rate of the first data unit sequence stream matches the rate of the first logical out port; Encoding the adjusted first data unit sequence stream; the sending, by the first logical egress port, the adjusted first data unit sequence stream, including: transmitting, adjusting, and encoding by using the first logical egress port The first sequence of data units after the stream.
  • the method may include: the first data unit sequence stream is an encoded data unit sequence stream, and the adjusting the first data
  • the number of idle cells in the unit sequence stream includes: adjusting the number of encoded idle symbols in the first data unit sequence stream, such that the adjusted first data unit sequence stream rate and the first logic out The rate of the port matches.
  • FIG. 8 is a schematic diagram of a manner of performing rate matching according to an embodiment of the present application.
  • the rate of the data unit sequence stream and the logical out port can be implemented by using the GFP protocol. match.
  • the GFP protocol defines an idle frame. The effect is like the idle byte of the Ethernet. Therefore, the original free unit of the data unit sequence stream of the Ethernet protocol (for example, it can be a free byte) can be deleted first, and the GFP protocol is used for the packet data unit. Perform encapsulation processing and insert GFP for idle rate adaptation.
  • the bandwidth allocated for the logical port in the embodiment of the present application should be sufficient to support the bandwidth of the data unit sequence stream after the packet data unit is encapsulated by using the GFP protocol.
  • the data units of FC and InfiniBand are similar to the packet data units of Ethernet.
  • the free cells between the data units of the FC and InfiniBand are also similar to the free cells of the Ethernet. Therefore, the method of adapting the rate of the data unit sequence stream of the FC and InfiniBand to the rate of the logical outbound port is similar to the method of adapting the rate of the stream of the data unit sequence of the Ethernet, and details are not described herein.
  • the physical interfaces of traditional third-party protocols such as SDH and OTN also have slot division and logical port support capabilities.
  • SDH time slot
  • OTN Optical (Channel) Payload Unit
  • rate matching can be implemented by using an emerging Generic Framing Procedure (GFP), or an Idle insert/delete based Mapping Procedure (IMP) for Ethernet services.
  • GFP Generic Framing Procedure
  • IMP Idle insert/delete based Mapping Procedure
  • the existing SDH, OTN, FlexOTN and other physical interface technologies, original investment and R&D investment, chips, optical modules and other resources, especially the resources involved in long-distance optical transmission can be used.
  • the CPRI interface protocol basic frame is in bytes and has a fixed frame length.
  • the physical interface typically also uses 8/10B encoding or 64/66B encoding.
  • Other types of services such as interface technology of CBR services such as SDH/OTN, can also adopt a CPRI-like method to perform 64/66B encoding on the corresponding data frame structure unit sequence. Therefore, under these protocols, the data frame is the data unit. Idle bytes or 8/10B encoded idle symbols or 64/66B encoded idle symbols can be inserted between frames (data units).
  • These data unit sequence streams can be supported on forwarding devices based on interface technologies such as Ethernet or FlexE.
  • the data unit of CPRI is a CPRI superframe, similar to the packet data unit of Ethernet, and the position of frame start, duration and end of frame can be marked in a corresponding way. Therefore, similar to the data unit sequence stream of Ethernet, rate matching can also be performed by adjusting the idle cells of the CPRI data unit sequence stream.
  • the idle unit of the stream of the data unit sequence of the CPRI is adjusted to mainly increase the idle unit. That is, a sequence of CPRI data unit sequences without idle originals is received from a native CPRI interface or port, and is added to a non-native interface or port by adding an idle unit, such as a flexible Ethernet port.
  • Figure 9 shows a schematic diagram of rate matching of a data unit sequence stream of a CPRI.
  • a of Fig. 9 shows two data units of a data unit sequence stream of CPRI when rate matching is not performed, the data unit includes a start portion and an end portion indicating the data unit, and the remaining portion is the data portion D.
  • the idle code block of the Ethernet is inserted into the encoded data unit of the CPRI (as shown in C of FIG. 9 , the data portion after encoding is encoded as a symbol, the beginning part)
  • the good, the end part and the idle are both encoded as control symbols) or equivalently, after the uncoded data unit is inserted into the idle (as shown in B of FIG.
  • the encoded rate is 10.1376G, which is less than 10.3125G of 10GE network, or less than FlexE.
  • the data unit sequence stream can be transmitted on a 10GE physical interface or a logical port corresponding to two FlexE 5G time slots.
  • the position of the IDLE insertion may be selected between the end code block and the start code block, and may also be placed in the middle of the data, which is not limited in this embodiment of the present application.
  • the uncoded rate of each option in the CPRI interface is n ⁇ 491.528M.
  • n is equal to 10
  • it can match the current FlexE 5G time slot and have enough bandwidth remaining.
  • option 8 and option 10 in CPRI technology is close to the bandwidth of FlexE's 2 ⁇ 5G time slot and 5 ⁇ 5G time slot and there is enough bandwidth remaining, together with the actual 10GE and 25GE Ethernet.
  • the bandwidth of the physical interface is close and there is enough bandwidth left.
  • the total bandwidth of the data unit sequence stream is less than or equal to the bandwidth of the logical port, even if the physical interface and the logical port have a clock frequency difference of plus or minus 100 ppm (of which 1 ppm is one ten thousandth), it can be realized by appropriately adjusting the idle time. Rate matching.
  • the first byte and the last byte of the FAS overhead in the OTU-k frame of the OTN can be replaced with /T/, respectively.
  • /S/ characters then insert idle bytes in the OTN data unit sequence stream (uncoded), or insert idle symbols in the OTN data unit sequence stream (encoded) to complete rate matching, and
  • the rate matched data unit sequence stream can be sent out from the logical outbound interface of the Ethernet protocol.
  • the adjusting the number of idle cells in the first data unit sequence stream may include: increasing or decreasing the first data unit when the first data unit sequence stream includes an idle unit. The number of idle cells in the sequence stream; when the first data unit sequence stream does not include an idle cell, increasing the number of free cells in the first data unit sequence stream.
  • the total bandwidth of the at least one first data unit in the first data unit sequence stream is less than or equal to a saturation bandwidth of the first logical in port, and is less than or equal to the The saturation bandwidth of the first logical out port.
  • the forwarding device does not distinguish between the service, the protocol, and the like.
  • the method for rate matching the data unit sequence stream under various protocols may adopt various existing solutions, and is not limited to the method described in the foregoing.
  • the method for forwarding data in the embodiment of the present application forwards the data unit sequence stream through a direct mapping relationship between logical ports, and adjusts the rate matching between the data unit sequence stream and the downstream outbound port by adjusting the number of idle units, thereby effectively reducing the forwarding device.
  • the forwarding pressure can effectively improve the service throughput of the forwarding device, and can reduce the forwarding delay of data, and can be adapted to delay-sensitive large-bandwidth services.
  • FIG. 10 is a schematic diagram of a method for forwarding packet data according to another embodiment of the present application.
  • the forwarding device may further receive the second data unit sequence stream through the second logical ingress interface (for example, the interface A.2 mentioned above), by using the existing method for forwarding data introduced in FIG. Data exchange is performed on the second data unit sequence stream.
  • the plurality of packet data units of the second data unit sequence stream received by the Ethernet inbound interface 4 are forwarded by the packet data unit corresponding to the Ethernet inbound interface 4 to the decision module 4, respectively, in the packet data unit queuing buffer module 5 and the packet data unit.
  • the queuing buffer in the queuing buffer module 6 is sent from the Ethernet outbound interface 5 and the Ethernet outbound interface 6.
  • a plurality of packet data units of the second data unit sequence stream received by a second logical in port on the FlexE inbound interface group 3 are forwarded by the packet data unit to the decision module 3, respectively, in the packet data unit queuing buffer module 5 and the packet.
  • the data unit queue buffer module 6 queues buffers and transmits them from the Ethernet outbound interface 5 and the Ethernet outbound interface 6.
  • the embodiment of the present application further includes a method for determining that a plurality of packet data units in the data unit sequence stream are not forwarded, and directly entering the corresponding packet data unit queuing buffer module for buffer queuing. For example, a plurality of packet data units of the data unit sequence stream received by the last logical ingress port on the FlexE inbound interface group 1 are directly sent to the packet data unit queuing buffer module 5 for queuing buffering without being determined by the packet data unit forwarding decision module. , sent from the Ethernet outbound interface 5.
  • the method for forwarding data of the present application may further include: acquiring, by the second logical ingress port, a second data unit sequence stream, where the second data unit sequence stream includes at least one second data unit, the at least one Each of the second data units in the second data unit includes forwarding decision reference information, and determining, according to the forwarding decision reference information, a second logical output corresponding to each of the at least one second data unit Storing each of the second data units in a buffer queue of the corresponding second logical egress port; transmitting, by the second logical egress port, the second data unit in the second data unit sequence stream .
  • the forwarding decision reference information may include a destination address, a forwarding label, and the like.
  • FIG. 11 is a schematic block diagram of an apparatus 1100 for forwarding data according to an embodiment of the present application.
  • the device includes a first logical ingress port 1110, a first logical egress port 1120, a mapping relationship control module 1130, and a rate matching module 1140.
  • the first logical ingress port 1110 is configured to obtain a first data unit sequence stream, where the first data unit sequence stream includes at least one first data unit, and the mapping relationship control module 1130 is configured to be configured according to the pre-configured Determining, by the mapping relationship between the at least one logical ingress port and the at least one logical egress port, the first logical ingress port 1120 corresponding to the first logical ingress port 1110, the at least one logical ingress port including the first logical ingress port 1110;
  • the rate matching module 1140 is configured to adjust the number of idle cells in the first data unit sequence stream, so that the rate of the adjusted first data unit sequence stream matches the rate of the first logical out port 1120.
  • the first logical output port 1120 is configured to send the adjusted first data unit sequence stream.
  • the mapping relationship includes software configuration and hardware configuration that is solidified in the device.
  • the software configuration mapping relationship may describe the correspondence between the logical ingress port and the logical egress port through the configuration table described in the foregoing. These mapping relationships are typically stored in a management system and can be stored and used in a network management computer system in the form of a table.
  • the hardware configuration mapping relationship may be a cross-switched connection relationship of the cross-switching devices that are solidified in the device. For example, a cross-connection relationship based on a Crossbar-based space division (S) cross device, or a sequential write configuration readout relationship based on a time slot storage time division (T) switching device, and a configuration sequence write order read relationship; or a combination
  • S Crossbar-based space division
  • T time slot storage time division
  • T time division
  • the form is a cross-switch connection relationship of TST, STS three-level cross device, and so on.
  • the currently available mapping relationship may be a switch connection relationship of a cell-based Fabric and Fabric Interface Chip (FAB & FIC), or a switched connection of a single-chip switching network based on shared memory. Relationships, etc., to achieve efficient table-free forwarding.
  • FAB & FIC cell-based Fabric and Fabric Interface Chip
  • the rate matching module 1140 and the cross-switching function that solidifies the mapping relationship may be integrated. For example, in a shared memory-based switching network device, the data is written according to the first input logical port rate. When more data is written, the appropriate Delete idle data that has not been written or written to shared memory, or write free data at all, only write data units; according to the first logical output port 1110, continuously read and send data from the shared memory, when When the data buffered in the buffer is insufficient to be output to the first logical out port 1120, an idle unit is inserted in the data unit sequence stream to complete rate matching.
  • the specific implementation form of the rate matching module 1140 and the mapping relationship is not limited in this embodiment of the present application.
  • the mapping relationship between the at least one logical ingress port and the at least one logical egress port includes at least one of the following mapping relationships: one of the at least one logical ingress port and the logical ingress port a one-to-one mapping relationship of one of the at least one logical out port; one of the at least one logical in port and one of the plurality of logical out ports of the logical out port a mapping relationship; and a many-to-one mapping relationship between the logical ingress ports of the at least one logical ingress port and the logical out port of the at least one logical egress port.
  • a physical interface corresponding to each of the logical ingress port and each of the at least one logical egress port is an interface of the following type: optical transmission Network OTN interface, flexible optical transport network FlexOTN interface, Ethernet interface, flexible Ethernet FlexE interface, universal public wireless interface CPRI, synchronous digital system SDH interface, Fibre Channel FC interface and unlimited bandwidth InfiniBand interface.
  • the at least one first data unit comprises at least one of the following data units: an OTN data unit, a FlexOTN data unit, an Ethernet packet data unit, a FlexE packet data unit, a CPRI data unit, Synchronous digital system SDH data unit, FC data unit and InfiniBand data unit.
  • a total bandwidth of the at least one first data unit in the first data unit sequence stream is less than or equal to a saturation bandwidth of the first logical in port, and is less than or equal to the First logic The saturated bandwidth of the port.
  • the first data unit sequence stream is an encoded data unit sequence stream
  • the rate matching module 1140 is specifically configured to: decode the first data unit sequence stream; adjust decoding The number of idle bytes in the sequence of the first data unit sequence is such that the rate of the adjusted first data unit sequence stream matches the rate of the first logical out port; and the adjusted first data unit sequence stream is performed
  • the first logical output port 1120 is specifically configured to: send the adjusted and encoded first data unit sequence stream.
  • the first data unit sequence stream is an encoded data unit sequence stream
  • the rate matching module 1140 is specifically configured to: adjust the coded idle in the first data unit sequence stream.
  • the number of symbols is such that the rate of the adjusted first data unit sequence stream matches the rate of the first logical out port.
  • the device further includes a second logical ingress port, a second logical egress port, a data unit forwarding decision module, and a data unit queuing buffer module, where the second logical ingress port is configured to obtain the first a second data unit sequence stream, wherein the second data unit sequence stream includes at least one second data unit, and each of the at least one second data unit includes forwarding decision reference information in each of the at least one second data unit; a forwarding decision module, configured to determine, according to the forwarding decision reference information, a second logical output port corresponding to each of the at least one second data unit sequence stream; the data unit queuing buffer module, Cache each of the second data units in a buffer queue of the corresponding second logical egress port; the second logical egress port is configured to send the second data in the second data unit sequence stream unit.
  • the forwarding decision reference information may include a destination address or a forwarding label, and the like.
  • the rate matching module 1140 is specifically configured to: when the first data unit sequence stream includes an idle unit, increase or decrease an idle unit in the first data unit sequence stream. A quantity; when the idle unit is not included in the first data unit sequence stream, increasing the number of idle units in the first data unit sequence stream.
  • the first data unit sequence stream further includes at least one idle unit.
  • the size of the sequence numbers of the foregoing processes does not mean the order of execution sequence, and the order of execution of each process should be determined by its function and internal logic, and should not be applied to the embodiment of the present application.
  • the implementation process constitutes any limitation.
  • the disclosed systems, devices, and methods may be implemented in other manners.
  • the device embodiments described above are merely illustrative, for example, the single The division of elements is only a logical function division. In actual implementation, there may be another division manner. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the functions may be stored in a computer readable storage medium if implemented in the form of a software functional unit and sold or used as a standalone product.
  • the technical solution of the present application which is essential or contributes to the prior art, or a part of the technical solution, may be embodied in the form of a software product, which is stored in a storage medium, including
  • the instructions are used to cause a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present application.
  • the foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like, which can store program codes. .

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Abstract

本申请公开了一种转发数据的方法和设备，该方法包括通过第一逻辑入端口获取第一数据单元序列流，所述第一数据单元序列流中包括至少一个第一数据单元；根据预配置的至少一个逻辑入端口和至少一个逻辑出端口的映射关系，确定所述第一逻辑入端口对应的第一逻辑出端口，所述至少一个逻辑入端口包括所述第一逻辑入端口；调整所述第一数据单元序列流中的空闲单元的数量，使得调整后的第一数据单元序列流的速率与所述第一逻辑出端口的速率匹配；通过所述第一逻辑出端口发送所述调整后的第一数据单元序列流。本申请的方法可以有效降低转发设备的转发压力，有效提高转发设备的业务吞吐能力，并能降低数据的转发时延，能够适应于对延迟敏感的大带宽业务。

Description

转发数据的方法和设备
本申请要求于2016年5月27日提交中国专利局、申请号为201610368270.7、发明名称为“转发数据的方法和设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及通信领域，并且更具体地，涉及一种转发数据的方法和设备。
背景技术
现有的各种网络系统中，分组数据的转发一般通过分组设备(或称为转发设备)对分组数据单元逐包进行。具体地，分组设备基于分组数据单元(或者称为报文)内包含的目的地址和标签等信息进行查表，确定对该分组数据的转发行为。例如，以太网中的分组设备以太网交换机基于目的介质访问控制(Medium Access Control，MAC)地址查表确定出端口。又如，多协议标签交换(Multi-Protocol Label Switching，MPLS)根据MPLS报文标签确定对报文的处理和转发行为。光纤通道(Fibre Channel，FC)交换机、无限带宽(InfiniBand)交换机、网际互连协议(Internet Protocol，IP)路由器等也有类似的分组数据的转发机制。各种网络系统中查找表的大小、规模、不一，查表的耗时、难度不一。
具体而言，以以太网为例，最简单的以太网的交换遵从802.1d标准，需要对经过CRC校验后符合完整性要求的报文中的源MAC地址和目的MAC地址进行识别。一方面通过对源MAC地址进行学习，维护一张学习得到的目的MAC地址与出端口(即转发目的端口)的对应关系的查找表。另一方面，以该查找表为依据，对所有入端口上到达的报文的目的MAC地址进行查表匹配，获得出端口。然后进行对应的出端口的报文数据单元缓存队列排队，等待从出端口被发送输出。此外，以太网802.1q标准还进一步引入了更多的标签用于区分不同的业务和流，也引入了其他的方式进行转发决策查找表的维护，以支持更灵活的转发决策，但机制不变。Fibre Channel交换机、InfiniBand交换机、IP路由器等，大体情况类似。这种逐包识别目的地址、标签等转发决策信息并进行分组数据单元转发的机制使得整个分组数据的转发时延较大。
并且，作为统计复用特性的基础特征，从各个入端口到达的报文又具有突发性和不确定性。当从不同入端口先后或者同时到达的多个报文都要从某一出端口发送，超过了出端口的服务能力的时候，势必要进行缓冲和排队。而当从各个入端口到达的报文中要从某一出端口发送的报文比较少，远低于该出端口的服务能力的时候，出端口存在空闲或者传输空闲填充信息的情况，造成出端口服务能力和出端口带宽的浪费。为了使得出端口的服务能力和带宽利用率达到一定的比例，例如95％。最有效的措施是维持每个出端口一定的被服务分组缓冲排队长度。因此现有的分组设备对分组数据的交换一般又描述为存储转发。
随着分组设备的端口数量的增长、端口带宽的增长和分组设备容量的增长，以及系统对转发时延的要求的日益提高。查表和数据缓冲存储会耗费巨大的硬件资源，使得分 组设备成本高，规模受限。并且，数据的不确定性缓冲存储以及查表会导致不确定性的高延迟，使得分组设备难以适应一些延迟敏感的应用。
发明内容
本申请提供一种转发数据的方法和设备，可以提高业务吞吐能力，降低数据的转发时延。
第一方面，本申请提供一种转发数据的方法，包括：通过第一逻辑入端口获取第一数据单元序列流，所述第一数据单元序列流中包括至少一个第一数据单元；根据预配置的至少一个逻辑入端口和至少一个逻辑出端口的映射关系，确定所述第一逻辑入端口对应的第一逻辑出端口，所述至少一个逻辑入端口包括所述第一逻辑入端口；调整所述第一数据单元序列流中的空闲单元的数量，使得调整后的第一数据单元序列流的速率与所述第一逻辑出端口的速率匹配；通过所述第一逻辑出端口发送所述调整后的第一数据单元序列流。
其中，所述第一逻辑入端口可以对应至少一个物理入接口或至少一个物理入接口的至少一个时隙，所述第一逻辑出端口可以对应至少一个物理出接口或至少一个物理出接口的至少一个时隙。
其中，第一数据单元序列流还可以包括至少一个空闲单元。
本申请的转发数据的方法和设备可以基于多种网络技术和协议。首先，基于多种网络物理接口提供逻辑端口，逻辑端口是与物理接口的具体形式无关的；其次，是与被转发的数据单元的协议类型无关的，数据可以是各种协议的，不需要对数据单元中的字段对应具体协议进行解析。
在本申请的方法通过逻辑端口间的直接的映射关系转发数据单元序列流，并通过调整空闲单元的数量实现数据单元序列流与下游出端口的速率匹配，可以有效降低转发设备的转发压力，有效提高转发设备的业务吞吐能力，并能降低数据的转发时延，能够适应于对延迟敏感的大带宽业务。
其中，所述至少一个逻辑入端口和至少一个逻辑出端口的映射关系可以包括以下映射关系中的至少一种：所述至少一个逻辑入端口中的一个逻辑入端口和所述至少一个逻辑出端口中的一个逻辑出端口的一对一的映射关系；所述至少一个逻辑入端口中的一个逻辑入端口和至少一个逻辑出端口中多个逻辑出端口的一对多的映射关系；和所述至少一个逻辑入端口中的多个逻辑入端口和至少一个逻辑出端口中一个逻辑出端口的多对一的映射关系。由此，逻辑入端口和逻辑出端口可以形成一对一、一对多、多对一和多对多的映射关系。
在第一方面的一种可能的实现方式中，所述至少一个逻辑入端口中的每个逻辑入端口和所述至少一个逻辑出端口中的每个逻辑出端口对应的物理接口为以下类型的接口：光传送网OTN接口、灵活光传送网FlexOTN接口、以太网接口、灵活以太网FlexE接口、通用公共无线接口CPRI、同步数字体系SDH接口、光纤通道FC接口或无限带宽InfiniBand接口。
在第一方面的一种可能的实现方式中，所述至少一个第一数据单元包括以下数据单元中的至少一种：OTN数据单元、FlexOTN数据单元、以太网分组数据单元、FlexE分组数据单元、CPRI数据单元、同步数字体系SDH数据单元、FC数据单元和InfiniBand 数据单元。
在第一方面的一种可能的实现方式中，当至少一个逻辑入端口中包括至少两个逻辑入端口时，至少两个逻辑入端口分别对应的物理接口为光传送网OTN接口、灵活光传送网FlexOTN接口、以太网接口、灵活以太网FlexE接口、通用公共无线接口CPRI、同步数字体系SDH接口、光纤通道FC接口和无限带宽InfiniBand接口中的至少两种；和/或当至少一个逻辑出端口中包括至少两个逻辑出端口时，至少两个逻辑出端口分别对应的物理接口为光传送网OTN接口、灵活光传送网FlexOTN接口、以太网接口、灵活以太网FlexE接口、通用公共无线接口CPRI、同步数字体系SDH接口、光纤通道FC接口和无限带宽InfiniBand接口中的至少两种。
在第一方面的一种可能的实现方式中，所述调整所述第一数据单元序列流中的空闲单元的数量，包括：当所述第一数据单元序列流中包括空闲单元时，增加或减少所述第一数据单元序列流中的空闲单元的数量；当所述第一数据单元序列流中不包括空闲单元时，增加所述第一数据单元序列流中的空闲单元的数量。使得不论是所述第一逻辑入端口所接收的数据单元序列流中既包括第一数据单元又包括空闲单元的情况，还是所述第一逻辑入端口所接收的数据单元序列流中仅包括第一数据单元而不包括空闲单元的情况，都能够对第一逻辑入端口所接收的数据单元序列流进行速率匹配。
在第一方面的一种可能的实现方式中，所述第一数据单元序列流中的所述至少一个第一数据单元的总带宽小于或等于所述第一逻辑入端口的饱和带宽，且小于或等于所述第一逻辑出端口的饱和带宽。这种配置可以保证业务能够通过调整空闲单元与逻辑入端口和逻辑出端口的速率分别匹配。
在第一方面的一种可能的实现方式中，所述第一数据单元序列流为经过编码的数据单元序列流，所述调整所述第一数据单元序列流中的空闲单元的数量，包括：对所述第一数据单元序列流进行解码；调整解码后的第一数据单元序列流中空闲字节的数量，使得调整后的第一数据单元序列流的速率与所述第一逻辑出端口的速率匹配；对调整后的第一数据单元序列流进行编码；所述通过所述第一逻辑出端口发送所述调整后的第一数据单元序列流，包括：通过所述第一逻辑出端口发送调整且编码后的第一数据单元序列流。
其中，编码可以为64/66B编码、8/10B编码、512/513B编码或512/514B编码；相应地，解码可以为64/66B解码、8/10B解码、512/513B解码或512/514B解码。
在第一方面的一种可能的实现方式中，所述第一数据单元序列流为经过编码的数据单元序列流，所述调整所述第一数据单元序列流中的空闲单元的数量，包括：调整所述第一数据单元序列流中经过编码的空闲码元的数量，使得调整后的第一数据单元序列流的速率与所述第一逻辑出端口的速率匹配。
在第一方面的一种可能的实现方式中，所述方法还包括：通过第二逻辑入端口获取第二数据单元序列流，所述第二数据单元序列流中包括至少一个第二数据单元，所述至少一个第二数据单元中每一个第二数据单元中分别包括转发决策参考信息；根据所述转发决策参考信息，确定所述至少一个第二数据单元中每一个第二数据单元分别对应的第二逻辑出端口；将所述每一个第二数据单元缓存在对应的所述第二逻辑出端口的缓存队列中；通过所述第二逻辑出端口发送所述第二数据单元序列流中的第二数据单元。
其中，所述转发决策参考信息可以包括目的地址或转发标签等。
第二方面，本申请还提供了一种转发数据的设备，该设备包括第一逻辑入端口、第一逻辑出端口、映射关系控制模块和速率匹配模块，所述第一逻辑入端口，用于获取第一数据单元序列流，所述第一数据单元序列流中包括至少一个第一数据单元；所述映射关系控制模块，用于根据预配置的至少一个逻辑入端口和至少一个逻辑出端口的映射关系，确定所述第一逻辑入端口对应的第一逻辑出端口，所述至少一个逻辑入端口包括所述第一逻辑入端口；所述速率匹配模块，用于调整所述第一数据单元序列流中的空闲单元的数量，使得调整后的第一数据单元序列流的速率与所述第一逻辑出端口的速率匹配；所述第一逻辑出端口，用于发送所述调整后的第一数据单元序列流。相应的模块用于完成本申请的第一方面的转发数据的方法，此处不再赘述。
本申请中，预配置的多个逻辑入端口和多个逻辑出端口的映射关系可以按照逻辑入端口和逻辑出端口的有效时间段进行更新。
第一数据单元内可以包括填充，也可以不包括填充。
附图说明
图1是以太网分组数据单元序列流的结构的示意图。
图2是现有的分组数据转发流程的示意图。
图3是本申请一个实施例的转发数据的方法的示意图。
图4是FC帧的结构示意图。
图5是本申请一个实施例的逻辑入端口和逻辑出端口的映射关系的示意图。
图6是本申请一个实施例的通过调整空闲单元的数量来进行速率匹配的示意图。
图7是本申请几个实施例的调整空闲单元的示意图。
图8是本申请一个实施例的进行速率匹配的方式的示意图。
图9是本申请另一个实施例的进行速率匹配的方式的示意图。
图10是本申请另一个实施例的转发数据的方法示意图。
图11是本申请一个实施例的转发数据的设备的示意性框图。
具体实施方式
下面将结合附图，对本申请实施例中的技术方案进行描述。
在本说明书中使用的术语“部件”、“模块”、“系统”等用于表示计算机相关的实体、硬件、固件、硬件和软件的组合、软件、或执行中的软件。例如，部件可以是但不限于，在处理器上运行的进程、处理器、对象、可执行文件、执行线程、程序和/或计算机。通过图示，在计算设备上运行的应用和计算设备都可以是部件。一个或多个部件可驻留在进程和/或执行线程中，部件可位于一个计算机上和/或分布在2个或更多个计算机之间。此外，这些部件可从在上面存储有各种数据结构的各种计算机可读介质执行。部件可例如根据具有一个或多个数据分组(例如来自与本地系统、分布式系统和/或网络间的另一部件交互的二个部件的数据，例如通过信号与其它系统交互的互联网)的信号通过本地和/或远程进程来通信。
应理解，本申请实施例的技术方案可以应用于光传送网(Optical Transport Network，OTN)、灵活光传送网(Flexible OTN，FlexOTN)、以太网(Ethernet)、灵活以太网(Flexible Ethernet，FlexE)、通用公共无线接口(Common Public Radio Interface，CPRI) 网络、同步数字体系(Synchronous Digital Hierarchy，SDH)网络、FC网络和InfiniBand网络等，本申请实施例对此不作限定。
下面说明本申请所应用的网络中数据的结构。本申请各实施例中，具有实质内容的多个数据单元(不同网络的数据单元的形式可以不同)构成了数据单元序列流，数据单元序列流中可以包括空闲(IDLE)单元也可以不包括空闲单元。这里，空闲单元也可以根据网络的不同而具有不同的形式。例如，空闲单元可以为空闲码元或空闲字节，还可以为数据间隙(Inter-Packet Gap，IPG)。以以太网为例，数据单元为以太网分组数据单元，以太网分组数据单元与以太网分组数据单元之间可以插入的空闲单元，空闲单元可以为空闲码元或空闲字节。
具体地，图1是以太网的分组数据单元序列流的结构的示意图。随时间推移以太网的分组设备的端口(包括入端口和出端口)自左而右传输数据。在无以太网分组数据单元进行传输的时候，一直对空闲单元(通常是对空闲字节进行编码后形成的空闲码元)进行传输；有以太网分组数据单元进行传输的时候，则传输以太网分组数据单元(通常也是进行编码后)。图中为了简洁将以太网分组数据单元简化写作分组数据单元。
如图1所示，情况A是在某一段时间内以太网端口无以太网分组数据单元发送，其连续发送空闲单元，以维持以太网端口两侧的硬件的正常发送和接收状态。情况B是另一段时间内有以太网分组数据单元需要传输，则由以太网分组数据单元和空闲单元形成分组数据单元序列流发送。图中主要示出了分组数据单元n-1、分组数据单元n和分组数据单元n+1以及各分组数据单元之间的空闲单元。
以太网分组数据单元通常具有一定范围内的可变长度，对发送侧，两个以太网分组数据单元之间的空闲单元则通常包括至少12字节，长度不限。特别地，在一些特殊情况下，空闲单元对应的最小字节数要求可以变化。例如10吉比特以太网(10Gigabit Ethernet，10GE)的接收侧允许的最小帧间空闲单元的字节数为5；100吉比特以太网(100Gigabit Ethernet，100GE)的接收侧允许的最小帧间空闲单元的字节数为1。
以太网分组数据单元的典型封装如图1所示，以8位元组(或称为字节)为基本单位。一个以太网分组数据单元中首先包含前7字节的前导码“0x55 0x55 0x55 0x55 0x550x55 0x55”，1字节的帧开始定界字段sfd(Start-of-Frame Delimiter，SFD)“0xD5”。随后是6字节长度的目的MAC地址，6字节长度的源MAC地址，2字节长度的分组类型/长度信息，至少为46字节的一定长度的分组载荷信息及填充信息字节(载荷不足46字节的时候，用填充字节(Pad/Padding，PAD)填充至46字节)。最后是4字节的帧校验字节，例如循环冗余码(Cyclic Redundancy Code，CRC)校验，用于校验分组的完整性。以太网分组数据单元之后的空闲单元中的第一个字节，作为控制字节，具体为帧结束定界字段efd(End-of-Frame Delimiter，EFD)。
在以太网中，以太网端口通常作为面向数据的逻辑上的概念出现，称为逻辑端口或简称为端口，以太网物理接口则为硬件上的概念出现，称为物理接口或简称为接口。通常，用一个MAC地址标记一个以太网端口。传统地，以太网端口的速率的确定以以太网物理接口的速率为基础。一般情况下，一个以太网端口最大带宽对应一个以太网物理接口的带宽，例如10Mbps、100Mbps、1000Mbps(1Gbps)、10Gbps、40Gbps、100Gbps以及400Gbps等以太网物理接口。
以太网在过去的相当一段时间内获得了广泛的应用和长足的发展。以太网端口速率 以10倍提升，从10Mbps向100Mbps、1000Mbps(1Gbps)、10Gbps、40Gbps、100Gbps、400Gbps不断演进发展。技术越发展，带宽颗粒差异越大，越容易出现与实际应用需求期望的偏差。主流应用需求的带宽增长并不呈现这样的10倍增长特征，例如50Gbps、75Gbps、200Gbps等。业界希望提供对50Gbps、60Gbps、75Gbps、200Gbps和150Gbps等带宽的以太网端口(虚拟连接)的支持。
一方面，更进一步地，希望能够提供一些灵活带宽的端口，这些端口可以共同使用一个或者若干个以太网物理接口，例如2个40GE端口和2个10GE端口共同使用一个100G物理接口；并能够随着需求的变化做出灵活的速率调整，例如从200Gbps调整为330Gbps，或者50Gbps调整为20Gbps，以提高端口使用效率或者延长其使用生命周期。对于固定速率的物理链路，可以将其级联捆绑，以支持逻辑端口速率的堆叠增加(例如，将2个100GE物理接口堆叠级联捆绑以支持200GE逻辑端口)。另一方面，能够将物理接口灵活堆叠所得到的带宽资源池化，将其带宽按照颗粒(例如，5G为一个颗粒)分配给特定的以太网逻辑端口，实现若干以太网虚拟连接对堆叠级联的物理链路组的高效共享。
由此，灵活以太网(Flexible Ethernet，FlexE)的概念应运而生，灵活以太网又称为灵活虚拟以太网。FlexE支持针对以太网业务的子速率、通道化、反向复用等功能。例如，针对以太网业务的子速率应用场景，FlexE能够支持将250G的以太网业务(MAC码流)采用3路现有的100GE的物理接口进行传送。针对以太网业务的反向复用场景，FlexE能够支持将200G的以太网业务采用2路现有的100GE的物理媒质相关子层(Physical Medium Dependent，PMD)进行传送。针对以太网业务的通道化场景，FlexE能够支持若干个逻辑端口共同使用一个或者多个物理接口，能够支持将多路低速率的以太网业务复用到高速率的灵活以太网的中。
由于接入网和城域网中大量采用以太网作为业务接口，这种基于以太网技术的业务流量汇聚功能的FlexE技术能够实现和底层业务网络的以太网接口的无缝连接。这些FlexE的子速率、通道化和反向复用功能的引入，极大的扩展了以太网的应用场合，增强了以太网应用的灵活性，并使得以太网技术逐渐向传送网领域渗透。
FlexE为以太网物理链路的虚拟化，提供了一个可行的演进方向。灵活以太网需要在级联的一组物理接口上支持若干个虚拟的以太网数据连接。例如，4个100GE物理接口级联捆绑，支持若干逻辑端口。若干逻辑端口中一部分逻辑端口的带宽减小，则另外一部分逻辑端口的带宽增大，并且带宽减小的总量和带宽增大的总量相等，若干逻辑端口的带宽快速弹性调整，共同使用4个100GE物理接口。
FlexE借鉴SDH/OTN技术，对物理接口传输构建固定帧格式，并进行时分复用(Time Division Multiplexing，TDM)的时隙划分。与SDH/OTN不同的是，FlexE的TDM时隙划分粒度是66比特，正好可以对应承载一个64/66b编码块。一个FlexE帧包含8行，每行第一个66b块位置为FlexE开销区域，开销区域后为进行时隙划分的净荷区域，以66比特为粒度，对应20x1023个66比特承载空间，100GE接口的带宽划分20个时隙，每个时隙的带宽约为5Gbps。
若干个物理接口可以级联捆绑，该若干个物理接口的全部的时隙可以组合承载一个以太网逻辑端口。例如10GE需要两个时隙，25GE需要5个时隙等。逻辑端口上可见的仍为顺序传输的66b编码块，每个逻辑端口对应一个MAC，传输相应的以太网报文，对 报文的起始结束和对空闲IDLE填充的识别与传统以太网相同。
图2是现有的分组数据转发流程的示意图。如图2所示的例子中，分组设备具有M个以太网入端口(以太网入端口1，以太网入端口2，…，以太网入端口M)，每个以太网入端口对应各自的分组数据单元转发决策模块。M个以太网入端口共对应M个分组数据单元转发决策模块(分组数据单元转发决策模块1，分组数据单元转发决策模块2，…，分组数据单元转发决策模块M)。分组设备具有N个以太网出端口(以太网出端口1，以太网出端口2，…，以太网出端口N)，每个以太网出端口对应各自的分组数据单元排队缓冲模块。N个以太网出端口共对应N个分组数据单元排队缓冲模块(分组数据单元排队缓冲模块1，分组数据单元排队缓冲模块2，…，分组数据单元排队缓冲模块N)。
应理解，图2示出的分组数据转发流程可以对应于传统的标准以太网，也可以对应于灵活以太网。图2中以太网入端口是逻辑上的概念。标准以太网中，由于没有对物理接口划分时隙，所以一个以太网入端口可以对应一个或多个物理接口；在灵活以太网中，则一个以太网入端口可以对应一个或多个物理接口，或者一个以太网入端口可以对应一个或多个物理接口的一个或多个时隙。
如前文中描述的，当分组数据单元序列流到达分组设备时，对应的以太网入端口的分组数据单元转发决策模块需要对每一个分组数据单元MAC地址进行识别，通过查表对分组数据单元的目的MAC地址进行匹配，获得以太网出端口。然后通过与查找到的以太网出端口对应的分组数据单元排队缓冲模块，对分组数据单元进行缓存排队，等待从以太网出端口被发送输出。查表和数据缓冲存储会耗费巨大的硬件资源，使得分组设备成本高，规模受限。并且，数据的不确定性缓冲存储以及查表会导致不确定性的高延迟，使得分组设备难以适应一些延迟敏感的应用。
针对上述情况，本申请实施例提供了一种转发数据的方法，包括：通过第一逻辑入端口获取第一数据单元序列流，所述第一数据单元序列流中包括至少一个第一数据单元；根据预配置的至少一个逻辑入端口和至少一个逻辑出端口的映射关系，确定所述第一逻辑入端口对应的第一逻辑出端口，所述至少一个逻辑入端口包括所述第一逻辑入端口；调整所述第一数据单元序列流中的空闲单元的数量，使得调整后的第一数据单元序列流的速率与所述第一逻辑出端口的速率匹配；通过所述第一逻辑出端口发送所述调整后的第一数据单元序列流。
其中，所述第一逻辑入端口对应至少一个物理入接口或至少一个物理入接口的至少一个时隙，所述第一逻辑出端口对应至少一个物理出接口或至少一个物理出接口的至少一个时隙。逻辑入端口和/或逻辑出端口的划分可以是根据业务需求的带宽划分的，具体的划分方式可以参考现有的标准，本申请实施例对此不作限定。
不考虑端口的接收发送功能，逻辑入端口和逻辑出端口均为逻辑端口。具体以FlexE为例，FlexE对以太网物理接口的时隙进行划分，例如100GE划分出20个5G带宽的时隙，若干(例如m)个100GE可以级联成一个FlexE组(FlexE Group)，共20*m个时隙。这些时隙可以任意组合成若干个不同大小的逻辑端口，每个逻辑端口的带宽为5G带宽的整数倍。一个的逻辑端口可以对应于传统的一个以太网物理接口。一个的逻辑端口也可以对应于传统的多个以太网物理接口。一个逻辑端口还可以由对应时隙组合而成，例如由一个以太网物理接口的至少一个时隙组合而成，或是由来自多个以太网物理接口的多个时隙组合而成。
图3是本申请一个实施例的转发数据的方法的示意图。图3中示出了多个逻辑端口，对与第一逻辑入端口和第一逻辑出端口而言，第一逻辑入端口对应于FlexE入接口组1(至少一个物理接口)的某些时隙，第一逻辑出端口对应于FlexE出接口组2(至少一个物理接口)的某些时隙。第一逻辑入端口接收第一数据单元序列流不经内容的解读而直接转发至第一逻辑出端口。其中，图中的每个FlexE入接口组可以对应一个或多个逻辑入端口，每个FlexE出接口组可以对应一个或多个逻辑出端口；每个以太网入接口可以对应一个逻辑入端口，每个以太网出接口可以对应一个逻辑出端口。图中仅是示意性的示出了以太网接口和FlexE接口组的情况，本申请实施例的方法还可以适用于包括其他类型接口的场景。图3中示出的除第一逻辑入端口和第一逻辑出端口以外的其它的逻辑入端口和逻辑出端口对数据单元序列流的转发过程类似，此处不再赘述。
应理解，图3中示出的逻辑入端口和逻辑出端口的个数仅是示意性的，本申请实施例的方法适应于有至少一个逻辑入端口和至少一个逻辑出端口的情况。
应理解，本申请实施例不仅可以支持一到一的数据转发，本申请实施例中还可以有多个逻辑入端口对应一个逻辑出端口。此时，要求多个逻辑入端口的总带宽等于逻辑出端口的带宽，即下游管道的带宽等于上游管道的总带宽。多个逻辑入端口对应一个逻辑出端口可以认为是数据的汇聚。
本申请实施例中一个逻辑入端口可以对应多个逻辑出端口。此时，将一个逻辑入端口接收的数据单元序列流直接复制多份分别发送到对应的多个逻辑出端口。即本申请实施例的方法可以支持一到多(组播)转发和多对一(汇聚)转发。
相应地，所述至少一个逻辑入端口和至少一个逻辑出端口的映射关系包括以下映射关系中的至少一种：所述至少一个逻辑入端口中的一个逻辑入端口和所述至少一个逻辑出端口中的一个逻辑出端口的一对一的映射关系；所述至少一个逻辑入端口中的一个逻辑入端口和至少一个逻辑出端口中多个逻辑出端口的一对多的映射关系；和所述至少一个逻辑入端口中的多个逻辑入端口和至少一个逻辑出端口中一个逻辑出端口的多对一的映射关系。
应理解，在本申请实施例中，当至少一个逻辑入端口中包括至少两个逻辑入端口时，至少两个逻辑入端口分别对应的物理接口为光传送网OTN接口、灵活光传送网FlexOTN接口、以太网接口、灵活以太网FlexE接口、通用公共无线接口CPRI、同步数字体系SDH接口、光纤通道FC接口和无限带宽InfiniBand接口中的至少两种；和/或当至少一个逻辑出端口中包括至少两个逻辑出端口时，至少两个逻辑出端口分别对应的物理接口为光传送网OTN接口、灵活光传送网FlexOTN接口、以太网接口、灵活以太网FlexE接口、通用公共无线接口CPRI、同步数字体系SDH接口、光纤通道FC接口和无限带宽InfiniBand接口中的至少两种。即本申请实施例的转发数据的方法和设备可以基于多种网络技术和协议。首先，基于多种网络物理接口提供逻辑端口，逻辑端口是与物理接口的具体形式无关的；其次，是与被转发的数据单元的协议类型无关的，数据可以是各种协议的，不需要对数据单元中的字段对应具体协议进行解析。
还应理解，本申请实施例中第一逻辑入端口对应的物理接口的类型与第一逻辑出端口对应的物理接口的类型，可以相同，也可以不同，本申请实施例对此不作限定。
需要指出的是，本申请各实施例并不限定物理接口的具体速率和类型，也不限定划分时隙的手段和颗粒度。例如，所述至少一个逻辑入端口中的每个逻辑入端口和所述至 少一个逻辑出端口中的每个逻辑出端口对应的物理接口为以下类型的接口：光传送网OTN接口、灵活光传送网FlexOTN接口、以太网接口、灵活以太网FlexE接口、通用公共无线接口CPRI、同步数字体系SDH接口、光纤通道FC接口或无限带宽InfiniBand接口。在本申请各实施例中，通常一个逻辑端口对应的多个物理接口或对应多个物理接口的多个时隙时，该多个物理接口的接口类型可以是相同的，但本申请实施例对此不作限定。
本申请实施例中，转发设备通过逻辑入端口接收数据单元序列流。第一数据单元序列流中包括至少一个第一数据单元。第一数据单元也可以理解为业务数据单元或报文。所述至少一个第一数据单元可以包括以下数据单元中的至少一种：OTN数据单元、FlexOTN数据单元、以太网分组数据单元、FlexE分组数据单元、CPRI数据单元、同步数字体系SDH数据单元、FC数据单元和InfiniBand数据单元。第一数据单元内可以包括填充，也可以不包括填充，是否包括填充与第一数据单元的类型有关。还应理解，从不同接口类型及从不同网络接收到的数据单元序列流，除包括数据单元外，还可以包括至少一个空闲单元。下面通过举例进行详细说明数据单元序列流以及其包括的数据单元和可能包括的空闲单元。
通过以太网接口、FlexE接口、FC接口和InfiniBand接口接收的数据单元序列流既包括数据单元，又包括空闲单元。需要指出的是，本申请实施例中的空闲单元也可以称作是空闲信息，例如以太网，不限定为解码后在媒体不相关接口(Media Independent Inteface，MII)上的数据格式，即以带外信息发送(字符)控制(信号)(Transmit(character)Control(signals)，TXC)、或接收(字符)控制(信号)(Received(character)Control(signals)，RXC)辅助指示是否空闲字节；也不限定为是将发送(字符)数据(Transmit(character)Data，TXD)+TXC编码在一起的10比特8/10B编码块数据格式的空闲码元，或者是64/66B编码块数据格式的空闲码元，即以显式指示数据单元或者空闲单元的数据形式。
第一数据单元序列流可以是经过编码的数据单元序列流。即第一数据单元序列流中的至少一个第一数据单元可以为经过编码的数据单元。进一步地，由于数据单元序列流既包括数据单元又包括空闲单元，数据单元序列流中包括的至少一个数据单元和伴随的空闲单元可以为经过编码的。这里编码可以是64/66B编码、8/10B编码、512/513B编码或512/514B编码。其中，64/66B编码的一个码元对应8字节原始数据，8/10B编码的一个码元则对应1字节原始数据。
在一个具体的例子中，当数据来自以太网时，通过以太网接口接收的第一数据单元序列流中的第一数据单元可以包括以0b10为同步头的类型为0x33或0x78的64/66B开始控制码块、以0b01为同步头的64/66B数据码块、以0b10为同步头的类型为0x87、0x99、0xAA、0xB4、0xCC、0xD2、0xA1或0xFF(依次对应结束字符在8字节码块中的位置1～8)的64/66B结束控制码块。8/10B编码的数据单元与64/66B编码的数据单元类似，1个字节编码为10比特，相对应地，第一数据单元可以包括8/10B开始控制码块、数据码块和8/10B结束控制码块。第一数据单元序列流中可以包括指示数据单元的开始、持续、结束或者指示空闲单元的存在和持续的控制信息。
第一数据单元序列流中的至少一个第一数据单元也可以是未经过编码的。在一个具体的例子中，当数据来自以太网时，第一数据单元序列流通过XGMII/CGMII等MII接口的带外控制信息TXC/RXC 0或者1指示数据单元的开始(TXC/RXC由1变0)、持 续和结束(TXC/RXC由0变1)，以及空闲单元的存在和持续(TXC/RXC＝1)。应理解，替代上述控制信息，也可以以其他方式例如指针和存储地址等在芯片或者计算机系统内部指示第一数据单元序列流的数据单元或空闲单元。
通过FlexE接口上的逻辑端口接收的数据单元序列流与通过以太网接口(也是一个逻辑端口)接收的数据单元序列流类似，包括以太网协议下的分组数据单元和以太网协议下的空闲单元，此处不再赘述。
通过FC接口(也是一个逻辑端口)接收的FC的数据单元序列流包括FC数据单元和FC协议下的空闲单元。通过InfiniBand接口(也是一个逻辑端口)接收的InfiniBand的数据单元序列流包括InfiniBand分组数据单元和InfiniBand网络协议下的空闲单元。FC和InfiniBand本身为基于统计复用技术的分组网络协议技术。FC和InfiniBand的数据单元类似于以太网的分组数据单元。FC和InfiniBand的数据单元的间的空闲单元也类似于以太网的空闲单元。
以FC的数据单元序列流为例进行详细说明，FC的数据单元序列流中的数据单元为FC帧，空闲单元为Fill Word(4个字节)。FC数据单元即FC帧中，4字节为一个字(Word)，FC帧的长度为4字节的整数倍。FC的数据单元序列流一般要求FC帧之间至少有2个Fill Words或者至少有6个服务原语字(其中至少4个为Fill Words)。
未进行编码(未进行8/10B编码或者未进行64/66B编码)的FC帧具有如图4所示的结构。FC帧通常由4字节的帧起始字(Start Of Frame，SOF)开始，随后是帧内容，最后以4字节的帧结束字(End Of Frame，EOF)结束。帧内容部分包括24字节的帧头(frame header)、数据段(data field)、4字节的循环冗余校验(Cyclic Redundancy Check，CRC)，帧内容还可以包括扩展头(extended header)，其中，数据段为4字节的整数倍，通常为0～2112字节。
对于经过64/66B编码的FC的数据单元序列流，其空闲单元可以称为空闲码块，典型的空闲码块对应两个Fill Words，FC的空闲码块与以太网的空闲码块一致。包含Fill Word在内的各种FC服务原语字两两组合，可以进行64/66B编码，获得与以太网64/66B编码一致的码块序列。采用8/10B编码的情形情况类似。
而通过OTN接口、FlexOTN接口、CPRI或SDH接口接收的数据单元序列流则只包括相应格式的数据单元，不包括空闲单元。
下面以CPRI的数据单元为例进行说明，CPRI技术具有多种不同的速率选项，如下：
·CPRI line bit rate option 1:614.4Mbit/s,8B/10B line coding(1x 491.52x 10/8Mbit/s)
·CPRI line bit rate option 2:1228.8Mbit/s,8B/10B line coding(2 x 491.52 x 10/8Mbit/s)
·CPRI line bit rate option 3:2457.6Mbit/s,8B/10B line coding(4 x 491.52 x 10/8Mbit/s)
·CPRI line bit rate option 4:3072.0Mbit/s,8B/10B line coding(5 x 491.52 x 10/8Mbit/s)
·CPRI line bit rate option 5:4915.2Mbit/s,8B/10B line coding(8 x 491.52 x 10/8Mbit/s)
·CPRI line bit rate option 6:6144.0Mbit/s,8B/10B line coding(10 x 491.52 x 10/8Mbit/s)
·CPRI line bit rate option 7:9830.4Mbit/s,8B/10B line coding(16 x 491.52 x 10/8Mbit/s)
·CPRI line bit rate option 7A:8110.08Mbit/s,64B/66B line coding(16 x 491.52 x 66/64Mbit/s)
·CPRI line bit rate option 8:10137.6Mbit/s,64B/66B line coding(20 x 491.52 x 66/64Mbit/s)
·CPRI line bit rate option 9:12165.12Mbit/s,64B/66B line coding(24 x 491.52 x 66/64Mbit/s)
·CPRI line bit rate option 10:24330.24Mbit/s,64B/66B line coding(48 x 491.52 x 66/64Mbit/s)
首先介绍CPRI接口协议下CPRI基本帧的结构，具体如表1所示。基本帧以字节为单位，并具有固定的帧长度。对速率选项1的CPRI基本帧，其包括共16个字，每个字1个字节，16个字中的第1个字为控制字，表示该基本帧的开始，其余15个字为数据字。对速率选项2的CPRI基本帧，其包括共16个字，每个字2个字节。类似地，表中未示出，对速率选项7/7A的CPRI基本帧，其包括共16个字，每个字16个字节。因此，基本帧的长度为8字节的整数陪，可以为整数个64/66B编码块。
表1 CPRI基本帧结构
Figure PCTCN2017080893-appb-000001
256个CPRI的基本帧构成一个CPRI超帧，CPRI超帧的第一个字为同步头控制字，可以代表CPRI超帧的开始。对选定的速率选项CPRI超帧的长度是固定的，因而可以确定CPRI超帧的帧开始、持续和帧结束的位置。
对于采用64/66B编码的速率选项，CPRI超帧的第一个基本帧的控制字(同步字) 的首8字节以及次8字节分别被编码为同步头为0b10，类型为0xFF的64/66B控制码块，以及同步头为0b10，类型为0x78的64/66B控制码块，可以实现CPRI超帧的帧开始、持续和帧结束的标记。其余数据全部编码为同步头为0b01的数据码块。由此可见，CPRI接口的数据单元序列流，与前文描述的以太网的数据单元、FC的数据单元的形式是一致的。在都为64/66B编码的情形下，CPRI的数据单元序列流与以太网的数据单元序列流、FC的数据单元序列流的主要区别在于CPRI的数据单元序列流中的数据单元间没有空闲码块。
再以OTN的数据单元为例进行简单说明。OTN的数据单元为OTU-k帧，为固定大小的帧结构。在OTU-k帧中包括4行4080列共计4x4080＝16320字节，其中14字节的OTU-k帧开销包括SM、GCC0、RES共7个字节和帧同步开销FAS、MFAS共7个字节。6字节的开销FAS是固定序列，类似于以太网中的前导码序列。以开销FAS作为OTU-k帧的帧开始的标记，由于OTU-k帧为固定大小的帧结构，因此，可以确定OTU-k帧的帧开始、持续和帧结束的位置。OTN的数据单元与前文描述的以太网的数据单元、FC的数据单元、CPRI的数据单元的形式是一致的。
应理解，本申请实施例的一个数据单元可以对应一个数据帧，也可以对应更多数量的数据帧，甚至可以将在逻辑端口上传播的无限多个数据帧看作一个数据单元。这里的数据帧可以是指前文中的FC帧、CPRI超帧或OTU-k帧等等。
综上所述，不论是以太网、FlexE、FC和InfiniBand等更接近于报文形式的数据单元，还是OTN、FlexOTN、CPRI和SDH等更接近于帧格式的数据单元，其都具有类似的格式，都可以通过各种标识确定数据单元的开始、持续和结束的位置。
应理解，本申请实施例的逻辑入端口接收的数据单元序列流的协议类型并不一定与逻辑入端口相对应的物理接口的类型相同。例如，由于在上游的转发设备处转发，OTN的物理接口对应的逻辑入端口接收的数据单元序列流的数据单元可能是以太网协议的，这里仅是举例说明，而非对本申请实施例的限定。
在本实施例中，通过预配置的至少一个逻辑入端口和至少一个逻辑出端口的映射关系，确定接收第一数据单元序列流的第一逻辑入端口对应的第一逻辑出端口。至少一个逻辑入端口和至少一个逻辑出端口的映射关系的实现形式可以是配置表也可以是固化到转发设备中的器件。该映射关系可以由网络管理员修改或更换，本申请实施例对此不作限定。
可选地，映射关系可以以表的形式在网络管理计算机系统中存储和使用。但本申请实施例的映射关系是不同于现有的方案的目的地址(例如目的MAC地址)和出端口的对应关系的。本申请实施例的映射关系中直接包括了逻辑入端口和逻辑出端口的关系，因此无需进行数据单元完整性的校验，例如CRC校验，不需要对数据单元进行内容的解读，无需进行目的地址的查表处理，逻辑出端口相对于逻辑入端口均是独占的并且预先配置好，因此从逻辑入端口抵达的数据单元序列流中的数据单元无需逐个查表、排队和缓存，直接从逻辑出端口发出。
本申请实施例中的某一个逻辑入端口接收到的数据可以是在转发设备的上游的其他设备中进行过分组识别集合在一起的，也可以是通过其他方式集合在一起的，本申请实施例对此不作限定。
具体地，本申请实施例从业务管理角度上看，数据单元的转发可以基于静态和半静 态配置。结合图5和表2至表5来进行详细说明。图5是本申请一个实施例的逻辑入端口和逻辑出端口的映射关系的示意图。图5中有三个物理接口组，物理接口A组、物理接口B组和物理接口C组。物理接口组中物理接口的类型可以是前文中提到的类型。在一个具体的例子中，物理接口B组可以为一个标准以太网接口，物理接口A组可以为FlexE接口组，物理接口C组可以为FlexOTN接口组。逻辑入端口A.1和逻辑入端口A.6分别对应物理接口A组的某些时隙，具体参见表2。逻辑出端口B.1对应整个物理接口B组，具体参见表3。逻辑出端口C.2对应物理接口C组的某些时隙，具体参见表4。表2至表4中还可以为每个逻辑端口分配数据单元序列流标识以区分数据单元序列流。表5给出了逻辑入端口和逻辑出端口的映射关系。例如，逻辑入端口A.1对应逻辑出端口C.2，逻辑入端口A.6对应逻辑出端口B.1，属于在上文中所描述的本申请实施例的转发数据的方法。表5中还给出图5中未示出的逻辑入端口A.2接收的数据单元序列流需要进行逐数据单元查表存储转发，具体交换方式将在下文中详细描述。
配置表精简容易维护，一般由网管进行配置或者由协议自动配置。配置表主要包括分配和标识逻辑端口对应的接口组的时隙，具体为物理接口的时隙分配和逻辑端口映射关系(表2至表4)；以及无延迟转发的端口到端口的映射关系配置(表5)。上述映射关系精简短小，可以认为是抽象出来的一些表格，实际上可以并不以表格的形式存在。这些映射关系一般保存在管理系统中，数据面上已经固化为设备的硬件配置，规避了和降低了转发设备按照分许协议地址和标签进行大规模查找表的维护和海量表项的查找问题，实现了无表转发。
Figure PCTCN2017080893-appb-000002
Figure PCTCN2017080893-appb-000003
Figure PCTCN2017080893-appb-000004
Figure PCTCN2017080893-appb-000005
在本申请实施例中，预配置的至少一个逻辑入端口和至少一个逻辑出端口的映射关系可以按照逻辑入端口和逻辑出端口的有效时间段进行更新，即当系统内逻辑入端口和逻辑出端口的定义发生变化时，系统中的相应的设备(例如控制器)可以对上述映射关系进行更新。
应理解，本申请实施例中逻辑端口可以为单向逻辑端口也可以为双向逻辑端口，第一数据单元序列流可以为单向数据单元序列流，也可以为双向数据单元序列流，本申请实施例对此不作限定。
逻辑端口由一组(至少一个)物理接口划分时隙组合而得，与物理接口的时钟速率相关。因此，物理接口组上的逻辑端口的速率由其对应的物理接口的速率决定，当物理接口的时钟有偏差时，逻辑端口会继承该偏差。
以太网的异步通信物理接口，允许正负100ppm(其中，1ppm为万分之一)的时钟频率差异以降低对设备的要求。例如在10GE网络中，两个标称10G带宽的物理接口可能一个比标称值大万分之一，一个比标称值小万分之一，分别为10G*(1+0.0001)和10G*(1-0.0001)。
逻辑端口之间的实际时钟速率继承物理接口的正负100ppm的时钟频率差异。例如，逻辑入端口和逻辑出端口都是5个5G时隙级联的逻辑端口，除去灵活以太网划分时隙和管理时隙的开销，在极端情况下，两个不同物理接口组上的标称带宽同样的逻辑端口的实际带宽分别为25G*(20460/20461)*(1+0.0001)和25G*(20460/20461)*(1-0.0001)。此时，如果通过该逻辑入端口和逻辑出端口转发数据，则需要进行速率匹配。
由此，逻辑入端口及其相应的逻辑出端口的速率可能是不相等的，换而言之，数据单元序列流在第一逻辑入端口的传输速率和数据单元序列流在第一逻辑出端口的传输速率可能是不相等的。在本申请实施例中，调整所述第一数据单元序列流中的空闲单元的数量，使得调整后的第一数据单元序列流的速率与所述第一逻辑出端口的速率匹配。
具体而言，以数据单元序列流同时包括数据单元和空闲单元为例进行说明。对从第一逻辑入端口接收的第一数据单元序列流进行区分，区分出数据单元和空闲单元，对空闲单元的数量进行必要的增删，以匹配逻辑出端口的带宽差异，实现数据单元序列流在两个逻辑端口的速率匹配。
可选地，可以将第一数据单元序列流中的空闲单元全部删除，在第一逻辑出端口处按照需要重新插入适当数量的空闲单元。当然，本申请实施例中，还可以实时地按照需要插入或者删除空闲单元。本申请实施例中，数据是以流的形式一直在转发的，空闲单 元的插入或者删除也是随着流实时进行的。当第一逻辑入端口的传输速率和第一逻辑出端口的传输速率差异不大时，有可能在相当一段时间内，第一逻辑出端口处的第一数据单元序列流中的空闲单元的数量与第一逻辑入端口处的第一数据单元序列流中的空闲单元的数量是相等的。
可选地，本申请实施例还允许切断连续的数据单元而插入空闲单元。简单的方法是在切断处插入一种新型的空闲单元；或者，使用现有的空闲单元(例如，空闲字节或者空闲码元)，但在切断处插入的空闲单元与第一数据单元序列流中的空闲单元的类型不相同。这样，接收端可以通过空闲单元的类型来判断是前一数据单元的延续，不是新的数据单元。
在切断处插入的空闲单元显而易见的情况下，例如以太网中，不是上一分组结束后和或下一分组开始之前出现的空闲单元，可以使用相同的空闲单元。此外，还可以通过判断数据单元的长度进行判断。例如，当前接收到n个碎片，该n个碎片的总长度小于正常数据单元的允许长度，当接收端接收到数据时，接收到的数据与n个碎片的长度相加的总长度依然小于正常数据单元的允许长度，那可以判断当前接收到的数据仍为碎片(即数据单元的第n+1个碎片)。一旦被确认为碎片，则其为前一数据单元的延续，不是新的数据单元。本申请实施例中还可以通过其他的方式区分碎片，这里不作限定。
图6是本申请一个实施例的通过调整空闲单元的数量来进行速率匹配的示意图。图6中(A)以接收到的为以太网的数据单元序列流为例，数据单元序列流包括空闲单元组n-1、分组数据单元n-1、空闲单元组n、分组数据单元n、空闲单元组n+1和分组数据单元n+1。由于其对应的逻辑入端口的速率小于逻辑出端口的速率，因此在(B)中进行速率匹配时将空闲单元组n中空闲单元的数量增加。图6中(C)为接收到的数据单元序列流，包括空闲数据单组元n-1、分组数据单元n-1、空闲单元组n、分组数据单元n、空闲单元组n+1和分组数据单元n+1。由于其对应的逻辑入端口的速率小于逻辑出端口的速率，且速率的差异较大，因此在(D)中进行速率匹配时，切断了连续的分组数据单元n而插入空闲单元。
就以太网1500字节左右的分组数据单元长度而言，即使第一逻辑入端口与第一逻辑出端口具有200ppm的时钟速率差异，只在以太网分组之间进行空闲单元的增删调整(不切断分组数据单元)，缓存深度也只需要1500*0.0002；即使9.6k超长帧，缓存深度需求也不足2个字节。相比10GE、100GE采用的4字节以上的数据位宽，这样的缓存需求可以忽略不计。因此，本申请实施例的转发分组数据的方法可以称为无延迟高效转发。
可选地，本申请实施例可以按照系统的位宽控制空闲单元的增删。图7是本申请几个实施例的调整空闲单元的示意图。图7中的(A)至(C)示出了基于8/10B码块的以太网系统。图7中的(D)至(F)示出了基于64/66B码块的以太网系统。在两种系统中，我们抽象地在功能上进行了区域划分，其中，第一功能区域对应的功能为物理接口技术以及时隙划分，包括入端口接收数据、解扰码(仅对应于64/66B码块系统)和时隙划分逻辑端口呈现等步骤，第一功能区域对应的功能整体对应于前文中描述的通过第一逻辑入端口获取第一数据单元序列流；第二功能区域对应的功能为速率匹配，主要包括调整空闲单元(空闲字节或空闲码元的增加或删除)，第二功能区域对应的功能整体对应于前文中描述的调整所述第一数据单元序列流中的空闲单元的数量，使得调整后的第一数据单元序列流的速率与所述第一逻辑出端口的速率匹配；第三功能区域对应的功能为逻 辑端口区分技术，包括逻辑端口匹配接口时隙、扰码(仅对应于64/66B码块系统)和出端口发送数据等步骤，第三功能区域对应的功能整体对应于前文中描述的通过所述第一逻辑出端口发送所述调整后的第一数据单元序列流。由于映射关系通常固化为设备的硬件配置，因此该例子中未体现根据预配置的多个逻辑入端口和多个逻辑出端口的映射关系，确定所述第一逻辑入端口对应的第一逻辑出端口这一过程。
调整空闲单元可以在接收到的原始数据单元序列流后不进行解码和重新编码的情况下进行，此时调整空闲单元为空闲码元的增加或删除，例如图7中的(A)和(D)。调整空闲单元也可以在对接收到的数据单元序列流进行解码和重新编码的情况下进行，此时调整空闲单元为空闲字节的增加或删除，例如图7中的(B)、(C)(E)和(F)。其中，图7中的(B)和(E)解码和重新编码是在物理接口执行的；图7中的(C)和(F)解码和重新编码是在逻辑端口执行的。
对应图7，当所述第一数据单元序列流为经过编码的数据单元序列流时，一种调整所述第一数据单元序列流中的空闲单元的数量的方式，步骤可以包括：对所述第一数据单元序列流进行解码；调整解码后的第一数据单元序列流中空闲字节的数量，使得调整后的第一数据单元序列流的速率与所述第一逻辑出端口的速率匹配；对调整后的第一数据单元序列流进行编码；所述通过所述第一逻辑出端口发送所述调整后的第一数据单元序列流，包括：通过所述第一逻辑出端口发送调整且编码后的第一数据单元序列流。另一种调整所述第一数据单元序列流中的空闲单元的数量的方式，步骤可以包括：所述第一数据单元序列流为经过编码的数据单元序列流，所述调整所述第一数据单元序列流中的空闲单元的数量，包括：调整所述第一数据单元序列流中经过编码的空闲码元的数量，使得调整后的第一数据单元序列流的速率与所述第一逻辑出端口的速率匹配。
图8是本申请一个实施例的进行速率匹配的方式的示意图。在逻辑入端口接收到数据单元序列流为以太网协议的数据单元序列流，而逻辑出端口对应的物理接口为OTN的物理接口时，可以使用GFP协议实现数据单元序列流与逻辑出端口的速率匹配。GFP协议定义有空闲帧，效果如同以太网的空闲字节，因此可以先将以太网协议的数据单元序列流的原空闲单元(例如可以是空闲字节)全部删除，使用GFP协议对分组数据单元进行封装处理，并插入GFP的空闲进行速率适配。这种情况下，本申请实施例为逻辑端口分配的带宽，应当足以支持使用GFP协议对分组数据单元进行封装处理后的数据单元序列流的带宽。
前文中提到，FC和InfiniBand的数据单元类似于以太网的分组数据单元。FC和InfiniBand的数据单元的间的空闲单元也类似于以太网的空闲单元。因此，FC和InfiniBand的数据单元序列流与逻辑出端口的速率适配的方法与以太网的数据单元序列流的速率适配的方法类似，此处不再进行赘述。
传统的SDH和OTN等第三方协议的物理接口也具有时隙划分和逻辑端口支持能力。例如，SDH的时隙、传统OTN以及FlexOTN的高阶光传输载荷单元(Optical(Channel)Payload Unit，OPU)中的时隙。对应地，可以采用新兴的通用成帧规程(Generic Framing Procedure，GFP)，或针对以太网业务的基于空闲增删的映射处理规程(Idle insert/delete based Mapping Procedure，IMP)等等实现速率匹配。使得现有的SDH、OTN、FlexOTN等物理接口技术、原有投资和研发投入、芯片、光模块等资源，尤其是长距离光传输涉及的资源可以沿用。
下面以对CPRI接口接收到的数据单元序列流进行速率匹配为例进行详细说明。CPRI接口协议基本帧以字节为单位，并具有固定的帧长度。其物理接口典型也可使用8/10B编码或者64/66B编码。其他类型业务，例如SDH/OTN等CBR业务的接口技术也可以采用类似CPRI的方式，对其相应的数据帧结构单元序列进行64/66B编码等。因此，在这些协议下，数据帧即为数据单元。在帧(数据单元)之间可以插入空闲字节或者8/10B编码空闲码元或者64/66B编码空闲码元。这些数据单元序列流可以在基于以太网或FlexE等接口技术的转发设备上得到支持。
前文中提到，CPRI的数据单元为CPRI超帧，与以太网的分组数据单元类似，可以以相应的方法标记帧开始、持续和帧结束的位置。因此，与以太网的数据单元序列流类似地，也可以靠调整CPRI的数据单元序列流的空闲单元来进行速率匹配。这里的调整CPRI的数据单元序列流的空闲单元主要是增加空闲单元。即从原生的CPRI接口或端口接收无空闲原生的CPRI数据单元序列流，通过增加空闲单元，适配到非原生的接口或端口上发生，例如灵活以太网端口。
图9示出了对CPRI的数据单元序列流进行速率匹配的示意图。图9的A示出了未进行速率匹配时，CPRI的数据单元序列流的两个数据单元，数据单元包括指示数据单元开始部分和结束部分，其余部分为数据部分D。当逻辑出端口为以太网协议的端口时，将以太网的空闲码块插入到CPRI的编码后的数据单元中(如图9的C所示，编码之后数据部分被编码为码元，开始部分好、结束部分和空闲均被编码为控制码元)或者等效的先在未编码的数据单元插入空闲(如图9的B所示)后再进行编码处理，都可以将CPRI超帧的数据单元序列流转成前文的实施例中的以太网的分组数据单元序列流，并通过本申请实施例的方法实现对CPRI业务在本申请实施例的转发数据的设备上进行交换。例如，对于CPRI line bit rate option 8:10137.6Mbit/s,64B/66B line coding(20x491.52x66/64Mbit/s)，其编码后的速率为10.1376G，小于10GE网络的10.3125G，或者小于FlexE的两个时隙的总带宽。由此，可以通过在数据单元序列流插入适当数量的IDLE，使得数据单元序列流可以在10GE的物理接口或者2个FlexE 5G时隙对应的逻辑端口上传输。对IDLE插入的位置，可以选择在结束码块和开始码块之间，也可以选择放在数据中间，本申请实施例对此不做限定。
在一个具体的例子中，可以进行类似以下的设计。例如，参考以下速率值，CPRI接口中各个选项的未编码速率为n×491.528M，当n等于10的时候，可以匹配当前的FlexE的5G时隙中，并有足够的带宽剩余。
对于CPRI技术中编码后的option 8和option 10的速率与FlexE的2×5G时隙和5×5G时隙的带宽比较接近并还有足够的带宽剩余，同时又与实际的10GE和25GE以太网物理接口的带宽接近并还有足够的带宽剩余。数据单元序列流的总带宽小于或等于逻辑端口的带宽时，即使物理接口和逻辑端口有正负100ppm(其中，1ppm为万分之一)的时钟频率差异，通过适当的调整空闲，均可以实现速率匹配。
类似地，将OTN的数据单元序列流速率匹配到以太网协议的逻辑出接口时，可以将OTN的数据单元OTU-k帧中的FAS开销的首字节和末字节分别替换为/T/和/S/字符，再在OTN的数据单元序列流(未编码的)中插入空闲字节，或者在OTN的数据单元序列流(经过编码的)中插入空闲码元，以完成速率匹配，并使速率匹配后的数据单元序列流能够从以太网协议的逻辑出接口发出。
综合以上例子可知，所述调整所述第一数据单元序列流中的空闲单元的数量，可以包括：当所述第一数据单元序列流中包括空闲单元时，增加或减少所述第一数据单元序列流中的空闲单元的数量；当所述第一数据单元序列流中不包括空闲单元时，增加所述第一数据单元序列流中的空闲单元的数量。
应理解，本申请实施例中，所述第一数据单元序列流中的所述至少一个第一数据单元的总带宽小于或等于所述第一逻辑入端口的饱和带宽，且小于或等于所述第一逻辑出端口的饱和带宽。这种配置可以保证业务能够通过调整空闲单元与逻辑入端口和逻辑出端口的速率分别匹配。
还应理解，各种协议类型的数据单元序列流被按照本申请实施例的方法进行转发的时候，转发设备并不对其从业务、协议等角度进行区分。
还应理解，本申请实施例中，对各种协议下的数据单元序列流进行速率匹配的方法可以采用各种现有的方案，而不局限于前文中描述的方法。
本申请实施例的转发数据的方法通过逻辑端口间的直接的映射关系转发数据单元序列流，并通过调整空闲单元的数量实现数据单元序列流与下游出端口的速率匹配，可以有效降低转发设备的转发压力，有效提高转发设备的业务吞吐能力，并能降低数据的转发时延，能够适应于对延迟敏感的大带宽业务。
图10是本申请另一个实施例的转发分组数据的方法示意图。如图10所示，转发设备还可以通过第二逻辑入接口(例如，上文中提到的接口A.2)接收第二数据单元序列流，通过图2中介绍的现有的转发数据的方法对第二数据单元序列流进行数据交换。例如，以太网入接口4接收的第二数据单元序列流的多个分组数据单元经以太网入接口4对应的分组数据单元转发决策模块4，分别在分组数据单元排队缓冲模块5和分组数据单元排队缓冲模块6中排队缓冲，从以太网出接口5和以太网出接口6中发送。再如，FlexE入接口组3上的一个第二逻辑入端口接收的第二数据单元序列流的多个分组数据单元经分组数据单元转发决策模块3，分别在分组数据单元排队缓冲模块5和分组数据单元排队缓冲模块6中排队缓冲，从以太网出接口5和以太网出接口6中发送。
本申请实施例还包括一种对数据单元序列流中的多个分组数据单元不进行转发决策的判断，直接进入对应的分组数据单元排队缓冲模块进行缓冲排队的方案。例如，FlexE入接口组1上的最后一个逻辑入端口接收的数据单元序列流的多个分组数据单元不经经分组数据单元转发决策模块决策，直接发送到分组数据单元排队缓冲模块5中排队缓冲，从以太网出接口5中发送。
相对应地，本申请的转发数据的方法还可以包括：通过第二逻辑入端口获取第二数据单元序列流，所述第二数据单元序列流中包括至少一个第二数据单元，所述至少一个第二数据单元中每一个第二数据单元中分别包括转发决策参考信息；根据所述转发决策参考信息，确定所述至少一个第二数据单元中每一个第二数据单元分别对应的第二逻辑出端口；将所述每一个第二数据单元缓存在对应的所述第二逻辑出端口的缓存队列中；通过所述第二逻辑出端口发送所述第二数据单元序列流中的第二数据单元。
其中，所述转发决策参考信息可以包括目的地址或转发标签等。
本申请实施例还提供了一种转发数据的设备，对应于上文的转发设备。图11是本申请一个实施例的转发数据的设备1100的示意性框图。如图11所示，该设备包括第一逻辑入端口1110、第一逻辑出端口1120、映射关系控制模块1130和速率匹配模块1140， 所述第一逻辑入端口1110，用于获取第一数据单元序列流，所述第一数据单元序列流中包括至少一个第一数据单元；所述映射关系控制模块1130，用于根据预配置的至少一个逻辑入端口和至少一个逻辑出端口的映射关系，确定所述第一逻辑入端口1110对应的第一逻辑出端口1120，所述至少一个逻辑入端口包括所述第一逻辑入端口1110；所述速率匹配模块1140，用于调整所述第一数据单元序列流中的空闲单元的数量，使得调整后的第一数据单元序列流的速率与所述第一逻辑出端口1120的速率匹配；所述第一逻辑出端口1120，用于发送所述调整后的第一数据单元序列流。
其中，映射关系包括软件配置和固化在设备中的硬件配置。
软件配置映射关系可以是通过前文描述的配置表描述逻辑入端口和逻辑出端口的对应。这些映射关系一般保存在管理系统中，可以以表的形式在网络管理计算机系统中存储和使用。
硬件配置映射关系可以是固化在设备中的交叉交换器件的交叉交换连接关系。例如，基于Crossbar的空分(S)交叉器件的交叉连接关系，或者基于时隙存储时分(T)交换器件的顺序写入配置序读出关系以及配置序写入顺序读出关系；或者是组合形式为T-S-T、S-T-S三级交叉器件的交叉交换连接关系等等。随着通信技术的发展，现在可用的映射关系可以是基于信元的交换网片套片(Fabric and Fabric Interface Chip，FAB&FIC)的交换连接关系，或者基于共享内存的单片交换网片的交换连接关系等，实现高效无表转发。
速率匹配模块1140和和固化了映射关系的交叉交换功能可以集成在一起，例如基于共享内存的交换网器件中，按照第一输入逻辑端口速率写入，当写入的数据较多的时候，适当删除未写入或者已写入共享内存中的空闲数据，或者完全不写入空闲数据，只写入数据单元；按照第一逻辑出端口1110不断地从共享内存中读取出并发送数据，当缓存中缓存的数据不足以输出到第一逻辑出端口1120时，在数据单元序列流中插入空闲单元，以完成速率匹配。本申请实施例对速率匹配模块1140和映射关系的具体实现形式不作限定。
可选地，作为一个实施例，所述至少一个逻辑入端口和至少一个逻辑出端口的映射关系包括以下映射关系中的至少一种：所述至少一个逻辑入端口中的一个逻辑入端口和所述至少一个逻辑出端口中的一个逻辑出端口的一对一的映射关系；所述至少一个逻辑入端口中的一个逻辑入端口和至少一个逻辑出端口中多个逻辑出端口的一对多的映射关系；和所述至少一个逻辑入端口中的多个逻辑入端口和至少一个逻辑出端口中一个逻辑出端口的多对一的映射关系。
可选地，作为一个实施例，所述至少一个逻辑入端口中的每个逻辑入端口和所述至少一个逻辑出端口中的每个逻辑出端口对应的物理接口为以下类型的接口：光传送网OTN接口、灵活光传送网FlexOTN接口、以太网接口、灵活以太网FlexE接口、通用公共无线接口CPRI、同步数字体系SDH接口、光纤通道FC接口和无限带宽InfiniBand接口。
可选地，作为一个实施例，所述至少一个第一数据单元包括以下数据单元中的至少一种：OTN数据单元、FlexOTN数据单元、以太网分组数据单元、FlexE分组数据单元、CPRI数据单元、同步数字体系SDH数据单元、FC数据单元和InfiniBand数据单元。
可选地，作为一个实施例，所述第一数据单元序列流中的所述至少一个第一数据单元的总带宽小于或等于所述第一逻辑入端口的饱和带宽，且小于或等于所述第一逻辑出 端口的饱和带宽。
可选地，作为一个实施例，所述第一数据单元序列流为经过编码的数据单元序列流，所述速率匹配模块1140具体用于：对所述第一数据单元序列流进行解码；调整解码后的第一数据单元序列流中空闲字节的数量，使得调整后的第一数据单元序列流的速率与所述第一逻辑出端口的速率匹配；对调整后的第一数据单元序列流进行编码；所述第一逻辑出端口1120具体用于：发送调整且编码后的第一数据单元序列流。
可选地，作为一个实施例，所述第一数据单元序列流为经过编码的数据单元序列流，所述速率匹配模块1140具体用于：调整所述第一数据单元序列流中经过编码的空闲码元的数量，使得调整后的第一数据单元序列流的速率与所述第一逻辑出端口的速率匹配。
可选地，作为一个实施例，所述设备还包括第二逻辑入端口、第二逻辑出端口、数据单元转发决策模块和数据单元排队缓冲模块，所述第二逻辑入端口，用于获取第二数据单元序列流，所述第二数据单元序列流中包括至少一个第二数据单元，所述至少一个第二数据单元中每一个第二数据单元中分别包括转发决策参考信息；所述数据单元转发决策模块，用于根据所述转发决策参考信息，确定所述至少一个第二数据单元序列流中每一个第二数据单元分别对应的第二逻辑出端口；所述数据单元排队缓冲模块，用于将所述每一个第二数据单元缓存在对应的所述第二逻辑出端口的缓存队列中；所述第二逻辑出端口，用于发送所述第二数据单元序列流中的第二数据单元。
所述转发决策参考信息可以包括目的地址或转发标签等。
可选地，作为一个实施例，所述速率匹配模块1140具体用于：当所述第一数据单元序列流中包括空闲单元时，增加或减少所述第一数据单元序列流中的空闲单元的数量；当所述第一数据单元序列流中不包括空闲单元时，增加所述第一数据单元序列流中的空闲单元的数量。
可选地，作为一个实施例，第一数据单元序列流还包括至少一个空闲单元。
应理解，本文中涉及的第一、第二等以及各种数字编号仅为描述方便进行的区分，并不用来限制本申请实施例的范围。
应理解，本文中术语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，本文中字符“/”，一般表示前后关联对象是一种“或”的关系。
应理解，在本申请的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单 元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种转发数据的方法，其特征在于，包括：
    通过第一逻辑入端口获取第一数据单元序列流，所述第一数据单元序列流中包括至少一个第一数据单元；
    根据预配置的至少一个逻辑入端口和至少一个逻辑出端口的映射关系，确定所述第一逻辑入端口对应的第一逻辑出端口，所述至少一个逻辑入端口包括所述第一逻辑入端口；
    调整所述第一数据单元序列流中的空闲单元的数量，使得调整后的第一数据单元序列流的速率与所述第一逻辑出端口的速率匹配；
    通过所述第一逻辑出端口发送所述调整后的第一数据单元序列流。
  2. 根据权利要求1所述的方法，其特征在于，所述至少一个逻辑入端口和至少一个逻辑出端口的映射关系包括以下映射关系中的至少一种：
    所述至少一个逻辑入端口中的一个逻辑入端口和所述至少一个逻辑出端口中的一个逻辑出端口的一对一的映射关系；
    所述至少一个逻辑入端口中的一个逻辑入端口和至少一个逻辑出端口中多个逻辑出端口的一对多的映射关系；和
    所述至少一个逻辑入端口中的多个逻辑入端口和至少一个逻辑出端口中一个逻辑出端口的多对一的映射关系。
  3. 根据权利要求1或2所述的方法，其特征在于，所述至少一个逻辑入端口中的每个逻辑入端口和所述至少一个逻辑出端口中的每个逻辑出端口对应的物理接口为以下类型的接口：
    光传送网OTN接口、灵活光传送网FlexOTN接口、以太网接口、灵活以太网FlexE接口、通用公共无线接口CPRI、同步数字体系SDH接口、光纤通道FC接口或无限带宽InfiniBand接口。
  4. 根据权利要求1至3中任一项所述的方法，其特征在于，所述至少一个第一数据单元包括以下数据单元中的至少一种：
    OTN数据单元、FlexOTN数据单元、以太网分组数据单元、FlexE分组数据单元、CPRI数据单元、同步数字体系SDH数据单元、FC数据单元和InfiniBand数据单元。
  5. 根据权利要求1至4中任一项所述的方法，其特征在于，所述第一数据单元序列流中的所述至少一个第一数据单元的总带宽小于或等于所述第一逻辑入端口的饱和带宽，且小于或等于所述第一逻辑出端口的饱和带宽。
  6. 根据权利要求1至5中任一项所述的方法，其特征在于，所述第一数据单元序列流为经过编码的数据单元序列流，
    所述调整所述第一数据单元序列流中的空闲单元的数量，包括：
    对所述第一数据单元序列流进行解码；
    调整解码后的第一数据单元序列流中空闲字节的数量，使得调整后的第一数据单元序列流的速率与所述第一逻辑出端口的速率匹配；
    对调整后的第一数据单元序列流进行编码；
    所述通过所述第一逻辑出端口发送所述调整后的第一数据单元序列流，包括：
    通过所述第一逻辑出端口发送调整且编码后的第一数据单元序列流。
  7. 根据权利要求1至5中任一项所述的方法，其特征在于，所述第一数据单元序列流为经过编码的数据单元序列流，
    所述调整所述第一数据单元序列流中的空闲单元的数量，包括：
    调整所述第一数据单元序列流中经过编码的空闲码元的数量，使得调整后的第一数据单元序列流的速率与所述第一逻辑出端口的速率匹配。
  8. 根据权利要求1至7中任一项所述的方法，其特征在于，所述方法还包括：
    通过第二逻辑入端口获取第二数据单元序列流，所述第二数据单元序列流中包括至少一个第二数据单元，所述至少一个第二数据单元中每一个第二数据单元中分别包括转发决策参考信息；
    根据所述转发决策参考信息，确定所述至少一个第二数据单元中每一个第二数据单元分别对应的第二逻辑出端口；
    将所述每一个第二数据单元缓存在对应的所述第二逻辑出端口的缓存队列中；
    通过所述第二逻辑出端口发送所述第二数据单元序列流中的第二数据单元。
  9. 根据权利要求1至8中任一项所述的方法，其特征在于，所述调整所述第一数据单元序列流中的空闲单元的数量，包括：
    当所述第一数据单元序列流中包括空闲单元时，增加或减少所述第一数据单元序列流中的空闲单元的数量；
    当所述第一数据单元序列流中不包括空闲单元时，增加所述第一数据单元序列流中的空闲单元的数量。
  10. 根据权利要求1至8中任一项所述的方法，其特征在于，第一数据单元序列流还包括至少一个空闲单元。
  11. 一种转发数据的设备，其特征在于，包括第一逻辑入端口、第一逻辑出端口、映射关系控制模块和速率匹配模块，
    所述第一逻辑入端口，用于获取第一数据单元序列流，所述第一数据单元序列流中包括至少一个第一数据单元；
    所述映射关系控制模块，用于根据预配置的至少一个逻辑入端口和至少一个逻辑出端口的映射关系，确定所述第一逻辑入端口对应的第一逻辑出端口，所述至少一个逻辑入端口包括所述第一逻辑入端口；
    所述速率匹配模块，用于调整所述第一数据单元序列流中的空闲单元的数量，使得调整后的第一数据单元序列流的速率与所述第一逻辑出端口的速率匹配；
    所述第一逻辑出端口，用于发送所述调整后的第一数据单元序列流。
  12. 根据权利要求11所述的设备，其特征在于，所述至少一个逻辑入端口和至少一个逻辑出端口的映射关系包括以下映射关系中的至少一种：
    所述至少一个逻辑入端口中的一个逻辑入端口和所述至少一个逻辑出端口中的一个逻辑出端口的一对一的映射关系；
    所述至少一个逻辑入端口中的一个逻辑入端口和至少一个逻辑出端口中多个逻辑出端口的一对多的映射关系；和
    所述至少一个逻辑入端口中的多个逻辑入端口和至少一个逻辑出端口中一个逻辑出 端口的多对一的映射关系。
  13. 根据权利要求11或12所述的设备，其特征在于，所述至少一个逻辑入端口中的每个逻辑入端口和所述至少一个逻辑出端口中的每个逻辑出端口对应的物理接口为以下类型的接口：
    光传送网OTN接口、灵活光传送网FlexOTN接口、以太网接口、灵活以太网FlexE接口、通用公共无线接口CPRI、同步数字体系SDH接口、光纤通道FC接口或无限带宽InfiniBand接口。
  14. 根据权利要求11至13中任一项所述的设备，其特征在于，所述至少一个第一数据单元包括以下数据单元中的至少一种：
    OTN数据单元、FlexOTN数据单元、以太网分组数据单元、FlexE分组数据单元、CPRI数据单元、同步数字体系SDH数据单元、FC数据单元和InfiniBand数据单元。
  15. 根据权利要求11至14中任一项所述的设备，其特征在于，所述第一数据单元序列流中的所述至少一个第一数据单元的总带宽小于或等于所述第一逻辑入端口的饱和带宽，且小于或等于所述第一逻辑出端口的饱和带宽。
  16. 根据权利要求11至15中任一项所述的设备，其特征在于，所述第一数据单元序列流为经过编码的数据单元序列流，
    所述速率匹配模块具体用于：
    对所述第一数据单元序列流进行解码；
    调整解码后的第一数据单元序列流中空闲字节的数量，使得调整后的第一数据单元序列流的速率与所述第一逻辑出端口的速率匹配；
    对调整后的第一数据单元序列流进行编码；
    所述第一逻辑出端口具体用于：
    发送调整且编码后的第一数据单元序列流。
  17. 根据权利要求11至15中任一项所述的设备，其特征在于，所述第一数据单元序列流为经过编码的数据单元序列流，
    所述速率匹配模块具体用于：
    调整所述第一数据单元序列流中经过编码的空闲码元的数量，使得调整后的第一数据单元序列流的速率与所述第一逻辑出端口的速率匹配。
  18. 根据权利要求11至17中任一项所述的设备，其特征在于，所述设备还包括第二逻辑入端口、第二逻辑出端口、数据单元转发决策模块和数据单元排队缓冲模块，
    所述第二逻辑入端口，用于获取第二数据单元序列流，所述第二数据单元序列流中包括至少一个第二数据单元，所述至少一个第二数据单元中每一个第二数据单元中分别包括转发决策参考信息；
    所述数据单元转发决策模块，用于根据所述转发决策参考信息，确定所述至少一个第二数据单元序列流中每一个第二数据单元分别对应的第二逻辑出端口；
    所述数据单元排队缓冲模块，用于将所述每一个第二数据单元缓存在对应的所述第二逻辑出端口的缓存队列中；
    所述第二逻辑出端口，用于发送所述第二数据单元序列流中的第二数据单元。
  19. 根据权利要求11至18中任一项所述的设备，其特征在于，所述速率匹配模块具体用于：
    当所述第一数据单元序列流中包括空闲单元时，增加或减少所述第一数据单元序列流中的空闲单元的数量；
    当所述第一数据单元序列流中不包括空闲单元时，增加所述第一数据单元序列流中的空闲单元的数量。
  20. 根据权利要求11至18中任一项所述的设备，其特征在于，第一数据单元序列流还包括至少一个空闲单元。
PCT/CN2017/080893 2016-05-27 2017-04-18 转发数据的方法和设备 Ceased WO2017202158A1 (zh)

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