WO2018018886A1 - 驱动电路、显示面板、显示设备及驱动方法 - Google Patents

驱动电路、显示面板、显示设备及驱动方法 Download PDF

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Publication number
WO2018018886A1
WO2018018886A1 PCT/CN2017/074394 CN2017074394W WO2018018886A1 WO 2018018886 A1 WO2018018886 A1 WO 2018018886A1 CN 2017074394 W CN2017074394 W CN 2017074394W WO 2018018886 A1 WO2018018886 A1 WO 2018018886A1
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Prior art keywords
transistor
voltage
control signal
display area
sub
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PCT/CN2017/074394
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English (en)
French (fr)
Inventor
马占洁
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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Priority to US15/552,011 priority Critical patent/US10692441B2/en
Priority to EP17751228.2A priority patent/EP3493187B1/en
Publication of WO2018018886A1 publication Critical patent/WO2018018886A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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    • G09G3/03—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes specially adapted for displays having non-planar surfaces, e.g. curved displays
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    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/3433—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using light modulating elements actuated by an electric field and being other than liquid crystal devices and electrochromic devices
    • G09G3/344—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using light modulating elements actuated by an electric field and being other than liquid crystal devices and electrochromic devices based on particles moving in a fluid or in a gas, e.g. electrophoretic devices
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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Definitions

  • Embodiments of the present disclosure relate to a driving circuit, a display panel, a display device, and a driving method.
  • organic light-emitting diode (OLED) display panels have self-illumination, high contrast, thin thickness, wide viewing angle, fast response speed, can be used for flexible panels, wide temperature range, simple manufacturing, etc., and have broad development. prospect.
  • the Gate-Driver on Array (GOA) technology integrates the gate driving circuit directly on the array substrate of the display device by a photolithography process.
  • a GOA circuit typically includes a plurality of cascaded shift registers, each shift register corresponding to a row of gate lines.
  • Embodiments of the present disclosure provide a driving circuit including: a plurality of shift registers; a first switching circuit coupled to the shift register, configured to selectively output the according to a first control signal and a second control signal An output signal or a first voltage of the shift register; and a second switching circuit coupled to the shift register, configured to selectively output an output signal of the shift register according to the third control signal and the fourth control signal The first voltage.
  • the first switching circuit includes: a first control sub-circuit configured to selectively output the first according to the first control signal and the second control signal a voltage or a second voltage to the first node; a plurality of first switch sub-circuits configured to selectively output the shift register to the first display screen according to the first control signal and the voltage of the first node An output signal or the first voltage, the second switching circuit comprising: a second control sub-circuit configured to selectively output the first voltage or according to the third control signal and the fourth control signal The second voltage to the second node; the plurality of second switch sub-circuits configured to selectively output the shift register to the second display screen according to the fourth control signal and the voltage of the second node Outputting the signal or the first voltage.
  • the first control sub-circuit includes a transistor and a second transistor, each of the first switch sub-circuits comprising a fifth transistor and a sixth transistor, the second control sub-circuit comprising a third transistor and a fourth transistor, each of the second switch sub-circuits
  • the seventh transistor and the eighth transistor are included.
  • the first pole of the first transistor is connected to the first voltage terminal to receive the first voltage, and the gate of the first transistor and the first control signal end Connected to receive the first control signal, a second pole of the first transistor is coupled to the first node; a first pole of the second transistor is coupled to the first node, the second transistor a gate is coupled to the second control signal terminal for receiving the second control signal, a second pole of the second transistor is coupled to the second voltage terminal for receiving the second voltage; and a first pole of the third transistor Connected to the second node, a gate of the third transistor is connected to a third control signal terminal for receiving the third control signal, and a second pole of the third transistor is connected to the second voltage terminal Receiving the second voltage; a first pole of the fourth transistor is connected to the first voltage terminal to receive the first voltage, and a gate of the fourth transistor is connected to a fourth control signal end for receiving Four control a second pole of the fourth transistor is coupled to the second node;
  • a plurality of the first switch sub-circuits, a plurality of the second switch sub-circuits, and a plurality of the shift registers are in one-to-one correspondence.
  • the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the The seventh transistor and the eighth transistor are both P-type transistors.
  • the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth crystal are all thin film transistors.
  • Embodiments of the present disclosure also provide a display panel including the driving circuit of any of the embodiments of the present disclosure.
  • the display panel provided by the embodiment of the present disclosure further includes a first display area and a second display area, wherein the first switch circuit is configured to be based on the first control signal and the second control signal An output signal or a first voltage of the shift register is selectively outputted to the first display area, and the second switch circuit is configured to output an output signal of the shift register according to the third control signal and the fourth control signal Or the first voltage is selectively output to the second display area.
  • the display panel provided by the embodiment of the present disclosure further includes a flexible circuit board, wherein the flexible circuit board is disposed between the first display area and the second display area, and the driving circuit is disposed at the On the flexible circuit board.
  • the display panel provided by the embodiment of the present disclosure is a foldable display panel that can be folded from a position between the first display area and the second display area.
  • the display panel provided by the embodiment of the present disclosure further includes a plurality of sub-pixel units, wherein a portion of the sub-pixel unit has a light emitting area overlapping the driving circuit.
  • the light emitting regions of the plurality of sub-pixel units cover the driving circuit.
  • the plurality of sub-pixel units include a first sub-pixel unit and a second sub-pixel unit, and a size of a light-emitting area of the first sub-pixel unit is larger than the second sub-pixel The size of the light emitting area of the pixel unit.
  • a portion of the light emitting area of the first sub-pixel unit overlaps with the driving circuit.
  • An embodiment of the present disclosure further provides a display device including the display panel of any of the embodiments of the present disclosure.
  • the display device provided by the embodiment of the present disclosure further includes a full screen control switch, a first display area control switch, and a second display area control switch, wherein the full screen control switch is used to simultaneously turn on or off the first display area.
  • the second display area, the first display area control switch is used to separately turn on or off the first display area, and the second display area control switch is used to separately turn on or off the second display area.
  • Embodiments of the present disclosure also provide a method of driving a driving circuit according to any of the embodiments of the present disclosure.
  • the method includes: when the first display area and the second display area are simultaneously displayed, setting the first control signal to a shutdown voltage, setting the second control signal to an on voltage, and setting the third control signal to an on voltage Setting the fourth control signal to be a shutdown voltage; when the first display area is separately displayed, setting the first control signal to a shutdown voltage, setting the second control signal to an on voltage, and setting the third control signal
  • the fourth control signal is set to be an on voltage when the voltage is turned off; when the second display area is separately displayed, the first control signal is set to be an on voltage, and the second control signal is set to be a shutdown voltage, and the The third control signal is an on voltage, and the fourth control signal is set to be a shutdown voltage.
  • FIG. 1 is a schematic diagram of a driving circuit according to an embodiment of the present disclosure
  • FIG. 2 is a second schematic diagram of a driving circuit according to an embodiment of the present disclosure
  • FIG. 3 is a third schematic diagram of a driving circuit according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of a shift register provided by an embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram of a display panel according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of a sub-pixel unit in a display panel according to an embodiment of the present disclosure
  • FIG. 7 is a second schematic diagram of a display panel according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of a display device according to an embodiment of the present disclosure.
  • the shift register is separately configured for the two display screens
  • the two screens when the two screens are reversely folded, if only one screen is normally displayed, the other screen needs to be displayed in a pure black screen.
  • the state that is, still in working state, leads to an increase in the overall panel power consumption, and there is a certain waste.
  • Embodiments of the present disclosure provide a driving circuit, a display panel, a display device, and a driving method.
  • a set of shift registers can be used to drive two display areas simultaneously or separately, saving shift registers, realizing independent operation of the display area, reducing power consumption, and saving power.
  • the driving circuit 10 includes: a plurality of shift registers 110 (eg, M shift registers 110), and a first connection to the shift register 110
  • the switch circuit 120 and the second switch circuit 130 connected to the shift register 110.
  • the first switch circuit 120 is configured to selectively output the output signal OUTPUT of the shift register 110 according to the first control signal SW1 and the second control signal SW2 (eg, the output signal OUTPUT of the shift register includes OUTPUT1, OUTPUT2, ..., OUTPUTM Or the first voltage VGH;
  • the second switching circuit 130 is configured to selectively output the output signal OUTPUT of the shift register or the first voltage VGH according to the third control signal SW3 and the fourth control signal SW4.
  • the first voltage VGH in the embodiment of the present disclosure is, for example, a high voltage (for example, 5 V), and the second voltage VGL is, for example, a low voltage (for example, 0 V).
  • the first switching circuit 120 includes: a first control sub-circuit 121 and a plurality of first switch sub-circuits 122.
  • the first control sub-circuit 121 is configured to selectively output the first voltage VGH or the second voltage VGL to the first node N1 according to the first control signal SW1 and the second control signal SW2;
  • the first switch sub-circuit 122 is configured according to the first A control signal SW1 and a voltage of the first node N1 selectively output an output signal OUTPUT or a first voltage VGH of the shift register 110 to a first display screen (not shown in FIG. 2).
  • the second switch circuit 130 includes a second control sub-circuit 131 and a plurality of second switch sub-circuits 132.
  • the second control sub-circuit 131 is configured to be based on the third control signal SW3 and the fourth control signal SW4 Selectively outputting the first voltage VGH or the second voltage VGL to the second node N2;
  • the second switch sub-circuit 132 is configured to be directed to the second display screen according to the voltages of the fourth control signal SW4 and the second node N2 (not shown in FIG. 2
  • the output signal OUTPUT or the first voltage VGH of the shift register 110 is selectively outputted.
  • the first control sub-circuit 121 includes a first transistor T1 and a second transistor T2, and each of the first switching sub-circuits 122 includes a fifth transistor T5.
  • the sixth transistor T6 the second control sub-circuit 131 includes a third transistor T3 and a fourth transistor T4, and each of the second switching sub-circuits 132 includes a seventh transistor T7 and an eighth transistor T8.
  • the first electrode of the first transistor T1 is connected to the first voltage terminal to receive the first voltage VGH, and the gate and the first transistor T1 are connected.
  • a control signal terminal is connected to receive the first control signal SW1, a second pole of the first transistor T1 is connected to the first node N1; a first pole of the second transistor T2 is connected to the first node N1, and a gate of the second transistor T2 Connected with the second control signal terminal to receive the second control signal SW2, the second pole of the second transistor T2 is connected to the second voltage terminal to receive the second voltage VGL; the first pole of the third transistor T3 is connected to the second node N2
  • the third transistor T3 has a gate connected to the third control signal terminal for receiving the third control signal SW3, the second transistor of the third transistor T3 is connected to the second voltage terminal for receiving the second voltage VGL, and the fourth transistor T4 is One pole is connected to the first voltage terminal to receive the first voltage VGH, the gate
  • the driving circuit shown in FIG. 3 is a kind of the driving circuit shown in FIG. 1 or FIG.
  • the implementation of the present disclosure includes, but is not limited to, the implementation of the driving circuit shown in FIG. 3, and the changes made to the driving circuit shown in FIG. 3 can be made by those skilled in the art without creative efforts. It should be within the scope of protection of the present disclosure.
  • the plurality of first switching sub-circuits 122, the plurality of second switching sub-circuits 132, and the plurality of shift registers 110 are in one-to-one correspondence.
  • the first switch sub-circuit, the second switch sub-circuit, and the shift register of the first row are in one-to-one correspondence.
  • the fifth transistor or the sixth transistor in the switch sub-circuit of the first row is turned on, and outputs the first voltage VGH or the output signal OUTPUT1 of the shift register of the first row; in the second switch sub-circuit of the first row
  • the seventh transistor or the eighth transistor is turned on to output the first voltage VGH or the output signal OUTPUT1 of the shift register of the first row.
  • the other lines are similar to the first line and will not be described here.
  • the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the The eight transistors T8 are all P-type transistors.
  • the transistor T8 is a thin film transistor.
  • the shift register 110 includes an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, The first capacitor C1, the second capacitor C2, and the third capacitor C3.
  • the first pole of the ninth transistor T9 is connected to the second voltage terminal to receive the second voltage VGL
  • the gate of the ninth transistor T9 is connected to the first clock signal terminal for receiving the first clock signal CLK1
  • the second of the ninth transistor T9 The pole is connected to the third node N3.
  • the first pole of the tenth transistor T10 is connected to the third node N3, the gate of the tenth transistor T10 is connected to the second clock signal terminal to receive the second clock signal CLK2, and the second pole and the fourth node N4 of the tenth transistor T10 connection.
  • the first pole of the eleventh transistor T11 is connected to the third node, the gate of the eleventh transistor T11 is connected to the fifth node, and the second pole of the eleventh transistor T11 is connected to the first clock signal terminal to receive the first clock. Signal CLK1.
  • the first pole of the twelfth transistor T12 is connected to the output control signal terminal to receive the output control signal STV, and the gate of the twelfth transistor T12 is connected to the first clock signal terminal for receiving the first The clock signal CLK1, the second pole of the twelfth transistor T12 is connected to the fifth node N5.
  • the first pole of the thirteenth transistor T13 is connected to the seventh node N7, the seventh node N7 is connected to the first voltage terminal to receive the first voltage VGH, and the gate of the thirteenth transistor T13 is connected to the fifth node N5, tenth
  • the second pole of the three transistor T13 is connected to the fourth node N4.
  • the first pole of the fourteenth transistor T14 is connected to the seventh node N7, the gate of the fourteenth transistor T14 is connected to the fourth node N4, and the second pole of the fourteenth transistor T14 is connected to the sixth node N6, the sixth node Used to output the output signal OUTPUT1 of the shift register.
  • the first pole of the fifteenth transistor T15 is connected to the sixth node N6, the gate of the fifteenth transistor T15 is connected to the fifth node N5, and the second pole of the fifteenth transistor T15 is connected to the second voltage terminal for receiving the second Voltage VGL.
  • the first end of the first capacitor C1 is connected to the third node N3, and the second end of the first capacitor C1 is connected to the second clock signal end to receive the second clock signal CLK2.
  • the first end of the second capacitor C2 is connected to the seventh node N7, and the second end of the second capacitor C2 is connected to the fourth node N4.
  • the first end of the third capacitor C3 is connected to the sixth node N6, and the second end of the third capacitor is connected to the fifth node N5.
  • the shift register 110 shown in FIG. 4 is only one example in the embodiment of the present disclosure, and embodiments of the present disclosure include, but are not limited to, the shift register shown in FIG. 4, and may also be other shift registers. .
  • the capacitor used in the embodiment of the present disclosure includes a first end and a second end, and the first end and the second end of the capacitor are symmetric, for example, so the first capacitor, the second capacitor, and the third capacitor are Both the end and the second end are interchangeable.
  • the transistors used in the embodiments of the present disclosure may each be a thin film transistor or a field effect transistor or other switching devices having the same characteristics.
  • the source and drain of the transistor used here may be structurally symmetrical, so that the source and the drain may be structurally indistinguishable.
  • the transistors in order to distinguish the two poles of the transistor except the gate, one of the first poles and the other pole are directly described, so the first pole of all or part of the transistors in the embodiment of the present disclosure The second pole is interchangeable as needed.
  • the transistors can be divided into N-type and P-type transistors according to the characteristics of the transistors. Embodiments of the present disclosure are described by taking a P-type transistor as an example.
  • An embodiment of the present disclosure further provides a display panel 20, as shown in FIG.
  • the drive circuit 10 provided by any of the embodiments of the present disclosure is included.
  • the display panel 20 may be an organic light emitting diode display (OLED) panel, or may be a liquid crystal display panel (LD), an electronic ink display panel, or the like.
  • the display panel 20 provided by the embodiment of the present disclosure further includes a first display area 210 and a second display area 220.
  • the first switch circuit 120 is configured to output the output signal OUTPUT of the shift register 110 according to the first control signal SW1 and the second control signal SW2 (eg, the output signal OUTPUT of the shift register includes OUTPUT1, OUTPUT2, ..., OUTPUTM) or
  • the first voltage VGH is selectively output to the first display area 210;
  • the second switch circuit 130 is configured to selectively output the output signal OUTPUT or the first voltage VGH of the shift register 110 according to the third control signal SW3 and the fourth control signal SW4.
  • the output is to the second display area 220.
  • the display panel 20 provided by the embodiment of the present disclosure further includes a flexible circuit board 230 disposed between the first display area 210 and the second display area 220, and the driving circuit 10 is disposed on the flexible circuit board 230.
  • the display panel 20 provided by the embodiment of the present disclosure is a foldable display panel that can be folded from a position between the first display area 210 and the second display area 220.
  • the first display area 210 and the second display area 220 may be folded to form a certain angle between each other, or both may be completely overlapped and the display faces of both may face outward.
  • the display panel 20 provided by the embodiment of the present disclosure further includes a plurality of sub-pixel units 240.
  • the sub-pixel unit 240 includes an emission control transistor ET, an organic light emitting diode OLED, and a drive control circuit 243.
  • the drive control circuit 243 is for driving the OLED to emit light according to the illuminating data signal.
  • the first end of the drive control circuit 243 is connected to the first drive power terminal to receive the first drive power voltage VDD, and the second end of the drive control circuit 243 is connected to the first pole of the light emission control transistor ET.
  • the gate of the illuminating control transistor ET is for receiving the output signal OUTPUT or the first voltage VGH of the shift register 110 selectively output by the driving circuit 10, and the second pole of the illuminating control transistor ET and the first pole of the OLED (for example, the anode) connection.
  • a second pole (eg, a cathode) of the OLED is coupled to the second drive power source to receive the second drive power voltage VSS.
  • the drive control circuit 243 and the light emission control transistor ET of the plurality of sub-pixel units 240 are disposed in the first display area 210 and the second display area 220.
  • the sub-pixel unit 240 includes a light emitting region (for example, an OLED)
  • the light emitting region overlaps with the driving circuit 10.
  • the light emitting regions of the plurality of sub-pixel units 240 cover the driving circuit 10 .
  • the plurality of sub-pixel units 240 include a first sub-pixel unit 241 and a second sub-pixel unit 242 .
  • the light emitting region of the first sub-pixel unit 241 includes the light emitting region 241A of the red pixel unit, the light emitting region 241B of the green pixel unit, and the light emitting region 241C of the blue pixel unit;
  • the light emitting region of the second sub-pixel unit 242 includes the light emitting of the red pixel unit A region 242A, a light emitting region 242B of the green pixel unit, and a light emitting region 242C of the blue pixel unit.
  • the size of the light emitting area of the first sub-pixel unit 241 is larger than the size of the light emitting area of the second sub-pixel unit 242.
  • a portion of the light emitting area of the first sub-pixel unit 241 overlaps with the driving circuit 10.
  • the lateral length d occupied by the driving circuit 10 is 300 ⁇ m
  • the first display area and the second display area each occupy a lateral length of 150 ⁇ m
  • the lateral length of the light-emitting area of one first sub-pixel unit is 100 ⁇ m.
  • the lateral length of the light-emitting area of one second sub-pixel unit is 50 ⁇ m
  • three first sub-pixel units are respectively disposed in portions of the first display area and the second display area adjacent to the driving circuit 10, so that the first sub- The pixel unit covers the drive circuit 10. Taking the first row of sub-pixels of the second display area as an example, as shown in FIG.
  • An embodiment of the present disclosure also provides a display device 1, which, as shown in FIG. 8, includes a display panel 20 of any of the embodiments of the present disclosure.
  • the display device 1 provided by the embodiment of the present disclosure may further include a full screen control switch 31, a first display area control switch 32 and a second display area control switch 33 for simultaneously turning on or off the first display area 210.
  • the second display area 220, the first display area control switch 32 is used to individually open or close the first display area 210, and the second display area control switch 33 is used to individually turn on or off the second display area 220.
  • the full screen control switch 31, the first display area control switch 32, and the second display area control switch 33 can be realized by setting the first control signal SW1, the second control signal SW2, the third control signal SW3, and the fourth control signal SW4.
  • the positions and shapes of the full-screen control switch 31, the first display area control switch 32, and the second display area control switch 33 are not limited to the case shown in FIG. 8, and may be other shapes or other settings on the display panel. position.
  • the display device 1 can be folded along the folding rotation axis 34.
  • the first display area and the second display area can be spliced into one display area; when the first display is needed
  • the display device 1 can be folded along the folding rotation axis 34, reducing the occupied area of the display device 1 and improving the user experience.
  • the full screen control switch 31 can be formed on one side of a display area on the display device 1 and simultaneously connected to two display areas.
  • the display device 1 further includes other components such as a power switch (not shown in FIG. 8).
  • An embodiment of the present disclosure further provides a method for driving a driving circuit of any of the embodiments of the present disclosure, including: when the first display area and the second display area are simultaneously displayed, setting the first control signal SW1 to a shutdown voltage, and setting a second
  • the control signal SW2 is an on voltage
  • the third control signal SW3 is set to be an on voltage
  • the fourth control signal SW4 is set to be a shutdown voltage
  • the second control is set.
  • the signal SW2 is an on voltage
  • the third control signal SW3 is set to be a shutdown voltage
  • the fourth control signal SW4 is set to be an on voltage
  • the second control signal is set.
  • SW2 is a turn-off voltage
  • a third control signal SW3 is set to be an on voltage
  • a fourth control signal SW4 is set to be a turn-off voltage.
  • the turn-on voltage refers to a voltage that can be turned on between the first pole and the second pole of the transistor when loaded on the gate of the transistor, and the turn-off voltage means that the transistor can be first applied when being loaded on the gate of the transistor.
  • the turn-on voltage is, for example, a low voltage (for example, 0 V)
  • the turn-off voltage is, for example, a high voltage (for example, 5 V)
  • the turn-on voltage is, for example, a high voltage (for example, 5 V)
  • the voltage is turned off.
  • it is a low voltage (for example, 0V).
  • the embodiment of the present disclosure is described by taking a P-type transistor as an example.
  • the first control signal SW1 is set to a high voltage
  • the second control signal SW2 is set to a low voltage
  • the third control signal SW3 is set.
  • the fourth control signal SW4 is set to a high voltage.
  • the first transistor T1, the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7 are all turned off, and the second transistor T2 and the third transistor T3 are turned on.
  • the voltages of the first node N1 and the second node N2 are the second voltage VGL (the second voltage VGL is, for example, a low voltage), the low voltage of the first node N1 turns on the sixth transistor T6, and the low voltage of the second node N2
  • the eighth transistor T8 is turned on all.
  • the output signal OUTPUT of the shift register 110 eg, the output signal OUTPUT of the shift register includes OUTPUT1, OUTPUT2, . . . , OUTPUTM
  • the output signal OUTPUT of the shift register 110 includes, but is not limited to, a gate transmitted to the light-emission control transistor ET, a control signal for controlling the light-emitting function, or a scan signal for controlling data writing or a control reset. Other signals such as the function of the scan signal.
  • the second display area When the first display area is displayed separately, the second display area is in a shutdown or sleep state.
  • the first control signal SW1 is set to a high voltage
  • the second control signal SW2 is set to a low voltage
  • the third control signal SW3 is set to a high voltage
  • the fourth control signal SW4 is set to a low voltage.
  • the first transistor T1 and the fifth transistor T5 are turned off, and the second transistor T2 is turned on.
  • the voltage of the first node N1 is the second voltage VGL (the second voltage VGL is, for example, a low voltage), and the low voltage of the first node N1 turns on the sixth transistor T6.
  • the output signal OUTPUT of the shift register 110 (for example, the output signal OUTPUT of the shift register includes OUTPUT1, OUTPUT2, ..., OUTPUTM) is transmitted to the first display area 210.
  • the third transistor T3 is turned off, the fourth transistor T4 and the seventh transistor T7 are turned on, the voltage of the second node N2 is the first voltage VGH (the first voltage VGH is, for example, a high voltage), and the high voltage of the second node N2 is the eighth
  • the transistor T8 is all turned off, and the first voltage VGH is transmitted to the second display region 220 through the seventh transistor T7 (for example, to the gate of the light emission control transistor ET in the second display region 220).
  • the second display area is turned off or in a sleep state, thereby saving power.
  • the first display area is in a shutdown or sleep state.
  • the first control signal SW1 is set to a low voltage
  • the second control signal SW2 is set to a high voltage
  • the third control signal SW3 is set to a low voltage
  • the fourth control signal SW4 is set to a high voltage.
  • the fourth transistor T4 and the seventh transistor T7 are turned off, and the third transistor T3 is turned on.
  • the voltage of the second node N2 is the second voltage VGL (the second voltage VGL is, for example, a low voltage), and the low voltage of the second node N2 turns on the eighth transistor T8.
  • the output signal OUTPUT of the shift register 110 (for example, the output signal OUTPUT of the shift register includes OUTPUT1, OUTPUT2, ..., OUTPUTM) is transmitted to The second display area 220.
  • the second transistor T2 is turned off, the first transistor T1 and the fifth transistor T5 are turned on, the voltage of the first node N1 is the first voltage VGH (the first voltage VGH is, for example, a high voltage), and the high voltage of the first node N1 makes the sixth
  • the transistor T6 is all turned off, and the first voltage VGH is transmitted to the first display region 210 through the fifth transistor T5 (for example, to the gate of the light emission control transistor ET in the first display region 210).
  • the first display area is turned off or in a sleep state, thereby saving power.
  • a driving circuit, a display panel, a display device, and a driving method are provided by embodiments of the present disclosure.
  • a set of shift registers can drive two display areas simultaneously or separately, which can save shift registers, realize independent operation of the display area, and can also reduce power consumption and save power.

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Abstract

一种驱动电路(10)、显示面板(20)、显示设备(1)及驱动方法。该驱动电路(10)包括：多个移位寄存器(110)；与所述移位寄存器(110)连接的第一开关电路(120)，被配置为根据第一控制信号(SW1)和第二控制信号(SW2)选择性输出所述移位寄存器(110)的输出信号(OUTPUT)或第一电压(VGH)；以及与所述移位寄存器(110)连接的第二开关电路(130)，被配置为根据第三控制信号(SW3)和第四控制信号(SW4)选择性输出所述移位寄存器(110)的输出信号(OUTPUT)或所述第一电压(VGH)。一组移位寄存器(110)可同时或分别驱动两个显示区，这可以节省移位寄存器(110)，实现显示区的独立工作，并且降低功耗，节省电能。

Description

驱动电路、显示面板、显示设备及驱动方法 技术领域
本公开的实施例涉及一种驱动电路、显示面板、显示设备及驱动方法。
背景技术
在显示领域，有机发光二极管(OLED)显示面板具有自发光、对比度高、厚度薄、视角广、反应速度快、可用于挠曲性面板、使用温度范围广、制造简单等特点，具有广阔的发展前景。
栅极驱动电路基板(Gate-driver on Array，GOA)技术是通过光刻工艺将栅极驱动电路直接集成在显示装置的阵列基板上。GOA电路通常包括多个级联的移位寄存器，每个移位寄存器均对应一行栅线。
发明内容
本公开的实施例提供一种驱动电路，包括：多个移位寄存器；与所述移位寄存器连接的第一开关电路，被配置为根据第一控制信号和第二控制信号选择性输出所述移位寄存器的输出信号或第一电压；以及与所述移位寄存器连接的第二开关电路，被配置为根据第三控制信号和第四控制信号选择性输出所述移位寄存器的输出信号或所述第一电压。
例如，在本公开实施例提供的驱动电路中，所述第一开关电路包括：第一控制子电路，被配置为根据所述第一控制信号和所述第二控制信号选择性输出所述第一电压或第二电压到第一节点；多个第一开关子电路，被配置为根据所述第一控制信号和所述第一节点的电压向第一显示屏选择性输出所述移位寄存器的输出信号或所述第一电压，所述第二开关电路包括：第二控制子电路，被配置为根据所述第三控制信号和所述第四控制信号选择性输出所述第一电压或所述第二电压到第二节点；多个第二开关子电路，被配置为根据所述第四控制信号和所述第二节点的电压向第二显示屏选择性输出所述移位寄存器的输出信号或所述第一电压。
例如，在本公开实施例提供的驱动电路中，所述第一控制子电路包括第 一晶体管和第二晶体管，每个所述第一开关子电路包括第五晶体管和第六晶体管，所述第二控制子电路包括第三晶体管和第四晶体管，每个所述第二开关子电路包括第七晶体管和第八晶体管。
例如，在本公开实施例提供的驱动电路中，所述第一晶体管的第一极与第一电压端连接以便接收所述第一电压，所述第一晶体管的栅极与第一控制信号端连接以便接收所述第一控制信号，所述第一晶体管的第二极与所述第一节点连接；所述第二晶体管的第一极与所述第一节点连接，所述第二晶体管的栅极与第二控制信号端连接以便接收所述第二控制信号，所述第二晶体管的第二极与第二电压端连接以便接收所述第二电压；所述第三晶体管的第一极与所述第二节点连接，所述第三晶体管的栅极与第三控制信号端连接以便接收所述第三控制信号，所述第三晶体管的第二极与所述第二电压端连接以便接收所述第二电压；所述第四晶体管的第一极与所述第一电压端连接以便接收所述第一电压，所述第四晶体管的栅极与第四控制信号端连接以便接收第四控制信号，所述第四晶体管的第二极与所述第二节点连接；所述第五晶体管的第一极与所述第一电压端连接以便接收所述第一电压，所述第五晶体管的栅极与所述第一控制信号端连接以便接收所述第一控制信号，所述第五晶体管的第二极与所述第六晶体管的第二极连接；所述第六晶体管的第一极与所述移位寄存器连接以便接收所述移位寄存器的输出信号，所述第六晶体管的栅极与所述第一节点连接；所述第七晶体管的第一极与所述第一电压端连接以便接收所述第一电压，所述第七晶体管的栅极与所述第四控制信号端连接以便接收所述第四控制信号，所述第七晶体管的第二极与所述第八晶体管的第二极连接；所述第八晶体管的第一极与所述移位寄存器连接以便接收所述移位寄存器的输出信号，所述第八晶体管的栅极与所述第二节点连接。
例如，在本公开实施例提供的驱动电路中，多个所述第一开关子电路、多个所述第二开关子电路和多个所述移位寄存器一一对应。
例如，在本公开实施例提供的驱动电路中，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管、所述第七晶体管和所述第八晶体管均为P型晶体管。
例如，在本公开实施例提供的驱动电路中，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶 体管、所述第七晶体管和所述第八晶体管均为薄膜晶体管。
本公开的实施例还提供一种显示面板，包括本公开任一实施例所述的驱动电路。
例如，本公开实施例提供的显示面板，还包括第一显示区和第二显示区，其中，所述第一开关电路被配置为根据所述第一控制信号和所述第二控制信号将所述移位寄存器的输出信号或第一电压选择性输出到所述第一显示区，所述第二开关电路被配置为根据第三控制信号和第四控制信号将所述移位寄存器的输出信号或所述第一电压选择性输出到所述第二显示区。
例如，本公开实施例提供的显示面板，还包括柔性电路板，其中，所述柔性电路板设置在所述第一显示区和所述第二显示区之间，所述驱动电路设置在所述柔性电路板上。
例如，本公开实施例提供的显示面板为可折叠显示面板，可从所述第一显示区和所述第二显示区之间的位置被折叠。
例如，本公开实施例提供的显示面板，还包括多个子像素单元，其中，部分所述子像素单元的发光区域与所述驱动电路交叠。
例如，在本公开实施例提供的显示面板中，所述多个子像素单元的发光区域覆盖所述驱动电路。
例如，在本公开实施例提供的显示面板中，所述多个子像素单元包括第一子像素单元和第二子像素单元，所述第一子像素单元的发光区域的尺寸大于所述第二子像素单元的发光区域的尺寸。
例如，在本公开实施例提供的显示面板中，部分所述第一子像素单元的发光区域与所述驱动电路交叠。
本公开的实施例还提供一种显示设备，包括本公开任一实施例所述的显示面板。
例如，本公开实施例提供的显示设备，还包括全屏控制开关、第一显示区控制开关和第二显示区控制开关，其中，所述全屏控制开关用于同时开启或关闭所述第一显示区和所述第二显示区，所述第一显示区控制开关用于单独开启或关闭所述第一显示区，所述第二显示区控制开关用于单独开启或关闭所述第二显示区。
本公开的实施例还提供一种驱动本公开任一实施例所述驱动电路的方 法，包括：当第一显示区和第二显示区同时显示时，设置所述第一控制信号为关闭电压，设置所述第二控制信号为开启电压，设置所述第三控制信号为开启电压，设置所述第四控制信号为关闭电压；当第一显示区单独显示时，设置所述第一控制信号为关闭电压，设置所述第二控制信号为开启电压，设置所述第三控制信号为关闭电压，设置所述第四控制信号为开启电压；当第二显示区单独显示时，设置所述第一控制信号为开启电压，设置所述第二控制信号为关闭电压，设置所述第三控制信号为开启电压，设置所述第四控制信号为关闭电压。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，并非对本公开的限制。
图1是本公开实施例提供的一种驱动电路的示意图之一；
图2是本公开实施例提供的一种驱动电路的示意图之二；
图3是本公开实施例提供的一种驱动电路的示意图之三；
图4是本公开实施例提供的一种移位寄存器的示意图；
图5是本公开实施例提供的一种显示面板的示意图之一；
图6是本公开实施例提供的一种显示面板中子像素单元的示意图；
图7是本公开实施例提供的一种显示面板的示意图之二；以及
图8是本公开实施例提供的一种显示设备的示意图。
具体实施方式
下面将结合附图，对本公开实施例中的技术方案进行清楚、完整地描述参考在附图中示出并在以下描述中详述的非限制性示例实施例，更加全面地说明本公开的示例实施例和它们的多种特征及有利细节。应注意的是，图中示出的特征不是必须按照比例绘制。本公开省略了已知材料、组件和工艺技术的描述，从而不使本公开的示例实施例模糊。所给出的示例仅旨在有利于理解本公开示例实施例的实施，以及进一步使本领域技术人员能够实施示例实施例。因而，这些示例不应被理解为对本公开的实施例的范围的限制。
除非另外特别定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。此外，在本公开各个实施例中，相同或类似的参考标号表示相同或类似的构件。
在折叠显示设备中，在对两个显示屏分别配置移位寄存器的情形，当将两个屏进行反向折叠后，如果只需一个屏正常显示，则需要将另外一个屏处于显示纯黑画面的状态，也即仍然处于工作状态，导致整体面板功耗增加，存在一定的浪费。
本公开的实施例提供一种驱动电路、显示面板、显示设备和驱动方法。可以使用一组移位寄存器可同时或分别驱动两个显示区，节省移位寄存器，实现显示区的独立工作，降低了功耗，节省了电能。
本公开的实施例提供一种驱动电路10，如图1所示，该驱动电路10包括：多个移位寄存器110(例如，M个移位寄存器110)、与移位寄存器110连接的第一开关电路120以及与移位寄存器110连接的第二开关电路130。第一开关电路120被配置为根据第一控制信号SW1和第二控制信号SW2选择性输出移位寄存器110的输出信号OUTPUT(例如，移位寄存器的输出信号OUTPUT包括OUTPUT1，OUTPUT2，……，OUTPUTM)或第一电压VGH；第二开关电路130被配置为根据第三控制信号SW3和第四控制信号SW4选择性输出移位寄存器的输出信号OUTPUT或第一电压VGH。
例如，本公开实施例中的第一电压VGH例如为高电压(例如，5V)，第二电压VGL例如为低电压(例如，0V)。
例如，如图2所示，在本公开实施例提供的驱动电路10中，第一开关电路120包括：第一控制子电路121和多个第一开关子电路122。第一控制子电路121被配置为根据第一控制信号SW1和第二控制信号SW2选择性输出第一电压VGH或第二电压VGL到第一节点N1；第一开关子电路122被配置为根据第一控制信号SW1和第一节点N1的电压向第一显示屏(图2中未示出)选择性输出移位寄存器110的输出信号OUTPUT或第一电压VGH。第二开关电路130包括：第二控制子电路131和多个第二开关子电路132。第二控制子电路131被配置为根据第三控制信号SW3和第四控制信号SW4 选择性输出第一电压VGH或第二电压VGL到第二节点N2；第二开关子电路132被配置为根据第四控制信号SW4和第二节点N2的电压向第二显示屏(图2中未示出)选择性输出移位寄存器110的输出信号OUTPUT或第一电压VGH。
例如，如图3所示，在本公开实施例提供的驱动电路10中，第一控制子电路121包括第一晶体管T1和第二晶体管T2，每个第一开关子电路122包括第五晶体管T5和第六晶体管T6，第二控制子电路131包括第三晶体管T3和第四晶体管T4，每个第二开关子电路132包括第七晶体管T7和第八晶体管T8。
例如，如图3所示，在本公开实施例提供的驱动电路10中，第一晶体管T1的第一极与第一电压端连接以便接收第一电压VGH，第一晶体管T1的栅极与第一控制信号端连接以便接收第一控制信号SW1，第一晶体管T1的第二极与第一节点N1连接；第二晶体管T2的第一极与第一节点N1连接，第二晶体管T2的栅极与第二控制信号端连接以便接收第二控制信号SW2，第二晶体管T2的第二极与第二电压端连接以便接收第二电压VGL；第三晶体管T3的第一极与第二节点N2连接，第三晶体管T3的栅极与第三控制信号端连接以便接收第三控制信号SW3，第三晶体管T3的第二极与第二电压端连接以便接收第二电压VGL；第四晶体管T4的第一极与第一电压端连接以便接收第一电压VGH，第四晶体管T4的栅极与第四控制信号端连接以便接收第四控制信号SW4，第四晶体管T4的第二极与第二节点N2连接；第五晶体管T5的第一极与第一电压端连接以便接收第一电压VGH，第五晶体管T5的栅极与第一控制信号端连接以便接收第一控制信号SW1，第五晶体管T5的第二极与第六晶体管T6的第二极连接；第六晶体管T6的第一极与移位寄存器110连接以便接收移位寄存器110的输出信号，第六晶体管T6的栅极与第一节点N1连接；第七晶体管T7的第一极与第一电压端连接以便接收第一电压VGH，第七晶体管T7的栅极与第四控制信号端连接以便接收第四控制信号SW4，第七晶体管T7的第二极与第八晶体管T8的第二极连接；第八晶体管T8的第一极与移位寄存器110连接以便接收移位寄存器110的输出信号，第八晶体管T8的栅极与第二节点N2连接。
需要说明的是，图3所示的驱动电路是图1或图2所示驱动电路的一种 具体实现方式，本公开的实施例包括但不局限于图3所示驱动电路的实现方式，本领域技术人员在没有做出创造性劳动前提下可对图3所示的驱动电路做出的改变均应在本公开的保护范围内。
例如，在本公开实施例提供的驱动电路10中，多个第一开关子电路122、多个第二开关子电路132和多个移位寄存器110一一对应。例如，以第一行为例，第一行的第一开关子电路、第二开关子电路和移位寄存器一一对应。也就是说，第一行的开关子电路中的第五晶体管或第六晶体管开启，输出第一电压VGH或第一行的移位寄存器的输出信号OUTPUT1；第一行的第二开关子电路中的第七晶体管或第八晶体管开启，输出第一电压VGH或第一行的移位寄存器的输出信号OUTPUT1。其它行的情况与第一行类似，在此不再赘述。
例如，在本公开实施例提供的驱动电路10中，第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7和第八晶体管T8均为P型晶体管。
例如，在本公开实施例提供的驱动电路中，第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7和第八晶体管T8均为薄膜晶体管。
例如，移位寄存器的一个示例如图4所示，以第一行的移位寄存器为例进行说明。移位寄存器110包括第八晶体管T8、第九晶体管T9、第十晶体管T10、第十一晶体管T11、第十二晶体管T12、第十三晶体管T13、第十四晶体管T14、第十五晶体管T15、第一电容C1、第二电容C2和第三电容C3。第九晶体管T9的第一极与第二电压端连接以便接收第二电压VGL，第九晶体管T9的栅极与第一时钟信号端连接以便接收第一时钟信号CLK1，第九晶体管T9的第二极与第三节点N3连接。第十晶体管T10的第一极与第三节点N3连接，第十晶体管T10的栅极与第二时钟信号端连接以便接收第二时钟信号CLK2，第十晶体管T10的第二极与第四节点N4连接。第十一晶体管T11的第一极与第三节点连接，第十一晶体管T11的栅极与第五节点连接，第十一晶体管T11的第二极与第一时钟信号端连接以便接收第一时钟信号CLK1。第十二晶体管T12的第一极与输出控制信号端连接以便接收输出控制信号STV，第十二晶体管T12的栅极与第一时钟信号端连接以便接收第一 时钟信号CLK1，第十二晶体管T12的第二极与第五节点N5连接。第十三晶体管T13的第一极与第七节点N7连接，第七节点N7与第一电压端连接以便接收第一电压VGH，第十三晶体管T13的栅极与第五节点N5连接，第十三晶体管T13的第二极与第四节点N4连接。第十四晶体管T14的第一极与第七节点N7连接，第十四晶体管T14的栅极与第四节点N4连接，第十四晶体管T14的第二极与第六节点N6连接，第六节点用于输出该移位寄存器的输出信号OUTPUT1。第十五晶体管T15的第一极与第六节点N6连接，第十五晶体管T15的栅极与第五节点N5连接，第十五晶体管T15的第二极与第二电压端连接以便接收第二电压VGL。第一电容C1的第一端与第三节点N3连接，第一电容C1的第二端与第二时钟信号端连接以便接收第二时钟信号CLK2。第二电容C2的第一端与第七节点N7连接，第二电容C2的第二端与第四节点N4连接。第三电容C3的第一端与第六节点N6连接，第三电容的第二端与第五节点N5连接。
需要说明的是，图4所示的移位寄存器110只是本公开实施例中的一个示例，本公开的实施例包括但不仅限于图4所示的移位寄存器，也可以是其他的移位寄存器。
需要说明的是，本公开实施例中采用的电容包括第一端和第二端，电容的第一端和第二端例如是对称的，所以第一电容、第二电容和第三电容的第一端和第二端均是可以互换的。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极，所以本公开实施例中全部或部分晶体管的第一极和第二极根据需要是可以互换的。此外，按照晶体管的特性区分可以将晶体管分为N型和P型晶体管，本公开的实施例均以P型晶体管为例进行说明。基于本公开对P型晶体管实现方式的描述和教导，本领域普通技术人员在没有做出创造性劳动前提下能够容易想到本公开实施例采用N型晶体管的实现方式，因此，这些实现方式也是在本公开的保护范围内的。
本公开的实施例还提供一种显示面板20，如图5所示，显示面板20包 括本公开任一实施例提供的驱动电路10。该显示面板20可以为有机发光二极管显示(OLED)面板，也可以为液晶显示面板(LD)、电子墨水显示面板等。
例如，本公开实施例提供的显示面板20，还包括第一显示区210和第二显示区220。第一开关电路120被配置为根据第一控制信号SW1和第二控制信号SW2将移位寄存器110的输出信号OUTPUT(例如，移位寄存器的输出信号OUTPUT包括OUTPUT1，OUTPUT2，……，OUTPUTM)或第一电压VGH选择性输出到第一显示区210；第二开关电路130被配置为根据第三控制信号SW3和第四控制信号SW4将移位寄存器110的输出信号OUTPUT或第一电压VGH选择性输出到第二显示区220。
例如，本公开实施例提供的显示面板20，还包括柔性电路板230，柔性电路板230设置在第一显示区210和第二显示区220之间，驱动电路10设置在柔性电路板230上。
例如，本公开实施例提供的显示面板20为可折叠显示面板，可从第一显示区210和第二显示区220之间的位置被折叠。第一显示区210和第二显示区220可以被折叠从而在彼此之间形成一定夹角，或者二者完全重叠且二者的显示面均朝向外侧。
例如，本公开实施例提供的显示面板20，还包括多个子像素单元240。如图6所示，子像素单元240包括发光控制晶体管ET、有机发光二级管OLED和驱动控制电路243。
例如，驱动控制电路243用于根据发光数据信号驱动OLED发光。驱动控制电路243的第一端与第一驱动电源端连接以便接收第一驱动电源电压VDD，驱动控制电路243的第二端与发光控制晶体管ET的第一极连接。发光控制晶体管ET的栅极用于接收驱动电路10选择性输出的移位寄存器110的输出信号OUTPUT或第一电压VGH，发光控制晶体管ET的第二极与OLED的第一极(例如，阳极)连接。OLED的第二极(例如，阴极)与第二驱动电源连接以便接收第二驱动电源电压VSS。
例如，多个子像素单元240的驱动控制电路243和发光控制晶体管ET设置在第一显示区210和第二显示区220中。
例如，如图7所示，子像素单元240包括的发光区域(例如，OLED的 发光区域)与驱动电路10交叠。
例如，如图7所示，在本公开实施例提供的显示面板20中，多个子像素单元240的发光区域(例如，子像素单元240中OLED的发光区域)覆盖驱动电路10。
例如，如图7所示，在本公开实施例提供的显示面板20中，多个子像素单元240包括第一子像素单元241和第二子像素单元242。第一子像素单元241的发光区域包括红色像素单元的发光区域241A、绿色像素单元的发光区域241B和蓝色像素单元的发光区域241C；第二子像素单元242的发光区域包括红色像素单元的发光区域242A、绿色像素单元的发光区域242B和蓝色像素单元的发光区域242C。第一子像素单元241的发光区域的尺寸大于第二子像素单元242的发光区域的尺寸。
例如，在本公开实施例提供的显示面板20中，部分第一子像素单元241的发光区域与驱动电路10交叠。
例如，如图7所示，驱动电路10占用的横向长度d为300μm，第一显示区和第二显示区各占用150μm的横向长度，一个第一子像素单元的发光区域的横向长度为100μm，一个第二子像素单元的发光区域的横向长度为50μm，在第一显示区和第二显示区的每一行临近驱动电路10的部分分别设置三个第一子像素单元，即可使第一子像素单元覆盖驱动电路10。以第二显示区的第一行子像素为例，如图7所示，红色像素单元的发光区域241A以及绿色像素单元的发光区域241B的一半覆盖驱动电路10；绿色像素单元的发光区域241B的另一半以及蓝色像素单元的发光区域241C覆盖例如驱动控制电路243和发光控制晶体管ET等电路或电路元件。这种设置可以实现第一显示区和第二显示区的无缝拼接显示，提高用户体验。
本公开的实施例还提供一种显示设备1，如图8所示，显示设备1包括本公开任一实施例的显示面板20。
例如，本公开实施例提供的显示设备1还可以包括全屏控制开关31、第一显示区控制开关32和第二显示区控制开关33，全屏控制开关31用于同时开启或关闭第一显示区210和第二显示区220，第一显示区控制开关32用于单独开启或关闭第一显示区210，第二显示区控制开关33用于单独开启或关闭第二显示区220。
例如，全屏控制开关31、第一显示区控制开关32和第二显示区控制开关33可以通过设置第一控制信号SW1、第二控制信号SW2、第三控制信号SW3和第四控制信号SW4实现第一显示区210和/或第二显示区220的开启或关闭。
需要说明的是，全屏控制开关31、第一显示区控制开关32和第二显示区控制开关33的位置和形状不限于图8所示的情形，也可以是其他形状或设置在显示面板的其他位置。
例如，显示设备1可沿折叠旋转轴34被折叠，当需要第一显示区和第二显示区同时显示时，第一显示区和第二显示区可拼接为一个显示区；当需要第一显示区或第二显示区单独显示时，可将显示设备1沿折叠旋转轴34折叠，减少显示设备1占用面积，提升用户体验。全屏控制开关31可以形成在显示设备1上某一个显示区所在的一侧，并同时与两个显示区信号连接。
例如，显示设备1还包括电源开关(图8中未示出)等其它部件。
本公开的实施例还提供一种驱动本公开任一实施例驱动电路的方法，包括：当第一显示区和第二显示区同时显示时，设置第一控制信号SW1为关闭电压，设置第二控制信号SW2为开启电压，设置第三控制信号SW3为开启电压，设置第四控制信号SW4为关闭电压；当第一显示区单独显示时，设置第一控制信号SW1为关闭电压，设置第二控制信号SW2为开启电压，设置第三控制信号SW3为关闭电压，设置第四控制信号SW4为开启电压；当第二显示区单独显示时，设置第一控制信号SW1为开启电压，设置第二控制信号SW2为关闭电压，设置第三控制信号SW3为开启电压，设置第四控制信号SW4为关闭电压。
例如，开启电压是指加载在晶体管的栅极上时可使该晶体管第一极和第二极之间导通的电压，关闭电压是指加载在晶体管的栅极上时可使该晶体管第一极和第二极之间断开的电压。例如，对于P型晶体管，开启电压例如为低电压(例如，0V)，关闭电压例如为高电压(例如，5V)；对于N型晶体管，开启电压例如为高电压(例如，5V)，关闭电压例如为低电压(例如，0V)。本公开的实施例以P型晶体管为例进行说明。
当第一显示区和第二显示区同时显示时，参见图5，设置第一控制信号SW1为高电压，设置第二控制信号SW2为低电压，设置第三控制信号SW3 为低电压，设置第四控制信号SW4为高电压。第一晶体管T1、第四晶体管T4、第五晶体管T5和第七晶体管T7均关闭，第二晶体管T2和第三晶体管T3导通。第一节点N1和第二节点N2的电压为第二电压VGL(第二电压VGL例如为低电压)，第一节点N1的低电压使第六晶体管T6全部导通，第二节点N2的低电压使第八晶体管T8全部导通。移位寄存器110的输出信号OUTPUT(例如，移位寄存器的输出信号OUTPUT包括OUTPUT1，OUTPUT2，……，OUTPUTM)传输到第一显示区210和第二显示区220(例如，传输到第一显示区210和第二显示区220中发光控制晶体管ET的栅极)。
需要说明的是，移位寄存器110的输出信号OUTPUT包括但不仅限于是传输到发光控制晶体管ET的栅极，用于控制发光功能的控制信号，也可以是控制数据写入的扫描信号或控制复位功能的扫描信号等其它信号。
当第一显示区单独显示时，第二显示区处于关机或休眠状态。设置第一控制信号SW1为高电压，设置第二控制信号SW2为低电压，设置第三控制信号SW3为高电压，设置第四控制信号SW4为低电压。第一晶体管T1和第五晶体管T5关闭，第二晶体管T2导通。第一节点N1的电压为第二电压VGL(第二电压VGL例如为低电压)，第一节点N1的低电压使第六晶体管T6全部导通。移位寄存器110的输出信号OUTPUT(例如，移位寄存器的输出信号OUTPUT包括OUTPUT1，OUTPUT2，……，OUTPUTM)传输到第一显示区210。第三晶体管T3关闭，第四晶体管T4和第七晶体管T7导通，第二节点N2的电压为第一电压VGH(第一电压VGH例如为高电压)，第二节点N2的高电压使第八晶体管T8全部关闭，第一电压VGH通过第七晶体管T7传输到第二显示区220(例如，传输到第二显示区220中发光控制晶体管ET的栅极)。使第二显示区处于关机或休眠状态，从而节省电能。
当第二显示区单独显示时，第一显示区处于关机或休眠状态。设置第一控制信号SW1为低电压，设置第二控制信号SW2为高电压，设置第三控制信号SW3为低电压，设置第四控制信号SW4为高电压。第四晶体管T4和第七晶体管T7关闭，第三晶体管T3导通。第二节点N2的电压为第二电压VGL(第二电压VGL例如为低电压)，第二节点N2的低电压使第八晶体管T8全部导通。移位寄存器110的输出信号OUTPUT(例如，移位寄存器的输出信号OUTPUT包括OUTPUT1，OUTPUT2，……，OUTPUTM)传输到 第二显示区220。第二晶体管T2关闭，第一晶体管T1和第五晶体管T5导通，第一节点N1的电压为第一电压VGH(第一电压VGH例如为高电压)，第一节点N1的高电压使第六晶体管T6全部关闭，第一电压VGH通过第五晶体管T5传输到第一显示区210(例如，传输到第一显示区210中发光控制晶体管ET的栅极)。使第一显示区处于关机或休眠状态，从而节省电能。
本公开的实施例提供的驱动电路、显示面板、显示设备和驱动方法。在本公开的实施例中，一组移位寄存器可同时或分别驱动两个显示区，这样可以节省移位寄存器，实现显示区的独立工作，还可以降低功耗，节省电能。
虽然上文中已经用一般性说明及具体实施方式，对本公开作了详尽的描述，但在本公开实施例基础上，可以对之作一些修改或改进，这对本领域技术人员而言是显而易见的。因此，在不偏离本公开精神的基础上所做的这些修改或改进，均属于本公开要求保护的范围。
本专利申请要求于2016年7月29日递交的中国专利申请第201610615542.9号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (18)

  1. 一种驱动电路，包括：
    多个移位寄存器；
    与所述移位寄存器连接的第一开关电路，被配置为根据第一控制信号和第二控制信号选择性输出所述移位寄存器的输出信号或第一电压；以及
    与所述移位寄存器连接的第二开关电路，被配置为根据第三控制信号和第四控制信号选择性输出所述移位寄存器的输出信号或所述第一电压。
  2. 根据权利要求1所述的驱动电路，其中，
    所述第一开关电路包括：
    第一控制子电路，被配置为根据所述第一控制信号和所述第二控制信号选择性输出所述第一电压或第二电压到第一节点；
    多个第一开关子电路，被配置为根据所述第一控制信号和所述第一节点的电压向第一显示屏选择性输出所述移位寄存器的输出信号或所述第一电压，
    所述第二开关电路包括：
    第二控制子电路，被配置为根据所述第三控制信号和所述第四控制信号选择性输出所述第一电压或所述第二电压到第二节点；
    多个第二开关子电路，被配置为根据所述第四控制信号和所述第二节点的电压向第二显示屏选择性输出所述移位寄存器的输出信号或所述第一电压。
  3. 根据权利要求2所述的驱动电路，其中，所述第一控制子电路包括第一晶体管和第二晶体管，每个所述第一开关子电路包括第五晶体管和第六晶体管，所述第二控制子电路包括第三晶体管和第四晶体管，每个所述第二开关子电路包括第七晶体管和第八晶体管。
  4. 根据权利要求3所述的驱动电路，其中，
    所述第一晶体管的第一极与第一电压端连接以便接收所述第一电压，所述第一晶体管的栅极与第一控制信号端连接以便接收所述第一控制信号，所述第一晶体管的第二极与所述第一节点连接；
    所述第二晶体管的第一极与所述第一节点连接，所述第二晶体管的栅极 与第二控制信号端连接以便接收所述第二控制信号，所述第二晶体管的第二极与第二电压端连接以便接收所述第二电压；
    所述第三晶体管的第一极与所述第二节点连接，所述第三晶体管的栅极与第三控制信号端连接以便接收所述第三控制信号，所述第三晶体管的第二极与所述第二电压端连接以便接收所述第二电压；
    所述第四晶体管的第一极与所述第一电压端连接以便接收所述第一电压，所述第四晶体管的栅极与第四控制信号端连接以便接收第四控制信号，所述第四晶体管的第二极与所述第二节点连接；
    所述第五晶体管的第一极与所述第一电压端连接以便接收所述第一电压，所述第五晶体管的栅极与所述第一控制信号端连接以便接收所述第一控制信号，所述第五晶体管的第二极与所述第六晶体管的第二极连接；
    所述第六晶体管的第一极与所述移位寄存器连接以便接收所述移位寄存器的输出信号，所述第六晶体管的栅极与所述第一节点连接；
    所述第七晶体管的第一极与所述第一电压端连接以便接收所述第一电压，所述第七晶体管的栅极与所述第四控制信号端连接以便接收所述第四控制信号，所述第七晶体管的第二极与所述第八晶体管的第二极连接；
    所述第八晶体管的第一极与所述移位寄存器连接以便接收所述移位寄存器的输出信号，所述第八晶体管的栅极与所述第二节点连接。
  5. 根据权利要求2-4任一项所述的驱动电路，其中，多个所述第一开关子电路、多个所述第二开关子电路和多个所述移位寄存器一一对应。
  6. 根据权利要求2-4任一项所述的驱动电路，其中，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管、所述第七晶体管和所述第八晶体管均为P型晶体管。
  7. 根据权利要求2-4任一项所述的驱动电路，其中，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管、所述第七晶体管和所述第八晶体管均为薄膜晶体管。
  8. 一种显示面板，包括如权利要求1-7任一项所述的驱动电路。
  9. 根据权利要求8所述的显示面板，还包括第一显示区和第二显示区，其中，所述第一开关电路被配置为根据所述第一控制信号和所述第二控制信号将所述移位寄存器的输出信号或第一电压选择性输出到所述第一显示区，
    所述第二开关电路被配置为根据第三控制信号和第四控制信号将所述移位寄存器的输出信号或所述第一电压选择性输出到所述第二显示区。
  10. 根据权利要求9所述的显示面板，还包括柔性电路板，其中，所述柔性电路板设置在所述第一显示区和所述第二显示区之间，所述驱动电路设置在所述柔性电路板上。
  11. 根据权利要求10所述的显示面板，其中所述显示面板为可折叠显示面板，可从所述第一显示区和所述第二显示区之间的位置被折叠。
  12. 根据权利要求8-11任一项所述的显示面板，还包括多个子像素单元，其中，部分所述子像素单元的发光区域与所述驱动电路交叠。
  13. 根据权利要求12所述的显示面板，其中，所述多个子像素单元的发光区域覆盖所述驱动电路。
  14. 根据权利要求12所述的显示面板，其中，所述多个子像素单元包括第一子像素单元和第二子像素单元，所述第一子像素单元的发光区域的尺寸大于所述第二子像素单元的发光区域的尺寸。
  15. 根据权利要求12所述的显示面板，其中，部分所述第一子像素单元的发光区域与所述驱动电路交叠。
  16. 一种显示设备，包括8-15任一项所述的显示面板。
  17. 根据权利要求16所述的显示设备，还包括全屏控制开关、第一显示区控制开关和第二显示区控制开关，
    其中，所述全屏控制开关用于同时开启或关闭所述第一显示区和所述第二显示区，
    所述第一显示区控制开关用于单独开启或关闭所述第一显示区，
    所述第二显示区控制开关用于单独开启或关闭所述第二显示区。
  18. 一种驱动如1-7任一项所述驱动电路的方法，包括：
    当第一显示区和第二显示区同时显示时，设置所述第一控制信号为关闭电压，设置所述第二控制信号为开启电压，设置所述第三控制信号为开启电压，设置所述第四控制信号为关闭电压；
    当第一显示区单独显示时，设置所述第一控制信号为关闭电压，设置所述第二控制信号为开启电压，设置所述第三控制信号为关闭电压，设置所述第四控制信号为开启电压；
    当第二显示区单独显示时，设置所述第一控制信号为开启电压，设置所述第二控制信号为关闭电压，设置所述第三控制信号为开启电压，设置所述第四控制信号为关闭电压。
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