WO2018027587A1 - 一种片上系统和处理设备 - Google Patents

一种片上系统和处理设备 Download PDF

Info

Publication number
WO2018027587A1
WO2018027587A1 PCT/CN2016/094226 CN2016094226W WO2018027587A1 WO 2018027587 A1 WO2018027587 A1 WO 2018027587A1 CN 2016094226 W CN2016094226 W CN 2016094226W WO 2018027587 A1 WO2018027587 A1 WO 2018027587A1
Authority
WO
WIPO (PCT)
Prior art keywords
secure
processor
security
memory
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2016/094226
Other languages
English (en)
French (fr)
Inventor
檀珠峰
鹿甲寅
刘宇
孙少杰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Huawei Technologies Co Ltd
Original Assignee
Huawei Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Priority to EP16912042.5A priority Critical patent/EP3461016A4/en
Priority to PCT/CN2016/094226 priority patent/WO2018027587A1/zh
Priority to KR1020187033145A priority patent/KR20180135940A/ko
Priority to BR112018073991-0A priority patent/BR112018073991A2/pt
Priority to CN201680084559.4A priority patent/CN109075815A/zh
Priority to TW106126726A priority patent/TWI633438B/zh
Publication of WO2018027587A1 publication Critical patent/WO2018027587A1/zh
Priority to US16/268,294 priority patent/US20190172047A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06Q—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
    • G06Q20/00—Payment architectures, schemes or protocols
    • G06Q20/30—Payment architectures, schemes or protocols characterised by the use of specific devices or networks
    • G06Q20/32—Payment architectures, schemes or protocols characterised by the use of specific devices or networks using wireless devices
    • G06Q20/322—Aspects of commerce using mobile devices [M-devices]
    • G06Q20/3227—Aspects of commerce using mobile devices [M-devices] using secure elements embedded in M-devices
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/30—Authentication, i.e. establishing the identity or authorisation of security principals
    • G06F21/31—User authentication
    • G06F21/32—User authentication using biometric data, e.g. fingerprints, iris scans or voiceprints
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
    • G06F21/52—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity ; Preventing unwanted data erasure; Buffer overflow
    • G06F21/53—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity ; Preventing unwanted data erasure; Buffer overflow by executing in a restricted environment, e.g. sandbox or secure virtual machine
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
    • G06F21/57—Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
    • G06F21/57—Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
    • G06F21/575—Secure boot
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/60—Protecting data
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/60—Protecting data
    • G06F21/602—Providing cryptographic facilities or services
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/74—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information operating in dual or compartmented mode, i.e. at least one secure mode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06Q—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
    • G06Q20/00—Payment architectures, schemes or protocols
    • G06Q20/30—Payment architectures, schemes or protocols characterised by the use of specific devices or networks
    • G06Q20/32—Payment architectures, schemes or protocols characterised by the use of specific devices or networks using wireless devices
    • G06Q20/326—Payment applications installed on the mobile devices
    • G06Q20/3263—Payment applications installed on the mobile devices characterised by activation or deactivation of payment capabilities
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06Q—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
    • G06Q20/00—Payment architectures, schemes or protocols
    • G06Q20/30—Payment architectures, schemes or protocols characterised by the use of specific devices or networks
    • G06Q20/32—Payment architectures, schemes or protocols characterised by the use of specific devices or networks using wireless devices
    • G06Q20/327—Short range or proximity payments by means of M-devices
    • G06Q20/3278—RFID or NFC payments by means of M-devices
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06Q—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
    • G06Q20/00—Payment architectures, schemes or protocols
    • G06Q20/30—Payment architectures, schemes or protocols characterised by the use of specific devices or networks
    • G06Q20/34—Payment architectures, schemes or protocols characterised by the use of specific devices or networks using cards, e.g. integrated circuit [IC] cards or magnetic cards
    • G06Q20/356—Aspects of software for card payments
    • G06Q20/3563—Software being resident on card
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06Q—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
    • G06Q20/00—Payment architectures, schemes or protocols
    • G06Q20/38—Payment protocols; Details thereof
    • G06Q20/40—Authorisation, e.g. identification of payer or payee, verification of customer or shop credentials; Review and approval of payers, e.g. check credit lines or negative lists
    • G06Q20/401—Transaction verification
    • G06Q20/4014—Identity check for transactions
    • G06Q20/40145—Biometric identity checks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B5/00—Near-field transmission systems, e.g. inductive or capacitive transmission systems
    • H04B5/20—Near-field transmission systems, e.g. inductive or capacitive transmission systems characterised by the transmission technique; characterised by the transmission medium
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B5/00—Near-field transmission systems, e.g. inductive or capacitive transmission systems
    • H04B5/70—Near-field transmission systems, e.g. inductive or capacitive transmission systems specially adapted for specific purposes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L63/00—Network architectures or network communication protocols for network security
    • H04L63/08—Network architectures or network communication protocols for network security for authentication of entities
    • H04L63/0861—Network architectures or network communication protocols for network security for authentication of entities using biometrical features, e.g. fingerprint, retina-scan
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
    • H04L9/0861—Generation of secret information including derivation or calculation of cryptographic keys or passwords
    • H04L9/0869—Generation of secret information including derivation or calculation of cryptographic keys or passwords involving random numbers or seeds
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W12/00—Security arrangements; Authentication; Protecting privacy or anonymity
    • H04W12/06—Authentication
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W4/00—Services specially adapted for wireless communication networks; Facilities therefor
    • H04W4/80—Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2221/00—Indexing scheme relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/21—Indexing scheme relating to G06F21/00 and subgroups addressing additional information or applications relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/2149—Restricted operating environment
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06Q—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
    • G06Q2220/00—Business processing using cryptography
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12—Fingerprints or palmprints
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/16—Human faces, e.g. facial parts, sketches or expressions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/18—Eye characteristics, e.g. of the iris
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B5/00—Near-field transmission systems, e.g. inductive or capacitive transmission systems
    • H04B5/20—Near-field transmission systems, e.g. inductive or capacitive transmission systems characterised by the transmission technique; characterised by the transmission medium
    • H04B5/24—Inductive coupling

Definitions

  • the present invention relates to the field of chip technologies, and in particular, to a system of chip and a processing device.
  • Mobile Payment refers to a service that allows users to pay for goods or services they consume using mobile terminals, such as mobile phones, tablets, or wearable devices.
  • mobile terminals such as mobile phones, tablets, or wearable devices.
  • SD Secure Digital
  • SIM Subscriber Identity Module
  • NFC Near Field Communication
  • SE Full terminal solution.
  • the all-terminal solution of near-field communication combined with security components is becoming the mainstream of mobile payment solutions.
  • these solutions have begun to show a convergence trend.
  • the secure element can also have a SIM function or other functionality.
  • the mobile terminal 10 communicates with a Point of Sales (POS) machine 11 through its internal near field communication unit 101, a near field communication unit 101 and a POS machine 11
  • the short-range wireless communication link 12 is a two-way path, and can be implemented by various suitable short-range wireless communication protocols to implement basic wireless communication functions in mobile payment.
  • the communication link 12 can be used to transfer POS command data or the like from the POS machine 11 to the near field communication unit 101 inside the mobile terminal 10.
  • the secure element 102 can be a component coupled to a separate Central Processing Unit (CPU) 103 for operating various functions related to the financial payment service and storing keys, certificates, etc. related to the banking service. data.
  • CPU Central Processing Unit
  • the secure element 102 receives the POS command data from the near field communication unit 101, parses the command data, and responds accordingly according to the financial transaction protocol. The response is fed back to the POS machine 11 by the near field communication unit 101 to complete the data transmission in the mobile payment to implement the function of the mobile terminal 10 as a transaction verification card.
  • the central processing unit 103 is then run with general operating system software 1031, such as Android system software, for controlling the near field communication unit 101 and the secure element 102, such as controlling the opening or closing of the near field communication unit 101 and the secure element. 102.
  • the mobile terminal 10 may include an input unit 104, inputting a single
  • the element 104 can be a touch screen, which can be regarded as a user interface (UI) for interacting with the user, so that the user can input an operation instruction through the user interface software-driven input unit 104 to indicate the operating system software 1031.
  • the POS machine 11 accesses the cloud server 14 on the network side through the Internet as a terminal device of the transaction to implement calculation and completion of the payment service by the server 14.
  • the server 14 located on the network side is usually operated by a bank or an internet company or the like.
  • All-terminal solutions can include online payments and offline payments.
  • the mobile terminal 10 When paying offline, as shown in FIG. 1, the mobile terminal 10 performs a non-contact card swiping with the POS machine 11, that is, the mobile phone, and the near field communication unit 101 and the secure element 102 cooperate to complete the payment transaction.
  • the central processing unit 103 and the secure element 102 can access the Internet through the mobile communication network to realize online payment, and the secure element 102 is equivalent to the bank U.
  • the role of the shield is to store and verify the bank's certificate, so the near field communication unit 101 of Figure 1 above is optional. Specifically, referring to FIG.
  • the mobile terminal 10 may further include a mobile communication unit 105 for replacing the role of the near field communication unit 101 when offline payment is applied to the radio access network (Radio Access).
  • Network, RAN radio access network
  • the radio access network 15 may specifically include a wireless access point, such as a base station.
  • the mobile communication unit 105 accesses the Internet through the wireless access network 15, which is connected to the server 14 located in the Internet to enable the server 14 to receive command data or transmit information to the secure element 102.
  • the secure element 102 parses the command data and responds accordingly in accordance with the financial transaction protocol to transmit data to the network side server 14 over the mobile internet via the mobile communication unit 105.
  • the mobile communication unit 105 can now be a unit operating a wireless cellular communication protocol for accessing the mobile terminal 10 to the Internet via the cellular wireless communication link 13.
  • the mobile communication unit 105 is also a cellular communication processor, specifically supporting Global System for Mobile (GSM), Universal Mobile Telecommunications System (UMTS), Worldwide Interoperability for Microwave (Worldwide Interoperability for Microwave) Access, WiMAX), Time Division-Synchronous Code Division Multiple Access (TSS), Code Division Multiple Access 2000 (CDMA2000), Long Term Evolution (LTE) Or a cellular wireless communication protocol such as 5G (fifth generation) to assist in implementing the mobile internet function of the mobile terminal 10.
  • GSM Global System for Mobile
  • UMTS Universal Mobile Telecommunications System
  • WiMAX Worldwide Interoperability for Microwave
  • TSS Time Division-Synchronous Code Division Multiple Access
  • CDMA2000 Code Division Multiple Access 2000
  • LTE Long Term Evolution
  • 5G fifth generation
  • Chinese patent application 201510201343.9 provides a solution for integrating the secure element 102 with the central processing unit 103 (or optionally also the mobile communication unit 105) on the same semiconductor substrate, ie integrated into a master chip 106, and
  • the secure element 102 can load general purpose operating system software, such as Android or Windows operating system software, required by the central processing unit 103 from a storage unit external to the main chip 106.
  • general purpose operating system software such as Android or Windows operating system software
  • the security component 102 runs more and more kinds of application software, and the application scenario of the security component 102 is not limited to mobile payment, and may also include some SIM card related software, such as a communication carrier customized application. software. Therefore, the complexity of SoCs implemented in an integrated manner is becoming higher and higher, and how to achieve a highly integrated and complex SoC and fully satisfy the security requirements becomes a problem.
  • a security zone Trustzone, TZ
  • TEE Trust Execute Environment
  • the user can input some information related to security applications such as mobile payment under the TEE, and the TEE and the general operating system environment respectively implement different security level application operations, since the TEE is an environment generated by the central processing unit, Security still needs to be improved.
  • the secure element 102 can interact with the peripheral device through the existing TEE with certain specific information.
  • the secure element 102 interacts with the fingerprint sensor via the TEE and the fingerprint sensor. Since the transmission of the related information passes through the TEE, the information interaction is reduced. safety. Therefore, how to implement mobile payment service based on NFC communication on SoC under the premise of ensuring security becomes an urgent problem to be solved.
  • Embodiments of the present invention provide an SoC and a processing device to improve the security of an NFC communication-based mobile payment service in a highly integrated SoC.
  • an embodiment of the present invention provides an SoC, where the SoC is integrated in a first semiconductor On-chip, comprising: a system bus, at least one processor coupled to the system bus, and a secure processor system coupled to the system bus; there is security isolation between the secure processor system and the at least one processor
  • the at least one processor includes at least one central processing unit for running general operating system software and operating through the system bus and the secure processing under the action of the general operating system software System communication;
  • the secure processor system includes a security processor, a first memory, a plurality of interfaces, and a security bus, the security processor, the first memory, and the plurality of interfaces are coupled to the secure bus, and the a security bus coupled to the system bus; wherein the security processor is configured to run secure operating system software and at least one security application software based on the secure operating system software, the at least one security application software comprising Mobile payment software for mobile payment; said first memory for providing said security And storing, by the processor, the storage space required by the security operating system software and the at least one
  • the NFC information includes at least one of a mobile payment instruction, mobile payment data, or NFC authentication information.
  • the at least one processor cannot directly access at least one of the first memory or the secure processor system.
  • the at least one processor and the secure processor system can be coupled by a dedicated interactive channel.
  • the above SoC integrates the functions of the processor and the secure processor system, which can reduce the implementation cost and area of the entire system, and implements a function equivalent to a secure component in the secure processor system, capable of running at least the mobile payment software.
  • a security application the security processor system integrates its own biometric input interface, which can conveniently obtain biometric data, and the security processor system is securely isolated from at least one processor.
  • the solution is more secure than the scheme of transferring user biometric data to the secure processor system through the TEE of the central processing unit.
  • the communication of the at least one central processing unit with the secure processor system comprises a data interaction or an instruction interaction.
  • the instructions may be instructions for at least one central processing unit to control or operate the secure processor system, including but not limited to Start command, close command, restart command, sleep command, enter or exit low power state command, or suspend or resume work command.
  • the secure processor system can be used to implement a function of a secure element or a SIM function.
  • the security processor is equivalent to realize the function of the security element, and can further integrate other functions. Therefore, the at least one security application software may further include other security application software such as SIM software, and the security application scenario of the SoC may be extended by implementing the software functions in the security processor system.
  • the first memory may be a power-down volatile memory, such as a random access memory (RAM).
  • the first memory may be used to store the loaded security operating system software and the at least one security application software, and may further be used to store and run the security operating system software and the at least one security application software.
  • Security temporary data is intermediate data or intermediate operation results generated by the security processor running the secure operating system software and the at least one security application software or other information related to the security application software or its operation that does not require long-term storage. .
  • the RAM is therefore a power-down volatile storage device such as SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory) or SDRAM (Synchronous Dynamic Random Access Memory), and is preferably SRAM. Since the RAM is integrated in the SoC, the RAM can use the same manufacturing process as the at least one central processing unit, and the process is relatively easy to implement.
  • SRAM Static Random Access Memory
  • DRAM Dynamic Random Access Memory
  • SDRAM Synchronous Dynamic Random Access Memory
  • the multiple interfaces further include a security input interface, configured to receive user information input by the user related to mobile payment.
  • the user information includes a password, a user instruction, or a financial transaction amount.
  • the secure input interface is coupled to an input device to receive the user information via the input device.
  • the input device can be a touch screen or a button.
  • the multiple interfaces further include a peripheral interface for indicating to the user by the peripheral device that the mobile payment is performed.
  • the peripheral A pointing device is provided, and the peripheral interface is coupled to the pointing device.
  • the pointing device can be an indicator light, a speaker for playing sound, or a vibrator to alert the user that the mobile payment is or has been or will be performed.
  • the peripheral interface is also integrated in the security processor system, the transmission of the indication information does not need to rely on the TEE of the central processing unit, so that higher security can be achieved.
  • the security processor system further includes a non-power-down volatile second memory coupled to the secure bus for storing the secure operating system.
  • Software and at least one security application software the security processor is configured to read the security operating system software and the at least one security application software from the second memory, and load the security operating system software and the at least one security application software Going to the first memory to run the secure operating system software and at least one secure application software. Since the second memory is also integrated in the SoC, all software executed by the security processor is stored in the second memory for a long time, and the security operating system software and the at least one security application need not be stored by relying on a memory external to the SoC. Software, high security.
  • the security processor system further comprises a security isolation device coupled to the safety bus and configured to implement the security isolation
  • the at least one processor is in communication with the secure processor system via the system bus and the secure isolation device.
  • the secure isolation device includes at least one of an isolated memory or a bus bridge for implementing interaction data or instructions by at least one processor and the secure processor system.
  • the at least one central processing unit can be coupled to the secure processor system via the system bus and the isolated memory or bus bridge by the general operating system software to interact with the secure processor system Communication, the content of which includes data or instructions.
  • the bus bridge can be a bus that spans between the secure bus and the system bus.
  • the at least one processor cannot directly access any component of the secure processor system other than the isolated memory or bus bridge. Since the at least one processor and the secure processor system only use any one of the isolated memory or the bus bridge as a dedicated interaction channel, or even a unique interaction channel, avoiding direct access by the at least one processor to the first memory Or any component or module in the secure processor system can improve security.
  • the security processor system further Included is a secure boot memory coupled to the secure bus for storing bootstrapping instructions required for initialization of the secure processor; the secure processor passes before operating the secure operating system software and the at least one secure application software
  • the bootstrap instructions are obtained from the secure boot memory to initialize the secure processor.
  • the secure boot memory is a non-power-down volatile memory, such as a ROM, which is similar to a BIOS (Basic Input Output System) in a conventional PC (Personal Computer), guaranteeing the initial startup of the secure processor system each time. It is started from the secure boot memory to ensure the security of the boot. For example, when the secure processor system is powered on, the security processor is configured to read the boot program instructions from the secure boot memory, and load the secure operating system software under the boot program instructions Going to the first memory to run the secure operating system software.
  • BIOS Basic Input Output System
  • the boot program instruction is an encrypted boot program instruction; when the security processor acquires the boot program instruction from the secure boot memory, the boot program instruction is The decryption logic circuit decrypts to obtain a decrypted bootstrap program instruction that is used to initialize the secure processor. This solution further guarantees startup security.
  • the secure processor system further includes an One Time Programable (OTP) memory coupled to the secure bus for storing the security
  • OTP One Time Programable
  • the security parameter including at least one of a root key, a calibration parameter, a configuration parameter, or an enable parameter.
  • the root key is used to generate other keys needed for encryption and decryption by the secure processor system.
  • the calibration parameters include parameters required to calibrate at least one component within the safety processor system.
  • the configuration parameters include configuration parameters of at least one component within the secure processor system.
  • the enabling parameter includes parameters that control at least one component of the safety processor system to be turned on or off.
  • the security parameters may be programmed into the OTP memory to enable calibration, configuration or setup of the secure processor system, or to disable or disable some of the device functions within the secure processor system. Therefore, the OTP memory allows some functions within the corresponding secure processor system to be set or changed after the SoC is manufactured, which improves the design flexibility after the SoC is manufactured.
  • the OTP memory is further configured to store a patch instruction of a boot program instruction required for the security processor to initialize.
  • the patch instruction can be a guide Supplement to program instructions or replacement of some of them. For example, when the SoC is manufactured, if the boot program instruction is found to be insufficient, the shortage of the existing boot program instructions can be compensated by programming the patch instruction in the OTP memory, which makes the implementation more flexible.
  • the security processor system further includes an attack defense sensor, configured to detect an abnormality of an operating parameter of the security processor system, and when the abnormality occurs Trimming at least one of: the security processor system performing an alert, the secure processor reset, or at least one of the first memory or the secure processor system being reset or emptied; the operating parameter Including at least one of voltage, current, clock frequency, temperature, or laser intensity.
  • an attack defense sensor configured to detect an abnormality of an operating parameter of the security processor system, and when the abnormality occurs Trimming at least one of: the security processor system performing an alert, the secure processor reset, or at least one of the first memory or the secure processor system being reset or emptied; the operating parameter Including at least one of voltage, current, clock frequency, temperature, or laser intensity.
  • the security processor system further includes an attack-resistant metal layer, where the attack-resistant metal layer is located in an upper layer or multiple layers of the first semiconductor chip, And covering at least a portion of the security processor system on a layout of the security; the attack-resistant metal layer is configured to detect a physical detection or attack from the outside, and generate an electrical signal when the physical detection or attack is detected, the electrical The signal is for triggering at least one of: the security processor system performing an alert, the secure processor reset, or at least one of the first memory or the secure processor system being reset or emptied.
  • the attack-resistant metal layer technology is effectively applied to the SoC, so that the security of the secure processor system executing the security application software is further improved.
  • the attack resistant metal layer is Shielding.
  • the safety bus comprises at least one of an Advanced High Performance Bus (AHB) or an Advanced Peripheral Bus (APB).
  • ALB Advanced High Performance Bus
  • APIB Advanced Peripheral Bus
  • different parts, components or circuits of the security processor system may be further divided into different security levels, and connected by using different levels of bus technology, which can meet the rate requirement and security of different components in the security processor system.
  • the data or related address transmitted on the secure bus may be processed by one or more methods such as encryption, scrambling, or Cyclic Redundancy Check (CRC) to ensure data on the secure bus. And the privacy and integrity of the address.
  • CRC Cyclic Redundancy Check
  • the security processor system further includes a direct memory access (DMA) controller coupled to the secure bus,
  • DMA direct memory access
  • the first memory reads data and outputs to the safety bus or through the security
  • the full bus writes data to the first memory.
  • the efficiency of data reading or writing is improved due to the presence of the DMA controller.
  • the security processor system further includes a cipher system coupled to the secure bus, the cryptosystem comprising at least one of: an encryption and decryption device And for performing encryption and decryption processing on at least one of the data in the security processor system; an authentication device, configured to authenticate at least one data in the security processor system; and a random number generator for generating a random number used as a unique identifier for the seed or chip that generated the key; or a key manager for generating, distributing, or destroying the encryption or decryption process or The key required for authentication.
  • the cryptosystem is a hardware accelerator capable of implementing fast secure operations or processing, and its processing security is higher than that performed by the secure processor running the software program to perform related processing.
  • the authentication device is configured to perform the biometric-based user authentication.
  • the user authentication can be performed by the security processor. It can be understood that the use of the authentication device to perform the user authentication is more efficient, but the cost is slightly improved.
  • the at least one processor further includes: a communications processor, configured to send the first communications data to the wireless access point or the second communications data from the wireless access point; a voice signal processor for processing a voice signal from a user to generate the first communication data sent by the communication processor, or for processing the second communication data received by the communication processor Obtaining a voice signal required by the user; the encryption and decryption device is further configured to perform encryption processing on the first communication data or decryption processing on the second communication data.
  • the encryption and decryption device in the security processor system that originally implements the security element function is also used to perform other functions, such as encryption and decryption processing of communication data based on voice signals, and realizes secure processing capability. diversification.
  • the voice signal may be a PS (Packet Switched) domain voice signal or a CS (Circuit Switched) domain voice signal.
  • the voice signal processor may include at least one of a HiFi (High Fidelity) processor or a voice codec (Codec).
  • the HiFi processor can be used to implement echo cancellation, smoothing, timbre enhancement, and the like of the speech signal.
  • the speech codec can be used to implement a speech codec operation to effect conversion between the speech signal in digital form and a natural analog speech signal (ordinary sound signal).
  • the wireless access point may be a base station, and the communication processor is a cellular communication processor.
  • the at least one processor may further comprise: a communication processor.
  • the encryption and decryption device is further configured to perform encryption processing on the biometric identification data to obtain encrypted biometric identification data; and the communication processor is configured to send the encrypted biometric identification data to a wireless access point for use A server that performs the user authentication.
  • the biometric data can be uploaded to the server by the communication processor, and the server is implemented by the server to save the authentication cost of the SoC.
  • the communication processor comprises at least one of a cellular communication processor or a short range communication processor. That is to say, the manner of communication transmission can be implemented in many different ways.
  • the cellular communication processor may support at least one of GSM, UMTS, WiMAX, TDS-CDMA, CDMA2000, LTE, or 5G.
  • the short-range communication processor may support at least one of infrared, wireless fidelity (WIFI), Bluetooth, or LTE D2D (Device to Device).
  • the at least one processor further includes at least one of the following: an image processing unit (GPU), a system power management unit, or a system peripheral interface.
  • the GPU is for processing image signals.
  • the system power management unit is configured to perform system power consumption control on the SoC, for example, managing and controlling clock and operating voltage of the SoC or at least one component thereof.
  • the number of system peripheral interfaces may be multiple for coupling to a plurality of peripheral devices, respectively.
  • the peripheral device may be at least one of a USB (Universal Serial Bus) device, a display, a sensor, a camera, a headphone, or a speaker.
  • USB Universal Serial Bus
  • the SoC further includes: the NFC processor.
  • the NFC processor can also be external to the SoC.
  • the manufacturing cost of the entire system can be further reduced.
  • the security processor is further configured to perform the user authentication by using the biometric data.
  • the secure processor system further includes: a biometric authenticator for performing the user authentication using the biometric data.
  • a biometric authenticator for performing the user authentication using the biometric data.
  • the biometric authenticator is equivalent to a hardware accelerator, and the user authentication function is actually equivalent to a dedicated accelerator, which is superior in security and speed.
  • the secure processor is used to implement user authentication, the cost of manufacturing and designing a dedicated accelerator can be saved.
  • the multiple interfaces further include a storage interface for coupling to a third memory;
  • the third memory is configured to store the secure operating system Software and at least one security application software;
  • the security processor is configured to read the secure operating system software and the at least one security application software from the third memory through the storage interface, the security operating system software and at least one A security application is loaded into the first memory to run the secure operating system software and the at least one secure application.
  • the third memory is coupled to the secure processor system through the dedicated storage interface, such that the secure operating system software and the at least one secure application are read by the dedicated storage.
  • the interface can achieve higher security without relying on the TEE of the central processing unit.
  • the third memory is integrated on a second semiconductor chip different from the first semiconductor chip.
  • the third memory is a non-power-down volatile memory, and may be a flash memory.
  • the third memory is dedicated to storing the secure operating system software and the at least one security application software, and is not used for storing non-secure common software, thereby achieving higher security.
  • the biometric identification includes at least one of the following: fingerprint recognition, iris recognition, voiceprint recognition, face recognition, or scent recognition.
  • the biometric sensor may include at least one of a fingerprint sensor, an iris sensor, a voiceprint sensor, an image sensor, or an odor sensor.
  • the biometric input interface may include at least one of the following: a fingerprint input interface, an iris data input interface, a voiceprint input interface, a face image input interface, or an scent data input interface.
  • the embodiment of the present invention further provides a processing device, including the SoC of the first aspect or any one of the possible implementation manners.
  • the processing device further includes a fourth memory integrated on the third semiconductor chip, the SoC and the fourth memory being coupled by an inter-chip interface, the fourth memory including a secure storage area and a common storage area isolated from each other;
  • the secure storage area is configured to store the secure operating system software and at least one secure application software;
  • the normal storage area is configured to store the general operating system software;
  • the at least one central processing unit is configured to pass the chip
  • the inter-interface obtains the general-purpose operating system software from the normal storage area and runs the general-purpose operating system software;
  • the security processor is configured to use the inter-chip interface, the system bus, and the secure bus from the secure storage area Obtaining the secure operating system software and the at least one secure application software, and running the secure operating system software and the at least one secure application software.
  • the fourth memory can simultaneously store the security software and the non-secure software, hardware multiplexing is realized, and the cost is reduced.
  • the processing device is a mobile terminal.
  • the fourth memory is non- Power-down volatile memory, such as EMMC (Embedded Multi Media Card) or UFS (Universal Flash Storage).
  • the embodiment of the present invention further provides a data processing method, which is performed by the SoC described in the first aspect or any one of the possible implementation manners.
  • the method at least includes: interacting with the NFC peer through the NFC interface with NFC information related to the mobile payment; receiving biometric data from a biometric sensor, the biometric data being used in the mobile payment based Biometric user authentication; displaying at least one display information to the user through a user interface (UI).
  • the display information includes at least one of a user information input interface, a transaction interface of the mobile payment, or a transaction success interface.
  • the user interface is driven by the UI software of the general operating system software that is run by the at least one central processing unit. Or formed by the security processor running the security user interface software in the at least one security application software.
  • Embodiments of the present invention may enable the secure processor system to use its own dedicated interface to receive various types of information without relying on traditional TEE to improve security.
  • FIG. 1 is a simplified schematic diagram of a simplified mobile terminal structure capable of running a secure mobile payment application in a mobile payment scenario provided by the prior art
  • FIG. 2 is a simplified schematic diagram of a mobile terminal according to an embodiment of the present invention.
  • FIG. 3 is a simplified schematic diagram of a security processor system according to an embodiment of the present invention.
  • FIG. 4 is a simplified schematic diagram of an application manner of multiple interfaces of a security processor system according to an embodiment of the present invention
  • FIG. 5 is a simplified schematic diagram of a secure storage manner of a bootloader instruction in a secure processor system according to an embodiment of the present invention
  • FIG. 6 is a simplified schematic diagram of an anti-attack sensor according to an embodiment of the present invention.
  • FIG. 7 is a simplified schematic diagram of a layered layout of an attack-resistant metal layer on a semiconductor chip according to an embodiment of the present invention.
  • FIG. 8 is a simplified schematic diagram of an attack-resistant metal layer in a layout of a semiconductor chip according to an embodiment of the present invention.
  • FIG. 9 is a simplified schematic diagram of an application scenario of a memory using a system memory as a security operating system software and the at least one security application software according to an embodiment of the present disclosure
  • FIG. 10 is a simplified schematic diagram of an application scenario of a memory using a dedicated secure memory as a secure operating system software and the at least one secure application software according to an embodiment of the present disclosure
  • FIG. 11 is a schematic flowchart of a mobile payment related method according to an embodiment of the present invention.
  • FIG. 12 is a simplified schematic diagram of an application scenario for performing voice signal encryption using a secure processor system according to an embodiment of the present invention
  • FIG. 13 is a simplified schematic diagram of an application scenario of performing user authentication based on fingerprint data by a cloud side server according to an embodiment of the present invention
  • FIG. 14 is a simplified schematic diagram of an application scenario for collecting and storing fingerprint data according to an embodiment of the present invention.
  • FIG. 15 is a schematic flowchart of a processing method in a mobile payment process according to an embodiment of the present invention.
  • the mobile terminal may also be called a user equipment (UE), a wireless terminal, or a user terminal, and may enjoy the wireless access service of the service site or the wireless access point.
  • the serving station or wireless access point is typically a base station, such as an eNodeB or NodeB in LTE (Long Term Evolution), or
  • the access point for connecting the user equipment to the mobile communication network may also be a base station controller in the GSM mode or the like.
  • the serving station may form one or more cells when providing access services for the mobile terminal, and a cell may geographically cover a certain range and occupy a segment of a carrier or a frequency band in the frequency domain.
  • the mobile terminal and the service station can implement a communication process by running a wireless communication protocol, including but not limited to various types of cellular wireless communications such as GSM, UMTS, WiMAX, TDS-CDMA, CDMA2000, LTE, or 5G. protocol.
  • a wireless communication protocol including but not limited to various types of cellular wireless communications such as GSM, UMTS, WiMAX, TDS-CDMA, CDMA2000, LTE, or 5G. protocol.
  • FIG. 2 is a simplified schematic diagram of a mobile terminal 20 according to an embodiment of the present invention.
  • the mobile terminal 20 can be a User Equipment (UE), such as a mobile phone, a tablet, or a wearable device.
  • UE User Equipment
  • the mobile terminal 20 may specifically include a system on chip 21 and a system memory 22, and the system on chip 21 and the system memory 22 may be coupled to each other through a dedicated interface.
  • the system on chip (SoC) involved in the embodiments of the present invention is a system fabricated on the same semiconductor chip or semiconductor substrate by an integrated circuit process.
  • a semiconductor chip also referred to simply as a chip, may be a collection of integrated circuits formed on a substrate of an integrated circuit (typically a semiconductor material such as silicon) fabricated using an integrated circuit process, the outer layers of which are typically packaged by a semiconductor package material.
  • the integrated circuit may include various functional devices, each of which includes a logic gate circuit, a metal-oxide-semiconductor (MOS) transistor, a bipolar transistor or a diode, and may also include a capacitor and a resistor. Or other components such as inductors.
  • MOS metal-oxide-semiconductor
  • each functional device or module of the device mentioned in the embodiments of the present invention may be hardware, and each functional device may include a plurality of logic gate circuits or transistors.
  • the system memory 22 and the system on chip 21 are respectively located on different semiconductor chips.
  • system on chip 21 is located on a first semiconductor chip and system memory 22 is located on a third semiconductor chip.
  • the system memory 22 is a non-power-down volatile memory such as EMMC or UFS.
  • the system on chip 21 may include various types of functional devices, such as a system bus 210, at least one processor coupled to the system bus 210, and a secure processor system 23 coupled to the system bus 210.
  • the secure processor system 23 is in safe isolation from other components within the system on chip 21, i.e., with the at least one processor.
  • the at least one processor may optionally include at least one central processing unit 211, image processing unit 212, communication processor 213, voice signal processor 214, system peripheral interface 215, system power management unit 216, and image signal processing. (ISP, Image Signal Processor) 217.
  • the secure processor system may include one or more interfaces 24, which may include an interface coupled to other components than the system on chip 21 or an interface coupled with other components within the system on chip 21.
  • the secure isolation can be used to limit access by the at least one processor to devices or modules within the secure processor system 23.
  • the at least one processor including the central processing unit 211 cannot directly access at least one of the random access memory 32 or the secure processor system 23, and thus cannot read the security processor arbitrarily. Data or information within system 23.
  • the at least one central processing unit 211 is configured to run general purpose operating system software and communicate with the secure processor system 23 via the system bus 210 under the action of the general operating system software.
  • the at least one central processing unit 211 can be implemented based on an Advanced RISC Machine (ARM) architecture or an Intel X86 architecture or a Million Instructions Per Second (MIPS) architecture. This embodiment does not limit this.
  • ARM Advanced RISC Machine
  • MIPS Million Instructions Per Second
  • the general-purpose operating system software is a general-purpose software platform that runs a variety of common application software.
  • the general operating system software may be an Android operating system, a Windows operating system, or an iOS operating system.
  • the image processing unit 212 is configured to process image signals, such as processing video image signals or photo image signals, and may also selectively process 3D (3 Dimensions) image signals.
  • the system power consumption management unit 216 is configured to perform system power consumption control on the system on chip 21, for example, to manage and control clock and operating voltage of the system on chip 21 or at least one component thereof, for example, performing AVS (from AVS) Adaptive Voltage Scaling, DVS (Dynamic Doltage Scaling) or clock frequency adjustment.
  • the number of system peripheral interfaces 215 may be multiple for coupling to a plurality of peripheral devices of the mobile terminal 20 outside of the system on chip 21.
  • the peripheral device can be at least one of a USB device, a display, a sensor, a camera, a headset, or a speaker.
  • the sensor can be a gravity accelerometer, a gyroscope, or a light sensor.
  • the image signal processor 217 can be used to process the image signals acquired by the camera of the mobile terminal 20 to obtain a processed acquired image, which can be further processed by the image processing unit 212.
  • the communication processor 213 of FIG. 2 may include a plurality of processors that perform different communication functions.
  • a cellular communication processor or a short range communication processor can alternatively be included.
  • the cellular communication processor can support at least one cellular wireless communication protocol of GSM, UMTS, WiMAX, TDS-CDMA, CDMA2000, LTE, or 5G.
  • the short range communication processor can support at least one of infrared, WIFI, Bluetooth, or LTE D2D.
  • each communication processor may include an RF processor for performing radio frequency (RF) signal processing, and a baseband communication processor for performing baseband communication processing or communication protocol algorithms.
  • each of the communication processors may include only a baseband communication processor, and the corresponding RF processor may be external to the system on chip 21. That is, if the system on chip 21 is integrated on the first semiconductor chip, the RF processor can be integrated on another chip different from the first semiconductor chip.
  • the speech signal processor 214 of Figure 2 is for performing speech signal processing.
  • the speech signal processor 214 can include at least one of a HiFi processor or a speech codec.
  • the HiFi processor can be used to implement echo cancellation, smoothing, timbre enhancement, and the like of the speech signal.
  • the speech codec can be used to implement a speech codec operation to effect conversion between the speech signal in digital form and a natural analog speech signal.
  • voice signal processor 214 may only include a HiFi processor.
  • the voice codec is implemented on the other semiconductor chip of the on-chip system 21 because it includes an analog circuit, which is not limited in this embodiment.
  • FIG. 3 is a diagram of a security processor system 23 provided by an embodiment of the present invention.
  • the secure processor system 23 can also implement more secure application functions in this embodiment as a schedule and execution of the secure processor system 23. Work at the center.
  • the secure processor system 23 includes a secure bus 35, and a secure processor 31, random access memory (RAM) 32, secure boot memory 33, OTP memory 34, and the plurality of interfaces 24 coupled to the secure bus 35.
  • the random access memory 32 is a power-down volatile memory
  • the secure boot memory 33 is a non-power-down volatile memory.
  • a random access memory 32, a secure boot memory 33, and an OTP memory 34 are included in one storage system.
  • the respective memories may not be included in one system, but are each independently independent, and there is no close association in the circuit structure, and the specific implementation manner is not limited in this embodiment.
  • the security processor 31 is configured to run a security operating system software and at least one security application software based on the security operating system software, where the at least one security application software comprises mobile payment software, and the security processor can be operated by The mobile payment software implements mobile payment.
  • the at least one security application software may further include SIM card application software, including but not limited to virtual SIM software or a SIM feature application software customized by a communication carrier.
  • the security processor 31 is equivalent to implement the functions of the security element in the prior art, and can further integrate other functions to expand the security application scenario of the system on chip 21.
  • the random access memory 32 is configured to provide a storage space required by the security processor 31 to run the secure operating system software and the at least one secure application software.
  • the random access memory 32 may be configured to store the loaded secure operating system software and the at least one secure application software, and may also be configured to store the generated by the running the secure operating system software and the at least one secure application software Secure temporary data.
  • the security operating system software and the at least one security application software may be loaded into the random access memory 32 after the security processor 31 is powered on, and the corresponding software is run by using the internal storage space of the random access memory 32.
  • the secure temporary data is intermediate data or intermediate operation results generated by the security processor 31 running the secure operating system software and the at least one security application software or other related to the security application software or its operation without long-term storage. Information such as various types of intermediate operation result data or configuration data in arithmetic processing.
  • the random access memory 32 is equivalent to realizing the memory function in the computer, and is a power-down volatile storage device, which can be any one of SRAM, DRAM, SDRAM or DDR SDRAM (Double Rate Synchronous Dynamic Random Access Memory). . Since the random access memory 32 is integrated into the system on chip 21, the random access memory 32 can use the same manufacturing process as the other components in the system on chip 21, and the process is relatively easy to implement.
  • the security processor 31 can be used to boot initialization of other components within the secure processor system 23 during power-on startup, and load the secure operating system software and the at least one secure application into the random access memory 32 to perform related operational operations. .
  • the security processor 31 may be a processor with a lower computing speed or implementation complexity than the at least one central processing unit 211, but the power consumption is generally lower and the security is better, for example, it may be an ARM architecture processor, or It is another dedicated anti-attack processor, or it can be a digital signal processor (DSP).
  • DSP digital signal processor
  • the secure operating system software run by the security processor 31 may be an on-chip operating system (COS).
  • COS also known as a COS image
  • COS image may include functionality to host operating system software within a smart card or an integrated circuit (IC) card, where the secure processor system 23 includes conventional secure components, resident smart cards, or The function of a financial card, which is used to provide mobile cards such as swipe cards to external POS machines, card readers or financial servers on the cloud side.
  • Pay for the data required by the business such as data related to the banking financial business or personal account data of the user, such as personal account number, password, and various types of verification information required for the bank server to verify the personal account.
  • the COS image may also be an operation platform for receiving and processing external payment information (such as various payment information sent by a financial server or a card reader or a POS machine), and may be selectively used to execute various instructions sent by the outside world, such as Operations such as authentication operations.
  • the COS is generally based on the JAVA computer programming language design, and can be preset not only in the secure processor system 23, but also the mobile terminal 20 can dynamically download and install various security application software, such as various financial application software, based on the COS.
  • the specific design of the COS is part of the prior art and is outside the scope of this application.
  • communication of the at least one central processing unit 211 with the secure processor system 23 includes data interaction or instruction interaction.
  • the instructions may be instructions of at least one central processing unit 211 to control or operate the secure processor system 23, including but not limited to a start command, a close command, a restart command, a sleep command, an entry or exit of a low power state command, or
  • the work order is suspended or resumed to instruct the secure processor system 23 to enter a state corresponding to each instruction, respectively.
  • central processing unit 211 sends a sleep command to the secure processor system 23
  • the secure processor system 23 can enter a sleep state in response to the instruction.
  • the operational state of the secure processor system 23 can be controlled by the at least one central processing unit 211, but does not affect the security of the data in the secure processor system 23.
  • the instructions may also be used to implement other control processes, such as controlling the operating state, and may specifically include controlling the operating voltage, operating clock frequency, or information processing rate of the security processor system 23 or at least some of the components therein. This embodiment does not limit this.
  • the plurality of interfaces 24 in FIG. 3 can flexibly adapt to different usage scenarios, and can optionally include an NFC interface 241 and a fingerprint input interface 242.
  • the NFC interface 241 is configured to exchange, by the NFC processor 41, NFC information related to the mobile payment with an NFC peer, where the NFC information includes a mobile payment instruction, a mobile payment data, or an NFC authentication. At least one of the information.
  • the NFC processor 41 is a processor that performs NFC communication signal processing, which can be integrated in the communication processor 213 to reduce the manufacturing cost of the entire system, and can also be located outside the system on the chip 21 in the mobile terminal 20. Independent of the semiconductor chip.
  • the NFC processor 41 can include at least one of an NFC baseband processor and an RF processor.
  • the NFC processor 41 is also commonly referred to as an NFC controller for implementing short-range contactless data communication with the NFC peer to implement data. Read or write or interact.
  • the NFC peer is a device that interacts with the NFC processor 41 within the mobile terminal 20 for NFC data and instructions, and may be a POS machine.
  • the security processor 31 is configured to implement operations and processing related to mobile payment, and interact with the NFC processor 41 coupled to the NFC interface 241 via the secure bus 35, the NFC information being sent by the NFC processor 41 to The NFC peer receives or receives from the NFC peer.
  • the NFC peer may be NFC authentication information related to mobile payment, mobile payment amount, mobile payment request or response information, and the like.
  • the NFC processor 41 can support an NFC communication protocol or an RFID (Radio Frequency Identification) communication protocol.
  • the security processor 31 runs the mobile payment software, and sends a mobile payment request to the NFC peer through the secure bus 35, the NFC interface 241, and the NFC processor 41, and receives the reverse payment.
  • the mobile payment response from the NFC peer and further interact with the NFC peer to perform the NFC authentication information required for the two-way NFC authentication, and transmit the user-determined payment amount to the NFC peer.
  • the NFC interface 241 can be a Single Wire Protocol (SWP) interface. Of course, it can also be other types of interfaces, such as Serial Peripheral Interface (SPI), General Purpose Input Output (GPIO). ) Interface or Inter-Integrated Circuit (I2C) interface.
  • SWP Single Wire Protocol
  • SPI Serial Peripheral Interface
  • GPIO General Purpose Input Output
  • I2C Inter-Integrated Circuit
  • the fingerprint input interface 242 is coupled to a fingerprint sensor 42 for receiving fingerprint data from the fingerprint sensor 42, the fingerprint data being used in the mobile payment for user authentication based on fingerprint recognition.
  • the fingerprint sensor 42 is typically a device located within the mobile terminal 20 and located outside of the system on chip 21.
  • the fingerprint sensor 42 collects fingerprint data of the user and transmits it to the secure processor 31 or other authentication component via the fingerprint input interface 242 to authenticate the identity of the user. Only when the user authentication based on fingerprint recognition passes, the mobile payment is executed or further executed.
  • the fingerprint input interface 242 can be an SPI, and of course can be other types of interfaces.
  • the fingerprint input interface 242 can be used to collect the fingerprint data of the user for the first time and further store the fingerprint data in the secure memory 45 through the storage interface 245 or transmit the fingerprint data to the line system bus 210 through the isolation memory 36 or the bus bridge. Further transfer to system memory 22 is saved.
  • the security processor 31 or other component in the secure processor system 23, such as a fingerprint reader can read the saved fingerprint data from the secure memory 45 or system memory 22 and the newly acquired fingerprint data. Do comparisons to achieve user authentication.
  • Port 242 can also be replaced by other types of interfaces, such as interfaces for transmitting iris data, voiceprint data, face data, or scent data.
  • User authentication at this time is no longer based on fingerprint recognition, but may be Based on iris recognition, voiceprint recognition, face recognition, or odor recognition.
  • Corresponding sensors can be: iris sensors, voiceprint sensors, image sensors for capturing facial images, or odor sensors. That is, by collecting user-specific biometric data and passing it to the secure processor system 23 through the relevant interface, authentication of the relevant user identity can be achieved.
  • the secure processor system 23 may include a biometric input interface that supports all of the above types of biometric data to enable more flexible user identity authentication, and the figures referred to in the embodiments are for illustration only.
  • biometric input interfaces may be SWP interfaces, and of course other types of interfaces, such as SPI interfaces or I2C interfaces.
  • the plurality of interfaces 24 may further include a secure input interface 243, a peripheral interface 244, and a storage interface 245.
  • the security input interface 243 is configured to receive user information related to mobile payment input by the user.
  • the user information includes a password input by a user, a user instruction, or a financial transaction amount.
  • the user instruction can be an instruction to agree, stop or continue to move the payment. Therefore, the secure input interface 243 needs to be coupled to an input device 43 to receive the user information through the input device 43.
  • the input device 43 may be a touch screen or button located within the mobile terminal 20 for performing input.
  • Peripheral interface 244 is configured to indicate to the user via peripheral device 44 that the mobile payment is being performed.
  • the peripheral device 44 can be a pointing device and the peripheral interface 244 is coupled to the pointing device 44.
  • the pointing device 44 can be an indicator light, a speaker or a vibrator for playing sound for alerting the user that the mobile payment is being or has been or will be performed by a light signal, sound or vibration.
  • the secure input interface 243 can be an I2C interface or other type of interface.
  • Peripheral interface 244 can be a GPIO interface or other type of interface.
  • the storage interface 245 can be coupled to a secure memory 45 outside of the system on chip 21, which can be an SPI interface or other type of interface.
  • the secure memory 245 can be used to store the secure operating system software and at least one secure application.
  • the secure memory 45 includes memory with enhanced features such as physical and logical attacks for securely storing secure operating system software and at least one secure application.
  • the security processor 31 is configured to read the security operating system software and the at least one security application software from the secure memory 45 through the storage interface 245, and run the security operating system software and the at least one security application software.
  • the storage connection The port 245 is a dedicated interface
  • the secure memory 45 is a processor dedicated to secure processing, so that the reading of the secure operating system software and the at least one secure application software is performed through the dedicated storage interface 245 without dependency.
  • the secure memory 45 can be a rewritable non-volatile memory such as Flash.
  • the secure memory 45 is integrated on a second semiconductor chip that is different from the first semiconductor chip on which the system on chip 21 is located. Since the secure memory 45 is dedicated to storing the secure operating system software and at least one secure application software, it is not used to store non-secure software, achieving higher security.
  • the data stored in the secure memory 45 is different from intermediate data or temporary data and can be stored for a long time.
  • the temporary data stored by the random access memory 32, or intermediate data or memory data is process data generated by running a software that does not need to be stored for a long period of time, but may be lost as the device or device loses power.
  • the security processor 31 may trigger the loading of the secure operating system software and the at least one secure application software from the secure memory 45 into the random access memory 32 after power up or based on user indications or other conditions, the random access memory 32 being operationally related
  • the software provides the storage space needed.
  • the secure memory 45 function may also be replaced by an internal memory within the secure processor system 23 in the event that the storage process evolves.
  • the internal memory may be an on-chip ROM, or an electrically erasable programmable read-only memory (EEPROM) or other on-chip non-volatile memory for storing the secure operating system software.
  • EEPROM electrically erasable programmable read-only memory
  • the internal memory allows the secure processor system 23 to store the secure operating system software and the at least one secure application without relying on external memory, which is highly secure and only results in higher costs.
  • a plurality of processors including the at least one central processing unit 211 and the secure processor system 23 are integrated, which can reduce the implementation cost and area of the entire system, and the secure processor system 23 Safety isolation from other non-secure components ensures safety.
  • the NFC interface 241, the fingerprint input interface 242, and the secure input interface 243 and the peripheral interface 244 for inputting user information are integrated in the secure processor system 23, and the information collection related to these interfaces will no longer be like the conventional system.
  • the transmission of NFC information, fingerprint data, user information, and the like is made more secure.
  • the system bus 210 and the secure bus 35 are coupled by an isolated memory 36 under the security isolation. That is, located outside the secure processor system 23 At least one processor and the secure processor system 23 interact with data or instructions via the isolated memory 36.
  • the at least one processor including central processing unit 211, cannot directly access any of the components of security processor system 23 other than isolation memory 36.
  • the at least one central processing unit 211 can be coupled to the secure processor system 23 via the system bus 210 and the isolated memory 36 by the general operating system software to interact with the secure processor System 23 communicates, the content of which includes data or instructions, such as passing data to at least one component within secure processor system 23.
  • the isolated memory 36 is a dedicated interaction channel for the security processor system 23 to interact with the outside world, or even a unique channel, that is, a mailbox box for realizing data or information interaction, avoiding being directly directly from the outside of the at least one processor. Access to any of the components or modules of the random access memory 32 or the secure processor system 23 may improve security.
  • the isolated memory 36 is preferably a power-down volatile memory such as a RAM, but may be replaced with a non-power-down volatile memory such as a ROM.
  • a non-power-down volatile memory such as a ROM.
  • the isolated memory 36 of FIG. 3 of the present embodiment may be replaced by a other type of safety isolation device, such as a bus bridge.
  • the bus bridge is a bus that spans between the secure bus 35 of the secure processor system 23 and the system bus 210.
  • the bus bridge is dedicated to transferring data or information between two different security buses in place of the function of the isolated memory 36, coupling the system bus 210 to the secure bus 35.
  • the data that can be transmitted on the bus bridge can be further processed to improve the security.
  • the data transmitted on the bus bridge needs to undergo special encryption and decryption processing, which is not limited in this embodiment.
  • Security isolation is achieved by isolating memory 36 or a safety isolation device such as a bus bridge, and at least one processor other than the secure processor system 23 is not free to access memory or registers within the secure processor system 23.
  • the secure processor system 23 can selectively couple one to the system bus 210.
  • the data read by the processor is transmitted to the processor through the secure isolation device, and the secure processor system 23 does not want the data acquired by the processor to be transmitted to the processor through the secure isolation device.
  • the security processor system 23 does not want the data acquired by the processor to include fingerprint data acquired through the fingerprint input interface 242, or secure temporary data temporarily stored in the random access memory 32 or loaded in the random access memory 32.
  • the secure operating system software and the at least one secure application software are examples of the data acquired by the processor to include fingerprint data acquired through the fingerprint input interface 242, or secure temporary data temporarily stored in the random access memory 32 or loaded in the random access memory 32.
  • Security isolation can be achieved between the secure processor system 23 and the at least one processor via the dedicated pass lanes and by data or instruction interaction.
  • the isolated memory 36 or bus bridge is one form of the dedicated interactive channel.
  • the dedicated interaction channel can be the only channel coupled between the secure processor system 23 and the at least one processor.
  • the secure processor system 23 in FIG. 3 or FIG. 4 may further include a secure boot memory 33 coupled to the secure bus 35.
  • the secure boot memory 33 stores the boot program instructions required for the security processor 31 to initialize.
  • the security processor 31 initializes the security processor 31 by reading the bootstrap program instructions from the secure boot memory 33 prior to running the secure operating system software and the at least one secure application software.
  • at least one central processing unit 211 may first power up, and then trigger the security processor system 23 to power up.
  • the secure boot memory 33 is similar to the BIOS in a conventional PC, and it can be guaranteed that each time the boot of the secure processor system 23 is read from the bootloader in the secure boot memory 33.
  • the instruction starts and the startup is guaranteed to be safe.
  • the secure boot memory 33 is preferably an on-chip ROM.
  • the security processor 31 when the security processor system 23 is powered on, the security processor 31 is configured to read the boot program instructions from the secure boot memory 33, and the security is performed by the boot program instructions. Operating system software is loaded into the random access memory 32 to run the secure operating system software. Further, the security processor 31 may launch one or more security applications after the security processor system 23 is powered on, ie load one or more security applications into the random access memory 32 to run the security. Application system software. Alternatively, the security processor 31 can receive a trigger from a user command or other condition to launch the secure application.
  • the security processor 31 when the security processor 31 reads the boot program instruction from the secure boot memory 33, it may undergo a decryption process. That is, stored in the secure boot memory 33 is an encrypted bootstrapping instruction.
  • the boot program instruction 33 acquires the boot program instruction, the boot program instruction is decrypted by the decryption logic circuit 51 to obtain a decrypted boot program instruction, and the decrypted boot program instruction is used to initialize the secure processor 31, To further ensure startup security.
  • the decryption logic circuit 51 can be hidden in the layout of the system on chip 21, that is, the various partial circuits in the decryption logic circuit 51 can be dispersed in different parts of the layout of the system on chip 21, so that it is difficult to be cracked by the outside world. Increased security.
  • the OTP memory 34 in FIG. 3 is configured to store security parameters of the security processor system 23, and the security parameters may optionally include a root key, a calibration parameter, a configuration parameter, or an enable parameter. At least one.
  • the root key is used to generate other keys required by the secure processor system 23 to perform at least one type of encryption and decryption.
  • the calibration parameters include parameters required to calibrate at least one component of the safety processor system 23, such as calibration parameters of one or more anti-attack sensors 39, to calibrate the anti-attack sensor 39.
  • the configuration parameters include configuration parameters of at least one component within the security processor system 23, such as configuration parameters of the random number generator 304, such as the configuration of the length of the random number generated by the random number generator 304.
  • the enabling parameters include parameters that control at least one component of the safety processor system 23 to be turned “on” or "off".
  • the enabling parameter may enable enabling control of a portion of the component, such as the anti-attack sensor 39.
  • the configuration of the enable parameters is implemented by performing programming in the OTP memory 34.
  • the enable parameter is configured to be active, related components, such as anti-attack sensor 39, are turned on so that after the system-on-chip 21 is manufactured, whether the functionality of at least one of its components is still available is configurable.
  • the enabling parameters may also include life management cycle parameters for enabling management of portions of the secure processor system 23 at different times. For example, whether the partial key saved in the secure processor system 23 is readable can be configured by the life management cycle parameter.
  • the OEM needs to read the relevant key due to the need for OEM (Original Equipment Manufacturer) debugging using the system on chip 21, and can be in the OTP memory 34 when the debugging is completed.
  • the security parameters may be programmed into the OTP memory 34 to effect calibration, configuration or setup of the secure processor system 23, or for some of the device functions within the secure processor system 23. Can be turned off or disabled.
  • the OTP memory 34 allows some functions within the secure processor system 23 to be set or changed after the system on chip 21 is manufactured, improving design flexibility after fabrication.
  • the OTP memory 34 is further configured to store a patch instruction of the boot program instruction required by the security processor 31 to initialize.
  • the patch instruction can be a supplement to the bootstrap instructions or a replacement for some of the programs.
  • the system-on-chip 21 when the system-on-chip 21 is manufactured, if it is found that the boot program instructions applied to the secure processor system 23 are insufficient, and the information or data in the secure boot memory 33 is not rewritten, the death can still pass through the OTP memory 34. Burning related patch instructions to compensate for the lack of existing bootloader instructions or errors makes the implementation more flexible.
  • the secure processor 31 When the secure processor 31 is booted, a portion of the patched program instructions can be read from the OTP memory 34 in place of at least a portion of the boot program instructions read from the secure boot memory 33.
  • the security processor 31 when the security processor 31 reads a partial boot program instruction from the secure boot memory 33, it can jump to the OTP memory 34 to read the relevant patch command, and can jump back to read the secure boot memory 33 if necessary. Other bootstrap instructions for safe boot.
  • OTP memory 34 can be further added to the OTP memory 34, such as authenticating data or information read from the OTP memory 34 by some security authentication devices, and performing power abnormality detection on the OTP memory 34.
  • the alarm is improved by performing an error detection and alarm on the OTP memory 34, encrypting the read information in the OTP memory 34, or using the data storage address disorder in the OTP memory 34.
  • OTP memory 34 can be a non-power-down volatile memory.
  • the random access memory 32 in FIG. 3 is integrated in the system on chip 21, and is difficult to implement using EEPROM due to process and the like, but can be implemented by SRAM, DRAM, SDRAM or DDRSDRAM, etc.
  • the capacity of KB (kilobytes).
  • the data in the random access memory 32 may be encrypted data or its data security may be improved by security means such as data storage address out of order.
  • the secure processor system 23 also includes a DMA controller 37 coupled to the secure bus 35.
  • the DMA controller 37 is for reading data from the random access memory 32 and outputting it to the secure bus or writing data to the random access memory 32 through the secure bus.
  • the DMA controller 37 functions to replace the security processor 31 for data transfer and relocation.
  • the specific working principle can be referred to the description of the prior art, and details are not described herein.
  • the secure processor system 23 also includes an anti-attack system to increase security.
  • the anti-attack system can include various types of anti-attack means or devices, such as the attack-resistant metal layer 38 and the anti-attack sensor 39.
  • the anti-attack sensor 39 is configured to detect whether there are abnormalities in various operating parameters of the secure processor system 23, and generate a trigger signal and transmit a trigger signal to the secure processor system 23 when the abnormality occurs. At least one of the following operations is triggered: the security processor system 23 performs an alert, the secure processor 31 resets, or at least one of the random access memory 32 or the secure processor system 23 is reset or emptied.
  • the operating parameter includes at least one of voltage, current, clock frequency, temperature, or laser intensity. Therefore, as shown in FIG. 6, the anti-attack sensor 39 may include one or more of a voltage monitor 61, a current monitor 62, a clock frequency monitor 63, a temperature monitor 64, or a laser intensity detector 65, for The security of the secure processor system 23 is described.
  • the voltage monitor 61 is configured to detect whether the voltage of the at least one component of the secure processor system 23 or its internals is normal, and to report the abnormality to the secure processor system 23 when there is an abnormality in the voltage.
  • the voltage monitor 61 determining whether the voltage is abnormal may include comparing the detected voltage to a voltage threshold or matching the data to determine if the voltage is within a normal range or if a predetermined voltage threshold is reached. When the voltage is within the normal range or does not reach the preset voltage threshold, the abnormality is not reported or reported to the normal state; otherwise, the voltage monitor 61 reports an abnormality.
  • the voltage monitor 61 may include a detecting part (ie, a sensor) for sensing a voltage and a determining part for comparing or matching processing.
  • the security processor 31 or component can send an alarm instruction to the peripheral interface 244 through the safety bus 35, and send an alarm indication signal to the peripheral device 44 through the peripheral interface 244 to implement alarming to the user.
  • the security processor 31 may perform a reset operation after receiving the abnormal report, or may selectively trigger the random access memory 32 or the secure processor system 23 in the secure processor system 23 by the secure processor 31 or the component.
  • One or more registers are reset or cleared.
  • the voltage monitor 61 can recognize the outside Boundary attacks, such as voltage anomalies caused by external voltage spike attacks and perform corresponding operations to prevent data or information leakage. Some of the calibration parameters of the voltage monitor 61 can be stored in the OTP memory 34.
  • the current monitor 62 is configured to detect whether the current of the safety processor system 23 or at least one component thereof is abnormal, and may selectively include a component that detects the current and a component that determines the abnormality of the current, and executes when an abnormality occurs. Corresponding operations such as alarm operation, reset or emptying to accurately identify the current anomaly caused by external attacks.
  • the clock frequency monitor 63 is configured to detect whether there is an abnormality in the operating clock frequency of the at least one component of the secure processor system 23 or therein, and perform a corresponding alarming operation or resetting operation when an abnormality occurs, and optionally include detecting the clock frequency
  • the components and components that determine the abnormal clock frequency to accurately identify the abnormality or instability of the working clock caused by external attacks. Due to the complexity of the clock structure of the entire system, the clock frequency delivered to the secure processor system 23 is multi-frequency multiplied or divided, and the frequency attack is more difficult. Reducing the clock frequency is generally advantageous for external attacks, which makes it desirable for the outside world to more easily locate and change the clock frequency of the operating clock supplied to the secure processor system 23.
  • the clock conversion of the complex system makes it difficult for the external device to accurately locate the clock of the specific security processor system 23, so the clock frequency monitor 63 can be used to detect the clock associated with the security processor system 23 to implement anti-attack detection. .
  • the clock frequency monitor 63 can be used to detect not only the operating clock of the secure processor system 23 but also the source clock that generates the operating clock, that is, the divided or multiplied clock of the operating clock.
  • the principle of the temperature monitor 64 is similar to that of other previously mentioned detectors for detecting whether the temperature of the safety processor system 23 or at least one component thereof is abnormal and performing a corresponding alarm operation when an abnormality occurs. Or a reset operation, which may selectively include a component that detects temperature and a component that determines an abnormal temperature, and recognizes an abnormal temperature change caused by an external attack to improve safety.
  • the temperature monitor 64 for implementing the anti-attack can be multiplexed with other temperature sensors inside the system on the chip for implementing thermal protection or thermal retraction, in addition to the thermal protection function, and also prevents the external system from damaging the system with low temperature attacks.
  • the laser intensity detector 65 is then used to detect whether the laser signal strength of the security processor system 23 or a portion thereof is beyond a preset threshold to identify an abnormality and perform a corresponding alarm, reset or clear operation when an abnormality occurs.
  • the laser intensity detector 65 is mainly used to prevent external laser attacks. For example, when an external device invades the security processor system 23 by using a laser cutting technique, the laser intensity detector 65 can detect the laser signal, or detect that the intensity of the laser signal exceeds the threshold, and touch Send the corresponding operation, such as the alarm, reset or empty operation described earlier.
  • the attack resistant metal layer 38 is formed based on a metal mask layer.
  • FIG. 7 a schematic cross-sectional view of the first semiconductor chip 70 in the vertical direction is shown, and the first semiconductor chip 70 includes a semiconductor physical device 72 at the bottom layer.
  • the semiconductor physical device 72 includes other parts of the system-on-chip 21 except the attack-resistant metal layer 38, including modules, functional devices, or circuits for implementing signal or information processing functions. For example, the description of the corresponding parts of FIGS. 2 to 4 is shown.
  • Located above the semiconductor physical device 72 is usually one or more metal mask layers, wherein one or more metal mask layers are specially designed to form the anti-attack metal layer 38, and are fabricated by a semiconductor integrated circuit.
  • the metal mask layer of the uppermost layer can be processed only to form the attack-resistant metal layer 38, and all of the multilayer metal mask layers can be used to form the attack-resistant metal layer 38.
  • the attack resistant metal layer 38 can be one or more layers and overlying the semiconductor physical device 72. Therefore, it can be understood that the attack-resistant metal layer 38 in the system on chip 21 can be located at least one top layer of the plurality of semiconductor layers formed by the first semiconductor chip 70, except for the attack-resistant metal layer 38 in the system on chip 21. Other components or modules or units may be located on the bottom layer of the plurality of semiconductor layers. Wherein the at least one top layer is located above the bottom layer.
  • FIG. 8 a schematic diagram of a layout layout of the first semiconductor chip 70 in the horizontal direction is illustrated, wherein the anti-attack metal layer 38 may cover at least the mesh structure of the first semiconductor chip 70 on the layout of the layout.
  • the optional attack resistant metal layer 38 may be other shapes than the mesh structure in the layout of the layout.
  • the attack-resistant metal layer 38 can detect the intrusion of the object and pass the SoC.
  • the circuitry associated with the attack-resistant metal layer 38 performs an anti-attack operation such as alarming, resetting, or clearing.
  • the attack resistant metal layer 38 can generate an electrical signal upon detection of the intrusion that can reflect changes in electrical characteristics on the attack resistant metal layer 38 caused by the intrusion, such as changes in voltage or current.
  • the electrical signal can be detected by circuitry associated with the anti-attack metal layer 38 that is coupled to the secure processor system 23.
  • the circuit can generate a trigger signal and transmit the trigger signal when receiving the electrical signal generated by the anti-attack metal layer 38.
  • the attack-resistant metal layer 38 may be Shielding, which may cover all of the system-on-chips 21 located on the first semiconductor chip 70, or may cover all of the secure processor system 23 only on the layout layout. Or a critical portion of the secure processor system 23, such as only the security processor 31 or the random access memory 32, etc., to increase security and reduce the cost associated with arranging the attack resistant metal layer 38. As shown in FIG. 8, the attack-resistant metal layer 38 covers all of the secure processor system 23 on the layout layout to ensure security.
  • system bus 210 or the secure bus 35 may each include at least one of an AHB or an APB.
  • Different portions or elements or circuits in the secure processor system 23 can be further divided into different levels of security, and connections using different levels of bus technology can meet the rate requirements and security requirements of different components within the secure processor system.
  • the security bus 35 can adopt the bus transmission mode in which the AHB and the APB are combined, the security level of the AHB and the APB is different, and the transmission rate may be different.
  • the transmission rate of the AHB may be higher than the APB, but the security level may be lower than the APB.
  • the coupling between different components may employ AHB technology, while the coupling between the security processor 31 and the cryptographic system 30 employs APB technology.
  • the specific bus transmission mode may also have other implementation manners, which are not described herein.
  • the data or related address transmitted on the secure bus 35 can be encrypted, scrambled or CRCed to avoid the related data or address being cracked by the outside, ensuring the privacy of the data and address on the secure bus 35 and Integrity.
  • a read/write initiating component (Master) in the secure processor system 23 accesses another component (Slave) through the secure bus 35
  • the read/write address of the secure bus 35 that is, the master occupying the secure bus 35
  • the address of the device with Slave can also be handled securely such as scrambling or interleaving.
  • the cryptosystem 30 includes at least one of the following: an encryption and decryption device 301, an authentication device 302, a key manager 303, and a random number generator 304.
  • the encryption and decryption device 301 is configured to perform encryption and decryption processing or authentication processing on at least one of the data in the security processor system 23.
  • the data stored in the random access memory 32 by the security processor 31 may be encrypted and encrypted.
  • the latter data is stored in the random access memory 32; conversely, before the secure processor 31 reads the data from the random access memory 32, the encryption/decryption device 301 can decrypt the relevant data and provide the decrypted data to the secure processor 31.
  • the secure processor 31 is enabled to process the decrypted data.
  • the encryption and decryption device 301 can encrypt the data or information transmitted by the security processor system 23 to the external device through any one of the interfaces 24, and decrypt the data transmitted by the external device through the corresponding interface for the security processor system. 23 use.
  • the encryption and decryption algorithm used by the encryption/decryption device 301 may be a symmetric or asymmetric encryption/decryption algorithm, or alternatively an authentication algorithm such as a hash algorithm.
  • the encryption and decryption algorithms include, but are not limited to, various types of cryptographic algorithms specified by international or Chinese, such as DES (Data Encryption Algorithm), 3DES (Triple Data Encryption Standard, Triple DES), AES (Advanced Encryption Standard, Advanced Data Encryption). Standard), RSA algorithm, ECC (Elliptic Curves Cryptography), and the like.
  • the hash algorithm may include MD5 (Message-Digest Algorithm 5), SHA (Secure Hash Algorithm), and the like.
  • the encryption and decryption device 301 can also support private exclusive encryption and decryption algorithms of various countries, such as SM2, SM3 or SM4 issued by the China Cryptographic Office.
  • the encryption and decryption device 301 also optionally supports an encryption/decryption algorithm combination mode, such as HMAC-SHA256 (Hash Message Authentication Code-Secure Hash Algorithm 256, Hash Message Authentication Code-Secure Hash Algorithm 256).
  • HMAC-SHA256 Hash Message Authentication Code-Secure Hash Algorithm 256
  • Hash Message Authentication Code-Secure Hash Algorithm 256 can also be designed to adopt the Side Channel Attack technology to enhance the security of the algorithm in the hardware circuit implementation.
  • the authentication device 302 is configured to authenticate at least one of the data in the security processor system 23, and the authentication may include hash authentication, for example, interacting with the security processor system 23 through any interface.
  • the data is processed for authentication.
  • the authentication device 302 hashes the relevant data and writes the hashed data to the secure The memory 45; when the security processor 21 needs to read the data from the secure memory 45, the data is first sent to the authentication device 302 for de-hashing operation, and only if the hash-success authentication is successful, the data is considered not to be invaded or modified.
  • the data is then sent to the security processor 21 for security.
  • the authentication device 302 may be further configured to perform the fingerprint recognition based user authentication mentioned in the previous embodiment.
  • a random number generator 304 is configured to generate a random number for use as a unique identifier of a seed or chip that generates a key required for at least one type of encryption, the unique identifier of the chip being used to identify the System on chip 21 or secure processor system 23.
  • the random number may be a true random number or a pseudo random number.
  • Key manager 303 for generating, distributing, or destroying in the secure processor system 23 The key required to perform the encryption and decryption process or authentication.
  • the key manager 303 can receive the random number generated by the random number generator 304, and generate a key required for encryption and decryption based on the random number, and generate the relevant key. It is provided for use by the encryption/decryption device 301, and the key manager 303 can maintain the key valid for a preset time, and when the time is exceeded, the encryption/decryption device 301 is notified to prohibit the continued use of the key. That is to say, the key manager 303 destroys the key when a key expires, ensuring that the usage time of any one or more keys is limited, thereby improving security.
  • the key manager 303 can acquire the seed from the random number generator 304 and generate a new key when a new seed is needed, and provide the new key to the encryption and decryption device 301 for use in place of the original key.
  • one or more functions of the cryptographic system 30 can be implemented by the security processor 31 to reduce the cost, but if the independent cryptographic system 30 as shown in FIG. 3 is used to implement the related functions, it is equivalent to using high security.
  • the hardware accelerator implements related functions, so that operations such as encryption and decryption can be separated from other operations of the security processor 31, and security can be improved.
  • the security processor 31 is further configured to perform the user authentication by using the fingerprint data transmitted by the fingerprint input interface 242.
  • the authentication function can be implemented by another fingerprint authenticator (not shown) in the secure processor system 23.
  • the fingerprint authenticator is equivalent to a hardware accelerator for faster processing and security.
  • the secure operating system software and the at least one secure application software are stored by the secure memory 45, and the secure operating system software can also be stored by the system memory 22, similar to FIG. And at least one security application.
  • the system memory 22 can be located on another second semiconductor chip than the first semiconductor chip on which the system on chip 21 is located. As shown in FIG. 2, the system on chip 21 and the system memory 22 can be coupled through an inter-chip dedicated interface.
  • the system memory 22 can include a secure storage area and a normal storage area that are isolated from each other.
  • the secure storage area is configured to store the secure operating system software and at least one secure application software; the normal storage area is configured to store the general operating system software.
  • the at least one central processing unit 211 is configured to acquire the general operating system software from the normal storage area and run the general operating system software through the inter-chip interface; the security processor 31 is configured to pass the The inter-chip interface, the system bus 210, and the secure bus 35 acquire secure operating system software and the at least one secure application software from the secure storage area, and run the secure operating system software and the at least one secure application software.
  • Separate secure storage areas and normal storage areas mean that The general operating system software running on the central processing unit 211 or other common software based on the general operating system software can only read and write the normal storage area, and cannot read and write the secure storage area.
  • the secure storage area is an area dedicated to executing a secure application, accessed and read and written by the secure processor 31. Since system memory 22 can store both secure and non-secure software, there is no need to rely on additional dedicated memory like secure memory 45, which reduces cost. Alternatively, system memory 22 and secure memory 45 may be Flash in various embodiments of the invention.
  • the embodiment of the invention proposes a system on chip 21 that can support multiple security application services.
  • the security processor system 23 can also be called a Security Protection Module (SPM), which is similar in function to the security components in the bank card, but achieves higher security and integration, and its security can be achieved.
  • SPM Security Protection Module
  • CC EAL4+ Common Criteria Evaluation Assurance Level 4+
  • the central processing unit 211 and the secure processor system 23 in the on-chip system 21 adopt the same integrated circuit fabrication process, and the performance is more optimized.
  • the solution of this embodiment integrates various external interfaces in the security processor system 23, and the transmission of related data is no longer dependent on the TEE of the central processing unit 211.
  • FIG. 9 a schematic diagram of an application scenario of a system memory 22 as a secure operating system software and a memory of the at least one secure application software is presented.
  • the usage scenario may not involve any dedicated secure memory, and the implementation cost is low.
  • the secure processor 31 can access the system memory 22 via the secure bus 35, the isolated memory 36 (or bus bridge), and the system bus 210 to write data to the secure memory area in the system memory 22.
  • the data in the secure storage area is read to enable reading or writing of the secure operating system software and the at least one secure application in the secure storage area.
  • the data or information may be encrypted or authenticated when the secure storage area and the security processor 31 interact to ensure data privacy and data not to be tampered with.
  • the secure processor system 23 has dedicated access rights required to access the secure storage area.
  • the security processor 31 can be further coupled to the NFC processor 41 via the NFC interface 241 and interact with the NFC peer to interact with the NFC information associated with the mobile payment through the NFC processor 41, such as The mobile payment instruction, the mobile payment data, the NFC authentication information, and the like are executed, and the operation related to the mobile payment is executed, and the calculated result is stored in the secure storage area.
  • the result includes payment information of the current mobile payment, such as transaction amount or transaction time.
  • FIG. 10 a schematic diagram of an application scenario using a dedicated secure memory 45 as a secure operating system software and a memory of the at least one secure application is presented.
  • the secure processor 31 can access the secure memory 45 via the secure bus 35 and the storage interface 245 to enable reading or writing of the secure operating system software and the at least one secure application.
  • the security processor 31 receives NFC information related to the mobile payment from the NFC peer through the NFC processor 41, and performs a mobile payment operation processing operation, and stores the processed data result in the secure memory 45.
  • the scenario of FIG. 10 is safer because it can prevent data from being transmitted on the system bus 210 with a lower security level, reducing the risk of exposure of data to be transmitted.
  • a schematic flowchart of the method for performing the mobile payment related to the system on chip 21 may be as shown in FIG. 11, including: in S111, the central processing unit 211 is powered on. In S112, the central processing unit 211 further triggers the boot of the secure processor system 23 upon completion of booting, including launching the secure processor 31. In S113, the secure operating system software and the at least one secure application are loaded into the secure processor system 23, for example into the secure processor 31 or into the cryptographic system 30. Specifically, relevant software data can be obtained from the secure storage area of the dedicated secure memory 45 or the system memory 22 and loaded accordingly.
  • the security processor 31 or the cryptographic system 30 performs secure authentication of the secure operating system software and the at least one secure application, such as at least one of performing a program integrity check and a signature check by the authentication device 302. Operation, such as optional CRC check, etc. If the check fails, then in S115, the secure processor system 23 is reset, for example, the secure processor system 23 can be selectively restarted. If the check passes, then in S116, the data of the relevant software is imported into the random access memory 32, so that the secure processor 31 performs the arithmetic operation of the related software using the storage space provided by the random access memory 32.
  • the secure processor system 23 or some of its components, such as the security processor 31, can enter a low power state, i.e., a standby state.
  • the security processor 31 can temporarily stop working in this state to save power.
  • the mobile payment application software or NFC processor 41 wakes up the secure processor system 23 via the NFC interface 241.
  • the NFC processor 41 or the mobile payment application can be used to wake up the secure processor system 23 such that the secure processor system 23 or the secure processor 31 therein recovers from a low power state to an awake state.
  • the security processor 31 may determine whether the mobile payment application has been turned on.
  • the security processor 31 needs to perform the determination to determine if the associated application has been turned on. If not, in S119, the security processor 31 needs to start the mobile payment application software, that is, read the relevant software data from the secure storage area of the external memory, such as the secure memory 45 or the system memory 22, and load it into the random access memory 32. In order to perform processing or operations related to the software application. If the mobile payment application has been turned on, then in S120, the security processor 31 performs normal payment transaction operations, including, for example, further information related to mobile payment interaction with the NFC processor 41, and performs with the storage space provided by the random access memory 32.
  • the related software operation obtains an operation result regarding the mobile payment, and the operation result includes intermediate data related to the transaction or a transaction result, such as a transaction amount or a transaction time.
  • the user may be required to enter an amount associated with the transaction or enter biometric data.
  • the biometric data is collected by the biometric sensor in the mobile terminal 20 and transmitted to the secure processor system 23 via the biometric input interface for user authentication or user authentication on the cloud side.
  • the fingerprint authentication-based user authentication can be implemented using a fingerprint input interface similar to that of FIG. 3, which is not described in this embodiment.
  • the security processor 31 stores the transaction result in an external memory such as the secure memory 45 or the secure storage area previously described to record the transaction information.
  • FIG. 12 a schematic diagram of an application scenario for performing voice signal encryption using secure processor system 23 is shown.
  • Communication processor 213 can transmit first communication data to or receive second communication data from the wireless access point.
  • the voice signal processor 214 may process the voice signal from the user to generate the first communication data transmitted by the communication processor 213, or to perform the second communication data received by the communication processor 213.
  • the voice signal required by the user is obtained, and the signal transmission direction is shown by a broken line in FIG.
  • the encryption and decryption device 301 in the cryptographic system 30 is further configured to perform encryption processing on the first communication data or decryption processing on the second communication data when the corresponding voice communication is performed. Therefore, the encryption/decryption device 301 can be used to perform encryption and decryption processing of communication data based on voice signals in addition to performing security operations related to mobile payment, and realizes diversification of security processing capabilities.
  • the communication processor 213 may include a baseband communication processor and RF processor.
  • the communication processor 213 can include a cellular communication processor or a short range communication processor. That is to say, the manner of communication transmission or the supported communication protocols can be various.
  • the wireless access point may be a WIFi access point, such as a WIFi router, and the communication processor 213 is a WIFi communication processor.
  • the wireless access point may also be a base station, such as a cellular communication access point supporting GSM, UMTS, WiMAX, TDS-CDMA, CDMA2000, LTE or 5G, where the communication processor 213 is one and the access. Point communication cellular communication processor.
  • the cellular communication access point can be, for example, an LTE base station, such as an eNodeB.
  • the speech signal can be a PS domain speech signal, such as a VoLTE speech signal.
  • the voice signal may also be a CS domain voice signal, such as a GSM, WCDMA or CDMA2000 voice signal.
  • the user can input a sound signal through an input device, such as a microphone, and transmit a sound signal to the voice signal processor 214 through the system peripheral interface 215 and the system bus 210, and the sound signal is processed by the voice signal processor 214.
  • Memory 36 (or bus bridge) and system bus 210 are transmitted to communication processor 213 for transmission of the encrypted data to the wireless access point by communication processor 213 for increased security.
  • the communication processor 213 receives the encrypted voice signal sent by the wireless access point, it will transmit to the encryption and decryption device 301 through a similar signal transmission path, and the decryption device 301 decrypts the voice information and transmits the voice information to the voice.
  • the signal processor 214 processes the signal by the speech signal processor 214 to obtain a sound signal.
  • the sound signal in this embodiment is an analog voice signal and can be played to the user through a speaker to realize the function of the user's secure call.
  • the decryption function of the encryption/decryption device 301 can also be implemented by the security processor 31.
  • FIG. 13 a schematic diagram of an application scenario in which user authentication based on fingerprint data is performed by a cloud side server is shown, and a specific signal transmission direction is shown by a broken line in FIG.
  • the encryption and decryption device 301 is further configured to perform encryption processing on the fingerprint data collected by the fingerprint sensor 42 to obtain encrypted fingerprint data.
  • the communication processor 213 sends the encrypted fingerprint data to a server for performing the user authentication through a wireless access point, and the server authenticates the fingerprint data to the communication processor 213 through the wireless access point.
  • the authentication result is returned, and the authentication result is provided to the security processor 31 so that the security processor 31 continues to perform related security operations, such as continuing the mobile payment operation, upon learning that the fingerprint data-based user authentication is obtained.
  • This type of authentication is also It is cloud side authentication, which reduces the overhead for the mobile terminal 20 to process authentication. Specifically, whether the user is authenticated by the security processor 31 or other components in the security processor system 23, or uploaded to the cloud side server for user authentication, the security processor system 23 needs to collect the fingerprint data collected by the fingerprint sensor 42. The pre-stored fingerprint data is compared to verify whether the authentication is passed.
  • the security processor 31 After the fingerprint data collected by the fingerprint sensor 42, the security processor 31 is triggered to perform the relevant authentication operation, and the security processor 31 triggers the acquisition of the pre-stored fingerprint data from the external memory, for example, reading from the secure memory 45 through the storage interface 245 like FIG.
  • the fingerprint data is taken or read through a secure storage area of system memory 22.
  • the pre-stored fingerprint data may be fingerprint data of the user previously captured by the fingerprint sensor 42 and stored in an external memory for subsequent comparison.
  • storing fingerprint data by using a dedicated secure memory 45 is a better choice.
  • the security processor 31 can store the fingerprint data obtained from the fingerprint sensor 42 into the secure memory 45 for the first time when the user fingerprint data is collected, so that the subsequent fingerprint data can be used for comparison. Avoiding confidential fingerprint data is transmitted over the less secure system bus 210, reducing the likelihood of data leakage.
  • a processing method in a mobile payment process is also provided, which is performed by the security processor system 23 in the aforementioned system on chip 21, wherein fingerprint authentication is taken as an example.
  • the security processor system 23 interacts with the NFC peer (such as a communication device such as a POS device) through the NFC interface 241 with the NFC information related to the mobile payment, and the NFC information may include a mobile payment instruction, for example, by security.
  • the processor system 23 requests the NFC peer to request a mobile payment request message or a connection setup message, and the security processor system 23 can further receive a response message from the NFC peer that agrees to establish a connection or request message.
  • the NFC information may further include mobile payment data, such as transaction amount or transaction time information sent from the NFC peer.
  • the NFC information may further include NFC authentication information, such as the security processor system 23 and the NFC peer performing mutual authentication to verify whether the other party is legitimate.
  • the NFC information is an information interaction between the secure processor system 23 and the NFC peer in order to complete the mobile payment.
  • the secure processor system 23 receives fingerprint data from the fingerprint sensor 42, which is used in the mobile payment for user authentication based on fingerprint recognition.
  • the user authentication is used to verify whether the user using the mobile terminal 20 is a legitimate user, and the authentication may be performed by the secure processor system 23 or by the cloud side server.
  • fingerprint recognition can also be replaced by other biometric authentication methods, such as iris recognition, voiceprint recognition, face recognition, or odor recognition. Due to the user's unique human characteristics, such as fingerprints or odors, the user can be distinguished from other users, thereby authenticating the user by comparing the data related to the feature with the pre-saved data.
  • the secure processor system 23 displays at least one piece of display information to the user through a user interface (UI).
  • the display information includes at least one of a user information input interface, a transaction interface of the mobile payment, or a transaction success interface.
  • the user interface is used to display relevant display information of the mobile payment to the user, including transaction amount or transaction time, etc., and may also selectively implement some user input, which may be formed on a hardware device such as a touch screen or a display screen.
  • the touch screen or display screen may be specifically coupled to the secure processor system 23 via a secure input interface 243. Or alternatively, the touch screen or display screen can be coupled to system bus 210 via system peripheral interface 215.
  • the security processor system 23 needs to transmit the display information to be displayed to the system peripheral interface 215 via the secure bus 35, the isolated memory 36 (or bus bridge), and the system bus 210, and is transmitted to the system peripheral interface 215 through the system peripheral interface 215.
  • the touch screen or the display screen is displayed so that the user can view the display information on the user interface formed by the touch screen or the display screen.
  • the user interface is formed by a UI software driver running by the at least one central processing unit 211 based on the universal operating system software, or is executed by the security processor 31 in the at least one security application software. Secure UI software drivers are formed. It can be understood that steps S15, S152 and S153 in the method do not have a strict execution order.
  • the related software functional unit may be A computer program product that can be stored in a computer readable storage medium.
  • the computer program product may include all of the general operating system software mentioned in the previous embodiment, the general application software based on the general operating system software, the secure operating system software, and at least one security application software based on the secure operating system software. Or part of the software.
  • At least part of the corresponding technical solution of the method can be embodied in the form of computer code, which can be stored in a storage medium, including a plurality of instructions for making a computer device (may be mentioned before) A mobile terminal, or a personal computer, etc.) performs all or part of the steps of the corresponding method.
  • the foregoing storage medium includes: a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or A medium such as a compact disc that can store program code.
  • a typical application scenario of the mobile terminal 20 mentioned in the embodiment of the present invention may be a mobile phone, such as various types of smart phones.
  • Each component within the system on chip 21, such as at least one processor or secure processor system 23, may include multiple transistors or logic gates and may operate with the necessary software drivers. Alternatively, some devices may optionally operate without software, such as a pure hardware accelerator.
  • the mobile payment in the embodiment of the present invention is a broad definition, which includes not only commercial and financial mobile payment services, but also other types of payment services such as public transportation, identity cards, and social security cards. That is to say, through mobile payment, the mobile terminal can connect with the communication peer to finally realize the interaction payment information with the server, and realize data transaction, data exchange or data settlement associated with one or more accounts in the mobile terminal.
  • the unit of the data transaction, the exchange, or the data settlement may include not only the currency, but also other units that can be used for realizing payment, redemption, or transaction settlement, such as a virtual currency, various types of credits, or a credit line. This embodiment does not limit this.
  • the account includes, but is not limited to, a personal account, a group account, or an organizational account. Compared with the payment behavior implemented only on the fixed terminal, the mobile payment implementation is more flexible, and the execution subject is the mobile terminal 20 shown in FIG. 2, which can better meet the requirement of performing payment anytime and anywhere.
  • the system on chip 21 mentioned in the embodiment of the present invention is applied to one mobile terminal 20, but can be applied to other processing devices that do not have mobile communication functions, such as a handheld device without mobile communication capability. . Therefore, the functions of some of the devices or units in the system on chip 21 mentioned in the embodiments of the present invention are not necessary, for example, at least one of the processors may be omitted, such as the image processing unit 212, the communication processor 213, and the voice signal processor 214. One or more of system peripherals 215, or image signal processor 217, etc., may optionally be omitted.
  • the central processing unit 211 or the system power management unit 216 may also be omitted and replaced by a control circuit that is simpler in function and design. Therefore, the form of the associated processing device including the system on chip 21 is also not limited.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Business, Economics & Management (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Software Systems (AREA)
  • Accounting & Taxation (AREA)
  • Signal Processing (AREA)
  • Strategic Management (AREA)
  • General Business, Economics & Management (AREA)
  • Health & Medical Sciences (AREA)
  • General Health & Medical Sciences (AREA)
  • Computing Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Bioethics (AREA)
  • Finance (AREA)
  • Mathematical Physics (AREA)
  • Biomedical Technology (AREA)
  • Telephone Function (AREA)
  • Storage Device Security (AREA)

Abstract

一种片上系统，集成于第一半导体芯片上，包括系统总线、耦合于所述系统总线的至少一个处理器、和耦合于所述系统总线的安全处理器系统。所述安全处理器系统包括安全处理器、第一存储器、多个接口和安全总线，所述安全处理器、第一存储器和多个接口均耦合于所述安全总线，且所述安全总线耦合于所述系统总线。所述安全处理器，用于运行安全操作系统软件和基于所述安全操作系统软件的至少一个安全应用软件，所述至少一个安全应用软件包括用于实现移动支付的移动支付软件。所述多个接口包括近场通信(NFC)接口和生物识别输入接口。

Description

一种片上系统和处理设备 技术领域
本发明涉及芯片技术领域，尤其涉及一种片上系统(System of Chip)和处理设备。
背景技术
移动支付(Mobile Payment)是指允许用户使用移动终端，例如手机、平板电脑、或可穿戴设备等，对所消费的商品或服务进行账务支付的一种服务方式。通过移动终端实现移动支付目前有三种方式，分别是安全数据(Secure Digital，SD)卡方案、用户识别模块(Subscriber Identity Module，SIM)方案、或近场通信(Near Field Communication，NFC)结合安全元件(Secure Element，SE)的全终端解决方案。目前近场通信结合安全元件的全终端解决方案正在成为实现移动支付方案的主流。并且，这几种解决方案已经开始出现融合的趋势。例如，安全元件也可以具有SIM功能或其他功能。
一种现有的全终端解决方案如图1所示，移动终端10通过其内部的近场通信单元101与销售点(Point of Sales，POS)机11通信，近场通信单元101和POS机11间的近距离无线通信连路12为双向通路，可采用各类合适的短距离无线通信协议实现，以实现移动支付中的基本无线通信功能。例如，通信连路12可用于从POS机11向移动终端10内部的近场通信单元101传输POS指令数据等。安全元件102则可以是与一个独立的中央处理单元(Central Processing Unit，CPU)103相耦合的部件，用于运行金融支付业务相关的各类功能，并存储与银行业务相关的密钥、证书等数据。在交易时，安全元件102从近场通信单元101收到POS指令数据，解析指令数据并根据金融交易协议进行相应回应。所述回应被近场通信单元101反馈给POS机11以完成移动支付中的数据传输，以实现移动终端10作为交易验证卡的功能。中央处理单元103则运行有通用操作系统软件1031，例如安卓(Android)系统软件，其用于对近场通信单元101和安全元件102进行控制，例如控制打开或关闭近场通信单元101和安全元件102。此外，移动终端10可包括输入单元104，输入单 元104可以是触摸屏，可以认为是一个用户界面(User Interface，UI)，用来与用户交互消息，使得用户可以通过该用户界面软件驱动的输入单元104上输入操作指令，以便指示操作系统软件1031和相关应用软件执行相关操作，也可包括交易的确认、或个人交易密码的输入等。POS机11作为一个交易的终端设备通过互联网接入网络侧的云服务器14，以实现通过服务器14计算并完成支付业务。位于网络侧的服务器14通常由银行或互联网公司等运营。
全终端的解决方案可包括线上支付和线下支付。在线下支付时，如图1所示，移动终端10与POS机11进行非接触式刷卡，即刷手机，近场通信单元101和安全元件102共同作用完成支付交易。在采用线上支付时，则可以不通过近场通信单元101实现，中央处理单元103和安全元件102此时可通过移动通信网络接入互联网实现线上支付，此时安全元件102相当于银行U盾的作用，用于存储并验证银行的证书，因此上述图1中近场通信单元101是可选的。具体地，请参见图1，在线上支付时，移动终端10可进一步包括一个移动通信单元105，用于代替线下支付时近场通信单元101的作用，其接入无线接入网(Radio Access Network，RAN)15。无线接入网15具体可以包括无线接入点，如基站。移动通信单元105通过该无线接入网15接入互联网，所述互联网与位于互联网中的服务器14连接，以实现利用服务器14接收指令数据或传输信息给安全元件102。安全元件102解析指令数据并根据金融交易协议进行相应回应，以便通过移动通信单元105将数据通过移动互联网传输给网络侧服务器14。此时移动通信单元105可以是一个运行无线蜂窝通信协议的单元，用于将移动终端10通过蜂窝无线通信链路13接入互联网。移动通信单元105也就是一个蜂窝通信处理器，具体可支持全球移动通信(Global System for Mobile，GSM)、通用移动通信系统(Universal Mobile Telecommunications System，UMTS)、全球微波互联接入(Worldwide Interoperability for Microwave Access，WiMAX)、时分-同步码分多址(Time Division-Synchronous Code Division Multiple Access TDS-CDMA)、码分多址2000(Code Division Multiple Access 2000，CDMA2000)、长期演进(Long Term Evolution，LTE)或5G(第五代)等蜂窝无线通信协议，以协助实现移动终端10的移动互联网功能。
中国专利申请201510201343.9提供了一种将安全元件102与中央处理单元103(或者可选地包括也移动通信单元105)集成在同一个半导体衬底上，即集成为一块主芯片106上的方案，并且安全元件102可以从主芯片106外部的存储单元中加载中央处理单元103需要的通用操作系统软件，如安卓或Windows操作系统软件。将多个部件集成在一个半导体衬底或半导体芯片上所形成的系统可以叫做SoC。通过将安全元件102和中央处理单元103集成在SoC上，显然可以达到很多好处，例如极大的降低成本，省略SoC在PCB(印制电路板)上的布局空间，使得安全元件102和中央处理单元103可以基于同样先进的集成电路制造工艺，而这种工艺提升意味着安全性提高。
随着移动应用场景的发展，安全元件102运行的应用软件种类越来越多，安全元件102的应用场景已经不限于移动支付，还可能包括一些SIM卡相关的软件，如通信运营商定制的应用软件。因此，采用集成方式实现的SoC的复杂度在变得越来越高，如何实现高集成度和复杂功能的SoC、且充分满足安全性要求就成为一个问题。例如，在中国专利201510201343.9中，可以由中央处理单元在通用操作系统环境之外形成一个安全域(Trustzone，TZ)。该TZ为一个可信执行环境(Trust Execute Environment，TEE)。用户可以在该TEE下输入一些与移动支付等安全应用相关的信息，并且该TEE与通用操作系统环境之间各自实现不同安全等级的应用操作，由于TEE是由中央处理单元所产生的环境，其安全性依然有待提高。例如，安全元件102可通过现有的TEE与外围设备交互某些特定信息，例如安全元件102经过TEE与指纹传感器交互指纹数据，由于相关信息的传输会经过TEE，这会降低所述信息交互的安全性。因此，如何在保证安全性的前提下，在SoC上实现基于NFC通信的移动支付业务就成为一个亟需解决的问题。
发明内容
本发明实施例提供了一种SoC和处理设备，以在高集成度的SoC中提高基于NFC通信的移动支付业务的安全性。
第一方面，本发明实施例提供了一种SoC，所述SoC集成于第一半导体 芯片上，包括：系统总线、耦合于所述系统总线的至少一个处理器、和耦合于所述系统总线的安全处理器系统；所述安全处理器系统与所述至少一个处理器间存在安全隔离；所述至少一个处理器包括至少一个中央处理单元，所述至少一个中央处理单元用于运行通用操作系统软件，并在所述通用操作系统软件的作用下通过所述系统总线与所述安全处理器系统通信；所述安全处理器系统包括安全处理器、第一存储器、多个接口和安全总线，所述安全处理器、第一存储器和多个接口均耦合于所述安全总线，且所述安全总线耦合于所述系统总线；其中，所述安全处理器，用于运行安全操作系统软件和基于所述安全操作系统软件的至少一个安全应用软件，所述至少一个安全应用软件包括用于实现移动支付的移动支付软件；所述第一存储器，用于提供所述安全处理器运行所述安全操作系统软件和所述至少一个安全应用软件所需的存储空间；所述多个接口包括近场通信NFC接口和生物识别输入接口；其中，所述NFC接口，用于经由NFC处理器与NFC对端交互与所述移动支付相关的NFC信息；所述生物识别输入接口，用于从生物识别传感器接收生物识别数据，所述生物识别数据在所述移动支付中被用于做基于生物识别的用户认证。可选地，所述NFC信息包括移动支付指令、移动支付数据或NFC认证信息中的至少一项。进一步地，在所述安全隔离下，所述至少一个处理器无法直接访问所述第一存储器或所述安全处理器系统中的至少一个寄存器。例如，所述至少一个处理器和所述安全处理器系统可以通过专用交互通道相耦合。
以上SoC集成了处理器和安全处理器系统的功能，可以降低整个系统的实现成本和面积，并且在安全处理器系统中实现了相当于是安全元件的功能，能够运行包括移动支付软件在内的至少一个安全应用软件。此外，该安全处理器系统内集成了属于自己的生物识别输入接口，能够方便的获取生物识别数据，并且该安全处理器系统与至少一个处理器存在安全隔离。当执行基于NFC通信的移动支付业务时，相对于通过中央处理单元的TEE转移用户生物识别数据给该安全处理器系统的方案，本方案安全性更高。
根据第一方面的描述，在一种可能的实现方式中，所述至少一个中央处理单元与所述安全处理器系统的通信包括数据交互或指令交互。所述指令可以是至少一个中央处理单元控制或操作所述安全处理器系统的指令，包括但不限于 启动指令、关闭指令、重启指令、睡眠指令、进入或退出低功耗状态指令、或暂停或恢复工作指令。通过以上交互过程，所述安全处理器系统的工作状态可以被所述至少一个中央处理单元控制，但是不会影响所述安全处理器系统中的数据的安全性。
根据第一方面的描述，在一种可能的实现方式中，所述安全处理器系统可用于实现安全元件的功能或SIM功能。其中，所述安全处理器等效为是实现了安全元件的功能，并且可以进一步集成其他功能。因此，至少一个安全应用软件还可包括SIM软件等其他安全应用软件，通过将这些软件功能在所述安全处理器系统中实现，可扩展该SoC的安全应用场景。
根据第一方面的描述，在一种可能的实现方式中，所述第一存储器可以是掉电易失性存储器，如随机存取存储器(RAM)。该第一存储器可以用于存储被加载的所述安全操作系统软件和所述至少一个安全应用软件，还可以进一步地用于存储运行所述安全操作系统软件和所述至少一个安全应用软件所产生的安全临时数据。所述安全临时数据是所述安全处理器运行所述安全操作系统软件和至少一个安全应用软件所产生的中间数据或中间运算结果或是其他无需长期存储的与安全应用软件或其运行相关的信息。因此所述RAM是一种掉电易失性存储设备，如SRAM(静态随机存储器)、DRAM(动态随机存储器)或SDRAM(同步动态随机存储器)，并且优选地是SRAM。由于RAM是集成于SoC内的，该RAM可以与所述至少一个中央处理单元使用同样的制造工艺，工艺实现比较容易。
根据第一方面的描述，在一种可能的实现方式中，所述多个接口还包括安全输入接口，用于接收用户输入的与移动支付相关的用户信息。可选地，所述用户信息包括密码、用户指令或金融交易金额。可选地，所述安全输入接口耦合于一个输入设备以通过所述输入设备接收所述用户信息。例如，所述输入设备可以是触摸屏或按键。在本实现方式中，由于用户信息的接口也被集成在所述安全处理器系统中，用户信息的采集也不再依赖于中央处理单元的TEE，可以实现更高的安全性。
根据第一方面的描述，在一种可能的实现方式中，所述多个接口还包括外设接口，用于通过外围设备向用户指示所述移动支付被执行。例如，该外围设 备是指示设备，且所述外设接口耦合于所述指示设备。该指示设备可以是指示灯、用于播放声音的扬声器或振动器，用于提醒用户所述移动支付正在或已经或将要被执行。在本实现方式中，由于外设接口也被集成在所述安全处理器系统中，指示信息的传输也无需再依赖于中央处理单元的TEE，可以实现更高的安全性。
根据第一方面的描述，在一种可能的实现方式中，所述安全处理器系统还包括耦合于所述安全总线的非掉电易失性的第二存储器，用于存储所述安全操作系统软件和至少一个安全应用软件；所述安全处理器用于从所述第二存储器读取所述安全操作系统软件和至少一个安全应用软件，并将所述安全操作系统软件和至少一个安全应用软件加载到所述第一存储器中以运行所述安全操作系统软件和至少一个安全应用软件。由于该第二存储器也是集成于SoC内，所有的由所述安全处理器执行的软件被长期存储于该第二存储器中，无需依赖SoC外部的存储器存储所述安全操作系统软件和至少一个安全应用软件，安全性高。
根据第一方面的描述，在一种可能的实现方式中，在所述安全隔离下，所述安全处理器系统还包括耦合于所述安全总线且用于实现所述安全隔离的安全隔离器件，所述至少一个处理器通过所述系统总线和所述安全隔离器件与所述安全处理器系统通信。进一步地，所述安全隔离器件包括隔离存储器或总线桥中的至少一项，所述隔离存储器或总线桥用于实现至少一个处理器和所述安全处理器系统交互数据或指令。例如，所述至少一个中央处理单元可以在所述通用操作系统软件的作用下通过所述系统总线和所述隔离存储器或总线桥耦合至所述安全处理器系统，以与所述安全处理器系统通信，该通信的内容包括数据或指令。该总线桥可以是一个跨接在所述安全总线和系统总线之间的总线。进一步地，在所述安全隔离下，所述至少一个处理器无法直接访问所述安全处理器系统中除了所述隔离存储器或总线桥外的任一部件。由于所述至少一个处理器和所述安全处理器系统仅将隔离存储器或总线桥中的任一个作为专用交互通道，甚至唯一交互通道，避免由所述至少一个处理器直接访问所述第一存储器或所述安全处理器系统中的任一部件或模块，可以提高安全性。
根据第一方面的描述，在一种可能的实现方式中，所述安全处理器系统还 包括耦合于所述安全总线的安全启动存储器，用于存储所述安全处理器初始化所需的引导程序指令；所述安全处理器在运行所述安全操作系统软件和至少一个安全应用软件前，通过从所述安全启动存储器获取所述引导程序指令以初始化所述安全处理器。该安全启动存储器是一个非掉电易失性存储器，如ROM，该安全启动存储器类似传统PC(个人电脑)中的BIOS(基本输入输出系统)，保证每次所述安全处理器系统的最初启动都是从该安全启动存储器开始，保证启动的安全。例如，当所述安全处理器系统上电时，所述安全处理器用于从所述安全启动存储器读取所述引导程序指令，在所述引导程序指令的作用下将所述安全操作系统软件加载到所述第一存储器中，以运行所述安全操作系统软件。
在上一实现方式中，可选地，所述引导程序指令是经过加密的引导程序指令；在所述安全处理器从所述安全启动存储器获取所述引导程序指令时，所述引导程序指令被解密逻辑电路解密以得到解密后的引导程序指令，所述解密后的引导程序指令被用于初始化所述安全处理器。该方案可进一步保证启动安全性。
根据第一方面的描述，在一种可能的实现方式中，所述安全处理器系统还包括耦合于所述安全总线的一次性可编程(OTP，One Time Programable)存储器，用于存储所述安全处理器系统的安全参数，所述安全参数包括根密钥、校准参数、配置参数、或使能参数中的至少一项。例如，所述根密钥用于产生所述安全处理器系统加解密所需的其他密钥。所述校准参数包括对所述安全处理器系统内至少一个部件做校准所需的参数。配置参数包括所述安全处理器系统内至少一个部件的配置参数。所述使能参数包括控制所述安全处理器系统内至少一个部件开启或关闭的参数。所述安全参数可以被烧写在所述OTP存储器中，实现对所述安全处理器系统的校准、配置或设置、或对所述安全处理器系统内的部分器件功能的关闭或去使能。因此，该OTP存储器使得SoC在被制造出来后相应的安全处理器系统内部的一些功能依然是可以被设置或更改的，提高了SoC制造完成后的设计灵活性。
在上一实现方式中，可选地，所述OTP存储器还用于存储所述安全处理器初始化所需的引导程序指令的补丁程序指令。该补丁程序指令可以是对引导 程序指令的补充或其中部分程序的替换。例如，当SoC制造完成后，如果发现引导程序指令存在不足，依然可以通过在该OTP存储器中烧写补丁程序指令来弥补现有引导程序指令的不足，使得实现更加灵活。
根据第一方面的描述，在一种可能的实现方式中，所述安全处理器系统还包括防攻击传感器，用于检测所述安全处理器系统的工作参数的异常，并在发生所述异常时触发以下至少一项操作：所述安全处理器系统进行告警、所述安全处理器复位、或所述第一存储器或所述安全处理器系统中的至少一个寄存器被复位或清空；所述工作参数包括电压、电流、时钟频率、温度或激光强度中的至少一项。通过本实现方式，使得执行安全应用软件的所述安全处理器系统的安全性进一步提高。
根据第一方面的描述，在一种可能的实现方式中，所述安全处理器系统还包括防攻击金属层，该防攻击金属层位于所述第一半导体芯片中的最上一层或多层、并在版图布局上覆盖所述安全处理器系统的至少一部分；所述防攻击金属层用于检测来自外界的物理探测或攻击，并在检测到所述物理探测或攻击时产生电信号，该电信号用于触发以下至少一项操作：所述安全处理器系统进行告警、所述安全处理器复位、或所述第一存储器或所述安全处理器系统中的至少一个寄存器被复位或清空。在本实现方式中，防攻击金属层技术被有效应用于该SoC，使得执行安全应用软件的所述安全处理器系统的安全性进一步提高。可选地，该防攻击金属层是个隔离(Shielding)。
根据第一方面的描述，在一种可能的实现方式中，所述安全总线包括高级高性能总线(AHB)或高级外围总线(APB)中的至少一项。可选地，所述安全处理器系统的不同部分、元件或电路可以进一步划分不同的安全等级，采用不同级别的总线技术做连接，可以满足所述安全处理器系统内不同部件的速率要求和安全要求。可选地，安全总线上传输的数据或相关地址可以被经过加密、加扰、或循环冗余校验(CRC，Cyclic Redundancy Check)等一种或多种方式所处理，以保证安全总线上数据和地址的私密性和完整性。
根据第一方面的描述，在一种可能的实现方式中，所述安全处理器系统还包括耦合于所述安全总线的直接存储器存取(DMA，Direct Memory Access)控制器，用于从所述第一存储器读取数据并输出至所述安全总线或通过所述安 全总线将数据写入所述第一存储器。由于DMA控制器的存在，数据读取或写入的效率有所提高。
根据第一方面的描述，在一种可能的实现方式中，所述安全处理器系统还包括耦合于所述安全总线的密码(Cipher)系统，所述密码系统包括如下至少一项：加解密器件，用于对所述安全处理器系统中的至少一种数据进行加解密处理；认证器件，用于对所述安全处理器系统中的至少一种数据进行认证；随机数产生器，用于产生随机数，该随机数用于作为生成密钥的种子或芯片的唯一标识；或密钥管理器，用于在所述安全处理器系统中生成、分发或销毁用于做所述加解密处理或认证所需的密钥。可选地，所述密码系统是硬件加速器，能够实现快速安全运算或处理，并且其处理安全性高于由所述安全处理器运行软件程序执行相关处理的安全性。
可选地，上一实现方式中，所述认证器件用于执行所述基于生物识别的用户认证。或者可替换地，所述用户认证可以由所述安全处理器所执行。可以理解，采用所述认证器件执行所述用户认证的效率更好，但成本略有提高。
在上一实现方式中，可选地，所述至少一个处理器还包括：通信处理器，用于向无线接入点发送第一通信数据或从所述无线接入点接收第二通信数据；语音信号处理器，用于对来自用户的语音信号做处理生成由所述通信处理器发送的所述第一通信数据，或用于对所述通信处理器接收的所述第二通信数据做处理得到用户所需的语音信号；所述加解密器件还用于对所述第一通信数据进行加密处理或对第二通信数据进行解密处理。在该集成的SoC中，原本实现安全元件功能的所述安全处理器系统中的所述加解密器件还用于执行其他功能，例如基于语音信号的通信数据的加解密处理，实现了安全处理能力多样化。可选地，该语音信号可以是PS(分组交换)域语音信号或CS(电路交换)域语音信号。可选地，该语音信号处理器可以包括HiFi(高保真)处理器或语音编解码器(Codec)之中的至少一个。所述HiFi处理器可用于实现对所述语音信号的回声消除、平滑、音色增强等处理。所述语音编解码器可以用于实现语音编解码操作以实现数字形式的所述语音信号和自然的模拟语音信号(普通声音信号)之间的转换。可选地，所述无线接入点可以是基站，所述通信处理器是蜂窝通信处理器。
可替换地，所述至少一个处理器还可以包括：通信处理器。所述加解密器件还用于对所述生物识别数据进行加密处理得到加密后的生物识别数据；所述通信处理器，用于将所述加密后的生物识别数据通过无线接入点发送至用于进行所述用户认证的服务器。在本实现方式中，生物识别数据可以通过所述通信处理器上传至所述服务器，由所述服务器实现用户认证，节省SoC的认证开销。可选地，所述通信处理器包括蜂窝通信处理器或短距离通信处理器中的至少一项。也就是说，通信传输的方式可以有多种不同实现方式。
可选地，针对以上可能的实现方式，所述蜂窝通信处理器可以支持GSM、UMTS、WiMAX、TDS-CDMA、CDMA2000、LTE或5G中的至少一种蜂窝无线通信协议。可选地，所述短距离通信处理器可以支持红外、无线保真(WIFI)、蓝牙、或LTE D2D(Device to Device，设备直连)中的至少一项。
根据第一方面的描述，在一种可能的实现方式中，所述至少一个处理器还包括如下至少一项：图像处理单元(GPU)、系统功耗管理单元、或系统外设接口。所述GPU用于处理图像信号。所述系统功耗管理单元用于对所述SoC进行系统功耗控制，例如对所述SoC或其中的至少一个部件进行时钟和工作电压的管理和控制。所述系统外设接口的数量可以是多个，分别用于耦合至多个外围设备。例如，外围设备可以是USB(通用串行总线)设备、显示器、传感器、摄像头、耳机、或扬声器等中至少一个。
根据第一方面的描述，在一种可能的实现方式中，所述SoC还包括：所述NFC处理器。或者可替换地，所述NFC处理器也可以外置于所述SoC。当所述NFC处理器包括在所述SoC内时，可进一步降低整个系统的制造成本。
根据第一方面的描述，在一种可能的实现方式中，所述安全处理器还用于利用所述生物识别数据执行所述用户认证。可替换地，所述安全处理器系统还包括：生物识别认证器，用于利用所述生物识别数据执行所述用户认证。当采用专用的生物识别认证器时，该生物识别认证器相当于是硬件加速器，用户认证功能实际上相当于通过专用加速器实现，安全性和速度更优。相反，如果采用所述安全处理器实现用户认证则可以节省制造和设计专用加速器的成本。
根据第一方面的描述，在一种可能的实现方式中，所述多个接口还包括存储接口，用于耦合至第三存储器；所述第三存储器用于存储所述安全操作系统 软件和至少一个安全应用软件；所述安全处理器用于通过所述存储接口从所述第三存储器读取所述安全操作系统软件和至少一个安全应用软件，将所述安全操作系统软件和至少一个安全应用软件加载到所述第一存储器中以运行所述安全操作系统软件和至少一个安全应用软件。在本实施方式中，所述第三存储器通过专用的所述存储接口耦合于所述安全处理器系统，这样所述安全操作系统软件和至少一个安全应用软件的读取都是通过该专用的存储接口，无需依赖于中央处理单元的TEE，可以实现更高的安全性。可选地，所述第三存储器集成于不同于第一半导体芯片的第二半导体芯片上。可选地，所述第三存储器是非掉电易失性存储器，可以是闪存(Flash Memory)。可选地，该第三存储器专用于存储所述安全操作系统软件和至少一个安全应用软件，且不用于存储非安全的普通软件，实现了更高安全性。
根据第一方面的描述，在一种可能的实现方式中，所述生物识别包括如下至少一项：指纹识别、虹膜识别、声纹识别、人脸识别、或气味识别。对应地，所述生物识别传感器可以包括如下至少一项：指纹传感器、虹膜传感器、声纹传感器、图像传感器、或气味传感器。对应地，所述生物识别输入接口可以包括如下至少一项：指纹输入接口、虹膜数据输入接口、声纹输入接口、人脸图像输入接口、或气味数据输入接口。
第二方面，本发明实施例还提供了一种处理设备，包括第一方面或其中任一种可能的实现方式所述的SoC。该处理设备还包括集成于第三半导体芯片上的第四存储器，所述SoC与所述第四存储器通过芯片间接口相耦合，所述第四存储器包括互相隔离的安全存储区域和普通存储区域；所述安全存储区域用于存储所述安全操作系统软件和至少一个安全应用软件；所述普通存储区域用于存储所述通用操作系统软件；所述至少一个中央处理单元，用于通过所述芯片间接口从所述普通存储区域获取所述通用操作系统软件并运行所述通用操作系统软件；所述安全处理器，用于通过所述芯片间接口、系统总线和安全总线从所述安全存储区域获取安全操作系统软件和所述至少一个安全应用软件，并运行所述安全操作系统软件和所述至少一个安全应用软件。在该第二方面中，由于第四存储器可以同时存储安全软件和非安全软件，实现了硬件复用，降低了成本。可选地，该处理设备是移动终端。可选地，所述第四存储器是非 掉电易失性存储器，如EMMC(Embedded Multi Media Card，嵌入式多媒体卡)或UFS(Universal Flash Storage，通用闪存存储)。
第三方面，本发明实施例还提供了一种数据处理方法，该方法由第一方面或其中任一种可能的实现方式所述的SoC所执行。该方法至少包括：通过所述NFC接口与NFC对端交互与所述移动支付相关的NFC信息；从生物识别传感器接收生物识别数据，所述生物识别数据在所述移动支付中被用于做基于生物识别的用户认证；通过用户界面(UI)向用户显示至少一项显示信息。可选地，所述显示信息包括用户信息输入界面、所述移动支付的交易界面或交易成功界面的至少一项。
可选地，根据第三方面的描述，在一种可能的实现方式中，所述用户界面是被所述至少一个中央处理单元运行的基于所述通用操作系统软件的UI软件所驱动所形成，或者是被所述安全处理器运行所述至少一个安全应用软件中的安全用户界面软件所驱动所形成。
本发明的实施例可以使得所述安全处理器系统用于自身专用的接口以接收各类信息，不需要依赖于传统的TEE，提高安全性。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例或现有技术的简要示意图，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术提供的一种简化的用于移动支付场景下的能够运行安全移动支付应用软件的移动终端结构的简化示意图；
图2为本发明实施例提供的一种移动终端的简化示意图；
图3为本发明实施例提供的一种安全处理器系统的简化示意图；
图4为本发明实施例提供的一种安全处理器系统的多个接口的应用方式的简化示意图；
图5为本发明实施例提供的一种安全处理器系统中引导程序指令的安全存储方式的简化示意图
图6为本发明实施例提供的一种防攻击传感器的简化示意图；
图7为本发明实施例提供的一种防攻击金属层在半导体芯片上的分层布局的简化示意图；
图8为本发明实施例提供的一种半导体芯片的版图布局中的防攻击金属层的简化示意图；
图9为本发明实施例提供的一种采用系统存储器作为安全操作系统软件和所述至少一个安全应用软件的存储器的应用场景的简化示意图；
图10为本发明实施例提供的一种采用专用的安全存储器作为安全操作系统软件和所述至少一个安全应用软件的存储器的应用场景的简化示意图；
图11为本发明实施例提供的一种移动支付相关方法的示意性流程图；
图12为本发明实施例提供的一种使用安全处理器系统执行语音信号加密的应用场景的简化示意图；
图13为本发明实施例提供的一种通过云侧服务器执行基于指纹数据的用户认证的应用场景的简化示意图；
图14为本发明实施例提供的一种采集并存储指纹数据的应用场景的简化示意图；
图15为本发明实施例提供的一种在移动支付过程中的处理方法的简化流程示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
在本发明实施例中，移动终端，也可以叫用户设备(UE)、无线终端或用户终端，可以享有服务站点或无线接入点的无线接入服务。所述服务站点或无线接入点通常是一个基站，如LTE(长期演进)中的eNodeB或NodeB，或 者也可以是GSM模式下的基站控制器等用于将用户设备接入移动通信网络的接入点。所述服务站点在为移动终端提供接入服务时，可形成一个或多个小区，一个小区可以在地理上覆盖一定范围并占据频域上的一段载波或频带。具体地，移动终端与所述服务站点可通过运行无线通信协议实现通信过程，所述无线通信协议包括但不限于GSM、UMTS、WiMAX、TDS-CDMA、CDMA2000、LTE或5G等各类蜂窝无线通信协议。
图2为本发明实施例提供的一种移动终端20的简化示意图。该移动终端20可以是一个用户设备(User Equipment，UE)，如手机、平板电脑或可穿戴设备等各种类型的便携式终端设备。该移动终端20具体可以包括片上系统21和系统存储器22，片上系统21和系统存储器22可以通过专用接口互相耦合。
在本发明实施例中涉及的片上系统(SoC)是以集成电路工艺制造在同一个半导体芯片或半导体衬底上的系统。半导体芯片也简称为芯片，其可以是利用集成电路工艺制作在集成电路的衬底(通常是例如硅一类的半导体材料)上形成的集成电路的集合，其外层通常被半导体封装材料封装。所述集成电路可以包括各类功能器件，每一类功能器件包括逻辑门电路、金属氧化物半导体(Metal-Oxide-Semiconductor，MOS)晶体管、双极晶体管或二极管等晶体管，也可包括电容、电阻或电感等其他部件。功能器件可以独立工作或者在必要的驱动软件的作用下工作，可以实现通信、运算、或存储等各类功能。因此，本发明实施例中提到的装置的各个功能器件或模块可以是硬件，每个功能器件可包括多个逻辑门电路或晶体管。在本实施例中，系统存储器22与片上系统21分别位于不同的半导体芯片上。例如，片上系统21位于第一半导体芯片上，而系统存储器22位于第三半导体芯片上。可选地，所述系统存储器22是非掉电易失性存储器，如EMMC或UFS。
在图2中，所述片上系统21可包括各类功能器件，如系统总线210、耦合于所述系统总线210的至少一个处理器、和耦合于所述系统总线210的安全处理器系统23。所述安全处理器系统23与该片上系统21内的其他部件，即与所述至少一个处理器间存在安全隔离。所述至少一个处理器可选择性地包括至少一个中央处理单元211、图像处理单元212、通信处理器213、语音信号处理器214、系统外设接口215、系统功耗管理单元216和图像信号处理器(ISP， Image Signal Processor)217。所述安全处理器系统可以包括一个或多个接口24，所述接口24可包括与所述片上系统21之外的其他部件耦合的接口或与所述片上系统21内的其他部件耦合的接口。
在本发明的各个实施例中，所述安全隔离能够用于限制所述至少一个处理器对所述安全处理器系统23内器件或模块的访问。在所述安全隔离，包括中央处理单元211在内的所述至少一个处理器无法直接访问所述随机存储器32或所述安全处理器系统23中的至少一个寄存器，因此不能随意读取安全处理器系统23内的数据或信息。
在图2中，所述至少一个中央处理单元211用于运行通用操作系统软件，并在所述通用操作系统软件的作用下通过所述系统总线210与所述安全处理器系统23通信。其中，所述至少一个中央处理单元211可以基于先进精简指令集机器(Advanced RISC Machine，ARM)架构或英特尔X86架构或单字长定点指令平均执行速度(Million Instructions Per Second，MIPS)架构等来实现，本实施例对此不作限制。中央处理单元211的数量越多，能够处理数据的能力越强。通用操作系统软件则是运行各种普通应用软件的通用软件平台。所述通用操作系统软件可以是安卓操作系统、Windows操作系统或iOS操作系统。
在图2中，所述图像处理单元212用于处理图像信号，例如处理视频图像信号或照片图像信号，也可选择性地处理3D(三维，3 Dimensions)图像信号。所述系统功耗管理单元216用于对所述片上系统21进行系统功耗控制，例如对所述片上系统21或其中的至少一个部件进行时钟和工作电压的管理和控制，例如进行AVS(自适应电压缩放，Adaptive Voltage Scaling)、DVS(动态电压缩放，Dynamic Doltage Scaling)或时钟频率的调整。所述系统外设接口215的数量可以是多个，分别用于耦合至所述片上系统21之外的所述移动终端20的多个外围设备。例如，外围设备可以是USB设备、显示器、传感器、摄像头、耳机、或扬声器等中至少一个。所述感器可以是重力加速计、陀螺仪、或光传感器。图像信号处理器217可以用于对移动终端20的摄像头所采集的图像信号进行处理，以得到处理后的采集图像，该图像可以被图像处理单元212做进一步处理。
图2中的通信处理器213可以包括多个执行不同的通信功能的处理器。例 如可选择性地包括蜂窝通信处理器或短距离通信处理器。所述蜂窝通信处理器可以支持GSM、UMTS、WiMAX、TDS-CDMA、CDMA2000、LTE或5G中的至少一种蜂窝无线通信协议。所述短距离通信处理器可以支持红外、WIFI、蓝牙、或LTE D2D中的至少一项。可选地，每种通信处理器可包括用于进行射频(RF)信号处理的RF处理器、和用于执行基带通信处理或通信协议算法的基带通信处理器。或者，可替换地，每种通信处理器可以只包括基带通信处理器，而相应RF处理器可以外置于所述片上系统21。也就是说，如果片上系统21集成在第一半导体芯片上，则RF处理器可以集成在另一个不同于第一半导体芯片的其他芯片上。
图2中的语音信号处理器214用于执行语音信号处理。该语音信号处理器214可以包括HiFi处理器或语音编解码器之中的至少一个。所述HiFi处理器可用于实现对所述语音信号的回声消除、平滑、音色增强等处理。所述语音编解码器可以用于实现语音编解码操作以实现数字形式的所述语音信号和自然的模拟语音信号之间的转换。通常情况下，语音信号处理器214可以只包括HiFi处理器。语音编解码器由于包括模拟电路，可以在外置于所述片上系统21的另一个半导体芯片上来实现，本实施例对此不作限定。
图3对于本发明实施例提供的安全处理器系统23进行介绍。所述安全处理器系统23除了可用于实现类似现有技术中安全元件的功能或SIM功能，其在本实施例中还可以实现更多安全应用功能，作为该安全处理器系统23的调度和执行中枢而工作。该安全处理器系统23包括安全总线35，以及耦合至该安全总线35的安全处理器31、随机存储器(RAM)32、安全启动存储器33、OTP存储器34、和所述多个接口24。随机存储器32是掉电易失性存储器，而安全启动存储器33则是非掉电易失性存储器。在图3中，随机存储器32、安全启动存储器33、OTP存储器34被包括在一个存储系统中。或者，可替换地，所述各个存储器可以不是被包括在一个系统中，而是各自分别独立的，在电路结构上不存在紧密关联，本实施例对具体实现方式不作限制。
所述安全处理器31，用于运行安全操作系统软件和基于所述安全操作系统软件的至少一个安全应用软件，所述至少一个安全应用软件包括移动支付软件，所述安全处理器能够通过运行所述移动支付软件实现移动支付。可选地， 所述至少一个安全应用软件还可以包括SIM卡应用软件，所述SIM卡应用软件包括但不限于虚拟SIM软件或通信运营商定制的SIM特性应用软件。所述安全处理器31等效为是实现了现有技术中安全元件的功能，并且可以进一步集成其他功能，扩展该片上系统21的安全应用场景。所述随机存储器32，用于提供所述安全处理器31运行所述安全操作系统软件和所述至少一个安全应用软件所需的存储空间。该随机存储器32可以用于存储被加载的所述安全操作系统软件和所述至少一个安全应用软件，并还可以用于存储运行所述安全操作系统软件和所述至少一个安全应用软件所产生的安全临时数据。当所述安全处理器31上电后可以将所述安全操作系统软件和所述至少一个安全应用软件加载到随机存储器32，并利用随机存储器32的内部存储空间运行相应软件。所述安全临时数据是所述安全处理器31运行所述安全操作系统软件和至少一个安全应用软件所产生的中间数据或中间运算结果或是其他无需长期存储的与安全应用软件或其运行相关的信息，例如各类中间运算结果数据或运算处理中的配置数据等。此时，随机存储器32相当于实现电脑中的内存功能，是一种掉电易失性存储设备，可以是SRAM、DRAM、SDRAM或DDR SDRAM(双倍速率同步动态随机存储器)中的任一种。由于该随机存储器32是集成于片上系统21内的，该随机存储器32可以与所述片上系统21内的其他部件使用同样的制造工艺，工艺实现比较容易。所述安全处理器31可以用于在上电启动过程中引导该安全处理器系统23内的其他部件的初始化，并加载安全操作系统软件和至少一个安全应用软件至随机存储器32中执行相关运算操作。所述安全处理器31可以是运算速度或实现复杂度低于至少一个中央处理单元211的处理器，但是功耗通常更低且安全性更好，例如其可以是ARM架构的处理器，也可以是其他专用的防攻击处理器，或者也可以是数字信号处理器(DSP)。
其中，由安全处理器31所运行的安全操作系统软件可以是一个片内操作系统(Chip Operating System，COS)。该COS也叫COS镜像，可以包括驻留智能卡或金融集成电路(Integrated Circuit，IC)卡内的操作系统软件的功能，此时的安全处理器系统23包括了传统的安全元件、驻留智能卡或金融卡的功能，其用于向外界的POS机、读卡器或云侧的金融服务器提供刷卡等移动支 付业务所需的数据，如银行金融业务相关的数据或用户个人的账户数据，例如个人账号、密码、银行服务器对个人账户进行验证所需的各类验证信息等。此外，COS镜像也可以是接收和处理外界支付信息(如金融服务器或者读卡器、POS机发送的各种支付信息)的操作平台，可选择性的用于执行外界发送的各种指令，比如鉴权运算等操作。COS一般基于JAVA计算机程序语言设计，不仅能够在安全处理器系统23中被预置，而且移动终端20还能基于该COS动态下载和安装各类安全应用软件，如各类金融应用软件。COS的具体设计属于现有技术的内容，不在本申请讨论范围内。
在图2中，所述至少一个中央处理单元211与所述安全处理器系统23的通信包括数据交互或指令交互。所述指令可以是至少一个中央处理单元211控制或操作所述安全处理器系统23的指令，包括但不限于启动指令、关闭指令、重启指令、睡眠指令、进入或退出低功耗状态指令、或暂停或恢复工作指令，以分别指示所述安全处理器系统23进入与每个指令相应的状态。例如，当中央处理单元211发送睡眠指令至所述安全处理器系统23，所述安全处理器系统23可以响应该指令进入睡眠状态。通过以上交互过程，所述安全处理器系统23的工作状态可以被所述至少一个中央处理单元211控制，但是不会影响所述安全处理器系统23中的数据的安全性。此外，可选地，所述指令还可被用于实现其他控制过程，如控制工作状态，具体可包括控制安全处理器系统23或其中至少部分部件的工作电压、工作时钟频率或信息处理速率等，本实施例对此不作限定。
图3中的所述多个接口24可以灵活适配不同的使用场景，可选择性地包括NFC接口241和指纹输入接口242。进一步如图4所示，所述NFC接口241，用于经由NFC处理器41与NFC对端交互与所述移动支付相关的NFC信息，所述NFC信息包括移动支付指令、移动支付数据或NFC认证信息中的至少一项。其中所述NFC处理器41是一个做NFC通信信号处理的处理器，其可以集成在通信处理器213内以降低整个系统的制造成本，也可以在移动终端20中位于片上系统21之外的一个独立的半导体芯片之上。该NFC处理器41可包括NFC基带处理器和RF处理器的至少一个。该NFC处理器41通常也叫NFC控制器，用于与NFC对端实现短距离的非接触式数据通信来实现数据的 读写或交互。NFC对端是与移动终端20内的所述NFC处理器41交互NFC数据和指令的设备，可以是POS机。具体地，安全处理器31用于实现与移动支付相关的运算和处理，并通过安全总线35与耦合至NFC接口241的NFC处理器41交互NFC信息，该NFC信息则被NFC处理器41发送至NFC对端或从NFC对端接收。例如，该NFC对端可以是移动支付相关的NFC认证信息、移动支付金额、移动支付请求或响应信息等。该NFC处理器41可支持NFC通信协议或RFID(Radio Frequency Identification，射频识别)通信协议。在安全处理器31上电启动后，如果要实现移动支付功能，其运行移动支付软件，并通过安全总线35、NFC接口241和NFC处理器41向NFC对端发送移动支付请求，并反向接收来自NFC对端的移动支付响应，以及与NFC对端进一步交互执行双向NFC认证所需的NFC认证信息，并且将用户确定的支付金额传输至NFC对端。NFC接口241可以是一个单线协议(SWP，Single Wire Protocol)接口，当然也可以是其他类型接口，如串行外设接口(SPI，Serial Peripheral Interface)、通用输入/输出(General Purpose Input Output，GPIO)接口或集成电路间(Inter-Integrated Circuit，I2C)接口等。
在图4中，所述指纹输入接口242耦合于指纹传感器42，用于从所述指纹传感器42接收指纹数据，所述指纹数据在所述移动支付中被用于做基于指纹识别的用户认证。所述指纹传感器42通常是位于移动终端20内且位于片上系统21之外的一个设备。该指纹传感器42采集用户的指纹数据并通过指纹输入接口242传输至安全处理器31或其他认证元件，以便认证用户的身份。只有基于指纹识别的用户认证通过，移动支付才被执行或被进一步执行。所述指纹输入接口242可以是SPI，当然也可以是其他类型接口。进一步地，该指纹输入接口242可以用于首次采集用户的指纹数据并进一步将该指纹数据通过存储接口245存储在安全存储器45或通过隔离存储器36或总线桥将指纹数据传输至行系统总线210并进一步传输至系统存储器22保存。当需要做用户认证时，安全处理器系统23中的安全处理器31或其他部件，如指纹识别器，可以从安全存储器45或系统存储器22读取保存的指纹数据并与新采集到的指纹数据做比对以实现用户认证。
应该理解，本发明实施例虽然以指纹识别为例描述接口242，但实际上接 口242也可以由其他类型的接口来代替，如用于传输虹膜数据、声纹数据、人脸数据、或气味数据的接口，此时的用户认证不再是基于指纹识别的认证，而可以是基于虹膜识别、声纹识别、人脸识别、或气味识别。对应的传感器可以是：虹膜传感器、声纹传感器、用于采集人脸图像的图像传感器、或气味传感器。也就是说，通过采集用户特定的生物识别数据，并通过相关接口传递至安全处理器系统23中，可以实现相关的用户身份的认证。当然，安全处理器系统23可以包括支持以上全部类型的生物识别数据的生物识别输入接口，以实现更灵活的用户身份认证，实施例涉及的附图仅用于示意。这些一个或多个生物识别输入接口可以是SWP接口，当然也可以是其他类型的接口，如SPI接口或I2C接口。
请一并参考图3和图4，进一步地，多个接口24还可以包括安全输入接口243、外设接口244和存储接口245。其中安全输入接口243用于接收用户输入的与移动支付相关的用户信息。可选地，所述用户信息包括用户输入的密码、用户指令或金融交易金额。用户指令可以是同意、停止或继续移动支付的指令。因此，所述安全输入接口243需要耦合于一个输入设备43以通过所述输入设备43接收所述用户信息。所述输入设备43可以是位于移动终端20内的用于执行输入的触摸屏或按键。外设接口244，用于通过外围设备44向用户指示所述移动支付被执行。例如，该外围设备44可以是指示设备，且所述外设接口244耦合于所述指示设备44。该指示设备44可以是指示灯、用于播放声音的扬声器或振动器，用于通过光线信号、声音或震动提醒用户所述移动支付正在或已经或将要被执行。所述安全输入接口243可以是I2C接口或其他类型接口。外设接口244可以是GPIO接口或其他类型接口。
存储接口245可以耦合至所述片上系统21之外的一个安全存储器45，该存储接口245可以是SPI接口或其他类型接口。所述安全存储器245可用于存储所述安全操作系统软件和至少一个安全应用软件。可选地，该安全存储器45包括具有防物理和逻辑攻击等增强特性的存储器，以用于安全地存储安全操作系统软件和至少一个安全应用软件。所述安全处理器31用于通过所述存储接口245从所述安全存储器45读取所述安全操作系统软件和至少一个安全应用软件，并运行所述安全操作系统软件和至少一个安全应用软件。该存储接 口245是一个专用接口，该安全存储器45则是专用于安全处理的处理器，这样所述安全操作系统软件和至少一个安全应用软件的读取都是通过该专用的存储接口245进行，无需依赖于中央处理单元211的TEE，可以实现更高的安全性。该安全存储器45可以是可擦写的非易失性存储器，如Flash。所述安全存储器45集成于不同于片上系统21所在的第一半导体芯片的第二半导体芯片上。由于该安全存储器45专用于存储所述安全操作系统软件和至少一个安全应用软件，不用于存储非安全的软件，实现了更高安全性。所述安全存储器45存储的数据不同于中间数据或临时数据，可以被长期保存。相反，随机存储器32存储的临时数据或者叫做中间数据或内存数据，是运行一个软件所产生的过程数据，其无需被长期保存，可以是随着设备或装置掉电而丢失。安全处理器31可以在上电后或基于用户指示或其他条件触发将所述安全操作系统软件和至少一个安全应用软件从所述安全存储器45加载到随机存储器32中，该随机存储器32为运行相关软件提供了所需要的存储空间。
可替换地，在存储工艺发展的情况下，安全存储器45功能也可以由安全处理器系统23内的一个内部存储器所代替。该内部存储器可以是一个片上ROM，也可以是电可擦可编程只读存储器(Electrically Erasable Programmable Read-Only Memory，EEPROM)或其它片内非易失性存储器，用于存储所述安全操作系统软件和至少一个安全应用软件，且是非掉电易失性存储器。该内部存储器使得安全处理器系统23无需依赖外部的存储器存储所述安全操作系统软件和至少一个安全应用软件，安全性高，只是会导致更高成本。
在图3和图4对应的片上系统21中，包括至少一个中央处理单元211的多个处理器和安全处理器系统23被集成，可以降低整个系统的实现成本和面积，并且安全处理器系统23与其他非安全元件存在安全隔离保证安全性。且NFC接口241、指纹输入接口242和用于输入用户信息的安全输入接口243和外设接口244被集成在所述安全处理器系统23中，这些接口相关的信息采集将不再像传统系统一样依赖于中央处理单元211的TEE，使得NFC信息、指纹数据、用户信息等的传输更加安全。
在所述片上系统21中，在所述安全隔离下，所述系统总线210和所述安全总线35通过隔离存储器36相耦合。也就是说，位于安全处理器系统23外 的至少一个处理器和所述安全处理器系统23通过所述隔离存储器36交互数据或指令。在一个实例中，包括中央处理单元211在内的所述至少一个处理器无法直接访问所述安全处理器系统23中除了隔离存储器36之外的任一部件。例如，所述至少一个中央处理单元211可以在所述通用操作系统软件的作用下通过所述系统总线210和所述隔离存储器36耦合至所述安全处理器系统23，以与所述安全处理器系统23通信，该通信的内容包括数据或指令，比如传递数据至安全处理器系统23内的至少一个元件。此时隔离存储器36是安全处理器系统23与外界交互的专用交互通道，甚至唯一通道，即用于实现数据或信息交互的邮箱(Mailbox)通道，避免由所外界的所述至少一个处理器直接访问所述随机存储器32或所述安全处理器系统23中的任一部件或模块，可以提高安全性。
该隔离存储器36优选是一个掉电易失性的存储器，如RAM，但是也可以用非掉电易失性存储器，如ROM替代。当片上系统21中的非安全的一个或多个处理器，如中央处理单元211需要对安全处理器系统23进行写数据时，先将数据写入隔离存储器36，然后通过中断或其他指示信息通知安全处理器系统23中的安全处理器31，由安全处理器31从隔离存储器36进行数据读取和搬运。反之，安全处理器31将数据或信息写入隔离存储器36，并通过中断或其他指示信息通知安全处理器系统23之外的其他处理器从隔离存储器36中读取数据。
可替换地，本实施例的图3中涉及的隔离存储器36可以由一个其他类型的安全隔离器件，如总线桥来代替。该总线桥就是一个跨接在安全处理器系统23的安全总线35和系统总线210之间的总线。该总线桥专用于在两条不同安全性的总线之间传输数据或信息，以代替隔离存储器36的功能，将系统总线210耦合于安全总线35。可选地，该总线桥可上传输的数据可以被做进一步安全处理以提高安全性，例如在该总线桥上传输的数据需要经过特别的加解密处理，本实施例对此不作限定。
通过隔离存储器36或总线桥等安全隔离器件实现安全隔离，安全处理器系统23之外的至少一个处理器不能随意访问安全处理器系统23内的存储器或寄存器。安全处理器系统23可以选择性地将希望耦合至系统总线210上的一 个处理器读取的数据通过安全隔离器件传输至该处理器，安全处理器系统23不希望该处理器获取的数据将不会被通过安全隔离器件传输至该处理器。例如，安全处理器系统23不希望该处理器获取的数据可以包括通过指纹输入接口242获取的指纹数据、或在所述随机存储器32中临时存储的安全临时数据或被加载在所述随机存储器32中的所述安全操作系统软件和所述至少一个安全应用软件。
安全处理器系统23和至少一个处理器之间可以通过所述专用通传输道耦合并实现数据或指令交互，实现安全隔离。隔离存储器36或总线桥都是一种形式的所述专用交互通道。该专用交互通道可以是唯一的耦合在安全处理器系统23和至少一个处理器之间的通道。
在图3或图4中的安全处理器系统23可以进一步包括耦合于安全总线35的安全启动存储器33。安全启动存储器33存储所述安全处理器31初始化所需的引导程序指令。所述安全处理器31在运行所述安全操作系统软件和至少一个安全应用软件前，通过从所述安全启动存储器33读取所述引导程序指令以初始化所述安全处理器31。具体地，在移动终端20启动的过程中，至少一个中央处理单元211可以首先上电，然后触发安全处理器系统23上电。在该安全处理器系统23上电过程中，安全启动存储器33类似传统PC中的BIOS，可以保证每次所述安全处理器系统23的启动都是从读取该安全启动存储器33内的引导程序指令开始，保证启动安全。安全启动存储器33优选是一个片上ROM。例如，当所述安全处理器系统23上电时，所述安全处理器31用于从所述安全启动存储器33读取所述引导程序指令，在所述引导程序指令的作用下将所述安全操作系统软件加载到所述随机存储器32中，以运行所述安全操作系统软件。进一步地，所述安全处理器31可以在安全处理器系统23上电后启动一个或多个安全应用软件，即将一个或多个安全应用软件加载到所述随机存储器32中，以运行所述安全应用系统软件。或者，所述安全处理器31可以接收用户指令或其他条件的触发来启动安全应用软件。
进一步地，如图5所示，当所述安全处理器31从所述安全启动存储器33读取所述引导程序指令时，可以经过解密处理。也就是说，安全启动存储器33中存储的是经过加密的引导程序指令。在所述安全处理器31从所述安全启 动存储器33获取所述引导程序指令时，所述引导程序指令被解密逻辑电路51解密以得到解密后的引导程序指令，所述解密后的引导程序指令被用于初始化所述安全处理器31，以进一步保证启动安全性。解密逻辑电路51可以被隐藏在片上系统21的版图中，也就是说，解密逻辑电路51中的各个部分电路可以分散在所述片上系统21的版图的不同部分，因此很难被外界所破解，提高了安全性。
进一步地，图3中的OTP存储器34，用于存储所述安全处理器系统23的安全参数，所述安全参数可以选择性的包括根密钥、校准参数、配置参数、或使能参数中的至少一项。例如，所述根密钥用于产生所述安全处理器系统23执行至少一类加解密所需的其他密钥。所述校准参数包括对所述安全处理器系统23内至少一个部件做校准所需的参数，例如一个或多个防攻击传感器39的校准参数，以校准所述防攻击传感器39。配置参数包括所述安全处理器系统23内至少一个部件的配置参数，如随机数产生器304的配置参数，比如随机数产生器304产生的随机数的长度的配置。所述使能参数包括控制所述安全处理器系统23内至少一个部件开启或关闭的参数。所述使能参数可实现使能部分部件，例如防攻击传感器39的使能控制。通过在OTP存储器34中执行烧写，以实现使能参数的配置。当使能参数被配置为有效时，相关部件，如防攻击传感器39被开启，使得在片上系统21被制造完成后，其内部的至少一个部件的功能是否可用依然是可配置的。所述使能参数还可包括生命管理周期参数，用于实现安全处理器系统23中部分部件在不同时间内的管理。例如，对于安全处理器系统23中保存的部分密钥是否可读，可通过该生命管理周期参数进行配置。当片上系统21被制造完成后，由于使用该片上系统21的OEM(原始设备制造，Original Equipment Manufacturer)厂商调试的需要，OEM厂商需要读取相关密钥，当调试完成后可在OTP存储器34中配置相关生命管理周期参数，该参数限定了密钥不可读，安全处理器31或其他部件通过读取OTP存储器34中的生命管理周期参数可以获知相关密钥已经被配置是不可读的，因此该密钥将无法被继续读取，从而避免该密钥的泄露。
所述安全参数可以被烧写在所述OTP存储器34中，实现对所述安全处理器系统23的校准、配置或设置、或对所述安全处理器系统23内的部分器件功 能的关闭或去使能。因此，该OTP存储器34使得片上系统21在被制造出来后，安全处理器系统23内部的一些功能依然是可以被设置或更改的，提高了制造完成后的设计灵活性。进一步地，该OTP存储器34还用于存储所述安全处理器31初始化所需的引导程序指令的补丁程序指令。该补丁程序指令可以是对引导程序指令的补充或其中部分程序的替换。例如，当片上系统21制造完成后，如果发现应用于安全处理器系统23的引导程序指令存在不足，而安全启动存储器33内的信息或数据已经不可改写，辞世依然可以通过在该OTP存储器34中烧写相关补丁程序指令来弥补现有的引导程序指令的不足或错误，使得实现更加灵活。当所述安全处理器31被启动时，可以从OTP存储器34中读取被烧写的一部分补丁程序指令来代替从该安全启动存储器33内读取的引导程序指令的至少一部分。例如，当安全处理器31从安全启动存储器33读取部分引导程序指令后可跳转至OTP存储器34读取相关补丁程序指令，并可在必要的时候跳转回去继续读取安全启动存储器33的其他引导程序指令，以实现安全启动。
本领域技术人员可以理解，可以进一步在该OTP存储器34上增加其他安全措施，例如通过一些安全认证器件对从该OTP存储器34读取的数据或信息做认证、对该OTP存储器34做电源异常检测和报警、对该OTP存储器34做读写异常检测和报警、对该OTP存储器34内部读取信息加密、或采用OTP存储器34中数据存储地址乱序等手段实现安全性提高。OTP存储器34可以是非掉电易失性存储器。
图3中的该随机存储器32由于是集成在片上系统21之内的，由于工艺等原因很难使用EEPROM来实现，但可以通过SRAM、DRAM、SDRAM或DDRSDRAM等来实现，目前可以做到几百KB(千字节)的容量。该随机存储器32中的数据可以是被加密的数据或者通过数据存储地址乱序等安全手段提高其数据安全性。
进一步地，该安全处理器系统23还包括耦合于所述安全总线35的DMA控制器37。DMA控制器37用于从所述随机存储器32读取数据并输出至所述安全总线或通过所述安全总线将数据写入所述随机存储器32。例如，当需要将数据从NFC接口经由安全总线35传输至随机存储器32时，相关传输操作 可以由DMA控制器37执行，不需要由安全处理器31执行，数据读取或写入的效率有所提高。因此DMA控制器37在本发明实施例中起到了替换安全处理器31进行数据转移和搬迁的作用，其具体工作原理可参照现有技术的描述，此处不作赘述。
进一步地，该安全处理器系统23还包括防攻击系统，以提高安全性。该防攻击系统可包括各类防攻击手段或器件，例如防攻击金属层38以及防攻击传感器39。防攻击传感器39用于检测所述安全处理器系统23的各种工作参数是否存在异常，并在发生所述异常时通过产生一个触发信号并将触发信号传输至所述安全处理器系统23，以触发以下至少一项操作：所述安全处理器系统23进行告警、所述安全处理器31复位、或随机存储器32或所述安全处理器系统23中的至少一个寄存器被复位或清空。具体地，所述工作参数包括电压、电流、时钟频率、温度或激光强度中的至少一项。因此如图6所示，防攻击传感器39可包括电压监测器61、电流监测器62、时钟频率监测器63、温度监测器64或激光强度检测器65中的一种或多种，用于所述安全处理器系统23的安全性。
在一种实现方式中，电压监测器61用于用于检测安全处理器系统23或其内部至少一个部件的电压是否正常，并在电压存在异常时将该异常上报所述安全处理器系统23中的安全处理器31或其他一个用于接收该异常上报的元件，并通过该安全处理器31或该元件执行告警操作。电压监测器61确定电压是否存在异常可以包括将检测到的电压与电压阈值比较、或做数据匹配，以确定该电压是否在正常范围内或是否达到预设的电压阈值。当所述电压在所述正常范围内或未达到预设的电压阈值则不上报异常或上报正常状态；反之，则电压监测器61上报异常。例如，该电压监测器61可包括用于感受电压的检测部件(即传感器)和用于比较或匹配处理的判断部件。具体地，当执行告警操作时，该安全处理器31或元件可以通过安全总线35发送告警指令至外设接口244，并通过外设接口244发送告警指示信号至外围设备44，以实现向用户告警。或者可替换地，该安全处理器31可以在接收该异常上报后执行复位操作，也可以选择性地由该安全处理器31或所述元件触发随机存储器32或所述安全处理器系统23中的一个或多个寄存器被复位或清空。电压监测器61可以识别由外 界攻击，如外界电压尖峰攻击导致的电压异常并执行相应操作，防止数据或信息泄露。该电压监测器61的一些校准参数可以被存储在OTP存储器34中。
进一步地，电流监测器62用于检测安全处理器系统23或其内部至少一个部件的电流是否异常，并且可选择性地包括检测电流的部件和判断电流异常的部件，以及在出现异常的时候执行相应的告警操作、复位或清空等操作，以准确识别由外界攻击导致的电流异常。
时钟频率监测器63用于检测安全处理器系统23或其内部至少一个部件的工作时钟频率是否存在异常并在出现异常的时候执行相应的告警操作或复位操作，并且可选择性地包括检测时钟频率的部件和判断时钟频率异常的部件，以准确识别由外界攻击导致的工作时钟的异常或不稳定。由于整个系统的时钟结构复杂，输送给安全处理器系统23的时钟频率经过多级倍频或分频，频率攻击难度增强。降低时钟频率通常有利于外界施加攻击，这使得外界希望更容易定位并改变供应给安全处理器系统23的工作时钟的时钟频率。而复杂系统的时钟变换使得外界设备很难准确定位具体的安全处理器系统23的时钟是哪一个，因此可以使用时钟频率监测器63检测与安全处理器系统23相关的时钟即可实现防攻击检测。例如，可以不仅检测安全处理器系统23的工作时钟也可以检测产生该工作时钟的源时钟，即工作时钟的分频或倍频时钟。
进一步地，温度监测器64的原理也与其他之前提到的检测器类似，用于检测安全处理器系统23或其内部至少一个部件的温度是否存在异常并在出现异常的时候执行相应的告警操作或复位操作，可以选择性地包括检测温度的部件和判断温度异常的部件，识别由外界攻击导致的温度异常变化以提高安全性。该用于实现防攻击的温度监测器64可以与片上系统内部其他用于实现热保护或热回退的温度传感器进行复用，除了起到热保护功能，还防止外界用低温攻击破坏本系统。
激光强度检测器65则用于检测安全处理器系统23或其内部某个部分的激光信号强度是否超预设阈值以识别异常，并在出现异常的时候执行相应的告警、复位或清空操作。激光强度检测器65主要用于防止外界的激光攻击。例如外部设备采用激光切割技术侵入本安全处理器系统23时，该激光强度检测器65能够检测到激光信号、或检测到该激光信号的强度超过所述阈值，并触 发相应的操作，如之前所述的告警、复位或清空等操作。
在图3的防攻击系统中，防攻击金属层38是基于金属掩膜层形成的。如图7所示，展示了第一半导体芯片70在垂直方向的剖面示意图，第一半导体芯片70中包括位于底层的半导体物理器件72。所述半导体物理器件72内包括所述片上系统21中除防攻击金属层38外的其他部分，包括各模块、各功能器件或各电路，用于实现信号或信息处理功能，具体请参照之前实施例，如图2至图4相应的各部分的描述。位于半导体物理器件72之上的通常是一层或多层金属掩膜层，其中一层或多层金属掩膜层经过特殊的电路设计形成了防攻击金属层38，并通过半导体集成电路制作工艺被制作出来，以用于检测来自外界的物理探测或攻击。可以理解，可以仅对最上一层的金属掩膜层做处理形成防攻击金属层38，也可以利用所有多层金属掩膜层都形成防攻击金属层38。因此，防攻击金属层38可以是一层或多层，并覆盖于半导体物理器件72上。因此，可以理解，所述片上系统21中的防攻击金属层38可位于第一半导体芯片70所形成的多个半导体层的至少一个顶层，片上系统21中的除了防攻击金属层38之外的其他部件或模块或单元可位于多个半导体层的底层。其中所述至少一个顶层位于所述底层之上。
如图8所示，展示了第一半导体芯片70在水平方向的版图布局的示意图，其中防攻击金属层38在版图布局上可以图8所示的网状结构覆盖在第一半导体芯片70的至少一个层71上，由于用于执行攻击的物体的尺寸通常大于防攻击金属层38的网状结构的金属线间距，不可避免会接触到网状结构，可实现对外界入侵物体的检测。或者可选的防攻击金属层38可以在版图布局上是网状结构之外的其他形状。当外界用于执行攻击的物体，如物理上的金属探针或切割工具等，深入到第一半导体芯片70内时，防攻击金属层38可以检测到该物体的侵入，并通过该所述SoC内与该防攻击金属层38相关联的电路执行告警、复位、或清空等防攻击操作。例如，该防攻击金属层38可在检测到所述侵入时生成一个电信号，该电信号可以反应由所述侵入导致的防攻击金属层38上的电特性的改变，如电压或电流的改变，所述电信号可被与该防攻击金属层38相关联的电路检测到，该电路耦合至所述安全处理器系统23。该电路在收到该防攻击金属层38产生的电信号时能够产生触发信号并将触发信号传 输至所述安全处理器系统23，以触发以下至少一项操作：所述安全处理器系统23进行告警、所述安全处理器31复位、或随机存储器32或所述安全处理器系统23中的至少一个寄存器被复位或清空。该防攻击金属层38可以是个隔离(Shielding)，其可以覆盖全部位于该所述第一半导体芯片70上的全部片上系统21，也可以仅在版图布局上覆盖所述安全处理器系统23的全部或该安全处理器系统23的关键部分，如仅覆盖安全处理器31或随机存储器32等，以提高安全性并降低由布置该防攻击金属层38带来的成本。如图8所示，防攻击金属层38在版图布局上覆盖了安全处理器系统23的全部，以保证安全性。
进一步地，该系统总线210或安全总线35都可以包括AHB或APB中的至少一项。所述安全处理器系统23中的不同部分或元件或电路可以进一步划分不同的安全等级，并采用不同级别的总线技术做连接可以满足所述安全处理器系统内不同部件的速率要求和安全要求。例如，当安全总线35可以采用AHB与APB相结合的总线传输方式，AHB与APB的安全级别不同，传输速率也可以不同，例如AHB的传输速率可以高于APB，但安全级别可以低于APB。不同部件，例如安全处理器31与存储系统或防攻击系统之间的耦合可采用AHB技术，而安全处理器31与密码系统30之间的耦合采用APB技术。具体的总线传输方式还可以有其他实现方式，此处不作赘述。进一步地，为了提高安全性，安全总线35上传输的数据或相关地址可以被加密、加扰或经过CRC，以避免相关数据或地址被外界破解，保证安全总线35上数据和地址的私密性和完整性。具体地，当安全处理器系统23中的一个读写发起部件(Master)通过该安全总线35访问另一部件(Slave)时，该安全总线35的读写地址，即占用该安全总线35的Master和Slave的器件的地址也可以进行加扰或交织等安全处理。
进一步地，在图3中，密码系统30包括如下至少一项：加解密器件301、认证器件302、密钥管理器303和随机数产生器304。加解密器件301，用于对所述安全处理器系统23中的至少一种数据进行加解密处理或鉴权处理，例如可以对安全处理器31存入随机存储器32的数据做加密，并将加密后的数据存入随机存储器32；反之，在安全处理器31从随机存储器32读取数据之前，加解密器件301可对相关数据做解密并将解密后的数据提供给安全处理器31， 使得安全处理器31可处理解密后的数据。或者，加解密器件301可以对安全处理器系统23通过接口24中任一个接口传输至外部设备的数据或信息做加密，并将外部设备通过对应接口传输来的数据做解密以供安全处理器系统23使用。该加解密器件301使用的加解密算法可以是对称或非对称的加解密算法，或者可选地还有哈希算法等鉴权算法。该加解密算法包括但不限于国际或中国规定的各类密码算法，如DES(数据加密标准，Data Encryption Algorithm)、3DES(三重数据加密标准，Triple DES)、AES(Advanced Encryption Standard，高级数据加密标准)、RSA算法、ECC(Elliptic Curves Cryptography，椭圆曲线密码学)等。哈希算法可包括MD5(Message-Digest Algorithm 5，信息摘要算法5)、SHA(安全哈希算法，Secure Hash Algorithm)等。另外加解密器件301还可支持各国私有的专用加解密算法，如中国密码局发布的SM2、SM3或SM4等算法。该加解密器件301还可选地支持加解密算法组合模式，如支持HMAC-SHA256(Hash Message Authentication Code-Secure Hash Algorithm 256，哈希消息认证码-安全哈希算法256)等。可选地，加解密器件301在硬件电路实现中，还可被设计为采用防侧信道攻击(Side Channel Attack)技术以增强算法的安全性。
该认证器件302，用于对所述安全处理器系统23中的至少一种数据进行认证，该认证可包括哈希(Hash)认证，例如对所述安全处理器系统23通过任意接口与外部交互的数据做认证处理。例如，当安全处理器系统23内任一部件，如安全处理器21需要向安全存储器45写入数据时，则认证器件302对相关数据做哈希处理并将哈希处理后的数据写入安全存储器45；当安全处理器21需要从安全存储器45读取该数据时，首先该数据被送入认证器件302进行解哈希运算，只有解哈希认证成功，则认为数据没有被入侵或修改，则该数据被送入安全处理器21，以保证安全性。可选地，该认证器件302也可以进一步用于执行之前实施例中提到的所述基于指纹识别的用户认证。
在图3中，随机数产生器304，用于产生随机数，该随机数用于作为生成至少一类加密所需的密钥的种子或芯片的唯一标识，该芯片的唯一标识用于标识该片上系统21或安全处理器系统23。所述随机数则可以是真随机数或伪随机数。密钥管理器303，用于在所述安全处理器系统23中生成、分发或销毁 用于做所述加解密处理或认证所需的密钥。例如，当加解密器件301需要做加解密处理时，密钥管理器303可接收随机数产生器304产生的随机数，并基于该随机数生成加解密所需的密钥，并将相关密钥提供给加解密器件301使用，并且该密钥管理器303可以在预设时间内维护该密钥有效，当超过所述时间则通知加解密器件301禁止继续使用该密钥。也就是说，该密钥管理器303在一个密钥超期时对该密钥做销毁，保证任一个或多个密钥的使用时间是被限制的，提高安全性。该密钥管理器303可以在需要新的种子时从随机数产生器304获取该种子并生成新密钥，并将新密钥提供给加解密器件301使用以替换原密钥。可以理解，密码系统30的一个或多个功能均可以由安全处理器31实现以降低成本，但是如果采用如图3所示的独立的所述密码系统30实现相关功能，就相当于使用高安全性的硬件加速器实现相关功能，使得加解密等操作可以与安全处理器31的其他操作相分离，可提高安全性。
在一种可选的实现方式中，所述安全处理器31还可以用于利用指纹输入接口242传输的所述指纹数据执行所述用户认证。或者，该认证功能可以由安全处理器系统23中另一指纹认证器(图中未示出)实现。该指纹认证器相当于是个硬件加速器，实现更快的处理速度和安全性。
在一种可替换的实现方式中，除了类似图4那样，通过所述安全存储器45存储所述安全操作系统软件和至少一个安全应用软件，还可通过系统存储器22来存储所述安全操作系统软件和至少一个安全应用软件。系统存储器22可以位于片上系统21所在的第一半导体芯片之外的另一第二半导体芯片上。如图2所示，所述片上系统21与所述系统存储器22可以通过芯片间专用接口相耦合。所述系统存储器22可以包括互相隔离的安全存储区域和普通存储区域。所述安全存储区域用于存储所述安全操作系统软件和至少一个安全应用软件；所述普通存储区域用于存储所述通用操作系统软件。所述至少一个中央处理单元211，用于通过所述芯片间接口从所述普通存储区域获取所述通用操作系统软件并运行所述通用操作系统软件；所述安全处理器31，用于通过所述芯片间接口、系统总线210和安全总线35从所述安全存储区域获取安全操作系统软件和所述至少一个安全应用软件，并运行所述安全操作系统软件和所述至少一个安全应用软件。互相隔离的安全存储区域和普通存储区域意味着，对 于中央处理单元211运行的通用操作系统软件或基于通用操作系统软件的其他普通软件，其仅能读写普通存储区域，不能读写安全存储区域。该安全存储区域是被专用于执行安全应用的区域，由所述安全处理器31所访问和读写。由于系统存储器22可以同时存储安全软件和非安全软件，不需要依赖额外的类似安全存储器45那样的专用存储器，降低了成本。可选地，本发明的各个实施例中系统存储器22和安全存储器45可以都是Flash。
本发明实施例提出了一种可支持多种安全应用业务的片上系统21。其中的安全处理器系统23也可以叫做安全保护模块(Security Protection Module，SPM)，其功能上与银行卡中的安全元件类似，但实现了更高的安全性和集成度，其安全性可达到金融行业应用的CC EAL4+(Common Criteria Evaluation Assurance Level4+，通用准则评估保证级别4+)，实现各类安全应用产品或解决方案的安全性、可靠性，以及对信息隐私的保护目的。相对于现有的非集成方案或低集成度方案，成本大大降低，省略了复杂的芯片之间的调试和PCB上布局空间。且在本片上系统21中的中央处理单元211和安全处理器系统23采用完全相同的集成电路制作工艺，性能更加优化。并且，本实施例的方案在安全处理器系统23集成了多种对外接口，相关数据的传输不再依赖于中央处理单元211的TEE。
在一种实现方式中，如图9所示，给出了一种采用系统存储器22作为安全操作系统软件和所述至少一个安全应用软件的存储器的应用场景的示意图。该使用场景可以不涉及任何专用的安全存储器，实现成本较低。具体如图9中的虚线所示，安全处理器31可通过安全总线35、隔离存储器36(或总线桥)与系统总线210访问系统存储器22，向系统存储器22中的安全存储区域写入数据或读取该安全存储区域中的数据，以实现对该安全存储区域中安全操作系统软件和所述至少一个安全应用软件的读取或写入。数据或信息在该安全存储区域和安全处理器31之间交互的时候可以是经过加密或鉴权运算的，保证数据私密性和数据并不被篡改。所述加密或鉴权运算的具体运算形式有多种，此处不赘述。安全处理器系统23具有专门的用于访问该安全存储区域所需的访问权限。安全处理器31可进一步通过NFC接口241耦合至NFC处理器41，并通过NFC处理器41与NFC对端交互与所述移动支付相关的NFC信息，如 移动支付指令、移动支付数据或NFC认证信息等，并执行移动支付相关的运算，将运算后的结果存入安全存储区域。所述结果包括本次移动支付的支付信息，如交易额或交易时间等。
在另一种实现方式中，如图10所示，给出了一种采用专用的安全存储器45作为安全操作系统软件和所述至少一个安全应用软件的存储器的应用场景的示意图。具体如图10中的虚线所示，安全处理器31可通过安全总线35和存储接口245访问安全存储器45，以实现对安全操作系统软件和所述至少一个安全应用软件的读取或写入。例如，安全处理器31通过NFC处理器41从NFC对端接收与所述移动支付相关的NFC信息，并执行移动支付运算处理操作，并将操作后的数据结果存入安全存储器45。图10的场景相对于图9的应用场景，由于可避免数据在安全级别更低的系统总线210上传输，减少待传输数据的暴露风险，安全性更好。
在一种实现方式中，所述片上系统21执行移动支付相关方法的示意性流程图可以如图11所示，包括：在S111中，中央处理单元211上电启动。在S112中，中央处理单元211在完成启动后进一步触发安全处理器系统23启动，包括启动安全处理器31。在S113中，将安全操作系统软件和所述至少一个安全应用软件加载进入安全处理器系统23内，例如可加载到安全处理器31中或密码系统30中。具体地，可从专用的安全存储器45或系统存储器22的安全存储区域中获取相关软件数据并做相应加载。在S114中，安全处理器31或密码系统30对安全操作系统软件和所述至少一个安全应用软件做安全认证，例如由认证器件302执行程序完整性校验和签名的校验中的至少一种操作，如可选择性执行CRC校验等。如果校验不通过，则在S115中，复位安全处理器系统23，例如可以选择性的对该安全处理器系统23执行重新启动。如果所述校验通过，则在S116中，将相关软件的数据导入到随机存储器32中，以使得安全处理器31利用随机存储器32提供的存储空间执行相关软件的运算操作。当没有任何安全应用软件需要被运行的时候，安全处理器系统23或其中的部分部件，如安全处理器31可进入低功耗状态，即待机状态。安全处理器31可以在此状态下暂时停止工作，以节省功耗。在S117中，移动支付应用软件或NFC处理器41通过NFC接口241唤醒安全处理器系统23。当有移动支付应用需 求，则NFC处理器41或移动支付应用软件均可用于唤醒安全处理器系统23，使得安全处理器系统23或其中的安全处理器31从低功耗状态恢复为唤醒状态。可选地，在S118中，安全处理器31可判断移动支付应用软件是否已经被开启。如果该应用需求是由NFC处理器41触发的，那么安全处理器31需要执行该判断以确定相关应用软件是否已经开启。如果否，在S119中，安全处理器31需要启动该移动支付应用软件，即从外部存储器，如安全存储器45或系统存储器22的安全存储区域中读取相关软件数据并载入到随机存储器32中，以便执行该软件应用相关的处理或运算。如果移动支付应用软件已经被开启，则在S120中，安全处理器31进行正常的支付交易运算，例如包括与NFC处理器41进一步交互移动支付相关的信息，并利用随机存储器32提供的存储空间执行相关软件运算得到关于移动支付的运算结果，该运算结果包括交易相关的中间数据或交易结果，如交易金额或交易时间。在S120中，可能会需要用户输入与交易相关的金额或输入生物识别数据。该生物识别数据被移动终端20中的生物识别传感器采集，并被通过生物识别输入接口传输至安全处理器系统23，以便进行用户认证或云侧的用户认证。例如，可以使用类似图3的指纹输入接口实现基于指纹识别的用户认证，本实施例对此不作赘述。在S121中，安全处理器31将交易结果存入外部存储器，如安全存储器45或之前所述的安全存储区域，以便记录交易信息。
在图12中，展示了一种使用安全处理器系统23执行语音信号加密的应用场景的示意图。通信处理器213可以向无线接入点发送第一通信数据或从所述无线接入点接收第二通信数据。语音信号处理器214可以对来自用户的语音信号做处理生成由所述通信处理器213发送的所述第一通信数据，或用于对所述通信处理器213接收的所述第二通信数据做处理得到用户所需的语音信号，信号传输方向如图12中虚线所示。在执行相应的语音通信的时候，所述密码系统30中的加解密器件301还用于对所述第一通信数据进行加密处理或对第二通信数据进行解密处理。因此该加解密器件301除了执行移动支付相关的安全操作，还可用于执行基于语音信号的通信数据的加解密处理，实现了安全处理能力多样化。
在以上实现方式中，所述通信处理器213可以包括基带通信处理器和RF 处理器。在通信模式上，该通信处理器213可以包括蜂窝通信处理器或短距离通信处理器。也就是说通信传输的方式或支持的通信协议可以有多种。所述无线接入点可以是一个WIFi接入点，如WIFi路由器，此时的所述通信处理器213是一个WIFi通信处理器。所述无线接入点也可以是一个基站，如支持GSM、UMTS、WiMAX、TDS-CDMA、CDMA2000、LTE或5G的蜂窝通信接入点，则此时的通信处理器213是一个与该接入点通信的蜂窝通信处理器。该蜂窝通信接入点例如可以是LTE基站，如eNodeB。因此，该语音信号可以是PS域语音信号，如VoLTE语音信号。或者该语音信号也可以是CS域语音信号，如GSM、WCDMA或CDMA2000语音信号。在本应用场景下，用户可以通过输入设备，如麦克风输入声音信号，并通过系统外设接口215和系统总线210向语音信号处理器214传输声音信号，该声音信号被语音信号处理器214处理，并通过系统总线210、隔离存储器36(或总线桥)、和安全总线35传输至密码系统30，并由密码系统30中的加解密器件301进行加密，并将加密的数据通过安全总线35、隔离存储器36(或总线桥)和系统总线210传输至通信处理器213，以便由通信处理器213将加密后的数据传输至无线接入点，以提高安全性。反之，当通信处理器213收到无线接入点发来的已经加密的语音信号，会通过类似的信号传输路径传输给加解密器件301，由加解密器件301解密后得到语音信息并传输给语音信号处理器214，由语音信号处理器214处理该信号得到声音信号。本实施例中的该声音信号是一个模拟的语音信号并可以通过扬声器播放该声音信号给用户，实现用户安全通话的功能。可替换地，加解密器件301的解密功能也可以由安全处理器31实现。
在一种实现方式中，在图13中，展示了一种通过云侧服务器执行基于指纹数据的用户认证的应用场景的示意图，具体信号传输方向如图13中虚线所示。所述加解密器件301还用于对所述指纹传感器42采集的指纹数据进行加密处理得到加密后的指纹数据。所述通信处理器213将所述加密后的指纹数据通过无线接入点发送至用于进行所述用户认证的服务器，由服务器对指纹数据做用户认证并通过无线接入点给通信处理器213返回认证结果，该认证结果被提供至安全处理器31，以便安全处理器31在获知该基于指纹数据的用户认证获得通过时继续执行相关安全操作，如继续移动支付操作。这种认证方式也就 是云侧认证，减少移动终端20处理认证的开销。具体地，无论是由安全处理器31或安全处理器系统23内的其他部件做用户认证，或是上传至云侧服务器做用户认证，安全处理器系统23需要将指纹传感器42采集的指纹数据与预先存储的指纹数据做比对，以验证是否通过认证。
当指纹传感器42采集的指纹数据后，会触发安全处理器31执行相关认证操作，安全处理器31会触发从外部存储器获取预先存储指纹数据，例如类似图14那样通过存储接口245从安全存储器45读取相关指纹数据，或者通过系统存储器22的安全存储区域读取所述指纹数据。该预先存储的指纹数据可以是之前由指纹传感器42采集的用户的指纹数据并保存在外部存储器中，以供后续比对。优选地，通过使用专用的安全存储器45保存指纹数据是更优的选择。具体如图14所示的信号传输路径，安全处理器31可以在首次采集用户指纹数据时，将从指纹传感器42得到的指纹数据存入安全存储器45，以供后续的指纹数据比对使用，可避免机密的指纹数据在安全性低的系统总线210上传输，减少数据泄露的可能性。
如图15所示，还提供一种在移动支付过程中的处理方法，该方法由之前提到的片上系统21中的安全处理器系统23所执行，其中对生物认证以指纹识别为例作为说明。在S151中，安全处理器系统23通过所述NFC接口241与NFC对端(如POS机等通信设备)交互与所述移动支付相关的NFC信息，该NFC信息可以包括移动支付指令，例如由安全处理器系统23向NFC对端请求执行移动支付的请求消息或连接建立消息，安全处理器系统23可进一步从NFC对端接收同意建立连接的消息或请求消息的响应消息。或者该NFC信息可以进一步包括移动支付数据，如从NFC对端发送的交易金额或交易时间信息等。或者该NFC信息可以进一步包括NFC认证信息，如安全处理器系统23和NFC对端执行双向认证以验证对方是否合法的交互消息。所述NFC信息是为了完成移动支付而发生在安全处理器系统23和NFC对端之间的信息交互。在S152中，安全处理器系统23从指纹传感器42接收指纹数据，所述指纹数据在所述移动支付中被用于做基于指纹识别的用户认证。如之前所述，该用户认证用于验证使用该移动终端20的用户是否是合法用户，该认证可以由安全处理器系统23执行，也可以由云侧服务器执行。可以理解，正如之前实 施例所介绍的那样，指纹识别也可以由其他生物认证方式所代替，如虹膜识别、声纹识别、人脸识别、或气味识别。由于用户独特的人体特征，如指纹或气味可以使该用户区别于其他用户，从而通过比较该特征相关的数据与预先保存的数据实现对用户的认证。在S153中，安全处理器系统23通过用户界面(UI)向用户显示至少一项显示信息。可选地，所述显示信息包括用户信息输入界面、所述移动支付的交易界面或交易成功界面的至少一项。该用户界面用来向用户展示移动支付的相关显示信息，包括交易金额或交易时间等，也可以选择性的实现一些用户输入，其可以形成在触摸屏或显示屏等硬件设备上。所述触摸屏或显示屏具体可以是通过安全输入接口243直接耦合至安全处理器系统23。或者可替换地，该触摸屏或显示屏可以通过系统外设接口215耦合至系统总线210。安全处理器系统23此时需要将待显示的显示信息通过安全总线35、隔离存储器36(或总线桥)、和系统总线210传输至系统外设接口215，并通过该系统外设接口215传输至触摸屏或显示屏进行显示，以便于用户在该触摸屏或显示屏所形成的用户界面上观看该显示信息。可选地，所述用户界面被至少一个中央处理单元211运行的基于所述通用操作系统软件的UI软件驱动所形成，或者是被所述安全处理器31运行所述至少一个安全应用软件中的安全UI软件驱动所形成。可以理解，本方法中的步骤S15、S152和S153并没有严格的执行顺序。
可以理解，本发明的各个实施例所涉及到的由软件所执行的方法或流程的全部或部分步骤也可以以软件功能单元的形式实现并作为独立的产品销售或使用，相关软件功能单元可以是计算机程序产品，可存储在一个计算机可读取存储介质中。该计算机程序产品可以包括之前实施例提到的通用操作系统软件、基于所述通用操作系统软件的普通应用软件、安全操作系统软件和基于所述安全操作系统软件的至少一个安全应用软件中的全部或部分软件。基于这样的理解，该方法相应的技术方案的至少部分可以计算机代码的形式体现出来，该计算机代码可以被存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是之前提到的移动终端、或个人计算机等)执行相应方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(ROM，Read-Only Memory)、随机存储器(RAM，Random Access Memory)、磁碟或 者光盘等各种可以存储程序代码的介质。
可以理解，本发明实施例提到的移动终端20的一种典型应用场景可以是手机，如各类智能手机。所述片上系统21内的每个部件，如至少一个处理器或安全处理器系统23都可以包括多个晶体管或逻辑门电路，并可以在必要的软件驱动下工作。或者，部分器件可以选择性地无需软件而工作，如可以是一个纯硬件加速器。
需要说明的是，本发明实施例中的移动支付是一个广义上的定义，其不仅包括商业、金融上的移动支付业务，也包括公共交通、身份证、社保卡等其他类型的支付业务。也就是说，通过移动支付，移动终端可以与通信对端连接最终实现与服务器的交互支付信息，并实现与该移动终端内一个或多个账户相关联的数据交易、数据兑换或数据结算。数据交易、兑换或数据结算的单位可以不仅包括货币，也可以是虚拟货币、各类积分或信用额度等其他能够用于实现支付、兑换或交易结算的单位，本实施例对此不做限定。所述账户包括但不限于个人账户、团体账户或组织账户。相对于仅在固定终端上实施的支付行为，移动支付实现更加灵活，其执行主体为图2所示的移动终端20，可以更好满足随时随地执行支付的需求。
需要说明的是，本发明实施例提到的片上系统21是应用于一个移动终端20的，但实际上也可以应用于不具有移动通信功能的其他处理设备，如不具有移动通信能力的手持设备。因此本发明实施例提到的片上系统21中的一些器件或单元的功能不是必需的，比如其中至少一个处理器是可以省略的，例如图像处理单元212、通信处理器213、语音信号处理器214、系统外设215、或图像信号处理器217等的一个或多个可选择性被省略。其中的中央处理单元211或系统功耗管理单元216也可以省略并由功能和设计上更加简单的控制电路所代替。因此包括片上系统21的相关处理设备的形态如何也是不被限定的。
以上所述仅为本发明的几个实施例，本领域的技术人员依据申请文件公开的可以对本发明进行各种改动或变型而不脱离本发明的精神和范围。例如本发明实施例的附图中的各个部件具体形状或结构是可以根据实际应用场景进行调整的。

Claims (25)

  1. 一种片上系统SoC，其特征在于，所述SoC集成于第一半导体芯片上，包括：系统总线、耦合于所述系统总线的至少一个处理器、和耦合于所述系统总线的安全处理器系统；所述安全处理器系统与所述至少一个处理器间存在安全隔离；
    所述至少一个处理器包括至少一个中央处理单元，所述至少一个中央处理单元用于运行通用操作系统软件，并在所述通用操作系统软件的作用下通过所述系统总线与所述安全处理器系统通信；
    所述安全处理器系统包括安全处理器、第一存储器、多个接口和安全总线，所述安全处理器、第一存储器和多个接口均耦合于所述安全总线，且所述安全总线耦合于所述系统总线；其中，
    所述安全处理器，用于运行安全操作系统软件和基于所述安全操作系统软件的至少一个安全应用软件，所述至少一个安全应用软件包括用于实现移动支付的移动支付软件；
    所述第一存储器，用于提供所述安全处理器运行所述安全操作系统软件和所述至少一个安全应用软件所需的存储空间；
    所述多个接口包括近场通信NFC接口和生物识别输入接口；其中，
    所述NFC接口，用于经由NFC处理器与NFC对端交互与所述移动支付相关的NFC信息；
    所述生物识别输入接口，用于从生物识别传感器接收生物识别数据，所述生物识别数据在所述移动支付中被用于做基于生物识别的用户认证。
  2. 根据权利要求1所述的SoC，其特征在于，所述多个接口还包括安全输入接口，用于接收用户输入的与所述移动支付相关的用户信息。
  3. 根据权利要求1或2所述的SoC，其特征在于，所述多个接口还包括外设接口，用于通过外围设备向用户指示所述移动支付被执行。
  4. 根据权利要求1至3中任一项所述的SoC，其特征在于，所述安全处理器系统还包括耦合于所述安全总线的非掉电易失性的第二存储器，用于存储所述安全操作系统软件和至少一个安全应用软件；
    所述安全处理器用于从所述第二存储器读取所述安全操作系统软件和至 少一个安全应用软件，并将所述安全操作系统软件和至少一个安全应用软件加载到所述第一存储器中以运行所述安全操作系统软件和至少一个安全应用软件。
  5. 根据权利要求1至4中任一项所述的SoC，其特征在于，所述安全处理器系统还包括耦合于所述安全总线且用于实现所述安全隔离的安全隔离器件，所述至少一个处理器通过所述系统总线和所述安全隔离器件与所述安全处理器系统通信。
  6. 根据权利要求5所述的SoC，其特征在于，所述安全隔离器件包括隔离存储器或总线桥中的至少一项；所述隔离存储器或总线桥用于实现至少一个处理器和所述安全处理器系统交互数据或指令。
  7. 根据权利要求1至6中任一项所述的SoC，其特征在于，所述安全处理器系统还包括耦合于所述安全总线的安全启动存储器，用于存储所述安全处理器初始化所需的引导程序指令；
    所述安全处理器在运行所述安全操作系统软件和至少一个安全应用软件前，通过从所述安全启动存储器获取所述引导程序指令以初始化所述安全处理器。
  8. 根据权利要求7所述的SoC，其特征在于，所述引导程序指令是经过加密的引导程序指令；
    在所述安全处理器从所述安全启动存储器获取所述引导程序指令时，所述引导程序指令被解密逻辑电路解密以得到解密后的引导程序指令，所述解密后的引导程序指令被用于初始化所述安全处理器。
  9. 根据权利要求1至8中任一项所述的SoC，其特征在于，所述安全处理器系统还包括耦合于所述安全总线的一次性可编程存储器，用于存储所述安全处理器系统的安全参数，所述安全参数包括根密钥、校准参数、配置参数、或使能参数中的至少一项。
  10. 根据权利要求9所述的SoC，其特征在于，所述一次性可编程存储器还用于存储所述安全处理器初始化所需的引导程序指令的补丁程序指令。
  11. 根据权利要求1至10中任一项所述的SoC，其特征在于，所述安全处理器系统还包括防攻击传感器，用于检测所述安全处理器系统的工作参数的 异常，并在发生所述异常时触发以下至少一项操作：所述安全处理器系统进行告警、所述安全处理器复位、或所述第一存储器或所述安全处理器系统中的至少一个寄存器被复位或清空；
    所述工作参数包括电压、电流、时钟频率、温度或激光强度中的至少一项。
  12. 根据权利要求1至11中任一项所述的SoC，其特征在于，所述安全处理器系统还包括防攻击金属层，该防攻击金属层位于所述第一半导体芯片中的最上一层或多层、并在版图布局上覆盖所述安全处理器系统的至少一部分；
    所述防攻击金属层用于检测来自外界的物理探测或攻击，并在检测到所述物理探测或攻击时产生电信号，该电信号用于触发以下至少一项操作：所述安全处理器系统进行告警、所述安全处理器复位、或所述第一存储器或所述安全处理器系统中的至少一个寄存器被复位或清空。
  13. 根据权利要求1至12中任一项所述的SoC，其特征在于，所述安全总线包括高级高性能总线AHB或高级外围总线APB中的至少一项。
  14. 根据权利要求1至13中任一项所述的SoC，其特征在于，所述安全处理器系统还包括耦合于所述安全总线的直接存储器存取DMA控制器，用于从所述第一存储器读取数据并输出至所述安全总线或通过所述安全总线将数据写入所述第一存储器。
  15. 根据权利要求1至14中任一项所述的SoC，其特征在于，所述安全处理器系统还包括耦合于所述安全总线的密码系统，所述密码系统包括如下至少一项：
    加解密器件，用于对所述安全处理器系统中的至少一种数据进行加解密处理；
    认证器件，用于对所述安全处理器系统中的至少一种数据进行认证；
    随机数产生器，用于产生随机数，该随机数用于作为生成密钥的种子或芯片的唯一标识；或
    密钥管理器，用于在所述安全处理器系统中生成、分发或销毁用于做所述加解密处理或认证所需的密钥。
  16. 根据权利要求15所述的SoC，其特征在于，所述至少一个处理器还包括：
    通信处理器，用于向无线接入点发送第一通信数据或从所述无线接入点接收第二通信数据；
    语音信号处理器，用于对来自用户的语音信号做处理生成由所述通信处理器发送的所述第一通信数据，或用于对所述通信处理器接收的所述第二通信数据做处理得到用户所需的语音信号；
    所述加解密器件还用于对所述第一通信数据进行加密处理或对第二通信数据进行解密处理。
  17. 根据权利要求15所述的SoC，其特征在于，所述至少一个处理器还包括：通信处理器；
    所述加解密器件还用于对所述生物识别数据进行加密处理得到加密后的生物识别数据；
    所述通信处理器，用于将所述加密后的生物识别数据通过无线接入点发送至用于进行所述用户认证的服务器。
  18. 根据权利要求16或17所述的SoC，其特征在于，所述通信处理器包括蜂窝通信处理器或短距离通信处理器中的至少一项。
  19. 根据权利要求1至18中任一项所述的SoC，其特征在于，所述安全处理器还用于利用所述生物识别数据执行所述用户认证。
  20. 根据权利要求1至19中任一项所述的SoC，其特征在于，所述安全处理器系统还包括：生物识别认证器，用于利用所述生物识别数据执行所述用户认证。
  21. 根据权利要求1至20中任一项所述的SoC，其特征在于，在所述安全隔离下，所述至少一个处理器无法直接访问所述第一存储器或所述安全处理器系统中的至少一个寄存器。
  22. 根据权利要求1至21中任一项所述的SoC，其特征在于，所述生物识别包括如下至少一项：指纹识别、虹膜识别、声纹识别、人脸识别、或气味识别。
  23. 根据权利要求1至22中任一项所述的SoC，其特征在于，所述多个接口还包括存储接口，用于耦合至第三存储器；
    所述第三存储器用于存储所述安全操作系统软件和至少一个安全应用软 件；
    所述安全处理器用于通过所述存储接口从所述第三存储器读取所述安全操作系统软件和至少一个安全应用软件，并将所述安全操作系统软件和至少一个安全应用软件加载到所述第一存储器中以运行所述安全操作系统软件和至少一个安全应用软件。
  24. 一种处理设备，其特征在于，包括根据权利要求23所述的SoC以及所述第三存储器，所述第三存储器集成于第二半导体芯片上。
  25. 一种处理设备，包括根据权利要求1至22中任一项所述的SoC、以及集成于第三半导体芯片上的第四存储器，所述SoC与所述第四存储器通过芯片间接口相耦合，所述第四存储器包括互相隔离的安全存储区域和普通存储区域；
    所述安全存储区域用于存储所述安全操作系统软件和至少一个安全应用软件；
    所述普通存储区域用于存储所述通用操作系统软件；
    所述至少一个中央处理单元，用于通过所述芯片间接口从所述普通存储区域获取所述通用操作系统软件并运行所述通用操作系统软件；
    所述安全处理器，用于通过所述芯片间接口、系统总线和安全总线从所述安全存储区域获取安全操作系统软件和所述至少一个安全应用软件，并运行所述安全操作系统软件和所述至少一个安全应用软件。
PCT/CN2016/094226 2016-08-09 2016-08-09 一种片上系统和处理设备 Ceased WO2018027587A1 (zh)

Priority Applications (7)

Application Number Priority Date Filing Date Title
EP16912042.5A EP3461016A4 (en) 2016-08-09 2016-08-09 SYSTEM ON CHIP AND PROCESSING DEVICE
PCT/CN2016/094226 WO2018027587A1 (zh) 2016-08-09 2016-08-09 一种片上系统和处理设备
KR1020187033145A KR20180135940A (ko) 2016-08-09 2016-08-09 시스템 온 칩 및 처리 장치
BR112018073991-0A BR112018073991A2 (pt) 2016-08-09 2016-08-09 sistema em chip e dispositivo de processamento
CN201680084559.4A CN109075815A (zh) 2016-08-09 2016-08-09 一种片上系统和处理设备
TW106126726A TWI633438B (zh) 2016-08-09 2017-08-08 系統晶片和處理設備
US16/268,294 US20190172047A1 (en) 2016-08-09 2019-02-05 System on chip and processing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2016/094226 WO2018027587A1 (zh) 2016-08-09 2016-08-09 一种片上系统和处理设备

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US16/268,294 Continuation US20190172047A1 (en) 2016-08-09 2019-02-05 System on chip and processing device

Publications (1)

Publication Number Publication Date
WO2018027587A1 true WO2018027587A1 (zh) 2018-02-15

Family

ID=61161246

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/094226 Ceased WO2018027587A1 (zh) 2016-08-09 2016-08-09 一种片上系统和处理设备

Country Status (7)

Country Link
US (1) US20190172047A1 (zh)
EP (1) EP3461016A4 (zh)
KR (1) KR20180135940A (zh)
CN (1) CN109075815A (zh)
BR (1) BR112018073991A2 (zh)
TW (1) TWI633438B (zh)
WO (1) WO2018027587A1 (zh)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112100016A (zh) * 2020-07-27 2020-12-18 珠海亿智电子科技有限公司 一种系统异常场景下的soc诊断方法及系统
CN112184974A (zh) * 2020-09-27 2021-01-05 江苏天创科技有限公司 一种基于5g通讯节点的监测系统
CN112309006A (zh) * 2020-10-19 2021-02-02 深圳市信锐网科技术有限公司 一种门锁设备及信息处理方法、存储介质
CN113902080A (zh) * 2020-06-22 2022-01-07 三星电子株式会社 生物特征认证智能卡
US11308495B2 (en) * 2017-12-11 2022-04-19 Feitian Technologies Co., Ltd. Financial card with function of fingerprint verification and working method therefor
US11405202B2 (en) 2018-06-14 2022-08-02 Huawei Technologies Co., Ltd. Key processing method and apparatus
CN115130146A (zh) * 2021-03-29 2022-09-30 广东跃昉科技有限公司 Soc芯片及应用于soc芯片的数据处理方法

Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10897360B2 (en) 2017-01-26 2021-01-19 Microsoft Technology Licensing, Llc Addressing a trusted execution environment using clean room provisioning
US10897459B2 (en) * 2017-01-26 2021-01-19 Microsoft Technology Licensing, Llc Addressing a trusted execution environment using encryption key
US10972265B2 (en) 2017-01-26 2021-04-06 Microsoft Technology Licensing, Llc Addressing a trusted execution environment
CN109862553B (zh) * 2017-11-30 2022-07-12 华为技术有限公司 终端和通信方法
KR102635811B1 (ko) * 2018-03-19 2024-02-13 삼성전자 주식회사 사운드 데이터를 처리하는 시스템 및 시스템의 제어 방법
EP3570197A1 (en) * 2018-05-16 2019-11-20 Gemalto Sa Electronic system and method for preventing malicious actions on a processing system of the electronic system
GB2578158B (en) * 2018-10-19 2021-02-17 Advanced Risc Mach Ltd Parameter signature for realm security configuration parameters
JP2020087293A (ja) * 2018-11-30 2020-06-04 キヤノン株式会社 情報処理装置および情報処理装置の制御方法
US11275820B2 (en) 2019-03-08 2022-03-15 Master Lock Company Llc Locking device biometric access
KR102621645B1 (ko) * 2019-03-12 2024-01-05 삼성전자주식회사 보안 집적 회로를 포함하는 전자 장치
CN112020043B (zh) * 2019-05-28 2024-11-05 瑞昱半导体股份有限公司 蓝牙装置与其操作方法及非瞬时计算机可读记录介质
EP3761201B1 (en) * 2019-07-03 2024-08-07 Nokia Technologies Oy Cryptographic memory attestation
WO2021087417A1 (en) * 2019-11-01 2021-05-06 Google Llc Alert handling
CN111292716A (zh) * 2020-02-13 2020-06-16 百度在线网络技术（北京）有限公司 语音芯片和电子设备
WO2021167617A1 (en) * 2020-02-21 2021-08-26 Hewlett-Packard Development Company, L.P. Computing devices for encryption and decryption of data
TWI760703B (zh) * 2020-03-05 2022-04-11 香港商冠捷投資有限公司 資料修復方法及模組及顯示裝置
US11880454B2 (en) * 2020-05-14 2024-01-23 Qualcomm Incorporated On-die voltage-frequency security monitor
KR102857871B1 (ko) * 2020-06-22 2025-09-10 삼성전자주식회사 생체인증 기반 스마트카드
CN111901363B (zh) * 2020-08-12 2022-05-17 吉林大学 一种基于FPGA的5G—Profibus-DP数据加密传输装置
CN112330852A (zh) * 2020-09-08 2021-02-05 深圳晒尔科技有限公司 多功能物联门锁电路板及物联门锁装置
WO2022055490A1 (en) * 2020-09-11 2022-03-17 Google Llc Hardware-based save-and-restore controller
TWI758866B (zh) * 2020-09-16 2022-03-21 英業達股份有限公司 系統單晶片產品的嚴重錯誤提供方法及嚴重錯誤識別方法
US20220166762A1 (en) * 2020-11-25 2022-05-26 Microsoft Technology Licensing, Llc Integrated circuit for obtaining enhanced privileges for a network-based resource and performing actions in accordance therewith
CN116601629A (zh) * 2021-01-25 2023-08-15 华为技术有限公司 一种终端芯片及其度量方法
JP7610428B2 (ja) * 2021-03-02 2025-01-08 日立Astemo株式会社 制御装置
CN113010470B (zh) * 2021-03-30 2023-06-20 上海西井信息科技有限公司 边缘节点远程控制系统、方法、设备及存储介质
WO2022226520A1 (en) 2021-04-23 2022-10-27 Google Llc Secure serial peripheral interface communication
US12566835B2 (en) 2021-09-24 2026-03-03 Apple Inc. Quick response codes for data transfer
FR3128545A1 (fr) * 2021-10-25 2023-04-28 STMicroelectronics (Grand Ouest) SAS Procédé de transaction entre une application et un périphérique
CN113821834B (zh) * 2021-11-24 2022-02-15 飞腾信息技术有限公司 数据处理方法、安全架构系统和计算设备
CN114238946B (zh) * 2022-02-23 2022-05-03 湖北芯擎科技有限公司 设备管理方法、装置、电子设备及计算机可读存储介质
CN115455396A (zh) * 2022-03-08 2022-12-09 神盾股份有限公司 用于处理指纹信息的方法、硬件加速器及指纹识别设备
CN115174431B (zh) * 2022-06-30 2023-09-05 无锡融卡科技有限公司 一种简易的swp全双工逻辑信号采集装置及方法
KR102772789B1 (ko) * 2022-08-16 2025-02-27 국방과학연구소 전자 장치 및 그의 물리 공격 모니터링 방법
US20240231471A1 (en) * 2023-01-11 2024-07-11 Meta Platforms Technologies, Llc Artificial reality system having a system on a chip with an integrated reduced power microcontroller and application transition
US12561440B2 (en) * 2023-07-31 2026-02-24 Hewlett Packard Enterprise Development Lp Integrity validation of management devices
US12231580B1 (en) * 2024-03-12 2025-02-18 Citigroup Technology, Inc. Systems and methods for establishing data provenance by generating one-time signatures
US20260087130A1 (en) * 2024-09-26 2026-03-26 Nvidia Corporation Detecting and preventing frequency attacks
CN121187990B (zh) * 2025-11-27 2026-03-20 四川华鲲振宇智能科技有限责任公司 解决安卓和X86系统在同一产品上切换Touchpad黄标的方法及系统

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101299228A (zh) * 2008-01-26 2008-11-05 青岛大学 一种基于单cpu双总线的安全网络终端
CN203057229U (zh) * 2012-12-26 2013-07-10 福建联迪商用设备有限公司 带指纹识别功能的pos手机
CN104778794A (zh) * 2015-04-24 2015-07-15 华为技术有限公司 移动支付装置和方法
US20150324791A1 (en) * 2014-05-06 2015-11-12 Apple Inc. Storage of credential service provider data in a security domain of a secure element
CN105354706A (zh) * 2015-10-08 2016-02-24 广东欧珀移动通信有限公司 Nfc安全支付方法和系统

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9002014B2 (en) * 2008-05-24 2015-04-07 Via Technologies, Inc. On-die cryptographic apparatus in a secure microprocessor
CN202093521U (zh) * 2011-03-24 2011-12-28 重庆大学 一种计算机身份认证系统
US20130054473A1 (en) * 2011-08-23 2013-02-28 Htc Corporation Secure Payment Method, Mobile Device and Secure Payment System
US9436940B2 (en) * 2012-07-09 2016-09-06 Maxim Integrated Products, Inc. Embedded secure element for authentication, storage and transaction within a mobile terminal
US20140244513A1 (en) * 2013-02-22 2014-08-28 Miguel Ballesteros Data protection in near field communications (nfc) transactions
CN104268487B (zh) * 2014-09-23 2017-04-26 杭州晟元数据安全技术股份有限公司 一种安全芯片的复位和自毁管理系统

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101299228A (zh) * 2008-01-26 2008-11-05 青岛大学 一种基于单cpu双总线的安全网络终端
CN203057229U (zh) * 2012-12-26 2013-07-10 福建联迪商用设备有限公司 带指纹识别功能的pos手机
US20150324791A1 (en) * 2014-05-06 2015-11-12 Apple Inc. Storage of credential service provider data in a security domain of a secure element
CN104778794A (zh) * 2015-04-24 2015-07-15 华为技术有限公司 移动支付装置和方法
CN105354706A (zh) * 2015-10-08 2016-02-24 广东欧珀移动通信有限公司 Nfc安全支付方法和系统

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3461016A4

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11308495B2 (en) * 2017-12-11 2022-04-19 Feitian Technologies Co., Ltd. Financial card with function of fingerprint verification and working method therefor
US11405202B2 (en) 2018-06-14 2022-08-02 Huawei Technologies Co., Ltd. Key processing method and apparatus
CN113902080A (zh) * 2020-06-22 2022-01-07 三星电子株式会社 生物特征认证智能卡
CN112100016A (zh) * 2020-07-27 2020-12-18 珠海亿智电子科技有限公司 一种系统异常场景下的soc诊断方法及系统
CN112100016B (zh) * 2020-07-27 2023-07-14 珠海亿智电子科技有限公司 一种系统异常场景下的soc诊断方法及系统
CN112184974A (zh) * 2020-09-27 2021-01-05 江苏天创科技有限公司 一种基于5g通讯节点的监测系统
CN112309006A (zh) * 2020-10-19 2021-02-02 深圳市信锐网科技术有限公司 一种门锁设备及信息处理方法、存储介质
CN115130146A (zh) * 2021-03-29 2022-09-30 广东跃昉科技有限公司 Soc芯片及应用于soc芯片的数据处理方法

Also Published As

Publication number Publication date
EP3461016A1 (en) 2019-03-27
TWI633438B (zh) 2018-08-21
BR112018073991A2 (pt) 2019-02-26
EP3461016A4 (en) 2019-06-12
TW201805824A (zh) 2018-02-16
US20190172047A1 (en) 2019-06-06
CN109075815A (zh) 2018-12-21
KR20180135940A (ko) 2018-12-21

Similar Documents

Publication Publication Date Title
TWI633438B (zh) 系統晶片和處理設備
US10853519B2 (en) System on chip and method for implementing secure operating system switching
US10366237B2 (en) Providing a trusted execution environment using a processor
JP6517926B2 (ja) モバイル支払い装置および方法
CN110741370B (zh) 利用用户输入的生物识别认证
US9891969B2 (en) Method and apparatus for device state based encryption key
WO2017177814A1 (zh) 一种控制多个安全应用软件的运行的装置和方法
KR20150034196A (ko) 하드웨어 강제 액세스 보호
TW201706899A (zh) 安全裝置及在其內提供安全服務至主機的方法、安全設備以及電腦軟體產品
KR102226665B1 (ko) 다수의 사용자를 갖는 보안 요소
CN108875412A (zh) 一种inSE安全模块
CN111736770A (zh) 嵌入式安全存储器
EP4273722A1 (en) Terminal chip and measurement method therefor

Legal Events

Date Code Title Description
ENP Entry into the national phase

Ref document number: 20187033145

Country of ref document: KR

Kind code of ref document: A

REG Reference to national code

Ref country code: BR

Ref legal event code: B01A

Ref document number: 112018073991

Country of ref document: BR

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16912042

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2018567806

Country of ref document: JP

Kind code of ref document: A

ENP Entry into the national phase

Ref document number: 2016912042

Country of ref document: EP

Effective date: 20181221

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 112018073991

Country of ref document: BR

Kind code of ref document: A2

Effective date: 20181122