WO2018032308A1 - 一种线性调整器 - Google Patents

一种线性调整器 Download PDF

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Publication number
WO2018032308A1
WO2018032308A1 PCT/CN2016/095428 CN2016095428W WO2018032308A1 WO 2018032308 A1 WO2018032308 A1 WO 2018032308A1 CN 2016095428 W CN2016095428 W CN 2016095428W WO 2018032308 A1 WO2018032308 A1 WO 2018032308A1
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Prior art keywords
voltage
output
circuit
linear regulator
input
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Ceased
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PCT/CN2016/095428
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English (en)
French (fr)
Inventor
王程左
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Shenzhen Goodix Technology Co Ltd
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Shenzhen Goodix Technology Co Ltd
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Priority to PCT/CN2016/095428 priority Critical patent/WO2018032308A1/zh
Priority to CN201680000905.6A priority patent/CN106537276B/zh
Priority to EP16897477.2A priority patent/EP3309646B1/en
Priority to KR1020177030870A priority patent/KR102124241B1/ko
Priority to US15/790,976 priority patent/US10248144B2/en
Publication of WO2018032308A1 publication Critical patent/WO2018032308A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current 
    • G05F1/46—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC
    • G05F1/56—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
    • G05F1/561—Voltage to current converters
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current 
    • G05F1/46—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC
    • G05F1/56—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
    • G05F1/575—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current 
    • G05F1/46—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC
    • G05F1/468—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC characterised by reference voltage circuitry, e.g. soft start, remote shutdown
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is DC
    • G05F3/10—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only

Definitions

  • the present invention relates to the field of electronic technologies, and in particular, to a linear regulator.
  • the linear regulator also known as the series regulator, converts the unstable input voltage into an adjustable DC output voltage for use as a power supply for other systems.
  • Linear regulators are often used for on-chip power management of mobile consumer electronics chips due to their simple structure, low static power consumption, and low output voltage ripple.
  • FIG. 1 is a schematic diagram showing the structure of a linear regulator in the prior art: the linear regulator includes: a biasing module 1, a reference voltage module 2, an error amplifier 3, a power regulating tube 4, and a sampling resistor network 5.
  • the input voltage V IN of the linear regulator is input to the bias module 1, the reference voltage module 2, and the power adjustment tube 4, respectively, and the bias module 1 provides the current bias and the error current required for the normal operation of the reference voltage module 2 and the error amplifier 3.
  • Voltage biasing the reference voltage module 2 generates a low-temperature drift reference voltage V REF to the error amplifier 3, and the error amplifier 3 error-amplifies the feedback voltages V FB and V REF of the sampling resistor network 5 for sampling the output voltage V O so that According to the result of the error amplification, the gate voltage of the power adjustment tube 4 is adjusted so that the output voltage V O is stably output.
  • the power consumption of the on-chip power management of the electronic device chip is required to be as low as possible to extend the use time of the device, so that the electronic device has a long standby time.
  • the linear regulator in the prior art is difficult to meet the requirement that the quiescent current of the electronic device is several hundred nanoamperes or even several tens of nanoamperes during standby.
  • the linear adjustment in the prior art The sampling resistor network 5 in the whole device will occupy a large chip area, which is not conducive to the development of miniaturization of electronic equipment.
  • One of the objects of embodiments of the present invention is to provide a linear regulator that makes the linear regulator have lower static power consumption and smaller chip footprint, and compensates for the inverted voltage follower by a voltage biasing module having positive temperature characteristics.
  • the negative temperature characteristic makes the linear regulator's output voltage also have good temperature characteristics without the need for a reference voltage module.
  • an embodiment of the present invention provides a linear regulator including: a current biasing module, a voltage biasing module having positive temperature characteristics, and a flip voltage follower;
  • the input end of the current biasing module receives the input voltage of the linear regulator, and the output of the current biasing module outputs a bias current
  • the first input end and the second input end of the voltage biasing module respectively receive an input voltage and a bias current, and an output terminal of the voltage biasing module outputs a bias voltage
  • the first input end and the second input end of the flip voltage follower respectively receive the input voltage and the bias voltage, and the output end of the flip voltage follower outputs the output voltage of the linear regulator.
  • the input voltage of the linear regulator is input to the input terminal of the current biasing module, the first input terminal of the voltage biasing module, and the first input terminal of the inverting voltage follower, the current is compared with the prior art.
  • the biasing module generates a bias current
  • the second input of the voltage biasing module receives the bias current
  • the voltage biasing module generates a bias voltage
  • the second input of the flipping voltage follower receives the biasing voltage
  • the output voltage of the regulator is output by the output of the inverted voltage follower.
  • the output voltage of the linear regulator is compensated by the flip voltage follower so that the output voltage of the linear regulator is relatively stable.
  • the voltage biasing module has a positive temperature characteristic and can compensate each other with the inverted voltage follower, canceling the negative temperature characteristic of the inverted voltage follower, so that the linear adjustment
  • the output voltage of the device has good temperature characteristics.
  • the linear regulator has the characteristics of low static power consumption and small chip footprint, and the linear regulator does not need to specifically set the reference voltage module, and the linear regulator output voltage has good temperature characteristics.
  • the current biasing module includes a bias current generating circuit and an auxiliary output circuit.
  • the input end of the bias current generating circuit is connected to the input voltage of the linear regulator; the output end of the bias current generating circuit is connected to the input end of the auxiliary output circuit; the output end of the auxiliary output circuit is connected to the input end of the voltage biasing module;
  • the input end of the bias current generating circuit and the output end of the auxiliary output circuit respectively form an input end and an output end of the current biasing module.
  • the bias current generating circuit is used to generate the required bias current (generally, the required bias current is a nanoampere bias current), and the auxiliary current output circuit is used to bias the current output of the bias current generating circuit. To voltage bias module.
  • the auxiliary output circuit includes a current mirror circuit and a field effect transistor; an input end of the current mirror circuit is connected to an output end of the bias current generating circuit, and an output end of the current mirror circuit is connected to a drain of the field effect transistor; The source and the gate are respectively connected to the input end and the output end of the current biasing module.
  • the auxiliary output circuit provides a specific implementation of the auxiliary output circuit, that is, the current mirror circuit is used to copy the bias current in the bias current generating circuit to the drain of the field effect transistor, so that the field effect transistor will bias current Input to the voltage bias module.
  • the use of an auxiliary output circuit having a current mirror circuit enables the bias current generating circuit to have greater flexibility in circuit design.
  • the auxiliary output circuit includes a field effect transistor; the drain and gate of the field effect transistor form an input and an output of the auxiliary output circuit, respectively.
  • This embodiment provides a specific implementation of the auxiliary output circuit, which increases the feasibility of the present invention.
  • the voltage biasing module includes a serial self-coherent sigma transistor SSCM (SSCM) circuit, which provides a specific implementation form of the voltage biasing module, which increases the feasibility of the present invention.
  • SSCM serial self-coherent sigma transistor
  • the SSCM circuit can operate in the sub-threshold region, so that the static power consumption of the linear regulator is small.
  • the flip voltage follower includes a folded cascode amplifier and a power adjustment tube; the first input end of the folded cascode amplifier and the emitter of the power adjustment tube form a first input end of the flip voltage follower;
  • the second input of the cascode amplifier forms a second input of the flip voltage follower;
  • the first output of the folded cascode amplifier is connected to the gate of the power regulating tube;
  • the folded cascode amplifier The second output forms an output of the flip voltage follower and is coupled to the drain of the power transfer transistor.
  • the output voltage of the linear regulator is sampled by a folded cascode amplifier, and the error is amplified.
  • the result of the error method is output and applied to the gate of the power adjustment tube to adjust the gate voltage of the power adjustment tube so that the output of the linear regulator The voltage is stable.
  • the flip voltage follower further includes an output capacitor; the output capacitor is connected between the output of the flip voltage follower and the ground. The output capacitor is used to ensure the stability of the linear regulator.
  • FIG. 1 is a schematic structural view of a linear adjuster in the prior art
  • FIG. 2 is a schematic structural view of a linear adjuster according to a first embodiment of the present invention
  • FIG. 3 is a circuit diagram of a linear regulator in accordance with a first embodiment of the present invention.
  • FIG. 4 is a circuit diagram of a nanoampere level bias current generating circuit in accordance with a first embodiment of the present invention
  • Figure 5 is a circuit diagram of a linear regulator in accordance with a second embodiment of the present invention.
  • a first embodiment of the present invention is directed to a linear regulator comprising: a current biasing module, a voltage biasing module having positive temperature characteristics, and a flip voltage follower, as shown in FIG.
  • the linear adjuster in this embodiment can be applied to a mobile terminal of a rechargeable battery, such as a mobile phone, a computer, a tablet computer, a wearable device, or the like.
  • the input of the current biasing module 6 receives the input voltage V IN of the linear regulator, and the output of the current biasing module 6 outputs a bias current.
  • the first input terminal and the second input terminal of the voltage biasing module 7 respectively receive the input voltage V IN and the bias current, and the output terminal of the voltage biasing module 7 outputs a bias voltage.
  • the first input terminal and the second input terminal of the flip voltage follower 8 respectively receive the input voltage V IN and the bias voltage, and the output terminal of the flip voltage follower 8 outputs the output voltage V O of the linear regulator.
  • the current biasing module 6 generates a bias current and outputs the bias current to the voltage biasing module 7, which generates a bias voltage.
  • Inverting voltage follower 8 using linear adjustment of the output voltage V O to compensate for follow, a more stable so that the output voltage V O to a linear regulator.
  • the voltage biasing module 7 has a positive temperature characteristic and can compensate each other with the inverted voltage follower 8 to cancel the negative temperature characteristic of the inverted voltage follower 8, so that the output voltage V O of the linear regulator has good temperature characteristics.
  • the current biasing module 6 includes a bias current generating circuit and an auxiliary output circuit.
  • the input of the bias current generating circuit is connected to the input voltage V IN of the linear regulator, and the output of the bias current generating circuit is connected to the input of the auxiliary output circuit.
  • the output of the auxiliary output circuit is connected to the input of the voltage biasing module 7.
  • the input end of the bias current generating circuit and the output end of the auxiliary output circuit respectively form an input end and an output end of the current biasing module.
  • the bias current generating circuit is used to generate the required bias current (generally, the required bias current is a nanoampere bias current), and the auxiliary current output circuit is used to bias the current output of the bias current generating circuit.
  • the auxiliary output circuit includes a current mirror circuit and a field effect transistor.
  • the input end of the current mirror circuit is connected to the output end of the bias current generating circuit, and the output end of the current mirror circuit is connected to the field effect The drain of the transistor.
  • the source and the gate of the field effect transistor are respectively connected to the input end and the output end of the current biasing module.
  • the current mirror circuit is used to replicate the bias current in the bias current generating circuit to the drain of the field effect transistor, so that the field effect transistor inputs the bias current into the voltage biasing module.
  • the use of an auxiliary output circuit having a current mirror circuit enables the bias current generating circuit to have greater flexibility in terms of selection.
  • the current biasing module 6 includes a bias current generating circuit and an auxiliary output circuit.
  • the bias current generating circuit is a nanoampere-level bias current generating circuit as shown in FIG.
  • the auxiliary output circuit includes a current mirror circuit and a field effect transistor M 2 .
  • the current mirror circuit includes a field effect transistor M 1 and 3, the drain of the field effect transistor M 1 as the input of the current mirror circuit, the drain of the field effect transistor M 3 as the output terminal of the current mirror circuit M.
  • An embodiment of a specific circuit of the nanoampere bias current generating circuit can be seen in FIG. As shown in FIG.
  • the sources of the field effect transistors M 8 , M 11 , M 13 , and M 15 serve as the input terminals of the nanoampere-level bias current generating circuit, and the drain of the field effect transistor M 15 serves as the nanoampere level.
  • the output of the bias current generating circuit The output of the bias current generating circuit.
  • N, J, and K in Fig. 4 represent the mirror ratio of the current mirror circuit, where N is the mirror ratio of the current mirror circuit composed of M 11 and M 8 , and J is the mirror ratio of the current mirror circuit composed of M 14 and M 12 , K is the mirror ratio of the current mirror circuit composed of M 11 and M 13 , and M 9 and M 10 constitute a self-source cascode transistor SCM circuit.
  • M 8 to M 14 are main circuits of the nanoampere-level bias current generating circuit
  • M 15 is a bias current output terminal of the nanoampere-level bias current generating circuit.
  • the gate-source voltage V GS of M 12 and M 14 will be different, V GS14 >V GS12 .
  • the source of M 12 produces a voltage that is the difference between V GS14 and V GS12 .
  • M 10 operates in a linear region and can be equivalent to a resistor in electrical characteristics. Further, since the drain-source voltage of M 10 M 12 is biased by the output current thus produced is equal to the ratio of M and M 12 is the source voltage of the equivalent resistance 10.
  • M 10 Since the difference between V GS14 and V GS12 is relatively small, only a few tens of millivolts, and the equivalent resistance of M 10 is the transistor resistance. In actual operation, M 10 is designed as an inverted tube, which can be easily obtained. A large equivalent value allows a bias current output of the nanoampere level to be obtained.
  • the nanoampere level bias current generating circuit mentioned in the embodiment has the characteristics of small output bias current, small static power consumption, and small chip area.
  • the output of the order of nanoamperes bias current generating circuit is connected to the drain of the field effect transistor M 1.
  • the gate of the field effect transistor M 1 is connected to the drain and is connected to the gate of the field effect transistor M 3 .
  • the drain of the field effect transistor and the field effect transistor M 3 is connected to the drain of M 2.
  • the source of the field effect transistor M 1 and the source of the field effect transistor M 3 are both grounded.
  • the voltage biasing module 7 having positive temperature characteristics may be a series-connected cascode transistor SSCM circuit, and the number of stages of the SSCM circuit may be three stages, by the field effect transistors M B1 to M B4 , M shown in FIG. U1 to M U3 , M D1 to M D3 .
  • the number of stages of the SSCM circuit is not limited, and the number of stages of the SSCM circuit can be selected according to different compensation amount requirements and output voltage V O requirements.
  • the specific structure of the voltage biasing module is not limited in this embodiment, and any structural form of the voltage biasing module having positive temperature characteristics can be applied to the present embodiment.
  • the field effect transistors M B1 , M U1 , and M D1 shown in FIG. 3 constitute a first stage circuit of the SSCM circuit
  • M B2 , M U2 , and M D2 constitute a second stage circuit of the SSCM circuit
  • M B3 , M U3 and M D3 form the third stage circuit of the SSCM circuit.
  • the first stage circuit in the SSCM circuit is the SSCM circuit.
  • the source of M B1 receives the input voltage V IN of the linear regulator, the gate is connected to the gate of the field effect transistor M 2 , and the drain is connected to the drain of M U1 .
  • the gate of M U1 is connected to the drain, and the source is connected to the drain of M D1 .
  • the gate of M D1 is connected to the gate of M U1 and the source is grounded.
  • the drain of M D1 is connected to the source of M U1 and serves as the output of the first stage of the SSCM circuit, and the output voltage is V SSCM1 .
  • V SSCM1 V GS_MD1 -V GS_MU1 , V GS_MD1 M D1 to the gate-source voltage, V GS_MU1 M U1 is a gate-source voltage.
  • the current amplification factor of M B1 is k 1 , so that the bias current I 0 generated by the nanoampere-level bias current generating circuit is amplified to k 1 *I 0 after passing through M B1 .
  • the source of M B2 receives the input voltage V IN of the linear regulator, the gate is connected to the gate of the field effect transistor M 2 , and the drain is connected to the drain of M U2 .
  • the gate of M U2 is connected to the drain, and the source is connected to the drain of M D2 .
  • the gate of M D2 is connected to the gate of M U2 , and the source is grounded.
  • the drain of M D2 is connected to the source of M U2 and serves as the output of the second stage of the SSCM circuit.
  • the output voltage is V SSCM2 .
  • V SSCM2 V GS_MD2 -V GS_MU2 , V GS_MD2 the gate-source voltage of M D2, V GS_MU2 M U2 for the gate-source voltage.
  • the current amplification factor of M B2 is k 2 such that the bias current I 0 generated by the nanoampere-level bias current generating circuit is amplified to k 2 *I 0 after passing through M B2 .
  • the third stage circuit in the SSCM circuit is the third stage circuit in the SSCM circuit:
  • the source of M B3 receives the input voltage V IN of the linear regulator, the gate is connected to the gate of the field effect transistor M 2 , and the drain is connected to the drain of M U3 .
  • the gate of M U3 is connected to the drain, and the source is connected to the drain of M D3 .
  • the gate of M D3 is connected to the gate of M U3 and the source is grounded.
  • the drain of M D3 is connected to the source of M U3 and serves as the output of the third stage of the SSCM circuit, and the output voltage is V SSCM3 .
  • V SSCM3 V GS_MD3 -V GS_MU3 , V GS_MD3 M D3 to the gate-source voltage, V GS_MU3 for the gate-source voltage of M U3.
  • the current amplification factor of M B3 is k 3 , so that the bias current I 0 generated by the nanoampere-level bias current generating circuit is amplified to k 3 *I 0 after passing through M B3 .
  • the flip voltage follower 8 includes a folded cascode amplifier and a power adjustment transistor M P .
  • the folded cascode amplifier is composed of a field effect transistor M 4 to a field effect transistor M 7 .
  • the source of the field effect transistor M 4 is the first electrode of the input ends of the folded cascode amplifier, and the emitter of the power regulator P M together form a first inverting input terminal of the voltage follower 8.
  • the gate of the field effect transistor M 5 is the folded a second input of the common source of common gate amplifier, a second inverting input terminal of the voltage follower 8.
  • the drain of the field effect transistor M 4 is the first output of the folded cascode amplifier and is connected to the gate of the power transfer transistor M P .
  • M is a field effect transistor source electrode 7 is the folded a second common source output terminal of the common gate amplifier, forming inverted output terminal of the voltage follower 8, and is connected to the drain of the power adjustment tube P M.
  • the order of nanoamperes bias current generating circuit generates a bias current I 0, I 0 after converting the current mirror circuit, an output circuit to SSCM.
  • the SSCM circuit output voltages V B and V PTAT act on the gates of the field effect transistor M 5 and the field effect transistor M 7 , respectively.
  • V GS7 V TH + V OVM7
  • V TH a field effect transistor M is the threshold voltage of 7, V OVM7 field effect transistors M overdrive voltage 7, the field effect transistor M 7 operating in the subthreshold region, V OVM7 Can be ignored.
  • the source of the field effect transistor M 7 samples the output voltage V O of the linear regulator, and then performs error amplification by the folded cascode amplifier composed of the field effect transistor M 4 to the field effect transistor M 7 , and the result of the error amplification At the node Y output, it acts on the gate of the power adjustment transistor M P .
  • the field effect transistor M 4 and the field effect transistor M 6 provide bias currents I B1 and I B2 for the folded cascode amplifier, and I B2 >I B1 .
  • V B is biased at the gate of field effect transistor M 5 such that node X has a suitable bias voltage to ensure that both field effect transistor M 6 and field effect transistor M 7 operate at a suitable operating voltage.
  • the inversion voltage follower 8 further includes an output capacitor C 0 .
  • the output capacitor C 0 is connected between the output of the flip voltage follower 8 and the ground.
  • the output capacitor C 0 is used to ensure the stability of the linear regulator.
  • V O V PTAT +V GS7 . Since the flip voltage follower 8 has a negative temperature characteristic, it is necessary to properly design the SSCM circuit so that the SSCM circuit has a suitable positive temperature characteristic, so that the output voltage V O of the linear regulator has a good temperature over the entire temperature range. Precision. That is, it is necessary to have a suitable positive temperature characteristic of V PTAT in the SSCM circuit so that V PTAT can compensate for the negative temperature characteristic of the inverted voltage follower 8.
  • n is the subthreshold slope coefficient
  • V T is the thermal voltage
  • I S0 is the process related parameter
  • S MDi and S MUi represent the channel width to length ratio of M Di and M Ui , respectively.
  • T is the absolute temperature
  • T 0 is the reference absolute temperature (eg room temperature)
  • ⁇ VT is the temperature coefficient of the threshold voltage of the field effect transistor.
  • the output voltage V O can be obtained by combining equations (2) and (3):
  • k b is the Boltzmann constant and q is the potential charge constant.
  • the output voltage of the linear regulator is compensated by the inversion voltage follower 8 so that the output voltage of the linear regulator is relatively stable.
  • the voltage biasing module 7 has a positive temperature characteristic and can compensate each other with the inversion voltage follower 8, counteracting the negative temperature characteristic in the inverting voltage follower 8, so that the output voltage of the linear regulator has good temperature characteristics.
  • the linear regulator eliminates the need to specifically set the reference voltage module, which saves current consumption.
  • the linear regulator has the characteristics of low static power consumption and small chip footprint.
  • a second embodiment of the invention relates to a linear regulator, as shown in FIG.
  • the second embodiment is substantially the same as the first embodiment, and the main difference is that in the first embodiment of the present invention, the auxiliary output circuit includes a current mirror circuit and a field effect transistor.
  • the auxiliary output circuit includes only the field effect transistor M 16 .
  • the drain and gate of field effect transistor M 16 form the input and output of the auxiliary output circuit, respectively.
  • the drain of the field effect transistor M 16 is connected to the input of the nanoampere-level bias current generating circuit, and the gate is connected to the gate of the field effect transistor M 6 of the folded cascode amplifier.
  • the source of M 16 is grounded, and the gate is also connected to the drain of M 16 .
  • the field effect transistor M 16 does not need to be connected to the SSCM circuit, and the field effect transistor M 16 functions to receive the bias current and supply the bias voltage follower 8 with a bias current.

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Abstract

一种线性调整器，包括：电流偏置模块（6）、具有正温度特性的电压偏置模块（7）以及翻转电压跟随器（8）；电流偏置模块（6）的输入端接收线性调整器的输入电压，电流偏置模块（6）的输出端输出偏置电流；电压偏置模块（7）的第一输入端与第二输入端分别接收输入电压与偏置电流，电压偏置模块（7）的输出端输出偏置电压；翻转电压跟随器（8）的第一输入端与第二输入端分别接收输入电压与偏置电压，翻转电压跟随器（8）的输出端输出线性调整器的输出电压。该线性调整器利用具有正温度特性的电压偏置模块（7）补偿翻转电压跟随器（8）的负温度特性，无需基准电压模块的情况下，输出电压也具有良好的温度特性，静态功耗较低且芯片占用面积较小。

Description

一种线性调整器 技术领域
本发明涉及电子技术领域，特别涉及一种线性调整器。
背景技术
线性调整器也称串联调整器，通过它可以将不稳定的输入电压转换为可调节的直流输出电压，以便于作为其它系统的供电电源。由于线性调整器具有结构简单、静态功耗小、输出电压纹波小等特点，因此线性调整器常被用于移动消费类电子设备芯片的片内电源管理。
图1给出了现有技术中的线性调整器的结构示意图：线性调整器包括：偏置模块1、基准电压模块2、误差放大器3、功率调整管4以及采样电阻网络5。
线性调整器的输入电压VIN分别输入至偏置模块1、基准电压模块2以及功率调整管4中，偏置模块1为基准电压模块2以及误差放大器3提供正常工作所需的电流偏置和电压偏置，基准电压模块2产生一个低温漂的参考电压VREF给误差放大器3，误差放大器3将采样电阻网络5对输出电压VO采样得到的反馈电压VFB与VREF进行误差放大，以便于根据误差放大的结果，调整功率调整管4的栅极电压，使得输出电压VO稳定输出。
随着物联网技术的快速发展，人们对移动消费类电子设备的要求越来越高。当电子设备的系统处于睡眠待机状态时，便要求电子设备芯片的片内电源管理的功耗尽可能的低，以延长设备的使用时间，使得电子设备具有较长的待机时间。但是，现有技术中的线性调整器很难满足电子设备在待机时，静态电流为几百纳安培甚至几十纳安培的要求。另外，现有技术中的线性调 整器中的采样电阻网络5会占用较大的芯片面积，不利于电子设备的小型化的发展。
发明内容
本发明实施方式的目的之一在于提供一种线性调整器，使得线性调整器静态功耗较低，且芯片占用面积较小，并通过具有正温度特性的电压偏置模块来补偿翻转电压跟随器的负温度特性，使得线性调整器在无需基准电压模块的情况下，线性调整器的输出电压也具有良好的温度特性。
为解决上述技术问题，本发明的实施方式提供了一种线性调整器，包括：电流偏置模块、具有正温度特性的电压偏置模块以及翻转电压跟随器；
电流偏置模块的输入端接收线性调整器的输入电压，电流偏置模块的输出端输出偏置电流；
电压偏置模块的第一输入端与第二输入端分别接收输入电压与偏置电流，电压偏置模块的输出端输出偏置电压；
翻转电压跟随器的第一输入端与第二输入端分别接收输入电压与偏置电压，翻转电压跟随器的输出端输出线性调整器的输出电压。
本发明实施方式相对于现有技术而言，线性调整器的输入电压输入至电流偏置模块的输入端、电压偏置模块的第一输入端以及翻转电压跟随器的第一输入端中，电流偏置模块产生偏置电流，且电压偏置模块的第二输入端接收该偏置电流，电压偏置模块产生偏置电压，且翻转电压跟随器的第二输入端接收该偏置电压，线性调整器的输出电压由翻转电压跟随器的输出端输出。利用翻转电压跟随器对线性调整器的输出电压进行跟随补偿，以便于线性调整器的输出电压较为稳定。并且，电压偏置模块具有正温度特性，能够与翻转电压跟随器相互补偿，抵消翻转电压跟随器的负温度特性，使得线性调整 器的输出电压具有良好的温度特性。通过这种方式，使得线性调整器具有静态功耗较低，芯片占用面积较小的特点，并且线性调整器无需专门的设置基准电压模块，也能实现线性调整器的输出电压具有良好的温度特性。
另外，电流偏置模块包括偏置电流产生电路与辅助输出电路。偏置电流产生电路的输入端连接于线性调整器的输入电压；偏置电流产生电路的输出端连接于辅助输出电路的输入端；辅助输出电路的输出端连接于电压偏置模块的输入端；偏置电流产生电路的输入端与辅助输出电路的输出端分别形成电流偏置模块的输入端与输出端。利用偏置电流产生电路产生所需的偏置电流(一般而言，所需的偏置电流为纳安培量级偏置电流)，并利用辅助输出电路将偏置电流产生电路的偏置电流输出至电压偏置模块。
另外，辅助输出电路包括电流镜电路与场效应晶体管；电流镜电路的输入端连接于偏置电流产生电路的输出端，电流镜电路的输出端连接于场效应晶体管的漏极；场效应晶体管的源极与栅极分别连接于电流偏置模块的输入端与输出端。本实施例提供了辅助输出电路的一种具体实现方式，即，利用电流镜电路将偏置电流产生电路中的偏置电流复制给场效应晶体管的漏极，以便于场效应晶体管将偏置电流输入至电压偏置模块中。并且，采用具有电流镜电路的辅助输出电路，能够使得偏置电流产生电路在电路设计方面，具有较大的灵活性。
另外，辅助输出电路包括场效应晶体管；场效应晶体管的漏极和栅极分别形成辅助输出电路的输入端和输出端。本实施例提供了辅助输出电路的一种具体实现方式，增加了本发明的可行性。
另外，电压偏置模块包括串联自共源共栅晶体管SSCM(SSCM，Series Self Cascode MOSFET)电路，提供了一种电压偏置模块的具体实现形式，增加了本发明的可行性。并且，在本发明中，SSCM电路能够工作在亚阈值区，从而使线性调整器的静态功耗很小。
另外，翻转电压跟随器包括折叠式共源共栅放大器与功率调整管；折叠式共源共栅放大器的第一输入端与功率调整管的发射极形成翻转电压跟随器的第一输入端；折叠式共源共栅放大器的第二输入端形成翻转电压跟随器的第二输入端；折叠式共源共栅放大器的第一输出端连接于功率调整管的栅极；折叠式共源共栅放大器的第二输出端形成翻转电压跟随器的输出端，且连接于功率调整管的漏极。利用折叠式共源共栅放大器对线性调整器的输出电压进行采样，误差放大，误差方法的结果输出并作用在功率调整管的栅极，以调整功率调整管的栅电压使得线性调整器的输出电压稳定输出。
另外，翻转电压跟随器还包括输出电容；输出电容连接在翻转电压跟随器的输出端与接地端之间。利用输出电容保证线性调整器的稳定性。
附图说明
图1是现有技术中线性调整器的结构示意图；
图2是根据本发明第一实施方式中线性调整器的结构示意图；
图3是根据本发明第一实施方式中线性调整器的电路示意图；
图4是根据本发明第一实施方式中纳安培量级偏置电流产生电路的电路示意图；
图5是根据本发明第二实施方式中线性调整器的电路示意图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明的各实施方式进行详细的阐述。然而，本领域的普通技术人员可以理解，在本发明各实施方式中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施方式的种种变化和修改， 也可以实现本申请所要求保护的技术方案。
本发明的第一实施方式涉及一种线性调整器，包括：电流偏置模块、具有正温度特性的电压偏置模块以及翻转电压跟随器，如图2所示。本实施方式中的线性调整器可以应用于可充电电池的移动终端，如手机、电脑、平板电脑、穿戴设备等。
电流偏置模块6的输入端接收线性调整器的输入电压VIN，电流偏置模块6的输出端输出偏置电流。电压偏置模块7的第一输入端与第二输入端分别接收输入电压VIN与偏置电流，电压偏置模块7的输出端输出偏置电压。翻转电压跟随器8的第一输入端与第二输入端分别接收输入电压VIN与偏置电压，翻转电压跟随器8的输出端输出线性调整器的输出电压VO。
具体的说，电流偏置模块6产生偏置电流，并将偏置电流输出给电压偏置模块7，由电压偏置模块7产生偏置电压。利用翻转电压跟随器8对线性调整器的输出电压VO进行跟随补偿，以便于线性调整器的输出电压VO较为稳定。并且，电压偏置模块7具有正温度特性，能够与翻转电压跟随器8相互补偿，抵消翻转电压跟随器8的负温度特性，使得线性调整器的输出电压VO具有良好的温度特性。
本实施方式中，电流偏置模块6包括偏置电流产生电路与辅助输出电路。偏置电流产生电路的输入端连接于线性调整器的输入电压VIN，偏置电流产生电路的输出端连接于辅助输出电路的输入端。辅助输出电路的输出端连接于电压偏置模块7的输入端。偏置电流产生电路的输入端与辅助输出电路的输出端分别形成电流偏置模块的输入端与输出端。利用偏置电流产生电路产生所需的偏置电流(一般而言，所需的偏置电流为纳安培量级偏置电流)，并利用辅助输出电路将偏置电流产生电路的偏置电流输出至电压偏置模块。
其中，辅助输出电路包括电流镜电路与场效应晶体管。电流镜电路的输入端连接于偏置电流产生电路的输出端，电流镜电路的输出端连接于场效应 晶体管的漏极。场效应晶体管的源极与栅极分别连接于电流偏置模块的输入端与输出端。利用电流镜电路将偏置电流产生电路中的偏置电流复制给场效应晶体管的漏极，以便于场效应晶体管将偏置电流输入至电压偏置模块中。并且，采用具有电流镜电路的辅助输出电路，能够使得偏置电流产生电路在选型方面，具有较大的灵活性。
下面以图3所示的电路对线性调整器的工作原理进行说明：
电流偏置模块6包括偏置电流产生电路与辅助输出电路。偏置电流产生电路为可以采用如图3所示的纳安培量级偏置电流产生电路。辅助输出电路包括电流镜电路与场效应晶体管M2。电流镜电路包括场效应晶体管M1以及M3，场效应晶体管M1的漏极作为电流镜电路的输入端，场效应晶体管M3的漏极作为电流镜电路的输出端。其中，纳安培量级偏置电流产生电路的具体电路的一种实施例可参看图4。如图4所示，场效应晶体管M8、M11、M13以及M15的源极作为纳安培量级偏置电流产生电路的输入端，场效应晶体管M15的漏极作为纳安培量级偏置电流产生电路的输出端。
图4中的N、J、K表示电流镜电路的镜像比率，其中N是M11与M8组成的电流镜电路的镜像比率，J是M14与M12组成的电流镜电路的镜像比率，K是M11与M13组成的电流镜电路的镜像比率，M9与M10构成自共源共栅晶体管SCM电路。
其中，M8至M14是纳安培量级偏置电流产生电路的主体电路，M15是纳安培量级偏置电流产生电路的偏置电流输出端。
由于M14与M12组成的电流镜电路工作在亚阈值区，且镜像比率大于1(J>1)，因此M12、M14的栅-源电压VGS将不同，VGS14>VGS12。M12的源极产生一个电压，该电压为VGS14与VGS12的差值。
M9与M10构成的自共源共栅晶体管SCM电路中，M10工作在线性区，电气特性上可以等效为一个电阻。并且，由于M10的漏极由上述M12的源极 电压偏置，因而产生的输出电流等于M12的源极电压与M10的等效电阻的比值。
由于VGS14与VGS12的差值比较小，仅有几十毫伏，且M10的等效电阻是晶体管电阻，在实际操作时，将M10设计成倒比管，就可以很容易的得到很大的等效阻值，从而能够得到纳安培量级的偏置电流输出。
综上所述，本实施方式所提及的纳安培量级偏置电流产生电路具有输出偏置电流小，静态功耗小，占用芯片面积小的特点。
纳安培量级偏置电流产生电路的输入端、场效应晶体管的源极M2作为电流偏置模块6的输入端，接收线性调整器的输入电压VIN，场效应晶体管M2的栅极作为电流偏置模块6的输出端，与电压偏置模块7的输入端连接。其中，纳安培量级偏置电流产生电路的输出端与场效应晶体管M1的漏极连接。场效应晶体管M1的栅极与漏极连接，且与场效应晶体管M3的栅极连接。场效应晶体管M3的漏极与场效应晶体管M2的漏极连接。场效应晶体管M1的源极与场效应晶体管M3的源极均接地。
具有正温度特性的电压偏置模块7可为串联自共源共栅晶体管SSCM电路，且SSCM电路的级数可为三级，由图3中所示的场效应晶体管MB1至MB4、MU1至MU3、MD1至MD3组成。本实施方式中，对SSCM电路的级数不作任何限制，SSCM电路的级数可以根据不同的补偿量需求及输出电压VO的需求，进行选择。另外需要强调的是，本实施例对电压偏置模块的具体结构形式也不作任何限制，只要是具有正温度特性的电压偏置模块的任何结构形式，均可以应用于本实施方式中。
具体的说，图3中所示的场效应晶体管MB1、MU1以及MD1组成SSCM电路的第一级电路，MB2、MU2以及MD2组成SSCM电路的第二级电路，MB3、MU3以及MD3组成SSCM电路的第三级电路。以下对SSCM电路中各级电路进行详细说明：
SSCM电路中的第一级电路：
MB1的源极接收线性调整器的输入电压VIN，栅极与场效应晶体管M2的栅极连接，漏极与MU1的漏极连接。MU1的栅极与漏极连接，源极与MD1的漏极连接。MD1的栅极与MU1的栅极连接，源极接地。其中，MD1的漏极与MU1的源极相连，并作为SSCM电路第一级的输出端，输出电压为VSSCM1。
其中，VSSCM1＝VGS_MD1-VGS_MU1，VGS_MD1为MD1的栅源电压，VGS_MU1为MU1的栅源电压。MB1的电流放大系数为k1，从而使得纳安培量级偏置电流产生电路产生的偏置电流I0在经过MB1后，放大为k1*I0。
SSCM电路中的第二级电路：
MB2的源极接收线性调整器的输入电压VIN，栅极与场效应晶体管M2的栅极连接，漏极与MU2的漏极连接。MU2的栅极与漏极连接，源极与MD2的漏极连接。MD2的栅极与MU2的栅极连接，源极接地。其中，MD2的漏极与MU2的源极相连，并作为SSCM电路第二级的输出端，输出电压为VSSCM2。
其中，VSSCM2＝VGS_MD2-VGS_MU2，VGS_MD2为MD2的栅源电压，VGS_MU2为MU2的栅源电压。MB2的电流放大系数为k2，从而使得纳安培量级偏置电流产生电路产生的偏置电流I0在经过MB2后，放大为k2*I0。
SSCM电路中的第三级电路：
MB3的源极接收线性调整器的输入电压VIN，栅极与场效应晶体管M2的栅极连接，漏极与MU3的漏极连接。MU3的栅极与漏极连接，源极与MD3的漏极连接。MD3的栅极与MU3的栅极连接，源极接地。其中，MD3的漏极与MU3的源极相连，并作为SSCM电路第三级的输出端，输出电压为VSSCM3。
其中，VSSCM3＝VGS_MD3-VGS_MU3，VGS_MD3为MD3的栅源电压，VGS_MU3为MU3的栅源电压。MB3的电流放大系数为k3，从而使得纳安培量级偏置电流产生电路产生的偏置电流I0在经过MB3后，放大为k3*I0。
翻转电压跟随器8包括折叠式共源共栅放大器与功率调整管MP。其中，折叠式共源共栅放大器由场效应晶体管M4至场效应晶体管M7组成。其中，场效应晶体管M4的源极即为折叠式共源共栅放大器的第一输入端，与功率调整管MP的发射极一起形成翻转电压跟随器8的第一输入端。场效应晶体管M5的栅极即为折叠式共源共栅放大器的第二输入端，形成翻转电压跟随器8的第二输入端。场效应晶体管M4的漏极即为折叠式共源共栅放大器的第一输出端，与功率调整管MP的栅极连接。场效应晶体管M7的源极即为折叠式共源共栅放大器的第二输出端，形成翻转电压跟随器8的输出端，且连接于功率调整管MP的漏极。
具体的说：纳安培量级偏置电流产生电路产生偏置电流I0，I0经过电流镜电路转换后，输出给SSCM电路。SSCM电路输出电压VB及VPTAT分别作用在场效应晶体管M5和场效应晶体管M7的栅极。当线性调整器的输入电压VIN上电，电路工作稳定时，线性调整器的输出电压VO＝VPTAT+VGS7。其中，VGS7＝VTH+VOVM7，VTH为场效应晶体管M7的阈值电压，VOVM7是场效应晶体管M7的过驱动电压，当场效应晶体管M7工作在亚阈值区时，VOVM7可以忽略不计。
场效应晶体管M7的源极对线性调整器的输出电压VO进行采样，然后经场效应晶体管M4至场效应晶体管M7组成的折叠式共源共栅放大器做误差放大，误差放大的结果在节点Y输出，作用在功率调整管MP的栅极。其中，场效应晶体管M4和场效应晶体管M6为折叠式共源共栅放大器提供偏置电流IB1和IB2，且IB2>IB1。VB偏置在场效应晶体管M5的栅极使得节点X有合适的偏置电压，以保证场效应晶体管M6和场效应晶体管M7均工作在合适的工作电压下。
由于线性调整器的输入电压VIN不变，因此如果线性调整器的输出电压VO增大，则折叠式共源共栅放大器上的电压VO-VIN也会增大；这样，Y节 点上的电压会变大，使得功率调整管MP关闭，线性调整器的输出电压VO减小。反之，如果如果线性调整器的输出电压VO减小，折叠式共源共栅放大器上的电压VO-VIN也会减小，则Y节点上的电压也会减小，此时功率调整管MP会增大供给电流，以使得线性调整器的输出电压VO增大。
值得一提的是，本实施方式中，翻转电压跟随器8还包括输出电容C0。输出电容C0连接在翻转电压跟随器8的输出端与接地端之间。利用输出电容C0来保证线性调整器的稳定性。
以下对电压偏置模块7与翻转电压跟随器8相互补偿的原理进行说明：
从上文可知：VO＝VPTAT+VGS7。由于翻转电压跟随器8具有负温度特性，因此，需合理的设计SSCM电路，以使得SSCM电路有合适的正温度特性，从而使得线性调整器的输出电压VO在全温度范围内都有良好的精度。即，需要使得SSCM电路中的VPTAT有合适的正温度特性，以便于VPTAT可以补偿翻转电压跟随器8的负温度特性。
本实施方式中，SSCM电路的级数为三级，SSCM电路中第i级的输出VSSCMi＝VGS_MDi-VGS_MUi。由于SSCM电路工作在亚阈值区，根据亚阈值区的电流-电压公式得到SSCM电路每一级的输出为：
公式(1)：
Figure PCTCN2016095428-appb-000001
其中，n是亚阈值斜率系数、VT是热电压、IS0是工艺相关的参数、SMDi和SMUi分别表示MDi和MUi的沟道宽长比。
将上述公式(1)与图3相结合，可得：
公式(2)：
Figure PCTCN2016095428-appb-000002
已知，场效应晶体管的阈值电压可以表示成：
公式(3)：
|VTH(T)|＝|VTH(T0)|-αVT(T-T0)
其中，T是绝对温度、T0是参考绝对温度(如室温)、αVT是场效应晶体管的阈值电压的温度系数。
假设，场效应晶体管M7也工作在亚阈值区，则结合式公式(2)、公式(3)可得到输出电压VO为：
公式(4)：
Figure PCTCN2016095428-appb-000003
不难看出，当SSCM电路的级数为N时，公式(4)可以拓展为：
公式(5)：
Figure PCTCN2016095428-appb-000004
对输出电压VO按照温度进行求导，获得：
公式(6)：
Figure PCTCN2016095428-appb-000005
以及公式(7)：
Figure PCTCN2016095428-appb-000006
其中，kb为玻尔兹曼常数、q为电位电荷常数。
由公式(6)、(7)可知，合理的设计SSCM的级数、电流放大系数ki(i＝1,2,…,N，N+1)、MUi及MDi(i＝1,2,…,N)的尺寸以及场效应晶体管M7的尺寸使得
Figure PCTCN2016095428-appb-000007
时，则输出电压VO表现为零温度特性。
不难看出，本实施方式中，利用翻转电压跟随器8对线性调整器的输出电压进行跟随补偿，以便于线性调整器的输出电压较为稳定。并且，电压偏置模块7具有正温度特性，能够与翻转电压跟随器8相互补偿，抵消翻转电压跟随器8中的负温度特性，使得线性调整器的输出电压具有良好的温度特性。这样，从而使得线性调整器无需专门的设置基准电压模块，节省了电流消耗，线性调整器具有静态功耗较低，芯片占用面积较小的特点。
本发明的第二实施方式涉及一种线性调整器，如图5所示。第二实施方式与第一实施方式大致相同，主要区别之处在于：在本发明第一实施方式中，辅助输出电路包括电流镜电路与场效应晶体管。而在本发明第二实施方式中，辅助输出电路只包括场效应晶体管M16。
具体的说，场效应晶体管M16的漏极和栅极分别形成辅助输出电路的输入端和输出端。场效应晶体管M16的漏极与纳安培量级偏置电流产生电路的输入端连接，栅极与折叠式共源共栅放大器的场效应晶体管M6的栅极连接。其中，M16的源极接地，栅极还连接M16的漏极。
本实施方式中，场效应晶体管M16不需要与SSCM电路连接，场效应晶体管M16作用是接收偏置电流，给翻转电压跟随器8提供偏置电流。
本领域的普通技术人员可以理解，上述各实施方式是实现本发明的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本发明的精神和范围。

Claims (10)

  1. 一种线性调整器，其特征在于，包括：电流偏置模块、具有正温度特性的电压偏置模块以及翻转电压跟随器；
    所述电流偏置模块的输入端接收所述线性调整器的输入电压，所述电流偏置模块的输出端输出偏置电流；
    所述电压偏置模块的第一输入端与第二输入端分别接收所述输入电压与所述偏置电流，所述电压偏置模块的输出端输出偏置电压；
    所述翻转电压跟随器的第一输入端与第二输入端分别接收所述输入电压与所述偏置电压，所述翻转电压跟随器的输出端输出所述线性调整器的输出电压。
  2. 根据权利要求1所述的线性调整器，其特征在于，所述电流偏置模块包括偏置电流产生电路与辅助输出电路；
    所述偏置电流产生电路的输入端连接于所述线性调整器的输入电压；
    所述偏置电流产生电路的输出端连接于所述辅助输出电路的输入端；
    所述辅助输出电路的输出端连接于所述电压偏置模块的输入端；
    所述偏置电流产生电路的输入端与所述辅助输出电路的输出端分别形成所述电流偏置模块的输入端与输出端。
  3. 根据权利要求2所述的线性调整器，其特征在于，所述辅助输出电路包括电流镜电路与场效应晶体管；
    所述电流镜电路的输入端连接于所述偏置电流产生电路的输出端，所述电流镜电路的输出端连接于所述场效应晶体管的漏极；
    所述场效应晶体管的源极与栅极分别连接于所述电流偏置模块的输入端与输出端。
  4. 根据权利要求2所述的线性调整器，其特征在于，所述辅助输出电路包括场效应晶体管；
    所述场效应晶体管的漏极和栅极分别形成所述辅助输出电路的输入端和输出端。
  5. 根据权利要求2所述的线性调整器，其特征在于，所述偏置电流产生电路包括纳安培量级偏置电流产生电路。
  6. 根据权利要求1所述的线性调整器，其特征在于，所述电压偏置模块包括串联自共源共栅晶体管SSCM电路。
  7. 根据权利要求6所述的线性调整器，其特征在于，所述SSCM电路的级数为三级。
  8. 根据权利要求1所述的线性调整器，其特征在于，所述翻转电压跟随器包括折叠式共源共栅放大器与功率调整管；
    所述折叠式共源共栅放大器的第一输入端与所述功率调整管的发射极形成所述翻转电压跟随器的第一输入端；
    所述折叠式共源共栅放大器的第二输入端形成所述翻转电压跟随器的第二输入端；
    所述折叠式共源共栅放大器的第一输出端连接于所述功率调整管的栅极；
    所述折叠式共源共栅放大器的第二输出端形成所述翻转电压跟随器的输出端，且连接于所述功率调整管的漏极。
  9. 根据权利要求8所述的线性调整器，其特征在于，所述功率调整管包括场效应晶体管。
  10. 根据权利要求8所述的线性调整器，其特征在于，所述翻转电压跟随器还包括输出电容；
    所述输出电容连接在所述翻转电压跟随器的输出端与接地端之间。
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