WO2018040866A1 - Vdmos器件及其制造方法 - Google Patents

Vdmos器件及其制造方法 Download PDF

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Publication number
WO2018040866A1
WO2018040866A1 PCT/CN2017/096597 CN2017096597W WO2018040866A1 WO 2018040866 A1 WO2018040866 A1 WO 2018040866A1 CN 2017096597 W CN2017096597 W CN 2017096597W WO 2018040866 A1 WO2018040866 A1 WO 2018040866A1
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layer
region
trench region
trench
insulating layer
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French (fr)
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卞诤
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CSMC Technologies Fab2 Co Ltd
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CSMC Technologies Fab2 Co Ltd
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Priority to JP2019511970A priority Critical patent/JP6797286B2/ja
Priority to EP17845168.8A priority patent/EP3499581B1/en
Priority to US16/329,663 priority patent/US10854743B2/en
Publication of WO2018040866A1 publication Critical patent/WO2018040866A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H10D64/117—Recessed field plates, e.g. trench field plates or buried field plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs

Definitions

  • the present invention relates to a semiconductor fabrication process, and more particularly to a vertical double-diffused metal-oxide-semiconductor field-effect transistor (VDMOS) device and a method of fabricating the same.
  • VDMOS vertical double-diffused metal-oxide-semiconductor field-effect transistor
  • the split gate device structure is a form that is relatively easy to implement based on existing processes.
  • the split gate technology because it uses a double gate design, the double gate needs to be led to different electrodes (source and gate), and the middle deep trench gate is connected by direct hole and source metal. Connected to the source, the shallow trench gate on the side is extracted to the periphery of the active region by adding a polysilicon lithography layer and then punched out.
  • this requires additional polysilicon lithography to separate the two gates, thereby increasing the process cost, causing the shallow trench gate to be drawn higher than the plane of the silicon wafer to form a certain step. It has a certain impact on the implementation of the subsequent process.
  • VDMOS device which can realize separation and extraction of the first and second electrodes of the gate without increasing the lithography level of the polysilicon, and a method of manufacturing the same.
  • a method of manufacturing a VDMOS device comprising:
  • a trench in the semiconductor substrate including a first trench region, a second trench region, a third trench region, and a fourth trench connecting the first trench region and the second trench region a groove region, and a fifth groove region communicating with the second groove region and the third groove region; a width of the second groove region being greater than a width of the first groove region, the first groove The width of the groove region is greater than the width of the third groove region, the fourth groove region, and the fifth groove region;
  • first insulating layer Forming a first insulating layer on the semiconductor substrate, the first insulating layer filling the third trench region and the fifth trench region, and attaching to the first trench region and the second trench a groove region and a sidewall of the fourth groove region;
  • first polysilicon layer Forming a first polysilicon layer on the first insulating layer, the first polysilicon layer filling the first trench region, and attaching the first in the second trench region a sidewall of the insulating layer, and the first polysilicon layer in the first trench region is connected to the first polysilicon layer in the second trench region;
  • a portion of the second polysilicon layer is removed to expose a gate oxide layer on a surface of the semiconductor substrate and a top of the second insulating layer, and a second polysilicon layer is formed to constitute a second electrode.
  • VDMOS device including:
  • a semiconductor substrate provided with a trench, the trench including a first trench region, a second trench region, a third trench region, and the first trench region and the second trench a fourth trench region of the region, and a fifth trench region connecting the second trench region and the third trench region; a width of the second trench region is greater than a width of the first trench region, The width of the first trench region is greater than the width of the third trench region, the fourth trench region, and the fifth trench region;
  • a first electrode of a deep gate formed of a first polysilicon layer, a first insulating layer and a second insulating layer separated by the first electrode, and the first electrode are disposed in the second trench region Top by a second electrode of a shallow gate composed of two polysilicon layers and a gate oxide layer between the first electrode and the second pair of crystalline silicon layers;
  • a bottom portion of the third trench region is provided with a first insulating layer, a second electrode of a shallow gate formed of a second polysilicon layer at the top of the first insulating layer; and a second electrode is wrapped Gate oxide layer
  • a first electrode of a deep gate formed of a first polysilicon layer, a first insulating layer encapsulating the first electrode, and a second polycrystal located at a top of the first electrode are disposed in the fourth trench a second electrode of a shallow gate composed of a silicon layer and a gate oxide layer between the first electrode and the second pair of crystalline silicon layers;
  • a bottom portion in the fifth trench region is provided with a first insulating layer, a second electrode of a shallow gate formed by a second polysilicon layer on top of the first insulating layer; and a second electrode is wrapped Gate oxide layer.
  • the separation of the first and second electrodes of the gate can be realized without increasing the lithography level of the polysilicon.
  • all the polysilicon gates remain in the trench, so the surface of the product is not obvious.
  • the steps of the subsequent lithography and etching processes are less difficult to implement.
  • FIG. 1 is a flow chart of a method of fabricating a VDMOS device in accordance with an embodiment
  • 2A-2I are schematic cross-sectional views of devices respectively obtained by sequentially performing steps of a method according to an embodiment
  • 2J is a schematic view of a section taken from the position D1 in FIG. 2I;
  • 2K is a schematic view of a section taken from the position D2 in FIG. 2I;
  • 2L is a schematic view of a section taken from the position D3 in FIG. 2I;
  • FIG. 3 is a schematic diagram of a VDMOS device layout prepared by a method in accordance with an embodiment.
  • a method for manufacturing a VDMOS device includes:
  • a trench is formed in the semiconductor substrate, the trench including a first trench region, a second trench region, a third trench region, and the first trench region and the second trench region are connected a fourth trench region, and a fifth trench region communicating the second trench region and the third trench region, the width of the second trench region being greater than the width of the first trench region, the first trench region The width is greater than the width of the third trench region, the fourth trench region, and the fifth trench region.
  • a semiconductor substrate 200 is provided.
  • the constituent material of the semiconductor substrate 200 may be undoped single crystal silicon, monocrystalline silicon doped with impurities, silicon-on-insulator (SOI), and silicon on insulator ( SSOI), silicon germanium (S-SiGeOI) on insulator, silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI).
  • the constituent material of the semiconductor substrate 200 is selected from single crystal silicon.
  • An isolation structure is formed in the semiconductor substrate 200, and as an example, the isolation structure is a shallow trench isolation (STI) structure or a local silicon oxide (LOCOS) isolation structure.
  • STI shallow trench isolation
  • LOC local silicon oxide
  • the trench includes a first trench region 201, a second trench region 202, a third trench region 203, and a fourth connecting the first trench region 201 and the second trench region 202.
  • a trench region 216 and a fifth trench region 217 communicating the second trench region 202 and the third trench region 203, the width of the second trench region 202 being much larger than the width of the first trench region 201, the first trench
  • the width of the groove region 201 is larger than the widths of the third groove region 203, the fourth groove region 216, and the fifth groove region 217, and the width of the third groove region 203 is different from the fourth groove region 216 and the fifth groove region.
  • the width of 217 is the same or similar.
  • the process of forming the gate electrode by the first trench region 201, the second trench region 202, and the third trench region 203 is exemplarily shown in the cross-sectional schematic views of FIGS. 2A-2I, respectively, for simplicity, in FIG. 2A. - The fourth trench region 216 and the fifth trench region 217 are not shown in FIG. 2I.
  • a second electrode as a shallow gate is formed in the trench.
  • the width A of the first trench region 201 is greater than the width C of the third trench region 203 to ensure that after the first insulating layer is subsequently formed on the semiconductor substrate 200, the first insulating layer fills only the third trench region 203 and fifth trench region 217.
  • the width B of the second trench region 202 is much larger than the width A of the first trench region 201 to ensure that the first polysilicon layer is only filled after the first polysilicon layer is subsequently formed on the semiconductor substrate 200.
  • the first trench region 201 and the fourth trench region 216 is much larger than the width A of the first trench region 201 to ensure that the first polysilicon layer is only filled after the first polysilicon layer is subsequently formed on the semiconductor substrate 200.
  • the process step of forming the trench includes: forming a mask layer having the trench pattern on the semiconductor substrate 200, and forming the mask layer by a conventional photolithography and etching process, the mask layer It may be a single layer structure or a multilayer structure, a mask layer having a single layer structure is a patterned photoresist layer, and a mask layer having a multilayer structure may include a patterned advanced pattern layer stacked from bottom to top.
  • An anti-reflective coating and a photoresist layer etching the semiconductor substrate 200 with the mask layer as a mask, the trench is formed in the semiconductor substrate 200, and the etching may be conventional anisotropic Dry etching; removing the mask layer, the mask layer may be removed by a conventional ashing process; wet cleaning is performed to remove by-products and impurities generated by the foregoing etching.
  • a first insulating layer is formed on the semiconductor substrate to ensure that the third trench region and the fifth trench region are filled, and the first trench region, the second trench region, and the fourth trench region
  • the sidewalls are formed with a first insulating layer but do not fill the first trench region, the second trench region, and the fourth trench region.
  • a first insulating layer 204 is formed on the semiconductor substrate 200 to ensure that the third trench region 203 and the fifth trench region are filled, and the first trench region 201 and the second trench region 202 are formed.
  • the sidewalls of the fourth trench region are formed with the first insulating layer 204 but not filled with the first trench region 201, the second trench region 202, and the fourth trench region.
  • the method of forming the first insulating layer 204 may employ any prior art familiar to those skilled in the art, such as deposition or oxidative growth processes, preferably chemical vapor deposition (CVD), such as low temperature chemical vapor deposition (LTCVD), low pressure chemical vapor phase. Deposition (LPCVD), Rapid Thermal Chemical Vapor Deposition (RTCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD).
  • the material of the first insulating layer 204 includes an oxide such as silicon dioxide.
  • a first polysilicon layer is formed on the first insulating layer to ensure that the first trench region is filled, the second trench region is not filled, and the first polycrystal in the first trench region
  • the silicon layer is connected to the first polysilicon layer in the second trench region.
  • a first polysilicon layer 205 is formed over the first insulating layer 204 to ensure that the first trench region 201 and the fourth trench region are filled. Since the first insulating layer 204 has filled the third trench region 203 and the fifth trench region, the first polysilicon layer 205 can only enter the first trench region 201, the second trench region 202, and the fourth trench. region.
  • the method of forming the first polysilicon layer 205 can be employed Any prior art familiar to those skilled in the art is preferably a chemical vapor deposition method such as low temperature chemical vapor deposition, low pressure chemical vapor deposition, rapid thermal chemical vapor deposition, plasma enhanced chemical vapor deposition.
  • step 304 a second insulating layer is formed over the first polysilicon layer to ensure that the second trench region is filled.
  • a second insulating layer 206 is formed on the first polysilicon layer 205. Since the first insulating layer 204 has filled the third trench region 203 and the fifth trench region, the first polysilicon layer 205 has filled the first trench region 201 and the fourth trench region, and the second insulating layer 206 Only the second trench region 202 can be accessed.
  • the method of forming the second insulating layer 206 may employ any prior art familiar to those skilled in the art, such as a deposition process, preferably a chemical vapor deposition method such as low temperature chemical vapor deposition, low pressure chemical vapor deposition, rapid thermal chemical vapor deposition, plasma. Body enhanced chemical vapor deposition.
  • the material of the second insulating layer 206 includes an oxide such as TEOS.
  • step 105 a portion of the second insulating layer is removed until the first polysilicon layer is exposed.
  • the excess second insulating layer 206 is removed until the first polysilicon layer 205 is exposed.
  • the excess second insulating layer 206 is removed using an etching process, which may be wet etching.
  • step 106 after removing a portion of the first polysilicon layer, the remaining first polysilicon layer constitutes the first electrode.
  • the excess first polysilicon layer 205 is removed to form a first electrode as a deep gate (bottom gate of the cell separation gate).
  • the excess first polysilicon layer 205 is removed using an etching process, which may be wet etching.
  • a third insulating layer is formed over the semiconductor substrate to ensure that the unfilled portions of the first trench region, the second trench region, and the fourth trench region are filled.
  • a third insulating layer 207 is formed over the semiconductor substrate 200 to ensure that the unfilled portions of the first trench region 201, the second trench region 202, and the fourth trench region are filled.
  • the method of forming the third insulating layer 207 may employ any prior art familiar to those skilled in the art, such as a deposition process, preferably a chemical vapor deposition method such as low temperature chemical vapor deposition, low pressure chemical vapor deposition, rapid thermal chemical vapor deposition, plasma. Body enhanced chemical vapor deposition.
  • the material of the third insulating layer 207 includes an oxide such as TEOS.
  • step 108 a portion of the third insulating layer, the second insulating layer, and the first insulating layer are removed such that the top of the first polysilicon layer is higher than the tops of the first insulating layer and the second insulating layer.
  • the excess third insulating layer 207, the first insulating layer 204, and the second insulating layer are removed.
  • the height difference of the surface of the bottom 200 is determined according to the actual situation of the device structure, and is not specifically limited herein.
  • the excess third insulating layer 207, the first insulating layer 204, and the second insulating layer 206 are removed using an etching process, which may be wet etching.
  • the third insulating layer 207 on the top of the first polysilicon layer 205 is removed while performing wet cleaning to remove etching residues and impurities. After the wet cleaning is performed, the top of the first polysilicon layer 205 is higher than the tops of the first insulating layer 204 and the second insulating layer 206.
  • step 109 a gate oxide layer is formed over the semiconductor substrate.
  • a gate oxide layer 208 is formed to achieve electrical isolation between the first polysilicon layer 205 and the subsequently formed second polysilicon layer 209.
  • the gate oxide layer 208 is formed using a thermal oxidation or chemical oxidation process.
  • a gate oxide layer 208 is located on a surface of the semiconductor substrate 200, a surface of the exposed first polysilicon layer 205, and an exposed sidewall portion of the trench.
  • step 110 a second polysilicon layer is formed over the gate oxide layer, the second polysilicon layer filling the trench.
  • a second polysilicon layer 209 is formed over the semiconductor substrate 200, and the second polysilicon layer 209 fills the unfilled portions of the trenches.
  • the method of forming the second polysilicon layer 209 may employ any prior art familiar to those skilled in the art, preferably chemical vapor deposition, such as low temperature chemical vapor deposition, low pressure chemical vapor deposition, rapid thermal chemical vapor deposition, plasma enhancement. Chemical vapor deposition.
  • step 111 a portion of the second polysilicon layer is removed to expose a gate oxide layer on the surface of the semiconductor substrate and a top portion of the second insulating layer.
  • the excess second polysilicon layer 209 is removed to expose the gate oxide layer 208 on the surface of the semiconductor substrate 200 and the second polysilicon layer 206 in the second trench 202.
  • the excess second polysilicon layer 209 is removed using an etching process, which may be wet etching.
  • the second polysilicon layer 209 formed in the trench constitutes a second electrode as a shallow gate (top extraction gate).
  • the gate oxide layer 208 serves as an electrically insulating layer between the first polysilicon layer 205 and the second polysilicon layer 209.
  • a photolithography process is used in addition to forming the trench, and the photolithography process is not used when the first electrode and the second electrode are formed, and the surface of the semiconductor substrate 200 has no obvious step, and the well region and the metal are not formed subsequently.
  • the lithography and etching processes performed at the time of interconnecting layers have an effect.
  • the manufacturing method of the above VDMOS device it is possible to increase the polysilicon lithography level without The separation of the first and second electrodes of the gate is realized, and at the same time, all the polysilicon gates remain in the trenches, so that there is no obvious step on the surface of the product, and the implementation of the subsequent photolithography and etching processes is reduced.
  • the method of fabricating a VDMOS device further includes forming a well region and a source region in the semiconductor substrate 200 by an ion implantation process.
  • the processes for forming the well region and the source region are well known to those skilled in the art and will not be described again.
  • the method of fabricating a VDMOS device further includes forming an interlayer dielectric layer 210 on the semiconductor substrate 200.
  • the material of the interlayer dielectric layer 210 is preferably a material having a low dielectric constant including, but not limited to, a silicate compound having a k value of 2.5 to 2.9 (Hydrogen Silsesquioxane, abbreviated as HSQ) a methyl silicate compound (Methyl Silsesquioxane, MSQ for short) having a k value of 2.2, a porous silica formed by a chemical vapor deposition method, or the like.
  • HSQ Hydrogen Silsesquioxane
  • MSQ methyl silicate compound
  • the method of forming the interlayer dielectric layer 210 may employ any prior art familiar to those skilled in the art, preferably chemical vapor deposition, such as low temperature chemical vapor deposition, low pressure chemical vapor deposition, rapid thermal chemical vapor deposition, plasma enhanced chemical vapor phase. Deposition and so on.
  • chemical vapor deposition such as low temperature chemical vapor deposition, low pressure chemical vapor deposition, rapid thermal chemical vapor deposition, plasma enhanced chemical vapor phase. Deposition and so on.
  • the method for fabricating a VDMOS device further includes forming a bottom portion of the inter-layer dielectric layer 210 electrically connected to a source region located in the cell region by a photolithography or etching process, and located in the second trench.
  • a mask layer having a pattern of a first contact plug 211, a second contact plug 212, and a third contact plug 213 is formed on the interlayer dielectric layer 210, and the exposed interlayer dielectric is etched by using the mask layer as a mask.
  • the layer 210 is formed in the interlayer dielectric layer 210 to expose a source region located in the cell region, a first polysilicon layer 205 located in the second trench region 202, and a second poly layer located in the third trench region 203.
  • the method of fabricating the VDMOS device further includes forming a first metal layer 214 and a second metal layer 215 that are independent of each other on the interlayer dielectric layer 210.
  • the tops of the first contact plug 211 and the second contact plug 212 are electrically connected to the first metal layer 214, and the top of the third contact plug 213 is electrically connected to the second metal layer 215.
  • the first polysilicon layer 205 and the second trench are located in the first trench region 201.
  • the first polysilicon layer 205 in region 202 is connected.
  • the first polysilicon layer 205 constitutes a first electrode, and the first electrode includes a columnar first polysilicon layer and a second trench left at the bottom in the first trench region 201.
  • a barrel-like first polysilicon layer is left at the bottom in region 202.
  • the second polysilicon layer 209 constitutes a second electrode, and the second electrode includes a columnar second polysilicon layer left in the upper portion of the first trench region 201, in the second trench An annular second polysilicon layer left in the upper portion of the region 202 and a columnar second polysilicon layer remaining in the upper portion in the third trench region 203 are connected.
  • the VDMOS device fabrication method includes not only the above steps, but also other necessary steps before, during or after the above steps, which are included in the scope of the method of the present implementation.
  • the separation of the first and second electrodes of the gate can be realized without increasing the lithography level of the polysilicon, and at the same time, all the polysilicon gates remain.
  • the trench there is no obvious step on the surface of the product, and the implementation of subsequent photolithography and etching processes is reduced.
  • the VDMOS device includes: a semiconductor substrate 200 in which an isolation structure is formed, as an example, an isolation structure It is a shallow trench isolation (STI) structure or a local silicon oxide (LOCOS) isolation structure.
  • an isolation structure is formed, as an example, an isolation structure It is a shallow trench isolation (STI) structure or a local silicon oxide (LOCOS) isolation structure.
  • STI shallow trench isolation
  • LOC local silicon oxide
  • a trench is further disposed in the semiconductor substrate 200, and the trench includes a first trench region, a second trench region, a third trench region, and a fourth trench connecting the first trench region and the second trench region a groove region and a fifth groove region communicating the second groove region and the third groove region, the width of the second groove region is much larger than the width of the first groove region, and the width of the first groove region is greater than the third The width of the trench region, the fourth trench region, and the fifth trench region, the width of the third trench region being the same as or similar to the width of the fourth trench region and the fifth trench region.
  • the first trench region, the second trench region and the fourth trench region are provided with a first electrode as a deep gate, and a second electrode as a shallow gate is disposed in the trench.
  • the width of the first trench region is greater than the width of the third trench region to ensure that the first insulating layer on the semiconductor substrate subsequently fills only the third trench region and the fifth trench region.
  • the width of the second trench region is much larger than the width of the first trench region to ensure that the first polysilicon layer on the semiconductor substrate subsequently fills only the first trench region and the fourth trench region.
  • a VDMOS Formed in the semiconductor substrate 200 defined by the isolation structure to form a VDMOS a first trench gate formed by a polysilicon layer 205 and a second trench gate formed by a second polysilicon layer 209, the first trench gate forming a first electrode as a deep gate, and a second The trench gate constitutes a second electrode as a shallow gate.
  • the sidewalls of the first trench-shaped gates located in the first trench region and the fourth trench region are surrounded by the first insulating layer 204, and the first trench gates located in the second trench region are sandwiched
  • An insulating layer 204 and a second insulating layer 206 are U-shaped, and a top portion of the first trench-shaped gate is formed with a second polysilicon layer 209, a first trench gate and a second polysilicon layer.
  • a gate oxide layer 208 is formed between 209 to achieve electrical isolation.
  • a first insulating layer 204 is formed under the bottom of the second trench-shaped gate.
  • a first electrode of the deep gate formed by the first polysilicon layer 205, a first insulating layer 204 enclosing the first electrode, and a second polycrystal located at the top of the first electrode are disposed in the first trench region.
  • a first electrode of a deep gate formed by the first polysilicon layer 205, a first insulating layer 204 and a second insulating layer 206 separated by the first electrode, and a top portion of the first electrode are disposed in the second trench region
  • a bottom portion in the third trench region is provided with a first insulating layer 204, a second electrode of a shallow gate formed by the second polysilicon layer 209 at the top of the first insulating layer; and a gate oxide layer encasing the second electrode 208.
  • a first electrode of a deep gate formed by the first polysilicon layer 205, a first insulating layer 204 encasing the first electrode, and a second polysilicon layer 209 at the top of the first electrode are disposed in the fourth trench.
  • a bottom portion in the fifth trench region is provided with a first insulating layer 204, a second electrode of a shallow gate formed by the second polysilicon layer 209 at the top of the first insulating layer; and a gate oxide layer encasing the second electrode 208.
  • the first polysilicon layer 205 located within the first trench region 201 is coupled to the first polysilicon layer 205 within the second trench region 202.
  • the first polysilicon layer 205 constitutes a first electrode
  • the first electrode includes a columnar first polysilicon layer left at the bottom in the first trench region 201 and a second trench region 202 A barrel-shaped first polysilicon layer left at the bottom of the inner portion.
  • the second polysilicon layer 209 constitutes a second electrode
  • the second electrode includes a columnar second polysilicon layer left in the upper portion of the first trench region 201, in the second trench region 202.
  • the annular second polysilicon layer left in the upper portion and the columnar second polysilicon layer remaining in the upper portion in the third trench region 203 are connected to each other.
  • the above VDMOS device can realize the separation and extraction of the first and second electrodes of the gate. At the same time, all the polysilicon gates of the VDMOS device remain in the trench, so the surface of the VDMOS device has no obvious step, and the subsequent photolithography and etching process The implementation difficulty has been reduced.
  • the VDMOS device further includes an interlayer dielectric layer 210 on the semiconductor substrate 200.
  • the material of the interlayer dielectric layer 210 is preferably a material having a low dielectric constant, and the material having a low dielectric constant includes, but is not limited to, a silicate compound having a k value of 2.5 to 2.9 (Hydrogen Silsesquioxane, abbreviated as HSQ), A methyl silicate compound (Methyl Silsesquioxane, MSQ for short) having a k value of 2.2, a porous silica formed by a chemical vapor deposition method, or the like.
  • HSQ Hydrogen Silsesquioxane
  • MSQ Metal Silsesquioxane
  • the interlayer dielectric layer 210 is provided with a source region electrically connected to the cell region, a first trench gate in the second trench region, and a second trench in the third trench region.
  • the first contact plug 211, the second contact plug 212, and the third contact plug 213 of the gate are provided with a source region electrically connected to the cell region, a first trench gate in the second trench region, and a second trench in the third trench region.
  • the VDMOS device further includes first metal layers 214 and second metal layers 215 that are independent of each other on the interlayer dielectric layer 210.
  • the tops of the first contact plug 211 and the second contact plug 212 are electrically connected to the first metal layer 214, and the top of the third contact plug 213 is electrically connected to the second metal layer 215.

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Abstract

一种VDMOS器件及其制造方法，制造方法包括：在半导体衬底中形成沟槽，沟槽包括第一沟槽区域、第二沟槽区域、第三沟槽区域、第四沟槽区域、以及第五沟槽区域；在半导体衬底上依次形成第一绝缘层、第一多晶硅层、第二绝缘层；去除部分第二绝缘层，直至露出第一多晶硅层；去除部分第一多晶硅层，留下的第一多晶硅层构成第一电极；在半导体衬底上形成第三绝缘层，去除部分第三绝缘层、第二绝缘层和第一绝缘层，以使第一多晶硅层的顶部高于第一绝缘层和第二绝缘层的顶部；在半导体衬底上依次形成栅氧化物层、第二多晶硅层，并去除部分第二多晶硅层，露出位于半导体衬底表面的栅氧化物层以及第二绝缘层的顶部，留下的第二多晶硅层构成第二电极。

Description

VDMOS器件及其制造方法 技术领域
本发明涉及半导体制造工艺，具体而言涉及一种垂直双扩散金属-氧化物半导体场效应晶体管(Vertical Double-diffused MOS，VDMOS)器件及其制造方法。
背景技术
目前沟槽型VDMOS产品开始引入电荷平衡的技术，分离栅器件结构是基于现有工艺较容易实现的一种形式。对于分离栅技术而言，由于其采用了双栅设计，而双栅需要引出到不同的电极(源极和栅极)，中间的深沟槽栅极采用直接打孔与源极金属连接的方式连接到源极，侧面的浅沟槽栅极则使用增加多晶硅光刻层次的方法引出到有源区的外围再做打孔接出。相比传统的沟槽型VDMOS，这需要增加额外的多晶硅光刻来分离两个栅极，由此增加了工艺成本，造成浅沟槽栅极的引出高于硅片平面，形成一定的台阶，对后续工艺的实施有一定影响。
发明内容
基于此，有必要提供一种无需增加多晶硅光刻层次，就可以实现栅极第一和第二电极的分离引出的VDMOS器件及其制造方法。
一种VDMOS器件的制造方法，包括：
在半导体衬底中形成沟槽，所述沟槽包括第一沟槽区域、第二沟槽区域、第三沟槽区域、连通所述第一沟槽区域和第二沟槽区域的第四沟槽区域、以及连通所述第二沟槽区域和第三沟槽区域的第五沟槽区域；所述第二沟槽区域的宽度大于所述第一沟槽区域的宽度，所述第一沟槽区域的宽度大于所述第三沟槽区域、第四沟槽区域和第五沟槽区域的宽度；
在所述半导体衬底上形成第一绝缘层，所述第一绝缘层填满所述第三沟槽区域和第五沟槽区域，且贴附在所述第一沟槽区域、第二沟槽区域和第四沟槽区域的侧壁上；
在所述第一绝缘层上形成第一多晶硅层，所述第一多晶硅层填满所述第一沟槽区域，贴附在所述第二沟槽区域中的所述第一绝缘层的侧壁上，且所述第一沟槽区域内的第一多晶硅层与所述第二沟槽区域内的第一多晶硅层相连；
在所述第一多晶硅层上形成第二绝缘层，所述第二绝缘层填满所述第二沟槽区域；
去除部分所述第二绝缘层，直至露出所述第一多晶硅层；
去除部分所述第一多晶硅层，留下的第一多晶硅层构成第一电极；
在所述半导体衬底上形成第三绝缘层，所述第三绝缘层填满所述第一沟槽区域、第二沟槽区域和第四沟槽区域；
去除部分所述第三绝缘层、第二绝缘层和第一绝缘层，以使所述第一多晶硅层的顶部高于所述第一绝缘层和所述第二绝缘层的顶部；
在所述半导体衬底上形成栅氧化物层；
在所述栅氧化物层上形成第二多晶硅层，所述第二多晶硅层填满所述沟槽；
去除部分所述第二多晶硅层，露出位于所述半导体衬底表面的栅氧化物层以及所述第二绝缘层的顶部，留下的第二多晶硅层构成第二电极。
此外，还提供一种VDMOS器件，包括：
半导体衬底，所述半导体衬底设有沟槽，所述沟槽包括第一沟槽区域、第二沟槽区域、第三沟槽区域、连通所述第一沟槽区域和第二沟槽区域的第四沟槽区域、以及连通所述第二沟槽区域和第三沟槽区域的第五沟槽区域；所述第二沟槽区域的宽度大于所述第一沟槽区域的宽度，所述第一沟槽区域的宽度大于所述第三沟槽区域、第四沟槽区域和第五沟槽区域的宽度；
所述第一沟槽区域内设有由第一多晶硅层构成的深栅的第一电极、包裹所述第一电极的第一绝缘层、位于所述第一电极顶部的由第二多晶硅层构成的浅栅的第二电极以及位于所述第一电极和所述第二对晶硅层之间的栅氧化物层；
所述第二沟槽区域内设有由第一多晶硅层构成的深栅的第一电极、被所述第一电极隔离的第一绝缘层和第二绝缘层、位于所述第一电极顶部的由第 二多晶硅层构成的浅栅的第二电极以及位于所述第一电极和所述第二对晶硅层之间的栅氧化物层；
所述第三沟槽区域内的底部设有第一绝缘层、位于所述第一绝缘层顶部的由第二多晶硅层构成的浅栅的第二电极；以及包裹所述第二电极的栅氧化物层；
所述第四沟槽内设有由第一多晶硅层构成的深栅的第一电极、包裹所述第一电极的第一绝缘层、位于所述第一电极顶部的由第二多晶硅层构成的浅栅的第二电极以及位于所述第一电极和所述第二对晶硅层之间的栅氧化物层；
所述第五沟槽区域内的底部设有第一绝缘层、位于所述第一绝缘层顶部的由第二多晶硅层构成的浅栅的第二电极；以及包裹所述第二电极的栅氧化物层。
根据上述VDMOS器件的制造方法，无需增加多晶硅光刻层次，就可以实现栅极第一和第二电极的分离引出，同时，所有的多晶硅栅极仍然留在沟槽内，因此产品的表面没有明显的台阶，后续光刻、腐蚀工艺的实施难度有所降低。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1为根据一实施例的VDMOS器件的制造方法的流程图；
图2A-图2I为根据一实施例的方法依次实施的步骤所分别获得的器件的示意性剖面图；
图2J为从图2I中的D1位置获取的截面的示意图；
图2K为从图2I中的D2位置获取的截面的示意图；
图2L为从图2I中的D3位置获取的截面的示意图；
图3为根据一实施例的方法所制备的VDMOS器件版图的示意图。
具体实施方式
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的较佳实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容的理解更加透彻全面。
为了解决现有的分离栅技术所存在的工艺成本提高、增加后续工艺的实施难度等不足之处，如图1所示，在一个实施例中，一种VDMOS器件的制造方法包括：
在步骤101中，在半导体衬底中形成沟槽，所述沟槽包括第一沟槽区域、第二沟槽区域、第三沟槽区域、将第一沟槽区域和第二沟槽区域连通的第四沟槽区域、以及将第二沟槽区域和第三沟槽区域连通的第五沟槽区域，第二沟槽区域的宽度大于第一沟槽区域的宽度，第一沟槽区域的宽度大于第三沟槽区域、第四沟槽区域和第五沟槽区域的宽度。
如图2A所示，提供半导体衬底200，半导体衬底200的构成材料可以采用未掺杂的单晶硅、掺杂有杂质的单晶硅、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。作为示例，在本实施例中，半导体衬底200的构成材料选用单晶硅。在半导体衬底200中形成有隔离结构，作为示例，隔离结构为浅沟槽隔离(STI)结构或者局部氧化硅(LOCOS)隔离结构。
接下来，在半导体衬底200中形成沟槽。如图3所示，所述沟槽包括第一沟槽区域201、第二沟槽区域202、第三沟槽区域203、将第一沟槽区域201和第二沟槽区域202连通的第四沟槽区域216以及将第二沟槽区域202和第三沟槽区域203连通的第五沟槽区域217，第二沟槽区域202的宽度远大于第一沟槽区域201的宽度，第一沟槽区域201的宽度大于第三沟槽区域203、第四沟槽区域216和第五沟槽区域217的宽度，第三沟槽区域203的宽度与第四沟槽区域216、第五沟槽区域217的宽度相同或相近。在图2A-图2I的剖面示意图中仅分别示例性的示出第一沟槽区域201、第二沟槽区域202和第三沟槽区域203形成栅极电极的过程，为了简化，在图2A-图2I中未示出第四沟槽区域216和第五沟槽区域217。
后续在第一沟槽区域201、第二沟槽区域202和第四沟槽区域216内形 成作为深栅的第一电极，在所述沟槽内形成作为浅栅的第二电极。第一沟槽区域201的宽度A大于第三沟槽区域203的宽度C，以确保后续在半导体衬底200上形成第一绝缘层之后，所述第一绝缘层仅填满第三沟槽区域203和第五沟槽区域217。第二沟槽区域202的宽度B远大于第一沟槽区域201的宽度A，以确保后续在半导体衬底200上形成第一多晶硅层之后，所述第一多晶硅层仅填满第一沟槽区域201和第四沟槽区域216。
形成所述沟槽的工艺步骤包括：在半导体衬底200上形成具有所述沟槽图案的掩膜层，可以采用常规的光刻、刻蚀工艺形成所述掩膜层，所述掩膜层可以为单层结构或多层结构，具有单层结构的掩膜层为图案化的光刻胶层，具有多层结构的掩膜层可以包括自下而上层叠的图案化的先进图案化层、抗反射涂层和光刻胶层；以所述掩膜层为掩膜，蚀刻半导体衬底200，在半导体衬底200中形成所述沟槽，所述蚀刻可以是常规的各向异性的干法蚀刻；去除所述掩膜层，可以采用常规的灰化工艺去除所述掩膜层；实施湿法清洗，以去除前述蚀刻所产生的副产物和杂质。
在步骤102中，在半导体衬底上形成第一绝缘层，以确保填满第三沟槽区域和第五沟槽区域，且第一沟槽区域、第二沟槽区域和第四沟槽区域的侧壁形成有第一绝缘层但未填满第一沟槽区域、第二沟槽区域和第四沟槽区域。
如图2B所示，在半导体衬底200上形成第一绝缘层204，以确保填满第三沟槽区域203和第五沟槽区域，且第一沟槽区域201、第二沟槽区域202和第四沟槽区域的侧壁形成有第一绝缘层204但未填满第一沟槽区域201、第二沟槽区域202和第四沟槽区域。形成第一绝缘层204的方法可以采用本领域技术人员所熟习的任何现有技术，例如沉积或者氧化生长工艺，优选化学气相沉积法(CVD)，如低温化学气相沉积(LTCVD)、低压化学气相沉积(LPCVD)、快热化学气相沉积(RTCVD)、等离子体增强化学气相沉积(PECVD)。第一绝缘层204的材料包括氧化物，例如二氧化硅。
在步骤103中，在第一绝缘层上形成第一多晶硅层，以确保填满第一沟槽区域，第二沟槽区域未填满，且第一沟槽区域内的第一多晶硅层与第二沟槽区域内的第一多晶硅层相连。
如图2B所示，在第一绝缘层204上形成第一多晶硅层205，以确保填满第一沟槽区域201和第四沟槽区域。由于第一绝缘层204已填满第三沟槽区域203和第五沟槽区域，第一多晶硅层205只能进入第一沟槽区域201、第二沟槽区域202以及第四沟槽区域。形成第一多晶硅层205的方法可以采用 本领域技术人员所熟习的任何现有技术，优选化学气相沉积法，如低温化学气相沉积、低压化学气相沉积、快热化学气相沉积、等离子体增强化学气相沉积。
在步骤304中，在第一多晶硅层上形成第二绝缘层，以确保填满第二沟槽区域。
如图2B所示，在第一多晶硅层205上形成第二绝缘层206。由于第一绝缘层204已填满第三沟槽区域203和第五沟槽区域，第一多晶硅层205已填满第一沟槽区域201和第四沟槽区域，第二绝缘层206只能进入第二沟槽区域202。形成第二绝缘层206的方法可以采用本领域技术人员所熟习的任何现有技术，例如沉积工艺，优选化学气相沉积法，如低温化学气相沉积、低压化学气相沉积、快热化学气相沉积、等离子体增强化学气相沉积。第二绝缘层206的材料包括氧化物，例如TEOS。
在步骤105中，去除部分第二绝缘层，直至露出第一多晶硅层。
如图2C所示，去除多余的第二绝缘层206，直至露出第一多晶硅层205。作为示例，采用腐蚀工艺去除多余的第二绝缘层206，所述腐蚀工艺可以为湿法腐蚀。
在步骤106中，去除部分第一多晶硅层后，留下的第一多晶硅层构成第一电极。
如图2C所示，去除多余的第一多晶硅层205，以形成作为深栅(元胞分离栅的底部栅极)的第一电极。作为示例，采用腐蚀工艺去除多余的第一多晶硅层205，所述腐蚀工艺可以为湿法腐蚀。
在步骤107中，在半导体衬底上形成第三绝缘层，以确保填满第一沟槽区域、第二沟槽区域和第四沟槽区域的未填充部分。
如图2D所示，在半导体衬底200上形成第三绝缘层207，以确保填满第一沟槽区域201、第二沟槽区域202和第四沟槽区域的未填充部分。形成第三绝缘层207的方法可以采用本领域技术人员所熟习的任何现有技术，例如沉积工艺，优选化学气相沉积法，如低温化学气相沉积、低压化学气相沉积、快热化学气相沉积、等离子体增强化学气相沉积。第三绝缘层207的材料包括氧化物，例如TEOS。
在步骤108中，去除部分第三绝缘层、第二绝缘层和第一绝缘层，以使第一多晶硅层的顶部高于第一绝缘层和第二绝缘层的顶部。
如图2E所示，去除多余的第三绝缘层207、第一绝缘层204和第二绝缘 层206。实施所述去除后，第三绝缘层207、第一绝缘层204和第二绝缘层206的顶部平齐，第三绝缘层207、第一绝缘层204和第二绝缘层206的顶部与半导体衬底200表面的高度差根据器件结构的实际情况加以确定，在此不做具体限定。作为示例，采用腐蚀工艺去除多余的第三绝缘层207、第一绝缘层204和第二绝缘层206，所述腐蚀工艺可以为湿法腐蚀。
如图2F所示，实施湿法清洗，去除蚀刻残留物和杂质的同时，去除位于第一多晶硅层205顶部的第三绝缘层207。实施所述湿法清洗之后，第一多晶硅层205的顶部高于第一绝缘层204和第二绝缘层206的顶部。
在步骤109中，在半导体衬底上形成栅氧化物层。
如图2G所示，形成栅氧化物层208，以实现第一多晶硅层205和后续形成的第二多晶硅层209之间的电气绝缘。作为示例，采用热氧化或者化学氧化工艺形成栅氧化物层208。栅氧化物层208位于半导体衬底200的表面、露出的第一多晶硅层205的表面以及所述沟槽的露出的侧壁部分。
在步骤110中，在栅氧化物层上形成第二多晶硅层，第二多晶硅层填满所述沟槽。
如图2G所示，在半导体衬底200上形成第二多晶硅层209，第二多晶硅层209填满所述沟槽的未填充部分。形成第二多晶硅层209的方法可以采用本领域技术人员所熟习的任何现有技术，优选化学气相沉积法，如低温化学气相沉积、低压化学气相沉积、快热化学气相沉积、等离子体增强化学气相沉积。
在步骤111中，去除部分第二多晶硅层，露出位于半导体衬底表面的栅氧化物层以及第二绝缘层的顶部。
如图2H所示，去除多余的第二多晶硅层209，露出位于半导体衬底200表面的栅氧化物层208和位于第二沟槽202内的第二多晶硅层206。作为示例，采用腐蚀工艺去除多余的第二多晶硅层209，所述腐蚀工艺可以为湿法腐蚀。此时，形成于所述沟槽内的第二多晶硅层209构成作为浅栅(顶部引出栅)的第二电极。此时，栅氧化物层208作为第一多晶硅层205和第二多晶硅层209之间的电气绝缘层。
除了形成所述沟槽时使用一次光刻工艺，形成所述第一电极和第二电极时未使用光刻工艺，半导体衬底200的表面没有明显的台阶，不会对后续形成阱区及金属互连层时实施的光刻、刻蚀工艺造成影响。
根据上述VDMOS器件的制造方法，无需增加多晶硅光刻层次，就可以 实现栅极第一和第二电极的分离引出，同时，所有的多晶硅栅极仍然留在沟槽内，因此产品的表面没有明显的台阶，后续光刻、腐蚀工艺的实施难度有所降低。
为了彻底理解本发明，将在下列的描述中提出详细的结构及/或步骤，以便阐释本发明提出的技术方案。本发明的较佳实施例详细描述如下，然而除了这些详细描述外，本发明还可以具有其他实施方式。
在一个实施例中，VDMOS器件的制造方法还包括通过离子注入工艺在半导体衬底200中形成阱区和源区。形成阱区和源区的工艺为本领域技术人员所熟习，在此不再加以赘述。
在一个实施例中，VDMOS器件的制造方法还包括在半导体衬底200上形成层间介质层210。作为示例，层间介质层210的材料优选具有低介电常数的材料，所述具有低介电常数的材料包括但不限于k值为2.5-2.9的硅酸盐化合物(Hydrogen Silsesquioxane，简称为HSQ)、k值为2.2的甲基硅酸盐化合物(Methyl Silsesquioxane，简称MSQ)、以及化学气相沉积方法形成的多孔性二氧化硅等等。层间介质层210的形成方法可以采用本领域技术人员所熟习的任何现有技术，优选化学气相沉积法，如低温化学气相沉积、低压化学气相沉积、快热化学气相沉积、等离子体增强化学气相沉积等。
如图2I所示，在一个实施例中，VDMOS器件的制造方法还包括通过光刻、刻蚀工艺形成贯穿层间介质层210的底部分别电连接位于元胞区的源区、位于第二沟槽区域202内的第一多晶硅层205和位于第三沟槽区域203内的第二多晶硅层209的第一接触塞211、第二接触塞212和第三接触塞213。作为示例，在层间介质层210上形成具有第一接触塞211、第二接触塞212和第三接触塞213图案的掩膜层，以该掩膜层为掩膜，蚀刻露出的层间介质层210，在层间介质层210中形成露出位于元胞区的源区、位于第二沟槽区域202内的第一多晶硅层205和位于第三沟槽区域203内的第二多晶硅层209顶部的通孔，去除该掩膜层后，在所述通孔中填充金属层，以形成第一接触塞211、第二接触塞212和第三接触塞213。
在一个实施例中，VDMOS器件的制造方法还包括在层间介质层210上形成彼此独立的第一金属层214和第二金属层215。第一接触塞211和第二接触塞212的顶部电连接第一金属层214，第三接触塞213的顶部电连接第二金属层215。
如图2J所示，位于第一沟槽区域201内的第一多晶硅层205与第二沟槽 区域202内的第一多晶硅层205相连接。
如图2K所示，第一多晶硅层205构成第一电极，所述第一电极包括在第一沟槽区域201内的底部留下的柱状第一多晶硅层与在第二沟槽区域202内的底部留下的桶状第一多晶硅层。
如图2L所示，第二多晶硅层209构成第二电极，所述第二电极包括在第一沟槽区域201内的上部留下的柱状第二多晶硅层、在第二沟槽区域202内的上部留下的环状第二多晶硅层与在第三沟槽区域203内的上部留下的柱状第二多晶硅层，且三者相连接。
至此，完成了根据一实施例的方法实施的工艺步骤。可以理解的是，VDMOS器件制作方法不仅包括上述步骤，在上述步骤之前、之中或之后还可包括其他需要的步骤，其都包括在本实施制作方法的范围内。
与现有工艺相比，根据上述实施例提出的VDMOS器件的制造方法，无需增加多晶硅光刻层次，就可以实现栅极第一和第二电极的分离引出，同时，所有的多晶硅栅极仍然留在沟槽内，因此产品的表面没有明显的台阶，后续光刻、腐蚀工艺的实施难度有所降低。
此外，还提供根据一实施例的方法实施的工艺步骤获得的VDMOS器件，如图2I所示，VDMOS器件包括：半导体衬底200，在半导体衬底200中形成有隔离结构，作为示例，隔离结构为浅沟槽隔离(STI)结构或者局部氧化硅(LOCOS)隔离结构。
半导体衬底200内还设有沟槽，述沟槽包括第一沟槽区域、第二沟槽区域、第三沟槽区域、将第一沟槽区域和第二沟槽区域连通的第四沟槽区域以及将第二沟槽区域和第三沟槽区域连通的第五沟槽区域，第二沟槽区域的宽度远大于第一沟槽区域的宽度，第一沟槽区域的宽度大于第三沟槽区域、第四沟槽区域和第五沟槽区域的宽度，第三沟槽区域的宽度与第四沟槽区域、第五沟槽区域的宽度相同或相近。
其中，第一沟槽区域、第二沟槽区域和第四沟槽区域内设有作为深栅的第一电极，在沟槽内设有作为浅栅的第二电极。第一沟槽区域的宽度大于第三沟槽区域的宽度，以确保后续在半导体衬底上的第一绝缘层仅填满第三沟槽区域和第五沟槽区域。第二沟槽区域的宽度远大于第一沟槽区域的宽度，以确保后续在半导体衬底上的第一多晶硅层仅填满第一沟槽区域和第四沟槽区域。
在隔离结构所限定的需要形成VDMOS的半导体衬底200中形成有由第 一多晶硅层205构成的第一沟槽状栅极和由第二多晶硅层209构成的第二沟槽状栅极，第一沟槽状栅极构成作为深栅的第一电极，第二沟槽状栅极构成作为浅栅的第二电极。位于第一沟槽区域和第四沟槽区域内的第一沟槽状栅极的侧壁被第一绝缘层204围绕，位于第二沟槽区域内的第一沟槽状栅极夹在第一绝缘层204和第二绝缘层206之间，呈U形，第一沟槽状栅极的顶部形成有第二多晶硅层209，第一沟槽状栅极和第二多晶硅层209之间形成有栅氧化物层208以实现电气绝缘。第二沟槽状栅极底部的下方形成有第一绝缘层204。
具体地，第一沟槽区域内设有由第一多晶硅层205构成的深栅的第一电极、包裹第一电极的第一绝缘层204、位于第一电极顶部的由第二多晶硅层209构成的浅栅的第二电极以及位于第一电极和第二对晶硅层209之间的栅氧化物层208。
第二沟槽区域内设有由第一多晶硅层205构成的深栅的第一电极、被第一电极隔离的第一绝缘层204和第二绝缘层206、位于第一电极顶部的由第二多晶硅层209构成的浅栅的第二电极以及位于第一电极和第二对晶硅层之间的栅氧化物层208。
第三沟槽区域内的底部设有第一绝缘层204、位于第一绝缘层顶部的由第二多晶硅层209构成的浅栅的第二电极；以及包裹第二电极的栅氧化物层208。
第四沟槽内设有由第一多晶硅层205构成的深栅的第一电极、包裹第一电极的第一绝缘层204、位于第一电极顶部的由第二多晶硅层209构成的浅栅的第二电极以及位于第一电极和第二对晶硅层209之间的栅氧化物层208。
第五沟槽区域内的底部设有第一绝缘层204、位于第一绝缘层顶部的由第二多晶硅层209构成的浅栅的第二电极；以及包裹第二电极的栅氧化物层208。
在一个实施例中，位于第一沟槽区域201内的第一多晶硅层205与第二沟槽区域202内的第一多晶硅层205相连接。
在一个实施例中，第一多晶硅层205构成第一电极，第一电极包括在第一沟槽区域201内的底部留下的柱状第一多晶硅层与在第二沟槽区域202内的底部留下的桶状第一多晶硅层。
在一个实施例中，第二多晶硅层209构成第二电极，第二电极包括在第一沟槽区域201内的上部留下的柱状第二多晶硅层、在第二沟槽区域202内 的上部留下的环状第二多晶硅层与在第三沟槽区域203内的上部留下的柱状第二多晶硅层，且三者相连接。
上述VDMOS器件可以实现栅极第一和第二电极的分离引出，同时，VDMOS器件所有的多晶硅栅极仍然留在沟槽内，因此VDMOS器件的表面没有明显的台阶，后续光刻、腐蚀工艺的实施难度有所降低。
在一个实施例中，VDMOS器件还包括位于半导体衬底200上的层间介质层210。作为示例，层间介质层210的材料优选具有低介电常数的材料，具有低介电常数的材料包括但不限于k值为2.5-2.9的硅酸盐化合物(Hydrogen Silsesquioxane，简称为HSQ)、k值为2.2的甲基硅酸盐化合物(Methyl Silsesquioxane，简称MSQ)、以及化学气相沉积方法形成的多孔性二氧化硅等等。层间介质层210中设有有底部分别电连接位于元胞区的源区、位于第二沟槽区域内的第一沟槽状栅极、位于第三沟槽区域内的第二沟槽状栅极的第一接触塞211、第二接触塞212、第三接触塞213。
在一个实施例中，VDMOS器件还包括位于层间介质层210上的彼此独立的第一金属层214和第二金属层215。第一接触塞211和第二接触塞212的顶部电连接第一金属层214，第三接触塞213的顶部电连接第二金属层215。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种VDMOS器件的制造方法，包括：
    在半导体衬底中形成沟槽，所述沟槽包括第一沟槽区域、第二沟槽区域、第三沟槽区域、连通所述第一沟槽区域和第二沟槽区域的第四沟槽区域、以及连通所述第二沟槽区域和第三沟槽区域的第五沟槽区域；所述第二沟槽区域的宽度大于所述第一沟槽区域的宽度，所述第一沟槽区域的宽度大于所述第三沟槽区域、第四沟槽区域和第五沟槽区域的宽度；
    在所述半导体衬底上形成第一绝缘层，所述第一绝缘层填满所述第三沟槽区域和第五沟槽区域，且贴附在所述第一沟槽区域、第二沟槽区域和第四沟槽区域的侧壁上；
    在所述第一绝缘层上形成第一多晶硅层，所述第一多晶硅层填满所述第一沟槽区域，贴附在所述第二沟槽区域中的所述第一绝缘层的侧壁上，且所述第一沟槽区域内的第一多晶硅层与所述第二沟槽区域内的第一多晶硅层相连；
    在所述第一多晶硅层上形成第二绝缘层，所述第二绝缘层填满所述第二沟槽区域；
    去除部分所述第二绝缘层，直至露出所述第一多晶硅层；
    去除部分所述第一多晶硅层，留下的第一多晶硅层构成第一电极；
    在所述半导体衬底上形成第三绝缘层，所述第三绝缘层填满所述第一沟槽区域、第二沟槽区域和第四沟槽区域；
    去除部分所述第三绝缘层、第二绝缘层和第一绝缘层，以使所述第一多晶硅层的顶部高于所述第一绝缘层和所述第二绝缘层的顶部；
    在所述半导体衬底上形成栅氧化物层；
    在所述栅氧化物层上形成第二多晶硅层，所述第二多晶硅层填满所述沟槽；
    去除部分所述第二多晶硅层，露出位于所述半导体衬底表面的栅氧化物层以及所述第二绝缘层的顶部，留下的第二多晶硅层构成第二电极。
  2. 根据权利要求1所述的方法，其特征在于，所述第一电极包括在所述第一沟槽区域内的底部留下的柱状第一多晶硅层与在所述第二沟槽区域内的底部留下的桶状第一多晶硅层，所述柱状第一多晶硅层与所述桶状第一多晶硅层相连接。
  3. 根据权利要求1所述的方法，其特征在于，所述第二电极包括在所述第一沟槽区域内的上部留下的柱状第二多晶硅层、在所述第二沟槽区域内的上部留下的环状第二多晶硅层以及在所述第三沟槽区域内的上部留下的柱状第二多晶硅层；所述第一沟槽区域内、第二沟槽区域内和第三沟槽区域内的第二多晶硅层相连接。
  4. 根据权利要求1所述的方法，其特征在于，在所述半导体衬底上形成栅氧化物层包括：在所述沟槽露出的侧壁上以及所述第一多晶硅层上形成所述栅氧化物层。
  5. 根据权利要求1所述的方法，其特征在于，采用沉积或者氧化生长工艺形成所述第一绝缘层；采用沉积工艺形成所述第二绝缘层和所述第三绝缘层。
  6. 根据权利要求1所述的方法，其特征在于，通过湿法腐蚀工艺实施所述去除。
  7. 根据权利要求1所述的方法，其特征在于，所述去除部分所述第三绝缘层、第二绝缘层和第一绝缘层的步骤包括：
    去除部分所述第三绝缘层、所述第一绝缘层和所述第二绝缘层，使所述第三绝缘层、第一绝缘层和第二绝缘层的顶部平齐；
    实施湿法清洗，去除所述第三绝缘层的同时使所述第一多晶硅层的顶部高于所述第一绝缘层和所述第二绝缘层的顶部。
  8. 根据权利要求1所述的方法，其特征在于，去除多余的所述第二多晶硅层后，所述方法还包括：在所述半导体衬底上形成层间介质层的步骤。
  9. 根据权利要求1所述的方法，其特征在于，去除多余的所述第二多晶硅层后，所述方法还包括：在所述半导体衬底中形成阱区和源区的步骤。
  10. 根据权利要求6所述的方法，其特征在于，所述方法还包括：
    形成贯穿所述层间介质层的第一接触塞、第二接触塞和第三接触塞；
    所述第一接触塞的底部与元胞区的源区电连接；所述第二接触塞的底部与所述第一沟槽区域内的第一多晶硅层电连接；所述第三接触塞的底部与所述第二沟槽区域内的第二多晶硅层电连接。
  11. 根据权利要求10所述的方法，其特征在于，所述方法还包括：在所述层间介质层上形成彼此独立的第一金属层和第二金属层，所述第一接触塞 和所述第二接触塞的顶部电连接所述第一金属层，所述第三接触塞的顶部电连接所述第二金属层。
  12. 根据权利要求1所述的方法，其特征在于，所述第一电极构成深栅，所述第二电极构成浅栅，所述第一电极与所述第二电极之间通过所述栅氧化物层实现电气绝缘。
  13. 一种VDMOS器件，包括：
    半导体衬底，所述半导体衬底设有沟槽，所述沟槽包括第一沟槽区域、第二沟槽区域、第三沟槽区域、连通所述第一沟槽区域和第二沟槽区域的第四沟槽区域、以及连通所述第二沟槽区域和第三沟槽区域的第五沟槽区域；所述第二沟槽区域的宽度大于所述第一沟槽区域的宽度，所述第一沟槽区域的宽度大于所述第三沟槽区域、第四沟槽区域和第五沟槽区域的宽度；
    所述第一沟槽区域内设有由第一多晶硅层构成的深栅的第一电极、包裹所述第一电极的第一绝缘层、位于所述第一电极顶部的由第二多晶硅层构成的浅栅的第二电极以及位于所述第一电极和所述第二对晶硅层之间的栅氧化物层；
    所述第二沟槽区域内设有由第一多晶硅层构成的深栅的第一电极、被所述第一电极隔离的第一绝缘层和第二绝缘层、位于所述第一电极顶部的由第二多晶硅层构成的浅栅的第二电极以及位于所述第一电极和所述第二对晶硅层之间的栅氧化物层；
    所述第三沟槽区域内的底部设有第一绝缘层、位于所述第一绝缘层顶部的由第二多晶硅层构成的浅栅的第二电极；以及包裹所述第二电极的栅氧化物层；
    所述第四沟槽内设有由第一多晶硅层构成的深栅的第一电极、包裹所述第一电极的第一绝缘层、位于所述第一电极顶部的由第二多晶硅层构成的浅栅的第二电极以及位于所述第一电极和所述第二对晶硅层之间的栅氧化物层；
    所述第五沟槽区域内的底部设有第一绝缘层、位于所述第一绝缘层顶部的由第二多晶硅层构成的浅栅的第二电极；以及包裹所述第二电极的栅氧化 物层。
  14. 根据权利要求13所述的VDMOS器件，其特征在于，还包括位于所述半导体衬底的层间介质层；所述层间介质层中设有第一接触塞、第二接触塞和第三接触塞；
    所述第一接触塞的底部与元胞区的源区电连接；所述第二接触塞的底部与所述第一沟槽区域内的第一多晶硅层电连接；所述第三接触塞的底部与所述第二沟槽区域内的第二多晶硅层电连接。
  15. 根据权利要求13所述的VDMOS器件，其特征在于，还包括位于所述层间介质层上方且彼此独立的第一金属层和第二金属层；
    所述第一接触塞和所述第二接触塞的顶部分别与所述第一金属层电连接；所述第三接触塞的顶部与所述第二金属层电连接。
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