WO2018072288A1 - Goa驱动电路及液晶显示装置 - Google Patents

Goa驱动电路及液晶显示装置 Download PDF

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Publication number
WO2018072288A1
WO2018072288A1 PCT/CN2016/109868 CN2016109868W WO2018072288A1 WO 2018072288 A1 WO2018072288 A1 WO 2018072288A1 CN 2016109868 W CN2016109868 W CN 2016109868W WO 2018072288 A1 WO2018072288 A1 WO 2018072288A1
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Prior art keywords
thin film
film transistor
pull
gate
source
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Ceased
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PCT/CN2016/109868
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English (en)
French (fr)
Inventor
吕晓文
陈书志
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to JP2019541834A priority Critical patent/JP6775691B2/ja
Priority to EP16919423.0A priority patent/EP3531411A4/en
Priority to KR1020197013917A priority patent/KR102190083B1/ko
Priority to US15/326,014 priority patent/US10204583B2/en
Publication of WO2018072288A1 publication Critical patent/WO2018072288A1/zh
Anticipated expiration legal-status Critical
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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present invention relates to the field of liquid crystal display, and in particular to a GOA driving circuit and a liquid crystal display device.
  • Gate Driver On Array is a technology that uses a conventional thin film transistor liquid crystal display array process to fabricate a gate row scan driving signal circuit on an array substrate to realize a driving method of progressively scanning a pixel structure.
  • the thin film transistor of the GOA circuit often uses indium gallium zinc oxide, and the turn-on voltage Vth of the indium gallium zinc oxide is likely to drift.
  • the thin film transistor of the pull-up control module is likely to cause the gate signal due to the floating voltage Vth drift. Point Q leakage affects the function of the GOA unit.
  • the present invention provides a GOA driving circuit including a plurality of cascaded GOA units, and outputs a gate driving signal to an N-th horizontal scanning line Gn of a display area according to an Nth-level GOA unit, the N-th stage GOA unit
  • the device includes a pull-up module, a pull-up control module, a pull-down maintenance module, a downlink module, and a bootstrap capacitor module.
  • the pull-up module, the pull-down maintenance module, and the bootstrap capacitor module are respectively associated with the Nth-level gate signal point Qn and the The N-level horizontal scanning line Gn is electrically connected, and the pull-up control module and the downlink module are connected to the Nth-level gate signal point Qn;
  • the pull-up control module includes a first thin film transistor, a second thin film transistor, and a third thin film transistor, and a source of the first thin film transistor and a drain of the second thin film transistor are both connected to a drain of the third thin film transistor.
  • the source of the second thin film transistor and the gate of the third thin film transistor are both connected to the Nth stage gate signal point Qn, and the source of the third thin film transistor is connected to the pull-down maintaining module, the first thin film transistor And connecting a gate of the second thin film transistor and accessing the first high frequency clock signal;
  • the pull-down maintaining module is connected to the reference low voltage source.
  • the pull-down maintaining module sets the Nth-level gate signal point Qn and the N-th horizontal scanning line Gn with
  • the reference low voltage source is connected to pull the potential of the Nth gate signal point Qn and the Nth horizontal scan line Gn to a low level; and the source of the third thin film transistor is connected to the reference low voltage source, Thereby, the source of the third thin film transistor is pulled low to a low level.
  • the pull-down maintaining module includes two pull-down maintaining units; each of the pull-down maintaining units includes a fourth thin film transistor, a sixth thin film transistor, a seventh thin film transistor, an eighth thin film transistor, a ninth thin film transistor, and a Ten thin film transistors;
  • the drain and the gate of the seventh thin film transistor are both connected to the drain of the eighth thin film transistor and are connected to the low frequency clock signal, the source of the seventh thin film transistor, the gate of the eighth thin film transistor, and the tenth thin film.
  • a drain of the transistor is connected to the first node, a source of the eighth thin film transistor, a drain of the ninth thin film transistor, a gate of the fourth thin film transistor, and a gate of the sixth thin film transistor are connected to the second node.
  • the sources of the fourth thin film transistor, the sixth thin film transistor, and the tenth thin film transistor are connected to and connected to a first low voltage input of a reference low voltage source, and the source of the ninth thin film transistor is connected to a reference low voltage source input a second low voltage, a drain of the fourth thin film transistor, a gate of the ninth thin film transistor, and a gate of the tenth thin film transistor are both connected to the Nth gate signal point Qn, and the drain of the sixth thin film transistor
  • the poles are respectively connected to the source of the third thin film transistor and the Nth horizontal scanning line Gn; the low frequency clock signals respectively accessed by the two pulldown maintaining units are opposite in phase.
  • the low frequency clock signals LC of the two pull-down sustaining units are respectively accessed through different common metal lines.
  • the downlink module includes an eleventh thin film transistor, a drain of the eleventh thin film transistor is connected to a second high frequency clock signal, and a gate of the eleventh thin film transistor and an Nth gate Signal point Qn, the source of the eleventh thin film transistor outputs an Nth stage down signal STn;
  • the first pull-down maintaining unit further includes a fifth thin film transistor, a gate of the fifth thin film transistor is connected to the second node, a drain of the fifth thin film transistor and the eleventh thin film transistor The source is connected, and a source of the fifth thin film transistor is connected to the first low voltage.
  • the voltage value of the second low voltage is less than the voltage value of the second low voltage.
  • the pull-up module includes a twelfth thin film transistor, a drain of the twelfth thin film transistor is connected to the second high frequency clock signal, a source of the twelfth thin film transistor and the first The N-level horizontal scanning line Gn is connected, and the gate of the second thin film transistor is connected to the Nth-level gate signal point.
  • the second high frequency clock signal is inverted from the second high frequency clock signal.
  • the bootstrap capacitor module includes a bootstrap capacitor, one end of the bootstrap capacitor is connected to the Nth stage gate signal point Qn, and the other end of the bootstrap capacitor is horizontally scanned with the Nth stage Wire connection.
  • the first thin film transistor, the first thin film transistor, the second thin film transistor, and the third thin film transistor are all indium gallium zinc oxide thin film transistors.
  • the present invention also provides a liquid crystal display device comprising the GOA driving circuit according to any of the above.
  • the pull-up control module of the GOA driving circuit provided by the present invention comprises a first thin film transistor, a second thin film transistor and a third thin film transistor, and the source of the first thin film transistor and the drain of the second thin film transistor are both connected to the third thin film
  • the drain of the transistor is connected, the source of the second thin film transistor and the gate of the third thin film transistor are both connected to the Nth gate signal point Qn, and the source of the third thin film transistor is connected to the pull-down maintaining module.
  • the gates of the first thin film transistor and the second thin film transistor are connected to and connected to the first high frequency clock signal; when the Nth horizontal scanning line Gn is in the non-working time, the pull-down maintaining module will be the third thin film transistor
  • the source is in communication with the reference low voltage source, thereby pulling the source of the third thin film transistor to a low level, thereby preventing the pull-up control module from leaking to the gate signal point, and since the pull-down module is omitted
  • the number of thin film transistors can be reduced.
  • FIG. 1 is a schematic block diagram of an Nth stage GOA unit of a GOA driving circuit in a preferred embodiment of the present invention.
  • FIG. 2 is a circuit configuration diagram of an Nth stage GOA unit of the GOA driving circuit in the embodiment shown in FIG. 1 of the present invention.
  • the GOA driving circuit includes a GOA unit including a plurality of cascades, and outputs a gate driving signal to the N-th horizontal scanning line Gn of the display region according to the N-th stage GOA unit.
  • the Nth stage GOA unit includes a pull-up control module 101, a pull-up module 102, a pull-down maintenance module 103, a downlink module 105, and a bootstrap capacitor module 104.
  • the pull-up module 102, the pull-down maintaining module 103, and the bootstrap capacitor module 104 are respectively electrically connected to the Nth-level gate signal point Qn and the N-th horizontal scanning line Gn, and the pull-up control module 101 and the Nth The gate signal point Qn is connected, and the down module 105 is connected to the Nth gate signal point Qn.
  • the pull-up module 102 includes a twelfth thin film transistor T12, and a drain of the twelfth thin film transistor T12 is connected to a second high frequency clock signal CK, the twelfth thin film transistor.
  • the source of T12 is connected to the Nth horizontal scanning line Gn, and the gate of the twelfth thin film transistor T12 is connected to the Nth stage gate signal point Qn.
  • the pull-up module 102 is configured to output a gate scan signal to the Nth horizontal scan line according to the second high frequency clock signal CK.
  • the downstream module 105 includes an eleventh thin film transistor T11.
  • the drain of the eleventh thin film transistor T11 is connected to the second high frequency clock signal CK.
  • the gate of the eleventh thin film transistor T11 and the Nth gate signal At point Qn, the source of the eleventh thin film transistor T11 outputs an Nth stage down signal STn to the pull-up control module 101 of the (N+1)th GOA unit.
  • the pull-up control module 101 is configured to control the on-time of the twelfth thin film transistor T12 of the pull-up module 102 and the eleventh thin film transistor T11 of the downlink module 105.
  • the pull-up control module 101 includes a first thin film transistor T1, a second thin film transistor T2, and a third thin film transistor T3.
  • the source of the first thin film transistor T1 and the drain of the second thin film transistor T2 are both connected to the drain of the third thin film transistor T3, the source of the second thin film transistor T2 and the gate of the third thin film transistor T3 are both
  • the N-level gate signal point Qn is connected, the source of the third thin film transistor T3 is connected to the pull-down maintaining module 103, and the gates of the first thin film transistor T1 and the second thin film transistor T2 are connected and connected to the first high-frequency clock signal XCK.
  • the drain of the first thin film transistor T1 is connected to the turn-on signal STV.
  • the gates of the first thin film transistor and the second thin film transistor are connected and connected to the downlink module 105 of the N-1th stage GOA unit to receive the downlink.
  • the bootstrap capacitor module 104 includes a bootstrap capacitor Cb. One end of the bootstrap capacitor is connected to the Nth gate signal point, and the other end of the bootstrap capacitor Cb is connected to the Nth horizontal scan line Gn.
  • the pull-down maintaining module 103 is connected to the reference low voltage source.
  • the pull-down maintaining module 103 sets the Nth-level gate signal point Qn and the N-th horizontal scanning line Gn with
  • the reference low voltage source is connected to pull the potential of the Nth gate signal point Qn and the Nth horizontal scanning line Gn to a low level;
  • the source of the third thin film transistor T3 is connected to the reference low voltage source, thereby The source of the third thin film transistor T3 is pulled low to a low level.
  • the pull-down maintaining module 103 includes two pull-down maintaining units 1031 of the same structure.
  • Each of the pull-down maintaining units 1031 includes a fourth thin film transistor T4, a fifth thin film transistor T5, a sixth thin film transistor T6, a seventh thin film transistor T7, an eighth thin film transistor T8, a ninth thin film transistor T9, and a tenth thin film transistor. T10.
  • the drain and the gate of the seventh thin film transistor T7 are both connected to the drain of the eighth thin film transistor T8 and are connected to the low frequency clock signal LC1/LC2.
  • the source of the seventh thin film transistor T7, the gate of the eighth thin film transistor T8, and the drain of the tenth thin film transistor T10 are connected to the first node a1.
  • the source of the eighth thin film transistor T8, the drain of the ninth thin film transistor T9, the gate of the fourth thin film transistor T4, the gate of the fifth thin film transistor T5, and the gate of the sixth thin film transistor T6 are connected to the second node.
  • A2 the fourth thin film transistor T4, the fifth thin film transistor T5, and the sixth thin film transistor T6 are controlled by the voltage of the a2 point.
  • the sources of the fourth thin film transistor T4, the fifth thin film transistor T5, the sixth thin film transistor T6, and the tenth thin film transistor T10 are connected and connected to the first low voltage VSS1 of the reference low voltage source input, and the source of the ninth thin film transistor T9
  • the second low voltage VSS2 of the reference low voltage source input is connected.
  • the drain of the fourth thin film transistor T4, the gate of the ninth thin film transistor T9, and the gate of the tenth thin film transistor T10 are both connected to the Nth gate signal point Qn, and the drain of the sixth thin film transistor T6 is respectively
  • the source of the third thin film transistor T3 and the Nth horizontal scanning line Gn are connected; the drain of the fifth thin film transistor T5 is connected to the source of the eleventh thin film transistor T11. Since the voltage value of the second low voltage is less than the voltage value of the second low voltage, leakage of the gate signal point can be further prevented.
  • the first to twelfth thin film transistors are all indium gallium zinc oxide thin film transistors.
  • the phases of the low frequency clock signals LC1/LC2 respectively accessed by the two pull-down maintaining units 1031 are opposite, so that the two pull-down maintaining units 1031 can be alternately operated to avoid failure of the thin film transistors due to voltage stress.
  • the pull-up control module of the GOA driving circuit provided by the present invention comprises a first thin film transistor, a second thin film transistor and a third thin film transistor, and the source of the first thin film transistor and the drain of the second thin film transistor are both connected to the third thin film
  • the drain of the transistor is connected, the source of the second thin film transistor and the gate of the third thin film transistor are both connected to the Nth gate signal point Qn, and the source of the third thin film transistor is connected to the pull-down maintaining module.
  • the gates of the first thin film transistor and the second thin film transistor are connected to and connected to the first high frequency clock signal; when the Nth horizontal scanning line Gn is in the non-working time, the pull-down maintaining module will be the third thin film transistor
  • the source is in communication with the reference low voltage source, thereby pulling the source of the third thin film transistor to a low level, thereby preventing the pull-up control module from leaking to the gate signal point, and since the pull-down module is omitted
  • the number of thin film transistors can be reduced.

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  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Nonlinear Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Shift Register Type Memory (AREA)
  • Liquid Crystal (AREA)

Abstract

一种GOA驱动电路及液晶显示装置，GOA驱动电路包括多个级联的GOA单元，按照第N级GOA单元输出栅极驱动信号给显示区域第N级水平扫描线Gn，第N级GOA单元包括上拉模块(101)、上拉控制模块(102)、下拉维持模块(103)、下传模块(105)以及自举电容模块(104)。

Description

GOA驱动电路及液晶显示装置 技术领域
本发明涉及液晶显示领域，特别是涉及一种GOA驱动电路及液晶显示装置。
 背景技术
Gate Driver On Array，简称GOA，也就是利用现有薄膜晶体管液晶显示器阵列制程将栅极行扫描驱动信号电路制作在阵列基板上，实现对像素结构逐行扫描的驱动方式的一项技术。
现有技术中，GOA电路的薄膜晶体管经常采用铟镓锌氧化物，铟镓锌氧化物的开启电压Vth容易产生漂移，该上拉控制模块的薄膜晶体管由于开启电压Vth飘移容易造成该栅极信号点Q漏电，影响GOA单元的功能。
因此，现有技术存在缺陷，急需改进。
 技术问题
本发明的目的在于提供一种改进的GOA驱动电路及液晶显示装置。
 技术解决方案
为解决上述问题，本发明提供的技术方案如下：
本发明提供一种GOA驱动电路，该GOA驱动电路包括多个级联的GOA单元，按照第N级GOA单元输出栅极驱动信号给显示区域第N级水平扫描线Gn，该第N级GOA单元包括上拉模块、上拉控制模块、下拉维持模块、下传模块以及自举电容模块；所述上拉模块、下拉维持模块以及自举电容模块均分别与第N级栅极信号点Qn以及第N级水平扫描线Gn电连接，所述上拉控制模块以及下传模块与第N级栅极信号点Qn连接；
所述上拉控制模块包括第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管，所述第一薄膜晶体管的源极以及第二薄膜晶体管的漏极均与第三薄膜晶体管的漏极连接，所述第二薄膜晶体管的源极以及第三薄膜晶体管的栅极均与第N级栅极信号点Qn连接，所述第三薄膜晶体管的源极与下拉维持模块连接，所述第一薄膜晶体管以及第二薄膜晶体管的栅极连接并接入第一高频时钟信号；
所述下拉维持模块接入基准低电压源，当第N级水平扫描线Gn处于非工作时间内时，所述下拉维持模块将第N级栅极信号点Qn以及第N级水平扫描线Gn与基准低电压源连通，从而将第N级栅极信号点Qn以及第N级水平扫描线Gn的电位拉低至低电平；将第三薄膜晶体管的源极与所述基准低电压源连通，从而将第三薄膜晶体管的源极拉低至低电平。
优选地，所述下拉维持模块包括两个下拉维持单元；每一所述下拉维持单元均包括第四薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管、第九薄膜晶体管以及第十薄膜晶体管；
所述第七薄膜晶体管的漏极与栅极均与第八薄膜晶体管的漏极连接并接入低频时钟信号，所述第七薄膜晶体管的源极、第八薄膜晶体管的栅极以及第十薄膜晶体管的漏极连接于第一节点，所述第八薄膜晶体管的源极、第九薄膜晶体管的漏极、第四薄膜晶体管的栅极以及第六薄膜晶体管的栅极连接于第二节点，所述第四薄膜晶体管、第六薄膜晶体管以及第十薄膜晶体管的源极连接并接入基准低电压源输入的第一低电压，所述第九薄膜晶体管的源极接入基准低电压源输入的第二低电压，所述第四薄膜晶体管的漏极、第九薄膜晶体管的栅极以及第十薄膜晶体管的栅极均与第N级栅极信号点Qn连接，所述第六薄膜晶体管的漏极分别与第三薄膜晶体管的源极以及第N级水平扫描线Gn连接；该两个下拉维持单元分别接入的低频时钟信号相位相反。
优选地，该两个下拉维持单元的低频时钟信号LC分别通过不同的公共金属线接入。
优选地，所述下传模块包括第十一薄膜晶体管，所述第十一薄膜晶体管的漏极接入第二高频时钟信号，所述第十一薄膜晶体管的栅极与第N级栅极信号点Qn，所述第十一薄膜晶体管的源极输出第N级下传信号STn；
所述第一下拉维持单元还包括第五薄膜晶体管，所述第五薄膜晶体管的栅极与所述第二节点连接，所述第五薄膜晶体管的漏极与所述第十一薄膜晶体管的源极连接，所述第五薄膜晶体管的源极接入所述第一低电压。
优选地，所述第二低电压的电压值小于所述第二低电压的电压值。
优选地，所述上拉模块包括第十二薄膜晶体管，所述第十二薄膜晶体管的漏极接入所述第二高频时钟信号，所述第十二薄膜晶体管的源极与所述第N级水平扫描线Gn连接，所述第二薄膜晶体管的栅极与所述第N级栅极信号点连接。
优选地，所述第二高频时钟信号与所述第二高频时钟信号反相。
优选地，所述自举电容模块包括自举电容，所述自举电容的一端与所述第N级栅极信号点Qn连接，所述自举电容的另一端与所述第N级水平扫描线连接。
优选地，所述第一薄膜晶体管第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管均为铟镓锌氧化物薄膜晶体管。
本发明还提供一种液晶显示装置，包括上述任一项所述的GOA驱动电路。
 有益效果
本发明提供的GOA驱动电路的上拉控制模块包括第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管，所述第一薄膜晶体管的源极以及第二薄膜晶体管的漏极均与第三薄膜晶体管的漏极连接，所述第二薄膜晶体管的源极以及第三薄膜晶体管的栅极均与第N级栅极信号点Qn连接，所述第三薄膜晶体管的源极与下拉维持模块连接，所述第一薄膜晶体管以及第二薄膜晶体管的栅极连接并接入第一高频时钟信号；当第N级水平扫描线Gn处于非工作时间内时，所述下拉维持模块将第三薄膜晶体管的源极与所述基准低电压源连通，从而将第三薄膜晶体管的源极拉低至低电平，从而避免该上拉控制模块向该栅极信号点漏电，并且由于省略了下拉模块开可以减少薄膜晶体管的数量。
 附图说明
图1是本发明一优选实施例中的GOA驱动电路的第N级GOA单元的原理框图。
图2是本发明图1所示实施例中的GOA驱动电路的第N级GOA单元的电路结构图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
在图中，结构相似的模块是以相同标号表示。
请参照图1，该GOA驱动电路包括包括多个级联的GOA单元，按照第N级GOA单元输出栅极驱动信号给显示区域第N级水平扫描线Gn。该第N级GOA单元包括上拉控制模块101、上拉模块102、下拉维持模块103、下传模块105以及自举电容模块104。
其中，该上拉模块102、下拉维持模块103以及自举电容模块104均分别与第N级栅极信号点Qn以及第N级水平扫描线Gn电连接，该上拉控制模块101与该第N级栅极信号点Qn连接，下传模块105与第N级栅极信号点Qn连接。
同时参照图1以及图2，具体地，该上拉模块102包括第十二薄膜晶体管T12，该第十二薄膜晶体管T12的漏极接入第二高频时钟信号CK，该第十二薄膜晶体管T12的源极与第N级水平扫描线Gn连接，该第十二薄膜晶体管T12的栅极与第N级栅极信号点Qn连接。该上拉模块102用于根据该第二高频时钟信号CK输出栅极扫描信号给该第N级水平扫描线。
该下传模块105包括第十一薄膜晶体管T11，该第十一薄膜晶体管T11的漏极接入第二高频时钟信号CK，该第十一薄膜晶体管T11的栅极与第N级栅极信号点Qn，该第十一薄膜晶体管T11源极输出第N级下传信号STn给第N+1级GOA单元的上拉控制模块101。
该上拉控制模块101用于控制该上拉模块102的第十二薄膜晶体管T12以及下传模块105的第十一薄膜晶体管T11的导通时间。
该上拉控制模块101包括第一薄膜晶体管T1、第二薄膜晶体管T2以及第三薄膜晶体管T3。该第一薄膜晶体管T1的源极以及第二薄膜晶体管T2的漏极均与第三薄膜晶体管T3的漏极连接，第二薄膜晶体管T2的源极以及第三薄膜晶体管T3的栅极均与第N级栅极信号点Qn连接，第三薄膜晶体管T3的源极与下拉维持模块103连接，第一薄膜晶体管T1以及第二薄膜晶体管T2的栅极连接并接入第一高频时钟信号XCK。当该第N级GOA单元为第1级GOA单元时，该第一薄膜晶体管T1的漏极接入开启信号STV。当该第N级GOA单元不为第1级GOA单元时，该第一薄膜晶体管以及第二薄膜晶体管的栅极连接并与第N-1级GOA单元的下传模块105连接，以接收下传模块105发送的下传信号STn-1。
该自举电容模块104包括自举电容Cb，该自举电容的一端与该第N级栅极信号点连接，该自举电容Cb的另一端与该第N级水平扫描线Gn连接。
该下拉维持模块103下接入基准低电压源，当第N级水平扫描线Gn处于非工作时间内时，下拉维持模块103将第N级栅极信号点Qn以及第N级水平扫描线Gn与基准低电压源连通，从而将第N级栅极信号点Qn以及第N级水平扫描线Gn的电位拉低至低电平；将第三薄膜晶体管T3的源极与基准低电压源连通，从而将第三薄膜晶体管T3的源极拉低至低电平。
具体地，该下拉维持模块103包括两个结构相同的下拉维持单元1031。
其中，每一下拉维持单元1031均包括第四薄膜晶体管T4、第五薄膜晶体管T5、第六薄膜晶体管T6、第七薄膜晶体管T7、第八薄膜晶体管T8、第九薄膜晶体管T9以及第十薄膜晶体管T10。
该第七薄膜晶体管T7的漏极与栅极均与第八薄膜晶体管T8的漏极连接并接入低频时钟信号LC1/LC2。该第七薄膜晶体管T7的源极、第八薄膜晶体管T8的栅极以及第十薄膜晶体管T10的漏极连接于第一节点a1。该第八薄膜晶体管T8的源极、第九薄膜晶体管T9的漏极、第四薄膜晶体管T4的栅极、第五薄膜晶体管T5的栅极以及第六薄膜晶体管T6的栅极连接于第二节点a2，通过该a2点的电压来控制该第四薄膜晶体管T4、第五薄膜晶体管T5以及第六薄膜晶体管T6开关。
第四薄膜晶体管T4、第五薄膜晶体管T5、第六薄膜晶体管T6以及第十薄膜晶体管T10的源极连接并接入基准低电压源输入的第一低电压VSS1，第九薄膜晶体管T9的源极接入基准低电压源输入的第二低电压VSS2。该第四薄膜晶体管T4的漏极、第九薄膜晶体管T9的栅极以及第十薄膜晶体管T10的栅极均与第N级栅极信号点Qn连接，第六薄膜晶体管T6的漏极分别与第三薄膜晶体管T3的源极以及第N级水平扫描线Gn连接；该第五薄膜晶体管T5的漏极与该第十一薄膜晶体管T11的源极连接。由于第二低电压的电压值小于所述第二低电压的电压值，可以进一步防止栅极信号点漏电。
该第一至第十二薄膜晶体管均为铟镓锌氧化物薄膜晶体管。
该两个下拉维持单元1031分别接入的低频时钟信号LC1/LC2的相位相反，从而可以使得该两个下拉维持单元1031交替工作，避免因为电压应力导致薄膜晶体管失效。
本发明提供的GOA驱动电路的上拉控制模块包括第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管，所述第一薄膜晶体管的源极以及第二薄膜晶体管的漏极均与第三薄膜晶体管的漏极连接，所述第二薄膜晶体管的源极以及第三薄膜晶体管的栅极均与第N级栅极信号点Qn连接，所述第三薄膜晶体管的源极与下拉维持模块连接，所述第一薄膜晶体管以及第二薄膜晶体管的栅极连接并接入第一高频时钟信号；当第N级水平扫描线Gn处于非工作时间内时，所述下拉维持模块将第三薄膜晶体管的源极与所述基准低电压源连通，从而将第三薄膜晶体管的源极拉低至低电平，从而避免该上拉控制模块向该栅极信号点漏电，并且由于省略了下拉模块开可以减少薄膜晶体管的数量。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (12)

  1. 一种GOA驱动电路，其中，该GOA驱动电路包括多个级联的GOA单元，按照第N级GOA单元输出栅极驱动信号给显示区域第N级水平扫描线Gn，该第N级GOA单元包括上拉模块、上拉控制模块、下拉维持模块、下传模块以及自举电容模块；所述上拉模块、下拉维持模块以及自举电容模块均分别与第N级栅极信号点Qn以及第N级水平扫描线Gn电连接，所述上拉控制模块以及下传模块与第N级栅极信号点Qn连接；
    所述上拉控制模块包括第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管，所述第一薄膜晶体管的源极以及第二薄膜晶体管的漏极均与第三薄膜晶体管的漏极连接，所述第二薄膜晶体管的源极以及第三薄膜晶体管的栅极均与第N级栅极信号点Qn连接，所述第三薄膜晶体管的源极与下拉维持模块连接，所述第一薄膜晶体管以及第二薄膜晶体管的栅极连接并接入第一高频时钟信号；
    所述下拉维持模块接入基准低电压源，当第N级水平扫描线Gn处于非工作时间内时，所述下拉维持模块将第N级栅极信号点Qn以及第N级水平扫描线Gn与基准低电压源连通，从而将第N级栅极信号点Qn以及第N级水平扫描线Gn的电位拉低至低电平；将第三薄膜晶体管的源极与所述基准低电压源连通，从而将第三薄膜晶体管的源极拉低至低电平。
  2. 根据权利要求1所述的GOA驱动电路，其中，所述下拉维持模块包括两个下拉维持单元；每一所述下拉维持单元均包括第四薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管、第九薄膜晶体管以及第十薄膜晶体管；
    所述第七薄膜晶体管的漏极与栅极均与第八薄膜晶体管的漏极连接并接入低频时钟信号，所述第七薄膜晶体管的源极、第八薄膜晶体管的栅极以及第十薄膜晶体管的漏极连接于第一节点，所述第八薄膜晶体管的源极、第九薄膜晶体管的漏极、第四薄膜晶体管的栅极以及第六薄膜晶体管的栅极连接于第二节点，所述第四薄膜晶体管、第六薄膜晶体管以及第十薄膜晶体管的源极连接并接入基准低电压源输入的第一低电压，所述第九薄膜晶体管的源极接入基准低电压源输入的第二低电压，所述第四薄膜晶体管的漏极、第九薄膜晶体管的栅极以及第十薄膜晶体管的栅极均与第N级栅极信号点Qn连接，所述第六薄膜晶体管的漏极分别与第三薄膜晶体管的源极以及第N级水平扫描线Gn连接；该两个下拉维持单元分别接入的低频时钟信号相位相反。
  3. 根据权利要求2所述的GOA驱动电路，其中，该两个下拉维持单元的低频时钟信号分别通过不同的公共金属线接入。
  4. 根据权利要求2所述的GOA驱动电路，其中，所述下传模块包括第十一薄膜晶体管，所述第十一薄膜晶体管的漏极接入第二高频时钟信号，所述第十一薄膜晶体管的栅极与第N级栅极信号点Qn，所述第十一薄膜晶体管的源极输出第N级下传信号STn；
    所述第一下拉维持单元还包括第五薄膜晶体管，所述第五薄膜晶体管的栅极与所述第二节点连接，所述第五薄膜晶体管的漏极与所述第十一薄膜晶体管的源极连接，所述第五薄膜晶体管的源极接入所述第一低电压。
  5. 根据权利要求4所述的GOA驱动电路，其中，所述第二低电压的电压值小于所述第二低电压的电压值。
  6. 根据权利要求5所述的GOA驱动电路，其中，所述上拉模块包括第十二薄膜晶体管，所述第十二薄膜晶体管的漏极接入所述第二高频时钟信号，所述第十二薄膜晶体管的源极与所述第N级水平扫描线Gn连接，所述第二薄膜晶体管的栅极与所述第N级栅极信号点连接。
  7. 根据权利要求6所述的GOA驱动电路，其中，所述第一高频时钟信号与所述第二高频时钟信号反相。
  8. 根据权利要求1所述的GOA驱动电路，其中，所述自举电容模块包括自举电容，所述自举电容的一端与所述第N级栅极信号点Qn连接，所述自举电容的另一端与所述第N级水平扫描线Gn连接。
  9. 根据权利要求1所述的GOA驱动电路，其中，所述第一薄膜晶体管第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管均为铟镓锌氧化物薄膜晶体管。
  10. 一种GOA驱动电路，其包括多个级联的GOA单元，按照第N级GOA单元输出栅极驱动信号给显示区域第N级水平扫描线Gn，该第N级GOA单元包括上拉模块、上拉控制模块、下拉维持模块、下传模块以及自举电容模块；所述上拉模块、下拉维持模块以及自举电容模块均分别与第N级栅极信号点Qn以及第N级水平扫描线Gn电连接，所述上拉控制模块以及下传模块与第N级栅极信号点Qn连接；
    所述上拉控制模块包括第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管，所述第一薄膜晶体管的源极以及第二薄膜晶体管的漏极均与第三薄膜晶体管的漏极连接，所述第二薄膜晶体管的源极以及第三薄膜晶体管的栅极均与第N级栅极信号点Qn连接，所述第三薄膜晶体管的源极与下拉维持模块连接，所述第一薄膜晶体管以及第二薄膜晶体管的栅极连接并接入第一高频时钟信号；
    所述下拉维持模块接入基准低电压源，当第N级水平扫描线Gn处于非工作时间内时，所述下拉维持模块将第N级栅极信号点Qn以及第N级水平扫描线Gn与基准低电压源连通，从而将第N级栅极信号点Qn以及第N级水平扫描线Gn的电位拉低至低电平；将第三薄膜晶体管的源极与所述基准低电压源连通，从而将第三薄膜晶体管的源极拉低至低电平；
    所述下拉维持模块包括两个下拉维持单元；每一所述下拉维持单元均包括第四薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管、第九薄膜晶体管以及第十薄膜晶体管；
    所述第七薄膜晶体管的漏极与栅极均与第八薄膜晶体管的漏极连接并接入低频时钟信号，所述第七薄膜晶体管的源极、第八薄膜晶体管的栅极以及第十薄膜晶体管的漏极连接于第一节点，所述第八薄膜晶体管的源极、第九薄膜晶体管的漏极、第四薄膜晶体管的栅极以及第六薄膜晶体管的栅极连接于第二节点，所述第四薄膜晶体管、第六薄膜晶体管以及第十薄膜晶体管的源极连接并接入基准低电压源输入的第一低电压，所述第九薄膜晶体管的源极接入基准低电压源输入的第二低电压，所述第四薄膜晶体管的漏极、第九薄膜晶体管的栅极以及第十薄膜晶体管的栅极均与第N级栅极信号点Qn连接，所述第六薄膜晶体管的漏极分别与第三薄膜晶体管的源极以及第N级水平扫描线Gn连接；该两个下拉维持单元分别接入的低频时钟信号相位相反；
    该两个下拉维持单元的低频时钟信号分别通过不同的公共金属线接入；
    所述下传模块包括第十一薄膜晶体管，所述第十一薄膜晶体管的漏极接入第二高频时钟信号，所述第十一薄膜晶体管的栅极与第N级栅极信号点Qn，所述第十一薄膜晶体管的源极输出第N级下传信号STn；
    所述第一下拉维持单元还包括第五薄膜晶体管，所述第五薄膜晶体管的栅极与所述第二节点连接，所述第五薄膜晶体管的漏极与所述第十一薄膜晶体管的源极连接，所述第五薄膜晶体管的源极接入所述第一低电压；
    所述第二低电压的电压值小于所述第二低电压的电压值；
    所述上拉模块包括第十二薄膜晶体管，所述第十二薄膜晶体管的漏极接入所述第二高频时钟信号，所述第十二薄膜晶体管的源极与所述第N级水平扫描线Gn连接，所述第二薄膜晶体管的栅极与所述第N级栅极信号点连接；
    所述第一高频时钟信号与所述第二高频时钟信号反相；
    所述自举电容模块包括自举电容，所述自举电容的一端与所述第N级栅极信号点Qn连接，所述自举电容的另一端与所述第N级水平扫描线Gn连接；
    所述第一薄膜晶体管第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管均为铟镓锌氧化物薄膜晶体管。
  11. 一种液晶显示装置，其包括权利要求1所述的GOA驱动电路。
  12. 一种液晶显示装置，其包括权利要求10所述的GOA驱动电路。
PCT/CN2016/109868 2016-10-18 2016-12-14 Goa驱动电路及液晶显示装置 Ceased WO2018072288A1 (zh)

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