WO2018090607A1 - 一种场效应晶体管及其制作方法 - Google Patents

一种场效应晶体管及其制作方法 Download PDF

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WO2018090607A1
WO2018090607A1 PCT/CN2017/088086 CN2017088086W WO2018090607A1 WO 2018090607 A1 WO2018090607 A1 WO 2018090607A1 CN 2017088086 W CN2017088086 W CN 2017088086W WO 2018090607 A1 WO2018090607 A1 WO 2018090607A1
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layer
semiconductor material
material layer
gate
support structure
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French (fr)
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马小龙
张日清
巴德尔⋅斯蒂芬
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Priority to EP17872453.0A priority Critical patent/EP3534407B1/en
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Priority to US16/417,544 priority patent/US11043575B2/en
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Priority to US17/352,161 priority patent/US11664440B2/en
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/014—Manufacture or treatment of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/026—Manufacture or treatment of FETs having insulated gates [IGFET] having laterally-coplanar source and drain regions, a gate at the sides of the bulk channel, and both horizontal and vertical current flow
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/402—Single electron transistors; Coulomb blockade transistors
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/43—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6735—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes having gates fully surrounding the channels, e.g. gate-all-around
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H10D62/116—Dielectric isolations, e.g. air gaps adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H10D62/118—Nanostructure semiconductor bodies
    • H10D62/119—Nanowire, nanosheet or nanotube semiconductor bodies
    • H10D62/121—Nanowire, nanosheet or nanotube semiconductor bodies oriented parallel to substrates
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs

Definitions

  • Embodiments of the present invention relate to the field of semiconductor technologies, and in particular, to a field effect transistor and a method of fabricating the same.
  • a MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor
  • a first semiconductor material layer 11 and a second semiconductor material layer 12 are stacked in sequence, and a dummy gate structure 13 on the second semiconductor material layer 12 is formed, and source and drain regions on both sides of the channel 100 are formed by a doping process.
  • the second semiconductor material layer 12 and the dummy gate structure 13 can be removed by an etching process.
  • the RMG (Replacement Metal Gate) process can be used.
  • the locations of a layer of semiconductor material 11 and dummy gate structure 13 are filled with a gate material, such as a high dielectric constant (High-K) material, to form a true gate 21.
  • a gate material such as a high dielectric constant (High-K) material
  • the source 14 and the drain 15 are formed by a doping process, as shown in FIG. 1, the source 14 (or the drain 15) and the first semiconductor material layer 11 and the second in the channel 100 are as shown in FIG.
  • the semiconductor material layer 12 is in direct contact such that a part of impurity atoms are diffused into the second semiconductor material layer 12 and the first semiconductor material layer 11 to form an extension region 22, resulting in an increase in parasitic capacitance such as a parasitic capacitance of a subsequently formed MOSFET, MOSFET
  • the GIDL gated-induce drain leakage
  • Embodiments of the present invention provide a field effect transistor and a method of fabricating the same, which can reduce parasitic parameters of a field effect transistor, thereby improving performance and reliability of the field effect transistor.
  • an embodiment of the present invention provides a method of fabricating a field effect transistor, comprising: forming a fin-shaped support structure having a superlattice feature on a semiconductor substrate, the support structure including alternating first semiconductor materials a layer and a second layer of semiconductor material, the support structure is provided with an isolation layer on both sides thereof; and a dummy gate structure covering the support structure is formed along the boundary between the isolation layer and the support structure, the dummy gate structure is in the gate length direction (gate length direction) a length indicating a transport direction of carriers in the field effect transistor is smaller than a length of the first semiconductor material layer in the gate length direction; and a first semiconductor material layer is removed in the gate length direction except the sacrificial layer An insulating recess is formed in the first semiconductor material layer in the target direction (ie, perpendicular to the bottom surface of the semiconductor substrate) a projection region of the direction, a dielectric constant of the dielectric filled in the insulating recess is smaller than a dielectric constant
  • the gate material ie, the material having a larger dielectric constant
  • the gate material can also be isolated from the source and the drain through the insulating recess, thereby reducing the source and the source.
  • Parasitic parameters such as parasitic capacitance formed by direct contact of the drain with the gate material improve the performance and reliability of the field effect transistor.
  • a region other than the sacrificial layer in the first semiconductor material layer is removed along the gate length direction to form an insulating recess, including: along the gate length direction, the first semiconductor The material layer is subjected to a selective oxidation process such that a region other than the sacrificial layer in the first semiconductor material layer is oxidized to form an insulating recess.
  • the dielectric filled in the insulating recess is an oxide of the first semiconductor material layer,
  • the dielectric constant is generally low, so the insulating recess can isolate the subsequently formed source (or drain) and the high-K (high dielectric constant) dielectric material filling the sacrificial layer, avoiding the source (or drain). Parasitic capacitance is generated directly after contact with High-K dielectric material.
  • a region other than the sacrificial layer in the first semiconductor material layer is removed along the gate length direction to form an insulating recess, including: along the gate length direction, the first semiconductor The material layer is subjected to a selective etching process such that a region other than the sacrificial layer in the first semiconductor material layer is removed to form an insulating groove.
  • the dielectric filled in the insulating recess is air having a low dielectric constant, and therefore, the insulating recess can isolate the subsequently formed source (or drain) and the high-k dielectric material filled with the sacrificial layer, avoiding the source. Parasitic capacitance is generated when the pole (or drain) is in direct contact with the High-K dielectric material.
  • the method further comprises: filling the dielectric recess with a dielectric material having a dielectric constant of less than 3.9.
  • the insulating recess is filled with a dielectric material having a dielectric constant of less than 3.9, that is, a Low-K dielectric material. Therefore, the insulating recess can isolate the subsequently formed source (or drain) and the high layer filled with the sacrificial layer. K dielectric material prevents parasitic capacitance from being generated when the source (or drain) is directly in contact with the High-K dielectric material.
  • the method further comprises: forming an etch stop on the surface of the insulating recess by an ALD process along the gate length direction. Floor.
  • the etch stop layer can block the etching of the etching solution to a region other than the sacrificial layer when the sacrificial layer is removed.
  • the method further includes: removing the dummy gate structure and the sacrificial layer; along the cross-sectional direction of the gate structure, The thickness of the second semiconductor material layer is adjusted, and the cross-sectional direction of the gate structure is perpendicular to the gate length direction. Since the channel effect of the field effect transistor is related to the thickness of the second semiconductor material layer, by adjusting the thickness of the second semiconductor material layer, the channel effect of the field effect transistor can be improved, and the channel effect can be flexibly adjusted.
  • adjusting the thickness of the second semiconductor material layer comprises: reducing the thickness of the second semiconductor material layer from 8 nm to 4 nm by an etching process.
  • the method further includes: removing the dummy gate structure and the sacrifice by the RMG process The position of the layer forms a gate.
  • a support structure having superlattice features is formed on a semiconductor substrate, comprising: periodically growing a periodic superlattice of the first semiconductor material layer and the second semiconductor material layer on the semiconductor substrate.
  • the structure, the first semiconductor material layer and the second semiconductor material layer each have a thickness of less than 50 nm; the superlattice structure is etched to form a fin-shaped support structure.
  • forming a dummy gate structure covering the support structure along the interface between the isolation layer and the support structure comprises: forming an oxide layer on the exposed support structure; forming a support structure on the oxide layer covering the support structure False gate structure.
  • the length of the dummy gate structure in the cross-sectional direction of the gate structure is smaller than the length of the isolation layer, wherein after forming the dummy gate structure surrounding the support structure on the isolation layer, the method further includes: An insulating layer is deposited on the periphery of the dummy gate structure, and sidewalls of the insulating layer are flush with sidewalls of the isolation layer.
  • an embodiment of the present invention provides a field effect transistor including a source and a drain, a gate is disposed in the channel between the source and the drain, and the gate passes through the insulating recess and the source and the drain
  • the dielectric constant of the dielectric filled in the insulating recess is smaller than the dielectric constant of the first semiconductor material layer
  • the first semiconductor material layer is a superlattice material thin film formed when the field effect transistor is fabricated.
  • FIG. 1 is a schematic diagram 1 of a fabrication principle of a field effect transistor in the prior art
  • FIG. 2 is a schematic diagram 2 of a fabrication principle of a field effect transistor in the prior art
  • FIG. 3 is a schematic structural diagram of a field effect transistor according to an embodiment of the present invention.
  • FIG. 4 is a schematic flow chart of a method for fabricating a field effect transistor according to an embodiment of the present invention
  • FIG. 5 is a schematic diagram 1 of a manufacturing principle of a field effect transistor according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram 2 of a fabrication principle of a field effect transistor according to an embodiment of the present invention.
  • FIG. 7 is a schematic diagram 3 of a manufacturing principle of a field effect transistor according to an embodiment of the present invention.
  • FIG. 8 is a schematic diagram 4 of a manufacturing principle of a field effect transistor according to an embodiment of the present invention.
  • FIG. 9 is a schematic diagram 5 of a manufacturing principle of a field effect transistor according to an embodiment of the present invention.
  • FIG. 10 is a schematic diagram 6 of a fabrication principle of a field effect transistor according to an embodiment of the present invention.
  • FIG. 11 is a schematic diagram 7 of a manufacturing principle of a field effect transistor according to an embodiment of the present invention.
  • FIG. 12 is a schematic diagram 8 of a fabrication principle of a field effect transistor according to an embodiment of the present invention.
  • FIG. 13 is a schematic diagram IX of a fabrication principle of a field effect transistor according to an embodiment of the present invention.
  • FIG. 14 is a schematic diagram of a manufacturing principle of a field effect transistor according to an embodiment of the present invention.
  • FIG. 15 is a schematic diagram 11 of a fabrication principle of a field effect transistor according to an embodiment of the present invention.
  • FIG. 16 is a schematic diagram 12 of a fabrication principle of a field effect transistor according to an embodiment of the present invention.
  • FIG. 17 is a schematic diagram of a fabrication principle of a field effect transistor according to an embodiment of the present invention.
  • Embodiments of the present invention provide a field effect transistor, which may be a MOSFET, for example, a Stacked Gate-All-Around Nanowire Transistor, a Fin Field-Effect Transistor The FinFET and the like may also be a Tunneling Field Effect Transistor (TFET), etc., which is not limited in the embodiment of the present invention.
  • a field effect transistor which may be a MOSFET, for example, a Stacked Gate-All-Around Nanowire Transistor, a Fin Field-Effect Transistor The FinFET and the like may also be a Tunneling Field Effect Transistor (TFET), etc., which is not limited in the embodiment of the present invention.
  • TFET Tunneling Field Effect Transistor
  • a field effect transistor and a method for fabricating the same are provided.
  • FIG. 3 a field provided by an embodiment of the present invention is provided.
  • a schematic diagram of the structure of the effect transistor wherein the semiconductor substrate 31 is provided with a gate 32, and both sides of the gate 32 are source and drain regions, respectively provided with fin-shaped source 33 and drain 34, then, along the XX' direction It is used to indicate the gate length direction of the field effect transistor, that is, the transport direction of carriers in the field effect transistor; in the YY' direction, it is used to indicate the gate structure direction of the gate effect transistor, the gate length direction and the gate structure.
  • the cross-sectional directions are perpendicular to each other.
  • FIG. 3 only the structure of a set of gates 32, sources 33 and drains 34 in the field effect transistor is shown. It can be understood that the field effect transistors may also include multiple sets of similarly structured gates. The embodiment of the present invention does not limit the pole, the source and the drain.
  • an embodiment of the present invention provides a method for fabricating a field effect transistor, as shown in FIG. 4, including:
  • a support structure having a superlattice feature on a semiconductor substrate comprising a first layer of semiconductor material and a second layer of semiconductor material disposed alternately, and an isolation layer is disposed on both sides of the support structure.
  • the semiconductor substrate may be a SOI (Silicon-On-Insulator) substrate, a bulk silicon substrate, an ETSOI (Extremely Thin SOI) substrate, and SGOI (SiGe-On-). Insulator, a silicon germanium substrate on an insulating substrate or a IIIV-OI (IIIV-On-Insulator) substrate, etc., is not limited in the embodiment of the present invention.
  • FIG. 5 ((a) in FIG. 5 is a schematic cross-sectional view along the length of the gate, and (b) in FIG. 5 is a schematic cross-sectional view along the cross-sectional direction of the gate structure), which may be first on the semiconductor substrate 51.
  • the thickness of the first semiconductor material layer 52 and the second semiconductor material layer 53 may both be less than 50 nm.
  • the first semiconductor material layer 52 is a silicon material
  • the second semiconductor material layer 53 may be a silicon germanium material.
  • the superlattice structure composed of the first semiconductor material layer 52 and the second semiconductor material layer 53 may be etched to form a support structure 61 as shown in FIG. 6.
  • the support structure 61 may be a fin.
  • the shape is provided on the semiconductor substrate 51. (a) in FIG. 6 is a schematic cross-sectional view along the length of the gate, and (b) in FIG. 6 is a schematic cross-sectional view along the cross-sectional direction of the gate structure.
  • the isolation layer 71 may be continuously formed on both sides of the support structure 61 by a CMP (chemical mechanical flattening) process and a Recess process.
  • CMP chemical mechanical flattening
  • the thickness of the isolation layer 71 is the same as the thickness of the etched semiconductor substrate 51.
  • the isolation layer 71 may be made of an oxide such as silicon oxide, which is not limited in the embodiment of the present invention.
  • the length of the dummy gate structure in the gate length direction is smaller than the length of the first semiconductor material layer in the gate length direction.
  • a dummy gate structure 81 covering the support structure 61 may be further formed on the isolation layer 71.
  • the support structure 61 is embedded in the isolation layer 71 and the dummy gate.
  • the structure 81 is formed in the gap.
  • the length of the dummy gate structure 81 in the gate length direction is smaller than the length of the first semiconductor material layer 52 in the gate length direction.
  • (a) in FIG. 9 is a schematic cross-sectional view along the length of the gate
  • (b) in FIG. 9 is a schematic cross-sectional view along the cross-sectional direction of the gate structure.
  • the dummy gate structure 81 may be made of a polysilicon or an amorphous silicon material, which is not limited in the embodiment of the present invention.
  • an oxide layer (Dummy Oxide) may be formed on the exposed support structure 61; and a dummy gate structure 81 enclosing the support structure 61 is formed on the oxide layer.
  • an insulating layer 91 may be deposited on the periphery of the dummy gate structure 81 such that the sidewall of the insulating layer 91 is aligned with the sidewall of the isolation layer 71 in the cross-sectional direction of the gate structure, wherein, in FIG. (a) is a schematic cross-sectional view along the length of the gate, and (b) in FIG. 10 is a schematic cross-sectional view along the cross-sectional direction of the gate structure.
  • the anisotropy of the etching is ensured as much as possible, and the etching selection ratio of the polysilicon: silicon oxide is adjusted as high as possible, thereby forming a pseudo gate structure with a steep topography 81.
  • the pseudo-gate structure 81 having a relatively steep shape is advantageous for the subsequent formation of the insulating layer 91, so that the dummy gate structure 81 and the insulating layer 91 can be better adhered, thereby ensuring effective isolation of the dummy gate structure 81.
  • the sacrificial layer is in the first semiconductor material layer 52, and the dummy gate structure 81 is in the target direction (the target direction is perpendicular to the bottom surface of the semiconductor substrate 51, that is, the front projection direction of the dummy gate structure 81 in the first semiconductor material layer 52.
  • the dielectric constant of the dielectric filled in the insulating recess is smaller than the dielectric constant of the first semiconductor material layer.
  • the first semiconductor material layer 52 and the second semiconductor material layer 53 may be etched along the sidewall of the insulating layer 91 to make the first semiconductor material layer 52 and The sidewall of the second semiconductor material layer 53 is aligned with the insulating layer 91 (as shown in (a) of FIG. 11).
  • FIG. 11 is a schematic cross-sectional view along the length of the gate
  • FIG. 11 is a schematic cross-sectional view along the cross-sectional direction of the gate structure.
  • a selective oxidization process is performed on the first semiconductor material layer 52 shown in (a) of FIG. 11 such that the dummy gate structure 81 is in the first semiconductor material layer 52 in the first semiconductor material layer 52.
  • the area outside the projection area is oxidized, and the portion of the space to be oxidized forms the insulating groove 101 as shown in (a) of FIG. 12, and the dummy gate structure 81 is in the first semiconductor
  • the projected area of the material layer 52 is not oxidized, forming the sacrificial layer 102 as shown in (a) of FIG.
  • the insulating recess 101 is filled with an oxide (for example, silicon oxide) of the first semiconductor material layer 52, and the dielectric constant of the oxide of the first semiconductor material layer 52 is generally low, and therefore, the insulating recess 101 can isolate the subsequently formed source (or drain) and the gate material filling the sacrificial layer 102, for example, a High-K (high dielectric constant) dielectric material, to avoid direct formation of the subsequently formed source (or drain) A parasitic capacitance is generated after the gate contact formed by the gate material contacts.
  • FIG. 12 is a schematic cross-sectional view along the length of the gate
  • FIG. 12 is a schematic cross-sectional view along the cross-sectional direction of the gate structure.
  • the first semiconductor material layer 52 is silicon
  • silicon oxide is formed in the insulating recess 101, and the dielectric constant of the silicon oxide is about 3.9, and the dielectric constant of silicon is about It is 11.5, much smaller than the dielectric constant of silicon oxide.
  • the first semiconductor material layer 52 shown in (a) of FIG. 11 may be selectively etched along the gate length direction such that the first semiconductor material In the layer 52, the dummy gate structure 81 is removed in a region other than the projection region of the first semiconductor material layer 52, forming an insulating recess 101 as shown in (a) of FIG. 13, and the dummy gate structure 81 is in the first semiconductor.
  • the projected area of the material layer 52 is retained to form the sacrificial layer 102 as shown in (a) of FIG. At this time, the air filled with the insulating groove 101 is air.
  • Air as a medium with a low dielectric constant can isolate the subsequently formed source (or drain) and the gate material filling the sacrificial layer 102, thereby avoiding the subsequently formed source.
  • the pole (or drain) directly contacts the gate formed by the gate material to create a parasitic capacitance.
  • FIG. 13 is a schematic cross-sectional view along the length of the gate, and
  • FIG. 13 is a schematic cross-sectional view along the cross-sectional direction of the gate structure.
  • FIG. 14 ((a) in FIG. 14 is a schematic cross-sectional view along the gate length direction, and (b) in FIG. 14 is along the gate.
  • an etch stop layer 111 may be formed on the surface layer of the insulating recess 101 by an ALD (Atomic Layer Deposition) process along the gate length direction.
  • ALD Atomic Layer Deposition
  • the etch stop layer 111 can block the etching of the etching solution to a region other than the sacrificial layer 102 when the sacrificial layer 102 is removed.
  • a dielectric material having a dielectric constant of less than 3.9 for example, a Low-K (low dielectric constant) dielectric material 121, may be filled in the insulating groove 101.
  • a lower K (dielectric constant) value is made in the insulating recess 101 to prevent the subsequently formed source (and drain) from directly contacting the gate formed by the gate material filling the sacrificial layer 102 to generate parasitic capacitance.
  • a dielectric material having a dielectric constant of less than 2.5 can be used as a Low-K dielectric material, for example, SiCOH (hydrogenated silicon oxide carbon) or the like.
  • a dielectric material having a dielectric constant of more than 4 can be used as a High-K dielectric material, for example, HfO 2 (cerium oxide) or the like.
  • the first semiconductor material layer 52 or the second semiconductor material layer 53 has a dielectric constant of about 10-12.
  • a material such as silicon or germanium silicon may be epitaxially grown in a predetermined source/drain region by using a selective epitaxial technique.
  • the source-drain region has a certain doping concentration by a doping process, and is formed as shown in FIG. 15 ((a) in FIG. 15 is a schematic cross-sectional view along the gate length direction, and (b) in FIG. 15 is a cross-sectional direction along the gate structure.
  • a schematic cross-sectional view of the source 131 and the drain 132 is shown.
  • the source 131 and the drain 132 are separated from the sacrificial layer 102 by the insulating groove 101. Subsequently, after the sacrificial layer 102 is removed, the high-k dielectric material can be filled to the position of the sacrificial layer 102 to form a gate. Then, the source 131 and the drain 132 can still be isolated from the gate through the insulating recess 101, thereby reducing The source 131 and the drain 132 directly contact the gate to generate a parasitic capacitance.
  • the source 131 and the drain 132 are formed, impurity atoms are diffused to the second semiconductor material layer 53, forming the expanded region 133, and the size and field effect of the extended region.
  • the parasitic resistance of the transistor is related. When the extended region is larger, the value of the parasitic resistance is smaller. When the extended region is smaller, the value of the parasitic resistance is larger.
  • the thickness of the second semiconductor material layer 53 can be set as large as possible, thereby forming a large expanded region.
  • the ability of the field effect transistor to suppress short-channel effects is lowered, for example, the leakage current of the field effect transistor is increased.
  • FIG. 16 (a) in FIG. 16 is a schematic cross-sectional view along the length of the gate, and (b) in FIG. 16 is a cross-sectional view along the cross-sectional direction of the gate structure, the dummy gate structure can be removed by an etching process. 81 and sacrificial layer 102.
  • the thickness of the second semiconductor material layer 53 in the channel region can be adjusted, for example, the thickness T1 of the second semiconductor material layer 53 before adjustment is adjusted to be 8 nm.
  • the thickness of the second semiconductor material layer 53 can improve the short channel effect of the field effect transistor, thereby achieving flexible adjustment of the short channel effect without increasing the parasitic resistance.
  • the gate 151 as shown in FIG. 17 may be formed at the position of the removed dummy gate structure 81 and the sacrificial layer 102 by the RMG (Replacement Metal Gate) process using the prior art. It includes at least two layers of structure, one layer is a High-K dielectric material, and the other layer is a metal material having a specific work function), and finally a field effect transistor is formed, wherein (a) in FIG. 17 is a section along the gate length direction. In the schematic view, (b) in FIG. 17 is a schematic cross-sectional view along the cross-sectional direction of the gate structure.
  • a position where the first semiconductor material layer 51 is originally disposed in the gate 151 can pass through a material having a lower dielectric constant and a source 131 in the insulating recess 101. (or the drain 132) is isolated, and the position of the gate 151 originally filled with the dummy gate structure 81 can be isolated from the source 131 (or the drain 132) through the insulating layer 91, that is, the gate 151 is insulated by the recess.
  • the trench 101 and the insulating layer 91 are almost completely isolated from the source 131 (or the drain 132), thereby reducing the parasitic capacitance of the entire field effect transistor and improving the performance and reliability of the field effect transistor.
  • the embodiment of the present invention further provides a field effect transistor, which may be a MOSFET or a tunneling field effect transistor, etc., which is not limited in this embodiment of the present invention.
  • a field effect transistor which may be a MOSFET or a tunneling field effect transistor, etc., which is not limited in this embodiment of the present invention.
  • the gate 151 is disposed in a channel formed between the source 131 and the drain 132, and the gate 151 is Instead of being in direct contact with the source 131 (or the drain 132), it is isolated from the source 131 (or the drain 132) by the insulating recess 101, and the insulating recess 101 is filled with a material having a low dielectric constant, thus The parasitic capacitance generated by the direct contact between the gate electrode 151 and the source 131 (or the drain 132) can be avoided, and the performance and reliability of the field effect transistor can be improved.
  • embodiments of the present invention provide a field effect transistor and a method of fabricating the same, in which a support structure having superlattice features is formed on a semiconductor substrate, the support structure including first semiconductors arranged alternately a material layer and a second semiconductor material layer, the support structure is provided with an isolation layer on both sides thereof; further, a dummy gate structure covering the support structure is formed on the isolation layer, and the length of the dummy gate structure in the gate length direction is smaller than the first a length of the semiconductor material layer in the gate length direction; then, in the gate length direction, a region other than the sacrificial layer in the first semiconductor material layer may be removed to form an insulating recess, and the first semiconductor material layer except the sacrificial layer The region forms an insulating recess, wherein the sacrificial layer is a projected region of the dummy semiconductor structure in the target direction (ie, perpendicular to the surface of the isolation layer provided with the support structure), and the insulating recess is
  • the source and the drain may be separated from the gate material filling the sacrificial layer (for example, High-K dielectric material) through the insulating recess, and the parasitic capacitance may be generated after the source (or the drain) is directly in contact with the gate material. , thereby reducing the parasitic capacitance of the entire field effect transistor and improving the performance and reliability of the field effect transistor.
  • the sacrificial layer for example, High-K dielectric material
  • the functions described herein can be implemented in hardware, software, firmware, or any combination thereof.
  • the functions may be stored in a computer readable medium or transmitted as one or more instructions or code on a computer readable medium.
  • Computer readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one location to another.
  • a storage medium may be any available media that can be accessed by a general purpose or special purpose computer.

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Abstract

提供一种场效应晶体管及其制作方法，涉及半导体技术领域，可减小场效应晶体管的寄生参数，从而提高场效应晶体管的可靠性。该方法包括：在半导体衬底（51）上形成具有超晶格特征的支撑结构（61），该支撑结构（61）包括交替设置的第一半导体材料层（52）和第二半导体材料层（53），支撑结构（61）的两侧设置有隔离层（71）。沿着隔离层（71）与支撑结构（61）的交界形成覆盖支撑结构（61）的假栅结构（81），假栅结构（81）在栅长方向的长度小于第一半导体材料层在栅长方向的长度。沿栅长方向，去除第一半导体材料层（52）中除牺牲层（102）以外的区域，形成绝缘凹槽（101），绝缘凹槽（101）中所填充的介质的介电常数小于第一半导体材料层（52）的介电常数。沿栅长方向，在预设的源漏区域形成源极（131）和漏极（132），源极（131）和漏极（132）通过绝缘凹槽（101）与牺牲层（102）隔离。

Description

一种场效应晶体管及其制作方法
本申请要求于2016年11月21日提交中国专利局、申请号为201611022835.2、发明名称为“一种场效应晶体管及其制作方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明实施例涉及半导体技术领域，尤其涉及一种场效应晶体管及其制作方法。
背景技术
目前，在制作场效应晶体管(Field-Effect Transistor，FET)时，以MOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor，金属-氧化物半导体场效应晶体管)为例，如图1所示，沟道100内一般依次堆叠有第一半导体材料层11和第二半导体材料层12，以及位于第二半导体材料层12上的假栅结构13，在沟道100两侧的源漏区域通过掺杂工艺形成源极14和漏极15之后，可通过刻蚀工艺去除第二半导体材料层12以及假栅结构13，进而，如图2所示，可通过RMG(Replacement Metal Gate，替代栅)工艺，在第一半导体材料层11和假栅结构13的位置填充栅极材料，例如，高介电常数(High-K)材料，形成真正的栅极21。
在上述制作方法中，通过掺杂工艺形成源极14和漏极15时，如图1所示，源极14(或漏极15)与沟道100内的第一半导体材料层11和第二半导体材料层12直接接触，使得一部分杂质原子扩散至第二半导体材料层12和第一半导体材料层11中形成扩展(Extension)区域22，导致后续形成的MOSFET的寄生电容等寄生参数增大，MOSFET的GIDL(gated-induce drain leakage，栅诱导漏极泄漏电流)也会增加，严重影响了MOSFET的性能和可靠性。
发明内容
本发明的实施例提供一种场效应晶体管及其制作方法，可减小场效应晶体管的寄生参数，从而提高场效应晶体管的性能和可靠性。
为达到上述目的，本发明的实施例采用如下技术方案：
第一方面，本发明的实施例提供一种场效应晶体管的制作方法，包括：在半导体衬底上形成具有超晶格特征的鳍状的支撑结构，该支撑结构包括交替设置的第一半导体材料层和第二半导体材料层，该支撑结构的两侧设置有隔离层；沿着隔离层与支撑结构的交界形成覆盖该支撑结构的假栅结构，该假栅结构在栅长方向(栅长方向用于指示所述场效应晶体管中载流子的输运方向)的长度小于该第一半导体材料层在该栅长方向的长度；沿栅长方向，去除第一半导体材料层中除牺牲层以外的区域，形成绝缘凹槽，该牺牲层为：第一半导体材料层中该假栅结构沿目标方向(即垂直于该半导体衬底底面的 方向)的投影区域，该绝缘凹槽中填充的介质的介电常数小于该第一半导体材料层的介电常数；沿该栅长方向，在预设的源漏区域形成源极和漏极，该源极和漏极通过该绝缘凹槽与该牺牲层隔离。这样，后续去除该牺牲层后，在牺牲层的位置填充的栅极材料(即介电常数较大的材料)也能够通过绝缘凹槽与源极和漏极隔离，从而减小因源极和漏极直接与栅极材料接触形成的寄生电容等寄生参数，提高场效应晶体管的性能和可靠性。
在一种可能的设计方式中，沿该栅长方向，沿栅长方向，去除第一半导体材料层中除牺牲层以外的区域，形成绝缘凹槽，包括：沿栅长方向，对第一半导体材料层进行选择性氧化工艺，使得第一半导体材料层中除牺牲层以外的区域被氧化，形成绝缘凹槽，此时，绝缘凹槽中填充的介质为第一半导体材料层的氧化物，其介电常数一般比较低，因此，该绝缘凹槽可以隔离后续形成的源极(或漏极)与填充牺牲层的High-K(高介电常数)介质材料，避免源极(或漏极)直接与High-K介质材料接触后产生寄生电容。
在一种可能的设计方式中，沿该栅长方向，沿栅长方向，去除第一半导体材料层中除牺牲层以外的区域，形成绝缘凹槽，包括：沿栅长方向，对第一半导体材料层进行选择性刻蚀工艺，使得第一半导体材料层中除牺牲层以外的区域被去除，形成绝缘凹槽。此时，绝缘凹槽内填充的介质为介电常数较低的空气，因此，该绝缘凹槽可以隔离后续形成的源极(或漏极)与填充牺牲层的High-K介质材料，避免源极(或漏极)直接与High-K介质材料接触后产生寄生电容。
在一种可能的设计方式中，在形成上述绝缘凹槽之后，还包括：在该绝缘凹槽内填充介电常数小于3.9的介质材料。此时，绝缘凹槽内被介电常数小于3.9的介质材料，即Low-K介质材料填充，因此，该绝缘凹槽可以隔离后续形成的源极(或漏极)与填充牺牲层的High-K介质材料，避免源极(或漏极)直接与High-K介质材料接触后产生寄生电容。
在一种可能的设计方式中，在该绝缘凹槽内填充介电常数小于3.9的介质材料之前，还包括：沿该栅长方向，通过ALD工艺在该绝缘凹槽的表层上形成刻蚀停止层。这样，后续在去除牺牲层时，刻蚀停止层可以阻挡刻蚀液刻蚀到除牺牲层以外的区域。
在一种可能的设计方式中，在沿该栅长方向，在预设的源漏区域形成源极和漏极之后，还包括：去除该假栅结构和该牺牲层；沿栅结构截面方向，调整该第二半导体材料层的厚度，该栅结构截面方向与该栅长方向垂直。由于场效应晶体管的沟道效应与第二半导体材料层的厚度是相关的，因此，通过调整第二半导体材料层的厚度，可以改善场效应晶体管的沟道效应，实现沟道效应的灵活调节。
在一种可能的设计方式中，调整该第二半导体材料层的厚度，包括：通过刻蚀工艺，将该第二半导体材料层的厚度从8nm减小至4nm。
在一种可能的设计方式中，在沿栅结构截面方向，调整该第二半导体材料层的厚度之后，还包括：通过RMG工艺，在已去除的该假栅结构和该牺牲 层的位置形成栅极。
在一种可能的设计方式中，在半导体衬底上形成具有超晶格特征的支撑结构，包括：在半导体衬底上依次生长第一半导体材料层和第二半导体材料层的周期性超晶格结构，该第一半导体材料层和该第二半导体材料层的厚度均小于50nm；对该超晶格结构进行刻蚀，形成鳍状的支撑结构。
在一种可能的设计方式中，沿着隔离层与支撑结构的交界形成覆盖支撑结构的假栅结构，包括：在裸露出的支撑结构上形成氧化层；在氧化层上形成覆盖该支撑结构的假栅结构。
在一种可能的设计方式中，该假栅结构在栅结构截面方向的长度小于该隔离层的长度，其中，在该隔离层上形成包裹该支撑结构的假栅结构之后，还包括：在该假栅结构的外围沉积绝缘层，该绝缘层的侧壁与该隔离层的侧壁齐平。
第二方面，本发明的实施例提供一种场效应晶体管，包括源极和漏极，该源极与漏极之间的沟道内设置有栅极，栅极通过绝缘凹槽与源极和漏极隔离，该绝缘凹槽内填充的介质的介电常数小于第一半导体材料层的介电常数，该第一半导体材料层为制作场效应晶体管时形成的一种超晶格材料薄膜。
本发明的这些方面或其他方面在以下实施例的描述中会更加简明易懂。
附图说明
图1为现有技术中场效应晶体管的制作原理示意图一；
图2为现有技术中场效应晶体管的制作原理示意图二；
图3为本发明实施例提供的一种场效应晶体管的结构示意图；
图4为本发明实施例提供的一种场效应晶体管的制作方法的流程示意图；
图5为本发明实施例提供的一种场效应晶体管的制作原理示意图一；
图6为本发明实施例提供的一种场效应晶体管的制作原理示意图二；
图7为本发明实施例提供的一种场效应晶体管的制作原理示意图三；
图8为本发明实施例提供的一种场效应晶体管的制作原理示意图四；
图9为本发明实施例提供的一种场效应晶体管的制作原理示意图五；
图10为本发明实施例提供的一种场效应晶体管的制作原理示意图六；
图11为本发明实施例提供的一种场效应晶体管的制作原理示意图七；
图12为本发明实施例提供的一种场效应晶体管的制作原理示意图八；
图13为本发明实施例提供的一种场效应晶体管的制作原理示意图九；
图14为本发明实施例提供的一种场效应晶体管的制作原理示意图十；
图15为本发明实施例提供的一种场效应晶体管的制作原理示意图十一；
图16为本发明实施例提供的一种场效应晶体管的制作原理示意图十二；
图17为本发明实施例提供的一种场效应晶体管的制作原理示意图十三。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行详细描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。
本发明的实施例提供一种场效应晶体管，该场效应晶体管可以为MOSFET，例如，堆叠环栅纳米线晶体管(Stacked Gate-All-Around Nanowire Transistor)，鳍式场效应晶体管(Fin Field-Effect Transistor，FinFET)等，也可以为隧穿场效应晶体管(TFET，Tunneling Field Effect Transistor)等，本发明实施例对此不作限制。
另外，为方便阐述本发明的实施例提供一种场效应晶体管及其制作方法，首先对场效应晶体管的各个截面方向进行解释，如图3所示，为本发明的实施例提供的一种场效应晶体管的结构示意图，其中，半导体衬底31上设置有栅极32，栅极32的两侧为源漏区域，分别设置有鳍状的源极33和漏极34，那么，沿XX’方向用于指示场效应晶体管的栅长方向，即场效应晶体管中载流子的输运方向；沿YY’方向用于指示场效应晶体管的栅结构(Gate structure)截面方向，栅长方向与栅结构截面方向互相垂直。
需要说明的是，图3中仅示出了场效应晶体管内一组栅极32，源极33和漏极34的结构，可以理解的是，场效应晶体管内还可以包括多组结构类似的栅极，源极和漏极，本发明实施例对此不作限制。
那么，基于图3所示的栅长方向和栅结构截面方向，本发明的实施例提供一种场效应晶体管的制作方法，如图4所示，包括：
401、在半导体衬底上形成具有超晶格特征的支撑结构，该支撑结构包括交替设置的第一半导体材料层和第二半导体材料层，支撑结构的两侧设置有隔离层。
其中，该半导体衬底可以为SOI(Silicon-On-Insulator，绝缘衬底上的硅)衬底、体硅衬底、ETSOI(Extremely Thin SOI，超薄SOI)衬底、SGOI(SiGe-On-Insulator，绝缘衬底上的锗硅)衬底或IIIV-OI(IIIV-On-Insulator，绝缘衬底上的IIIV族化合物)衬底等，本发明实施例对此不作限制。
具体的，如图5所示(图5中的(a)为沿栅长方向的截面示意图，图5中的(b)为沿栅结构截面方向的截面示意图)，可以先在半导体衬底51上交替生长第一半导体材料层52和第二半导体材料层53的周期性超晶格(superlattice)结构，其中，超晶格结构是指两种不同组元以几个纳米到几十个纳米的薄层交替生长并保持严格周期性的多层膜。
示例性的，第一半导体材料层52和第二半导体材料层53的厚度均可小于50nm，当第一半导体材料层52为硅材料时，第二半导体材料层53可以为锗硅材料。
进而，可以对上述第一半导体材料层52和第二半导体材料层53组成的超晶格结构进行刻蚀，形成如图6所示的支撑结构61，示例性的，该支撑结构61可以呈鳍状设置在半导体衬底51上。其中，图6中的(a)为沿栅长方向的截面示意图，图6中的(b)为沿栅结构截面方向的截面示意图。
进一步地，如图7所示，可继续通过CMP(chemical mechanical flattening，化学机械平坦化)工艺和回刻(Recess)工艺在支撑结构61的两侧形成隔离层71。
可选的，隔离层71的厚度与刻蚀掉的半导体衬底51的厚度相同。
示例性的，隔离层71具体可以为氧化硅等氧化物制成的，本发明实施例对此不作限制。
402、沿着隔离层与支撑结构的交界形成覆盖支撑结构的假栅结构，该假栅结构在栅长方向的长度小于第一半导体材料层在栅长方向的长度。
如图8所示，在形成隔离层71后，可进一步在隔离层71上形成覆盖支撑结构61的假栅(Poly Gate)结构81，此时，支撑结构61被镶嵌在隔离层71与假栅结构81形成的间隙中。
其中，如图9中的(a)所示，该假栅结构81在栅长方向的长度小于第一半导体材料层52在栅长方向的长度。其中，图9中的(a)为沿栅长方向的截面示意图，图9中的(b)为沿栅结构截面方向的截面示意图。
示例性的，假栅结构81具体可以为多晶硅或者非晶硅材料制成的，本发明实施例对此不作限制。
具体的，可以先在裸露出的支撑结构61上形成氧化层(Dummy Oxide)；再在氧化层上形成包裹支撑结构61的假栅结构81。
进一步地，如图10所示，还可以在假栅结构81的外围沉积绝缘层91，使绝缘层91的侧壁在栅结构截面方向上与隔离层71的侧壁对齐，其中，图10中的(a)为沿栅长方向的截面示意图，图10中的(b)为沿栅结构截面方向的截面示意图。
另外，在形成假栅结构81时，尽可能的保证刻蚀的各向异性，并调节使多晶硅:氧化硅的刻蚀选择比例尽可能的高，从而形成形貌较为陡直的假栅结构81，形貌较为陡直的假栅结构81有利于后续形成绝缘层91时，能够较好地使得假栅结构81与绝缘层91贴合，从而保证假栅结构81被有效的隔离。
403、沿栅长方向，去除第一半导体材料层中除牺牲层以外的区域，形成绝缘凹槽。
上述牺牲层为第一半导体材料层52中，假栅结构81沿目标方向(该目标方向为垂直于半导体衬底51底面的方向，即假栅结构81在第一半导体材料层52的正投影方向)的投影区域。
其中，绝缘凹槽中填充的介质的介电常数小于上述第一半导体材料层的介电常数。
在一种可能的设计方式中，在栅长方向上，可以先沿绝缘层91的侧壁对第一半导体材料层52和第二半导体材料层53进行刻蚀，使第一半导体材料层52和第二半导体材料层53的侧壁与绝缘层91对齐(如图11中的(a)所示)。其中，图11中的(a)为沿栅长方向的截面示意图，图11中的(b)为沿栅结构截面方向的截面示意图。
进而，对图11中的(a)中所示的第一半导体材料层52进行选择性氧化(selectively oxidization)工艺，使得第一半导体材料层52中，假栅结构81在第一半导体材料层52的投影区域以外的区域被氧化，被氧化的这部分空间形成了如图12中的(a)所示的绝缘凹槽101，而假栅结构81在第一半导体 材料层52的投影区域没有被氧化，形成如图12中的(a)所示的牺牲层102。此时，绝缘凹槽101内被第一半导体材料层52的氧化物(例如，氧化硅)填充，而第一半导体材料层52的氧化物的介电常数一般比较低，因此，该绝缘凹槽101可以隔离后续形成的源极(或漏极)与填充牺牲层102的栅极材料，例如，High-K(高介电常数)介质材料，避免后续形成的源极(或漏极)直接与栅极材料形成的栅极接触后产生寄生电容。其中，图12中的(a)为沿栅长方向的截面示意图，图12中的(b)为沿栅结构截面方向的截面示意图。
示例性的，当第一半导体材料层52为硅时，进行上述选择性氧化工艺后，在绝缘凹槽101内形成氧化硅，氧化硅的介电常数约为3.9，而硅的介电常数约为11.5，远小于氧化硅的介电常数。
在另一种可能的设计方式中，沿栅长方向，可以对图11中的(a)中所示的第一半导体材料层52进行选择性刻蚀(selectively removal)工艺，使得第一半导体材料层52中，假栅结构81在第一半导体材料层52的投影区域以外的区域被去除，形成如图13中的(a)所示的绝缘凹槽101，而假栅结构81在第一半导体材料层52的投影区域被保留，形成如图13中的(a)所示的牺牲层102。此时，填充绝缘凹槽101的为空气。空气作为一种介电常数较低的介质(空气的介电常数约为1)，可以隔离后续形成的源极(或漏极)与填充牺牲层102的栅极材料，从而避免后续形成的源极(或漏极)直接与栅极材料形成的栅极接触后产生寄生电容。其中，图13中的(a)为沿栅长方向的截面示意图，图13中的(b)为沿栅结构截面方向的截面示意图。
另外，在形成图13中的(a)所示的绝缘凹槽101之后，如图14(图14中的(a)为沿栅长方向的截面示意图，图14中的(b)为沿栅结构截面方向的截面示意图)所示，沿栅长方向，可以通过ALD(Atomic Layer Deposition，原子层沉积)工艺在绝缘凹槽101的表层上形成刻蚀停止层111。这样，后续在去除牺牲层102时，刻蚀停止层111可以阻挡刻蚀液刻蚀到除牺牲层102以外的区域。
进一步地，仍如图14中的(a)所示，可在绝缘凹槽101内填充介电常数小于3.9的介质材料，例如，Low-K(低介电常数)介质材料121。使绝缘凹槽101内具有更低的K(介电常数)值，从而避免后续形成的源极(和漏极)与填充牺牲层102的栅极材料形成的栅极直接接触产生寄生电容。
通常，可以将介电常数在小于2.5以内的介质材料作为Low-K介质材料，例如，SiCOH(掺氢的氧化硅碳)等。
类似的，可以将介电常数在大于4的介质材料作为High-K介质材料，例如，HfO2(二氧化铪)等。
其中，本发明实施例中所述的介电常数(ε)，是指相对介电常数(εr)与真空中绝对介电常数(ε0)乘积，即ε＝εr*ε0，ε0＝8.85*10-12F/m。
示例性的，上述第一半导体材料层52或第二半导体材料层53的介电常数约为10-12。
404、沿栅长方向，在预设的源漏区域形成源极和漏极，源极和漏极通过 绝缘凹槽与牺牲层隔离。
以图14所示的绝缘凹槽101内填充Low-K介质材料121为例，在步骤404中，可利用选择性外延技术，在预设的源漏区域外延生长硅或锗硅等材料，进而，通过掺杂工艺使源漏区域具有一定的掺杂浓度，形成如图15(图15中的(a)为沿栅长方向的截面示意图，图15中的(b)为沿栅结构截面方向的截面示意图)所示源极131和漏极132。
此时，源极131和漏极132通过绝缘凹槽101与牺牲层102隔离。后续，当去除牺牲层102后，可以向牺牲层102的位置填充High-K介质材料以形成栅极，那么，源极131和漏极132仍然可通过绝缘凹槽101与栅极隔离，从而降低源极131和漏极132直接与栅极接触产生的寄生电容。
另外，仍如图15中的(a)所示，在形成源极131和漏极132时，杂质原子会扩散到第二半导体材料层53，形成扩展区域133，而扩展区域的大小与场效应晶体管的寄生电阻有关，当扩展区域越大时，寄生电阻的值越小，当扩展区域越小时，寄生电阻的值越大。
因此，为了减小寄生电阻，可以将第二半导体材料层53的厚度设置的尽可能的大，从而形成较大的扩展区域。但是，当第二半导体材料层53的厚度越大时，会降低场效应晶体管对短沟道效应(Short-channel effects)的抑制能力，例如，使得场效应晶体管的漏电流增大，对此，可通过下述步骤406解决上述问题。
405、去除假栅结构和牺牲层。
如图16所示(图16中的(a)为沿栅长方向的截面示意图，图16中的(b)为沿栅结构截面方向的截面示意图)，可通过刻蚀工艺去除上述假栅结构81和牺牲层102。
406、沿栅结构截面方向，调整第二半导体材料层的厚度。
在步骤406中，如图16中的(b)所示，可调整沟道区域内第二半导体材料层53的厚度，例如，调整前第二半导体材料层53的厚度T1＝8nm，可通过刻蚀等工艺，将第二半导体材料层53的厚度减小至T2，T2＝4nm，这样，由于场效应晶体管的沟道效应与第二半导体材料层53的厚度是相关的，因此，通过调整第二半导体材料层53的厚度，可以改善场效应晶体管的短沟道效应，从而在不增加寄生电阻的情况下，实现短沟道效应的灵活调节。
407、通过RMG工艺，在已去除的假栅结构和牺牲层的位置形成栅极。
后续，可沿用现有技术，通过RMG(Replacement Metal Gate，替代栅)工艺，在已去除的假栅结构81和牺牲层102的位置形成如图17所示的栅极151(该栅极151中至少包括两层结构，一层是High-K介质材料，另外一层是具有特定功函数的金属材料)，最终形成场效应晶体管，其中，图17中的(a)为沿栅长方向的截面示意图，图17中的(b)为沿栅结构截面方向的截面示意图。
如图17所示，在形成的场效应晶体管中，栅极151中原本设置第一半导体材料层51的位置，可通过绝缘凹槽101内介电常数较低的材料与源极131 (或漏极132)隔离，而栅极151中原本填充有假栅结构81的位置，可通过绝缘层91与源极131(或漏极132)隔离，也就是说，栅极151通过绝缘凹槽101和绝缘层91，几乎完全与源极131(或漏极132)隔离，从而降低了整个场效应晶体管的寄生电容，提高场效应晶体管的性能和可靠性。
另外，本发明实施例还提供一种场效应晶体管，该场效应晶体管可以为MOSFET或隧穿场效应晶体管等，本发明实施例对此不作限制。
其中，本发明实施例还提供的场效应晶体管的制作方法可参见上述实施例中步骤401-407的相关内容，故此处不再赘述。
示例性的，如图17中的(a)所示，在本发明实施例提供的场效应晶体管中，栅极151设置在源极131与漏极132之间形成的沟道内，栅极151并不是与源极131(或漏极132)直接接触，而是通过绝缘凹槽101与源极131(或漏极132)隔离，而绝缘凹槽101内填充有介电常数较低的材料，因此，可避免栅极151与源极131(或漏极132)直接接触产生的寄生电容，提高场效应晶体管的性能和可靠性。
至此，本发明的实施例提供一种场效应晶体管及其制作方法，在该制作方法中，先在半导体衬底上形成具有超晶格特征的支撑结构，该支撑结构包括交替设置的第一半导体材料层和第二半导体材料层，该支撑结构的两侧设置有隔离层；进而，在隔离层上形成覆盖该支撑结构的假栅结构，该假栅结构在栅长方向的长度小于上述第一半导体材料层在栅长方向的长度；那么，沿栅长方向，可去除第一半导体材料层中除牺牲层以外的区域，形成绝缘凹槽，而第一半导体材料层中除牺牲层之外的区域形成了绝缘凹槽，该牺牲层为假栅结构沿目标方向(即垂直于设置有支撑结构的隔离层表面的方向)在第一半导体材料层的投影区域，该绝缘凹槽中所填充的介质的介电常数小于第一半导体材料层的介电常数，因此，后续沿栅长方向在预设的源漏区域形成源极和漏极后，该源极和漏极可通过上述绝缘凹槽与填充牺牲层的栅极材料(例如，High-K介质材料)隔离，避免源极(或漏极)直接与栅极材料接触后产生寄生电容，从而降低了整个场效应晶体管的寄生电容，提高场效应晶体管的性能和可靠性。
本领域技术人员应该可以意识到，在上述一个或多个示例中，本发明所描述的功能可以用硬件、软件、固件或它们的任意组合来实现。当使用软件实现时，可以将这些功能存储在计算机可读介质中或者作为计算机可读介质上的一个或多个指令或代码进行传输。计算机可读介质包括计算机存储介质和通信介质，其中通信介质包括便于从一个地方向另一个地方传送计算机程序的任何介质。存储介质可以是通用或专用计算机能够存取的任何可用介质。
以上所述的具体实施方式，对本发明的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本发明的具体实施方式而已，并不用于限定本发明的保护范围，凡在本发明的技术方案的基础之上，所做的任何修改、等同替换、改进等，均应包括在本发明的保护范围之内。

Claims (12)

  1. 一种场效应晶体管的制作方法，其特征在于，包括：
    在半导体衬底上形成具有超晶格特征的支撑结构，所述支撑结构包括交替设置的第一半导体材料层和第二半导体材料层，所述支撑结构的两侧设置有隔离层；
    沿着所述隔离层与所述支撑结构的交界形成覆盖所述支撑结构的假栅结构，所述假栅结构在栅长方向的长度小于所述第一半导体材料层在所述栅长方向的长度，所述栅长方向用于指示所述场效应晶体管中载流子的输运方向；
    沿所述栅长方向，去除所述第一半导体材料层中除牺牲层以外的区域，形成绝缘凹槽，所述牺牲层为所述第一半导体材料层中所述假栅结构沿目标方向的投影区域，所述绝缘凹槽中填充的介质的介电常数小于所述第一半导体材料层的介电常数，所述目标方向为垂直于所述半导体衬底底面的方向；
    沿所述栅长方向，在预设的源漏区域形成源极和漏极，所述源极和漏极通过所述绝缘凹槽与所述牺牲层隔离。
  2. 根据权利要求1所述的制作方法，其特征在于，沿所述栅长方向，去除所述第一半导体材料层中除牺牲层以外的区域，形成绝缘凹槽，包括：
    沿所述栅长方向，对所述第一半导体材料层进行选择性氧化工艺，使得所述第一半导体材料层中除所述牺牲层以外的区域被氧化，形成所述绝缘凹槽，其中，所述绝缘凹槽中填充的介质为所述第一半导体材料层的氧化物。
  3. 根据权利要求1所述的制作方法，其特征在于，沿所述栅长方向，去除所述第一半导体材料层中除牺牲层以外的区域，形成绝缘凹槽，包括：
    沿所述栅长方向，对所述第一半导体材料层进行选择性刻蚀工艺，使得所述第一半导体材料层中除所述牺牲层以外的区域被去除，形成所述绝缘凹槽。
  4. 根据权利要求3所述的制作方法，其特征在于，在形成所述绝缘凹槽之后，还包括：
    在所述绝缘凹槽内填充介电常数小于3.9的介质材料。
  5. 根据权利要求4所述的制作方法，其特征在于，在所述绝缘凹槽内填充介电常数小于3.9的介质材料之前，还包括：
    沿所述栅长方向，通过原子层沉积ALD工艺在所述绝缘凹槽的表层上形成刻蚀停止层。
  6. 根据权利要求1-5中任一项所述的制作方法，其特征在于，在沿所述栅长方向，在预设的源漏区域形成源极和漏极之后，还包括：
    去除所述假栅结构和所述牺牲层；
    沿栅结构截面方向，调整所述第二半导体材料层的厚度，所述栅结构截面方向与所述栅长方向垂直。
  7. 根据权利要求6所述的制作方法，其特征在于，调整所述第二半导体材料层的厚度，包括：
    通过刻蚀工艺，将所述第二半导体材料层的厚度从8nm减小至4nm。
  8. 根据权利要求6或7所述的制作方法，其特征在于，在沿栅结构截面 方向，调整所述第二半导体材料层的厚度之后，还包括：
    通过替代栅RMG工艺，在已去除的所述假栅结构和所述牺牲层的位置形成栅极。
  9. 根据权利要求1-8中任一项所述的制作方法，其特征在于，在半导体衬底上形成具有超晶格特征的支撑结构，包括：
    在半导体衬底上交替生长第一半导体材料层和第二半导体材料层的周期性超晶格结构，所述第一半导体材料层和所述第二半导体材料层的厚度均小于50nm；
    对所述超晶格结构进行刻蚀，形成鳍状的所述支撑结构。
  10. 根据权利要求1-9中任一项所述的制作方法，其特征在于，沿着所述隔离层与所述支撑结构的交界形成覆盖所述支撑结构的假栅结构，包括：
    在裸露出的支撑结构上形成氧化层；
    在所述氧化层上形成覆盖所述支撑结构的假栅结构。
  11. 根据权利要求1-10中任一项所述的制作方法，其特征在于，所述假栅结构在栅结构截面方向的长度小于所述隔离层的长度，
    其中，在所述隔离层上形成包裹所述支撑结构的假栅结构之后，还包括：
    在所述假栅结构的外围沉积绝缘层，所述绝缘层的侧壁与所述隔离层的侧壁齐平。
  12. 一种场效应晶体管，其特征在于，包括源极和漏极，所述源极与所述漏极之间的沟道内设置有栅极，所述栅极通过绝缘凹槽与所述源极和漏极隔离，所述绝缘凹槽内填充的介质的介电常数小于第一半导体材料层的介电常数，所述第一半导体材料层为制作所述场效应晶体管时形成的一种超晶格材料薄膜。
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