WO2018094579A1 - 电容感测电路及指纹辨识系统 - Google Patents

电容感测电路及指纹辨识系统 Download PDF

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Publication number
WO2018094579A1
WO2018094579A1 PCT/CN2016/106826 CN2016106826W WO2018094579A1 WO 2018094579 A1 WO2018094579 A1 WO 2018094579A1 CN 2016106826 W CN2016106826 W CN 2016106826W WO 2018094579 A1 WO2018094579 A1 WO 2018094579A1
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Prior art keywords
digital
analog conversion
coupled
code
analog
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Ceased
Application number
PCT/CN2016/106826
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English (en)
French (fr)
Inventor
梁佑安
杨孟达
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Shenzhen Goodix Technology Co Ltd
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Shenzhen Goodix Technology Co Ltd
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Application filed by Shenzhen Goodix Technology Co Ltd filed Critical Shenzhen Goodix Technology Co Ltd
Priority to KR1020177037727A priority Critical patent/KR101983618B1/ko
Priority to PCT/CN2016/106826 priority patent/WO2018094579A1/zh
Priority to EP16904840.2A priority patent/EP3351948B1/en
Priority to CN201680002048.3A priority patent/CN108700621B/zh
Priority to US15/841,328 priority patent/US10380401B2/en
Publication of WO2018094579A1 publication Critical patent/WO2018094579A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12—Fingerprints or palmprints
    • G06V40/13—Sensors therefor
    • G06V40/1306—Sensors therefor non-optical, e.g. ultrasonic or capacitive sensing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
    • G11C27/02—Sample-and-hold arrangements
    • G11C27/024—Sample-and-hold arrangements using a capacitive memory element
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/94—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the way in which the control signals are generated
    • H03K17/96—Touch switches
    • H03K17/962—Capacitive touch switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/94—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the way in which the control signals are generated
    • H03K17/96—Touch switches
    • H03K17/962—Capacitive touch switches
    • H03K17/9622—Capacitive touch switches using a plurality of detectors, e.g. keyboard
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
    • H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/74—Simultaneous conversion
    • H03M1/80—Simultaneous conversion using weighted impedances
    • H03M1/802—Simultaneous conversion using weighted impedances using capacitors, e.g. neuron-mos transistors, charge coupled devices
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/94—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00 characterised by the way in which the control signal is generated
    • H03K2217/96—Touch switches
    • H03K2217/9607—Capacitive touch switches
    • H03K2217/96071—Capacitive touch switches characterised by the detection principle
    • H03K2217/960725—Charge-transfer
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/94—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00 characterised by the way in which the control signal is generated
    • H03K2217/96—Touch switches
    • H03K2217/9607—Capacitive touch switches
    • H03K2217/960735—Capacitive touch switches characterised by circuit details
    • H03K2217/96074—Switched capacitor

Definitions

  • the patent application relates to a circuit structure, and in particular to a capacitance sensing circuit and a fingerprint identification system capable of generating a digital output.
  • a fingerprint sensing system uses a capacitive sensing circuit to accept finger contact, and a capacitive sensing circuit is used to receive a finger contact and form a contact capacitance with the finger.
  • the capacitive sensing circuit can measure the capacitance of the contact capacitor. Converted into an analog voltage signal, the analog voltage signal needs to be converted into a digital voltage signal, and then transmitted to the fingerprint judgment module at the back end to determine the Finger Ridge or Finger Valley corresponding to the fingerprint sensing circuit.
  • the analog voltage signal is converted to a digital voltage signal by an Analog to Digital Convertor (ADC).
  • ADC Analog to Digital Convertor
  • the analog-to-digital converter has a complicated circuit structure and occupies a large circuit area while increasing production cost and consuming high power.
  • the main purpose of the present patent application is to provide a capacitance sensing circuit and a fingerprint identification system with simple circuit configuration.
  • the present patent application provides a capacitance sensing circuit for sensing a contact capacitance, comprising an integrating circuit including an integrating input coupled to the contact capacitor, the integral input having An input voltage is used to output an output voltage; a comparator includes a first input coupled to the integrated output; and a second input for receiving a reference voltage a forward digital-to-analog conversion unit coupled to the integral input terminal; a negative digital-to-analog conversion unit coupled to the integral input terminal; a control circuit coupled to a comparison output of the comparator And the logic circuit is coupled to the comparison output for generating a first code in an integration interval. And generating a second code in a comparison interval, the logic circuit outputting an output code according to the first code and the second code, where the output code is related to a capacitance of the contact capacitor .
  • the forward digital-to-analog conversion unit includes a plurality of forward digital-to-analog conversion capacitors coupled to the integral input terminal; and a plurality of first digital-to-analog conversion switches, one end of which is coupled to the plurality of positive a digital-to-analog conversion capacitor, the other end receiving a positive voltage; and a plurality of second digital-to-analog conversion switches, one end of which is coupled to the plurality of forward digital-to-analog conversion capacitors, and the other end of which is coupled to a ground terminal;
  • the digital-to-analog conversion unit includes a plurality of negative-to-digital-to-analog conversion capacitors coupled to the integral input terminals, and a plurality of third digital-to-analog conversion switches coupled to the plurality of negative-to-digital analog-to-analog conversion capacitors at one end.
  • the other end receives a positive voltage; and a plurality of fourth digital-to-analog conversion switches, one end of which is coupled to the plurality of negative-to-digital-to-analog conversion capacitors, and the other end of which is coupled to a ground end; wherein the plurality of first A digital to analog switch, the plurality of second digital to analog switches, the plurality of third digital to analog switches, and the plurality of fourth digital to analog switches are controlled by the control circuit.
  • a plurality of positive digital-to-analog conversion capacitance values of the plurality of positive digital-to-analog conversion capacitors have an exponential relationship
  • a plurality of negative-negative digital-to-analog conversion capacitance values of the plurality of negative digital-to-analog conversion capacitances There is an exponential relationship between them.
  • the control circuit controls the plurality of first digital-to-analog conversion switches and the plurality of second digital-to-analog conversion switches of the forward digital-to-analog conversion unit such that when the comparison When the device is in a state of transition, the output voltage is increased by a first specific value.
  • the logic circuit accumulates a cumulative number of transitions of the comparator and generates the first code associated with the cumulative number of transitions.
  • the control circuit controls the plurality of first digital-to-analog conversion switches and the plurality of second digital-to-analog conversion switches of the forward digital-to-analog conversion unit such that the plurality of positive Receiving the positive voltage to the digital-to-analog conversion capacitor; in the sampling interval, the control circuit controls the plurality of first digital-to-analog conversion switches of the negative-to-digital-to-analog conversion unit and the plurality of second numbers And a mode switch, wherein the plurality of negative-to-digital-to-analog conversion capacitors are coupled to the ground.
  • the control circuit controls the plurality of first digital-to-analog conversion switches, the plurality of second digital-to-analog conversion switches, the plurality of third digital-to-analog conversion switches, and the plurality A fourth digital to analog switch to adjust the input voltage.
  • the comparison interval includes a plurality of comparison subintervals, and in a comparison subinterval of the plurality of comparison subintervals, the comparator result produces a comparison result corresponding to the comparison subinterval.
  • the logic circuit generates the second code based on a plurality of comparison results corresponding to the plurality of comparison subintervals.
  • the control circuit controls the plurality of first digital to analog conversion switches, the plurality of The dimodic mode changeover switch, the plurality of third digital to analog conversion switches, and the plurality of fourth digital to analog conversion switches cause the input voltage to drop by a second specific value in the next comparison subinterval.
  • the control circuit controls the plurality of first digital to analog conversion switches, the plurality of The binary to digital conversion switch, the plurality of third digital to analog conversion switches, and the plurality of fourth digital to analog conversion switches cause the input voltage to rise by a third specific value in the next comparison subinterval.
  • the output code is an addition result of the first code to the left (N-1) bits and the second code, where N represents the number of bits of the second code.
  • the capacitive sensing circuit further includes a sample and hold circuit coupled to the contact capacitor and the integral input.
  • the sampling and holding circuit includes a first switch, one end of which receives a positive voltage and the other end of which is coupled to the contact capacitor, and a second switch that has one end coupled to the contact capacitor and the other end coupled At the integration input; wherein, at a first time, the first switch is turned on and the second switch is turned off; and at a second time, the first switch is turned off and the second The switch is turned on.
  • the integrating circuit includes an amplifier coupled between the integrating input and the integrated output; an integrating capacitor coupled to the integrating input; a third switch coupled to the An integrating capacitor and the integrated output terminal; and a fourth switch having one end coupled to the integrating capacitor and the third switch, and the other end receiving a common mode voltage.
  • the reference voltage is equal to the common mode voltage.
  • the integration circuit further includes a fifth switch coupled between the integration input and the integration output.
  • the present application further provides a capacitive sensing circuit, comprising a plurality of pixel circuits for forming a plurality of contact capacitors by one finger; a capacitive sensing circuit coupled to the plurality of pixel circuits for sensing the a plurality of contact capacitors, the capacitance sensing circuit comprising an integrating circuit comprising an integrating input, the integrating input having an input voltage; and an integrating output for outputting an output voltage; a comparator comprising a first input end coupled to the integral output end; and a second input end for receiving a reference voltage; a forward digital to analog conversion unit coupled to the integral input end; a negative direction number a mode conversion unit coupled to the integration input terminal; a control circuit coupled to a comparison output of the comparator for controlling the forward digital to analog conversion unit and the negative digital to analog conversion unit And a logic circuit coupled to the comparison output for generating a first code in an integration interval and generating a second code in a comparison interval, the logic circuit root The first code and the second code, outputting
  • the capacitive sensing circuit provided by the patent application can convert the capacitance value in the contact capacitance into a digital signal, which has the advantages of simple circuit structure, small circuit area, low cost, low power consumption and low delay waiting time.
  • FIG. 1 is a schematic diagram of a capacitive sensing circuit according to a portion of the present application.
  • FIG. 2 is a waveform diagram of an input voltage and an output voltage in some embodiments of the present patent application.
  • FIG. 3 is a schematic diagram of a first code, a second code, and an output code in some embodiments of the present patent application.
  • FIG. 4 is a schematic diagram of a fingerprint identification system according to a part of the present patent application.
  • the capacitive sensing circuit of the present application is used to sense a contact capacitance, which can directly output an output code related to the capacitance value without requiring an analog-to-digital converter (ADC) at the back end to simulate the capacitance value.
  • ADC analog-to-digital converter
  • the signal is converted to an output code.
  • FIG. 1 is a schematic diagram of a capacitive sensing circuit 10 of the present application.
  • the capacitance sensing circuit 10 is used to sense a contact capacitance Cf, and the capacitance sensing circuit 10 can directly output an output code ctotoal related to the capacitance value of the contact capacitance Cf.
  • the capacitance sensing circuit 10 is coupled to a sample and hold circuit SH, and includes an integrating circuit 12, a comparator Comp, a forward digital to analog conversion unit 14a, and a negative digital to analog conversion unit 14b.
  • the integrating circuit 12 includes an integrating input terminal and an integral output terminal.
  • the integral input terminal forms an input voltage Vx, and the integrated output terminal outputs an output voltage Vo.
  • the sampling and holding circuit SH includes switches S1 and S2. One end of the switch S1 receives a positive voltage V DD , the other end of the switch S1 is coupled to the contact capacitor Cf, one end of the switch S2 is coupled to the contact capacitor Cf, and the other end of the switch S2 is coupled.
  • the integrating circuit 12 includes an amplifier Amp, an integrating capacitor C INT and switches S3, S4, and S5.
  • the amplifier Amp, the integrating capacitor C INT, and the switches S3 and S5 are all coupled between the integral input terminal and the integral output terminal of the integrating circuit 12.
  • the integrating capacitor C INT is connected in series with the switch S3 in series, and the switch S5 is connected in parallel with the sequence.
  • One end of the switch S4 is coupled to the integrating capacitor C INT and the switch S3, and the other end of the switch S4 receives a common mode voltage V CM .
  • a first input terminal of the comparator Comp is coupled to the integrated output terminal to receive an output voltage Vo
  • a second input terminal of the comparator Comp receives a reference voltage V R
  • the comparator Comp generates an output voltage Vo and a reference voltage
  • a comparison result q of V R is output to a comparison output of the comparator Comp.
  • the control circuit 16 is coupled to the comparison output of the comparator Comp for generating a plurality of control signals to control the forward digital to analog conversion unit 14a and the negative digital to analog conversion unit 14b.
  • the logic circuit 18 is coupled to the comparison output of the comparator Comp for generating a first code (Code) c 1 in an integration interval T INT and generating a second code c in a comparison interval T CP 2 , the logic circuit 18 can generate an output code ctotoal related to the capacitance value of the contact capacitance Cf according to the first code c 1 and the second code c 2 , wherein the first code c 1 , the second code c 2 and the output code c Totoal is a binary (Binary) signal, the details of which are detailed later.
  • the forward digital-to-analog conversion unit 14a includes forward digital-to-analog conversion capacitors C a0 to C aK , digital-to-analog conversion switches SV a0 to SV aK , and digital-to-analog conversion switches SG a0 to SG aK , and forward digital to analog conversion
  • the digital-to-analog switch SV ak is coupled to a first end of the digital-to-analog switch SG ak the forward digital to analog conversion capacitance C ak, a second end of the digital to analog converter to receive the positive switch voltage SV ak V DD, a second terminal coupled to a digital to analog converter connected to the switch SG ak is a ground terminal GND.
  • the negative digital to analog conversion unit 14b includes negative digital to analog conversion capacitors C b0 to C bK , digital to analog conversion switches SV b0 to SV bK , and digital to analog conversion switches SG b0 to SG bK , and negative digital to analog conversion capacitors .
  • the positive end of the digital-to-analog conversion capacitor C bk , the second end of the digital-to-analog switch SV bk receives a positive voltage V DD , and the second end of the digital-to-analog switch SG bk is coupled to a ground GND.
  • the digital-to-analog conversion switches SV a0 to SV aK , the digital-to-analog conversion switches SG a0 to SG aK , the digital-to-analog conversion switches SV b0 to SV bK , and the digital-to-analog conversion switches SG b0 to SG bK are all controlled by the control circuit 16 , in other words
  • the control circuit 16 can generate a plurality of control signals according to the comparison result q to control the forward digital to analog conversion unit 14a and the negative digital to analog conversion unit 14b.
  • the forward digital-to-analog conversion capacitors C a0 to C aK are arranged in accordance with the magnitude of the capacitance values (ie, C a0 ⁇ C a1 ⁇ ... ⁇ C aK or C b0 ⁇ C b1 ⁇ ... ⁇ C bK ).
  • FIG. 2 is a waveform diagram of an input voltage Vx and an output voltage Vo according to an embodiment of the present patent application.
  • T RST the capacitance sensing circuit 10 will clear the charge stored in the integrating capacitor C INT .
  • the switches S3, S5, the digital-to-analog switches SV a0 - SV aK , SG b0 - SG bK are conducting (ON), the digital-to-analog switches SG a0 - SG aK , SV b0 - SV bK
  • the input voltage Vx is equal to the output voltage Vo.
  • the input voltage Vx, the output voltage Vo, and the reference voltage V R Can be equal to the common mode voltage V CM .
  • the integration circuit 12 performs an integration operation on the charge stored in the contact capacitance Cf.
  • the switch S5 and the digital-to-analog switches SV b0 to SV bK , SG b0 SG SG bK may be open circuits , the switches S1 and S3 may be controlled by a clock signal CK1, and the switches S2 and S5 may be controlled for one time.
  • the pulse signal CK2 wherein the clock signal CK1 is at a high potential in a first half cycle of a clock cycle, and the clock signal CK2 is at a high potential in a second half cycle of the clock cycle.
  • the switch S1 in the first half cycle, the switch S1 is turned on and the switch S2 is turned off, the contact capacitor Cf is charged to the positive voltage V DD ; in the second half cycle, the switch S1 is turned off and the switch S2 is turned on, and stored in the contact capacitor Cf The charge flows to the integrating capacitor C INT , in other words, in the integration interval T INT , the output voltage Vo decreases with time.
  • the comparator Comp when the output voltage Vo is smaller than the reference voltage V R , the comparator Comp will be turned, and the control circuit 16 generates a control signal to control the digital-to-analog switches SV a0 ⁇ SV aK , SG a0 ⁇ SG aK , so that the output voltage Vo increases a specific voltage value V K (ie, the output voltage Vo increases to a voltage V R +V K ), and therefore, the value of the output voltage Vo will be limited between the voltage V R +V K and the voltage V R .
  • the logic circuit 18 can accumulate a cumulative number of transitions N CNT of the comparator Comp and generate a first code c 1 related to the cumulative number of transitions N CNT .
  • the output voltage Vo is less than the reference voltage V R at time t I1 , t I2 , resulting in the comparator Comp transition state, so the cumulative number of transitions N CNT is equal to 2
  • the logic circuit 18 generates a binary representation of the first code c 1 as the cumulative number of transitions N CNT , that is, the logic circuit 18 generates the first code c 1 to be 10.
  • the output voltage Vo has a sampled voltage value V SP .
  • control circuit 16 controls the digital-to-analog switches SV a0 to SV aK and SG a0 to SG aK such that the output voltage Vo is increased by the specific voltage value V K are described below.
  • the control circuit 16 controls the digital-to-analog switches SV a0 ⁇ SV aK to be turned on and in the first half of the clock cycle.
  • the second half of the cycle is turned off, and the control circuit 16 controls the digital-to-analog switches SG a0 to SG aK to be turned off during the first half of the clock period T and turned on during the second half of the clock period T.
  • the output voltage Vo can be increased to the voltage V R +V K when the output voltage Vo is decremented by integration so that the output voltage Vo is less than the reference voltage V R (in the instant pulse period T').
  • the value of the output voltage Vo will be limited between the voltage V R +V K and the voltage V R .
  • the capacitance sensing circuit 10 performs a sampling operation.
  • the digital-to-analog switch SV a0 to SV aK , the digital-to-analog switch SG b0 SG SG bK and the switch S4 can be turned on, the digital-to-analog switch SG a0 ⁇ SG aK , and the digital-to-analog switch SV b0 ⁇ SV bK and switches S3, S5 can be open.
  • the charge sharing effect can be generated between the integral capacitor C INT and the forward digital-to-analog conversion capacitors C a0 to C aK and the negative digital-to-analog conversion capacitors C b0 to C bK , resulting in the input voltage Vx being
  • the sampling interval T SP drops or rises, and the output voltage Vo also rises or falls.
  • the comparator Comp can generate a comparison result q corresponding to the sampling interval T SP as q SP (q SP can be a binary value), logic
  • the circuit 18 may generate a Most Significant Bit (MSB) of the second code c 2 according to q SP as q SP ' (q SP ' represents a reversal of q SP in terms of Boolean algebra/logical description , q SP 'is not q SP ).
  • MSB Most Significant Bit
  • the input voltage Vx decreases due to the charge sharing effect (ie, the input voltage Vx is smaller than the common mode voltage V CM ), because the amplifier Amp has a reverse amplification effect, the input A slight decrease in voltage Vx will cause the output voltage Vo to rise sharply (for example, the output voltage Vo rises sharply to a saturation voltage of the amplifier Amp, wherein the saturation voltage of the amplifier Amp can be a positive voltage V DD ), and the comparator Comp produces a comparison.
  • the control circuit 16 controls the digital-to-analog switches SV a0 to SV aK , SG a0 to SG aK , SV b0 to SV bK , and SG b0 to SG bK to adjust the input voltage Vx to approach the common Mode voltage V CM .
  • the comparison interval T CP can be divided into comparison sub-intervals T CP0 ⁇ T CPK , and in the comparison sub-interval T CP0 , the control circuit 16 controls the digital-to-analog conversion switches SV a0 , SG a0 , SV b0 according to the comparison result q SP , SG b0 causes the input voltage Vx to rise/fall, the output voltage Vo to fall/rise in the comparison subinterval T CP0 , and the comparator Comp produces a comparison result q corresponding to the comparison subinterval T CP0 as q 0 (q 0 is also a binary value), at this time, the logic circuit 18 generates a second significant bit (Second Significant Bit) of the second code c 2 according to q SP as q 0 ' (Similarly, q 0 ' represents a reverse of q 0 , that is, q 0 'non Q 0), wherein the second code c representative of the next most significant bits
  • the control circuit 16 controls the digital-to-analog switches SV a0 , SG a0 , SV b0 , SG b0 according to the comparison result q SP such that the input voltage Vx is compared.
  • the control circuit 16 controls the digital-to-analog switches SV ak , SG ak , SV bk , SG bk according to the comparison result q k-1 such that the input voltage Vx is allowed to rise/fall, the output voltage Vo is decreased/ risn in the comparison subinterval T CPk , and the comparator Comp produces a comparison result q corresponding to the comparison subinterval T CPk as q k (q k is also a binary value),
  • the logic circuit 18 generates a second code c 2 from the most significant bit to the right according to the comparison result q k , and the k+1th bit is q k ' (same reason, q k ' represents a reverse of q k , that is, q k 'is non-q k ), where the aforementioned right side represents the direction from the
  • the control circuit 16 controls the digital-to-analog switches SV a1 , SG a1 , SV b1 , and SG b1 according to the comparison result q 0 such that the input voltage Vx is compared.
  • the logic circuit 18 When the comparison interval T CP is terminated, the logic circuit 18 generates the second code c 2 to be 010.
  • the logic circuit 18 can generate an output code c related to the capacitance value of the contact capacitance Cf according to the first code c 1 and the second code c 2 . Totoal .
  • the logic circuit 18 may multiply the binary value represented by the first code c 1 by 2 N-1 (ie, shift the first code c 1 to the left ( After N-1) bits, the multiplication result (ie, the result after translation) is added to the second code c 2 , and the obtained addition result is the output code c totoal , and the output code c totoal represents The binary value is the capacitance value associated with the contact capacitance Cf.
  • the first code c 1 can be regarded as a coarse code (Coarse Code), which includes a component whose output code c totoal is more significant; and the second code c 2 can be regarded as a Fine Code.
  • the logic circuit 18 can generate an output code c totoal for the first code c 1 to shift left by 2 bits to the left and the second code c 2 , as shown in FIG. 3 .
  • the magnitude of the rise of the input voltage Vx in the comparison subinterval T CPk is related to the capacitance value of the forward digital-to-analog conversion capacitor C ak corresponding to the digital-to-analog switches SV ak and SG ak , and is input in the comparison sub-interval T CPk .
  • the magnitude of the voltage Vx rise is related to the capacitance value of the negative digital-to-analog conversion capacitor C bk corresponding to the digital-to-analog switches SV bk and SG bk , and the forward digital-to-analog conversion capacitors C a0 to C aK (or negative digital-to-analog conversion capacitors) C b0 to C bK )
  • the capacitance values are arranged from large to small
  • the magnitude of the rise/fall of the input voltage Vx decreases as k increases, and the input voltage gap voltage value Vx and the sampled V SP is also reduced as k increases, in other words, the control circuit 16 to the comparison by the control sub-interval T CPk DAC switch SV ak, SG ak, SV bk , SG bk
  • the input voltage Vx is adjusted to approximate the common mode voltage V CM .
  • the logic circuit 18 may generate the second code c 2 (ie, the fine code) according to the comparison result q generated by the comparator Comp in the sampling interval T SP and the comparison interval T CP , and according to the first code c 1 and the second
  • the code c 2 produces an output code c totoal , and therefore, the digital output code c totoal can represent the capacitance value of the contact capacitance Cf.
  • the remaining operational details of the forward digital-to-analog conversion unit 14a, the negative-to-digital-to-analog conversion unit 14b, the control circuit 16, and the logic circuit 18 in the sampling interval T SP and the comparison interval T CP are similar to a successive approximation register type simulation.
  • the SAR ADC is well known to those of ordinary skill in the art and will not be described here.
  • the present patent application uses the control circuit 16 to control the forward digital to analog conversion unit 14a and the negative digital to analog conversion unit 14b in the comparison interval T CP to adjust the input voltage Vx to approximate the common mode voltage V CM .
  • the comparison result q generated by the comparator Comp in the sampling interval T SP and the comparison interval T CP can be used to generate the second code c 2 (ie, the fine code), and thus, according to the first code c 1 and the second code c c totoal 2 output code generated by a digital signal, which may represent the capacitance value of the contact capacitance Cf.
  • the capacitance sensing circuit 10 can accurately convert the capacitance value of the contact capacitance Cf into a digital signal without using an analog to digital converter (ADC).
  • ADC analog to digital converter
  • the capacitance sensing circuit 10 In addition to the simple circuit structure, small circuit area, low cost, and low power consumption, the delay latency (Latency) required for the sampling interval T SP and the comparison interval T CP is further shortened.
  • FIG. 4 is a schematic diagram of a fingerprint identification system 40 according to an embodiment of the present application.
  • the fingerprint identification system 40 includes pixel circuits PC_1 - PC_N and a capacitance sensing circuit 10 , wherein the pixel circuits PC_1 - PC_N form a contact capacitance Cf_1 - Cf_N with the user's finger, and the capacitance sensing circuit 10 can be coupled to the pixel circuit
  • the sample-and-hold circuit SH included in PC_1 ⁇ PC_N (wherein the connection relationship between the capacitance sensing circuit 10 and the sample-and-hold circuit SH is the same as that of FIG.
  • each pixel circuit may include a top electrode MT and a shielding layer MS.
  • the top electrode MT is used to receive contact with a user's finger and form a contact capacitance with the user's finger.
  • the first code c 1 and the second code c 2 are not limited to a specific length (number of bits), that is, the lengths (number of bits) of the first code c 1 and the second code c 2 may be actually needed. Adjustment, for example, the first code c 1 may have 10 bits, the second code c 2 may have 3 bits, and the output code c totoal may have 12 bits.
  • the capacitive sensing circuit of the present patent application uses a forward digital-to-analog conversion unit and a negative-to-digital analog-to-analog conversion unit to adjust the input voltage in the sampling interval and the comparison interval to approximate the common mode voltage, and the comparator is in the sampling interval. And the comparison results produced in the comparison interval can be used to generate the detailed code.
  • the capacitance sensing circuit of the present patent application has the advantages of simple circuit structure, small circuit area, low cost, low power consumption, and low delay waiting time.

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Abstract

一种电容感测电路(10)，包括一积分电路(12)，包含有一积分输入端，耦接于接触电容(Cf)，所述积分输入端具有一输入电压(Vx)；以及一积分输出端，用来输出一输出电压(Vo)；一比较器(Comp)；一正向数模转换单元(14a)；一负向数模转换单元(14b)；一控制电路(16)，用来控制所述正向数模转换单元(14a)以及所述负向数模转换单元(14b)；以及一逻辑电路(18)，用来输出一输出码(ctotal)，所述输出码(ctotal)相关于所述接触电容(Cf)的一电容值。

Description

电容感测电路及指纹辨识系统 技术领域
本专利申请涉及电路结构，具体涉及一种可产生数字输出的电容感测电路及指纹辨识系统。
背景技术
随着科技日新月异，移动电话、数字相机、平板计算机、笔记本电脑等越来越多携带型电子装置已经成为了人们生活中必备的工具。由于携带型电子装置一般为个人使用，而具有一定的隐私性，因此其内部储存的数据，例如电话簿、相片、个人信息等等为私人所有。若电子装置一旦丢失，则这些数据可能会被他人所利用，而造成不必要的损失。虽然目前已有利用密码保护的方式来避免电子装置为他人所使用，但密码容易泄露或遭到破解，具有较低的安全性。并且，用户需记住密码才能使用电子装置，若忘记密码，则会带给使用者许多不便。因此，目前发展出利用个人指纹识别系统的方式来达到身份认证的目的，以提升数据安全性。
一般来说，指纹识别系统中利用一电容感测电路接受手指的接触，电容感测电路用来接受手指的接触并与手指之间形成一接触电容，电容感测电路可将接触电容的电容值转换成一模拟电压信号，模拟电压信号需转换成数字电压信号后，再传送至后端的指纹判断模块以判断电容感测电路对应于指纹的纹蜂(Finger Ridge)或纹谷(Finger Valley)。换句话说，模拟电压信号通过一模拟数字转换器(Analog to Digital Convertor，ADC)以转换成数字电压信号。然而，模拟数字转换器的电路结构复杂，且占据大幅电路面积，同时增加生产成本，且消耗较高功率。
发明内容
因此，本专利申请的主要目的即在于提供一种电路构造简单的电容感测电路及指纹辨识系统。
为了解决上述技术问题，本专利申请提供了一电容感测电路，用来感测一接触电容，包括一积分电路，包含有一积分输入端，耦接于所述接触电容，所述积分输入端具有一输入电压；以及一积分输出端，用来输出一输出电压；一比较器，包含有一第一输入端，耦接于所述积分输出端；以及一第二输入端，用来接收一参考电压；一正向数模转换单元，耦接于所述积分输入端；一负向数模转换单元，耦接于所述积分输入端；一控制电路，耦接于所述比较器的一比较输出端，用来控制所述正向数模转换单元以及所述负向数模转换单元；以及一逻辑电路，耦接于所述比较输出端，用来于一积分区间中，产生一第一码，并于一比较区间中，产生一第二码，所述逻辑电路根据所述第一码以及所述第二码，输出一输出码，所述输出码相关于所述接触电容的一电容值。
例如，所述正向数模转换单元包含有复数个正向数模转换电容，耦接于所述积分输入端；复数个第一数模转换开关，其一端耦接于所述复数个正向数模转换电容，另一端接收一正电压；以及复数个第二数模转换开关，其一端耦接于所述复数个正向数模转换电容，另一端耦接于一接地端；所述负向数模转换单元包含有复数个负向数模转换电容，耦接于所述积分输入端；复数个第三数模转换开关，其一端耦接于所述复数个负向数模转换电容，另一端接收一正电压；以及复数个第四数模转换开关，其一端耦接于所述复数个负向数模转换电容，另一端耦接于一接地端；其中，所述复数个第一数模转换开关、所述复数个第二数模转换开关、所述复数个第三数模转换开关以及所述复数个第四数模转换开关受控于所述控制电路。
例如，所述复数个正向数模转换电容的复数个正向数模转换电容值之间呈一指数型关系，所述复数个负向数模转换电容的复数个负向数模转换电容值 之间呈一指数型关系。
例如，于所述积分区间中，所述控制电路控制所述正向数模转换单元的所述复数个第一数模转换开关及所述复数个第二数模转换开关，使得当所述比较器转态时，将所述输出电压增加一第一特定值。
例如，于所述积分区间中，所述逻辑电路累计所述比较器的一累计转态次数，并产生相关于所述累计转态次数的所述第一码。
例如，于一采样区间中，所述控制电路控制所述正向数模转换单元的所述复数个第一数模转换开关及所述复数个第二数模转换开关，使得所述复数个正向数模转换电容接收所述正电压；于所述采样区间中，所述控制电路控制所述负向数模转换单元的所述复数个第一数模转换开关及所述复数个第二数模转换开关，使得所述复数个负向数模转换电容耦接于所述接地端。
例如，于所述比较区间中，所述控制电路控制所述复数个第一数模转换开关、所述复数个第二数模转换开关、所述复数个第三数模转换开关以及所述复数个第四数模转换开关，以调整所述输入电压。
例如，所述比较区间包含复数个比较子区间，于所述复数个比较子区间的一比较子区间中，所述比较器结果产生对应于所述比较子区间的一比较结果。
例如，所述逻辑电路根据对应于所述复数个比较子区间的复数个比较结果，产生所述第二码。
例如，于所述比较子区间中，当所述前置结果显示所述输入电压大于所述共模电压时，所述控制电路控制所述复数个第一数模转换开关、所述复数个第二数模转换开关、所述复数个第三数模转换开关以及所述复数个第四数模转换开关，使得所述输入电压于下一比较子区间中下降一第二特定值。
例如，于所述比较子区间中，当所述前置结果显示所述输入电压小于所述共模电压时，所述控制电路控制所述复数个第一数模转换开关、所述复数个第二数模转换开关、所述复数个第三数模转换开关以及所述复数个第四数模转换开关，使得所述输入电压于下一比较子区间中上升一第三特定值。例如，
例如，所述输出码为所述第一码向左平移(N－1)个比特后与所述第二码的相加结果，其中N代表所述第二码的比特数。
例如，电容感测电路另包含一取样保持电路，耦接于所述接触电容与所述积分输入端。
例如，所述取样保持电路包含一第一开关，其一端接收一正电压，另一端耦接于所述接触电容；以及一第二开关，其一端耦接于所述接触电容，另一端耦接于所述积分输入端；其中，于一第一时间，所述第一开关导通而所述第二开关断开；以及于一第二时间，所述第一开关断开而所述第二开关导通。
例如，所述积分电路包含有一放大器，耦接于所述积分输入端与所述积分输出端之间；一积分电容，耦接于所述积分输入端；一第三开关，耦接于所述积分电容与所述所述积分输出端；以及一第四开关，其一端耦接于所述积分电容与所述第三开关，另一端接收一共模电压。
例如，所述参考电压与所述共模电压相等。
例如，所述积分电路另包含有一第五开关，耦接于所述积分输入端与所述积分输出端之间。
本专利申请另提供了一種电容感测电路，包括复数个像素电路，用来一手指形成复数个接触电容；一电容感测电路，耦接于所述复数个像素电路，用来感测所述复数个接触电容，所述电容感测电路包含一积分电路，包含有一积分输入端，所述积分输入端具有一输入电压；以及一积分输出端，用来输出一输出电压；一比较器，包含有一第一输入端，耦接于所述积分输出端；以及一第二输入端，用来接收一参考电压；一正向数模转换单元，耦接于所述积分输入端；一负向数模转换单元，耦接于所述积分输入端；一控制电路，耦接于所述比较器的一比较输出端，用来控制所述正向数模转换单元以及所述负向数模转换单元；以及一逻辑电路，耦接于所述比较输出端，用来于一积分区间中，产生一第一码，并于一比较区间中，产生一第二码，所述逻辑电路根据所述第一码以及所述第二码，输出一输出码，所述输出码相关于所述复数个接触电容 中一接触电容的一电容值。
本专利申请提供的电容感测电路可将接触电容中的电容值转换成一数字信号，其具有电路结构简单、电路面积小、成本低、功耗低以及延迟等待时间低的优点。
附图说明
图1为本专利申请部分实施例一电容感测电路的示意图。
图2为本专利申请部分实施例中一输入电压与一输出电压及的波形图。
图3为本专利申请部分实施例中一第一码、一第二码以及一输出码的示意图。
图4为本专利申请部分实施例一指紋辨识系統的示意图。
具体实施方式
为了使本专利申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本专利申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本专利申请，并不用于限定本专利申请。
本专利申请的电容感测电路用来感测一接触电容，其可直接输出相关于该电容值的输出码，而不需要后端的模拟数字转换器(ADC)来将相关于该电容值的模拟信号转换成输出码。详细来说，请参考图1，图1为本专利申请一电容感测电路10的示意图。电容感测电路10用来感测一接触电容Cf，电容感测电路10可直接输出相关于接触电容Cf的电容值的一输出码ctotoal。
如图1所示，电容感测电路10耦接于一取样保持电路SH，其包含一积分电路12、一比较器Comp、一正向数模转换单元14a、一负向数模转换单元14b、一控制电路16以及一逻辑电路18。积分电路12包含一积分输入端以及一积分输出端，积分输入端形成有一输入电压Vx，积分输出端输出一输出电压Vo。取样保持电路SH包含开关S1、S2，开关S1的一端接收一正电压VDD， 开关S1的另一端耦接于接触电容Cf，开关S2的一端耦接于接触电容Cf，开关S2的另一端耦接于该积分输入端。积分电路12包含一放大器Amp、一积分电容CINT以及开关S3、S4、S5，放大器Amp、积分电容CINT以及开关S3、S5皆耦接于积分电路12的积分输入端与积分输出端之间。详细来说，积分电容CINT与开关S3串联成一序列，而开关S5与此序列并联，开关S4的一端耦接于积分电容CINT以及开关S3，开关S4的另一端接收一共模电压VCM。比较器Comp的一第一输入端耦接于所述积分输出端，以接收输出电压Vo，比较器Comp的一第二输入端接收一参考电压VR，比较器Comp产生输出电压Vo与参考电压VR的一比较结果q并输出至比较器Comp的一比较输出端。控制电路16耦接于比较器Comp的比较输出端，用来产生复数个控制信号以控制正向数模转换单元14a以及负向数模转换单元14b。逻辑电路18耦接于比较器Comp的比较输出端，用来于一积分区间TINT中，产生一第一码(Code)c1，并于一比较区间TCP中，产生一第二码c2，逻辑电路18可根据第一码c1以及第二码c2，产生相关于接触电容Cf的电容值的输出码ctotoal，其中第一码c1、第二码c2以及输出码ctotoal皆为二进制(Binary)信号，其细节详述于后。
详细来说，正向数模转换单元14a包含有正向数模转换电容Ca0～CaK、数模转换开关SVa0～SVaK以及数模转换开关SGa0～SGaK，正向数模转换电容Ca0～CaK皆耦接于所述积分输入端，(在k＝0,…,K的情况下)数模转换开关SVak与数模转换开关SGak的一第一端皆耦接于正向数模转换电容Cak，数模转换开关SVak的一第二端接收正电压VDD，数模转换开关SGak的第二端耦接于一接地端GND。同样地，负向数模转换单元14b包含有负向数模转换电容Cb0～CbK、数模转换开关SVb0～SVbK以及数模转换开关SGb0～SGbK，负向数模转换电容Cb0～CbK皆耦接于所述积分输入端，(在k＝0,…,K的情况下)数模转换开关SVbk与数模转换开关SGbak的一第一端皆耦接于正向数模转换电容Cbk，数模转换开关SVbk的一第二端接收正电压VDD，数模转换开关SGbk的第二端耦接于一接地端GND。数模转换开关SVa0～SVaK、数模转换开关SGa0～SGaK、数模转 换开关SVb0～SVbK以及数模转换开关SGb0～SGbK皆受控于控制电路16，换句话说，控制电路16可根据比较结果q产生复数个控制信号，以控制正向数模转换单元14a以及负向数模转换单元14b。
为了方便说明，正向数模转换电容Ca0～CaK(或负向数模转换电容Cb0～CbK)是依照电容值的大小由大到小排列(即Ca0≥Ca1≥…≥CaK或Cb0≥Cb1≥…≥CbK)。于一实施例中，正向数模转换电容Ca0～CaK(或负向数模转换电容Cb0～CbK)可呈一指数型递减关系，举例来说，(在k＝0,…,K的情况下)当正向数模转换电容Ca0的电容值为CA时，正向数模转换电容Cak的电容值为CA/2k；同理，当负向数模转换电容Cb0的电容值为CB时，负向数模转换电容Cbk的电容值为CB/2k。
电容感测电路10的操作细节叙述如下。放了方便说明，图2绘示本专利申请一实施例输入电压Vx与输出电压Vo的波形图。于一重置区间TRST中，电容感测电路10将清空积分电容CINT中所储存的电荷。于一实施例中，开关S3、S5、数模转换开关SVa0～SVaK、SGb0～SGbK为导通(Conducted，ON)，数模转换开关SGa0～SGaK、SVb0～SVbK为断路(Cutoff，OFF)，此时，积分电容CINT中的电荷会被清空，而输入电压Vx与输出电压Vo相等，于一实施例中，输入电压Vx、输出电压Vo及参考电压VR可等于共模电压VCM。
于积分区间TINT中，积分电路12对接触电容Cf中所储存的电荷进行一积分操作。于一实施例中，开关S5以及数模转换开关SVb0～SVbK、SGb0～SGbK可为断路，开关S1、S3可受控于一时脉信号CK1，开关S2、S5可受控于一时脉信号CK2，其中时脉信号CK1于一时脉周期的一前半周期为高电位，时脉信号CK2于时脉周期的一后半周期为高电位。在此情形下，于前半周期中，开关S1导通而开关S2断开，接触电容Cf充电至正电压VDD；于后半周期，开关S1断开而开关S2导通，储存于接触电容Cf的电荷流至积分电容CINT，换句话说，于积分区间TINT中，输出电压Vo会随时间递减。另外，当输出电压Vo小于参考电压VR时，将导致比较器Comp转态，此时控制电路16产生控制信号来控 制数模转换开关SVa0～SVaK、SGa0～SGaK，使得输出电压Vo增加一特定电压值VK(即输出电压Vo增加至一电压VR+VK)，因此，输出电压Vo的值将会被限制在电压VR+VK与电压VR之间。
更进一步的，逻辑电路18可累计比较器Comp的一累计转态次数NCNT，并产生相关于累计转态次数NCNT的第一码c1。以图2所绘示的实例为例，于积分区间TINT中，输出电压Vo于时间tI1、tI2小于参考电压VR而导致比较器Comp转态，因此累计转态次数NCNT等于2，而逻辑电路18产生第一码c1为累计转态次数NCNT的二进制表示法，即逻辑电路18产生第一码c1为10。另外，于积分区间TINT结束的一时间tSP时，输出电压Vo具有一采样电压值VSP。
控制电路16控制数模转换开关SVa0～SVaK、SGa0～SGaK使得输出电压Vo增加特定电压值VK的细节叙述如下。于输出电压Vo递减以至于输出电压Vo小于参考电压VR后的下一个时脉周期中，控制电路16控制数模转换开关SVa0～SVaK于时脉周期的前半周期导通且于时脉周期的一后半周期断开，控制电路16控制而数模转换开关SGa0～SGaK于时脉周期T的前半周期断开且于时脉周期T的后半周期导通。也就是说，于输出电压Vo因积分而递减，以至于输出电压Vo小于参考电压VR后的瞬间(即时脉周期T’中)，输出电压Vo即可增加至电压VR+VK。如此一来，输出电压Vo的值将会被限制在电压VR+VK与电压VR之间。
另外，于一采样区间TSP中，电容感测电路10进行一采样操作。于一实施例中，数模转换开关SVa0～SVaK、数模转换开关SGb0～SGbK以及开关S4可为导通，数模转换开关SGa0～SGaK、数模转换开关SVb0～SVbK以及开关S3、S5可为断路。在此情形下，积分电容CINT与正向数模转换电容Ca0～CaK、负向数模转换电容Cb0～CbK之间可产生电荷分享(Charge Sharing)作用，导致输入电压Vx于采样区间TSP中下降或上升，输出电压Vo也随之上升或下降，因此，比较器Comp可产生对应于采样区间TSP的比较结果q为qSP(qSP可为一二进制数值)，逻辑电路18可根据qSP产生第二码c2的一最高有效位(Most Significant  Bit，MSB)为qSP’(qSP’代表qSP的一反向，以布尔代数/逻辑的描述法来说，qSP’为非qSP)。
以图2所绘示的实例为例，于采样区间TSP中，输入电压Vx因电荷分享作用而下降(即输入电压Vx小于共模电压VCM)，因放大器Amp具有反向放大作用，输入电压Vx微幅下降将导致输出电压Vo因此急遽上升(举例来说，输出电压Vo急遽上升至放大器Amp的一饱和电压，其中放大器Amp的饱和电压可为正电压VDD)，比较器Comp产生比较结果qSP为1(qSP＝1)，逻辑电路18根据qSP产生第二码c2的最高有效位为0(qSP’＝0，因qSP＝1)。
另外，于比较区间TCP中，控制电路16控制数模转换开关SVa0～SVaK、SGa0～SGaK、SVb0～SVbK、SGb0～SGbK，以调整输入电压Vx，进而逼近共模电压VCM。具体来说，比较区间TCP可区分成比较子区间TCP0～TCPK，于比较子区间TCP0中，控制电路16根据比较结果qSP控制数模转换开关SVa0、SGa0、SVb0、SGb0，使得输入电压Vx得以上升/下降，输出电压Vo于比较子区间TCP0中得以下降/上升，比较器Comp产生对应于比较子区间TCP0的比较结果q为q0(q0亦为一二进制数值)，此时逻辑电路18根据qSP产生第二码c2的一次高有效位(Second Significant Bit)为q0’(同理，q0’代表q0的一反向，即q0’为非q0)，其中，第二码c2的次高有效位代表代表自第二码c2的最高有效位开始，往右边(即由最高有效位往最低有效位(Least Significant Bit，LSB)的方向)数来第1个比特。以图2所绘示的实例为例，于比较子区间TCP0中，控制电路16根据比较结果qSP控制数模转换开关SVa0、SGa0、SVb0、SGb0，使得输入电压Vx于比较子区间TCP0中得以上升，输出电压Vo于比较子区间TCP0中得以下降，比较器Comp产生比较结果q0为0(q0＝0)，此时逻辑电路18根据q0产生第二码c2的次高有效位为1(q0’＝1，因q0＝0)。
另外，于比较子区间TCP1～TCPK的一比较子区间TCPk中，控制电路16根据比较结果qk-1控制数模转换开关SVak、SGak、SVbk、SGbk，使得输入电压Vx得以上升/下降，输出电压Vo于比较子区间TCPk中得以下降/上升，比较器Comp 产生对应于比较子区间TCPk的比较结果q为qk(qk亦为一二进制数值)，此时逻辑电路18根据比较结果qk产生第二码c2自最高有效位往右边数来第k+1个比特为qk’(同理，qk’代表qk的一反向，即qk’为非qk)，其中，前述右边代表自最高有效位往最低有效位(Least Significant Bit，LSB)的方向。如此一来，于比较区间TCP终止时，逻辑电路18可产生第二码c2为qSP’q0’q2’…qK’。
以图2所绘示的实例为例，于比较子区间TCP1中，控制电路16根据比较结果q0控制数模转换开关SVa1、SGa1、SVb1、SGb1，使得输入电压Vx于比较子区间TCP1中得以下降上升，输出电压Vo于比较子区间TCP0中得以上升，比较器Comp产生比较结果q1为1(q1＝1)，此时逻辑电路18根据q1产生第二码c2自最高有效位往右边数来第2个比特为0(q1’＝0，因q1＝1)。于比较区间TCP终止时，逻辑电路18产生第二码c2为010。
另外，于逻辑电路18产生第一码c1以及第二码c2后，逻辑电路18可根据第一码c1及第二码c2，产生相关于接触电容Cf的电容值的输出码ctotoal。具体来说，在第二码c2具有N个比特的情况下，逻辑电路18可将第一码c1所代表的二进制数值乘以2N-1(即将第一码c1向左平移(N－1)个比特)后，将相乘结果(即平移后的结果)与第二码c2相加，所得的相加结果即为输出码ctotoal，此时输出码ctotoal所代表的二进制数值即相关于接触电容Cf的电容值。其中，第一码c1可视为一粗略码(Coarse Code)，其包含输出码ctotoal较为显着(Significant)的成份；而第二码c2可视为一细致码(Fine Code)，其包含输出码ctotoal较不显着的成份。以图2所绘示的实例为例，逻辑电路18可产生输出码ctotoal为第一码c1向左平移2个比特后与第二码c2的相加结果，如图3所示。
另一方面，于比较子区间TCPk中输入电压Vx上升的幅度相关于数模转换开关SVak、SGak所对应正向数模转换电容Cak的电容值，于比较子区间TCPk中输入电压Vx上升的幅度相关于数模转换开关SVbk、SGbk所对应负向数模转换电容Cbk的电容值，在正向数模转换电容Ca0～CaK(或负向数模转换电容Cb0～ CbK)依照电容值的大小由大到小排列的情况下，于比较子区间TCP1～TCPK中，输入电压Vx上升/下降的幅度随着k增大而减小，输入电压Vx与采样电压值VSP的差距也随着k增大而减小，换句话说，控制电路16藉由于比较子区间TCPk中控制数模转换开关SVak、SGak、SVbk、SGbk来调整输入电压Vx，以逼近共模电压VCM。另外，逻辑电路18可根据比较器Comp于采样区间TSP以及比较区间TCP的所产生的比较结果q来产生第二码c2(即细致码)，并根据第一码c1以及第二码c2产生输出码ctotoal，因此，数字的输出码ctotoal可代表接触电容Cf的电容值。
除此之外，正向数模转换单元14a、负向数模转换单元14b、控制电路16以及逻辑电路18于采样区间TSP以及比较区间TCP的其余操作细节类似于一逐次逼近寄存器型模拟数字转换器(Successive Approximation Register Analog-to-Digital Converter，简称SAR ADC)，SAR ADC已为本领域具通常知识者所熟知，于此不再赘述。
由上述可知，本专利申请利用控制电路16于比较区间TCP中，控制正向数模转换单元14a以及负向数模转换单元14b，以调整输入电压Vx，以逼近共模电压VCM，另外，于采样区间TSP以及比较区间TCP中比较器Comp所产生的比较结果q可用来产生第二码c2(即细致码)，如此一来，根据第一码c1及第二码c2所产生输出码ctotoal为数字信号，其可代表接触电容Cf的电容值。相较于习知技术，电容感测电路10不需额外使用模拟数字转换器(Analog to Digital Convertor，ADC)，即可精确地将接触电容Cf的电容值转换为数字信号，电容感测电路10除了电路结构简单、电路面积小、成本低以及低功耗之外，更缩短了采样区间TSP及比较区间TCP所需的延迟等待时间(Latency)。
另外，电容感测电路10可应用于一指纹辨识系统中。请参考图4，图4为本专利申请实施例一指纹辨识系统40的示意图。指纹辨识系统40包含像素电路PC_1～PC_N以及电容感测电路10，其中像素电路PC_1～PC_N与用户手指之间形成接触电容Cf_1～Cf_N，而电容感测电路10可耦接于像素电路 PC_1～PC_N所包含的取样保持电路SH(其中电容感测电路10與取样保持电路SH的連接關係與圖1相同)，进而量测接触电容Cf_1～Cf_N的电容大小，如此一来，指纹辨识系统40可根据接触电容Cf_1～Cf_N的电容大小，判断像素电路PC_1～PC_N的位置为纹蜂(Finger Ridge)或纹谷(Finger Valley)。另外，像素电路不限于特定电路结构，举例来说，每一像素电路可包含一顶层电极MT以及一屏蔽层MS，顶层电极MT用来接受使用者手指的接触，并与使用者手指形成接触电容，而顶层电极MT与屏蔽层MS之间具有寄生电容Cp。
需注意的是，前述实施例用以说明本专利申请之概念，本领域具通常知识者当可据以做不同之修饰，而不限于此。举例来说，第一码c1及第二码c2不限于特定长度(比特数)，也就是说，第一码c1及第二码c2的长度(比特数)可视实际需要而调整，举例来说，第一码c1可具有10个比特，第二码c2可具有3个比特，而输出码ctotoal可具有12个比特。
综上所述，本专利申请的电容感测电路利用正向数模转换单元以及负向数模转换单元，于采样区间以及比较区间中调整输入电压，以逼近共模电压，比较器于采样区间以及比较区间中所产生的比较结果即可用来产生细致码。相较于习知技术，本专利申请的电容感测电路具有电路结构简单、电路面积小、成本低、功耗低以及延迟等待时间低的优点。
以上所述仅为本专利申请的部分实施例而已，并不用以限制本专利申请，凡在本专利申请的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本专利申请的保护范围之内。

Claims (18)

  1. 一种电容感测电路，用来感测一接触电容，所述电容感测电路包括：
    一积分电路，包含有：
    一积分输入端，耦接于所述接触电容，所述积分输入端具有一输入电压；以及
    一积分输出端，用来输出一输出电压；
    一比较器，包含有：
    一第一输入端，耦接于所述积分输出端；以及
    一第二输入端，用来接收一参考电压；
    一正向数模转换单元，耦接于所述积分输入端；
    一负向数模转换单元，耦接于所述积分输入端；
    一控制电路，耦接于所述比较器的一比较输出端，用来控制所述正向数模转换单元以及所述负向数模转换单元；以及
    一逻辑电路，耦接于所述比较输出端，用来于一积分区间中，产生一第一码，并于一比较区间中，产生一第二码，所述逻辑电路根据所述第一码以及所述第二码，输出一输出码，所述输出码相关于所述接触电容的一电容值。
  2. 如权利要求1所述的电容感测电路，其中，所述正向数模转换单元包含有：
    复数个正向数模转换电容，皆耦接于所述积分输入端；
    复数个第一数模转换开关，每一第一数模转换开关之一端耦接于所述复数个正向数模转换电容，另一端接收一正电压；以及
    复数个第二数模转换开关，每一第二数模转换开关之一端耦接于所述复数个正向数模转换电容，另一端耦接于一接地端；
    所述负向数模转换单元包含有：
    复数个负向数模转换电容，耦接于所述积分输入端；
    复数个第三数模转换开关，其一端耦接于所述复数个负向数模转换电容，另一端接收一正电压；以及
    复数个第四数模转换开关，其一端耦接于所述复数个负向数模转换电容，另一端耦接于一接地端；
    其中，所述复数个第一数模转换开关、所述复数个第二数模转换开关、所述复数个第三数模转换开关以及所述复数个第四数模转换开关受控于所述控制电路。
  3. 如权利要求2所述的电容感测电路，其中，所述复数个正向数模转换电容的复数个正向数模转换电容值之间呈一指数型关系，所述复数个负向数模转换电容的复数个负向数模转换电容值之间呈一指数型关系。
  4. 如权利要求2所述的电容感测电路，其中，于所述积分区间中，所述控制电路控制所述正向数模转换单元的所述复数个第一数模转换开关及所述复数个第二数模转换开关，使得当所述比较器转态时，将所述输出电压增加一第一特定值。
  5. 如权利要求2所述的电容感测电路，其中，于所述积分区间中，所述逻辑电路累计所述比较器的一累计转态次数，并产生相关于所述累计转态次数的所述第一码。
  6. 如权利要求2所述的电容感测电路，其中，于一采样区间中，所述控制电路控制所述正向数模转换单元的所述复数个第一数模转换开关及所述复数个第二数模转换开关，使得所述复数个正向数模转换电容接收所述正电压；于所述采样区间中，所述控制电路控制所述负向数模转换单元的所述复数个第一数模转换开关及所述复数个第二数模转换开关，使得所述复数个负向数模转换电容耦接于所述接地端。
  7. 如权利要求2所述的电容感测电路，其中，于所述比较区间中，所述控制电路控制所述复数个第一数模转换开关、所述复数个第二数模转换开关、所述复数个第三数模转换开关以及所述复数个第四数模转换开关，以调整所述输入电压。
  8. 如权利要求7所述的电容感测电路，其中，所述比较区间包含复数个比较子区间，于所述复数个比较子区间的一比较子区间中，所述比较器结果产生对应于所述比较子区间的一比较结果。
  9. 如权利要求8所述的电容感测电路，其中，所述逻辑电路根据对应于所述复数个比较子区间的复数个比较结果，产生所述第二码。
  10. 如权利要求8所述的电容感测电路，其中，于所述比较子区间中，当所述前置结果显示所述输入电压大于所述共模电压时，所述控制电路控制所述复数个第一数模转换开关、所述复数个第二数模转换开关、所述复数个第三数模转换开关以及所述复数个第四数模转换开关，使得所述输入电压于下一比较子区间中下降一第二特定值。
  11. 如权利要求8所述的电容感测电路，其中，于所述比较子区间中，当所述前置结果显示所述输入电压小于所述共模电压时，所述控制电路控制所述复数个第一数模转换开关、所述复数个第二数模转换开关、所述复数个第三数模转换开关以及所述复数个第四数模转换开关，使得所述输入电压于下一比较子区间中上升一第三特定值。
  12. 如权利要求1-11中任一项所述的电容感测电路，其中，所述输出码为所述第一码向左平移(N－1)个比特后与所述第二码的相加结果，其中N代表所述第二码的比特数。
  13. 如权利要求1-12中任一项所述的电容感测电路，其中，另包含一取样保持电路，耦接于所述接触电容与所述积分输入端。
  14. 如权利要求13所述的电容感测电路，其中，所述取样保持电路包含：
    一第一开关，其一端接收一正电压，另一端耦接于所述接触电容；以及
    一第二开关，其一端耦接于所述接触电容，另一端耦接于所述积分输入端；
    其中，于一第一时间，所述第一开关导通而所述第二开关断开；以及于一第二时间，所述第一开关断开而所述第二开关导通。
  15. 如权利要求1-14中任一项所述的电容感测电路，其中，所述积分电路包含有：
    一放大器，耦接于所述积分输入端与所述积分输出端之间；
    一积分电容，耦接于所述积分输入端；
    一第三开关，耦接于所述积分电容与所述所述积分输出端；以及
    一第四开关，其一端耦接于所述积分电容与所述第三开关，另一端接收一共模电压。
  16. 如权利要求15所述的电容感测电路，其中，所述参考电压与所述共模电压相等。
  17. 如权利要求1-16中任一项所述的电容感测电路，其中，所述积分电路另包含有：
    一第五开关，耦接于所述积分输入端与所述积分输出端之间。
  18. 一种指纹辨识系统，包括：
    复数个像素电路，用来一手指形成复数个接触电容；
    一电容感测电路，耦接于所述复数个像素电路，用来感测所述复数个接触电容，
    所述电容感测电路包含：
    一积分电路，包含有：
    一积分输入端，所述积分输入端具有一输入电压；以及
    一积分输出端，用来输出一输出电压；
    一比较器，包含有：
    一第一输入端，耦接于所述积分输出端；以及
    一第二输入端，用来接收一参考电压；
    一正向数模转换单元，耦接于所述积分输入端；
    一负向数模转换单元，耦接于所述积分输入端；
    一控制电路，耦接于所述比较器的一比较输出端，用来控制所述正向数模转换单元以及所述负向数模转换单元；以及
    一逻辑电路，耦接于所述比较输出端，用来于一积分区间中，产生一第一码，并于一比较区间中，产生一第二码，所述逻辑电路根据所述第一码以及所述第二码，输出一输出码，所述输出码相关于所述复数个接触电容中一接触电容的一电容值。
PCT/CN2016/106826 2016-11-22 2016-11-22 电容感测电路及指纹辨识系统 Ceased WO2018094579A1 (zh)

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