WO2018103399A1 - 光电二极管器件、光电二极管探测器及其制造方法 - Google Patents

光电二极管器件、光电二极管探测器及其制造方法 Download PDF

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WO2018103399A1
WO2018103399A1 PCT/CN2017/101365 CN2017101365W WO2018103399A1 WO 2018103399 A1 WO2018103399 A1 WO 2018103399A1 CN 2017101365 W CN2017101365 W CN 2017101365W WO 2018103399 A1 WO2018103399 A1 WO 2018103399A1
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type
electrode region
substrate
heavily doped
region
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French (fr)
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张岚
胡海帆
曹雪朋
李军
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Nuctech Co Ltd
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Nuctech Co Ltd
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Priority to EP17878118.3A priority Critical patent/EP3518292B1/en
Priority to US16/343,983 priority patent/US11189741B2/en
Publication of WO2018103399A1 publication Critical patent/WO2018103399A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/10—Semiconductor bodies
    • H10F77/14—Shape of semiconductor bodies; Shapes, relative sizes or dispositions of semiconductor regions within semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/107—Integrated devices having multiple elements covered by H10F30/00 in a repetitive configuration, e.g. radiation detectors comprising photodiode arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H10F39/18—Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H10F39/18—Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors
    • H10F39/189—X-ray, gamma-ray or corpuscular radiation imagers
    • H10F39/1892—Direct radiation image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • H10F71/121—The active layers comprising only Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/10—Semiconductor bodies
    • H10F77/12—Active materials
    • H10F77/122—Active materials comprising only Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/10—Semiconductor bodies
    • H10F77/14—Shape of semiconductor bodies; Shapes, relative sizes or dispositions of semiconductor regions within semiconductor bodies
    • H10F77/147—Shapes of bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/20—Electrodes
    • H10F77/206—Electrodes for devices having potential barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/93—Interconnections
    • H10F77/933—Interconnections for devices having potential barriers

Definitions

  • the present disclosure relates to photodetector devices and, in particular, to photodiode devices and photodiode detectors having improved performance and methods of fabricating the same.
  • the semiconductor photodiode array ionizes with atoms in the semiconductor by incident light (eg, direct incident light, or visible light rays generated by X-rays in the scintillator), thereby generating unbalanced carriers to detect incident light.
  • incident light eg, direct incident light, or visible light rays generated by X-rays in the scintillator
  • Parameters that measure the performance of a photodiode array include resolution, signal-to-noise ratio, readout speed, optical response, and crosstalk between pixels.
  • X-rays pass through short-wavelength visible light generated by the scintillator, producing electron and hole carriers in a shallow depth on one side of the silicon optical device. These photo-generated carriers drift or diffuse in the device and are collected by the electrodes on the other side, producing an electrical signal. Due to defects in the wafer, in order to prevent most of the photogenerated carriers from being collected by defects, thinner wafers are often used in the fabrication of back-in photodiode array detectors, typically 100 to 150 microns. However, an excessively thin wafer reduces the overall mechanical strength and is prone to warpage and debris. Wafers are re-grinded (to reduce their thickness) and are also susceptible to particle contamination, reducing the quantum efficiency of incident light collection.
  • an object of the present disclosure is, at least in part, to provide a photodiode device and photodiode detector having improved performance and a method of fabricating the same.
  • a method of fabricating a photodiode device includes: growing an epitaxial layer on a first surface of a substrate, wherein the epitaxial layer is lightly doped by the first type, and is in the substrate Forming a first type of heavily doped region in contact with the first type of lightly doped epitaxial layer; from a side of the second surface of the substrate opposite the first surface, thinning the substrate and exposing the first type of heavy a doped region; patterning a first type of heavily doped region from a side of the second surface of the substrate to form a trench therein, the trench penetrating the first type of heavily doped region into the epitaxial layer, Wherein the patterned first type of heavily doped region acts as a first electrode region of the photodiode device; and a second type of heavily doped region is formed at the bottom of the trench, the region acting as a second electrode region of the photodiode device.
  • a photodiode device comprising: a first type of heavily doped substrate comprising first and second surfaces opposite to each other, the first type of heavily doped substrate a first electrode region serving as a photodiode device; an epitaxial layer grown on the first surface of the substrate, wherein the epitaxial layer is lightly doped by the first type, and the trench is included in the substrate to expose the epitaxial layer; A second type of heavily doped second electrode region formed within the trench, wherein the second electrode region is electrically isolated from the first electrode region.
  • a photodiode detector comprising an array of a plurality of the above described photodiode devices.
  • the overall thickness of the device may be relatively thick to maintain a certain mechanical strength; on the other hand, the second electrode region may be relatively concave, so that charge collection efficiency may be improved.
  • FIG. 1A is a top plan view showing a photodiode detector in accordance with an embodiment of the present disclosure
  • Figure 1B is a cross-sectional view taken along line AA' shown in Figure 1A;
  • FIGS. 1A and 1B are cross-sectional views showing a partial stage in the process of fabricating the photodiode detector illustrated in FIGS. 1A and 1B, in accordance with an embodiment of the present disclosure
  • FIG. 3 is a cross-sectional view showing a photodiode detector according to another embodiment of the present disclosure
  • 4A-4I are diagrams illustrating fabrication of the photodiode detector of FIG. 3 in accordance with an embodiment of the present disclosure. a cross-sectional view of a partial stage of the process;
  • 4J is a cross-sectional view showing a contact portion according to another embodiment of the present disclosure.
  • FIG. 5 is a cross-sectional view showing a photodiode detector according to another embodiment of the present disclosure.
  • 6A-6I are cross-sectional views showing a partial stage in the process of fabricating the photodiode detector illustrated in FIG. 5, in accordance with an embodiment of the present disclosure
  • FIG. 6J is a cross-sectional view showing a contact portion according to another embodiment of the present disclosure.
  • a layer/element when referred to as being "on" another layer/element, the layer/element may be directly on the other layer/element, or there may be a central layer between them/ element. In addition, if a layer/element is "on” another layer/element, the layer/element may be "under” the other layer/element when the orientation is reversed.
  • FIG. 1A is a plan view showing a photodiode detector according to an embodiment of the present disclosure
  • FIG. 1B is a cross-sectional view taken along line AA' shown in FIG. 1A.
  • the photodiode detector 100 may include a plurality of photodiode devices Pix formed on a semiconductor substrate 101, each of which may constitute one pixel of the photodiode detector 100.
  • the semiconductor substrate 101 may comprise various suitable semiconductor materials, such as a single wafer (eg, a silicon (Si) wafer) or an epitaxial wafer (including an epitaxial layer on the wafer, eg, including a Si epitaxial layer on the Si wafer).
  • the semiconductor substrate 101 includes the other The opposite two surfaces are a first surface 101-1S and a second surface 101-2S.
  • the semiconductor substrate 101 can be doped to a suitable conductivity type, such as a first type (eg, N-type).
  • the semiconductor substrate 101 may include different regions 101-1 and 101-2 depending on the doping concentration.
  • 101-1 may be a relatively heavily doped doped region in the wafer
  • 101-2 may be a relatively lightly doped doped region in the wafer.
  • 101-1 may be a relatively heavily doped wafer
  • 101-2 may be a relatively lightly doped epitaxial layer grown on wafer 101-1.
  • the first type heavily doped region 101-1 may serve as the first electrode region 103 of the photodiode device Pix.
  • the photodiode device Pix may further include a second electrode region 105.
  • the second electrode region 105 may be doped to a conductivity type different from that of the semiconductor substrate 101, for example, a second type (for example, P-type), thereby constituting a PN junction with the semiconductor substrate 101, particularly the region 101-2 therein.
  • the second electrode region 105 may constitute an anode of the photodiode device Pix, and the semiconductor substrate 101 is taken out through the first electrode region 103 to constitute a photodiode The cathode of device Pix.
  • the first electrode region 103 and the second electrode region 105 may be heavily doped.
  • the lightly doped region 101-2 is present, the two heavily doped regions are prevented from being directly adjacent, and thus the tunneling effect can be suppressed.
  • the thickness of the semiconductor substrate 101 may be about 200-400 ⁇ m, and the thickness of the first electrode region 103 may be about 10-100 ⁇ m; in addition, in the case of an epitaxial wafer, the epitaxial layer 101-2 The thickness may be about 50-150 ⁇ m, and the thickness of the first electrode region 103 may be about 10-150 ⁇ m.
  • the thickness of the second electrode region 105 may be about 0.5-5 ⁇ m.
  • the first electrode region 103 and the second electrode region 105 may be electrically isolated from each other, for example, the spacing between them may be about 10-100 ⁇ m.
  • the incident light may be incident on the photodiode device Pix from the second surface 101-2S.
  • the photodiode device Pix can operate in a reverse bias mode. At this time, a wider space charge region under reverse bias conditions can be formed in the vicinity of the light collecting active region (the region near the incident surface 101-2S) in the pixel.
  • the photodiode device Pix can also operate in a zero bias mode. At this time, a narrow built-in space charge region under zero bias conditions can be formed in the vicinity of the light collecting active region in the pixel. Electrodes may be drawn at the first electrode region 103 and the second electrode region 105, respectively, to apply a bias voltage and/or read a signal.
  • the incident light may be in the light collecting active region and the semiconductor substrate 101 (particularly the region 101-2)
  • the silicon atoms undergo impact ionization, resulting in electron-hole pairs.
  • the electrons may drift or diffuse toward the first electrode region 103 by the built-in electric field or an external biasing electric field, and are eventually collected by the first electrode region 103.
  • the holes may drift or diffuse toward the second electrode region 105 by the built-in electric field or an external biasing electric field, and are finally collected by the second electrode region 105.
  • An electrical signal can be read from the second electrode region 105, and information about the incident light (e.g., the intensity of the incident light) can be obtained therefrom.
  • the second electrode region 105 may be closer to the second surface 101-2S side than the first electrode region 103.
  • the distance between the hole carriers and the collecting mechanism can be reduced, so that the absorption of the hole carriers can be accelerated, and the trapping of the carriers by the semiconductor substrate defects can be reduced, thereby improving the photoresponsive output current.
  • the overall thickness of the photodiode detector 100 can still be kept relatively large, so that a certain mechanical strength can be maintained. This can be achieved, for example, by recessing the second electrode region 105 on the side of the first surface 101-1S. As described below, such a recess can be a trench structure.
  • the doping in each region can be formed by ion implantation, in-situ doping at the time of epitaxial growth, or the like.
  • Those skilled in the art are aware of a variety of means to form certain types of doped regions in/on a defined area of a semiconductor substrate.
  • the first electrode region 103 of the photodiode device Pix may surround the second electrode region 105.
  • the first electrode regions 103 of the respective photodiode devices Pix may be connected to each other to be integrated.
  • the second electrode regions 105 of the respective photodiode devices Pix may be separated from each other and arranged in an array, for example, in rows and columns.
  • the first type of lightly doped region 101-2 can maintain a high resistance, such as a resistivity of about 100-8 x 10 3 ⁇ cm.
  • a first type dopant such as phosphorus (P) or arsenic (As)
  • P phosphorus
  • a dopant such as boron (B).
  • a thinner layer of the first type heavily doped region 107 can be formed on the side of the second surface 101-2S.
  • the first type heavily doped region 107 has a thickness of about 0.2-1 ⁇ m.
  • an insulating layer 109 may be formed on the first type heavily doped region 107.
  • the insulating layer 109 may include a dielectric material such as silicon dioxide, silicon nitride, or a combination thereof.
  • each photoelectric The first type heavily doped region 107 and the insulating layer 109 at the side of the second surface 101-2S of the diode device Pix may continuously extend.
  • a passivation layer 111 may be formed to cover and protect the first electrode region 103 and the second electrode region 105.
  • the passivation layer 111 may comprise a dielectric material such as silicon dioxide, silicon nitride, or a combination thereof.
  • the passivation layer 111 may be formed to be thin, for example, formed on the first surface 101-1S side in a substantially conformal manner; or may be formed thicker and may, for example, fill the trench corresponding to the second electrode region 105 .
  • the passivation layer 111 may continuously extend on the side of the first surface 101-1S.
  • contact holes penetrating the passivation layer 111 corresponding to the first electrode region 103 and the second electrode region 105, respectively, may be formed.
  • Electrical contacts 113, 115 may be formed through the contact holes to lead the first electrode region 103 and the second electrode region 105 to achieve the desired electrical connection.
  • the electrical contacts 113, 115 may comprise a conductive material such as a metal such as copper (Cu), tungsten (W), or the like.
  • a common electrical contact portion to the common first electrode region 103 can be formed for the photodiode detector 100.
  • one or more common electrical contacts 113 may be formed depending on the size and layout of the photodiode detector 100.
  • FIGS. 1A and 1B are cross-sectional views showing a partial stage in the process of fabricating the photodiode detector illustrated in FIGS. 1A and 1B, in accordance with an embodiment of the present disclosure.
  • the epitaxial wafer 101 may include a semiconductor substrate 101-1 such as a silicon wafer.
  • the substrate 101-1 may be heavily doped by a first type (for example, N-type) and include two surfaces (upper and lower side surfaces in the drawing) opposed to each other.
  • the epitaxial layer 101-2 can be epitaxially grown. While the epitaxial layer 101-2 is grown, in-situ doping may be performed such that the epitaxial layer 101-2 is lightly doped by the first type.
  • a single wafer 101 can be provided and the wafer 101 can be lightly doped with a first type (eg, N-type). Then, at one side surface of the wafer 101, a first type heavily doped region 101-1 may be formed therein by, for example, contact diffusion (the rest is still the first type of lightly doped region labeled 101-2) .
  • the wafer 101 can be a single throw wafer or a dual throw wafer. In the case of a single-throw wafer, diffusion doping can be The polishing surface is performed; in the case of a double-throw wafer, diffusion doping can be performed on either surface. By forming a thicker N+ region by contact diffusion, part of the surface damage caused by back grinding can be eliminated.
  • the substrate 101-1 may be sanded to thin the thickness of the epitaxial wafer 101, for example, to about 150-250 ⁇ m.
  • the polished surface can be polished, such as chemically etched, to subsequently process the surface.
  • the thickness of the thinned substrate may be determined according to the thickness of the epitaxial layer. For example, when the epitaxial layer is thicker (eg, greater than about 100 ⁇ m), the thickness of the substrate can be reduced to be small (eg, less than about 50 ⁇ m); and when the epitaxial layer is thin (eg, less than about 50 ⁇ m), The thickness of the substrate can be thinned to be large (eg, greater than about 100 [mu]m). On the other hand, the total thickness of the semiconductor substrate 101 can be maintained to be about 150 to 250 ⁇ m.
  • the first type heavily doped substrate 101-1 is ground without polishing the epitaxial layer 101-2, the influence of particle contamination on quantum efficiency can be reduced.
  • the first type heavily doped substrate 101-1 can then be used as the first electrode region of the photodiode device.
  • the first type heavily doped substrate 101-1 may be patterned according to an array layout to form a trench therein for forming a second electrode region.
  • the trench may penetrate the first type heavily doped substrate 101-1 and enter The first type of lightly doped epitaxial layer 101-2.
  • a second electrode region can then be formed within the trench, such as at the bottom of the trench.
  • the oxide layer 121 may be formed on the opposite surfaces (upper and lower side surfaces in FIG. 2C) of the epitaxial wafer 101 by, for example, thermal oxidation. Then, a series of openings may be formed in the oxide layer 121 at the surface (in FIG. 2C, the lower surface) on the side of the substrate 101-1 by photolithography, the openings corresponding to the second electrode region to be formed later s position.
  • the oxide layer 121 having an opening formed at the lower surface can then be used as a mask layer when etching the trench, and the oxide layer 121 at the upper surface can then protect the upper surface during etching of the trench.
  • the epitaxial wafer 101 can be etched, such as wet etching.
  • the epitaxial wafer 101 may be immersed in a silicon etching solution such as KOH, TMAH or HF-HNO 3 . Due to the opening in the oxide layer 121 at the lower surface, the trench T is etched on the side of the lower surface. Due to the wet etching, the cross section of the trench T may exhibit a shape that tapers from one side of the lower surface toward the side of the upper surface.
  • the time of etching may be controlled such that the depth of the trench T exceeds the thickness of the first type heavily doped substrate 101-1 (eg, the depth of the trench T is greater than the first type of heavily doped).
  • the substrate 101-1 has a thickness of about 5-10 ⁇ m) such that the trench T penetrates the first type heavily doped substrate 101-1 into the first type of lightly doped epitaxial layer 101-2.
  • the patterned first type heavily doped substrate 101-1 can then be used as the first electrode region 103.
  • an oxide layer 123 may be formed on both the upper and lower surfaces of the epitaxial wafer 101 by, for example, thermal oxidation.
  • the oxide layer 123 is shown as being integrated with the oxide layer 121 for the sake of convenience.
  • the oxide layer 121 may be removed by cleaning, and then the oxide layer 123 may be formed by thermal oxidation; or, the oxide layer 123 may be directly formed by thermal oxidation without removing the oxide layer 121 (at this time, the oxide layer 121) May be thicker).
  • the oxide layer can then be patterned to at least partially expose the bottom region of the trench.
  • a series of openings may be formed at a position where a second electrode region is to be formed in the oxide layer 121/123 formed on one side of the lower surface by photolithography.
  • these openings may be formed, for example, in approximately the middle of the bottom of each trench, and the ends of the openings may be retracted inwardly relative to the respective trench sidewalls.
  • a second type of heavily doped region 105 may be formed on the lower surface side by ion implantation (eg, implant B or BF2) through an opening in the oxide layer 121/123 (which may be annealed to activate the implant) Ion), which can then be used as the second electrode region. Thereafter, the oxide layer 121/123 can be removed by washing.
  • ion implantation eg, implant B or BF2
  • the oxide layer 121/123 which may be annealed to activate the implant
  • ion implantation for example, implantation of P or As, implantation depth of about 0.2-1 ⁇ m
  • the first type is heavily doped region 107.
  • an insulating layer 109 may be formed on the first type heavily doped region 107.
  • a thin layer of oxide can be formed on the heavily doped region 107 of the first type by thermal oxidation.
  • the implanted impurity ions can also be activated during thermal oxidation.
  • a passivation layer 111 may be formed on the lower surface side so as to cover the first electrode region 103 and the second electrode region 105.
  • a silicon dioxide layer may be formed on the lower surface side by deposition such as chemical vapor deposition (CVD).
  • CVD chemical vapor deposition
  • the deposited silicon dioxide layer 111 is relatively thin so as to be formed on the lower surface side (having substantially the same or similar undulations as the underlying structure) in a substantially conformal manner.
  • Contact portions 113, 115 to the first electrode region 103 and the second electrode region 105 may be fabricated to take them out.
  • a contact hole penetrating the passivation layer 111 may be formed at a position corresponding to the first electrode region 103 and the second electrode region 105 in the passivation layer 111 by photolithography.
  • a conductive material such as a metal may be formed on the passivation layer 111, the conductive material fills the contact hole, and thus is connected to the first electrode region 103 and the second electrode region 105.
  • the conductive material can be patterned into separate electrodes by photolithography.
  • FIG. 3 is a cross-sectional view showing a photodiode detector according to another embodiment of the present disclosure.
  • the photodiode detector may include a plurality of photodiode devices formed on a semiconductor substrate 301.
  • the semiconductor substrate 301 may be an epitaxial wafer including a first type heavily doped substrate 301-1 (having a thickness of, for example, about 150 to 350 ⁇ m) and a first type of lightly doped grown on the substrate 301-1.
  • the epitaxial layer 301-2 (having a thickness of, for example, about 20 to 50 ⁇ m).
  • the substrate 301-1 may serve as the first electrode region 303 of the photodiode device, and each photodiode device may further include a second electrode region 305.
  • the second electrode region 305 may be heavily doped of the second type (thickness is, for example, about 0.5-5 ⁇ m).
  • a first type heavily doped region 307 and an insulating layer 309 may be formed on the side of the surface of the epitaxial layer 301-2 facing away from the substrate 301-1. Further, on the side of the substrate 301-1, a passivation layer 311 may be formed. The contact portions 313 and 315 may pass through the passivation layer 311 and are electrically connected to the first electrode region 303 and the second electrode region 305, respectively. Regarding these components, reference can be made to the above description. In this example, the passivation layer 311 is formed thicker and may have a substantially flat surface.
  • 4A-4I are cross-sectional views showing a portion of a stage in the process of fabricating the photodiode detector of FIG. 3 in accordance with an embodiment of the present disclosure.
  • an epitaxial wafer 301 such as a silicon epitaxial wafer, is provided.
  • the epitaxial wafer 301 may include a first type heavily doped substrate 301-1 and an epitaxial layer 301-2 grown on the substrate 301-1.
  • the substrate 301-1 is polished to a total thickness of the epitaxial wafer 301 of about 150 to 250 ⁇ m. As described above, the thickness of the thinned substrate can be determined according to the thickness of the epitaxial layer.
  • an oxide layer 321 may be formed on the opposite surfaces (upper and lower surfaces in FIG. 4B) of the epitaxial wafer 301 by, for example, thermal oxidation. Then, a series of openings may be formed in the oxide layer 321 at the surface (in FIG. 4B, the lower surface) on the side of the substrate 301-1 by photolithography, the openings corresponding to the second electrode region to be formed later s position.
  • the epitaxial wafer 301 can be etched, such as wet etching. Due to the opening in the oxide layer 321 at the lower surface, the trench T is etched on the side of the lower surface. As described above, the cross section of the groove T may exhibit a shape that tapers from the side of the lower surface toward the side of the upper surface. Likewise, the depth of the trench T may exceed the thickness of the first type heavily doped substrate 301-1 (eg, the depth of the trench T is greater than the thickness of the first type heavily doped substrate 301-1 by about 5) -10 [mu]m) such that the trench T penetrates the first type heavily doped substrate 301-1 into the first type of lightly doped epitaxial layer 301-2. The patterned first type heavily doped substrate 301-1 can then be used as the first electrode region 303.
  • an oxide layer 323 may be formed on both the upper and lower surfaces of the epitaxial wafer 301 by, for example, thermal oxidation.
  • the oxide layer 323 is shown as being integrated with the oxide layer 321 for the sake of convenience.
  • a series of openings may be formed at a position where the second electrode region is to be formed in the oxide layer 321/323 formed on one side of the lower surface by photolithography.
  • a second type of heavily doped region 305 (which can be annealed to activate the implanted ions) can be formed on the lower surface side by ion implantation through an opening in the oxide layer 321/323, which can then be used. As the second electrode area. Thereafter, the oxide layer 321/323 can be removed by washing.
  • a passivation layer 311 may be formed on the surface on the lower surface side so as to cover the first electrode region 303 and the second electrode region 305.
  • the deposited silicon dioxide layer 311 is relatively thick so that the filling of the trenches can be completed and beyond the lower surface of the epitaxial wafer 301.
  • the passivation layer 311 may be subjected to a planarization process such as chemical mechanical polishing (CMP).
  • a first type heavily doped region 307 may also be formed by ion implantation on the surface of the epitaxial layer 301-2 facing away from the substrate 301-1.
  • an insulating layer 309 may be formed in the first type heavily doped region 307.
  • a thin layer of oxide can be formed on the first type heavily doped region 307 by thermal oxidation.
  • the implanted impurity ions can also be activated during thermal oxidation.
  • Contact portions 313, 315 to the first electrode region 303 and the second electrode region 305 may be fabricated to take them out.
  • a contact hole penetrating the passivation layer 311 may be formed at a position corresponding to the first electrode region 303 and the second electrode region 305 in the passivation layer 311 by photolithography.
  • a conductive material such as a metal may be formed on the passivation layer 311, the conductive material fills the contact hole, and thus is connected to the first electrode region 303 and the second electrode region 305.
  • Conductive material can be lithographically
  • the composition is a separate electrode.
  • a second type of heavily doped semiconductor material such as polysilicon may be grown therein.
  • the semiconductor material can be patterned into separate portions 315' by photolithography.
  • a dielectric layer 311' may be formed on the passivation layer 311.
  • contact portions 313, 315 respectively electrically connected to the first electrode region 303 and the doped semiconductor 315' may be formed in the dielectric layer 311'. This avoids the difficulty of filling the metal in the deep contact hole.
  • the contact portion 313 to the first electrode region 303 is illustrated as being integrally formed of a metal material in the example of FIG. 4J, the present disclosure is not limited thereto.
  • the contact portion 313 may be formed in the same manner as the contact portion 315, and thus may also include a stacked structure of doped semiconductor and metal.
  • FIG. 5 is a cross-sectional view showing a photodiode detector according to another embodiment of the present disclosure.
  • the photodiode detector may include a plurality of photodiode devices formed on a semiconductor substrate 501.
  • the semiconductor substrate 501 may be an epitaxial wafer including a first type heavily doped substrate 501-1 (having a thickness of, for example, about 150 to 350 ⁇ m) and a first type of lightly doped grown on the substrate 501-1.
  • the epitaxial layer 501-2 (having a thickness of, for example, about 20 to 50 ⁇ m).
  • the substrate 501-1 may serve as the first electrode region 503 of the photodiode device, and each photodiode device may further include a second electrode region 505.
  • the second electrode region 505 may be heavily doped of the second type (thickness is, for example, about 0.5-5 ⁇ m).
  • a first type heavily doped region 507 and an insulating layer 509 may be formed on the side of the surface of the epitaxial layer 501-2 facing away from the substrate 501-1.
  • a passivation layer 511 can be formed on the side of the substrate 501-1.
  • the contact portions 513 and 515 may pass through the passivation layer 511 and are electrically connected to the first electrode region 503 and the second electrode region 505, respectively.
  • the configuration of this embodiment is substantially the same as the configuration shown in FIG. 3 above, but the trench used to form the second electrode region 505 has a substantially vertical sidewall.
  • FIG. 6A-6I are cross-sectional views showing a partial stage in the process of fabricating the photodiode detector shown in Fig. 5, in accordance with an embodiment of the present disclosure.
  • an epitaxial wafer 501 such as a silicon epitaxial wafer is provided.
  • the epitaxial wafer 501 may include a first type heavily doped substrate 501-1 and an epitaxial layer 501-2 grown on the substrate 501-1.
  • the substrate 501-1 is polished to a total thickness of the epitaxial wafer 501 of about 150 to 250 ⁇ m. As mentioned above, it can be The thickness of the epitaxial layer determines the thickness of the substrate after thinning.
  • an oxide layer 521 may be formed on the opposite surfaces (upper and lower surfaces in FIG. 6B) of the epitaxial wafer 501 by, for example, thermal oxidation. Then, a series of openings may be formed in the oxide layer 521 at the surface (on the lower surface in FIG. 6B) on the side of the substrate 501-1 by photolithography, the openings corresponding to the second electrode region to be formed later s position.
  • the epitaxial wafer 501 can be etched. Due to the opening in the oxide layer 521 at the lower surface, the trench T is etched on the lower surface side. Here, dry etching such as reactive ion etching (RIE) can be utilized. Thus, the trench T can have substantially vertical sidewalls. Likewise, the depth of the trench T may exceed the thickness of the first type heavily doped substrate 501-1 (eg, the depth of the trench T is greater than the thickness of the first type heavily doped substrate 501-1). -10 [mu]m) such that the trench T penetrates the first type heavily doped substrate 501-1 into the first type of lightly doped epitaxial layer 501-2. The patterned first type heavily doped region can then be used as the first electrode region 503.
  • RIE reactive ion etching
  • an oxide layer 523 may be formed on both the upper and lower surfaces of the epitaxial wafer 501 by, for example, thermal oxidation.
  • the oxide layer 523 is shown as being integrated with the oxide layer 521 for the sake of convenience.
  • the laterally extending portion of the oxide layer 521 / 523 can be removed by performing RIE in a direction substantially perpendicular to the substrate surface 501-1S, leaving its vertically extending portion.
  • the sidewall of the trench T is covered by the oxide layer 523, and the bottom portion thereof can be exposed.
  • a second type heavily doped region 505 (which may be annealed to activate the implanted ions) may be formed on the lower surface side by ion implantation, which may then be used as the second electrode region.
  • the oxide layer 521/223 can be removed by washing.
  • a passivation layer 511 may be formed on the lower surface side so as to cover the first electrode region 503 and the second electrode region 505.
  • the deposited silicon dioxide layer 511 is relatively thick so that the filling of the trenches can be completed and beyond the second surface 501-1S of the epitaxial wafer 501.
  • the passivation layer 511 may be subjected to a planarization process such as CMP.
  • a first type heavily doped region 507 may also be formed by ion implantation on the surface of the epitaxial layer 501-2 facing away from the substrate 501-1.
  • an insulating layer 509 may be formed in the first type heavily doped region 507.
  • it can be thermally oxidized in the first type heavily doped region 507 A thin layer of oxide is formed thereon.
  • the implanted impurity ions can also be activated during thermal oxidation.
  • Contact portions 513, 515 to the first electrode region 503 and the second electrode region 505 may be fabricated to lead them out, as shown in FIG. 6I.
  • a contact portion of the stacked structure of the doped semiconductor 515' and the metal 515 may be formed. For this, you can refer to the above description.
  • the laminated structure is formed only for the contact portion to the second electrode region.
  • the present disclosure is not limited thereto.
  • a laminated structure can be similarly formed for the contact portion to the first electrode region.

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Abstract

公开了光电二极管器件、光电二极管探测器及其制造方法。一种光电二极管器件的制造方法包括：在衬底（101-1）的第一表面上生长外延层（101-2），其中，该外延层（101-2）被第一类型轻掺杂，且在衬底（101-1）中形成与该第一类型轻掺杂的外延层（101-2）相接触的第一类型重掺杂区；从衬底（101-1）的与第一表面相对的第二表面一侧，减薄衬底（101-1），并露出第一类型重掺杂区；从衬底（101-1）的第二表面一侧，对第一类型重掺杂区进行构图，以在其中形成沟槽，该沟槽穿透第一类型重掺杂区而进入外延层（101-2）中，其中，构图后的第一类型重掺杂区充当光电二极管器件的第一电极区域（103）；以及在沟槽底部形成第二类型重掺杂的区域，该区域充当光电二极管器件的第二电极区域（105）。

Description

光电二极管器件、光电二极管探测器及其制造方法
相关申请的引用
本申请要求于2016年12月7日递交的题为“光电二极管器件、光电二极管探测器及其制造方法”的中国专利申请201611211395.6的优先权，其内容一并于此用作参考。
技术领域
本公开涉及光电探测器件，具体地，涉及具有改进性能的光电二极管器件及光电二极管探测器及其制造方法。
背景技术
半导体光电二极管阵列通过入射光(例如，直接入射的光线，或者X射线在闪烁体中产生的可见光线)与半导体中原子发生电离反应，从而产生非平衡载流子来检测入射光的。衡量光电二极管阵列性能的参数包括分辨率、信噪比、读出速度、光响应以及像素间电荷串扰等。
例如，X射线经过闪烁体产生的短波长可见光，在硅光器件一侧较浅的深度内产生电子和空穴载流子。这些光生载流子在器件中漂移或扩散而被另一侧的电极所收集，从而产生电信号。由于晶圆中存在缺陷，为避免大部分的光生载流子被缺陷所收集，在制作背入式光电二极管阵列探测器时，常采用较薄的晶圆片，一般为100～150微米。但是，过薄的晶圆片会降低其整体的机械强度，容易发生翘曲和碎片等现象。晶圆片出厂再打磨(以使其减薄)也容易引入颗粒污染，降低入射光收集的量子效率。
需要提供新的结构来改进光电二极管器件或光电二极管阵列的至少一部分性能。
发明内容
有鉴于此，本公开的目的至少部分地在于提供一种具有改进性能的光电二极管器件及光电二极管探测器及其制造方法。
根据本公开的一个方面，提供了一种制造光电二极管器件的方法，包括：在衬底的第一表面上生长外延层，其中，该外延层被第一类型轻掺杂，且在衬底中形成与该第一类型轻掺杂的外延层相接触的第一类型重掺杂区；从衬底的与第一表面相对的第二表面一侧，减薄衬底，并露出第一类型重掺杂区；从衬底的第二表面一侧，对第一类型重掺杂区进行构图，以在其中形成沟槽，该沟槽穿透第一类型重掺杂区而进入外延层中，其中，构图后的第一类型重掺杂区充当光电二极管器件的第一电极区域；以及在沟槽底部形成第二类型重掺杂的区域，该区域充当光电二极管器件的第二电极区域。
根据本公开的另一方面，提供了一种光电二极管器件，包括：第一类型重掺杂的衬底，包括彼此相对的第一表面和第二表面，该第一类型重掺杂的衬底充当光电二极管器件的第一电极区域；在衬底的第一表面上生长的外延层，其中，该外延层被第一类型轻掺杂，且衬底中包括沟槽以露出外延层；以及在沟槽内形成的第二类型重掺杂的第二电极区域，其中，该第二电极区域与第一电极区域电隔离。
根据本公开的另一方面，提供了一种光电二极管探测器，包括由多个上述光电二极管器件构成的阵列。
根据本公开的实施例，一方面，器件的总体厚度可以相对较厚，以保持一定的机械强度；另一方面，第二电极区域可以相对凹入，从而可以改进电荷收集效率。
附图说明
通过以下参照附图对本公开实施例的描述，本公开的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1A是示出了根据本公开实施例的光电二极管探测器的俯视图；
图1B是示出了沿图1A所示的AA′线的截面图；
图2A-2J是示出了根据本公开实施例的制造图1A和1B所示的光电二极管探测器的流程中部分阶段的截面图；
图3是示出了根据本公开另一实施例的光电二极管探测器的截面图；
图4A-4I是示出了根据本公开实施例的制造图3所示的光电二极管探测器 的流程中部分阶段的截面图；
图4J是示出了根据本公开另一实施例的接触部的截面图；
图5是示出了根据本公开另一实施例的光电二极管探测器的截面图；
图6A-6I是示出了根据本公开实施例的制造图5所示的光电二极管探测器的流程中部分阶段的截面图；
图6J是示出了根据本公开另一实施例的接触部的截面图。
贯穿附图，相同或相似的附图标记表示相同或相似的部件。
具体实施方式
以下，将参照附图来描述本公开的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在本公开的上下文中，当将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中层/元件。另外，如果在一种朝向中一层/元件位于另一层/元件“上”，那么当调转朝向时，该层/元件可以位于该另一层/元件“下”。
图1A是示出了根据本公开实施例的光电二极管探测器的俯视图，且图1B是示出了沿图1A所示的AA′线的截面图。
如图1A和1B所示，根据该实施例的光电二极管探测器100可以包括在半导体基板101上形成的多个光电二极管器件Pix，每个光电二极管器件Pix可以构成光电二极管探测器100的一个像素。半导体基板101可以包括各种合适的半导体材料，例如是单晶片(例如，硅(Si)晶片)或者外延片(在晶片上包括外延层，例如，在Si晶片上包括Si外延层)。半导体基板101包括彼 此相对的两个表面：第一表面101-1S和第二表面101-2S。
半导体基板101可以掺杂为合适的导电类型，例如第一类型(例如，N型)。在此，根据掺杂浓度的不同，半导体基板101可以包括不同的区域101-1和101-2。例如，在单晶片的情况下，101-1可以是该晶片中相对重掺杂的掺杂区，而101-2可以是该晶片中相对轻掺杂的掺杂区。在外延片的情况下，101-1可以是相对重掺杂的晶片，而101-2可以是在晶片101-1上生长的相对轻掺杂的外延层。
第一类型重掺杂区101-1可以充当光电二极管器件Pix的第一电极区域103。另外，在第一表面101-1S一侧，光电二极管器件Pix还可以包括第二电极区域105。在此，第二电极区域105可以被掺杂为与半导体基板101不同的导电类型，例如第二类型(例如，P型)，从而与半导体基板101特别是其中的区域101-2构成PN结。于是，在第一类型为N型且第二类型为P型的情况下，第二电极区域105可以构成光电二极管器件Pix的阳极，而半导体基板101通过第一电极区域103引出从而可以构成光电二极管器件Pix的阴极。根据本公开的实施例，第一电极区域103和第二电极区域105可以重掺杂。但是，由于存在轻掺杂区101-2，从而避免了两个重掺杂区域直接相邻，并因此可以抑制隧穿效应。
例如，在单晶片的情况下，半导体基板101的厚度可以为约200-400μm，且第一电极区域103的厚度可以为约10-100μm；另外，在外延片的情况下，外延层101-2的厚度可以为约50-150μm，且第一电极区域103的厚度可以为约10-150μm。第二电极区域105的厚度可以为约0.5-5μm。第一电极区域103与第二电极区域105可以彼此电隔离，例如它们之间的间距可以为约10-100μm。
入射光可以从第二表面101-2S处入射到光电二极管器件Pix上。光电二极管器件Pix可以工作于反偏模式。此时，在像素中的光收集有源区(入射面101-2S附近的区域)附近可以形成反偏条件下较宽的空间电荷区。备选地，光电二极管器件Pix也可以工作于零偏模式。此时，在像素中的光收集有源区附近可以形成零偏条件下较窄的内建空间电荷区。可以在第一电极区域103和第二电极区域105处分别引出电极，以便施加偏压和/或读出信号。
入射光可以在光收集有源区中与半导体基板101(特别是区域101-2)中 的硅原子发生碰撞电离，从而产生电子-空穴对。电子可以在内建电场或外加偏置电场作用下，向第一电极区域103漂移或扩散，并最终被第一电极区域103收集。另外，空穴可以在内建电场或外加偏置电场作用下，向第二电极区域105漂移或扩散，并最终被第二电极区域105收集。可以从第二电极区域105读出电信号，并据此得到有关入射光的信息(例如，入射光的强度)。
根据本公开的实施例，第二电极区域105相对于第一电极区域103可以更靠近第二表面101-2S一侧。这样，可以减小空穴载流子与其收集机构之间的距离，从而可以加快空穴载流子的吸收，并可以降低半导体基板缺陷对载流子的捕获，从而提高光响应输出电流。另一方面，光电二极管探测器100整体的厚度仍然可以保持相对较大，从而可以保持一定的机械强度。这例如可以通过在第一表面101-1S一侧使得第二电极区域105凹入来实现。如下所述，这种凹入可以是沟槽结构。
在此，各区域中的掺杂可以通过离子注入、在外延生长时原位掺杂等方式来形成。本领域技术人员知道多种手段来在半导体基板的限定区域中/上形成一定类型的掺杂区。光电二极管器件Pix的第一电极区域103可以围绕第二电极区域105。另外，在光电二极管探测器100中，各光电二极管器件Pix的第一电极区域103可以彼此连接从而形成一体。各光电二极管器件Pix的第二电极区域105可以彼此分离，并例如按行和列排列成阵列形式。
在此，所谓“重掺杂”和“轻掺杂”是相对而言的。例如，“重掺杂”是指掺杂浓度在约1×1017cm-3以上，而“轻掺杂”是指掺杂浓度在约1×1017cm-3以下。另外，第一类型轻掺杂区101-2可以保持高阻，例如电阻率在约100-8×103Ω·cm。为进行第一类型(例如，N型)掺杂，可以使用N型掺杂剂如磷(P)或砷(As)；为进行第二类型(例如，P型)掺杂，可以使用P型掺杂剂如硼(B)。
在第二表面101-2S一侧，可形成较薄的一层第一类型重掺杂区107。例如，该第一类型重掺杂区107的厚度为约0.2-1μm。通过该薄层的第一类型重掺杂区107，可以避免光生载流子被硅氧界面处存在的缺陷所复合。另外，在第一类型重掺杂区107上，可以形成绝缘层109。绝缘层109可以包括电介质材料，例如二氧化硅、氮化硅或其组合。在光电二极管探测器100中，各光电 二极管器件Pix的第二表面101-2S一侧处的第一类型重掺杂区107和绝缘层109可以连续延伸。
在第一表面101-1S一侧，可以形成钝化层111，以覆盖并保护第一电极区域103和第二电极区域105。钝化层111可以包括电介质材料，例如二氧化硅、氮化硅或其组合。钝化层111可以形成得较薄，例如以大致共形的方式在第一表面101-1S一侧形成；或者可以形成得较厚，并可以例如填满第二电极区域105所对应的沟槽。钝化层111可以在第一表面101-1S一侧连续延伸。在钝化层111中，可以形成分别与第一电极区域103和第二电极区域105相对应的贯穿钝化层111的接触孔。可以形成穿过这些接触孔的电接触部113、115，从而将第一电极区域103和第二电极区域105引出，以便实现所需的电连接。电接触部113、115可以包括导电材料，例如金属如铜(Cu)、钨(W)等。在该示例中，由于光电二极管探测器100中各光电二极管器件Pix的第一电极区域103彼此连接成一体，故而可以针对该光电二极管探测器100形成到公共第一电极区域103的公共电接触部113。当然，根据光电二极管探测器100的规模和布局，可以形成一个或多个公共电接触部113。
这里需要指出的是，在图1A的俯视图中，为清楚起见，并未示出钝化层111和接触部113、115。
图2A-2J是示出了根据本公开实施例的制造图1A和1B所示的光电二极管探测器的流程中部分阶段的截面图。
如图2A所示，提供外延片形式的半导体基板101。外延片101可以包括半导体衬底101-1，例如硅晶片。该衬底101-1可以被第一类型(例如，N型)重掺杂，并包括彼此相对的两个表面(图中的上下侧表面)。在衬底101-1的上表面上，可以外延生长外延层101-2。在生长外延层101-2的同时，可以进行原位掺杂，使得外延层101-2被第一类型轻掺杂。
尽管在此以外延片为例进行描述，但是本公开不限于此。例如，可以提供单晶片101，并可以对晶片101进行第一类型(例如，N型)轻掺杂。然后，在晶片101的一侧表面处，例如可以通过接触式扩散方式，在其中形成第一类型重掺杂区101-1(其余仍然为第一类型轻掺杂的区域标记为101-2)。晶片101可以是单抛型晶片或双抛型晶片。在单抛型晶片的情况下，扩散掺杂可以在非 抛光面进行；而在双抛型晶片的情况下，扩散掺杂可以在任一表面进行。通过接触式扩散形成较厚的N+区域，可以消除背部打磨所带来的部分表面损伤。
然后，如图2B所示，可以对衬底101-1进行打磨，以减薄外延片101的厚度，例如减薄至约150-250μm。可以对打磨后的表面进行抛光，例如化学腐蚀抛光，以便后继对该表面进行加工。
根据本公开的实施例，可以根据外延层的厚度，确定减薄后衬底的厚度。例如，当外延层较厚(例如，大于约100μm)时，可以将衬底的厚度减薄为较小(例如，小于约50μm)；而当外延层较薄(例如，小于约50μm)时，可以将衬底的厚度减薄为较大(例如，大于约100μm)。另一方面，可以使半导体基底101的总厚度保持为约150-250μm。
另外，由于对第一类型重掺杂的衬底101-1研磨，而并不研磨外延层101-2，所以可以降低颗粒污染对量子效率的影响。
第一类型重掺杂的衬底101-1随后可以用作光电二极管器件的第一电极区域。可以根据阵列布局，对第一类型重掺杂的衬底101-1构图，以在其中形成供形成第二电极区域用的沟槽。为了使得第二电极区域与外延层101-2相接触而形成PN结且更好地与第一电极区域相分离，沟槽可以穿透第一类型重掺杂的衬底101-1，并进入第一类型轻掺杂的外延层101-2中。然后，可以在沟槽内，例如在沟槽底部，形成第二电极区域。
这例如可以如下实现。
具体地，如图2C所示，可以通过例如热氧化，在外延片101的相对表面(图2C中的上下两侧表面)上均形成氧化层121。然后，可以通过光刻技术，在衬底101-1一侧的表面(在图2C中，下表面)处的氧化层121中形成一系列开口，这些开口对应于随后将要形成的第二电极区域的位置。下表面处形成有开口的氧化层121随后可以用作刻蚀沟槽时的掩模层，而上表面处的氧化层121随后可以在刻蚀沟槽过程中保护上表面。
然后，如图2D所示，可以对外延片101进行刻蚀，如湿法腐蚀。例如，可以将外延片101浸入硅腐蚀溶液如KOH、TMAH或者HF-HNO3中。由于下表面处的氧化层121中的开口，在下表面一侧会腐蚀出沟槽T。由于湿法腐蚀，沟槽T的截面可以呈现出从下表面一侧向着上表面一侧渐缩的形状。根 据本公开的实施例，可以控制腐蚀的时间，使得沟槽T的深度超过第一类型重掺杂的衬底101-1的厚度(例如，沟槽T的深度要大于第一类型重掺杂的衬底101-1的厚度约5-10μm)，从而沟槽T穿透第一类型重掺杂的衬底101-1而进入第一类型轻掺杂的外延层101-2中。构图后的第一类型重掺杂的衬底101-1随后可以用作第一电极区域103。
接着，如图2E所示，可以通过例如热氧化，在外延片101的上下表面处均形成氧化层123。在此，为方便起见，将氧化层123示出为与氧化层121一体。根据本公开的实施例，可以通过清洗去除氧化层121，然后再通过热氧化形成氧化层123；或者，可以不去除氧化层121，而直接通过热氧化形成氧化层123(此时，氧化层121可能加厚)。通过这种热氧化工艺，可以去除沟槽T的侧壁由于腐蚀而产生的毛刺或损伤，进一步使沟槽侧壁光滑。
随后，可以对氧化层进行构图，以至少部分地露出沟槽底部区域。例如，如图2F所示，可以通过光刻，在下表面一侧形成的氧化层121/123中将要形成第二电极区域的位置处形成一系列开口。为了更好地与第一电极区域相分离，这些开口例如可以形成于各沟槽底部的大约中部，且开口的端部可以相对于相应的沟槽侧壁向内缩进。接着，如图2G所示，可以经氧化层121/123中的开口，通过离子注入(例如，注入B或BF2)，在下表面一侧形成第二类型重掺杂区105(可以退火以激活注入的离子)，其随后可以用作第二电极区域。之后，可以通过清洗去除氧化层121/123。
另外，如图2H所示，还可以在外延层101-2背对衬底101-1一侧的表面上，通过离子注入(例如，注入P或As，注入深度为约0.2-1μm)，形成第一类型重掺杂区107。另外，在第一类型重掺杂区107上可以形成绝缘层109。例如，可以通过热氧化，在第一类型重掺杂区107上形成一薄层氧化物。在热氧化过程中，还可以激活所注入的杂质离子。
此外，如图2I所示，还可以在下表面一侧形成钝化层111以便覆盖第一电极区域103和第二电极区域105。例如，可以通过淀积如化学气相淀积(CVD)，在下表面一侧形成二氧化硅层。在该示例中，所淀积的二氧化硅层111相对较薄，从而以大致共形的方式形成于下表面一侧(具有与下方结构基本上相同或相似的起伏)。
可以制作到第一电极区域103和第二电极区域105的接触部113、115，以将它们引出。例如，如图2J所示，可以通过光刻，在钝化层111中与第一电极区域103和第二电极区域105相对应的位置处形成贯穿钝化层111的接触孔。然后，可以在钝化层111上形成导电材料如金属，导电材料填充接触孔，并因此与第一电极区域103和第二电极区域105连接。可以通过光刻将导电材料构图为分离的电极。
图3是示出了根据本公开另一实施例的光电二极管探测器的截面图。
如图3所示，根据该实施例的光电二极管探测器可以包括在半导体基板301上形成的多个光电二极管器件。如上所述，半导体基板301可以是外延片，包括第一类型重掺杂的衬底301-1(厚度例如为约150-350μm)以及在衬底301-1上生长的第一类型轻掺杂的外延层301-2(厚度例如为约20-50μm)。衬底301-1可以充当光电二极管器件的第一电极区域303，且每个光电二极管器件还可以包括第二电极区域305。第二电极区域305可以是第二类型重掺杂的(厚度例如为约0.5-5μm)。
在外延层301-2背对衬底301-1的表面一侧，可以形成第一类型重掺杂区307和绝缘层309。另外，在衬底301-1一侧，可以形成钝化层311。接触部313和315可以穿过钝化层311，分别与第一电极区域303和第二电极区域305电连接。关于这些部件，可以参见以上描述。在该示例中，钝化层311形成得较厚，且可以具有实质上平坦的表面。
图4A-4I是示出了根据本公开实施例的制造图3所示的光电二极管探测器的流程中部分阶段的截面图。
如图4A所示，提供外延片301，例如硅外延片。外延片301可以包括第一类型重掺杂的衬底301-1以及在衬底301-1上生长的外延层301-2。对衬底301-1进行打磨至外延片301的总厚度为约150-250μm。如上所述，可以根据外延层的厚度，确定减薄后衬底的厚度。
如图4B所示，可以通过例如热氧化，在外延片301的相对表面(图4B中的上下表面)上均形成氧化层321。然后，可以通过光刻技术，在衬底301-1一侧的表面(在图4B中，下表面)处的氧化层321中形成一系列开口，这些开口对应于随后将要形成的第二电极区域的位置。
然后，如图4C所示，可以对外延片301进行刻蚀，如湿法腐蚀。由于下表面处的氧化层321中的开口，在下表面一侧会腐蚀出沟槽T。如上所述，沟槽T的截面可以呈现出从下表面一侧向着上表面一侧渐缩的形状。同样地，沟槽T的深度可以超过第一类型重掺杂的衬底301-1的厚度(例如，沟槽T的深度要大于第一类型重掺杂的衬底301-1的厚度约5-10μm)，从而沟槽T穿透第一类型重掺杂的衬底301-1而进入第一类型轻掺杂的外延层301-2中。构图后的第一类型重掺杂的衬底301-1随后可以用作第一电极区域303。
接着，如图4D所示，可以通过例如热氧化，在外延片301的上下表面处均形成氧化层323。在此，为方便起见，将氧化层323示出为与氧化层321一体。通过这种热氧化工艺，可以去除沟槽T的侧壁由于腐蚀而产生的毛刺或损伤，进一步使沟槽侧壁光滑。
随后，如图4E所示，可以通过光刻，在下表面一侧形成的氧化层321/323中将要形成第二电极区域的位置处形成一系列开口。接着，如图4F所示，可以经氧化层321/323中的开口，通过离子注入，在下表面一侧形成第二类型重掺杂区305(可以退火以激活注入的离子)，其随后可以用作第二电极区域。之后，可以通过清洗去除氧化层321/323。
另外，如图4G所示，还可以在下表面一侧的表面上形成钝化层311以便覆盖第一电极区域303和第二电极区域305。在该示例中，所淀积的二氧化硅层311相对较厚，从而可以完成填满沟槽，并超出外延片301的下表面。可以对钝化层311进行平坦化处理例如化学机械抛光(CMP)。
此外，如图4H所示，还可以在外延层301-2背对衬底301-1一侧的表面上，通过离子注入，形成第一类型重掺杂区307。另外，在第一类型重掺杂区307可以形成绝缘层309。例如，可以通过热氧化，在第一类型重掺杂区307上形成一薄层氧化物。在热氧化过程中，还可以激活所注入的杂质离子。
可以制作到第一电极区域303和第二电极区域305的接触部313、315，以将它们引出。例如，如图4I所示，可以通过光刻，在钝化层311中与第一电极区域303和第二电极区域305相对应的位置处形成贯穿钝化层311的接触孔。然后，可以在钝化层311上形成导电材料如金属，导电材料填充接触孔，并因此与第一电极区域303和第二电极区域305连接。可以通过光刻将导电材 料构图为分离的电极。
根据本公开的另一实施例，如图4J所示，在钝化层311中形成接触孔之后，可以在其中生长第二类型重掺杂的半导体材料如多晶硅。可以通过光刻将半导体材料构图为分离的部分315′。然后，可以在钝化层311上形成电介质层311′。按照以上类似的方式，可以在电介质层311′中形成分别与第一电极区域303和掺杂半导体315′电连接的接触部313、315。这可以避免在深接触孔中填充金属的困难。
尽管图4J的示例中，将到第一电极区域303的接触部313示出为由金属材料一体形成，但是本公开不限于此。例如，该接触部313可以按照与接触部315相同的方式形成，从而也可以包括掺杂半导体和金属的叠层结构。
图5是示出了根据本公开另一实施例的光电二极管探测器的截面图。
如图5所示，根据该实施例的光电二极管探测器可以包括在半导体基板501上形成的多个光电二极管器件。如上所述，半导体基板501可以是外延片，包括第一类型重掺杂的衬底501-1(厚度例如为约150-350μm)以及在衬底501-1上生长的第一类型轻掺杂的外延层501-2(厚度例如为约20-50μm)。衬底501-1可以充当光电二极管器件的第一电极区域503，且每个光电二极管器件还可以包括第二电极区域505。第二电极区域505可以是第二类型重掺杂的(厚度例如为约0.5-5μm)。
在外延层501-2背对衬底501-1的表面一侧，可以形成第一类型重掺杂区507和绝缘层509。在衬底501-1一侧，可以形成钝化层511。接触部513和515可以穿过钝化层511，分别与第一电极区域503和第二电极区域505电连接。关于这些部件，可以参见以上描述。
该实施例的构造与以上图3中所示的构造大致相同，但是用来形成第二电极区域505的沟槽具有大致竖直的侧壁。
图6A-6I是示出了根据本公开实施例的制造图5所示的光电二极管探测器的流程中部分阶段的截面图。
如图6A所示，提供外延片501，例如硅外延片。外延片501可以包括第一类型重掺杂的衬底501-1以及在衬底501-1上生长的外延层501-2。对衬底501-1进行打磨至外延片501的总厚度为约150-250μm。如上所述，可以根据 外延层的厚度，确定减薄后衬底的厚度。
如图6B所示，可以通过例如热氧化，在外延片501的相对表面(图6B中的上下表面)上均形成氧化层521。然后，可以通过光刻技术，在衬底501-1一侧的表面(在图6B中，下表面)处的氧化层521中形成一系列开口，这些开口对应于随后将要形成的第二电极区域的位置。
然后，如图6C所示，可以对外延片501进行刻蚀。由于下表面处的氧化层521中的开口，在下表面一侧会刻蚀出沟槽T。在此，可以利用干法刻蚀如反应离子刻蚀(RIE)。于是，沟槽T可以具有大致竖直的侧壁。同样地，沟槽T的深度可以超过第一类型重掺杂的衬底501-1的厚度(例如，沟槽T的深度要大于第一类型重掺杂的衬底501-1的厚度约5-10μm)，从而沟槽T穿透第一类型重掺杂的衬底501-1而进入第一类型轻掺杂的外延层501-2中。构图后的第一类型重掺杂区随后可以用作第一电极区域503。
接着，如图6D所示，可以通过例如热氧化，在外延片501的上下表面处均形成氧化层523。在此，为方便起见，将氧化层523示出为与氧化层521一体。通过这种热氧化工艺，可以去除沟槽T的侧壁由于腐蚀而产生的毛刺或损伤，进一步使沟槽侧壁光滑。
随后，如图6E所示，可以通过以大致垂直于基板表面501-1S的方向进行RIE，去除氧化层521/523的横向延伸部分，而留下其竖直延伸部分。于是，沟槽T的侧壁被氧化层523所覆盖，而其底部可以露出。接着，如图6F所示，可以通过离子注入，在下表面一侧形成第二类型重掺杂区505(可以退火以激活注入的离子)，其随后可以用作第二电极区域。之后，可以通过清洗去除氧化层521/523。
另外，如图6G所示，还可以在下表面一侧形成钝化层511以便覆盖第一电极区域503和第二电极区域505。在该示例中，所淀积的二氧化硅层511相对较厚，从而可以完成填满沟槽，并超出外延片501的第二表面501-1S。可以对钝化层511进行平坦化处理如CMP。
此外，如图6H所示，还可以在外延层501-2背对衬底501-1一侧的表面上，通过离子注入，形成第一类型重掺杂区507。另外，在第一类型重掺杂区507可以形成绝缘层509。例如，可以通过热氧化，在第一类型重掺杂区507 上形成一薄层氧化物。在热氧化过程中，还可以激活所注入的杂质离子。
可以制作到第一电极区域503和第二电极区域505的接触部513、515，以将它们引出，如图6I所示。或者，如图6J所示，可以形成掺杂半导体515′和金属515的叠层结构的接触部。对此，可以参见以上的描述。
在以上实施例中，仅对于到第二电极区域的接触部形成叠层结构。但是，本公开不限于此。例如，对于到第一电极区域的接触部，也可以类似地形成叠层结构。
在以上的描述中，对于各层的构图、刻蚀等技术细节并没有做出详细的说明。但是本领域技术人员应当理解，可以通过各种技术手段，来形成所需形状的层、区域等。另外，为了形成同一结构，本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外，尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。
以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。本公开的范围由所附权利要求及其等价物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。

Claims (15)

  1. 一种制造光电二极管器件的方法，包括：
    在衬底的第一表面上生长外延层，其中，该外延层被第一类型轻掺杂，且在衬底中形成与该第一类型轻掺杂的外延层相接触的第一类型重掺杂区；
    从衬底的与第一表面相对的第二表面一侧，减薄衬底，并露出第一类型重掺杂区；
    从衬底的第二表面一侧，对第一类型重掺杂区进行构图，以在其中形成沟槽，该沟槽穿透第一类型重掺杂区而进入外延层中，其中，构图后的第一类型重掺杂区充当光电二极管器件的第一电极区域；以及
    在沟槽底部形成第二类型重掺杂的区域，该区域充当光电二极管器件的第二电极区域。
  2. 根据权利要求1所述的方法，其中，通过湿法腐蚀或干法刻蚀，对第一类型重掺杂区进行构图。
  3. 根据权利要求1所述的方法，其中，在沟槽底部形成第二类型重掺杂的区域包括：
    通过热氧化工艺，在第一类型重掺杂区和沟槽的表面上形成氧化层；
    对氧化层进行构图，以露出沟槽底部区域；以及
    通过离子注入，在露出的沟槽底部区域中形成第二类型重掺杂区域。
  4. 根据权利要求1所述的方法，还包括：
    在衬底的第二表面一侧形成覆盖第一电极区域和第二电极区域的钝化层；
    在钝化层中形成接触孔，以分别露出第一电极区域和第二电极区域；以及形成接触部，接触部穿过接触孔而分别与第一电极区域和第二电极区域电连接。
  5. 根据权利要求4所述的方法，其中，形成接触部包括：
    在接触孔中形成掺杂半导体材料；
    在钝化层上形成电介质层；
    在电介质层中形成与所述接触孔相对应的另外的接触孔；
    在另外的接触孔中形成导电材料，以形成到第一电极区域和第二电极区域 的导电通道。
  6. 根据权利要求1所述的方法，其中，根据外延层的厚度，确定减薄后衬底的厚度。
  7. 根据权利要求1所述的方法，还包括：
    在外延层背对衬底第一表面一侧的表面上形成第一类型重掺杂层；以及
    在该第一类型重掺杂层上形成绝缘层。
  8. 一种光电二极管器件，包括：
    第一类型重掺杂的衬底，包括彼此相对的第一表面和第二表面，该第一类型重掺杂的衬底充当光电二极管器件的第一电极区域；
    在衬底的第一表面上生长的外延层，其中，该外延层被第一类型轻掺杂，且衬底中包括沟槽以露出外延层；以及
    在沟槽内形成的第二类型重掺杂的第二电极区域，其中，该第二电极区域与第一电极区域电隔离。
  9. 根据权利要求8所述的光电二极管器件，其中，第一电极区域形成为围绕第二电极区域。
  10. 根据权利要求8所述的光电二极管器件，其中，沟槽的深度大于衬底的厚度，从而延伸进入外延层中。
  11. 根据权利要求8所述的光电二极管器件，还包括：
    在衬底的第二表面一侧形成的覆盖第一电极区域和第二电极区域的钝化层；以及
    穿透钝化层分别与第一电极区域和第二电极区域电连接的电接触部。
  12. 根据权利要求11所述的光电二极管器件，其中，到第一电极区域的电接触部和到第二电极区域的电接触部中至少之一具有掺杂半导体和金属的叠层构造。
  13. 根据权利要求8-12中任一项所述的光电二极管器件，还包括：
    在外延层背对衬底第一表面一侧的表面上形成的第一类型重掺杂层；以及
    在该第一类型重掺杂层上形成的绝缘层。
  14. 一种光电二极管探测器，包括：
    阵列，包括多个根据权利要求8-13中任一项所述的光电二极管器件。
  15. 根据权利要求14所述的光电二极管探测器，其中，各光电二极管器件的第一电极区域彼此连接在一起，而各光电二极管器件的第二电极区域彼此分离。
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Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106784071B (zh) * 2016-12-07 2018-09-28 同方威视技术股份有限公司 光电二极管器件、光电二极管探测器及其制造方法
US10854646B2 (en) * 2018-10-19 2020-12-01 Attollo Engineering, LLC PIN photodetector
DE112021006404T5 (de) * 2020-12-11 2023-09-28 Ams-Osram Ag Fotodiodenvorrichtung mit hoher Empfindlichkeit
CN113540140B (zh) * 2021-07-15 2022-12-09 上海芯物科技有限公司 背照式互补金属氧化物半导体图像传感器及其制备方法
CN114300581B (zh) * 2021-12-31 2024-05-17 北海惠科半导体科技有限公司 光敏元件的制备方法及半导体器件
CN114899268B (zh) * 2022-05-30 2024-08-02 中国科学院半导体研究所 硅光电倍增管及光电器件
CN115224150B (zh) * 2022-06-23 2025-03-07 中国科学院半导体研究所 一种硅光电倍增管及其制备方法
TWI831452B (zh) * 2022-11-01 2024-02-01 大陸商北京集創北方科技股份有限公司 吸收波長可調之感光元件、圖像採集裝置以及資訊處理裝置
CN116053289B (zh) * 2023-03-06 2023-06-27 合肥新晶集成电路有限公司 图像传感器及其制备方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050156213A1 (en) * 2003-12-31 2005-07-21 Dongbuanam Semiconductor Inc. CMOS image sensor and method for fabricating the same
CN1901239A (zh) * 2005-07-18 2007-01-24 桦晶科技股份有限公司 低寄生电容结构的贯穿式光电二极管
CN104465676A (zh) * 2014-12-09 2015-03-25 厦门大学 4H-SiC PIN紫外光电二极管一维阵列芯片及其制备方法
CN105448945A (zh) * 2015-12-29 2016-03-30 同方威视技术股份有限公司 同面电极光电二极管阵列及其制作方法
CN106784071A (zh) * 2016-12-07 2017-05-31 同方威视技术股份有限公司 光电二极管器件、光电二极管探测器及其制造方法
CN206516638U (zh) * 2016-12-07 2017-09-22 同方威视技术股份有限公司 光电二极管器件以及光电二极管探测器

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7810740B2 (en) * 2002-11-18 2010-10-12 Hamamatsu Photonics K.K. Back illuminated photodiode array, manufacturing method and semiconductor device thereof
DE102004053760A1 (de) * 2004-11-08 2006-05-11 Robert Bosch Gmbh Halbleitereinrichtung und Verfahren für deren Herstellung
DE102004059640A1 (de) * 2004-12-10 2006-06-22 Robert Bosch Gmbh Halbleitereinrichtung und Verfahren zu deren Herstellung
US20060289777A1 (en) * 2005-06-29 2006-12-28 Wen Li Detector with electrically isolated pixels
CN101714591B (zh) * 2009-11-10 2012-03-14 大连理工大学 一种硅光电二极管的制作方法
US8901697B2 (en) * 2012-03-16 2014-12-02 Analog Devices, Inc. Integrated circuit having a semiconducting via; an integrated circuit including a sensor, such as a photosensitive device, and a method of making said integrated circuit
TWM439885U (en) * 2012-04-13 2012-10-21 Taiwan Semiconductor Co Ltd Semiconductor component trench structure
JP2014120685A (ja) * 2012-12-18 2014-06-30 Toshiba Corp 半導体装置
CN104051546B (zh) * 2014-06-03 2017-05-17 无锡昕智隆电子科技有限公司 一种功率二极管的制备方法
CN106158868B (zh) * 2015-03-31 2019-04-26 中芯国际集成电路制造(上海)有限公司 掩膜式只读存储阵列、其制作方法以及存储器的制作方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050156213A1 (en) * 2003-12-31 2005-07-21 Dongbuanam Semiconductor Inc. CMOS image sensor and method for fabricating the same
CN1901239A (zh) * 2005-07-18 2007-01-24 桦晶科技股份有限公司 低寄生电容结构的贯穿式光电二极管
CN104465676A (zh) * 2014-12-09 2015-03-25 厦门大学 4H-SiC PIN紫外光电二极管一维阵列芯片及其制备方法
CN105448945A (zh) * 2015-12-29 2016-03-30 同方威视技术股份有限公司 同面电极光电二极管阵列及其制作方法
CN106784071A (zh) * 2016-12-07 2017-05-31 同方威视技术股份有限公司 光电二极管器件、光电二极管探测器及其制造方法
CN206516638U (zh) * 2016-12-07 2017-09-22 同方威视技术股份有限公司 光电二极管器件以及光电二极管探测器

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3518292A4 *

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