WO2018161657A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

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Publication number
WO2018161657A1
WO2018161657A1 PCT/CN2017/114555 CN2017114555W WO2018161657A1 WO 2018161657 A1 WO2018161657 A1 WO 2018161657A1 CN 2017114555 W CN2017114555 W CN 2017114555W WO 2018161657 A1 WO2018161657 A1 WO 2018161657A1
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Prior art keywords
shielding layer
light shielding
light
layer
substrate
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English (en)
French (fr)
Inventor
孙雪菲
李正亮
张斌
詹裕程
刘建宏
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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Priority to EP17899551.0A priority Critical patent/EP3595006A4/en
Priority to US16/066,205 priority patent/US20210167156A1/en
Publication of WO2018161657A1 publication Critical patent/WO2018161657A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6723—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device having light shields
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/20—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/36—Micro- or nanomaterials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • At least one embodiment of the present disclosure is directed to a display substrate, a method of fabricating the same, and a display device.
  • the active layer in the thin film transistor causes photo-generated carriers to increase after being irradiated with light, causing defects such as voltage drift of the display device and increase in leakage current.
  • the band corresponding to blue light has the greatest influence on the active layer, especially in the aspect of causing an increase in the leakage current of the display device.
  • a light shielding layer can be disposed in the region where the thin film transistor is located. The active layer is shielded from light.
  • the setting of the light shielding layer still fails to meet the demand, and it is easy to cause problems such as poor process.
  • At least one embodiment of the present disclosure provides a display substrate including: a substrate substrate; a thin film transistor disposed on the substrate; and a first light shielding layer and a second light shielding layer disposed on the substrate a light shielding layer; wherein an orthographic projection of the active layer of the thin film transistor on the substrate is located within an orthographic projection of the light shielding layer on the substrate, the second light shielding layer Nanoparticles to absorb light in a specific wavelength range.
  • the material of the first light shielding layer includes single crystal silicon, polycrystalline silicon or amorphous silicon.
  • the material of the second light shielding layer further includes silicon nitride or silicon carbide.
  • the thickness range of the first light shielding layer includes The thickness range of the second light shielding layer includes
  • the nanoparticles may be It is a nano silicon particle.
  • the nano silicon particles have a particle size ranging from 3 to 5 nanometers.
  • the light may be blue light, and the blue light has a wavelength range of 420 to 480 nm.
  • the first light shielding layer may be disposed on a side of the second light shielding layer away from the substrate substrate; or the second light shielding layer may be disposed. And a side of the first light shielding layer away from the substrate.
  • the thin film transistor may include a thin film transistor of a top gate type structure or a bottom gate type structure.
  • the light shielding layer when the thin film transistor is a bottom gate type structure, the light shielding layer is disposed on a side of the active layer away from the substrate; or When the thin film transistor is a top gate type structure, the light shielding layer is disposed between the base substrate and the active layer.
  • At least one embodiment of the present disclosure provides a display device including the display substrate in any of the above embodiments.
  • At least one embodiment of the present disclosure provides a method of fabricating a display substrate, including: providing a substrate; forming a thin film transistor on the substrate; forming a first light shielding layer and a second light shielding on the substrate a light shielding layer of the layer; wherein an orthographic projection of the active layer of the thin film transistor on the substrate substrate is located within an orthographic projection of the light shielding layer on the substrate substrate, the second light shielding
  • the layer includes nanoparticles to absorb light in a particular wavelength range.
  • the method of forming the second light shielding layer may include spiral wave plasma chemical vapor deposition.
  • the nanoparticles are nano silicon particles
  • forming the second light shielding layer includes: passing a reaction gas including at least nitrogen, silane, and hydrogen or at least including nitrogen, methane a reaction gas of silane and hydrogen forms a second light shielding layer film including the nano silicon particles; and the second light shielding layer film is patterned to form the second light shielding layer containing the nano silicon particles.
  • the process conditions of the spiral wave plasma chemical vapor deposition are formed when the second light shielding layer film is formed by a reaction gas including at least nitrogen, methane, silane, and hydrogen.
  • a reaction gas including at least nitrogen, methane, silane, and hydrogen.
  • the process conditions of the spiral wave plasma chemical vapor deposition may be: temperature 700 degrees Celsius; pressure 1.33 Pa, power 500 watts; magnetic induction intensity 110 Gs; hydrogen, methane
  • the volume ratio to silane is 1:2:40.
  • the light may be blue light, and the blue light has a wavelength range of 420 to 480 nm.
  • forming the light shielding layer including the first light shielding layer and the second light shielding layer on the base substrate may include: forming the first light shielding on the base substrate a layer, the second light shielding layer is formed on the first light shielding layer.
  • the light shielding layer and the active layer in the thin film transistor may be prepared in synchronization, the method comprising: sequentially forming the light shielding layer on the base substrate After the film and the thin film of the active layer, the thin film of the light shielding layer and the thin film of the active layer form the light shielding layer and the active layer using the same mask.
  • FIG. 1 is a schematic cross-sectional structural view of a display substrate according to an embodiment of the present disclosure
  • FIG. 2 is a schematic cross-sectional structural view of another display substrate according to an embodiment of the present disclosure.
  • 3a is a schematic cross-sectional structural view of another display substrate according to an embodiment of the present disclosure.
  • 3b is a schematic cross-sectional structural view of another display substrate according to an embodiment of the present disclosure.
  • 4a-4I are process diagrams of a method for preparing a display substrate according to an embodiment of the present disclosure
  • 5a-5g are process diagrams of another method for preparing a display substrate according to an embodiment of the present disclosure.
  • the conventional process generally uses a metal such as molybdenum as a material of the light shielding layer to shield the active layer in the thin film transistor, but the parasitic capacitance caused by the metal material may be relatively large, so that, for example, amorphous silicon may be used instead of the metal molybdenum to prepare a light shielding layer.
  • Amorphous silicon is a semiconductor material, and the parasitic capacitance in the thin film transistor is small, which can improve the display yield.
  • the thickness of the light shielding layer is limited.
  • the light shielding layer prepared by amorphous silicon can block or absorb part of the light on the path, and other portions of light such as part of the blue light may still pass through the light shielding layer. Therefore, it is necessary to thicken the thickness of the light shielding layer so that the absorption peak of the light shielding layer is blue-shifted, although the thickening of the light shielding layer causes the absorption peak of the light shielding layer to shift blue and reduce the transmittance of other light, but the thickness of the light shielding layer
  • the increase may cause a large step difference, and may further cause defects in subsequent fabrication processes such as thin film transistors in the display substrate.
  • At least one embodiment of the present disclosure provides a display substrate, a method of fabricating the same, and a display device.
  • the display substrate includes a base substrate, a thin film transistor disposed on the base substrate, and a light shielding layer disposed on the base substrate, the light shielding layer including at least one first light shielding layer corresponding to an active layer of the thin film transistor And a light shielding layer of at least one second light shielding layer, wherein the second light shielding layer comprises nanoparticles to absorb light in a specific wavelength range.
  • the active layer and the light shielding layer are correspondingly disposed, for example, that the orthographic projection of the active layer of the thin film transistor on the substrate substrate is located on the underlying substrate of the light shielding layer.
  • the light shielding layer can shield the active layer from light in a direction perpendicular to the substrate.
  • the adverse effect of the blue light on the active layer is obvious, so taking the light in the specific wavelength range as the blue light as an example, the technical solution in the following embodiments of the present disclosure Be explained.
  • the second light shielding layer contains nanoparticles, which can absorb the blue light transmitted through the first light shielding layer, so that the transmittance of the blue light can be reduced without increasing the thickness of the first light shielding layer (ie, it is not required)
  • the second light shielding layer may be a light absorbing layer.
  • the optical absorption spectrum of the quantum dot will appear blue-shifted.
  • the particle size (particle size) of the silicon particles is smaller, the band gap corresponding to the system composed of the silicon particles, for example, the band gap of the silicon particles is broadened, that is, the wavelength of the absorbable light is shorter,
  • the absorption peak blue shift is manifested, that is, the absorption peak of the second light shielding layer including the nano silicon particles in the above embodiment is blue-shifted, so that all or at least part of the blue light can be absorbed.
  • FIG. 1 is a cross-sectional structural view of a display substrate according to an embodiment of the present disclosure, which is a cross-sectional view.
  • the display substrate includes a base substrate 100, a thin film transistor disposed on the base substrate 100, and a light shielding layer disposed on the base substrate 100, the light shielding layer corresponding to an active layer of the thin film transistor.
  • 500 is disposed, and the light shielding layer comprises at least one first light shielding layer 200 and at least one second light shielding layer 300, wherein the second light shielding layer (eg, light absorption layer) 300 comprises nano silicon particles to absorb in a specific wavelength range Blu-ray.
  • the thin film transistor may include an active layer 500, a gate insulating layer 600, a gate electrode 700, an insulating layer 800, a source/drain electrode layer 900, and the like, wherein the source/drain electrode layer 900 includes a source electrode 910 and a drain electrode 920.
  • the thickness of the first light shielding layer 200 may be approximately
  • the thickness of the second light shielding layer may be approximately
  • the first light shielding layer 200 within this thickness range may still transmit part of the blue light.
  • the thickness of the first light shielding layer 200 is And the first light shielding layer 200 of this thickness may pass through part of the blue light, and adopt First light shielding layer 200 and The second light shielding layer 300 can obtain the technical effect of absorbing the blue light transmitted through the first light shielding layer 200, and the total thickness of the light shielding layer including the first light shielding layer 200 and the second light shielding layer 300 is smaller than that of the first light shielding layer 200.
  • the thickness is reduced on the basis of the technical effect of obtaining the same or better filtering of blue light, and the adverse effect of the step on the subsequent preparation process of the display substrate is reduced or eliminated, thereby significantly improving the yield of the display substrate.
  • the second light shielding layer 300 may be configured to absorb blue light in a wavelength range having the greatest influence on the active layer 500.
  • the blue light has a wavelength range of about 420 to 480 nanometers.
  • the second light shielding layer 300 may be configured to absorb light having a wavelength in the range of about 435 to 450 nanometers.
  • the second light shielding layer 300 absorbs blue light having a wavelength range of 420 to 480 nanometers (eg, 435 to 450 nanometers), and the nano silicon particles are required to have a particle size ranging from about 3 to 5 nanometers.
  • the light absorption peak of the second light shielding layer 300 is blue-shifted as the particle diameter of the nano silicon particles decreases, so if it is necessary to absorb light in a shorter wavelength range, the particle size of the nano silicon particles can be Set to, for example, less than 3 nanometers.
  • the embodiment of the present disclosure does not limit the specific shape of the silicon particles.
  • the shape of the silicon particles may be spherical or approximately spherical, or may be rod-shaped or the like.
  • the order in which the first light shielding layer 200 and the second light shielding layer 300 are stacked is not limited, and the positions of the two may be interchanged.
  • the second light shielding layer 300 is disposed on the first light shielding layer 200 , that is, the second light shielding layer 300 is disposed on a side of the first light shielding layer 200 away from the substrate 100 ; for example, the first The light shielding layer 200 may also be disposed on the second light shielding layer 300, that is, the first light shielding layer 200 is disposed on a side of the second light shielding layer 300 away from the substrate 100; for example, the first light shielding layer 200 included in the light shielding layer.
  • the first light shielding layer 200 and the second light shielding layer 300 may be alternately stacked.
  • the embodiment of the present disclosure does not limit the material for preparing the second light shielding layer 300.
  • the preparation material of the second light shielding layer 300 may further include silicon nitride or silicon carbide, etc., as long as the second light shielding layer 300 may be provided with nano silicon particles that meet the requirements of the above embodiments.
  • the second light shielding layer 300 can absorb the blue light transmitted through the first light shielding layer 200.
  • the preparation material of the first light shielding layer 200 may include single crystal silicon, polycrystalline silicon or amorphous silicon, etc., for example, may also include gallium arsenide, gallium aluminum arsenide, indium phosphide, cadmium sulfide. , cadmium telluride and so on.
  • amorphous silicon can be used as both the first light shielding layer and the constituent material of the active layer, and both can be formed by one process, and the steps of the preparation process of the thin film transistor in the display substrate can be reduced.
  • the second light shielding layer 300 provided in the embodiment can absorb the light transmitted through the first light shielding layer 200, so that the thickness of the first light shielding layer 200 does not need to be increased to achieve the purpose of shading, so in the embodiment provided by the present disclosure,
  • the material of the first light shielding layer may not be limited.
  • the type and specific structure of the thin film transistor in the display substrate are not limited.
  • the light shielding layer including the first light shielding layer 200 and the second light shielding layer 300 can be simultaneously applied to the top gate type and bottom gate type thin film transistors.
  • the light shielding layers including the first light shielding layer 200 and the second light shielding layer 300 may have different arrangement positions.
  • the thin film transistor is a bottom gate type structure, and a light shielding layer including the first light shielding layer 200 and the second light shielding layer 300 may be disposed on a side of the active layer 500 away from the substrate substrate; for example, the thin film transistor is a top gate
  • the type structure, the light shielding layer including the first light shielding layer 200 and the second light shielding layer 300 may be disposed between the base substrate 100 and the active layer 500.
  • the thin film transistor in the display substrate is a top gate type thin film transistor.
  • a light shielding layer including at least one first light shielding layer 200 and at least one second light shielding layer 300, an active layer 500, a gate insulating layer 600, a gate electrode 700, and insulation are sequentially disposed on the base substrate 100.
  • the layer 800 and the source-drain electrode layer 900, wherein the source electrode 910 and the drain electrode 920 of the source-drain electrode layer 900 may pass through, for example, via holes (not shown in the drawing, refer to the via 1 in FIG. 4h of the following embodiment) It is electrically connected to the active layer 500.
  • the top gate type thin film transistor needs to avoid the light of the side of the active layer 500 close to the substrate 100 from illuminating the active layer 500, so the light shielding layer including the first light shielding layer 200 and the second light shielding layer 300 needs to be disposed. Between the base substrate 100 and the active layer 500.
  • the top gate type thin film transistor in the display substrate may further include a buffer layer 400 serving as a transition film layer between the base substrate 100 and the active layer 500, which may be activated.
  • the bonding between the layer 500 and the base substrate 100 is more stable, and harmful impurities, ions, and the like in the base substrate 100 can be prevented from diffusing into the active layer 500.
  • the material for preparing the buffer layer 400 may include silicon oxide (SiOx) or silicon nitride (SiNx), silicon oxynitride (SiOxNy), or the like.
  • the buffer layer 400 may also be a single layer structure composed of silicon nitride or silicon oxide, or a double layer or multilayer structure composed of silicon nitride and silicon oxide.
  • the thin film transistor in the display substrate is a bottom gate type thin film transistor.
  • 2 is a cross section of another display substrate according to an embodiment of the present disclosure Schematic diagram of the surface structure, which is a sectional view.
  • a gate electrode 700, a gate insulating layer 600, an active layer 500, a source/drain electrode layer 900, a passivation layer 1000, and at least one first light shielding layer 200 and at least one layer are disposed on the base substrate 100.
  • the gate electrode 700 may function as a light-shielding, but the side away from the substrate 100 may be exposed to light, so the first light-shielding layer 200 is included.
  • the light shielding layer of the second light shielding layer 300 may be disposed on a side of the active layer 500 away from the base substrate 100 to thereby shield the active layer 500 from light.
  • the display substrate may further include a first electrode layer electrically connected to a source electrode or a drain electrode of the thin film transistor, and the display substrate may further include other different types of structures for application to liquid crystal display, organic LED display and electronic paper display, etc.
  • the structure of the display substrate will be further described based on the case where the thin film transistors in the display substrate are respectively a top gate type and a bottom gate type thin film transistor.
  • FIG. 3 is a cross-sectional structural view of another display substrate according to an embodiment of the present disclosure, which is a cross-sectional view showing that the thin film transistor in the substrate is a top gate structure.
  • the display substrate further includes a passivation layer 1000 and a first electrode layer 1010 disposed over the source/drain electrode layer 900, such as the first electrode layer 1010, for example It can be a pixel electrode.
  • the first electrode layer 1010 may be electrically connected to, for example, the drain electrode 920 in the source/drain electrode layer 900 through a via hole (not shown in the drawing, referring to the via 1 in FIG. 4h) provided in the passivation layer 1000.
  • the thin film transistor is a top gate type structure, and a side of the active layer 500 remote from the base substrate 100 may be shielded by the gate electrode 700.
  • the light shielding layer including the first light shielding layer 200 and the second light shielding layer 300 may be disposed between the base substrate 100 and the active layer 500, for example, to shield the light from the other side of the active layer 500.
  • the light shielding layer including the first light shielding layer 200 and the second light shielding layer 300 may be disposed on the active layer.
  • the side of the 500 that is away from the base substrate 100, for example, the first light shielding layer 200 and the second light shielding layer 300 may be disposed on the passivation layer 1000 to shield the active layer 500 from light.
  • the display substrate may further include a plurality of arrayed sub-pixel regions, wherein each of the sub-pixel regions may include a gate line, a data line, the first electrode layer and the thin film transistor described above, and the like.
  • the gate lines and the data lines in the display substrate cross each other to define a sub-pixel region, and for example, the data lines are electrically connected to, for example, source electrodes in the source-drain electrode layer,
  • An electrode layer (pixel electrode) is electrically connected to, for example, a drain electrode in the source/drain electrode layer.
  • the material of the passivation layer 1000 may be one or a combination of silicon nitride (SiNx), silicon oxide (SiOx), and an acrylic resin.
  • the first electrode layer (pixel electrode) 1010 may be formed of a transparent conductive material or a metal material.
  • the material forming the first electrode layer 1010 may include indium tin oxide (ITO), indium zinc oxide (IZO), and oxidation.
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • IGO Indium gallium
  • GZO gallium zinc oxide
  • ZnO zinc oxide
  • AZO aluminum zinc oxide
  • carbon nanotubes carbon nanotubes.
  • the display substrate may further include an organic light emitting device
  • the first electrode layer 1010 may be an anode or a cathode of the organic light emitting device such as an organic light emitting diode.
  • the organic light emitting device further includes a second electrode layer 1030 disposed on the first electrode layer 1010 and a light emitting layer 1020 disposed between the first electrode layer 1010 and the second electrode layer 1030.
  • one of the first electrode layer 1010 and the second electrode layer 1030 is an anode
  • the other of the first electrode layer 1010 and the second electrode layer 1030 is a cathode.
  • FIG. 3b is a cross-sectional structural view of another display substrate according to an embodiment of the present disclosure, which is a cross-sectional view showing that the thin film transistor in the substrate is a bottom gate type structure.
  • the display substrate further includes a passivation layer 1000 disposed on the source/drain electrode layer 900 and a first electrode electrically connected to the drain electrode 920 of the source/drain electrode layer 900.
  • An electrode layer 1010 for example, the first electrode layer 1010 is an anode, but embodiments of the present disclosure are not limited thereto.
  • the display substrate may further include a pixel defining layer 1100 disposed on the passivation layer 1000 and an organic light emitting device, such as an anode or a cathode of the organic light emitting device.
  • the pixel defining layer 1100 may define a pixel unit region and prepare, for example, portions of the organic light emitting device in a region defined by the pixel defining layer 1100.
  • the organic light emitting device may further include a second electrode layer 1030 disposed opposite to the first electrode layer 1010 and a light emitting layer 1020 disposed between the first electrode layer 1010 and the second electrode layer 1030. More specifically, the organic light emitting device may further include a hole transport layer, a hole injection layer, an electron transport layer, and an electron injection layer.
  • the order of arrangement of the structures in the organic light-emitting device may be: an anode, a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, an electron injection layer, and a cathode.
  • the thin film transistor has a bottom gate type structure, and a side of the active layer 500 close to the base substrate 100 may be shielded by the gate electrode 700.
  • the light shielding layer of the first light shielding layer 200 and the second light shielding layer 300 may be disposed, for example, to illuminate the light shielding the other side of the active layer 500.
  • the light shielding layer may be disposed on a side of the passivation layer 1000 away from the active layer 500, or the light shielding layer may also be disposed on a side of the pixel defining layer 1100 away from the active layer.
  • At least one embodiment of the present disclosure provides a display device including the display substrate in any of the above embodiments.
  • the display device may be a liquid crystal display panel, for example, the liquid crystal display panel may include an array substrate and an opposite substrate, which are opposed to each other to form a liquid crystal cell, and are filled in the liquid crystal cell. There are liquid crystal materials.
  • the counter substrate may be, for example, a color filter substrate.
  • the pixel electrode and the common electrode of each pixel unit of the array substrate are used to apply an electric field to control the degree of rotation of the liquid crystal material to perform a display operation.
  • the display device may be an organic light emitting diode (OLED) display panel, wherein a stack of organic light emitting materials may be formed in a sub-pixel region of the display panel, each of the sub-pixel units
  • the pixel electrode serves as an anode or a cathode for driving the organic light-emitting material to emit light for a display operation.
  • the display device may be an electronic paper display panel, wherein an electronic ink layer may be formed on the display substrate of the display panel, and the pixel electrode of each sub-pixel unit is used for application.
  • the voltage that drives the charged microparticles in the electronic ink to move for display operation may be an electronic paper display panel, wherein an electronic ink layer may be formed on the display substrate of the display panel, and the pixel electrode of each sub-pixel unit is used for application. The voltage that drives the charged microparticles in the electronic ink to move for display operation.
  • the display device can be configured as a display panel with a touch function, and can also be applied to any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • At least one embodiment of the present disclosure provides a method of fabricating a display substrate, the method comprising: providing a substrate; forming a thin film transistor on the substrate; forming an active corresponding to the thin film transistor on the substrate
  • the layer includes a light shielding layer of at least one first light shielding layer and at least one second light shielding layer, and the second light shielding layer includes nanoparticles to absorb light in a specific wavelength range.
  • the method of forming the second light shielding layer may include spiral wave plasma chemical vapor deposition.
  • Spiral wave plasma chemical vapor deposition technology can produce high-density plasma under low pressure conditions, and plasma generation generally does not require high confined magnetic fields. This technology requires simpler equipment and lower cost, so for example, preparation
  • the second light-shielding layer of nano-silicon particles is more suitable for industrial production.
  • the nanoparticles may be nano silicon particles
  • the method of forming the second light shielding layer may include: forming a nano silicon containing particle by a reaction gas including at least nitrogen, silane, and hydrogen. a second light shielding layer film; or forming a second light shielding layer film containing nano silicon particles by a reaction gas including at least nitrogen, methane, silane, and hydrogen; and patterning the second light shielding layer film to form the nano silicon containing particles The second light shielding layer.
  • the particle diameter of the nanoparticles can be adjusted by controlling the amount of nitrogen injection.
  • the first light shielding layer may be formed on a side of the second light shielding layer away from the substrate substrate; or the second light shielding layer may be formed on the first light shielding layer away from the liner One side of the base substrate.
  • the thin film transistor may be a bottom gate type or a top gate type structure provided in the above embodiment.
  • a preparation process of the display substrate under one of the thin film transistor structures is provided as an example.
  • an example of the present embodiment provides a process for preparing a display substrate under a top gate type thin film transistor structure
  • FIG. 4a to FIG. 4I are process diagrams of a method for preparing a display substrate according to an embodiment of the present disclosure.
  • the thin film transistor of the display substrate is of a top gate type.
  • an example of the display substrate preparation process provided by the embodiment includes the following process.
  • a base substrate 100 is provided, and a first light shielding layer film 210 is deposited on the base substrate 100.
  • the preparation material of the base substrate 100 may be transparent glass, ceramic or metal or the like.
  • the material for preparing the first light shielding layer film 210 may be, for example, single crystal silicon, polycrystalline silicon or amorphous silicon, and may be, for example, gallium arsenide, gallium aluminum arsenide, indium phosphide, cadmium sulfide, cadmium telluride or the like.
  • a second light shielding layer film 310 is deposited on the base substrate 10 on which the first light shielding layer film 210 is formed, and the second light shielding layer film 310 is formed to contain nanoparticles.
  • the second light shielding layer film 310 is formed to contain nanoparticles.
  • a process of forming nanoparticles by the second light shielding layer film 310 will be described by taking the nanoparticles as the nano silicon particles as an example.
  • the method of forming the second light shielding layer film 310 may be spiral wave plasma chemical vapor deposition.
  • the combination of the reaction gases in the spiral wave plasma chemical vapor deposition is not limited as long as nanoparticles such as nano silicon particles can be formed in the formed second light shielding layer film 310.
  • the reaction gas of the spiral wave plasma chemical vapor deposition may include a mixed gas of nitrogen, silane, and hydrogen, and the second light shielding layer film 310 including the nano silicon particles and the substrate being silicon nitride may be formed on the base substrate 100.
  • the reaction gas of the spiral wave plasma chemical vapor deposition may also be a mixed gas including nitrogen, methane, silane, and hydrogen, and a second light shielding layer film including nano silicon particles and a matrix of silicon carbide may be formed on the base substrate 100. .
  • the particle diameter of the nano-silicon particles in the second light-shielding layer film 310 can be controlled by controlling the amount of nitrogen gas injected in the reaction gas. For example, during the deposition process, the injection rate of the introduced nitrogen gas is increased, and the smaller the particle diameter of the prepared nano silicon particles, the second light shielding layer film 310 can absorb light having a shorter wavelength, that is, the second light shielding layer film 310 is opposite. The absorption peak of light is blue-shifted as the nano-silicon particles decrease.
  • the second light shielding layer film 310 may be formed to absorb blue light having a wavelength ranging from 420 to 480 nanometers, for example, to absorb blue light in a wavelength range of 435 to 450 nanometers.
  • the blue light in the above-mentioned wavelength range for example, in the wavelength range of 435 to 450 nm, has a large influence on the active layer, and the leakage current of the thin film transistor caused by the photo-generated carriers generated by the blue light irradiated to the active layer in the wavelength range is also more remarkable.
  • the nano-silicon particles have a particle size ranging from about 3 to 5 nanometers to satisfy that the second light-shielding film 310 can absorb blue light having a wavelength ranging, for example, in the range of 420 to 480 nm, particularly in the wavelength range of 435 to 450 nm.
  • a preparation process of the second light shielding layer film 310 including the nano silicon particles and the substrate being silicon carbide is taken as an example, for example, a second light shielding layer film including the particle size range of the nano silicon particles is prepared by a spiral wave plasma chemical vapor deposition technique.
  • the conditions may be, for example, a temperature range of about 650 to 750 degrees Celsius, a power of about 400 to 600 watts, a pressure low pressure of 1.33 Pa, a magnetic induction intensity of about 90 to 130 Gs, and a volume ratio of hydrogen, methane, and silane according to the prepared film layer.
  • a specific example includes: a temperature of about 700 degrees Celsius; a pressure of about 1.33 Pa, a power of about 500 watts; a magnetic induction intensity of about 110 Gs; a volume ratio of hydrogen, methane, and silane of about 1:2:40; by controlling the amount of nitrogen injected.
  • the implantation rate may be such that the nano-silicon particles in the second light-shielding layer film formed by the deposition have a particle size ranging from about 3 to 5 nanometers.
  • nano-silicon particles having a particle diameter ranging from 3 to 5 nm is a basic requirement for the second light-shielding layer to absorb blue light, but is not limited to this numerical range.
  • nano silicon particles having a particle diameter of less than 3 nm can be obtained by changing parameters of the reaction conditions, for example, by introducing more nitrogen gas. Under these conditions, the requirement for the second light shielding layer 300 to absorb blue light is also satisfied.
  • the order in which the second light shielding layer film 310 and the first light shielding layer film 210 are formed may be interchanged, and the second light shielding layer film 310 and the first light shielding layer film 210 may each be a plurality of layers, for example, the second light shielding layer film 310 and The first light shielding layer film 210 may also be laminated in a plurality of layers and overlap each other to obtain a laminate. In the case where the two are laminated, the second light shielding layer film and the first light shielding layer film are stacked on each other.
  • the order can be any arrangement.
  • a patterning process is performed on the first light shielding layer film 210 and the second light shielding layer film 310 using the same mask to form a light shielding layer including the first light shielding layer 200 and the second light shielding layer 300.
  • the patterning process may be, for example, a photolithography patterning process, which may include, for example, coating a photoresist layer on a structure layer to be patterned, exposing the photoresist layer using a mask, and developing the exposed photoresist layer.
  • a photolithography patterning process may include, for example, coating a photoresist layer on a structure layer to be patterned, exposing the photoresist layer using a mask, and developing the exposed photoresist layer.
  • the structural layer is etched using a photoresist pattern, and then the photoresist pattern is optionally removed.
  • the forming of the second light shielding layer 300 and the first light shielding layer 200 is not limited to being formed by the patterning process through the same mask plate, and the second light shielding layer film 310 and the first light shielding layer film 210 may be separately patterned to form the first The light shielding layer of the second light shielding layer 300 and the first light shielding layer 200.
  • a buffer layer 400 is deposited on the base substrate 100 on which the light shielding layer including the first light shielding layer 200 and the second light shielding layer 300 is formed.
  • the function and preparation materials of the buffer layer 400 have been provided in the above embodiments of the present disclosure, and are not described herein.
  • a thin film of semiconductor material is deposited on the buffer layer 40 and patterned to form the active layer 500.
  • materials for preparing the active layer 500 include amorphous silicon, polycrystalline silicon, indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), zinc oxide (ZnO), gallium zinc oxide (GZO), and the like.
  • a thin film of an insulating material and a thin film of a conductive material are sequentially deposited on the base substrate 100 on which the active layer 500 is formed and patterned using the same mask to form the gate insulating layer 600 and the gate electrode 700, respectively.
  • the material for preparing the gate insulating layer 600 may include silicon nitride (SiNx), silicon oxide (SiOx), aluminum oxide (Al 2 O 3 ), aluminum nitride (AlN), or other suitable materials.
  • the material of the gate electrode may be a copper-based metal, for example, copper (Cu), copper-molybdenum alloy (Cu/Mo), copper-titanium alloy (Cu/Ti), copper-molybdenum-titanium alloy (Cu/Mo/Ti), Copper-molybdenum-tungsten alloy (Cu/Mo/W), copper-molybdenum-niobium alloy (Cu/Mo/Nb), etc.; the material of the gate electrode may also be chromium
  • the base metal is, for example, a chromium-molybdenum alloy (Cr/Mo), a chrome-titanium alloy (Cr/Ti), a chromium-molybdenum-titanium alloy (Cr/Mo/Ti), or the like; the material of the gate electrode may also be aluminum or an aluminum alloy.
  • the formation of the gate insulating layer 600 and the gate electrode 700 is not limited to being formed by a patterning process through the same mask as described above, and a patterning process may be separately performed on the insulating material film and the conductive material film to form the gate insulating layer 600 and the gate electrode 700.
  • a thin film of an insulating material is deposited on the base substrate 100 to form an insulating layer 800.
  • the insulating layer 800 may be made of silicon nitride (SiNx) or silicon oxide (SiOx) or the like.
  • a via 1 is formed in the insulating layer 800 and the active layer 500 at the via 1 is exposed.
  • a thin film of a conductive material is deposited on the base substrate 100 on which the insulating layer 800 is formed and patterned to form a source/drain electrode layer 900.
  • the source/drain electrode layer 900 includes a source electrode 910 and a drain electrode 920.
  • the material of the source/drain electrode layer 900 may be a metal material, and may form a single layer or a multi-layer structure.
  • the source/drain electrode layer 900 may be a single-layer aluminum structure, a single-layer molybdenum structure, or a layer of two layers of molybdenum. A three-layer structure of aluminum.
  • the light shielding layer and the active layer can be simultaneously prepared using the same mask, thereby reducing the number of process steps.
  • the preparation process may be that after the light shielding layer (for example, the first light shielding layer 200 and the second light shielding layer 300), the buffer layer 400, and the active layer 500 are sequentially deposited, the active layer 500 is exposed once using a mask, and then The etching and stripping processes for the light shielding layer and the active layer 500 are completed, thereby reducing the masking process of the primary light shielding layer.
  • FIG. 5a-5g are process diagrams of another method for preparing a display substrate according to an embodiment of the present disclosure.
  • an example of the display substrate preparation process provided by the embodiment may include the following steps.
  • a base substrate 100 is provided, and a first light shielding layer film 210, a second light shielding layer film 310, a buffer layer film 410, and a semiconductor material film 510 are sequentially deposited on the substrate substrate 100.
  • the first light shielding layer film 210, the second light shielding layer film 310, the buffer layer film 410, and the semiconductor material film 510 are patterned by using a mask to form the first light shielding layer 200 and the second layer.
  • a gate insulating layer 600 is deposited on the base substrate 100 on which the active layer 500 is formed.
  • a thin film of a conductive material is deposited on the base substrate 100 on which the gate insulating layer 600 is formed and patterned to form a gate electrode 700.
  • an insulating layer film is deposited on the base substrate 100 to form an insulating layer 800.
  • a via 1 is formed in the insulating layer 800 and the gate insulating layer 600 and the active layer 500 at the via 1 is exposed.
  • a thin film of a conductive material is deposited on the base substrate 100 on which the insulating layer 800 is formed and patterned to form a source/drain electrode layer 900.
  • the source/drain electrode layer 900 may include a source electrode 910 and a drain electrode 920.
  • the materials, structures, and related processes of the structure of each layer in the process of preparing the substrate can be referred to the preparation method in the example shown in FIG. 4a to FIG. 4i. Make a statement.
  • the above example only shows the preparation process of the display substrate in the case where the thin film transistor is a top gate type structure.
  • the method for preparing each layer structure in the display substrate is similar to the method for preparing the thin film transistor as the bottom gate type display substrate.
  • the fabrication method of each structure in the thin film transistor can be the same as the conventional process.
  • the light shielding layer including the first light shielding layer and the second light shielding layer needs to be disposed on a side of the active layer away from the substrate, as long as the first light shielding layer and the second light shielding layer are formed to shield the active layer from light. can.
  • At least one embodiment of the present disclosure provides a display substrate, a method of fabricating the same, a display device, and may have at least one of the following beneficial effects:
  • At least one embodiment of the present disclosure provides a display substrate in which a second light shielding layer disposed in a display substrate can absorb light such as blue light in a specific wavelength range, thereby preventing an increase in photogenerated carriers of the active layer due to blue light irradiation.
  • the display device leakage current increases.
  • the second light shielding layer can absorb light such as blue light in a specific wavelength range, it is not necessary to increase the thickness of the first light shielding layer to make the first light shielding layer The absorption peak is blue-shifted, and the defect of the subsequent preparation process of the display substrate caused by the large step difference caused by thickening the first light-shielding layer is improved.
  • At least one embodiment of the present disclosure provides a method of fabricating a display substrate, in which a light shielding layer including a first light shielding layer and a second light shielding layer may be prepared in the same mask process as the active layer. Reduce process steps and reduce costs.

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Abstract

一种显示基板及其制备方法、显示装置。该显示基板包括：衬底基板(100)、设置于衬底基板(100)上的薄膜晶体管以及设置于衬底基板(100)上遮光层，该遮光层包含层叠设置的第一遮光层(200)和第二遮光层(300)，其中，薄膜晶体管的有源层(500)的在衬底基板(100)上的正投影位于遮光层的在衬底基板(100)上的正投影之内，第二遮光层(300)包括纳米颗粒以吸收特定波长范围内的光。该纳米颗粒可以吸收透过第一遮光层(200)的光以降低有源层(500)因光照射导致的薄膜晶体管漏电流增大问题，还可以避免因遮挡该特定波长范围内的光而增加第一遮光层(200)厚度造成的段差所引起的显示基板后续制备工艺不良。

Description

显示基板及其制备方法、显示装置
本申请要求于2017年3月10日递交的中国专利申请第201710143017.6号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开至少一个实施例涉及一种显示基板及其制备方法、显示装置。
背景技术
薄膜晶体管中的有源层在受到光照射后会使得光生载流子增加，造成显示器件的电压漂移、漏电流增加等不良。蓝光所对应的波段对有源层的影响最大，尤其是在导致显示器件的漏电流增加的方面有明显影响，通常为解决这一问题，可通过在薄膜晶体管所在的区域设置一遮光层以对有源层进行遮光。但是，现有工艺中，遮光层的设置仍然不能满足需求，并且容易引起工艺不良等问题。
发明内容
本公开至少一实施例提供一种显示基板，包括：衬底基板；设置于所述衬底基板上的薄膜晶体管；设置于所述衬底基板上的包含第一遮光层和第二遮光层的遮光层；其中，所述薄膜晶体管的有源层的在所述衬底基板上的正投影位于所述遮光层的在所述衬底基板上的正投影之内，所述第二遮光层包括纳米颗粒以吸收特定波长范围内的光。
例如，在本公开至少一实施例提供的显示基板中，所述第一遮光层的材料包括单晶硅、多晶硅或非晶硅。
例如，在本公开至少一实施例提供的显示基板中，所述第二遮光层的材料还包括氮化硅或碳化硅。
例如，在本公开至少一实施例提供的显示基板中，所述第一遮光层的厚度范围包括
Figure PCTCN2017114555-appb-000001
所述第二遮光层的厚度范围包括
Figure PCTCN2017114555-appb-000002
例如，在本公开至少一实施例提供的显示基板中，所述纳米颗粒可以 为纳米硅颗粒。
例如，在本公开至少一实施例提供的显示基板中，所述纳米硅颗粒的粒径范围包括3～5纳米。
例如，在本公开至少一实施例提供的显示基板中，所述光可以为蓝光，所述蓝光的波长范围包括420～480纳米。
例如，在本公开至少一实施例提供的显示基板中，所述第一遮光层可以设置于所述第二遮光层的远离所述衬底基板的一侧；或者所述第二遮光层可以设置于所述第一遮光层的远离所述衬底基板的一侧。
例如，在本公开至少一实施例提供的显示基板中，所述薄膜晶体管可以包括顶栅型结构或底栅型结构的薄膜晶体管。
例如，在本公开至少一实施例提供的显示基板中，在所述薄膜晶体管为底栅型结构时，所述遮光层设置于所述有源层的远离所述衬底基板的一侧；或者在所述薄膜晶体管为顶栅型结构时，所述遮光层设置于所述衬底基板和所述有源层之间。
本公开至少一实施例提供一种显示装置，包括上述任一实施例中的显示基板。
本公开至少一实施例提供一种显示基板的制备方法，包括：提供衬底基板；在所述衬底基板上形成薄膜晶体管；在所述衬底基板上形成包括第一遮光层和第二遮光层的遮光层；其中，所述薄膜晶体管的有源层的在所述衬底基板上的正投影位于所述遮光层的在所述衬底基板上的正投影之内，所述第二遮光层包括有纳米颗粒以吸收特定波长范围内的光。
例如，在本公开至少一实施例提供的制备方法中，形成所述第二遮光层的方法可以包括螺旋波等离子体化学气相沉积。
例如，在本公开至少一实施例提供的制备方法中，所述纳米颗粒为纳米硅颗粒，形成所述第二遮光层包括：通过至少包括氮气、硅烷和氢气的反应气体或者至少包括氮气、甲烷、硅烷和氢气的反应气体形成包含所述纳米硅颗粒的第二遮光层薄膜；对所述第二遮光层薄膜进行构图工艺以形成包含所述纳米硅颗粒的所述第二遮光层。
例如，在本公开至少一实施例提供的制备方法中，通过至少包括氮气、甲烷、硅烷和氢气的反应气体形成所述第二遮光层薄膜时，所述螺旋波等离子体化学气相沉积的工艺条件为：温度范围在650～750摄氏度、功率在 400～600瓦、压力低压可达1.33帕、磁感强度在90～130Gs。
例如，在本公开至少一实施例提供的制备方法中，所述螺旋波等离子体化学气相沉积的工艺条件可以为：温度700摄氏度；压力1.33帕，功率500瓦；磁感强度110Gs；氢气、甲烷和硅烷的体积比例为1:2:40。
例如，在本公开至少一实施例提供的制备方法中，所述光可以为蓝光，所述蓝光的波长范围包括420～480纳米。
例如，在本公开至少一实施例提供的制备方法中，在所述衬底基板上形成包含第一遮光层和第二遮光层的遮光层可以包括：在衬底基板上形成所述第一遮光层，在所述第一遮光层上形成所述第二遮光层。
例如，在本公开至少一实施例提供的制备方法中，所述遮光层与所述薄膜晶体管中的有源层可以同步制备，该方法包括：在所述衬底基板上依次形成所述遮光层的薄膜和所述有源层的薄膜之后，所述遮光层的薄膜和所述有源层的薄膜使用同一个掩模板形成所述遮光层和所述有源层。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1为本公开一实施例提供的一种显示基板的横截面结构示意图；
图2为本公开一实施例提供的另一种显示基板的横截面结构示意图；
图3a为本公开一实施例提供的另一种显示基板的横截面结构示意图；
图3b为本公开一实施例提供的另一种显示基板的横截面结构示意图；
图4a～图4i为本公开一实施例提供的一种显示基板制备方法的过程图；以及
图5a～图5g为本公开一实施例提供的另一种显示基板制备方法的过程图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。 基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
传统工艺一般使用金属例如钼作为遮光层的材料从而对薄膜晶体管中的有源层进行遮光，但是金属材料导致的寄生电容会比较大，所以可使用例如非晶硅代替金属钼以制备遮光层。非晶硅为半导体材料，在薄膜晶体管中的寄生电容较小，可以提高显示良率。
但是，在实际工艺中，遮光层的厚度是受到限制的，如此，例如非晶硅制备的遮光层可以遮挡或吸收路径上的部分光线，其它部分的光线例如部分蓝光仍可能透过遮光层。如此需要加厚遮光层的厚度才可以使得遮光层的对光的吸收峰蓝移，虽然加厚遮光层会使得遮光层的吸收峰蓝移并且减少其它光的透过率，但是遮光层的厚度增加会产生较大的段差，并可能进一步导致例如显示基板中薄膜晶体管等的后续制备工艺出现不良。
本公开的至少一个实施例提供了一种显示基板及其制备方法、显示装置。该显示基板包括衬底基板、设置于该衬底基板上的薄膜晶体管和设置于该衬底基板上的遮光层，该遮光层包括对应于薄膜晶体管的有源层的至少一层第一遮光层和至少一层第二遮光层的遮光层，其中，该第二遮光层包括纳米颗粒以吸收特定波长范围内的光。在本公开提供的实施例中，上述有源层和遮光层对应设置例如可以为：薄膜晶体管的有源层的在衬底基板上的正投影位于遮光层的在衬底基板上的正投影之内，如此遮光层可以在垂直于衬底基板的方向上对有源层进行遮光。
透过第一遮光层的光线中，蓝光对有源层产生的不良影响明显，所以以该特定波长范围内的光为蓝光为例，对本公开下述实施例中的技术方案 进行说明。
在该实施例中，第二遮光层中包含纳米颗粒，可以吸收透过第一遮光层的蓝光，从而不需要通过增加第一遮光层的厚度就可以减小蓝光的透过率(即不需要通过额外增加第一遮光层的厚度以使得第一遮光层对光线的吸收峰蓝移)，从而可以避免因增加第一遮光层厚度造成的段差所引起的例如薄膜晶体管等器件的制备工艺的不良。示例性的，第二遮光层可以为吸光层。根据量子尺寸效应，随着量子点尺寸的逐渐减小，量子点的光吸收谱会出现蓝移现象，尺寸越小，光吸收谱的蓝移现象越显著。以硅颗粒为例，当硅颗粒的粒径(颗粒大小)越小，由其构成的体系例如含硅颗粒的膜层所对应的带隙会展宽，即其可吸收的光的波长更短，表现为吸收峰蓝移，即上述实施例中的包括纳米硅颗粒的第二遮光层的吸收峰蓝移，从而可以吸收全部或至少部分蓝光。
下面，以纳米硅颗粒作为纳米颗粒为例，结合附图对根据本公开至少一个实施例中的显示基板及其制备方法、显示装置进行说明。
本公开至少一个实施例提供了一种显示基板，图1为本公开一实施例提供的一种显示基板的横截面结构示意图，其为剖面图。例如图1所示，该显示基板包括衬底基板100、设置于该衬底基板100上的薄膜晶体管和设置于该衬底基板100上的遮光层，该遮光层对应于薄膜晶体管的有源层500设置，并且该遮光层包括至少一层第一遮光层200和至少一层第二遮光层300，其中，该第二遮光层(例如吸光层)300包括纳米硅颗粒以吸收特定波长范围内的蓝光。该薄膜晶体管可以包括有源层500、栅绝缘层600、栅电极700、绝缘层800和源漏电极层900等，其中，源漏电极层900包括源电极910和漏电极920。
例如，在本公开至少一个实施例中，如图1所示，第一遮光层200的厚度范围可以约为
Figure PCTCN2017114555-appb-000003
第二遮光层的厚度范围可以约为
Figure PCTCN2017114555-appb-000004
Figure PCTCN2017114555-appb-000005
例如，在只设置有第一遮光层200的情况下，为遮挡光线特别是蓝光，第一遮光层200的厚度范围约为
Figure PCTCN2017114555-appb-000006
而且在此厚度范围内的第一遮光层200可能仍会透过部分蓝光。示例性的，单独设置第一遮光层200的情况下，第一遮光层200的厚度为
Figure PCTCN2017114555-appb-000007
且此厚度的第一遮光层200可能会透过部分蓝光，而采用
Figure PCTCN2017114555-appb-000008
的第一遮光层200和
Figure PCTCN2017114555-appb-000009
的第二遮光层300即可取得吸收透过第一遮光层200的蓝光的技术效果，而且包括 第一遮光层200和第二遮光层300的遮光层的总厚度小于单独设置第一遮光层200的厚度，在取得相同或更好地过滤蓝光的技术效果的基础上减小段差，降低或消除段差对显示基板的后续制备工艺的不良影响，从而显著提升显示基板的良率。
例如，在本公开至少一个实施例中，第二遮光层300可以配置为吸收对有源层500的影响最大的波长范围内的蓝光。例如该蓝光的波长范围约为420～480纳米，进一步，第二遮光层300可以配置为吸收波长范围在约435～450纳米内的光。
例如，在本公开至少一个实施例中，第二遮光层300吸收波长范围包括420～480纳米(例如435～450纳米)的蓝光，需要纳米硅颗粒的粒径范围可以达到约3～5纳米。需要说明的是，第二遮光层300的光吸收峰是随着纳米硅颗粒的粒径减小而蓝移的，所以如果需要吸收更短波长范围内的光线，可以将纳米硅颗粒的粒径设置为例如小于3纳米。本公开的实施例对硅颗粒的具体形状不做限制，例如，硅颗粒的形状可以为球形或近似球形，也可以为棒状等。
在本公开实施例中，对第一遮光层200和第二遮光层300的叠置顺序不做限制，两者的位置可以互换。如图1所示，例如，第二遮光层300设置在第一遮光层200之上，即第二遮光层300设置于第一遮光层200的远离衬底基板100的一侧；例如，第一遮光层200也可以设置在第二遮光层300之上，即第一遮光层200设置于第二遮光层300的远离衬底基板100的一侧；例如，在遮光层包括的第一遮光层200和第二遮光层300为多个的情况下，第一遮光层200和第二遮光层300之间也可以交替叠置。
本公开的实施例对第二遮光层300的制备材料不做限制。例如，在本公开至少一个实施例中，第二遮光层300的制备材料还可以包括氮化硅或碳化硅等，只要第二遮光层300中可以设置有符合上述实施例要求的纳米硅颗粒，第二遮光层300即可吸收透过第一遮光层200的蓝光。
例如，在本公开至少一个实施例中，第一遮光层200的制备材料可以包括单晶硅、多晶硅或非晶硅等，例如还可以包括砷化镓、镓铝砷、磷化铟、硫化镉、碲化镉等。例如非晶硅既可以作为第一遮光层又可以作为有源层的构成材料，而且两者可以通过一次工艺制备形成，可以减少显示基板中的例如薄膜晶体管的制备工艺流程的步骤。需要说明的是，本公开实 施例中提供的第二遮光层300可以吸收透过第一遮光层200的光，从而不需要增加第一遮光层200的厚度来实现遮光的目的，所以在本公开提供的实施例中，对第一遮光层的材料可以不作限制。
在本公开的实施例中，对显示基板中薄膜晶体管的类型及具体化结构不做限制。例如，在本公开至少一个实施例所提供的显示基板中，包括第一遮光层200和第二遮光层300的遮光层可以同时适用于顶栅型和底栅型的薄膜晶体管。对于不同结构类型的薄膜晶体管，包括第一遮光层200和第二遮光层300的遮光层可以有不同的设置位置。例如，该薄膜晶体管为底栅型结构，包括第一遮光层200和第二遮光层300的遮光层可以设置于有源层500的远离衬底基板的一侧；例如，该薄膜晶体管为顶栅型结构，包括第一遮光层200和第二遮光层300的遮光层可以设置在衬底基板100和有源层500之间。下面，根据不同类型的薄膜晶体管，对显示基板的结构进行进一步说明。
例如，在本公开至少一个实施例中，该显示基板中的薄膜晶体管为顶栅型的薄膜晶体管。如图1所示，衬底基板100上依次设置包括至少一层第一遮光层200和至少一层第二遮光层300的遮光层、有源层500、栅绝缘层600、栅电极700、绝缘层800和源漏电极层900，其中，源漏电极层900的源电极910和漏电极920可以通过例如过孔(图中未示出，参考下述实施例的图4h中的过孔1)与有源层500电连接。顶栅型的薄膜晶体管需要避免有源层500的靠近衬底基板100的一侧的光对其有源层500进行照射，所以包括第一遮光层200和第二遮光层300的遮光层需要设置在衬底基板100和有源层500之间。
例如，图1所示，显示基板中的顶栅型的薄膜晶体管还可以包括缓冲层400，该缓冲层400在衬底基板100和有源层500之间充当一个过渡膜层，可以使有源层500和衬底基板100之间结合得更稳固，且可以防止衬底基板100中的有害杂质、离子等扩散到有源层500之中。
缓冲层400的制备材料可以包括硅氧化物(SiOx)或硅氮化物(SiNx)、硅氮氧化物(SiOxNy)等。例如，该缓冲层400还可以为由氮化硅或者氧化硅构成的单层结构，或者由氮化硅和氧化硅构成的双层或多层结构。
例如，在本公开至少一个实施例中，该显示基板中的薄膜晶体管为底栅型的薄膜晶体管。图2为本公开一实施例提供的另一种显示基板的横截 面结构示意图，其为剖面图。例如图2所示，在衬底基板100上依次设置栅电极700、栅绝缘层600、有源层500、源漏电极层900、钝化层1000和包括至少一层第一遮光层200和至少一层第二遮光层300的遮光层，其中，源漏电极层900包括源电极910和漏电极920。对于有源层500的靠近衬底基板100的一侧来说，栅电极700可以起到遮光的作用，但是其远离衬底基板100的一侧可能会受到光照射，所以包括第一遮光层200和第二遮光层300的遮光层可以设置在有源层500的远离衬底基板100的一侧，从而对有源层500起到遮光的作用。
例如，在本公开至少一个实施例中，显示基板还可以包括与薄膜晶体管的源电极或漏电极电连接的第一电极层，显示基板还可以包括其他不同类型的结构以应用于液晶显示、有机发光二极管显示和电子纸显示等中。下面，根据显示基板中的薄膜晶体管分别为顶栅型和底栅型薄膜晶体管的情况，对显示基板的结构进一步进行说明。
图3a为本公开一实施例提供的另一种显示基板的横截面结构示意图，其为剖面图，显示基板中的薄膜晶体管为顶栅型结构。例如，在本公开至少一个实施例中，如图3a所示，该显示基板还包括设置在源漏电极层900之上的钝化层1000和第一电极层1010，该第一电极层1010例如可以为像素电极。第一电极层1010可以通过钝化层1000中设置的过孔(图中未示出，参考图4h中的过孔1)与源漏电极层900中的例如漏电极920电连接。
例如，如图3a所示，薄膜晶体管为顶栅型结构，有源层500的远离衬底基板100的一侧可以由栅电极700进行遮光。为遮挡有源层500的另一侧的光对其照射，包括第一遮光层200和第二遮光层300的遮光层例如可以设置在衬底基板100和有源层500之间。需要说明的是，在例如栅电极700的结构受限而不能对有源层500良好遮光的情况下，也可以将包括第一遮光层200和第二遮光层300的遮光层设置在有源层500的远离衬底基板100的一侧，示例性的，第一遮光层200和第二遮光层300可以设置在钝化层1000之上以对有源层500进行遮光。
例如，在本公开至少一个实施例中，显示基板还可以包括多个阵列排列的子像素区域，其中，每个子像素区域可以包括栅线、数据线、上述的第一电极层和薄膜晶体管等。显示基板中的栅线和数据线彼此交叉以限定出子像素区域，而且例如数据线与源漏电极层中的例如源电极电连接，第 一电极层(像素电极)与源漏电极层中的例如漏电极电连接。
例如，钝化层1000的制备材料可以为氮化硅(SiNx)、氧化硅(SiOx)和丙烯酸类树脂等中的一种或组合。
例如，第一电极层(像素电极)1010可以采用透明导电材料形成或金属材料形成，例如，形成该第一电极层1010的材料可以包括氧化铟锡(ITO)、氧化铟锌(IZO)、氧化铟镓(IGO)、氧化镓锌(GZO)氧化锌(ZnO)、氧化铟(In2O3)、氧化铝锌(AZO)和碳纳米管等。
例如，在本公开至少一个实施例中，显示基板还可以包括有机发光器件，并且第一电极层1010可以为该有机发光器件例如有机发光二极管的阳极或阴极。例如，该有机发光器件还包括设置于第一电极层1010上的第二电极层1030以及位于第一电极层1010和第二电极层1030之间的发光层1020。例如，第一电极层1010和第二电极层1030中的一方为阳极，第一电极层1010和第二电极层1030中的另一方为阴极。
图3b为本公开一实施例提供的另一种显示基板的横截面结构示意图，其为剖面图，显示基板中的薄膜晶体管为底栅型结构。例如，在本公开至少一个实施例中，如图3b所示，该显示基板还包括设置在源漏电极层900上的钝化层1000和与源漏电极层900的漏电极920电连接的第一电极层1010，例如，该第一电极层1010为阳极，但是本公开的实施例不限于此。在一个实施例中，该显示基板还可以包括设置于钝化层1000上的像素界定层1100和有机发光器件，第一电极层1010作为有机发光器件的例如阳极或阴极。
像素界定层1100可以限定像素单元区域并且在像素界定层1100限定的区域内制备例如有机发光器件中的各部分结构。例如，该有机发光器件还可以包括与第一电极层1010相对设置的第二电极层1030和设置于第一电极层1010和第二电极层1030之间的发光层1020。更为具体的，该有机发光器件还可以包括空穴传输层、空穴注入层、电子传输层和电子注入层。示例性的，该有机发光器件中的各结构的排列顺序可以为：阳极、空穴注入层、空穴传输层、发光层、电子传输层、电子注入层和阴极。
如图3b所示，薄膜晶体管为底栅型结构，有源层500的靠近衬底基板100的一侧可以由栅电极700进行遮光。为遮挡有源层500的另一侧的光对其照射，第一遮光层200和第二遮光层300的遮光层例如可以设置在 有源层500的远离衬底基板100的一侧。例如，该遮光层可以设置在钝化层1000的远离有源层500的一侧，或者遮光层也可以设置在像素界定层1100的远离有源层的一侧。
本公开至少一个实施例提供一种显示装置，该显示装置包括上述任一实施例中的显示基板。
例如，在本公开实施例的一个示例中，该显示装置可以为液晶显示面板，例如该液晶显示面板可以包括阵列基板和对置基板，二者彼此对置以形成液晶盒，在液晶盒中填充有液晶材料。该对置基板例如可以为彩膜基板。阵列基板的每个像素单元的像素电极和公共电极用于施加电场对液晶材料的旋转的程度进行控制从而进行显示操作。
例如，在本公开实施例的一个示例中，该显示装置可以为有机发光二极管(OLED)显示面板，其中，该显示面板的子像素区域中可以形成有机发光材料的叠层，每个子像素单元的像素电极作为阳极或阴极用于驱动有机发光材料发光以进行显示操作。
例如，在本公开实施例的一个示例中，该显示装置可以为电子纸显示面板，其中，在该显示面板的显示基板上可以形成有电子墨水层，每个子像素单元的像素电极作为用于施加驱动电子墨水中的带电微颗粒移动以进行显示操作的电压。
例如，该显示装置可以配置为具有触控功能的显示面板，例如还可以应用为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开至少一个实施例提供了一种显示基板的制备方法，该制备方法包括：提供衬底基板；在该衬底基板上形成薄膜晶体管；在该衬底基板上形成对应于薄膜晶体管的有源层的包括至少一层第一遮光层和至少一层第二遮光层的遮光层，第二遮光层包括有纳米颗粒以吸收特定波长范围内的光。
例如，在本公开至少一个实施例提供的制备方法中，形成第二遮光层的方法可以包括螺旋波等离子体化学气相沉积。螺旋波等离子体化学气相沉积技术可以在较低气压条件下产生高密度的等离子体，而且等离子体的产生一般不需要高的约束磁场，该技术需要的设备更简单，成本低所以在例如制备含纳米硅颗粒的第二遮光层的工业生产上更适用。
例如，在本公开至少一个实施例提供的制备方法中，纳米颗粒可以为纳米硅颗粒，形成第二遮光层的方法可以包括：通过至少包括氮气、硅烷和氢气的反应气体形成包含纳米硅颗粒的第二遮光层薄膜；或者通过至少包括氮气、甲烷、硅烷和氢气的反应气体形成包含纳米硅颗粒的第二遮光层薄膜；对第二遮光层薄膜进行构图工艺以形成包含纳米硅颗粒的所述第二遮光层。
例如，在本公开至少一个实施例提供的制备方法中，可以通过控制氮气的注入量以调整纳米颗粒的粒径。
例如，在本公开至少一个实施例提供的制备方法中，第一遮光层可以形成在第二遮光层的远离衬底基板的一侧；或者第二遮光层可以形成在第一遮光层的远离衬底基板的一侧。
在本公开实施例提供的显示基板中，薄膜晶体管可以为上述实施例中提供的底栅型或者顶栅型的结构，下面，提供其中一种薄膜晶体管结构下的显示基板的制备过程作为示例。例如，本实施例中的一个示例提供一种顶栅型的薄膜晶体管结构下的显示基板的制备过程，图4a～图4i为本公开一实施例提供的一种显示基板制备方法的过程图，该显示基板的薄膜晶体管为顶栅型。参照图4a～图4i，本实施例提供的显示基板制备过程的一个示例包括如下过程。
如图4a所示，提供一衬底基板100，并在该衬底基板100上沉积一层第一遮光层薄膜210。
例如，该衬底基板100的制备材料可以为透明的玻璃、陶瓷或金属等。该第一遮光层薄膜210的制备材料例如可以为单晶硅、多晶硅或非晶硅，例如还可以为砷化镓、镓铝砷、磷化铟、硫化镉、碲化镉等。
如图4b所示，在形成有第一遮光层薄膜210的衬底基板10上沉积一层第二遮光层薄膜310，形成的第二遮光层薄膜310中包含有纳米颗粒。下面，以纳米颗粒为纳米硅颗粒为例，对第二遮光层薄膜310形成纳米颗粒的过程进行说明。
例如，形成该第二遮光层薄膜310的方法可以为螺旋波等离子体化学气相沉积。在本公开的实施例中，对螺旋波等离子体化学气相沉积中的反应气体的组合不做限制，只要形成的第二遮光层薄膜310中可以形成纳米颗粒例如纳米硅颗粒即可。
例如，螺旋波等离子体化学气相沉积的反应气体可以包括氮气、硅烷和氢气的混合气体，可以在衬底基板100上形成包括纳米硅颗粒并且基质为氮化硅的第二遮光层薄膜310。
例如，螺旋波等离子体化学气相沉积的反应气体也可以为包括氮气、甲烷、硅烷和氢气的混合气体，可以在衬底基板100上形成包括纳米硅颗粒并且基质为碳化硅的第二遮光层薄膜。
第二遮光层薄膜310中的纳米硅颗粒的粒径可以通过控制反应气体中的氮气的注入量来控制。例如在沉积过程中，通入的氮气的注入速率增加，则制备的纳米硅颗粒的粒径越小，第二遮光层薄膜310可以吸收具有更短波长的光，即第二遮光层薄膜310对光的吸收峰随着纳米硅颗粒的减小而蓝移。
例如，第二遮光层薄膜310可以形成为吸收波长范围在420～480纳米范围内的蓝光，例如可以吸收波长范围435～450纳米范围内的蓝光。上述波段例如波长范围435～450纳米范围内的蓝光对有源层的影响大，该波长范围内的蓝光照射有源层后产生的光生载流子导致的薄膜晶体管漏电流增大也更明显。
例如，纳米硅颗粒的粒径范围在约3～5纳米以满足第二遮光层薄膜310可以吸收例如波长范围在420～480纳米尤其波长范围435～450纳米范围内的蓝光。例如，以包括纳米硅颗粒并且基质为碳化硅的第二遮光层薄膜310的制备过程为例，例如通过螺旋波等离子体化学气相沉积技术制备包含此纳米硅颗粒粒径范围的第二遮光层薄膜的条件例如可以为：温度范围在约650～750摄氏度、功率在约400～600瓦、压力低压可达1.33帕、磁感强度约90～130Gs，氢气、甲烷和硅烷的体积比根据制备膜层的具体需求而定。例如一个具体示例包括：温度约700摄氏度；压力约1.33帕，功率约500瓦；磁感强度约110Gs；氢气、甲烷和硅烷的体积比例可以约为1:2:40；通过控制氮气的注入量或注入速率即可使得沉积形成的第二遮光层薄膜中的纳米硅颗粒的粒径范围达到约3～5纳米的要求。
需要说明的是，上述纳米硅颗粒的粒径范围达到3～5纳米是对于第二遮光层可以吸收蓝光的基本要求，但不限于此数值范围。例如上述方法中通过改变反应条件的参数例如通入更多的氮气也可以得到粒径小于3纳米的纳米硅颗粒，此条件下同样满足第二遮光层300对蓝光进行吸收的要求。
例如，第二遮光层薄膜310和第一遮光层薄膜210的形成顺序可以互换，而且第二遮光层薄膜310和第一遮光层薄膜210都可以为多层，例如第二遮光层薄膜310和第一遮光层薄膜210还可以多层且彼此相互交叠以得到叠层，在两者构成叠层的情况下，叠层中的各第二遮光层薄膜和各第一遮光层薄膜的叠置顺序可以为任意布置。
如图4c所示，通过对第一遮光层薄膜210和第二遮光层薄膜310使用同一个掩模板进行构图工艺处理以形成包括第一遮光层200和第二遮光层300的遮光层。
构图工艺例如可以为光刻构图工艺，其例如可以包括：在需要被构图的结构层上涂覆光刻胶层，使用掩模板对光刻胶层进行曝光，对曝光的光刻胶层进行显影以得到光刻胶图案，使用光刻胶图案对结构层进行蚀刻，然后可选地去除光刻胶图案。
第二遮光层300和第一遮光层200的形成不限于经由上述同一个掩模板进行构图工艺形成，也可以分别对第二遮光层薄膜310和第一遮光层薄膜210进行构图工艺以形成包括第二遮光层300和第一遮光层200的遮光层。
如图4d所示，在形成有包括第一遮光层200和第二遮光层300的遮光层的衬底基板100上沉积一层缓冲层400。该缓冲层400的功能和制备材料在本公开上述中的实施例中已经提供，在此不做赘述。
如图4e所示，在缓冲层40上沉积一层半导体材料薄膜并对其进行构图工艺以形成有源层500。例如，制备该有源层500的材料包括非晶硅、多晶硅、氧化铟镓锌(IGZO)、氧化铟锌(IZO)、氧化锌(ZnO)、氧化镓锌(GZO)等金属氧化物等。
如图4f所示，在形成有有源层500的衬底基板100上依次沉积绝缘材料薄膜和导电材料薄膜并对两者使用同一掩模板进行构图工艺以分别形成栅绝缘层600和栅电极700。
例如，该栅绝缘层600的制备材料可以包括氮化硅(SiNx)、氧化硅(SiOx)、氧化铝(Al2O3)、氮化铝(AlN)或其他适合的材料等。
例如，该栅电极的材料可以为铜基金属，例如，铜(Cu)、铜钼合金(Cu/Mo)、铜钛合金(Cu/Ti)、铜钼钛合金(Cu/Mo/Ti)、铜钼钨合金(Cu/Mo/W)、铜钼铌合金(Cu/Mo/Nb)等；该栅电极的材料也可以为铬 基金属，例如，铬钼合金(Cr/Mo)、铬钛合金(Cr/Ti)、铬钼钛合金(Cr/Mo/Ti)等；该栅电极的材料还可以为铝或铝合金等。
栅绝缘层600和栅电极700的形成不限于经由上述同一掩模板进行构图工艺形成，也可以分别对绝缘材料薄膜和导电材料薄膜进行构图工艺以形成栅绝缘层600和栅电极700。
如图4g所示，在衬底基板100上沉积一层绝缘材料薄膜以形成绝缘层800。该绝缘层800的制备材料可以为氮化硅(SiNx)或者氧化硅(SiOx)等。
如图4h所示，在绝缘层800中形成过孔1并暴露过孔1处的有源层500。
如图4i所示，在形成有绝缘层800的衬底基板100上沉积导电材料薄膜并对其进行构图工艺以形成源漏电极层900。该源漏电极层900包括源电极910和漏电极920。
源漏电极层900的制备材料可以为金属材料，可以形成单层或多层结构，例如，源漏电极层900可以为单层铝结构、单层钼结构、或者由两层钼夹设一层铝的三层结构。
在本公开实施例提供的制备方法中，例如可以使用同一掩模同步制备遮光层和有源层，从而减少工艺步骤。例如该制备工艺过程可以为在依次沉积遮光层(例如第一遮光层200和第二遮光层300)、缓冲层400和有源层500之后，对有源层500使用掩模进行一次曝光，然后完成对于遮光层和有源层500的刻蚀和剥离工艺，从而减少一次遮光层的掩模工艺。
图5a～图5g为本公开一实施例提供的另一种显示基板制备方法的过程图。参照图5a～图5g，本实施例提供的显示基板制备过程的一个示例可以包括如下步骤。
如图5a所示，提供一衬底基板100，并在该衬底基板100上依次沉积一层第一遮光层薄膜210、第二遮光层薄膜310、缓冲层薄膜410以及半导体材料薄膜510。
如图5b所示，使用一次掩模板对所述第一遮光层薄膜210、第二遮光层薄膜310、缓冲层薄膜410以及半导体材料薄膜510进行构图工艺以形成包括第一遮光层200和第二遮光层300的遮光层、缓冲层400以及有源层500。
如图5c所示，在形成有所述有源层500的衬底基板100上沉积形成栅绝缘层600。
如图5d所示，在形成有所述栅绝缘层600的衬底基板100上沉积导电材料薄膜并对其进行构图工艺以形成栅电极700。
如图5e所示，在衬底基板100上沉积一层绝缘层薄膜以形成绝缘层800。
如图5f所示，在绝缘层800以及栅绝缘层600中形成过孔1并暴露过孔1处的有源层500。
如图5g所示，在形成有绝缘层800的衬底基板100上沉积导电材料薄膜并对其进行构图工艺以形成源漏电极层900。该源漏电极层900可以包括源电极910和漏电极920。
在如图5a～图5g所示的示例中，显示基板制备过程中各层结构的材料、结构及相关工艺等，可以参考如图4a～图4i所示的示例中的制备方法，在此不做赘述。需要说明的是，上述示例只给出了薄膜晶体管为顶栅型结构情况下的显示基板的制备过程。当薄膜晶体管为底栅型结构时，显示基板中各层结构的制备方法与上述薄膜晶体管为底栅型的显示基板的制备方法相近，例如，薄膜晶体管中各结构的制备方法可以与传统工艺相同，只是包括第一遮光层和第二遮光层的遮光层需要设置在有源层的远离衬底基板的一侧，只要形成的第一遮光层和第二遮光层可以对有源层进行遮光即可。
本公开的至少一个实施例提供一种显示基板及其制备方法、显示装置，并且可以具有以下至少一项有益效果：
(1)本公开至少一个实施例提供一种显示基板，显示基板中设置的第二遮光层可以吸收特定波长范围内的光例如蓝光，从而防止有源层因蓝光照射后光生载流子增加导致的显示器件漏电流增加。
(2)在本公开至少一个实施例提供的显示基板中，因为第二遮光层可以吸收特定波长范围内的光例如蓝光，所以不需要再增加第一遮光层的厚度以使得第一遮光层的吸收峰蓝移，改善因加厚第一遮光层所致的较大段差引起的显示基板后续制备工艺的不良。
(3)本公开至少一个实施例提供一种显示基板的制备方法，在该方法中，包括第一遮光层和第二遮光层的遮光层可以与有源层在同一掩模工艺中制备而成，减少工艺步骤，降低成本。
对于本公开，还有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (19)

  1. 一种显示基板，包括：
    衬底基板；
    设置于所述衬底基板上的薄膜晶体管；
    设置于所述衬底基板上的遮光层，所述遮光层包含层叠设置的第一遮光层和第二遮光层；
    其中，所述薄膜晶体管的有源层在所述衬底基板上的正投影位于所述遮光层在所述衬底基板上的正投影之内，所述第二遮光层包括纳米颗粒以吸收特定波长范围内的光。
  2. 根据权利要求1所述的显示基板，其中，所述第一遮光层的材料包括单晶硅、多晶硅或非晶硅。
  3. 根据权利要求1或2所述的显示基板，其中，所述第二遮光层的材料还包括氮化硅或碳化硅。
  4. 根据权利要求1-3中任一项所述的显示基板，其中，
    所述第一遮光层的厚度范围包括
    Figure PCTCN2017114555-appb-100001
    所述第二遮光层的厚度范围包括
    Figure PCTCN2017114555-appb-100002
  5. 根据权利要求1-4中任一项所述的显示基板，其中，所述纳米颗粒为纳米硅颗粒。
  6. 根据权利要求5所述的显示基板，其中，所述纳米硅颗粒的粒径范围包括3～5纳米。
  7. 根据权利要求1-6中任一项所述的显示基板，其中，所述光为蓝光，所述蓝光的波长范围包括420～480纳米。
  8. 根据权利要求1-7中任一项所述的显示基板，其中，
    所述第一遮光层设置于所述第二遮光层的远离所述衬底基板的一侧；或者
    所述第二遮光层设置于所述第一遮光层的远离所述衬底基板的一侧。
  9. 根据权利要求1-8任一所述的显示基板，其中，所述薄膜晶体管包括顶栅型结构或底栅型结构的薄膜晶体管。
  10. 根据权利要求9所述的显示基板，其中，
    在所述薄膜晶体管为底栅型结构时，所述遮光层设置于所述有源层的 远离所述衬底基板的一侧；或者
    在所述薄膜晶体管为顶栅型结构时，所述遮光层设置于所述衬底基板和所述有源层之间。
  11. 一种显示装置，包括权利要求1-10中任一项所述的显示基板。
  12. 一种显示基板的制备方法，包括：
    提供衬底基板；
    在所述衬底基板上形成薄膜晶体管；
    在所述衬底基板上形成包括第一遮光层和第二遮光层的遮光层；
    其中，所述薄膜晶体管的有源层的在所述衬底基板上的正投影位于所述遮光层的在所述衬底基板上的正投影之内，所述第二遮光层包括有纳米颗粒以吸收特定波长范围内的光。
  13. 根据权利要求12所述的制备方法，其中，形成所述第二遮光层的方法包括螺旋波等离子体化学气相沉积。
  14. 根据权利要求12或13所述的制备方法，其中，所述纳米颗粒为纳米硅颗粒，形成所述第二遮光层包括：
    通过至少包括氮气、硅烷和氢气的反应气体或者至少包括氮气、甲烷、硅烷和氢气的反应气体形成包含所述纳米硅颗粒的第二遮光层薄膜；
    对所述第二遮光层薄膜进行构图工艺以形成包含所述纳米硅颗粒的所述第二遮光层。
  15. 根据权利要求14所述的制备方法，其中，通过至少包括氮气、甲烷、硅烷和氢气的反应气体形成所述第二遮光层薄膜时，所述螺旋波等离子体化学气相沉积的工艺条件为：温度范围在650～750摄氏度、功率在400～600瓦、压力低压可达1.33帕、磁感强度在90～130Gs。
  16. 根据权利要求15所述的制备方法，其中，所述螺旋波等离子体化学气相沉积的工艺条件为：温度700摄氏度；压力1.33帕，功率500瓦；磁感强度110Gs；氢气、甲烷和硅烷的体积比例为1:2:40。
  17. 根据权利要求12-16任一项所述的制备方法，其中，所述光为蓝光，所述蓝光的波长范围包括420～480纳米。
  18. 根据权利要求12-17任一所述的制备方法，其中，在所述衬底基板上形成包含第一遮光层和第二遮光层的遮光层包括：
    在衬底基板上形成所述第一遮光层；
    在所述第一遮光层上形成所述第二遮光层。
  19. 根据权利要求18所述的制备方法，其中，所述遮光层与所述薄膜晶体管中的有源层同步制备，该方法包括：
    在所述衬底基板上依次形成所述遮光层的薄膜和所述有源层的薄膜之后，所述遮光层的薄膜和所述有源层的薄膜使用同一个掩模板形成所述遮光层和所述有源层。
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