WO2018166037A1 - 一种像素驱动电路及oled显示装置 - Google Patents

一种像素驱动电路及oled显示装置 Download PDF

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Publication number
WO2018166037A1
WO2018166037A1 PCT/CN2017/081248 CN2017081248W WO2018166037A1 WO 2018166037 A1 WO2018166037 A1 WO 2018166037A1 CN 2017081248 W CN2017081248 W CN 2017081248W WO 2018166037 A1 WO2018166037 A1 WO 2018166037A1
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Prior art keywords
thin film
film transistor
signal
electrically connected
data signal
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PCT/CN2017/081248
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English (en)
French (fr)
Inventor
蔡玉莹
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to US15/533,445 priority Critical patent/US10347658B2/en
Priority to KR1020197030476A priority patent/KR20190129948A/ko
Priority to JP2019550839A priority patent/JP6911276B2/ja
Priority to EP17900438.7A priority patent/EP3598427A4/en
Publication of WO2018166037A1 publication Critical patent/WO2018166037A1/zh
Anticipated expiration legal-status Critical
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Definitions

  • the present invention relates to the field of liquid crystal display, and in particular to a pixel driving circuit and an OLED display device.
  • the current Organic Light Emitting Diode (OLED) display device has many advantages such as small size, simple structure, independent illumination, high brightness, large viewing angle, short response time, etc., and is recognized as the most promising in the industry. Liquid crystal display device.
  • the OLED display device is a current driving device.
  • the organic light emitting diode When a current flows through the organic light emitting diode, the organic light emitting diode emits light, and the luminance of the light is determined by the current flowing through the organic light emitting diode itself.
  • Most existing integrated circuits only transmit voltage signals, so the pixel driving circuit of the OLED display device needs to complete the task of converting the voltage signal into a current signal.
  • the conventional pixel driving circuit is 2T1C, that is, two thin film transistors plus one capacitor structure to convert voltage into current, but the conventional 2T1C pixel driving circuit generally has no compensation function.
  • the 2T1C pixel driving circuit includes a first thin film transistor T10, a second thin film transistor T20, and a capacitor Cs.
  • the first thin film transistor T10 is a driving thin film transistor
  • the second thin film transistor T20 is a switching thin film transistor
  • the capacitor Cs is a storage capacitor.
  • the gate of the second thin film transistor T20 is electrically connected to the scan signal Vsel, the source is electrically connected to the data signal Vdata, and the drain is electrically connected to the gate of the first thin film transistor T10; the drain of the first thin film transistor T10 The pole is electrically connected to the anode of the organic light emitting diode D; the cathode of the organic light emitting diode D is electrically connected to the ground; the one end of the capacitor Cs is electrically connected to the drain of the second thin film transistor T20, and the other end is electrically connected The source of the first thin film transistor T10 is electrically connected.
  • FIG. 2 is an operation timing diagram of the 2T1C pixel driving circuit shown in FIG. 1.
  • the operation process of the 2T1C pixel driving circuit is divided into a first working phase S10 and a second working phase S20.
  • the data signal Vdata is the display data signal high potential VDATA, and the scan signal Vsel is at a high potential;
  • the second working phase S20 the data signal Vdata is at a low potential, and the scan signal Vsel is at a low potential.
  • the power signal Vdd is a constant high voltage.
  • the organic light emitting diode D emits light.
  • the gate-source voltage V gs of the first thin film transistor T10 that drives the organic light-emitting diode D to emit light satisfies the following formula:
  • V gs VDATA-V OLED ;
  • VDATA is a high potential of the data signal
  • V OLED is an anode point potential of the organic light emitting diode D.
  • the threshold voltage of the first thin film transistor T10 is not involved in the gate-source voltage V gs for driving the organic light-emitting diode D to emit light. Therefore, the 2T1C pixel driving circuit cannot compensate the driving thin film transistor (that is, the first thin film transistor). Threshold voltage of T10).
  • the technical problem to be solved by the present invention is to provide a pixel driving circuit and an OLED display device capable of effectively compensating for a threshold voltage variation of a driving thin film transistor.
  • a technical solution adopted by the present invention is to provide a pixel driving circuit including: a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a capacitor, And an organic light emitting diode; a gate of the first thin film transistor is electrically connected to the first node, a source is electrically connected to the second node, and a drain is electrically connected to the power signal; and a gate of the second thin film transistor is electrically connected to the a scan signal, the source is electrically connected to the first reference voltage signal, the drain is electrically connected to the first node; the gate of the third thin film transistor is electrically connected to the scan signal, and the source is electrically connected to the fourth thin film transistor a drain and a drain are electrically connected to the second node; a gate of the fourth thin film transistor is electrically connected to the data signal, and a source is electrically connected to the second reference voltage signal; one end of the capacitor is electrically connected to the first node
  • Vgs is a gate-source voltage of the first thin film transistor
  • Vb is a second reference voltage provided by the second reference voltage signal
  • VDATA1 is a high potential of the display data signal supplied by the data signal
  • Vth3 is the threshold voltage of the third thin film transistor
  • Vth1 is the threshold voltage of the first thin film transistor.
  • a pixel driving circuit including: a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, and a capacitor And an organic light emitting diode; the gate of the first thin film transistor is electrically connected to the first node, the source is electrically connected to the second node, the drain is electrically connected to the power signal; and the gate of the second thin film transistor is electrically connected In the scan signal, the source is electrically connected to the first reference voltage signal, and the drain is electrically connected to the first node; the gate of the third thin film transistor is electrically connected to the scan signal, and the source is electrically connected to the fourth thin film transistor The drain is electrically connected to the second node; the gate of the fourth thin film transistor is electrically connected to the data signal, and the source is electrically connected to the second reference voltage signal; one end of the capacitor is electrically connected to the first node The other end is electrically connected to the second node;
  • an OLED display device including a pixel driving circuit
  • the pixel driving circuit includes: a first thin film transistor, a second thin film transistor, a third thin film transistor, and a first a thin film transistor, a capacitor, and an organic light emitting diode; a gate of the first thin film transistor is electrically connected to the first node, a source is electrically connected to the second node, and a drain is electrically connected to the power signal; and the second thin film transistor is The gate is electrically connected to the scan signal, the source is electrically connected to the first reference voltage signal, and the drain is electrically connected to the first node; the gate of the third thin film transistor Electrically connected to the scan signal, the source is electrically connected to the drain of the fourth thin film transistor, and the drain is electrically connected to the second node; the gate of the fourth thin film transistor is electrically connected to the data signal, and the source is electrically connected The second reference voltage signal; one end of the capacitor
  • the pixel driving circuit and the OLED display device of the present invention can control the current flowing through the first thin film transistor by using the data signal and the second reference voltage signal in the threshold voltage compensation phase by introducing the fourth thin film transistor.
  • compensation of the threshold voltage of the first thin film transistor, that is, the driving thin film transistor is achieved; by introducing the third thin film transistor, it is possible to prevent the second reference voltage signal from affecting the gate potential of the first thin film transistor during the light emitting phase.
  • FIG. 1 is a circuit diagram of a prior art 2T1C pixel driving circuit
  • FIG. 2 is an operation timing chart of the 2T1C pixel driving circuit shown in FIG. 1;
  • FIG. 3 is a circuit diagram of a pixel driving circuit according to a first embodiment of the present invention.
  • FIG. 4 is a timing chart showing the operation of the pixel driving circuit shown in FIG. 3;
  • FIG. 5 is a circuit diagram of a pixel driving circuit according to a second embodiment of the present invention.
  • Figure 6 is a timing chart showing the operation of the pixel driving circuit shown in Figure 5;
  • FIG. 7 is a current simulation data diagram of a corresponding organic light emitting diode flowing through a threshold voltage drift of a driving thin film transistor in a conventional 2T1C pixel driving circuit;
  • FIG. 8 is a current simulation data diagram of a corresponding current flowing through an organic light emitting diode when a threshold voltage of a driving thin film transistor is shifted in a pixel driving circuit of the present invention
  • FIG. 9 is a schematic structural diagram of an OLED display device according to an embodiment of the present invention.
  • the pixel driving circuit 100 includes a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, a fourth thin film transistor T4, a capacitor C1, and an organic light emitting diode D1.
  • the first thin film transistor T1 is a driving thin film transistor
  • the second thin film transistor T2 and the third thin film transistor T3 are switching thin film transistors
  • the capacitor C1 is a storage capacitor.
  • the gate of the first thin film transistor T1 is electrically connected to the first node g
  • the source is electrically connected to the second node s
  • the drain is electrically connected to the power signal Vdd1
  • the gate of the second thin film transistor T2 Electrically connected to the scan signal Vsel1
  • the source is electrically connected to the first reference voltage signal Vref1
  • the drain is electrically connected to the first node g
  • the gate of the third thin film transistor T3 is electrically connected to the scan signal Vsel1
  • the source Electrically connected to the drain of the fourth thin film transistor T4, the drain is electrically connected to the second node s
  • the gate of the fourth thin film transistor T4 is electrically connected to the data signal Vdata1
  • the source is electrically connected to the second reference voltage a signal Vref2
  • one end of the capacitor C1 is electrically connected to the first node g, and the other end is electrically connected to the second node s
  • the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, and the fourth thin film transistor T4 are all low temperature polysilicon thin film transistors, oxide semiconductor thin film transistors, or amorphous silicon thin film transistors.
  • FIG. 4 is a timing chart showing the operation of the pixel driving circuit shown in FIG. As shown in FIG. 4, the operation of the pixel driving circuit 100 is divided into a threshold voltage compensation phase S1 and an emission phase S2.
  • the first reference voltage signal Vref1 and the second reference voltage signal Vref2 are constant low voltages, which are respectively used to provide the first reference voltage Va and the second reference voltage Vb, and the power supply signal Vdd1 during the operation of the pixel driving circuit 100.
  • the data signal Vdata1 and the scan signal Vsel1 are sequentially combined to correspond to the threshold voltage compensation phase S1 and the light-emitting phase S2.
  • the data signal Vdata1 and the scan signal Vsel1 are generated by an external timing controller.
  • the first reference voltage signal Vref1, the second reference voltage signal Vref2, and the power supply signal Vdd1 are generated by a constant voltage source.
  • the data signal Vdata1 is the display data signal high potential VDATA1, and the scan signal Vsel1 is high, so that the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, and the fourth thin film transistor T4 Both are open.
  • the data signal Vdata1 is written to the source of the first thin film transistor T1 via the third thin film transistor T3 and the fourth thin film transistor T4, and the first reference voltage Va1 is supplied by the first reference voltage signal Vref1.
  • the second thin film transistor T2 is written to the gate of the first thin film transistor T1.
  • V g V a ;
  • Vg represents the potential of the first node g (that is, the gate potential of the first thin film transistor T1)
  • Vs represents the potential of the second power saving s (that is, the source potential of the first thin film transistor T1)
  • Vgs represents the first a gate-to-source voltage of a thin film transistor T1
  • Va is a first reference voltage
  • Vb is a second reference voltage
  • VDATA1 is a high potential of the data signal
  • Vth3 is a threshold voltage of the third thin film transistor T3
  • Vth1 is a threshold voltage of the first thin film transistor T1.
  • the data signal Vdata1 is at a low potential
  • the scan signal Vsel1 is at a low potential
  • the first thin film transistor T1 and the fourth thin film transistor T4 are in an open state
  • the second thin film transistor T2 and the third thin film transistor T3 are turned off. status.
  • the first film due to the storage function of the capacitor C1
  • the gate-to-source voltage Vgs of the transistor T1 remains unchanged.
  • the gate-source voltage V gs that drives the organic light-emitting diode D1 to emit light includes the threshold voltage Vth1 of the first thin film transistor T10, and the current flowing through the organic light-emitting diode D1 and the gate-source voltage Vgs and the first thin film transistor T10.
  • the square of the difference of the threshold voltage Vth1 is proportional, so that the current flowing through the organic light emitting diode D1 is independent of the threshold voltage Vth1 of the first thin film transistor T10 (that is, the driving thin film transistor), and the threshold voltage compensation function is realized.
  • the gate of the fourth thin film transistor T4 is controlled by the data signal high potential VDATA1, and the source is controlled by the second reference voltage Vb, so that the data signal high potential VDATA1 and the second can be realized.
  • the reference voltage Vb controls the current flowing through the first thin film transistor T10; in the light emitting phase S2, the third thin film transistor T3 can prevent the second reference voltage Vb from affecting the gate potential of the first thin film transistor T10.
  • the second reference voltage Vb satisfies the following formula:
  • the first reference voltage Va satisfies the following formula:
  • Voled1 is the anode point potential of the organic light emitting diode D1 in the threshold voltage compensation phase.
  • Fig. 5 is a circuit diagram showing a pixel driving circuit of a second embodiment of the present invention. As shown in FIG. 5, the difference between the pixel driving circuit 200 shown in FIG. 5 and the pixel driving circuit 100 shown in FIG. 3 is that the first reference voltage signal Vref1 is the power supply signal Vdd1.
  • the pixel drive circuit 200 does not have the first reference voltage signal Vref1, and the source of the second thin film transistor T2 is directly connected to the power supply signal Vdd1.
  • FIG. 6 is a timing chart of the operation of the pixel driving circuit shown in FIG. 5.
  • the difference between the operation timing chart of the pixel driving circuit 200 shown in FIG. 6 and the operation timing chart of the pixel driving circuit 100 shown in FIG. 4 is that the power supply signal Vdd1 is low in the reference voltage compensation phase S1.
  • the potential, wherein the reference low potential is the first reference voltage Va; and in the light emitting phase S2, the power supply signal Vdd1 is at a high potential.
  • the power supply signal Vdd1, the data signal Vdata1, and the scan signal Vsel1 are generated by an external timing controller.
  • the second reference voltage signal Vref2 is generated by a constant voltage source.
  • the gate potential, the source potential, and the gate-source voltage of the first thin film transistor T1 satisfy the formula (1); the first reference voltage Va satisfies the formula (3); and the second reference voltage Vb satisfies the formula (2) ).
  • the first reference voltage Va is the reference low potential of the power supply signal Vdd1.
  • FIG. 7 and FIG. 8 are threshold voltages of the driving thin film transistor, that is, the first thin film transistor T10, respectively, in the conventional uncompensated 2T1C pixel driving circuit and the pixel driving circuit 100 or 200 of the present invention.
  • the analog data map of the current IOLED flowing through the organic light emitting diode when the drift value ⁇ Vth of the Vth and the drift value ⁇ Voled of the threshold voltage Vth1 of the first thin film transistor T1 are 0 V, +0.5 V, and -0.5 V, respectively.
  • the amount of current flowing through the organic light emitting diode in the circuit of the present invention is significantly smaller than the amount of current flowing through the organic light emitting diode in the conventional uncompensated 2T1C pixel driving circuit, so that the present invention can effectively compensate the driving of the thin film transistor.
  • the threshold voltage ensures the light-emitting stability of the organic light-emitting diode, and the display brightness of the OLED display panel can be kept uniform, and the threshold voltage does not change with the use time, thereby improving the display quality.
  • FIG. 9 is a schematic structural diagram of an OLED display device according to an embodiment of the present invention.
  • the OLED display device 1 includes a pixel driving circuit 2, wherein the pixel driving circuit 2 is the above-described pixel driving circuit 100 or pixel driving circuit 200.
  • the beneficial effects of the present invention are: the pixel driving circuit and the OLED display device of the present invention are introduced
  • the fourth thin film transistor can realize the control of the current flowing through the first thin film transistor by using the data signal and the second reference voltage signal in the threshold voltage compensation phase, thereby realizing compensation of the threshold voltage of the first thin film transistor, that is, the driving thin film transistor;
  • Introducing the third thin film transistor can prevent the second reference voltage signal from affecting the gate potential of the first thin film transistor during the light emitting phase.

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Abstract

一种像素驱动电路（100，200，2）及OLED显示装置（1）。像素驱动电路（100，200，2）包括：第一、第二、第三、第四薄膜晶体管（T1、T2、T3、T4）、电容（C1）及有机发光二极管（D1）；其中，第三薄膜晶体管（T3）的栅极与扫描信号（Vsel1）连接，源极与第四薄膜晶体管（T4）的漏极连接，漏极与第一薄膜晶体管（T1）的源极连接；第四薄膜晶体管（T4）的栅极与数据信号（Vdata1）连接，源极与第二参考电压信号（Vref2）连接。像素驱动电路（100，200，2）通过引入第四薄膜晶体管（T4），可以实现在阈值电压补偿阶段（S1）利用数据信号（Vdata1）和第二参考电压信号（Vref2）控制流经第一薄膜晶体管（T1）的电流，从而实现对第一薄膜晶体管（T1）也即驱动薄膜晶体管（T1）的阈值电压的补偿。

Description

一种像素驱动电路及OLED显示装置 【技术领域】
本发明涉及液晶显示领域，特别是涉及一种像素驱动电路及OLED显示装置。
【背景技术】
目前的有机发光二极管(Organic Light Emitting Diode，OLED)显示装置具有体积小、结构简单、自主发光、亮度高、可视角度大、响应时间短等诸多优点，被业界公认为是最有发展潜力的液晶显示装置。
OLED显示装置是电流驱动器件，当有电流流过有机发光二极管时，有机发光二极管发光，且发光亮度由流过有机发光二极管自身的电流决定。大部分已有的集成电路都只传输电压信号，故OLED显示装置的像素驱动电路需要完成电压信号转变为电流信号的任务。传统的像素驱动电路为2T1C，即两个薄膜晶体管加一个电容的结构来实现将电压变换为电流，但传统的2T1C像素驱动电路一般无补偿功能。
图1是现有的2T1C像素驱动电路的电路示意图。如图1所示，该2T1C像素驱动电路包括：第一薄膜晶体管T10、第二薄膜晶体管T20和电容Cs。其中，第一薄膜晶体管T10为驱动薄膜晶体管，第二薄膜晶体管T20为开关薄膜晶体管，电容Cs为存储电容。具体来说，第二薄膜晶体管T20的栅极电性连接扫描信号Vsel，源极电性连接数据信号Vdata，漏极与第一薄膜晶体管T10的栅极电性连接；第一薄膜晶体管T10的漏极电性连接电源信号Vdd，源极电性连接有机发光二极管D的阳极；有机发光二极管D的阴极电性连接接地端；电容Cs的一端电性连接第二薄膜晶体管T20的漏极，另一端电性连接第一薄膜晶体管T10的源极。
请一并参考图2，图2是图1所示的2T1C像素驱动电路的工作时序图。如 图2所示，2T1C像素驱动电路的工作过程分为第一工作阶段S10和第二工作阶段S20。其中，在第一工作阶段S10，数据信号Vdata为显示数据信号高电位VDATA，扫描信号Vsel为高电位；第二工作阶段S20，数据信号Vdata为低电位，扫描信号Vsel为低电位。其中，在第一工作阶段S10和第二工作阶段S20，电源信号Vdd为恒定高电压。
在本实施例中，在第二工作阶段S20，有机发光二极管D发光，此时，驱动有机发光二极管D发光的第一薄膜晶体管T10的栅源极电压Vgs满足如下公式：
Vgs＝VDATA-VOLED；
其中，VDATA为数据信号高电位，VOLED为有机发光二极管D的阳极点电位。
由上述公式可知，驱动有机发光二极管D发光的栅源极电压Vgs中不涉及到第一薄膜晶体管T10的阈值电压，因此，该2T1C像素驱动电路无法补偿驱动薄膜晶体管(也即第一薄膜晶体管T10)的阈值电压。
【发明内容】
本发明主要解决的技术问题是提供一种像素驱动电路及OLED显示装置，能够有效地补偿驱动薄膜晶体管的阈值电压变化。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种像素驱动电路，该像素驱动电路包括：第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、电容、及有机发光二极管；第一薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第二节点，漏极电性连接于电源信号；第二薄膜晶体管的栅极电性连接于扫描信号，源极电性连接于第一参考电压信号，漏极电性连接于第一节点；第三薄膜晶体管的栅极电性连接于扫描信号，源极电性连接于第四薄膜晶体管的漏极，漏极电性连接于第二节点；第四薄膜晶体管的栅极电性连接于数据信号，源极电性连接于第二参考电压信号；电容的一端电性连接于第一节点，另一端电性连接于第二节点；发光二极管的阳极电性 连接于第二节点，发光二极管的阴极电性连接于接地端；其中，第一参考电压信号为电源信号；其中，在发光阶段，第一薄膜晶体管的栅源极电压满足如下公式：
Figure PCTCN2017081248-appb-000001
其中，Vgs为第一薄膜晶体管的栅源极电压，Vb为第二参考电压信号提供的第二参考电压，
Figure PCTCN2017081248-appb-000002
为第四薄膜晶体管的沟道的宽度长度比，
Figure PCTCN2017081248-appb-000003
为第一薄膜晶体管的沟道的宽度长度比，VDATA1为数据信号提供的显示数据信号高电位，Vth3为第三薄膜晶体管的阈值电压，Vth1为第一薄膜晶体管的阈值电压。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种像素驱动电路，该像素驱动电路包括：第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、电容、及有机发光二极管；第一薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第二节点，漏极电性连接于电源信号；第二薄膜晶体管的栅极电性连接于扫描信号，源极电性连接于第一参考电压信号，漏极电性连接于第一节点；第三薄膜晶体管的栅极电性连接于扫描信号，源极电性连接于第四薄膜晶体管的漏极，漏极电性连接于第二节点；第四薄膜晶体管的栅极电性连接于数据信号，源极电性连接于第二参考电压信号；电容的一端电性连接于第一节点，另一端电性连接于第二节点；发光二极管的阳极电性连接于第二节点，发光二极管的阴极电性连接于接地端。
为解决上述技术问题，本发明采用的再一个技术方案是：提供一种OLED显示装置，包括像素驱动电路，该像素驱动电路包括：第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、电容、及有机发光二极管；第一薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第二节点，漏极电性连接于电源信号；第二薄膜晶体管的栅极电性连接于扫描信号，源极电性连接于第一参考电压信号，漏极电性连接于第一节点；第三薄膜晶体管的栅极 电性连接于扫描信号，源极电性连接于第四薄膜晶体管的漏极，漏极电性连接于第二节点；第四薄膜晶体管的栅极电性连接于数据信号，源极电性连接于第二参考电压信号；电容的一端电性连接于第一节点，另一端电性连接于第二节点；发光二极管的阳极电性连接于第二节点，发光二极管的阴极电性连接于接地端。
本发明的有益效果是：本发明的像素驱动电路及OLED显示装置通过引入第四薄膜晶体管，可以实现在阈值电压补偿阶段利用数据信号和第二参考电压信号控制流经第一薄膜晶体管的电流，从而实现对第一薄膜晶体管也即驱动薄膜晶体管的阈值电压的补偿；通过引入第三薄膜晶体管，可以防止在发光阶段第二参考电压信号影响第一薄膜晶体管的栅极电位。
【附图说明】
图1是现有技术的2T1C像素驱动电路的电路示意图；
图2是图1所示的2T1C像素驱动电路的工作时序图；
图3是本发明第一实施例的像素驱动电路的电路示意图；
图4是图3所示像素驱动电路的工作时序图；
图5是本发明第二实施例的像素驱动电路的电路示意图；
图6是图5所示像素驱动电路的工作时序图；
图7是现有的2T1C像素驱动电路中驱动薄膜晶体管的阈值电压漂移时对应的流经有机发光二极管的电流模拟数据图；
图8是本发明的像素驱动电路中驱动薄膜晶体管的阈值电压漂移时对应的流经有机发光二极管的电流模拟数据图；
图9是本发明实施例的OLED显示装置的结构示意图。
【具体实施方式】
在说明书及权利要求书当中使用了某些词汇来指称特定的组件，所属领域 中的技术人员应可理解，制造商可能会用不同的名词来称呼同样的组件。本说明书及权利要求书并不以名称的差异来作为区分组件的方式，而是以组件在功能上的差异来作为区分的基准。下面结合附图和实施例对本发明进行详细说明。
图3是本发明第一实施例的像素驱动电路的电路示意图。如图3所示，像素驱动电路100包括第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4、电容C1和有机发光二极管D1。其中，第一薄膜晶体管T1为驱动薄膜晶体管，第二薄膜晶体管T2、第三薄膜晶体管T3为开关薄膜晶体管，电容C1为存储电容。
具体来说，第一薄膜晶体管T1的栅极电性连接于第一节点g，源极电性连接于第二节点s，漏极电性连接于电源信号Vdd1；第二薄膜晶体管T2的栅极电性连接于扫描信号Vsel1，源极电性连接于第一参考电压信号Vref1，漏极电性连接于第一节点g；第三薄膜晶体管T3的栅极电性连接于扫描信号Vsel1，源极电性连接于第四薄膜晶体管T4的漏极，漏极电性连接于第二节点s；第四薄膜晶体管T4的栅极电性连接于数据信号Vdata1，源极电性连接于第二参考电压信号Vref2；电容C1的一端电性连接于第一节点g，另一端电性连接于第二节点s；发光二极管D1的阳极电性连接于第二节点s，发光二极管D1的阴极电性连接于接地端GND。
优选地，第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管。
图4是图3所示像素驱动电路的工作时序图。如图4所示，像素驱动电路100的工作过程分为阈值电压补偿阶段S1和发光阶段S2。
其中，在像素驱动电路100的工作过程中，第一参考电压信号Vref1、第二参考电压信号Vref2为恒定低电压，其分别用于提供第一参考电压Va和第二参考电压Vb；电源信号Vdd1为恒定高电压；数据信号Vdata1、扫描信号Vsel1相组合先后对应于阈值电压补偿阶段S1和发光阶段S2。
优选地，数据信号Vdata1和扫描信号Vsel1通过外部时序控制器产生。第一参考电压信号Vref1、第二参考电压信号Vref2、电源信号Vdd1通过恒定电压源产生。
在阈值电压补偿阶段S1，数据信号Vdata1为显示数据信号高电位VDATA1，扫描信号Vsel1为高电位，从而使得第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4均处于打开状态。其中，数据信号Vdata1经过第三薄膜晶体管T3、第四薄膜晶体管T4向第一薄膜晶体管T1的源极写入显示数据信号高电位VDATA1，第一参考电压信号Vref1提供的第一参考电压Va经第二薄膜晶体管T2写入第一薄膜晶体管T1的栅极。
也就是说，在阈值电压补偿阶段S1：
Vg＝Va；
Figure PCTCN2017081248-appb-000004
Figure PCTCN2017081248-appb-000005
其中，Vg表示第一节点g的电位(也即第一薄膜晶体管T1的栅极电位)，Vs表示第二节电s的电位(也即第一薄膜晶体管T1的源极电位)，Vgs表示第一薄膜晶体管T1的栅源极电压；Va为第一参考电压，Vb为第二参考电压，
Figure PCTCN2017081248-appb-000006
为第四薄膜晶体管T4的沟道的宽度长度比，
Figure PCTCN2017081248-appb-000007
为第一薄膜晶体管T1的沟道的宽度长度比，VDATA1为数据信号高电位，Vth3为第三薄膜晶体管T3的阈值电压，Vth1为第一薄膜晶体管T1的阈值电压。
在发光阶段S2，数据信号Vdata1为低电位，扫描信号Vsel1为低电位，从而使得第一薄膜晶体管T1、第四薄膜晶体管T4处于打开状态，第二薄膜晶体管T2、第三薄膜晶体管T3处于关断状态。由于电容C1的存储作用，第一薄膜 晶体管T1的栅源极电压Vgs保持不变。
其中，驱动有机发光二极管D1发光的栅源极电压Vgs中包括了第一薄膜晶体管T10的阈值电压Vth1，而流经有机发光二极管D1的电流与栅源极电压Vgs和第一薄膜晶体管T10的阈值电压Vth1的差的平方成正比，从而使得流经有机发光二极管D1的电流与第一薄膜晶体管T10(也即驱动薄膜晶体管)的阈值电压Vth1无关，实现了阈值电压补偿功能。
在本实施例中，在补偿阶段S1，通过第四薄膜晶体管T4的栅极由数据信号高电位VDATA1控制，源极由第二参考电压Vb控制，从而可以实现利用数据信号高电位VDATA1和第二参考电压Vb控制流经第一薄膜晶体管T10的电流；在发光阶段S2，第三薄膜晶体管T3可以防止第二参考电压Vb影响第一薄膜晶体管T10的栅极电位。
在本实施例中，为了保证在像素驱动电路100工作过程中，第一薄膜晶体管T1被正常打开，第二参考电压Vb满足如下公式：
Vb＜VDATA1-Vth3。(2)
在本实施例中，为了保证在阈值电压补偿阶段S1中，第一薄膜晶体管T1被正常打开且有机发光二极管D1不能被开启，第一参考电压Va满足如下公式：
Figure PCTCN2017081248-appb-000008
且
Figure PCTCN2017081248-appb-000009
其中，Voled1为在阈值电压补偿阶段，有机发光二极管D1的阳极点电位。
图5是本发明第二实施例的像素驱动电路的电路示意图。如图5所示，图5所示的像素驱动电路200与图3所示的像素驱动电路100的区别是：第一参考电压信号Vref1为电源信号Vdd1。
也就是说，像素驱动电路200中没有第一参考电压信号Vref1，第二薄膜晶体管T2的源极直接与电源信号Vdd1连接。
请一并参考图6，图6是图5所示像素驱动电路的工作时序图。如图6所示，图6所示的像素驱动电路200的工作时序图与图4所示的像素驱动电路100的工作时序图的区别是：在阈值电压补偿阶段S1，电源信号Vdd1为参考低电位，其中，参考低电位为第一参考电压Va；在发光阶段S2，电源信号Vdd1为高电位。
在本实施例中，电源信号Vdd1、数据信号Vdata1和扫描信号Vsel1通过外部时序控制器产生。第二参考电压信号Vref2通过恒定电压源产生。
在本实施例中，第一薄膜晶体管T1的栅极电位、源极电位和栅源极电压满足公式(1)；第一参考电压Va满足公式(3)；第二参考电压Vb满足公式(2)。
需要强调的是，不同于第一实施例，在本实施例中，第一参考电压Va为电源信号Vdd1的参考低电位。
请一并参考图7和图8，图7和图8分别为传统无补偿2T1C像素驱动电路和本发明的像素驱动电路100或200中，当驱动薄膜晶体管也即第一薄膜晶体管T10的阈值电压Vth的漂移值ΔVth和第一薄膜晶体管T1的阈值电压Vth1的漂移值ΔVoled分别为0V、+0.5V、-0.5V时，流经有机发光二极管的电流IOLED的模拟数据图。对比两图可见，本发明的电路中流经有机发光二极管的电流变化量明显小于传统无补偿2T1C像素驱动电路中的流经有机发光二极管的电流变化量，因此本发明能够有效地补偿驱动薄膜晶体管的阈值电压，保证了有机发光二极管的发光稳定性，能够使OLED显示面板的显示亮度保持均匀，不会伴随阈值电压随使用时间发生变化而变化，提升显示品质。
图9是本发明实施例的OLED显示装置的结构示意图。如图9所示，OLED显示装置1包括像素驱动电路2，其中，像素驱动电路2为上述像素驱动电路100或像素驱动电路200。
本发明的有益效果是：本发明的像素驱动电路及OLED显示装置通过引入 第四薄膜晶体管，可以实现在阈值电压补偿阶段利用数据信号和第二参考电压信号控制流经第一薄膜晶体管的电流，从而实现对第一薄膜晶体管也即驱动薄膜晶体管的阈值电压的补偿；通过引入第三薄膜晶体管，可以防止在发光阶段第二参考电压信号影响第一薄膜晶体管的栅极电位。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (20)

  1. 一种像素驱动电路，其中，所述像素驱动电路包括：第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、电容、及有机发光二极管；
    所述第一薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第二节点，漏极电性连接于电源信号；
    所述第二薄膜晶体管的栅极电性连接于扫描信号，源极电性连接于第一参考电压信号，漏极电性连接于所述第一节点；
    所述第三薄膜晶体管的栅极电性连接于扫描信号，源极电性连接于所述第四薄膜晶体管的漏极，漏极电性连接于所述第二节点；
    所述第四薄膜晶体管的栅极电性连接于数据信号，源极电性连接于第二参考电压信号；
    所述电容的一端电性连接于第一节点，另一端电性连接于第二节点；
    所述发光二极管的阳极电性连接于第二节点，所述发光二极管的阴极电性连接于接地端；
    其中，所述第一参考电压信号为所述电源信号；
    其中，在发光阶段，所述第一薄膜晶体管的栅源极电压满足如下公式：
    Figure PCTCN2017081248-appb-100001
    其中，Vgs为所述第一薄膜晶体管的栅源极电压，Vb为所述第二参考电压信号提供的第二参考电压，
    Figure PCTCN2017081248-appb-100002
    为所述第四薄膜晶体管的沟道的宽度长度比，
    Figure PCTCN2017081248-appb-100003
    为所述第一薄膜晶体管的沟道的宽度长度比，VDATA1为所述数据信号提供的显示数据信号高电位，Vth3为所述第三薄膜晶体管的阈值电压，Vth1为所 述第一薄膜晶体管的阈值电压。
  2. 根据权利要求1所述的像素驱动电路，其中，所述第二参考电压信号为恒定低电压，所述电源信号、所述扫描信号、所述数据信号相组合先后对应于阈值电压补偿阶段和发光阶段；
    在所述阈值电压补偿阶段，所述电源信号为参考低电位，所述数据信号为显示数据信号高电位，所述扫描信号为高电位；
    在所述发光阶段，所述电源信号为高电位，所述数据信号为低电位，所述扫描信号为低电。
  3. 一种像素驱动电路，其中，所述像素驱动电路包括：第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、电容、及有机发光二极管；
    所述第一薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第二节点，漏极电性连接于电源信号；
    所述第二薄膜晶体管的栅极电性连接于扫描信号，源极电性连接于第一参考电压信号，漏极电性连接于所述第一节点；
    所述第三薄膜晶体管的栅极电性连接于扫描信号，源极电性连接于所述第四薄膜晶体管的漏极，漏极电性连接于所述第二节点；
    所述第四薄膜晶体管的栅极电性连接于数据信号，源极电性连接于第二参考电压信号；
    所述电容的一端电性连接于第一节点，另一端电性连接于第二节点；
    所述发光二极管的阳极电性连接于第二节点，所述发光二极管的阴极电性连接于接地端。
  4. 根据权利要求3所述的像素驱动电路，其中，所述第一参考电压信号、所述第二参考电压信号为恒定低电压，所述电源信号为恒定高电压，所述数据信号、所述扫描信号相组合先后对应于阈值电压补偿阶段和发光阶段；
    在所述阈值电压补偿阶段，所述数据信号为显示数据信号高电位，所述扫 描信号为高电位；
    在所述发光阶段，所述数据信号为低电位，所述扫描信号为低电位。
  5. 根据权利要求4所述的像素驱动电路，其中，所述数据信号和所述扫描信号通过外部时序控制器产生。
  6. 根据权利要求3所述的像素驱动电路，其中，所述第一参考电压信号为所述电源信号。
  7. 根据权利要求6所述的像素驱动电路，其中，所述第二参考电压信号为恒定低电压，所述电源信号、所述扫描信号、所述数据信号相组合先后对应于阈值电压补偿阶段和发光阶段；
    在所述阈值电压补偿阶段，所述电源信号为参考低电位，所述数据信号为显示数据信号高电位，所述扫描信号为高电位；
    在所述发光阶段，所述电源信号为高电位，所述数据信号为低电位，所述扫描信号为低电位。
  8. 根据权利要求7所述的像素驱动电路，其中，所述电源信号、所述数据信号和所述扫描信号通过外部时序控制器产生。
  9. 根据权利要求3所述的像素驱动电路，其中，在发光阶段，所述第一薄膜晶体管的栅源极电压满足如下公式：
    Figure PCTCN2017081248-appb-100004
    其中，Vgs为所述第一薄膜晶体管的栅源极电压，Vb为所述第二参考电压信号提供的第二参考电压，
    Figure PCTCN2017081248-appb-100005
    为所述第四薄膜晶体管的沟道的宽度长度比，
    Figure PCTCN2017081248-appb-100006
    为所述第一薄膜晶体管的沟道的宽度长度比，VDATA1为所述数据信号提供的显示数据信号高电位，Vth3为所述第三薄膜晶体管的阈值电压，Vth1为所述第一薄膜晶体管的阈值电压。
  10. 根据权利要求3所述的像素驱动电路，其中，所述第二参考电压信号提供的第二参考电压Vb满足如下公式：
    Vb＜VDATA1-Vth3；
    其中，VDATA1为所述数据信号提供的显示数据信号高电位，Vth3为所述第三薄膜晶体管的阈值电压。
  11. 根据权利要求3所述的像素驱动电路，其中，所述第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管。
  12. 一种OLED显示装置，其中，包括像素驱动电路，所述像素驱动电路包括：第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、电容、及有机发光二极管；
    所述第一薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第二节点，漏极电性连接于电源信号；
    所述第二薄膜晶体管的栅极电性连接于扫描信号，源极电性连接于第一参考电压信号，漏极电性连接于所述第一节点；
    所述第三薄膜晶体管的栅极电性连接于扫描信号，源极电性连接于所述第四薄膜晶体管的漏极，漏极电性连接于所述第二节点；
    所述第四薄膜晶体管的栅极电性连接于数据信号，源极电性连接于第二参考电压信号；
    所述电容的一端电性连接于第一节点，另一端电性连接于第二节点；
    所述发光二极管的阳极电性连接于第二节点，所述发光二极管的阴极电性连接于接地端。
  13. 根据权利要求12所述的OLED显示装置，其中，所述第一参考电压信号、所述第二参考电压信号为恒定低电压，所述电源信号为恒定高电压，所述数据信号、所述扫描信号相组合先后对应于阈值电压补偿阶段和发光阶段；
    在所述阈值电压补偿阶段，所述数据信号为显示数据信号高电位，所述扫 描信号为高电位；
    在所述发光阶段，所述数据信号为低电位，所述扫描信号为低电位。
  14. 根据权利要求13所述的OLED显示装置，其中，所述数据信号和所述扫描信号通过外部时序控制器产生。
  15. 根据权利要求12所述的OLED显示装置，其中，所述第一参考电压信号为所述电源信号。
  16. 根据权利要求15所述的OLED显示装置，其中，所述第二参考电压信号为恒定低电压，所述电源信号、所述扫描信号、所述数据信号相组合先后对应于阈值电压补偿阶段和发光阶段；
    在所述阈值电压补偿阶段，所述电源信号为参考低电位，所述数据信号为显示数据信号高电位，所述扫描信号为高电位；
    在所述发光阶段，所述电源信号为高电位，所述数据信号为低电位，所述扫描信号为低电位。
  17. 根据权利要求16所述的OLED显示装置，其中，所述电源信号、所述数据信号和所述扫描信号通过外部时序控制器产生。
  18. 根据权利要求12所述的OLED显示装置，其中，在发光阶段，所述第一薄膜晶体管的栅源极电压满足如下公式：
    Figure PCTCN2017081248-appb-100007
    其中，Vgs为所述第一薄膜晶体管的栅源极电压，Vb为所述第二参考电压信号提供的第二参考电压，
    Figure PCTCN2017081248-appb-100008
    为所述第四薄膜晶体管的沟道的宽度长度比，
    Figure PCTCN2017081248-appb-100009
    为所述第一薄膜晶体管的沟道的宽度长度比，VDATA1为所述数据信号提供的显示数据信号高电位，Vth3为所述第三薄膜晶体管的阈值电压，Vth1为所述第一薄膜晶体管的阈值电压。
  19. 根据权利要求12所述的OLED显示装置，其中，所述第二参考电压信号提供的第二参考电压Vb满足如下公式：
    Vb＜VDATA1-Vth3；
    其中，VDATA1为所述数据信号提供的显示数据信号高电位，Vth3为所述第三薄膜晶体管的阈值电压。
  20. 根据权利要求12所述的OLED显示装置，其中，所述第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管。
PCT/CN2017/081248 2017-03-16 2017-04-20 一种像素驱动电路及oled显示装置 Ceased WO2018166037A1 (zh)

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