WO2018205606A1 - 薄膜晶体管及其制备方法、显示面板和显示装置 - Google Patents

薄膜晶体管及其制备方法、显示面板和显示装置 Download PDF

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WO2018205606A1
WO2018205606A1 PCT/CN2017/116200 CN2017116200W WO2018205606A1 WO 2018205606 A1 WO2018205606 A1 WO 2018205606A1 CN 2017116200 W CN2017116200 W CN 2017116200W WO 2018205606 A1 WO2018205606 A1 WO 2018205606A1
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layer
dielectric layer
thin film
film transistor
light shielding
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English (en)
French (fr)
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陈江博
宋泳锡
李伟
闫梁臣
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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Priority to JP2018543629A priority Critical patent/JP6949038B2/ja
Priority to US15/999,687 priority patent/US11251309B2/en
Priority to EP17896318.7A priority patent/EP3627560A4/en
Publication of WO2018205606A1 publication Critical patent/WO2018205606A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6723—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device having light shields
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H10D30/6734—Multi-gate TFTs having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6758—Thin-film transistors [TFT] characterised by the insulating substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/411—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by materials, geometry or structure of the substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO

Definitions

  • Embodiments of the present disclosure relate to the field of display technologies, and in particular, to a thin film transistor, a method of fabricating the same, a display panel, and a display device.
  • oxide thin film transistors have the characteristics of high electron mobility, low preparation temperature, and good uniformity, and thus are increasingly used by people.
  • the illumination of the light-emitting unit affects the thin film transistor, thereby affecting the light stability of the thin film transistor.
  • Embodiments of the present disclosure provide a thin film transistor, a method of fabricating the same, a display panel, and a display device.
  • a thin film transistor including: a substrate; an active layer over the substrate; and a substrate between the substrate and the active layer a light shielding layer, a first dielectric layer, and a second dielectric layer, wherein the first dielectric layer is located between the second dielectric layer and the substrate, and a refractive index of the first dielectric layer is greater than the second The refractive index of the dielectric layer.
  • the light shielding layer is between the substrate and the first dielectric layer.
  • the thin film transistor further includes a light blocking portion disposed on the substrate in the same layer and spaced apart from the light shielding layer, wherein the first dielectric layer covers the light shielding layer And the light blocking portion.
  • the number of the light blocking portions includes at least two, and the light blocking portions are disposed on both sides of the light shielding layer.
  • the material of the light blocking portion is the same as the material of the light shielding layer.
  • the cross-sectional shape of the light blocking portion includes a triangle, a circle, or a trapezoid.
  • the light shielding layer is between the first dielectric layer and the second dielectric layer.
  • the first dielectric layer comprises silicon nitride and the second dielectric layer comprises silicon oxide.
  • the thin film transistor further includes: a gate stack over the active layer, wherein the active layer includes a channel region under the gate stack and respectively a source/drain region on both sides of the channel region, the gate stack including a gate insulating layer and a gate over the gate insulating layer; at the second dielectric layer, the An active layer and an interlayer insulating layer over the gate stack, wherein the interlayer insulating layer includes a via hole exposing the source/drain region; and a via over the interlayer insulating layer The via is connected to the source/drain electrodes of the source/drain regions; and a passivation layer over the interlayer insulating layer and the source/drain electrodes.
  • a method of fabricating a thin film transistor comprising: forming a light shielding layer and a first dielectric layer on a substrate; forming on the light shielding layer and the first dielectric layer a second dielectric layer covering the light shielding layer and the first dielectric layer, wherein a refractive index of the first dielectric layer is greater than a refractive index of the second dielectric layer; and forming on the second dielectric layer Active layer.
  • forming the light shielding layer and the first dielectric layer on the substrate includes: forming the light shielding layer on the substrate; and on the light shielding layer and the substrate Forming the first dielectric layer.
  • the method further includes forming a light blocking portion disposed on the substrate in the same layer and spaced apart from the light shielding layer, the first dielectric layer covering the light shielding layer and the light blocking portion .
  • the material of the light blocking portion is the same as the material of the light shielding layer.
  • forming the light shielding layer and the first dielectric layer on the substrate includes: forming the first dielectric layer on the substrate; and forming on the first dielectric layer The light shielding layer.
  • the method further includes forming a gate stack over the active layer, wherein the active layer includes a channel region under the gate stack and respectively located a source/drain region on both sides of the channel region, the gate stack including a gate insulating layer and a gate over the gate insulating layer; forming an interlayer insulating layer to cover the second a dielectric layer, the active layer, and the gate stack; patterning the interlayer insulating layer to simultaneously form vias exposing the source/drain regions in the interlayer insulating layer; a conductive layer is formed on the insulating layer to fill the via; the conductive layer is patterned to form source/drain electrodes connected to the source/drain regions via the via; and the interlayer insulating layer and A passivation layer is formed on the source/drain electrodes.
  • a display panel including the thin film transistor described in the first aspect of the embodiment of the present disclosure.
  • a display device including the display panel described in the third aspect of the embodiment of the present disclosure.
  • FIG. 1 is a schematic view of a cross section of a thin film transistor in accordance with an embodiment of the present disclosure
  • FIG. 2 is a schematic view of a cross section of a thin film transistor in accordance with an embodiment of the present disclosure
  • FIG. 3 is a schematic view of a reflection effect of a light blocking portion according to an embodiment of the present disclosure
  • FIG. 4 is a schematic view of a cross section of a thin film transistor in accordance with an embodiment of the present disclosure
  • FIG. 5 is a flow chart of a method of fabricating a thin film transistor in accordance with an embodiment of the present disclosure
  • FIG. 6 is a schematic view showing formation of a light shielding layer of a thin film transistor according to an embodiment of the present disclosure
  • FIG. 7 is a schematic diagram of formation of a first dielectric layer of a thin film transistor according to an embodiment of the present disclosure
  • FIG. 8 is a schematic diagram of formation of a second dielectric layer of a thin film transistor according to an embodiment of the present disclosure
  • FIG. 9 is a schematic diagram of formation of an active layer of a thin film transistor according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic view showing the formation of a gate stack of a thin film transistor according to an embodiment of the present disclosure
  • FIG. 11 is a schematic view showing formation of an interlayer insulating layer of a thin film transistor according to an embodiment of the present disclosure
  • FIG. 12 is a schematic diagram of formation of via holes of a thin film transistor according to an embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram of formation of source/drain electrodes of a thin film transistor according to an embodiment of the present disclosure
  • FIG. 14 is a schematic view showing formation of a passivation layer of a thin film transistor according to an embodiment of the present disclosure
  • FIG. 15 is a flow chart of a method of fabricating a thin film transistor in accordance with an embodiment of the present disclosure
  • 16 is a schematic diagram of formation of a light shielding layer and a light blocking portion of a thin film transistor according to an embodiment of the present disclosure
  • FIG. 17 is a schematic diagram of formation of a first dielectric layer of a thin film transistor in accordance with an embodiment of the present disclosure
  • FIG. 18 is a schematic view showing the formation of a second dielectric layer of a thin film transistor according to an embodiment of the present disclosure
  • FIG. 19 is a flow chart of a method of fabricating a thin film transistor in accordance with an embodiment of the present disclosure
  • FIG. 20 is a schematic diagram of formation of a first dielectric layer of a thin film transistor according to an embodiment of the present disclosure
  • 21 is a schematic view showing formation of a light shielding layer of a thin film transistor according to an embodiment of the present disclosure
  • FIG. 22 is a schematic diagram of formation of a second dielectric layer of a thin film transistor according to an embodiment of the present disclosure. Figure.
  • a light shielding layer is generally provided between the active layer and the substrate.
  • the light shielding layer is capable of reflecting part of the incident light, thereby reducing light incident on the active layer.
  • light incident from both sides of the light shielding layer is still incident on the active layer, affecting the light stability of the thin film transistor. Ben The inventors have found through research that when the active layer is an oxide semiconductor, this adverse effect of light incident from both sides of the light shielding layer is particularly remarkable.
  • a thin film transistor in the embodiments described herein, includes a high refractive index dielectric layer and a low refractive index dielectric layer such that light incident from both sides of the light shielding layer is reflected out of the substrate by reflection at an interface of the high-low refractive index dielectric layer, or The light propagates laterally between the top surface of the light shielding layer and the top surface of the high refractive index dielectric layer. This can reduce the light intensity incident on the active layer, thereby improving the light stability of the thin film transistor.
  • FIG. 1 is a schematic view of a cross section of a thin film transistor according to an embodiment of the present disclosure.
  • the thin film transistor 100 includes: a substrate 1; a light shielding layer 2 over the substrate 1, a first dielectric layer 3 over the substrate 1 and the light shielding layer 2, and a first dielectric layer 3.
  • a second dielectric layer 4 an active layer 5 over the second dielectric layer 4; a gate stack 67 over the active layer 5, wherein the active layer 5 comprises a gate stack 67 a lower channel region 53 and source/drain regions 51, 52 respectively located on both sides of the channel region 53, the gate stack 67 comprises a gate insulating layer 6 and a gate 7 over the gate insulating layer 6;
  • An interlayer insulating layer 8 over the second dielectric layer 4, the gate stack 67, and the source/drain regions 51, 52, wherein the interlayer insulating layer 8 includes vias exposing the source/drain regions 51, 52 (not shown); source/drain electrode layer 9 over interlayer insulating layer 8, wherein source/drain electrode layer 9 includes sources connected to source/drain regions 51, 52 via vias, respectively The drain electrodes 91, 92; and the passivation layer 10 over the interlayer insulating layer 8 and the source/drain electrode layer 9.
  • the refractive index of the first dielectric layer 3 is greater than the refractive index of the second dielectric layer 4.
  • the first dielectric layer 3 comprises silicon nitride
  • the second dielectric layer 4 comprises silicon oxide
  • the first dielectric layer 3 has a refractive index of 2.0 and the second dielectric layer 4 has a refractive index of 1.4.
  • the materials of the first dielectric layer 3 and the second dielectric layer 4 are not limited to the above materials as long as the refractive index of the first dielectric layer 3 is greater than the refractive index of the second dielectric layer 4.
  • the first dielectric layer 3 has a thickness of 100 nm to 500 nm, and the second dielectric layer 4 has a thickness of 5 nm to 1000 nm.
  • the first medium The thickness of layer 3 is 100 nm, and the thickness of second dielectric layer 4 is 200 nm.
  • the substrate 1 is glass. It is to be understood that the substrate 1 may be other known materials as long as the substrate 1 is transparent.
  • the light shielding layer 2 includes a metal layer. In an exemplary embodiment, the light shielding layer 2 includes Mo, AlNd, Al, Cu, or the like. In an exemplary embodiment, the light shielding layer 2 has a thickness of 50 nm to 400 nm. In an exemplary embodiment, the light shielding layer 2 has a thickness of 100 nm.
  • the active layer 5 comprises a semiconductor material. It should be understood that the embodiments of the present disclosure are not particularly limited to the material of the semiconductor.
  • the active layer 5 includes an oxide semiconductor material such as IGZO, ITZO, or the like.
  • the active layer 5 has a thickness of 10 nm to 100 nm. In an exemplary embodiment, the active layer 5 has a thickness of 40 nm.
  • the gate insulating layer 6 includes silicon oxide. In an exemplary embodiment, the gate insulating layer 6 has a thickness of 100 nm to 500 nm. In an exemplary embodiment, the gate insulating layer 6 has a thickness of 150 nm.
  • the gate 7 includes a MoNb/Cu/MoNb composite metal film layer. It can be understood that the gate of the embodiment of the present disclosure may also adopt other well-known composite metal film layers.
  • the thickness of the gate electrode 7 is from 200 nm to 1000 nm. In an exemplary embodiment, the thickness of the gate 7 is 480 nm.
  • the interlayer insulating layer 8 includes silicon oxide. In an exemplary embodiment, the interlayer insulating layer 8 has a thickness of 100 nm to 500 nm. In an exemplary embodiment, the interlayer insulating layer 8 has a thickness of 300 nm.
  • the source/drain electrode layer 9 includes Mo, Al, Cu, or a composite film layer thereof or the like. In an exemplary embodiment, the source/drain electrode layer 9 has a thickness of 50 nm to 1000 nm. In an exemplary embodiment, the source/drain electrode layer 9 has a thickness of 480 nm.
  • passivation layer 10 comprises silicon nitride or silicon oxide. In an exemplary embodiment, the passivation layer 10 has a thickness of 200 nm to 400 nm. In an exemplary embodiment, the passivation layer 10 has a thickness of 300 nm.
  • the buffer layer employs a combination of a high refractive index dielectric layer and a low refractive index dielectric layer.
  • the buffer layer employs a combination of a high refractive index dielectric layer and a low refractive index dielectric layer.
  • FIG. 2 is a schematic diagram of a cross section of a thin film transistor in accordance with an embodiment of the present disclosure. As shown in FIG. 2, FIG. 2 differs from FIG. 1 in that, on the basis of FIG. 1, FIG. 2 further includes two layers on the substrate 1 which are disposed in the same layer and spaced apart from the light shielding layer 2 on both sides of the light shielding layer 2. Light blocking portion 11. Also, the first dielectric layer 3 in FIG. 2 covers the light shielding layer 2, the light blocking portion 11, and the substrate 1.
  • the number of the light blocking portions 11 includes at least two, and the light blocking portions 11 are disposed on both sides of the light shielding layer 2 as shown in FIG.
  • the material of the light blocking portion 11 is the same as the material of the light shielding layer 2. This makes it possible to simultaneously form the light blocking portion 11 and the light shielding layer 2 by patterning the same material layer once, so that the manufacturing steps can be simplified.
  • the cross-sectional shape of the light blocking portion 11 is a trapezoidal shape in which the cross section is perpendicular to the substrate 1.
  • the cross-sectional shape of the light blocking portion 11 may be a triangle or a circle.
  • FIG. 3 is a schematic diagram of a reflection effect of a light blocking portion according to an embodiment of the present disclosure.
  • the incident light when incident light is incident on the outside of the protrusion formed by the first dielectric layer 3 covering the light blocking portion 11 and at a position far from the protrusion, the incident light is not incident after being reflected by the a position. It is on the side surface of the light blocking portion 11, but is directly emitted from the substrate 1.
  • the incident light enters When incident to the b-position outside the projection and closer to the projection, the incident light is reflected by the b-position and then incident on the side surface of the light-blocking portion 11, and then reflected by the light-blocking portion 11 to be emitted from the substrate 1.
  • FIG. 3(a) when incident light is incident on the outside of the protrusion formed by the first dielectric layer 3 covering the light blocking portion 11 and at a position far from the protrusion, the incident light is not incident after being reflected by the a position. It is on the side surface of the light
  • the light blocking portion 11 By the design of the light blocking portion 11, light incident from both sides of the light shielding layer 2 is emitted from the thin film transistor, and incident light can be prevented from entering between the top surface of the light shielding layer 2 and the top surface of the high refractive index dielectric layer 3 to propagate. Thereby, the light intensity of the active layer entering the thin film transistor is more effectively reduced. Therefore, the light stability of the thin film transistor is more effectively improved.
  • FIG. 4 is a schematic view showing a cross section of a thin film transistor according to an embodiment of the present disclosure. 4 is different from FIG. 1 in that the positions of the light shielding layer and the first dielectric layer of the thin film transistor 300 in FIG. 4 are different from those of the thin film transistor 100 of FIG.
  • the first dielectric layer 3 is located above the substrate 1
  • the light shielding layer 2 is located above the first dielectric layer 3
  • the second dielectric layer 4 covers the first dielectric layer 3 and the light shielding layer 2.
  • the same portions of FIG. 4 as those of FIG. 1 are as described above, and are not described herein again.
  • the light in the case of light-irradiating the thin film transistor, the light is first incident on the high refractive index dielectric layer, and the incident light satisfying the total reflection condition is reflected and exits the thin film transistor when it reaches the interface of the high-low refractive index dielectric layer. This reduces the light intensity entering the active layer of the thin film transistor, thereby improving the light stability of the thin film transistor.
  • a method of preparing the above thin film transistor is also provided. Since the thin film transistor includes a high refractive index dielectric layer and a low refractive index dielectric layer, the light intensity entering the active layer can be reduced, thereby improving the light stability of the thin film transistor.
  • a method of fabricating a thin film transistor provided by an embodiment of the present disclosure will now be described in detail with reference to FIGS. 5 through 22.
  • FIG. 5 is a flow chart illustrating a method of fabricating a thin film transistor in accordance with an embodiment of the present disclosure. As shown in FIG. 5, in step S101, a light shielding layer is formed on the substrate. FIG. 6 further shows a schematic view of the formation of the light shielding layer 2.
  • a patterned light shielding layer 2 is formed on the substrate 1.
  • the method of forming the light shielding layer 2 includes a sputtering method or an evaporation method.
  • step S102 a first dielectric layer is formed over the light shielding layer and the substrate.
  • FIG. 7 further shows a schematic view of forming the first dielectric layer 3.
  • the first dielectric layer 3 is formed to completely cover the light shielding layer 2 and the substrate 1.
  • the method of forming the first dielectric layer 3 includes a plasma enhanced chemical vapor deposition method.
  • step S103 a second dielectric layer is formed on the first dielectric layer.
  • FIG. 8 further shows a schematic view of forming the second dielectric layer 4.
  • a second dielectric layer 4 is formed on the first dielectric layer 3.
  • the method of forming the second dielectric layer 4 includes a plasma enhanced chemical vapor deposition method.
  • step S104 an active layer is formed on the second dielectric layer.
  • FIG. 9 further shows a schematic view of forming the active layer 5.
  • a patterned active layer 5 is formed on the second dielectric layer 4.
  • the method of forming the active layer 5 includes a sputtering method or an evaporation method.
  • FIG. 10 further illustrates a schematic diagram of forming a gate stack 67.
  • a patterned gate stack 67 is formed on the active layer 5, wherein the active layer 5 includes a channel region 53 under the gate stack 67 and two in the channel region 53, respectively.
  • the side source/drain regions 51, 52, the gate stack 67 includes a gate insulating layer 6 and a gate 7 over the gate insulating layer 6.
  • a method of forming the gate insulating layer 6 includes a plasma enhanced chemical vapor deposition method; a method of forming the gate electrode 7 includes a sputtering method or an evaporation method.
  • step S106 an interlayer insulating layer is formed to cover the second dielectric layer, the active layer, and the gate stack.
  • FIG. 11 further shows a schematic view of forming the interlayer insulating layer 8.
  • an interlayer insulating layer 8 is formed to cover the second dielectric layer 4, the active layer 5, and the gate stack 67.
  • the method of forming the interlayer insulating layer 8 includes a plasma enhanced chemical vapor deposition method.
  • step S107 an interlayer insulating layer is patterned to simultaneously form a first via hole and a second via hole in the interlayer insulating layer.
  • FIG. 12 further shows a schematic view of forming the first via 81 and the second via 82.
  • the interlayer insulating layer 8 is patterned to form a first via 81 exposing the source/drain regions 51 and a second via 82 exposing the source/drain regions 52 in the interlayer insulating layer 8.
  • the first via 81 and the second via 82 may be formed by dry etching.
  • step S108 source/drain electrodes filling the first and second via holes are formed on the interlayer insulating layer.
  • FIG. 13 further shows a schematic diagram of forming the source/drain electrodes 91 and the source/drain electrodes 92.
  • step S108 further includes forming a conductive layer on the interlayer insulating layer 8, and then patterning the conductive layer to form a connection to the source/drain region 51 via the first via 81 on the interlayer insulating layer 8.
  • the source/drain electrodes 91 and the source/drain electrodes 92 connected to the source/drain regions 52 via the second vias 82.
  • a method of forming a conductive layer includes a sputtering method.
  • step S109 a passivation layer is formed over the interlayer insulating layer and the source/drain electrodes.
  • FIG. 14 further shows a schematic diagram of forming the passivation layer 10.
  • a passivation layer 10 is formed on the interlayer insulating layer 8 and the source/drain electrodes 91 and the source/drain electrodes 92.
  • the method of forming the passivation layer 10 includes a plasma enhanced chemical vapor deposition method.
  • FIG. 15 is a flowchart illustrating a method of fabricating a thin film transistor according to an embodiment of the present disclosure, wherein since the steps after forming the second dielectric layer are the same as those of the embodiment shown in FIG. 5, for the sake of brevity, not shown These steps.
  • FIG. 15 is different from FIG. 5 in that step S101a in FIG. 15 further includes forming a light blocking portion on the substrate; and step S102a is forming a first dielectric layer to cover the light shielding layer and the light blocking portion. And the substrate; and step S103a is at the first A second dielectric layer is formed on the dielectric layer.
  • FIG. 16 further shows a schematic view of forming the light blocking portion 11.
  • FIG. 17 further shows a schematic view of forming the first dielectric layer 3.
  • FIG. 18 further shows a schematic view of forming the second dielectric layer 4.
  • a patterned light shielding layer 2 and a light blocking portion 11 which are disposed in the same layer and spaced apart from the light shielding layer 2 are formed on the substrate 1, wherein the light blocking portion 11 is located on both sides of the light shielding layer 2.
  • the first dielectric layer 3 is formed to cover the light shielding layer 2, the light blocking portion 11, and the substrate 1.
  • a second dielectric layer 4 is formed on the first dielectric layer 3, and the second dielectric layer 4 completely covers the first dielectric layer 3.
  • FIG. 19 is a flowchart illustrating a method of fabricating a thin film transistor according to an embodiment of the present disclosure, in which since the steps after forming the second dielectric layer are the same as those of the embodiment illustrated in FIG. 5, for the sake of brevity, not shown These steps.
  • FIG. 19 is different from FIG. 5 in that step S101b in FIG. 19 is to form a first dielectric layer on a substrate; step S102b is to form a light shielding layer on the first dielectric layer; and step S103b
  • a second dielectric layer is formed to cover the first dielectric layer and the light shielding layer.
  • FIG. 20 further shows a schematic view of forming the first dielectric layer 3.
  • FIG. 21 further shows a schematic view of the formation of the light shielding layer 2.
  • FIG. 22 further shows a schematic view of forming the second dielectric layer 4.
  • a first dielectric layer 3 is formed on the substrate 1.
  • a patterned light shielding layer 2 is formed on the first dielectric layer 3.
  • a second dielectric layer 4 is formed to cover the first dielectric layer 3 and the light shielding layer 2.
  • the buffer layer in the thin film transistor employs a combination of a high refractive index dielectric layer and a low refractive index dielectric layer.
  • the buffer layer in the thin film transistor employs a combination of a high refractive index dielectric layer and a low refractive index dielectric layer.
  • the light intensity entering the active layer of the thin film transistor is reduced, thereby improving the light stability of the thin film transistor.
  • a light reflecting portion disposed in the same layer as the light shielding layer and located on both sides of the light shielding layer is formed on the substrate of the thin film transistor, so that light can be prevented from propagating between the top surface of the light shielding layer and the top surface of the high refractive index dielectric layer, thereby The light intensity entering the active layer in the thin film transistor is more effectively reduced. Therefore, the light stability of the thin film transistor is more effectively improved.
  • Embodiments of the present disclosure also provide a display panel including the above-described thin film transistor, which can improve the light stability of the thin film transistor.
  • Embodiments of the present disclosure also provide a display device including the above display panel, which can improve the display effect of the display device.

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  • Engineering & Computer Science (AREA)
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  • Thin Film Transistor (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

一种薄膜晶体管及其制备方法、显示面板和显示装置，所述薄膜晶体管包括：衬底(1)；位于所述衬底(1)之上的有源层(5)；以及位于所述衬底(1)与所述有源层(5)之间的遮光层(2)、第一介质层(3)和第二介质层(4)，其中，所述第一介质层(3)位于所述第二介质层(4)与所述衬底(1)之间，所述第一介质层(3)的折射率大于所述第二介质层(4)的折射率。

Description

薄膜晶体管及其制备方法、显示面板和显示装置
相关申请的交叉引用
本申请要求于2017年5月12日递交的中国专利申请第201710334764.8号优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及显示技术领域，尤其涉及一种薄膜晶体管及其制备方法、显示面板和显示装置。
背景技术
随着显示技术的不断发展，氧化物薄膜晶体管具有电子迁移率高、制备温度低、均一性好等特点，由此越来越受到人们的广泛使用。然而，在顶栅型薄膜晶体管中，发光单元的光照会对薄膜晶体管产生影响，从而影响薄膜晶体管的光照稳定性。
发明内容
本公开的实施例提供了一种薄膜晶体管及其制备方法、显示面板和显示装置。
在本公开的实施例的第一方面中，提供一种薄膜晶体管，包括：衬底；位于所述衬底之上的有源层；以及位于所述衬底与所述有源层之间的遮光层、第一介质层和第二介质层，其中，所述第一介质层位于所述第二介质层与所述衬底之间，所述第一介质层的折射率大于所述第二介质层的折射率。
在一个实施例中，所述遮光层位于所述衬底与所述第一介质层之间。
在一个实施例中，所述薄膜晶体管还包括位于所述衬底上的与所述遮光层同层且间隔设置的光阻挡部，其中，所述第一介质层覆盖所述遮光层 和所述光阻挡部。
在一个实施例中，所述光阻挡部的数量包括至少两个，所述光阻挡部设置在所述遮光层的两侧。
在一个实施例中，所述光阻挡部的材料与所述遮光层的材料相同。
在一个实施例中，所述光阻挡部的截面形状包括三角形、圆形或梯形。
在一个实施例中，所述遮光层位于所述第一介质层与所述第二介质层之间。
在一个实施例中，所述第一介质层包括氮化硅，所述第二介质层包括氧化硅。
在一个实施例中，所述薄膜晶体管还包括：位于所述有源层之上的栅极叠层，其中，所述有源层包括位于所述栅极叠层之下的沟道区以及分别位于所述沟道区两侧的源/漏极区，所述栅极叠层包括栅极绝缘层和位于所述栅极绝缘层之上的栅极；位于所述第二介质层、所述有源层和所述栅极叠层之上的层间绝缘层，其中，所述层间绝缘层包括暴露所述源/漏极区的过孔；位于所述层间绝缘层之上的经由所述过孔连接到所述源/漏极区的源/漏电极；以及位于所述层间绝缘层和所述源/漏电极之上的钝化层。
在本公开的实施例的第二方面中，提供一种制备薄膜晶体管的方法，包括：在衬底上形成遮光层和第一介质层；在所述遮光层和所述第一介质层上形成第二介质层以覆盖所述遮光层和所述第一介质层，其中，所述第一介质层的折射率大于所述第二介质层的折射率；以及在所述第二介质层上形成有源层。
在一个实施例中，在所述衬底上形成所述遮光层和所述第一介质层包括：在所述衬底上形成所述遮光层；以及在所述遮光层和所述衬底上形成所述第一介质层。
在一个实施例中，所述方法还包括在所述衬底上形成与所述遮光层同层且间隔设置的光阻挡部，所述第一介质层覆盖所述遮光层和所述光阻挡部。
在一个实施例中，所述光阻挡部的材料与所述遮光层的材料相同。
在一个实施例中，在所述衬底上形成所述遮光层和所述第一介质层包括：在所述衬底上形成所述第一介质层；以及在所述第一介质层上形成所述遮光层。
在一个实施例中，所述方法还包括：在所述有源层之上形成栅极叠层，其中，所述有源层包括位于所述栅极叠层之下的沟道区以及分别位于所述沟道区两侧的源/漏极区，所述栅极叠层包括栅极绝缘层和位于所述栅极绝缘层之上的栅极；形成层间绝缘层以覆盖所述第二介质层、所述有源层和所述栅极叠层；构图所述层间绝缘层以在所述层间绝缘层中同时形成暴露所述源/漏极区的过孔；在所述层间绝缘层上形成导电层以填充所述过孔；构图所述导电层以形成经由所述过孔连接到所述源/漏极区的源/漏电极；以及在所述层间绝缘层和所述源/漏电极上形成钝化层。
在本公开的实施例的第三方面中，提供一种包括在本公开的实施例的第一方面中描述的薄膜晶体管的显示面板。
在本公开的实施例的第四方面中，提供一种包括在本公开的实施例的第三方面中描述的显示面板的显示装置。
适应性的进一步的方面和范围从本文中提供的描述变得明显。应当理解，本申请的各个方面可以单独或者与一个或多个其他方面组合实施。还应当理解，本文中的描述和特定实施例旨在仅说明的目的并不旨在限制本申请的范围。
附图说明
本文中描述的附图用于仅对所选择的实施例的说明的目的，并不是所有可能的实施方式，并且不旨在限制本申请的范围，其中：
图1是根据本公开的实施例的薄膜晶体管的截面的示意图；
图2是根据本公开的实施例的薄膜晶体管的截面的示意图；
图3是根据本公开的实施例的光阻挡部的反射作用的示意图；
图4是根据本公开的实施例的薄膜晶体管的截面的示意图；
图5是根据本公开的实施例的制备薄膜晶体管的方法的流程图；
图6是根据本公开的实施例的薄膜晶体管的遮光层的形成示意图；
图7是根据本公开的实施例的薄膜晶体管的第一介质层的形成示意图；
图8是根据本公开的实施例的薄膜晶体管的第二介质层的形成示意图；
图9是根据本公开的实施例的薄膜晶体管的有源层的形成示意图；
图10是根据本公开的实施例的薄膜晶体管的栅极叠层的形成示意图；
图11是根据本公开的实施例的薄膜晶体管的层间绝缘层的形成示意图；
图12是根据本公开的实施例的薄膜晶体管的过孔的形成示意图；
图13是根据本公开的实施例的薄膜晶体管的源/漏电极的形成示意图；
图14是根据本公开的实施例的薄膜晶体管的钝化层的形成示意图；
图15是根据本公开的实施例的制备薄膜晶体管的方法的流程图；
图16是根据本公开的实施例的薄膜晶体管的遮光层和光阻挡部的形成示意图；
图17是根据本公开的实施例的薄膜晶体管的第一介质层的形成示意图；
图18是根据本公开的实施例的薄膜晶体管的第二介质层的形成示意图；
图19是根据本公开的实施例的制备薄膜晶体管的方法的流程图；
图20是根据本公开的实施例的薄膜晶体管的第一介质层的形成示意图；
图21是根据本公开的实施例的薄膜晶体管的遮光层的形成示意图；以及
图22是根据本公开的实施例的薄膜晶体管的第二介质层的形成示意 图。
贯穿这些附图的各个视图，相应的参考编号指示相应的部件或特征。
具体实施方式
首先，需要说明的是，除非上下文中另外明确地指出，否则在本文和所附权利要求中所使用的词语的单数形式包括复数，反之亦然。因而，当提及单数时，通常包括相应术语的复数。相似地，措辞“包含”和“包括”将解释为包含在内而不是独占性地。同样地，术语“包括”和“或”应当解释为包括在内的，除非本文中明确禁止这样的解释。在本文中使用术语“实例”之处，特别是当其位于一组术语之后时，所述“实例”仅仅是示例性的和阐述性的，且不应当被认为是独占性的或广泛性的。
此外，在附图中，为了清楚起见夸大了各层的厚度及区域。应当理解的是，当提到层、区域、或组件在别的部分“上”时，指其直接位于别的部分上，或者也可能有别的组件介于其间。相反，当某个组件被提到“直接”位于别的组件上时，指并无别的组件介于其间。
另外，还需要说明的是，当介绍本申请的元素及其实施例时，冠词“一”、“一个”、“该”和“所述”旨在表示存在一个或者多个要素；除非另有说明，“多个”的含义是两个或两个以上；用语“包含”、“包括”、“含有”和“具有”旨在包括性的并且表示可以存在除所列要素之外的另外的要素；术语“第一”、“第二”、“第三”等仅用于描述的目的，而不能理解为指示或暗示相对重要性及形成顺序。
现将参照附图更全面地描述示例性的实施例。
在诸如背光源的发光单元发出的光从薄膜晶体管的衬底侧照射薄膜晶体管时，入射到有源层的光会对有源层产生潜在的不利影响，由此会影响薄膜晶体管的光照稳定性。因此，一般会在有源层与衬底之间设置遮光层。该遮光层能够反射部分入射光，从而减少入射到有源层的光。然而，从遮光层两侧入射的光仍会入射到有源层，影响薄膜晶体管的光照稳定性。本 发明人经研究发现，当有源层为氧化物半导体时，从遮光层两侧入射的光的这种不利影响尤为显著。
在本文描述的实施例中，提供了一种薄膜晶体管。该薄膜晶体管中的缓冲层包括高折射率介质层和低折射率介质层，使得从遮光层两侧入射的光通过在高-低折射率介质层的界面处的反射而反射出衬底，或者上述光在遮光层的顶表面与高折射率介质层的顶表面之间横向传播。这样能够减少入射到有源层的光强，从而提高薄膜晶体管的光照稳定性。
图1是根据本公开的实施例的薄膜晶体管的截面的示意图。如图1所示，薄膜晶体管100包括：衬底1；位于衬底1之上的遮光层2；位于衬底1和遮光层2之上的第一介质层3；位于第一介质层3之上的第二介质层4；位于第二介质层4之上的有源层5；位于有源层5之上的栅极叠层67，其中，有源层5包括位于栅极叠层67之下的沟道区53以及分别位于沟道区53两侧的源/漏极区51、52，栅极叠层67包括栅极绝缘层6和位于栅极绝缘层6之上的栅极7；位于第二介质层4、栅极叠层67以及源/漏极区51、52之上的层间绝缘层8，其中，层间绝缘层8包括暴露源/漏极区51、52的过孔(图中未示出)；位于层间绝缘层8之上的源/漏电极层9，其中，源/漏电极层9包括经由过孔分别连接到源/漏极区51、52的源/漏电极91、92；以及位于层间绝缘层8和源/漏电极层9之上的钝化层10。
在一个示例性实施例中，第一介质层3的折射率大于第二介质层4的折射率。
在一个示例性实施例中，第一介质层3包括氮化硅，第二介质层4包括氧化硅，其中，第一介质层3的折射率为2.0，第二介质层4的折射率为1.4。可以理解，第一介质层3和第二介质层4的材料不限于上述材料，只要第一介质层3的折射率大于第二介质层4的折射率即可。
由于氧化硅致密度较高，因此能够减少氮化硅中的氢向有源层的扩散。
在一个示例性实施例中，第一介质层3的厚度为100nm至500nm，第二介质层4的厚度为5nm至1000nm。在一个示例性实施例中，第一介质 层3的厚度为100nm，第二介质层4的厚度为200nm。
在一个示例性实施例中，衬底1为玻璃。可以理解，衬底1可以为公知的其他材料，只要衬底1为透明的即可。
在一个示例性实施例中，遮光层2包括金属层。在一个示例性实施例中，遮光层2包括Mo、AlNd、Al、Cu等。在一个示例性实施例中，遮光层2的厚度为50nm至400nm。在一个示例性实施例中，遮光层2的厚度为100nm。
在一个示例性实施例中，有源层5包括半导体材料。应理解，本公开的实施例对半导体的材料没有特别的限制。在一个示例性实施例中，有源层5包括IGZO、ITZO等氧化物半导体材料。在一个示例性实施例中，有源层5的厚度为10nm至100nm。在一个示例性实施例中，有源层5的厚度为40nm。在一个示例性实施例中，栅极绝缘层6包括氧化硅。在一个示例性实施例中，栅极绝缘层6的厚度为100nm至500nm。在一个示例性实施例中，栅极绝缘层6的厚度为150nm。
在一个示例性实施例中，栅极7包括MoNb/Cu/MoNb复合金属膜层。可以理解，本公开的实施例的栅极也可以采用其他公知的复合金属膜层。在一个示例性实施例中，栅极7的厚度为200nm至1000nm。在一个示例性实施例中，栅极7的厚度为480nm。
在一个示例性实施例中，层间绝缘层8包括氧化硅。在一个示例性实施例中，层间绝缘层8的厚度为100nm至500nm。在一个示例性实施例中，层间绝缘层8的厚度为300nm。
在一个示例性实施例中，源/漏电极层9包括Mo、Al、Cu或其复合膜层等。在一个示例性实施例中，源/漏电极层9的厚度为50nm至1000nm。在一个示例性实施例中，源/漏电极层9的厚度为480nm。
在一个示例性实施例中，钝化层10包括氮化硅或氧化硅。在一个示例性实施例中，钝化层10的厚度为200nm至400nm。在一个示例性实施例中，钝化层10的厚度为300nm。
在该实施例中，缓冲层采用高折射率介质层和低折射率层介质层的组合。使得在发光单元发出的光从薄膜晶体管的衬底侧照射薄膜晶体管的情况下，光从高折射率介质层入射到低折射率介质层时，入射光通过光高折射率介质层与低折射率介质层的界面处的反射而射出衬底，或者上述入射光在遮光层的顶表面与高折射率层的顶表面之间横向传播。由此减少进入到薄膜晶体管的有源层的光强，从而提高薄膜晶体管的光照稳定性。
图2是根据本公开的实施例的薄膜晶体管的截面的示意图。如图2所示，图2与图1的区别在于：在图1的基础上，图2还包括位于衬底1之上的与遮光层2同层且间隔设置的位于遮光层2两侧的光阻挡部11。并且，图2中的第一介质层3覆盖遮光层2、光阻挡部11和衬底1。由此，使从遮光层2两侧入射的光经反射后从衬底侧射出薄膜晶体管200，以避免光在遮光层2的顶表面与第一介质层3的顶表面之间传播，从而更有效地减少进入到薄膜晶体管200的有源层5的光强。因此，更有效地提高薄膜晶体管的光照稳定性。此外，图2与图1相同的部分如在上文中所描述的，在此不再赘述。
在一个示例性实施例中，光阻挡部11的数量包括至少两个，该光阻挡部11设置在遮光层2的两侧，如图2所示。
在一个示例性实施例中，光阻挡部11的材料与遮光层2的材料相同。这样可以通过对同一材料层进行一次构图而同时形成光阻挡部11和遮光层2，从而可以简化制造步骤。
在图2中，光阻挡部11的截面形状为梯形形状，其中，该截面垂直于衬底1。在一个示例性实施例中，光阻挡部11的截面形状可以为三角形或圆形。
图3是根据本公开的实施例的光阻挡部的反射作用的示意图。在图3(a)中，入射光入射到位于第一介质层3覆盖光阻挡部11而形成的凸起外部且离该凸起较远的a位置时，入射光经a位置反射后没有入射到光阻挡部11的侧表面上，而是直接从衬底1射出。在图3(b)中，入射光入 射到该凸起外部且离该凸起较近的b位置时，入射光经b位置反射后入射到光阻挡部11的侧表面上，然后经光阻挡部11反射后射出衬底1。在图3(c)中，入射光入射到该凸起中的c位置时，入射光经c位置反射后入射到该凸起中与c位置对称的位置，然后经该对称的位置反射后直接射出衬底1。
通过光阻挡部11的设计，使从遮光层2两侧入射的光射出薄膜晶体管，还可以避免入射光进入遮光层2的顶表面与高折射率介质层3的顶表面之间而进行传播。从而更有效地减少进入到薄膜晶体管中的有源层的光强。因此，更有效地提高薄膜晶体管的光照稳定性。
图4是示出根据本公开的实施例的薄膜晶体管的截面的示意图。图4与图1的不同之处在于：图4中薄膜晶体管300的遮光层和第一介质层的位置与图1中薄膜晶体管100不同。在图4中，第一介质层3位于衬底1之上，遮光层2位于第一介质层3之上，第二介质层4覆盖第一介质层3和遮光层2。此外，图4与图1相同的部分如在上文中所描述的，在此不再赘述。
在该实施例中，在光照射薄膜晶体管的情况下，光首先入射到高折射率介质层，满足全反射条件的入射光到达高-低折射率介质层界面时被反射而射出薄膜晶体管，由此减少进入到薄膜晶体管的有源层的光强，从而提高薄膜晶体管的光照稳定性。
在本文描述的实施例中，还提供一种制备上述薄膜晶体管的方法。由于该薄膜晶体管包括高折射率介质层和低折射率层介质层，能够减少进入到有源层的光强，从而提高薄膜晶体管的光照稳定性。现将参照图5至图22详细地描述本公开的实施例提供的制备薄膜晶体管的方法。
图5是示出根据本公开的实施例的制备薄膜晶体管的方法的流程图。如图5所示，在步骤S101中，在衬底上形成遮光层。图6进一步示出了形成遮光层2的示意图。
如图6所示，在衬底1上形成图案化的遮光层2。
在一个示例性实施例中，形成遮光层2的方法包括溅射法或蒸镀法。
如图5所示，在步骤S102中，在遮光层和衬底之上形成第一介质层。图7进一步示出了形成第一介质层3的示意图。
如图7所示，形成第一介质层3以完全覆盖遮光层2和衬底1。
在一个示例性实施例中，形成第一介质层3的方法包括等离子体增强化学气相沉积法。
如图5所示，在步骤S103中，在第一介质层上形成第二介质层。图8进一步示出了形成第二介质层4的示意图。
如图8所示，在第一介质层3上形成第二介质层4。
在一个示例性实施例中，形成第二介质层4的方法包括等离子体增强化学气相沉积法。
如图5所示，在步骤S104中，在第二介质层上形成有源层。图9进一步示出了形成有源层5的示意图。
如图9所示，在第二介质层4上形成图案化的有源层5。
在一个示例性实施例中，形成有源层5的方法包括溅射法或蒸镀法。
如图5所示，在步骤S105中，在有源层上形成栅极叠层。图10进一步示出了形成栅极叠层67的示意图。
如图10所示，在有源层5上形成图案化的栅极叠层67，其中，有源层5包括位于栅极叠层67之下的沟道区53以及分别位于沟道区53两侧的源/漏极区51、52，栅极叠层67包括栅极绝缘层6和位于栅极绝缘层6之上的栅极7。
在一个示例性实施例中，形成栅极绝缘层6的方法包括等离子体增强化学气相沉积法；形成栅极7的方法包括溅射法或蒸镀法。
如图5所示，在步骤S106中，形成层间绝缘层以覆盖第二介质层、有源层和栅极叠层。图11进一步示出了形成层间绝缘层8的示意图。
如图11所示，形成层间绝缘层8以覆盖第二介质层4、有源层5和栅极叠层67。
在一个示例性实施例中，形成层间绝缘层8的方法包括等离子体增强化学气相沉积法。
如图5所示，在步骤S107中，构图层间绝缘层以在层间绝缘层中同时形成第一过孔和第二过孔。图12进一步示出了形成第一过孔81和第二过孔82的示意图。
如图12所示，构图层间绝缘层8以在层间绝缘层8中形成暴露源/漏极区51的第一过孔81和暴露源/漏极区52的第二过孔82。
在一个示例性实施例中，可以采用干法蚀刻形成第一过孔81和第二过孔82。
如图5所示，在步骤S108中，在层间绝缘层上形成填充第一和第二过孔的源/漏电极。图13进一步示出了形成源/漏电极91和源/漏电极92的示意图。
如图13所示，步骤S108还包括在层间绝缘层8上形成导电层，然后构图该导电层以在层间绝缘层8上形成经由第一过孔81连接到源/漏极区51的源/漏电极91和经由第二过孔82连接到源/漏极区52的源/漏电极92。
在一个示例性实施例中，形成导电层的方法包括溅射法。
如图5所示，在步骤S109中，在层间绝缘层和源/漏电极之上形成钝化层。图14进一步示出了形成钝化层10的示意图。
如图14所示，在层间绝缘层8以及源/漏电极91和源/漏电极92上形成钝化层10。
在一个示例性实施例中，形成钝化层10的方法包括等离子体增强化学气相沉积法。
图15是示出根据本公开的实施例的制备薄膜晶体管的方法的流程图，其中，由于在形成第二介质层之后的步骤与图5所示实施例相同，因此为了简明起见，未示出这些步骤。如图15所示，图15与图5的不同之处在于：图15中的步骤S101a还包括在衬底上形成光阻挡部；步骤S102a为形成第一介质层以覆盖遮光层、光阻挡部和衬底；以及步骤S103a为在第一 介质层上形成第二介质层。图16进一步示出了形成光阻挡部11的示意图。图17进一步示出了形成第一介质层3的示意图。图18进一步示出了形成第二介质层4的示意图。
如图16所示，在衬底1上形成图案化的遮光层2以及与遮光层2同层且间隔设置的光阻挡部11，其中，光阻挡部11位于遮光层2的两侧。
如图17所示，形成第一介质层3以覆盖遮光层2、光阻挡部11和衬底1。
如图18所示，在第一介质层3上形成第二介质层4，第二介质层4完全覆盖第一介质层3。
此外，图15与图5相同的步骤如上文所述，在此不再赘述。
图19是示出根据本公开的实施例的制备薄膜晶体管的方法的流程图，其中，由于在形成第二介质层之后的步骤与图5所示实施例相同，因此为了简明起见，未示出这些步骤。如图19所示，图19与图5的不同之处在于：图19中的步骤S101b为在衬底上形成第一介质层；步骤S102b为在第一介质层上形成遮光层；以及步骤S103b为形成第二介质层以覆盖第一介质层和遮光层。图20进一步示出了形成第一介质层3的示意图。图21进一步示出了形成遮光层2的示意图。图22进一步示出了形成第二介质层4的示意图。
如图20所示，在衬底1上形成第一介质层3。如图21所示，在第一介质层3上形成图案化的遮光层2。如图22所示，形成第二介质层4以覆盖第一介质层3和遮光层2。
此外，图19与图5相同的步骤如上文所述，在此不再赘述。
在本文描述的实施例中，薄膜晶体管中的缓冲层采用高折射率介质层和低折射率层介质层的组合。使得在发光单元发出的光从薄膜晶体管的衬底侧照射薄膜晶体管的情况下，光从高折射率介质层入射到低折射率介质层时，入射光通过高折射率介质层与低折射率介质层的界面处的反射而射出衬底，或者上述入射光在遮光层的顶表面与高折射率层的顶表面之间横 向传播。由此减少进入到薄膜晶体管的有源层的光强，从而提高薄膜晶体管的光照稳定性。此外，在薄膜晶体管的衬底上形成与遮光层同层设置并位于遮光层两侧的光反射部，能够避免光在遮光层的顶表面与高折射率介质层的顶表面之间传播，从而更有效地减少进入到薄膜晶体管中有源层的光强。因此，更有效地提高薄膜晶体管的光照稳定性。
本公开的实施例还提供一种显示面板，该显示面板包括上述薄膜晶体管，能够实现薄膜晶体管光照稳定性的提高。
本公开的实施例还提供一种显示装置，该显示装置包括上述显示面板，能够提高显示装置的显示效果。
以上为了说明和描述的目的提供了实施例的前述描述。其并不旨在是穷举的或者限制本申请。特定实施例的各个元件或特征通常不限于特定的实施例，但是，在合适的情况下，这些元件和特征是可互换的并且可用在所选择的实施例中，即使没有具体示出或描述。同样也可以以许多方式来改变。这种改变不能被认为脱离了本申请，并且所有这些修改都包含在本申请的范围内。

Claims (17)

  1. 一种薄膜晶体管，其中，包括：
    衬底；
    位于所述衬底之上的有源层；以及
    位于所述衬底与所述有源层之间的遮光层、第一介质层和第二介质层，其中，所述第一介质层位于所述第二介质层与所述衬底之间，所述第一介质层的折射率大于所述第二介质层的折射率。
  2. 根据权利要求1所述的薄膜晶体管，其中，所述遮光层位于所述衬底与所述第一介质层之间。
  3. 根据权利要求2所述的薄膜晶体管，其中，还包括位于所述衬底上的与所述遮光层同层且间隔设置的光阻挡部，其中，所述第一介质层覆盖所述遮光层和所述光阻挡部。
  4. 根据权利要求3所述的薄膜晶体管，其中所述光阻挡部的数量包括至少两个，所述光阻挡部设置在所述遮光层的两侧。
  5. 根据权利要求3所述的薄膜晶体管，其中，所述光阻挡部的材料与所述遮光层的材料相同。
  6. 根据权利要求5所述的薄膜晶体管，其中，所述光阻挡部的截面形状包括三角形、圆形或梯形。
  7. 根据权利要求1所述的薄膜晶体管，其中，所述遮光层位于所述第一介质层与所述第二介质层之间。
  8. 根据权利要求1所述的薄膜晶体管，其中，所述第一介质层包括氮化硅，所述第二介质层包括氧化硅。
  9. 根据权利要求1所述的薄膜晶体管，其中，还包括：位于所述有源层之上的栅极叠层，其中，所述有源层包括位于所述栅极叠层之下的沟道区以及分别位于所述沟道区两侧的源/漏极区，所述栅极叠层包括栅极绝缘层和位于所述栅极绝缘层之上的栅极；
    位于所述第二介质层、所述有源层和所述栅极叠层之上的层间绝缘层，其中，所述层间绝缘层包括暴露所述源/漏极区的过孔；
    位于所述层间绝缘层之上的经由所述过孔连接到所述源/漏极区的源/漏电极；以及
    位于所述层间绝缘层和所述源/漏电极之上的钝化层。
  10. 一种制备薄膜晶体管的方法，其中，包括：
    在衬底上形成遮光层和第一介质层；
    在所述遮光层和所述第一介质层上形成第二介质层以覆盖所述遮光层和所述第一介质层，其中，所述第一介质层的折射率大于所述第二介质层的折射率；以及
    在所述第二介质层上形成有源层。
  11. 根据权利要求10所述的方法，其中，在所述衬底上形成所述遮光层和所述第一介质层包括：在所述衬底上形成所述遮光层；以及在所述遮光层和所述衬底上形成所述第一介质层。
  12. 根据权利要求11所述的方法，其中，还包括在所述衬底上形成与所述遮光层同层且间隔设置的光阻挡部，所述第一介质层覆盖所述遮光层和所述光阻挡部。
  13. 根据权利要求12所述的薄膜晶体管，其中，所述光阻挡部的材料与所述遮光层的材料相同。
  14. 根据权利要求10所述的方法，其中，在所述衬底上形成所述遮光层和所述第一介质层包括：在所述衬底上形成所述第一介质层；以及在所述第一介质层上形成所述遮光层。
  15. 根据权利要求10所述的方法，其中，还包括：
    在所述有源层之上形成栅极叠层，其中，所述有源层包括位于所述栅极叠层之下的沟道区以及分别位于所述沟道区两侧的源/漏极区，所述栅极叠层包括栅极绝缘层和位于所述栅极绝缘层之上的栅极；
    形成层间绝缘层以覆盖所述第二介质层、所述有源层和所述栅极叠层；
    构图所述层间绝缘层以在所述层间绝缘层中同时形成暴露所述源/漏极区的过孔；
    在所述层间绝缘层上形成导电层以填充所述过孔；
    构图所述导电层以形成经由所述过孔连接到所述源/漏极区的源/漏电极；以及
    在所述层间绝缘层和所述源/漏电极上形成钝化层。
  16. 一种包括根据权利要求1至9中任一项所述的薄膜晶体管的显示面板。
  17. 一种包括根据权利要求16所述的显示面板的显示装置。
PCT/CN2017/116200 2017-05-12 2017-12-14 薄膜晶体管及其制备方法、显示面板和显示装置 Ceased WO2018205606A1 (zh)

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Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109817642B (zh) * 2019-01-22 2020-12-04 深圳市华星光电技术有限公司 薄膜晶体管阵列基板及其制造方法
CN110085678A (zh) * 2019-04-18 2019-08-02 深圳市华星光电半导体显示技术有限公司 显示面板和薄膜晶体管的制作方法
CN110909720B (zh) * 2019-12-18 2023-08-25 京东方科技集团股份有限公司 一种彩膜基板、显示面板及显示装置
CN212033021U (zh) * 2020-06-29 2020-11-27 京东方科技集团股份有限公司 Tft基板及显示装置
CN115988913B (zh) * 2022-11-29 2025-10-10 武汉天马微电子有限公司 一种显示面板和显示装置
CN115968230A (zh) * 2022-12-23 2023-04-14 京东方科技集团股份有限公司 显示面板及显示装置
CN117518548A (zh) * 2023-01-31 2024-02-06 武汉华星光电技术有限公司 液晶显示面板及其制作方法、显示装置
CN117529160A (zh) * 2023-03-31 2024-02-06 武汉华星光电技术有限公司 显示面板及显示装置
CN117075397A (zh) * 2023-06-09 2023-11-17 湖北长江新型显示产业创新中心有限公司 一种阵列基板、显示面板及显示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101093851A (zh) * 2006-06-22 2007-12-26 Lg.菲利浦Lcd株式会社 有机电致发光显示装置及其制造方法
CN102197485A (zh) * 2008-10-23 2011-09-21 夏普株式会社 半导体装置及其制造方法以及显示装置
CN103268878A (zh) * 2012-11-07 2013-08-28 厦门天马微电子有限公司 Tft阵列基板、tft阵列基板的制作方法及显示装置
US20140183476A1 (en) * 2012-12-27 2014-07-03 Lg Display Co. Ltd. Thin-film transistor, method for manufacturing the same and display device comprising the same
CN104218092A (zh) * 2014-08-13 2014-12-17 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法、阵列基板和显示装置

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000091584A (ja) 1998-09-08 2000-03-31 Matsushita Electric Ind Co Ltd 薄膜トランジスタ
JP3107075B2 (ja) * 1998-12-14 2000-11-06 日本電気株式会社 液晶表示装置
JP4481391B2 (ja) 1999-07-16 2010-06-16 東芝モバイルディスプレイ株式会社 液晶表示装置
JP3695308B2 (ja) 2000-10-27 2005-09-14 日本電気株式会社 アクティブマトリクス有機ｅｌ表示装置及びその製造方法
US6583440B2 (en) 2000-11-30 2003-06-24 Seiko Epson Corporation Soi substrate, element substrate, semiconductor device, electro-optical apparatus, electronic equipment, method of manufacturing the soi substrate, method of manufacturing the element substrate, and method of manufacturing the electro-optical apparatus
JP2003229573A (ja) 2002-01-31 2003-08-15 Sharp Corp 半導体装置およびその製造方法
JP2010027830A (ja) 2008-07-18 2010-02-04 Seiko Epson Corp 半導体膜の形成方法および電気光学装置の製造方法
JP2010074030A (ja) 2008-09-22 2010-04-02 Seiko Epson Corp 薄膜トランジスタおよび電気光学装置
JP5515287B2 (ja) 2008-12-22 2014-06-11 セイコーエプソン株式会社 表示装置、電子機器および表示装置の製造方法
WO2011065362A1 (ja) 2009-11-27 2011-06-03 シャープ株式会社 半導体装置およびその製造方法
CN102269900B (zh) 2010-06-03 2013-04-24 北京京东方光电科技有限公司 Tft阵列基板及其制造方法
KR101889748B1 (ko) 2011-01-10 2018-08-21 삼성디스플레이 주식회사 유기 발광 표시 장치 및 이의 제조 방법
KR101961427B1 (ko) 2012-10-29 2019-03-25 삼성디스플레이 주식회사 액정 표시 장치 및 이를 제조하는 방법
KR101975570B1 (ko) 2012-11-06 2019-08-26 삼성디스플레이 주식회사 박막 트랜지스터 표시판 및 그를 포함하는 유기 발광 표시 장치
KR102068089B1 (ko) * 2013-06-28 2020-01-20 엘지디스플레이 주식회사 산화물 반도체 박막 트랜지스터, 제조방법 및 이를 구비한 표시장치용 어레이 기판 및 제조방법
KR102062289B1 (ko) 2013-08-02 2020-01-06 삼성디스플레이 주식회사 와이드 그리드 편광자 및 이를 구비한 액정표시장치
CN104992948B (zh) * 2015-06-03 2018-07-06 京东方科技集团股份有限公司 一种薄膜晶体管、阵列基板及其制作方法
KR102373418B1 (ko) * 2015-08-31 2022-03-14 엘지디스플레이 주식회사 표시장치
KR102585124B1 (ko) * 2016-04-20 2023-10-05 삼성디스플레이 주식회사 표시 장치 및 그 제조 방법
CN106328586A (zh) * 2016-08-24 2017-01-11 武汉华星光电技术有限公司 低温多晶硅阵列基板的制备方法、阵列基板以及显示面板
CN106229338A (zh) * 2016-08-24 2016-12-14 深圳市华星光电技术有限公司 一种薄膜晶体管及其制备方法
JP6816417B2 (ja) * 2016-09-08 2021-01-20 セイコーエプソン株式会社 電気光学装置、電子機器

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101093851A (zh) * 2006-06-22 2007-12-26 Lg.菲利浦Lcd株式会社 有机电致发光显示装置及其制造方法
CN102197485A (zh) * 2008-10-23 2011-09-21 夏普株式会社 半导体装置及其制造方法以及显示装置
CN103268878A (zh) * 2012-11-07 2013-08-28 厦门天马微电子有限公司 Tft阵列基板、tft阵列基板的制作方法及显示装置
US20140183476A1 (en) * 2012-12-27 2014-07-03 Lg Display Co. Ltd. Thin-film transistor, method for manufacturing the same and display device comprising the same
CN104218092A (zh) * 2014-08-13 2014-12-17 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法、阵列基板和显示装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3627560A4 *

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