WO2018209751A1 - Tft基板的制作方法 - Google Patents

Tft基板的制作方法 Download PDF

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Publication number
WO2018209751A1
WO2018209751A1 PCT/CN2017/089247 CN2017089247W WO2018209751A1 WO 2018209751 A1 WO2018209751 A1 WO 2018209751A1 CN 2017089247 W CN2017089247 W CN 2017089247W WO 2018209751 A1 WO2018209751 A1 WO 2018209751A1
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Prior art keywords
layer
graphene
insulating layer
fabricating
metal foil
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French (fr)
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夏慧
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US15/570,369 priority Critical patent/US10153354B2/en
Priority to JP2019562541A priority patent/JP6857750B2/ja
Priority to KR1020197037105A priority patent/KR102190783B1/ko
Priority to EP17909921.3A priority patent/EP3627543B1/en
Publication of WO2018209751A1 publication Critical patent/WO2018209751A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6758—Thin-film transistors [TFT] characterised by the insulating substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/8303—Diamond
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/881—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being a two-dimensional material
    • H10D62/882—Graphene
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H10D64/0111—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
    • H10D64/0114—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors to diamond, semiconducting diamond-like carbon or graphene
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01364—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the semiconductor being diamond, semiconducting diamond-like carbon or graphene
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/411—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by materials, geometry or structure of the substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating a TFT substrate.
  • each pixel is driven by a Thin Film Transistor (TFT) integrated therein, thereby realizing a high-speed, high-brightness, high-contrast screen display effect.
  • TFT Thin Film Transistor
  • a common TFT is usually composed of a gate/source/drain three electrode, an insulating layer, and a semiconductor layer.
  • graphene as the world's thinnest and hardest nanomaterial, has become one of the current research hotspots because of its good electrical conductivity, mechanical properties and thermal conductivity. As a new material with extremely low conductivity, graphene has great potential for application in electronic components/transistors. According to reports, graphene films have extremely low sheet resistance ( ⁇ 100 ⁇ / ⁇ ), but after doping, broadband two-dimensional insulating materials can be formed, so that graphene can form n-type or p after certain treatment. The characteristics of semiconductors can be applied to TFT devices in the display industry. However, at present, for the large-area preparation of graphene, the most common technique for obtaining graphene is chemical vapor deposition (CVD).
  • CVD chemical vapor deposition
  • the process of fabricating TFT devices by this method is mainly on the metal substrate. For example, depositing graphene by CVD on copper/nickel, etching the metal substrate to obtain a graphene film, and transferring the graphene film to a substrate on which a desired film has been deposited by roll to roll or other means. Therefore, the TFT device is assembled, and the method has the disadvantages of a long cycle, a complicated process, and a high cost and a high cost of the metal substrate.
  • An object of the present invention is to provide a method for fabricating a TFT substrate, which can reduce production cost, simplify the process, and reduce the mask process.
  • a method for fabricating a TFT substrate of the present invention includes the following steps:
  • Step S1 providing a metal foil, depositing a graphene film on the metal foil, and obtaining a graphene semiconductor active layer by changing a graphene band gap;
  • Step S2 depositing an inorganic insulating layer on the graphene semiconductor active layer
  • Step S3 forming an organic substrate on the inorganic insulating layer to obtain a primary structure
  • Step S4 the primary structure obtained in the step S3 is turned upside down, so that the organic substrate is located at the lowermost layer, so that the metal foil is located at the uppermost layer, and a photoresist layer is formed on the metal foil by a patterning process by a reticle;
  • Step S5 using the photoresist layer as a shielding layer, etching the metal foil to obtain spaced source and drain electrodes;
  • Step S6 forming an organic insulating layer on the photoresist layer and the graphene semiconductor active layer, and depositing a gate conductive layer on the organic insulating layer;
  • Step S7 removing the photoresist layer by the photoresist stripping solution, and simultaneously removing the organic insulating layer and the gate conductive layer on the photoresist layer through the photoresist layer, and obtaining the remaining organic insulating layer on the active layer of the graphene semiconductor and A gate insulating layer between the source and the drain, and a gate on the gate insulating layer is obtained from the remaining gate conductive layer.
  • the material of the metal foil is copper or nickel.
  • the method for changing the band gap of the graphene is a chemical doping method, specifically, chemically doping the graphene film while depositing, and the deposited graphene film is doped graphene. a thin film to obtain a graphene semiconductor active layer; or
  • the method for changing the band gap of the graphene is photolithography. Specifically, after depositing the graphene film, the graphene film is cut into a thin strip shape to become a graphene nanoribbon, thereby obtaining a graphene semiconductor active layer.
  • the graphene film is deposited by plasma enhanced chemical vapor deposition, and the deposited graphene film is a single-layer graphene film; the graphene semiconductor active layer has a band gap value greater than 0.1 eV.
  • an inorganic insulating layer is formed by chemical vapor deposition, and the material of the inorganic insulating layer is silicon nitride, silicon oxide, antimony trioxide or hafnium oxide.
  • the organic substrate is formed by solution coating and curing, and the material of the organic substrate is polydimethylsiloxane.
  • the metal foil is etched by a wet etching process.
  • an organic insulating layer is formed by a coating process, and the material of the organic insulating layer is polymethyl methacrylate.
  • a gate conductive layer is formed by physical vapor deposition, and the material of the gate conductive layer is aluminum, copper, or indium tin oxide.
  • the method for fabricating the TFT substrate further includes a step S8, providing a reinforcing substrate, and melting the organic substrate to be attached to the reinforcing substrate;
  • the reinforcing substrate is glass, polyethylene terephthalate plastic, or silicon wafer.
  • the invention also provides a method for fabricating a TFT substrate, comprising the following steps:
  • Step S1 providing a metal foil, depositing a graphene film on the metal foil, and obtaining a graphene semiconductor active layer by changing a graphene band gap;
  • Step S2 depositing an inorganic insulating layer on the graphene semiconductor active layer
  • Step S3 forming an organic substrate on the inorganic insulating layer to obtain a primary structure
  • Step S4 the primary structure obtained in the step S3 is turned upside down, so that the organic substrate is located at the lowermost layer, so that the metal foil is located at the uppermost layer, and a photoresist layer is formed on the metal foil by a patterning process by a reticle;
  • Step S5 using the photoresist layer as a shielding layer, etching the metal foil to obtain spaced source and drain electrodes;
  • Step S6 forming an organic insulating layer on the photoresist layer and the graphene semiconductor active layer, and depositing a gate conductive layer on the organic insulating layer;
  • Step S7 removing the photoresist layer by the photoresist stripping solution, and simultaneously removing the organic insulating layer and the gate conductive layer on the photoresist layer through the photoresist layer, and obtaining the remaining organic insulating layer on the active layer of the graphene semiconductor and a gate insulating layer between the source and the drain, and a gate on the gate insulating layer is obtained by the remaining gate conductive layer;
  • an inorganic insulating layer is formed by chemical vapor deposition, and the material of the inorganic insulating layer is silicon nitride, silicon oxide, antimony trioxide or germanium dioxide;
  • the organic substrate is formed by solution coating and curing, and the material of the organic substrate is polydimethylsiloxane.
  • the present invention provides a method for fabricating a TFT substrate by first depositing a graphene film on a metal foil, and obtaining a graphene semiconductor active layer by changing a graphene band gap, and then having a graphene semiconductor layer
  • An inorganic insulating layer and an organic substrate are sequentially formed on the source layer, and the metal foil is placed on the uppermost layer by flipping up and down, and a photoresist layer is formed on the metal foil by a patterning process, wherein the photoresist layer is Masking layer, etching the metal foil to obtain a source and a drain, and then sequentially forming an organic insulating layer and a gate conductive layer on the photoresist layer and the graphene semiconductor active layer, and finally passing through the photoresist
  • the stripping liquid removes the photoresist layer and is separated from the organic insulating layer and the gate conductive layer thereon by the photoresist layer, thereby obtaining a patterned gate insulating layer and
  • FIG. 1 is a schematic flow chart of a method for fabricating a TFT substrate of the present invention
  • FIG. 2 is a schematic view showing a step S1 of a method for fabricating a TFT substrate according to the present invention
  • FIG. 3 is a schematic view showing a step S2 of a method for fabricating a TFT substrate according to the present invention
  • FIG. 4 is a schematic view showing a step S3 of a method for fabricating a TFT substrate according to the present invention
  • FIG. 5 is a schematic view showing a step S4 of a method for fabricating a TFT substrate according to the present invention
  • FIG. 6 is a schematic view showing a step S5 of a method for fabricating a TFT substrate according to the present invention.
  • FIG. 7 is a schematic view showing a step S6 of a method for fabricating a TFT substrate according to the present invention.
  • FIG. 8 is a schematic view showing a step S7 of a method for fabricating a TFT substrate according to the present invention.
  • FIG. 9 is a schematic view showing a step S8 of the method for fabricating the TFT substrate of the present invention.
  • the present invention provides a method for fabricating a TFT substrate, including the following steps:
  • Step S1 as shown in Fig. 2, a metal foil 100' is provided, a graphene film is deposited on the metal foil 100', and a graphene semiconductor active layer 200 is obtained by changing the band gap of the graphene.
  • the material of the metal foil 100' can be used as a base material for depositing a graphene film, and also has a conductive property, which can be subsequently used as an electrode material, such as copper (Cu), or nickel.
  • Metal material such as (Ni).
  • the method for changing the band gap of the graphene is a chemical doping method, specifically, chemically doping the graphene film while depositing, and the deposited graphene film is doped. a graphene film to obtain a graphene semiconductor active layer 200; or
  • the method for changing the band gap of the graphene is photolithography. Specifically, after depositing the graphene film, the graphene film is cut into a thin strip to form a graphene nanoribbon (GNR), thereby obtaining a graphene semiconductor active. Layer 200.
  • GNR graphene nanoribbon
  • the formed graphene semiconductor active layer 200 has a band gap value greater than 0.1 eV.
  • the graphene film is deposited by plasma enhanced chemical vapor deposition (Plasma)
  • the graphene film is deposited by Enhanced Chemical Vapor Deposition (PECVD), and the deposited graphene film is preferably a single-layer graphene film having a thickness of preferably less than 5 nm.
  • Step S2 depositing an inorganic insulating layer 300 on the graphene semiconductor active layer 200, thereby providing a certain insulation protection effect on the graphene semiconductor active layer 200 to prevent subsequent formation of organic
  • the substrate has an effect on the graphene semiconductor active layer 200.
  • the inorganic insulating layer 300 is formed by chemical vapor deposition (CVD) deposition, and the material of the inorganic insulating layer 300 may be silicon nitride (SiNx) or silicon oxide (Inorganic materials such as SiO 2 ), antimony trioxide, and hafnium dioxide (HfO 2 ).
  • CVD chemical vapor deposition
  • Step S3 as shown in FIG. 4, an organic substrate 400 is formed on the inorganic insulating layer 300 to obtain a primary structure.
  • the organic substrate 400 is formed by solution coating and curing, and the material of the organic substrate 400 may be polydimethylsiloxane (PDMS).
  • PDMS polydimethylsiloxane
  • Step S4 as shown in FIG. 5, the primary structure obtained in the step S3 is turned upside down, so that the organic substrate 400 is located at the lowermost layer, so that the metal foil 100' is located at the uppermost layer, and a metal foil 100' is utilized.
  • the photomask is patterned to form a photoresist (PR) layer 500.
  • the patterning process specifically includes a coating step, an exposure step, and a development step which are sequentially performed.
  • step S5 as shown in Fig. 6, the photoresist layer 500 is used as a shielding layer, and the metal foil 100' is etched to obtain a source 110 and a drain 120 which are spaced apart.
  • the metal foil 100' is etched by a wet etching process.
  • Step S6 as shown in FIG. 7, an organic insulating layer 600' is formed on the photoresist layer 500 and the graphene semiconductor active layer 200, and a gate conductive layer 700' is deposited on the organic insulating layer 600'.
  • the organic insulating layer 600' is formed by a coating process, the organic insulating layer 600' can be formed on the photoresist layer 500 at a low temperature, and the dielectric of the organic insulating layer 600' The coefficient needs to reach 3 times the vacuum permittivity, for example, the material may be polymethyl methacrylate (PMMA).
  • PMMA polymethyl methacrylate
  • the gate conductive layer 700' is formed by physical Vapor Deposition (PVD) deposition, and the material of the gate conductive layer 700' is a metal or oxide having a conductive function.
  • PVD physical Vapor Deposition
  • the material of the gate conductive layer 700' is a metal or oxide having a conductive function.
  • Al aluminum
  • copper copper
  • ITO indium tin oxide
  • Step S7 the photoresist layer 500 is removed by the photoresist stripping liquid while being carried away from the organic insulating layer 600' and the gate conductive layer 700' on the photoresist layer 500 through the photoresist layer 500.
  • the organic insulating layer 600' obtains a gate insulating layer 600 on the graphene semiconductor active layer 200 between the source 110 and the drain 120, which is obtained by the remaining gate conductive layer 700'. Gate 700 on layer 600.
  • the TFT substrate obtained by the invention can be used as the outermost substrate to support the TFT device, so the material needs to be resistant to acid, alkali and water, for example, can be prepared by PDMS or other solution coating methods. Base material.
  • the method for fabricating the TFT substrate of the present invention may further include the step S8. As shown in FIG. 9, the reinforcing substrate 800 is provided, and the organic substrate 400 is melted and then attached to the reinforcing substrate 800.
  • the reinforcing substrate 800 may be glass, polyethylene terephthalate (PET) plastic, silicon wafer, or the like.
  • the metal foil 100' for depositing a graphene film is reused as an electrode material for forming the source and drain electrodes 110 and 120 by upside down, thereby achieving cost reduction and simplification of the process. And through the stripping process, only a mask can be used to obtain the patterned source 110, drain 120 and gate 700.
  • the method for fabricating a TFT substrate first deposits a graphene film on a metal foil, obtains a graphene semiconductor active layer by changing a graphene band gap, and then activates the graphene semiconductor.
  • An inorganic insulating layer and an organic substrate are sequentially formed on the layer, and the metal foil is placed on the uppermost layer by flipping up and down, and a photoresist layer is formed on the metal foil by a patterning process, and the photoresist layer is shielded a layer, etching the metal foil to obtain a source and a drain, and then sequentially forming an organic insulating layer and a gate conductive layer on the photoresist layer and the graphene semiconductor active layer, and finally stripping through the photoresist
  • the liquid removes the photoresist layer and is separated from the organic insulating layer and the gate conductive layer thereon by the photoresist layer, thereby obtaining a patterned gate insulating layer and a gate; the manufacturing method is

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Abstract

一种TFT基板的制作方法，在金属箔片（100'）上依次形成石墨烯半导体有源层（200）、无机物绝缘层（300）和有机基底（400），上下翻转后，在最上面的金属箔片上经图案化形成光阻层（500），对金属箔片进行蚀刻，得到源极（110）和漏极（120），然后在光阻层及石墨烯半导体有源层上依次形成有机绝缘层（600'）和栅极导电层（700'），最后通过光阻剥离液去除光阻层并带离其上的有机绝缘层和栅极导电层，得到图形化的栅极绝缘层（600）和栅极（700）。该制作方法将用于沉积石墨烯薄膜的金属箔片再次利用为制作源漏极的电极材料，降低了成本和简化了工艺；并通过剥离工艺，只需一道光罩得到图形化源极、漏极和栅极。

Description

TFT基板的制作方法 技术领域
本发明涉及显示技术领域，尤其涉及一种TFT基板的制作方法。
背景技术
在有源矩阵显示技术中，每一个像素点都由集成在其后的薄膜晶体管(Thin Film Transistor，TFT)进行驱动，从而可以实现高速度、高亮度、高对比度的屏幕显示效果。常见的TFT通常由栅极/源极/漏极(Gate/Source/Drain)三电极、绝缘层以及半导体层构成。
石墨烯，作为目前已知世界上最薄、最坚硬的纳米材料，因其具有良好的导电调控性，机械特性，导热特性，从而成为当前研究热点之一。石墨烯作为一种极薄导电率极高的新型材料，具有很大潜能被应用到电子元件/晶体管中。根据报道，石墨烯薄膜具有极低的方块电阻(<100Ω/□)，然而经过掺杂之后，又可以形成宽带系的二维绝缘材料，因而石墨烯经过一定处理后，可形成n型或p型半导体的特性，可被应用到显示行业的TFT器件中。然而目前对于大面积制备石墨烯，较常用且得到的石墨烯性能较好的技术主要为化学气相沉积法(Chemical Vapor Deposition，CVD)，利用该方法制作TFT器件的过程主要为，首先在金属基底如铜/镍上通过CVD法沉积石墨烯，再蚀刻掉金属基底得到石墨烯薄膜，再将该石墨烯薄膜通过卷对卷(Roll to Roll)或其他方式转移至已沉积所需薄膜的基底上，从而组装成TFT器件，该方法具有周期长，工艺复杂，且金属基底耗费大成本高的等缺点。
故，对于含石墨烯的TFT基板，开发一种工艺简单且成本低的制备方法具有重要意义。
发明内容
本发明的目的在于提供一种TFT基板的制作方法，能够降低生产成本、简化工艺、减少光罩制程。
为实现上述目的，本发明一种TFT基板的制作方法，包括以下步骤：
步骤S1、提供金属箔片，在所述金属箔片上沉积石墨烯薄膜，通过改变石墨烯带隙的方法得到石墨烯半导体有源层；
步骤S2、在所述石墨烯半导体有源层上沉积形成无机物绝缘层；
步骤S3、在所述无机物绝缘层上形成有机基底，得到初级结构；
步骤S4、将所述步骤S3得到的初级结构上下翻转，使有机基底位于最下层，使金属箔片位于最上层，在所述金属箔片上利用一道光罩经图案化工艺形成光阻层；
步骤S5、以所述光阻层为遮蔽层，对所述金属箔片进行蚀刻，得到间隔的源极和漏极；
步骤S6、在所述光阻层及石墨烯半导体有源层上形成有机绝缘层，在所述有机绝缘层上沉积形成栅极导电层；
步骤S7、通过光阻剥离液去除光阻层，同时通过光阻层带离光阻层上的有机绝缘层和栅极导电层，由剩余的有机绝缘层得到位于石墨烯半导体有源层上且位于源极与漏极之间的栅极绝缘层，由剩余的栅极导电层得到位于所述栅极绝缘层上的栅极。
所述金属箔片的材料为铜、或镍。
所述步骤S1中，所述改变石墨烯带隙的方法为化学掺杂法，具体为，在沉积石墨烯薄膜的同时对其进行化学掺杂，所沉积的石墨烯薄膜为掺杂的石墨烯薄膜，从而得到石墨烯半导体有源层；或者，
所述改变石墨烯带隙的方法为光刻法，具体为，在沉积石墨烯薄膜后，将石墨烯薄膜切割成细带状，成为石墨烯纳米带，从而得到石墨烯半导体有源层。
所述步骤S1中，通过等离子增强化学气相沉积法沉积所述石墨烯薄膜，所沉积的石墨烯薄膜为单层石墨烯薄膜；所述石墨烯半导体有源层的带隙值大于0.1eV。
所述步骤S2中，通过化学气相沉积法沉积形成无机物绝缘层，所述无机物绝缘层的材料为氮化硅、氧化硅、三氧化二钇、或二氧化铪。
所述步骤S3中，所述有机基底通过溶液涂布及固化形成，所述有机基底的材料为聚二甲基硅氧烷。
所述步骤S5中，通过湿蚀刻工艺对对所述金属箔片进行蚀刻。
所述步骤S6中，通过涂布工艺形成有机绝缘层，所述有机绝缘层的材料为聚甲基丙烯酸甲酯。
所述步骤S6中，通过物理气相沉积法沉积形成栅极导电层，所述栅极导电层的材料为铝、铜、或氧化铟锡。
所述的TFT基板的制作方法，还包括步骤S8、提供加强基底，使有机基底融化后再贴附到加强基底上；
所述加强基底为玻璃、聚对苯二甲酸乙二酯塑料、或硅片。
本发明还提供一种TFT基板的制作方法，包括以下步骤：
步骤S1、提供金属箔片，在所述金属箔片上沉积石墨烯薄膜，通过改变石墨烯带隙的方法得到石墨烯半导体有源层；
步骤S2、在所述石墨烯半导体有源层上沉积形成无机物绝缘层；
步骤S3、在所述无机物绝缘层上形成有机基底，得到初级结构；
步骤S4、将所述步骤S3得到的初级结构上下翻转，使有机基底位于最下层，使金属箔片位于最上层，在所述金属箔片上利用一道光罩经图案化工艺形成光阻层；
步骤S5、以所述光阻层为遮蔽层，对所述金属箔片进行蚀刻，得到间隔的源极和漏极；
步骤S6、在所述光阻层及石墨烯半导体有源层上形成有机绝缘层，在所述有机绝缘层上沉积形成栅极导电层；
步骤S7、通过光阻剥离液去除光阻层，同时通过光阻层带离光阻层上的有机绝缘层和栅极导电层，由剩余的有机绝缘层得到位于石墨烯半导体有源层上且位于源极和漏极之间的栅极绝缘层，由剩余的栅极导电层得到位于所述栅极绝缘层上的栅极；
其中，所述步骤S2中，通过化学气相沉积法沉积形成无机物绝缘层，所述无机物绝缘层的材料为氮化硅、氧化硅、三氧化二钇、或二氧化铪；
其中，所述步骤S3中，所述有机基底通过溶液涂布及固化形成，所述有机基底的材料为聚二甲基硅氧烷。
本发明的有益效果：本发明提供的一种TFT基板的制作方法，首先在金属箔片上沉积石墨烯薄膜，通过改变石墨烯带隙的方法得到石墨烯半导体有源层，然后在石墨烯半导体有源层上依次形成无机物绝缘层和有机基底，通过上下翻转，使所述金属箔片位于最上层，再在所述金属箔片上经图案化工艺形成光阻层，以所述光阻层为遮蔽层，对所述金属箔片进行蚀刻，得到源极和漏极，再然后在所述光阻层及石墨烯半导体有源层上依次形成有机绝缘层和栅极导电层，最后通过光阻剥离液去除光阻层，并通过光阻层带离其上的有机绝缘层和栅极导电层，从而得到图形化的栅极绝缘层和栅极；该制作方法通过上下翻转的方式，将用于沉积石墨烯薄膜的金属箔片再次利用为制作源漏极的电极材料，从而达到降低成本和简化工艺的作用，并通过剥离(lift-off)工艺，只需一道光罩便可得到图形化的源极、漏极和栅极。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发 明加以限制。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为本发明TFT基板的制作方法的流程示意图；
图2为本发明TFT基板的制作方法步骤S1的示意图；
图3为本发明TFT基板的制作方法步骤S2的示意图；
图4为本发明TFT基板的制作方法步骤S3的示意图；
图5为本发明TFT基板的制作方法步骤S4的示意图；
图6为本发明TFT基板的制作方法步骤S5的示意图；
图7为本发明TFT基板的制作方法步骤S6的示意图；
图8为本发明TFT基板的制作方法步骤S7的示意图；
图9为本发明TFT基板的制作方法步骤S8的示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图1，本发明提供一种TFT基板的制作方法，包括以下步骤：
步骤S1、如图2所示，提供金属箔片100’，在所述金属箔片100’上沉积石墨烯薄膜，通过改变石墨烯带隙的方法得到石墨烯半导体有源层200。
具体地，本发明中，所述金属箔片100’的材料既可作为基底材料用于沉积制备石墨烯薄膜，同时也需具备导电性质后续可用作电极材料，例如铜(Cu)、或镍(Ni)等金属材料。
具体地，所述步骤S1中，所述改变石墨烯带隙的方法为化学掺杂法，具体为，在沉积石墨烯薄膜的同时对其进行化学掺杂，所沉积的石墨烯薄膜为掺杂的石墨烯薄膜，从而得到石墨烯半导体有源层200；或者，
所述改变石墨烯带隙的方法为光刻法，具体为，在沉积石墨烯薄膜后，将石墨烯薄膜切割成细带状，成为石墨烯纳米带(GNR)，从而得到石墨烯半导体有源层200。
具体地，所述步骤S1中，所形成的石墨烯半导体有源层200的带隙值大于0.1eV。
具体地，所述步骤S1中，通过等离子增强化学气相沉积法(Plasma  Enhanced Chemical Vapor Deposition，PECVD)沉积所述石墨烯薄膜，所沉积的石墨烯薄膜优选为单层石墨烯薄膜，其厚度优选为小于5nm。
步骤S2、如图3所示，在所述石墨烯半导体有源层200上沉积形成无机物绝缘层300，从而对石墨烯半导体有源层200起到一定的绝缘保护作用，阻止后续形成的有机基底对石墨烯半导体有源层200产生影响。
具体地，所述步骤S2中，通过化学气相沉积法(Chemical Vapor Deposition，CVD)沉积形成无机物绝缘层300，所述无机物绝缘层300的材料可以为氮化硅(SiNx)、氧化硅(SiO2)、三氧化二钇、二氧化铪(HfO2)等无机材料。
步骤S3、如图4所示，在所述无机物绝缘层300上形成有机基底400，得到初级结构。
具体地，所述步骤S3中，所述有机基底400通过溶液涂布及固化形成，所述有机基底400的材料可为聚二甲基硅氧烷(PDMS)。
步骤S4、如图5所示，将所述步骤S3得到的初级结构上下翻转，使有机基底400位于最下层，使金属箔片100’位于最上层，在所述金属箔片100’上利用一道光罩经图案化工艺形成光阻(PR)层500。
具体地，所述步骤S4中，所述图案化工艺具体包括依次进行的涂布步骤、曝光步骤、及显影步骤。
步骤S5、如图6所示，以所述光阻层500为遮蔽层，对所述金属箔片100’进行蚀刻，得到间隔的源极110和漏极120。
具体地，所述步骤S5中，通过湿蚀刻工艺对对所述金属箔片100’进行蚀刻。
步骤S6、如图7所示，在所述光阻层500及石墨烯半导体有源层200上形成有机绝缘层600’，在所述有机绝缘层600’上沉积形成栅极导电层700’。
具体地，所述步骤S6中，通过涂布工艺形成有机绝缘层600’，所述有机绝缘层600’可低温在所述光阻层500上形成，且所述有机绝缘层600’的介电系数需达到3倍真空介电常数，例如其材料可为聚甲基丙烯酸甲酯(PMMA)。
具体地，所述步骤S6中，通过物理气相沉积法(Physical Vapor Deposition，PVD)沉积形成栅极导电层700’，所述栅极导电层700’的材料为具备导电作用的金属或氧化物，例如铝(Al)、铜、氧化铟锡(ITO)等。
步骤S7、如图8所示，通过光阻剥离液去除光阻层500，同时通过光阻层500带离光阻层500上的有机绝缘层600’和栅极导电层700’，由剩余 的有机绝缘层600’得到位于石墨烯半导体有源层200上且位于源极110及漏极120之间的栅极绝缘层600，由剩余的栅极导电层700’得到位于所述栅极绝缘层600上的栅极700。
本发明所得到TFT基板，所述有机基底400可以作为最外侧的基底，对TFT器件起到支撑作用，因此其材料需能够耐酸耐碱耐水，例如可选用PDMS或其他可用溶液涂布法制备的基底材料。另外，本发明的TFT基板的制作方法，还可包括步骤S8、如图9所示，提供加强基底800，使有机基底400融化后再贴附到加强基底800上。
具体地，所述加强基底800可以为玻璃、聚对苯二甲酸乙二酯(PET)塑料、硅片等。
上述TFT基板的制作方法，通过上下翻转的方式，将用于沉积石墨烯薄膜的金属箔片100’再次利用为制作源漏极110、120的电极材料，从而达到降低成本和简化工艺的作用，并通过剥离工艺，只需一道光罩便可得到图形化的源极110、漏极120和栅极700。
综上所述，本发明提供的一种TFT基板的制作方法，首先在金属箔片上沉积石墨烯薄膜，通过改变石墨烯带隙的方法得到石墨烯半导体有源层，然后在石墨烯半导体有源层上依次形成无机物绝缘层和有机基底，通过上下翻转，使所述金属箔片位于最上层，再在所述金属箔片上经图案化工艺形成光阻层，以所述光阻层为遮蔽层，对所述金属箔片进行蚀刻，得到源极和漏极，再然后在所述光阻层及石墨烯半导体有源层上依次形成有机绝缘层和栅极导电层，最后通过光阻剥离液去除光阻层，并通过光阻层带离其上的有机绝缘层和栅极导电层，从而得到图形化的栅极绝缘层和栅极；该制作方法通过上下翻转的方式，将用于沉积石墨烯薄膜的金属箔片再次利用为制作源漏极的电极材料，从而达到降低成本和简化工艺的作用，并通过剥离工艺，只需一道光罩便可得到图形化的源极、漏极和栅极。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (18)

  1. 一种TFT基板的制作方法，包括以下步骤：
    步骤S1、提供金属箔片，在所述金属箔片上沉积石墨烯薄膜，通过改变石墨烯带隙的方法得到石墨烯半导体有源层；
    步骤S2、在所述石墨烯半导体有源层上沉积形成无机物绝缘层；
    步骤S3、在所述无机物绝缘层上形成有机基底，得到初级结构；
    步骤S4、将所述步骤S3得到的初级结构上下翻转，使有机基底位于最下层，使金属箔片位于最上层，在所述金属箔片上利用一道光罩经图案化工艺形成光阻层；
    步骤S5、以所述光阻层为遮蔽层，对所述金属箔片进行蚀刻，得到间隔的源极和漏极；
    步骤S6、在所述光阻层及石墨烯半导体有源层上形成有机绝缘层，在所述有机绝缘层上沉积形成栅极导电层；
    步骤S7、通过光阻剥离液去除光阻层，同时通过光阻层带离光阻层上的有机绝缘层和栅极导电层，由剩余的有机绝缘层得到位于石墨烯半导体有源层上且位于源极和漏极之间的栅极绝缘层，由剩余的栅极导电层得到位于所述栅极绝缘层上的栅极。
  2. 如权利要求1所述的TFT基板的制作方法，其中，所述金属箔片的材料为铜、或镍。
  3. 如权利要求1所述的TFT基板的制作方法，其中，所述步骤S1中，所述改变石墨烯带隙的方法为化学掺杂法，具体为，在沉积石墨烯薄膜的同时对其进行化学掺杂，所沉积的石墨烯薄膜为掺杂的石墨烯薄膜，从而得到石墨烯半导体有源层；或者，
    所述改变石墨烯带隙的方法为光刻法，具体为，在沉积石墨烯薄膜后，将石墨烯薄膜切割成细带状，成为石墨烯纳米带，从而得到石墨烯半导体有源层。
  4. 如权利要求1所述的TFT基板的制作方法，其中，所述步骤S1中，通过等离子增强化学气相沉积法沉积所述石墨烯薄膜，所沉积的石墨烯薄膜为单层石墨烯薄膜；所述石墨烯半导体有源层的带隙值大于0.1eV。
  5. 如权利要求1所述的TFT基板的制作方法，其中，所述步骤S2中，通过化学气相沉积法沉积形成无机物绝缘层，所述无机物绝缘层的材料为氮化硅、氧化硅、三氧化二钇、或二氧化铪。
  6. 如权利要求1所述的TFT基板的制作方法，其中，所述步骤S3中，所述有机基底通过溶液涂布及固化形成，所述有机基底的材料为聚二甲基硅氧烷。
  7. 如权利要求1所述的TFT基板的制作方法，其中，所述步骤S5中，通过湿蚀刻工艺对对所述金属箔片进行蚀刻。
  8. 如权利要求1所述的TFT基板的制作方法，其中，所述步骤S6中，通过涂布工艺形成有机绝缘层，所述有机绝缘层的材料为聚甲基丙烯酸甲酯。
  9. 如权利要求1所述的TFT基板的制作方法，其中，所述步骤S6中，通过物理气相沉积法沉积形成栅极导电层，所述栅极导电层的材料为铝、铜、或氧化铟锡。
  10. 如权利要求1所述的TFT基板的制作方法，还包括步骤S8、提供加强基底，使有机基底融化后再贴附到加强基底上；
    所述加强基底为玻璃、聚对苯二甲酸乙二酯塑料、或硅片。
  11. 一种TFT基板的制作方法，包括以下步骤：
    步骤S1、提供金属箔片，在所述金属箔片上沉积石墨烯薄膜，通过改变石墨烯带隙的方法得到石墨烯半导体有源层；
    步骤S2、在所述石墨烯半导体有源层上沉积形成无机物绝缘层；
    步骤S3、在所述无机物绝缘层上形成有机基底，得到初级结构；
    步骤S4、将所述步骤S3得到的初级结构上下翻转，使有机基底位于最下层，使金属箔片位于最上层，在所述金属箔片上利用一道光罩经图案化工艺形成光阻层；
    步骤S5、以所述光阻层为遮蔽层，对所述金属箔片进行蚀刻，得到间隔的源极和漏极；
    步骤S6、在所述光阻层及石墨烯半导体有源层上形成有机绝缘层，在所述有机绝缘层上沉积形成栅极导电层；
    步骤S7、通过光阻剥离液去除光阻层，同时通过光阻层带离光阻层上的有机绝缘层和栅极导电层，由剩余的有机绝缘层得到位于石墨烯半导体有源层上且位于源极和漏极之间的栅极绝缘层，由剩余的栅极导电层得到位于所述栅极绝缘层上的栅极；
    其中，所述步骤S2中，通过化学气相沉积法沉积形成无机物绝缘层，所述无机物绝缘层的材料为氮化硅、氧化硅、三氧化二钇、或二氧化铪；
    其中，所述步骤S3中，所述有机基底通过溶液涂布及固化形成，所述有机基底的材料为聚二甲基硅氧烷。
  12. 如权利要求11所述的TFT基板的制作方法，其中，所述金属箔片的材料为铜、或镍。
  13. 如权利要求11所述的TFT基板的制作方法，其中，所述步骤S1中，所述改变石墨烯带隙的方法为化学掺杂法，具体为，在沉积石墨烯薄膜的同时对其进行化学掺杂，所沉积的石墨烯薄膜为掺杂的石墨烯薄膜，从而得到石墨烯半导体有源层；或者，
    所述改变石墨烯带隙的方法为光刻法，具体为，在沉积石墨烯薄膜后，将石墨烯薄膜切割成细带状，成为石墨烯纳米带，从而得到石墨烯半导体有源层。
  14. 如权利要求11所述的TFT基板的制作方法，其中，所述步骤S1中，通过等离子增强化学气相沉积法沉积所述石墨烯薄膜，所沉积的石墨烯薄膜为单层石墨烯薄膜；所述石墨烯半导体有源层的带隙值大于0.1eV。
  15. 如权利要求11所述的TFT基板的制作方法，其中，所述步骤S5中，通过湿蚀刻工艺对对所述金属箔片进行蚀刻。
  16. 如权利要求11所述的TFT基板的制作方法，其中，所述步骤S6中，通过涂布工艺形成有机绝缘层，所述有机绝缘层的材料为聚甲基丙烯酸甲酯。
  17. 如权利要求11所述的TFT基板的制作方法，其中，所述步骤S6中，通过物理气相沉积法沉积形成栅极导电层，所述栅极导电层的材料为铝、铜、或氧化铟锡。
  18. 如权利要求11所述的TFT基板的制作方法，还包括步骤S8、提供加强基底，使有机基底融化后再贴附到加强基底上；
    所述加强基底为玻璃、聚对苯二甲酸乙二酯塑料、或硅片。
PCT/CN2017/089247 2017-05-15 2017-06-20 Tft基板的制作方法 Ceased WO2018209751A1 (zh)

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