WO2018214727A1 - 柔性显示基板及其制作方法、显示装置 - Google Patents

柔性显示基板及其制作方法、显示装置 Download PDF

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Publication number
WO2018214727A1
WO2018214727A1 PCT/CN2018/086090 CN2018086090W WO2018214727A1 WO 2018214727 A1 WO2018214727 A1 WO 2018214727A1 CN 2018086090 W CN2018086090 W CN 2018086090W WO 2018214727 A1 WO2018214727 A1 WO 2018214727A1
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Prior art keywords
flexible display
display substrate
layer
substrate
conductive
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English (en)
French (fr)
Inventor
牛亚男
李春延
田宏伟
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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Priority to US16/344,272 priority Critical patent/US10673001B2/en
Priority to EP18806304.4A priority patent/EP3633725B1/en
Publication of WO2018214727A1 publication Critical patent/WO2018214727A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/411—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by materials, geometry or structure of the substrates
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/301—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements flexible foldable or roll-able electronic displays, e.g. thin LCD, OLED
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H10D86/443—Interconnections, e.g. scanning lines adapted for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a flexible display substrate, a method of fabricating the same, and a display device.
  • the Organic Light Emitting Display has gradually become the mainstream in the display field due to its excellent performance such as low power consumption, high color saturation, wide viewing angle, thin thickness, and flexibility.
  • OLED is widely used in terminal products such as smart phones, tablet computers, and televisions.
  • the lead pads are typically fabricated on one side of the substrate and the OLED is bent at a very small radius.
  • the flexible display substrate still contains a large amount of inorganic layers, the inorganic layers are liable to be damaged and broken, further causing damage and breakage of the conductive wirings in the OLED, resulting in degradation or even failure of the performance of the flexible display substrate and the display device. Therefore, there is a need in the art to increase the resistance to damage during bending.
  • an embodiment of the present disclosure provides a flexible display substrate, including: a flexible substrate, and a gate, a source and a drain, and a plurality of conductive wirings disposed on the flexible substrate, wherein each conductive wiring is in the The bent region of the flexible display substrate is provided with a plurality of grooves.
  • the plurality of grooves in each of the conductive wirings are discontinuously distributed.
  • the plurality of grooves in each of the conductive wirings are equally spaced along the length direction of the conductive wiring.
  • the depth of the groove is 10-90% of the thickness of the conductive wiring.
  • the width of the groove is 10-90% of the width of the conductive wiring.
  • the conductive wiring is disposed in the same layer as the source drain.
  • the flexible display substrate further includes an interlayer dielectric layer disposed between the gate and the source and drain, and a planarization layer covering the source drain and the conductive wiring.
  • the conductive wiring is disposed in the same layer as the gate.
  • an embodiment of the present disclosure provides a display device including a flexible display substrate as described above.
  • a display device has the same or similar benefits as the flexible display substrate described above, and details are not described herein again.
  • an embodiment of the present disclosure provides a method of fabricating a flexible display substrate, comprising: preparing a flexible substrate; forming a gate, a source and a drain, and a plurality of conductive wirings on the flexible substrate; and In the bent region of the display substrate, a plurality of grooves are formed in each of the conductive wirings.
  • the depth of the groove is 10-90% of the thickness of the conductive wiring.
  • the width of the groove is 10-90% of the width of the conductive wiring.
  • forming the gate, the source and the drain, and the plurality of conductive wirings on the flexible substrate include forming the plurality of conductive wirings while forming the source and drain.
  • forming the gate, the source and the drain, and the plurality of conductive wirings on the flexible substrate include forming the plurality of conductive wirings while forming the gate.
  • the method of fabricating the flexible display substrate according to an embodiment of the present disclosure has the same or similar benefits as the flexible display substrate described above, and will not be described herein.
  • FIG. 1 is a schematic cross-sectional view of a flexible display substrate according to an embodiment of the present disclosure
  • 2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H are schematic cross-sectional views of a flexible display substrate according to an embodiment of the present disclosure at various stages of fabrication;
  • FIG. 3 is a schematic plan view of a portion of a flexible display substrate according to an embodiment of the present disclosure
  • FIG. 4 is a schematic cross-sectional view of a flexible display substrate according to an embodiment of the present disclosure
  • FIG. 5 is a schematic cross-sectional view of a display device according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic flowchart of a method for fabricating a flexible display substrate according to an embodiment of the present disclosure.
  • AA effective display area BA bending area; 100 carrier substrate; 102 flexible substrate; 104 buffer layer; 106 active layer; 108 gate insulating layer; 110 gate; Dielectric layer; 114 source-drain conductive layer; 116 photoresist; 118 source; 120 drain; 122, 1221, 1222, 122m data lines; 422 gate lines; 124, 1241, 1242, 1243, 1244, 124n, 424 groove; 126 planarization layer; 510 first electrode; 520 pixel definition layer; 530 functional layer; 540 second electrode; dW data line width direction; dL data line length direction.
  • Embodiments of the present disclosure provide a flexible display substrate having improved damage resistance during bending, a display device including the flexible display substrate, and a method of fabricating the flexible display substrate, which are intended to reduce or eliminate one or more of the foregoing Said defect.
  • the flexible display substrate includes a flexible substrate 102, and a gate 110, a source 118, a drain 120, and a plurality of conductive wirings disposed on the flexible substrate 102 (only shown in the figure) one of them).
  • the flexible display substrate further includes an active layer 106.
  • the active layer 106, the gate electrode 110, the source electrode 118, and the drain electrode 120 form a driving thin film transistor in the effective display area AA of the flexible display substrate.
  • Each of the conductive wirings is provided with a plurality of grooves 124 in the bent region BA of the flexible display substrate.
  • the active layer 106 is formed of low temperature polysilicon (LTPS).
  • LTPS low temperature polysilicon
  • the carrier mobility of LTPS is significantly increased compared to amorphous silicon (a-Si). This effectively reduces the area of the TFT, increases the aperture ratio of the display device, and reduces the overall power consumption while increasing the brightness of the display device.
  • LTPS is typically prepared at lower temperatures by processes such as excimer laser crystallization (ELC), which facilitates the use of LTPS in flexible display substrates and display devices.
  • ELC excimer laser crystallization
  • Forming the active layer 106 using LTPS is advantageous for improving response time, resolution, and display quality.
  • the flexible display substrate further includes a buffer layer 104 disposed between the flexible substrate 102 and the active layer 106.
  • the buffer layer 104 is a two-layer stack of silicon dioxide and silicon nitride, wherein the two-layer stack includes a silicon dioxide layer contacting the active layer 106 and a silicon nitride layer contacting the flexible substrate 102.
  • the silicon dioxide promotes the crystal quality of the LTPS when the active layer 106 of the LTPS is formed, and the silicon nitride blocks the contaminants from the flexible substrate 102.
  • the display substrate further includes a gate insulating layer 108 disposed between the active layer 106 and the gate 110, and an interlayer dielectric disposed between the gate 110 and the source 118 and the drain 120.
  • the flexible display substrate further includes a planarization layer 126 covering the source 118, the drain 120, and the conductive wiring.
  • the conductive traces are data lines 122. As shown in FIG. 1, the data line 122 and the source 118 and the drain 120 are disposed in the same layer.
  • the data line 122 is provided with a plurality of grooves 124 in the bent region BA of the flexible display substrate.
  • a flexible display substrate having the configuration shown in FIG. 1 will be taken as an example, and a manufacturing process of the flexible display substrate will be briefly described with reference to FIGS. 2A to 2H.
  • a pattern of the active layer 106 is formed in the effective display area AA of the flexible substrate 102.
  • the precursor material of the flexible substrate is coated on the carrier substrate 100, and the precursor material is formed into the flexible substrate 102 by a process such as drying and curing.
  • the carrier substrate 100 is a glass substrate
  • the flexible substrate 102 is a flexible polyimide (PI) substrate.
  • an amorphous silicon layer is formed on the flexible substrate 102, the amorphous silicon layer is converted into a polysilicon layer by a process such as excimer laser crystallization (ELC), and the polysilicon layer is patterned. A pattern of the active layer 106 is formed.
  • ELC excimer laser crystallization
  • the buffer layer 104 is formed on the flexible substrate 102 before the formation of the amorphous silicon layer.
  • the buffer layer 104 is a two-layer laminate of silicon dioxide and silicon nitride, and has a total thickness of 200-500 nm.
  • the patterning process herein includes a process of photoresist coating, exposure, development, etching, photoresist stripping, and the like. Since processes such as photoresist coating are known to those skilled in the art, various embodiments of the present disclosure do not specifically describe a process of coating a photoresist or the like when describing a patterning process, but this does not mean that these processes are not present or are omitted. .
  • a gate insulating layer 108 is formed, and a pattern including the gate electrode 110 is formed on the gate insulating layer 108 at the effective display region AA.
  • the gate insulating layer 108 is deposited on the flexible substrate 102 on which the pattern of the active layer 106 is formed by plasma chemical vapor deposition or the like.
  • a gate metal layer is formed on the gate insulating layer 108 by a method such as sputtering or evaporation, and a patterning process is performed on the gate metal layer to form a pattern of the gate electrode 110 in the effective display region AA.
  • the gate insulating layer 108 comprises a two-layer stack.
  • a gate insulating layer and a gate metal layer are sequentially formed, and a gate insulating layer and a gate metal layer are patterned to form a gate insulating layer and a gate in the effective display region AA.
  • the stack Further, after the stack of the gate insulating layer and the gate electrode is formed, the exposed portion of the active layer is subjected to plasma treatment, which is advantageous for improving the electrical properties of the channel region of the subsequently formed thin film transistor.
  • an interlayer dielectric layer 112 is formed, and a source-drain conductive layer 114 electrically connected to the active layer 106 is formed.
  • the interlayer dielectric layer 112 covering the gate 110 and the gate insulating layer 108 is formed by plasma chemical vapor deposition or the like.
  • the interlayer dielectric layer 112 is patterned to form a contact hole penetrating the interlayer dielectric layer 112 and the gate insulating layer 108 to partially expose the active layer 106.
  • the source/drain conductive layer 114 is formed by a method such as sputtering or vapor deposition.
  • the source-drain conductive layer 114 is electrically connected to the active layer 106 through the contact hole.
  • the interlayer dielectric layer 112 comprises a two-layer laminate.
  • the source-drain conductive layer 114 is a single layer or a laminate formed of one or more of Mo, MoNb, Al, AlNd, Ti, Cu.
  • the source-drain conductive layer 114 is a Ti/Al/Ti stack, and each layer has a thickness of 500 angstroms, 6500 angstroms, and 500 angstroms, respectively.
  • a patterned photoresist 116 is formed on the source-drain conductive layer 114.
  • a photoresist is formed on the source-drain conductive layer 114.
  • the photoresist is exposed by a gray scale reticle to form a fully exposed area, a partially exposed area, and an unexposed area, removing the photoresist in the fully exposed area, and partially removing the photoinduced resistance of the partially exposed area.
  • the etchant, and the photoresist in the unexposed areas is completely retained.
  • the patterned photoresist 116 thus obtained is shown in Fig. 2D.
  • the source-drain conductive layer 114 corresponding to the fully exposed region is etched.
  • the source-drain conductive layer 114 in the fully exposed region is removed by an etch process using the patterned photoresist 116 as a reticle.
  • the source 118 and the drain 120 are formed in the effective display area AA.
  • the source 118 and the drain 120 are electrically connected to the active layer 106 through a contact hole penetrating the interlayer dielectric layer 112 and the gate insulating layer 108.
  • the photoresist of the partially exposed region is removed using a gray scale reticle.
  • the photoresist in the partially exposed regions is removed using a gray scale reticle, thereby exposing a portion of the source and drain conductive layers 114 in the bend region BA.
  • the source-drain conductive layer 114 corresponding to the partially exposed region is etched, and a plurality of grooves 124 are formed in the bent region BA.
  • the source-drain conductive layer 114 in the partially exposed regions is partially removed by an etch process using the patterned photoresist 116 as a reticle. Thereby, a plurality of grooves 124 of the source-drain conductive layer 114 are formed in the bent region BA. The recess 124 does not completely penetrate the source and drain conductive layer 114.
  • the photoresist 116 of the unexposed regions is removed, and a planarization layer 126 is formed.
  • the photoresist 116 of the unexposed region is removed, thereby forming the source 118 and the drain 120 of the thin film transistor in the effective display area AA of the flexible display substrate, and simultaneously at the flexible display substrate A conductive wiring having a groove is formed in the bent region BA.
  • the conductive wiring is a data line 122 disposed in the same layer as the source 118 and the drain 120, and the data line 122 is provided with a plurality of grooves 124.
  • the groove 124 does not completely penetrate the data line 122.
  • the depth of the recess 124 is 10-90%, such as 50%, of the thickness of the data line 122. It is advantageous for the recess 124 not to completely penetrate the data line 122 as this reduces the likelihood of the data line 122 being broken.
  • source drain and data line are disposed in the same layer
  • Graphics. Structurally, the source drain and data lines are at the same stack level in the layers of the flexible display substrate. It should be noted that the source drain and data lines of the same layer are not necessarily the same distance from the flexible substrate.
  • a planarization layer 126 is formed over the flexible display substrate to cover the source 118, the drain 120, and the data line 122.
  • the introduction of planarization layer 126 helps to reduce or eliminate the step introduced by the various device layers on the flexible substrate, thereby providing a relatively flat surface for subsequently formed device layers.
  • the planarization layer 126 is formed of an organic resin. The organic resin fills the grooves 124 in the data lines 122, which increases the strength of the data lines 122 at the grooves 124.
  • the planarization layer 126 is formed on a flexible display substrate by a coating process such as spin coating. In another embodiment, the planarization layer 126 is formed on a flexible display substrate by an inkjet printing process. Further, when the planarization layer 126 is formed, the above-described coating process or inkjet printing process is performed a plurality of times, for example, on a flexible display substrate. This facilitates the formation of a flattened layer 126 having a flatter surface.
  • the carrier substrate 100 herein serves to provide support and protection for the flexible display substrate during fabrication.
  • the carrier substrate 100 is a glass substrate
  • the flexible substrate 102 is a polyimide substrate
  • the flexible display substrate is peeled off from the carrier substrate by, for example, a laser lift off process.
  • the flexible display substrate is described by taking a bottom gate type thin film transistor whose gate is located under the source and the drain as an example.
  • the thin film transistor may be of a top gate type in which the gate is located above the source and the drain.
  • the grooves formed in the conductive wiring will be briefly described with reference to FIG.
  • Fig. 3 schematically shows a plurality of conductive wirings formed by the above process steps.
  • the conductive wiring is the data line 122 disposed in the same layer as the source 118 and the drain 120 of the thin film transistor.
  • a plurality of grooves 1241, 1242, 1243, 1244 ... 124n are formed on each of the data lines 1221, 1222 ... 122m.
  • the grooves 1241, 1242, 1243, 1244 ... 124n are discontinuously distributed. That is, the grooves do not abut each other.
  • Each of the data lines is thinned at the position of the grooves, thereby forming thick portions and thin portions which are alternately arranged. This makes the data line 122 more resistant to the damage caused by damage and breakage of the inorganic layer.
  • the grooves 1241, 1242, 1243, 1244 ... 124n are equally spaced along the length direction dL of the data line 122. This is advantageous for uniformly increasing the damage resistance of the data line 122 when bent.
  • the width of the grooves 1241, 1242, 1243, 1244...124n is 10-90%, such as 50%, of the width of the data line 122.
  • the width here is defined as the width along the width direction dW of the data line 122.
  • the groove does not span the entire width of the data line 122.
  • at most one side of each groove is disposed adjacent to the edge of the data line.
  • the top view of Figure 3 shows only one exemplary scenario of the spatial distribution and shape of the grooves in the data lines.
  • Embodiments of the present disclosure do not constrain the spatial arrangement of the grooves in each data line.
  • all the grooves are distributed in a straight line along the length direction dL of the data line, or are randomly distributed.
  • the grooves in different data lines are distributed in the same pattern or distributed according to different rules.
  • the shape of the groove is any one of a rectangle, a rounded rectangle, a square, a rounded square, an ellipse, and a circle.
  • the conductive wiring formed with the recess in the bent region BA is a data line disposed in the same layer as the source drain of the thin film transistor.
  • the concepts of embodiments of the present disclosure are applicable to any conductive wiring that may be damaged and broken when repeatedly bent in a flexible display substrate.
  • the conductive wiring is a gate line provided in the same layer as the gate of the thin film transistor.
  • FIG. 4 depicts a flexible display substrate in accordance with an embodiment of the present disclosure.
  • the same or similar components as those of the flexible display substrate of FIG. 1 are denoted by the same or similar reference numerals, and the description of these components is omitted.
  • the flexible display substrate includes a plurality of conductive wirings (only one of which is shown), and each of the conductive wirings is provided with a plurality of grooves 424 in a bent region BA of the flexible display substrate.
  • the conductive trace is a gate line 422 disposed in the same layer as the gate 110 of the thin film transistor in the flexible display substrate.
  • the data line 122 is provided with a plurality of grooves 424 in the bent region BA of the flexible display substrate.
  • gate line 422 and gate 110 of the thin film transistor are formed, for example, using a gray scale reticle, as described above in connection with Figures 2C-2H.
  • the cross-sectional shape of the groove in the conductive wiring is exemplarily shown as a rectangle.
  • the cross-sectional shape of the groove is, for example, an inverted trapezoid or an inverted triangle. It should be noted that the provision of a groove of any cross-sectional shape in the conductive wiring is advantageous for improving the damage resistance of the conductive wiring when bent.
  • a contact hole is formed in the flexible display substrate shown in FIG. 1, and the contact hole penetrates through the planarization layer 126 to partially expose the drain electrode 120.
  • a metal layer is formed by a method such as sputtering or evaporation, and the first electrode 510 is formed by a patterning process.
  • the first electrode 510 is electrically connected to the drain electrode 120 through the contact hole.
  • a pixel defining layer 520 is formed on the planarization layer 126 on which the first electrode 510 is formed, and a majority of the surface area of the first electrode 510 is exposed by a patterning process.
  • the functional layer 530 and the second electrode 540 are sequentially formed on the flexible display substrate on which the pixel defining layer 520 is formed.
  • the functional layer 530 includes a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, an electron injection layer, and the like.
  • the first electrode 510, the functional layer 530, and the second electrode 540 form an OLED, thereby obtaining a display device.
  • the display device is described by taking an OLED as an example.
  • the display device of the embodiment of the present disclosure is not limited thereto.
  • the display device is, for example, a thin film transistor liquid crystal display device (TFT LCD) employing a flexible substrate.
  • the manufacturing process of the display device includes the steps of dropping liquid crystal on the flexible display substrate shown in FIG. 1, and opposing the substrate, such as a color filter substrate. These steps are well known to those skilled in the art and will not be described herein.
  • the display device of the embodiment of the present disclosure may be any product or component having a display function, such as a liquid crystal panel, an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, or the like.
  • a display function such as a liquid crystal panel, an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, or the like.
  • a manufacturing method of a flexible display substrate includes: preparing a flexible substrate in step S610; forming a gate, a source and a drain, and a plurality of conductive wirings on the flexible substrate; and step S630; In the bent region of the flexible display substrate, a plurality of grooves are formed in each of the conductive wirings.
  • the depth of the groove is 10-90%, such as 50%, of the thickness of the conductive wiring.
  • the width of the groove is 10-90%, such as 50%, of the width of the conductive wiring.
  • forming the gate, the source drain, and the plurality of conductive traces on the flexible substrate includes forming the plurality of conductive traces while forming the source and drain. Specific steps are for example described above in connection with Figures 2C-2H.
  • forming the gate, the source drain, and the plurality of conductive traces on the flexible substrate includes forming the plurality of conductive traces while forming the gate. Specific steps are for example described above in connection with Figures 2C-2H.
  • each of the conductive wirings is provided with a plurality of grooves in a bent region of the flexible display substrate.
  • the purpose of the grooves is to introduce portions of different thicknesses in the conductive wiring, such as the thick portions and thin portions described above, so that the damage resistance of the conductive wiring at the time of bending is improved.
  • the thin portion is referred to as a groove with respect to the thick portion.
  • the thick portion is referred to as a raised portion, for example, with respect to the thin portion. Therefore, in the context of the present disclosure, “the conductive wiring is provided with a groove” can also be understood as “the conductive wiring is provided with a convex portion”.
  • the embodiments of the present disclosure provide a flexible display substrate, a manufacturing method thereof, and a display device.
  • the display substrate includes a flexible substrate, and a gate, a source and a drain, and a plurality of conductive wirings disposed on the flexible substrate, wherein each of the conductive wirings is provided with a plurality of grooves in a bent region of the flexible display substrate. Since each of the conductive wirings is provided with a plurality of grooves in the bent region of the flexible display substrate, the deformation of the flexible display substrate during bending is reduced, deformation and cracking of the inorganic layer are suppressed, and the conductive wiring is bent. The damage resistance is improved. This improves the bending resistance of the flexible display substrate and improves the reliability and life of the flexible display substrate and the display device.

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Abstract

公开了一种柔性显示基板，包括：柔性基板，以及设置在所述柔性基板上的栅极、源漏极和多条导电布线。每条导电布线在所述柔性显示基板的弯折区域设有多个凹槽，使得导电布线在弯折时的损伤抗性提高。还公开了包括该柔性显示基板的显示装置以及该柔性显示基板的制作方法。

Description

柔性显示基板及其制作方法、显示装置
相关专利申请
本申请主张于2017年5月25日提交的中国专利申请No.201710378410.3的优先权，其全部内容通过引用结合于此。
技术领域
本公开涉及显示技术领域，并且具体涉及一种柔性显示基板及其制作方法、显示装置。
背景技术
有机电致发光显示装置(Organic Light Emitting Display，OLED)凭借其低功耗、高色饱和度、广视角、薄厚度、能实现柔性化等优异性能，逐渐成为显示领域的主流。目前，OLED广泛应用于智能手机、平板电脑、电视等终端产品。为了实现窄边框，引线焊盘通常制作在基板的一侧，并且OLED进行极小半径的弯折。进行弯折时，由于柔性显示基板依然包含大量无机层，这些无机层容易发生损伤和断裂，进一步引发OLED中导电布线的损伤与断裂，引起柔性显示基板和显示装置性能降低，甚至失效。因此，本领域中存在提高在弯折时的损伤抗性的需求。
发明内容
在第一方面，本公开实施例提供了一种柔性显示基板，包括：柔性基板，以及设置在所述柔性基板上的栅极、源漏极和多条导电布线，其中每条导电布线在所述柔性显示基板的弯折区域设有多个凹槽。
例如，每条导电布线中的所述多个凹槽不连续地分布。
例如，每条导电布线中的所述多个凹槽沿导电布线的长度方向等间距分布。
例如，所述凹槽的深度为所述导电布线的厚度的10-90％。
例如，其中所述凹槽的宽度为所述导电布线的宽度的10-90％。
例如，所述导电布线与所述源漏极同层设置。
例如，所述柔性显示基板还包括设置在所述栅极和所述源漏极之 间的层间电介质层，以及覆盖所述源漏极和所述导电布线的平坦化层。
例如，所述导电布线与所述栅极同层设置。
在第二方面，本公开实施例提供了一种显示装置，其包括如上文所述的柔性显示基板。
根据本公开实施例的显示装置具有与上文所述的柔性显示基板相同或相似的益处，此处不再赘述。
在第三方面，本公开实施例提供了一种柔性显示基板的制作方法，包括：准备柔性基板；在所述柔性基板上形成栅极、源漏极和多条导电布线；以及在所述柔性显示基板的弯折区域中，在每条导电布线中形成多个凹槽。
例如，所述凹槽的深度为所述导电布线的厚度的10-90％。
例如，所述凹槽的宽度为所述导电布线的宽度的10-90％。
例如，在所述柔性基板上形成栅极、源漏极和多条导电布线包括：在形成所述源漏极的同时，形成所述多条导电布线。
例如，在所述柔性基板上形成栅极、源漏极和多条导电布线包括：在形成所述栅极的同时，形成所述多条导电布线。
根据本公开实施例的柔性显示基板的制作方法具有与上文所述的柔性显示基板相同或相似的益处，此处不再赘述。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图做简单介绍。应理解，下面描述中的附图仅仅涉及本公开实施例的一些实施例，而不是旨在限制本公开。
图1为本公开一实施例的柔性显示基板的示意性剖面图；
图2A、2B、2C、2D、2E、2F、2G、2H为本公开一实施例的柔性显示基板在各个制作阶段的示意性剖面图；
图3为本公开一实施例的柔性显示基板的一部分的示意性俯视图；
图4为本公开一实施例的柔性显示基板的示意性剖面图；
图5为本公开一实施例的显示装置的示意性剖面图；以及
图6为本公开一实施例的柔性显示基板的制作方法的示意性流程图。
具体实施方式
为了使本领域技术人员更好地理解本公开实施例的技术方案，以下结合附图对本公开实施例的结构和原理进行详细说明，所举实施例仅用于解释本公开，并非以此限定本公开实施例的保护范围。
附图中示出的部件标注如下：AA有效显示区域；BA弯折区域；100载体基板；102柔性基板；104缓冲层；106有源层；108栅极绝缘层；110栅极；112层间电介质层；114源漏导电层；116光致抗蚀剂；118源极；120漏极；122、1221、1222、122m数据线；422栅线；124、1241、1242、1243、1244、124n、424凹槽；126平坦化层；510第一电极；520像素定义层；530功能层；540第二电极；dW数据线的宽度方向；dL数据线的长度方向。
本公开实施例提供了一种具有在弯折时损伤抗性提高的柔性显示基板、包括该柔性显示基板的显示装置以及该柔性显示基板的制作方法，其旨在减轻或消除一个或多个前文所述的缺陷。
以下结合图1描述根据本公开一实施例的柔性显示基板。在一实施例中，如图1所示，柔性显示基板包括柔性基板102，以及设置在柔性基板102上的栅极110、源极118、漏极120和多条导电布线(图中仅示出其中之一)。该柔性显示基板还包括有源层106。有源层106、栅极110、源极118和漏极120在该柔性显示基板的有效显示区域AA形成驱动薄膜晶体管。每条导电布线在该柔性显示基板的弯折区域BA设有多个凹槽124。
在一实施例中，有源层106由低温多晶硅(LTPS)形成。与非晶硅(a-Si)相比，LTPS的载流子迁移率显著增加。这有效减小TFT的面积，提高显示装置的开口率，并且在提高显示装置的亮度的同时降低整体功耗。LTPS通常通过诸如准分子激光晶化(ELC)的工艺在较低温度下制备，这有利于LTPS在柔性显示基板和显示装置中的应用。利用LTPS形成有源层106，有利于提高响应时间、分辨率以及显示质量。
在一实施例中，该柔性显示基板还包括设置在柔性基板102和有源层106之间的缓冲层104。在一实施例中，缓冲层104为二氧化硅和氮化硅的双层叠层，其中该双层叠层包括接触有源层106的二氧化硅层以及接触柔性基板102的氮化硅层。二氧化硅促进在形成LTPS的有源层106时LTPS的结晶质量，并且氮化硅阻挡来自柔性基板102的污 染物。
在一实施例中，该显示基板还包括设置在有源层106和栅极110之间的栅极绝缘层108，以及设置在栅极110和源极118以及漏极120之间的层间电介质层112。此外，该柔性显示基板还包括覆盖源极118、漏极120以及导电布线的平坦化层126。
在一实施例中，导电布线为数据线122。如图1所示，数据线122和源极118以及漏极120同层设置。数据线122在柔性显示基板的弯折区域BA设有多个凹槽124。
在下文中以具有图1所示构造的柔性显示基板为例，参考图2A-2H简要描述该柔性显示基板的制作过程。
如图2A所示，在柔性基板102的有效显示区域AA形成有源层106的图形。
在一实施例中，在载体基板100上涂布柔性基板的前驱体材料，通过诸如烘干和固化的工艺将该前驱体材料形成为柔性基板102。例如，该载体基板100为玻璃基板，并且该柔性基板102为柔性的聚酰亚胺(PI)基板。
在一实施例中，在该柔性基板102上形成非晶硅层，利用诸如准分子激光晶化(ELC)的工艺将该非晶硅层转变为多晶硅层，并且对该多晶硅层进行构图工艺以形成有源层106的图形。
如上所述，在一实施例中，在形成该非晶硅层之前，在柔性基板102上形成缓冲层104。例如，缓冲层104为二氧化硅和氮化硅的双层叠层，并且总厚度为200-500nm。
此处的构图工艺包括光刻胶涂敷、曝光、显影、刻蚀、光刻胶剥离等过程。由于光刻胶涂布等过程为本领域技术人员所知晓，本公开各实施例在描述构图工艺时，不具体描述涂布光刻胶等过程，但是这不意味着这些过程不存在或被省略。
如图2B所示，在形成了有源层106的图形的柔性基板102上，形成栅极绝缘层108，并且在栅极绝缘层108上在有效显示区域AA形成包括栅极110的图形。
在一实施例中，通过等离子体化学气相沉积等方法，在形成了有源层106的图形的柔性基板102上，沉积栅极绝缘层108。接着，通过溅射或蒸镀等方法，在栅极绝缘层108上形成栅极金属层，并且对该 栅极金属层进行构图工艺，在有效显示区域AA中形成栅极110的图形。在一实施例中，栅极绝缘层108包括双层叠层。
在可替换实施例中，依次形成栅极绝缘层和栅极金属层，对该栅极绝缘层和栅极金属层二者进行构图工艺，在有效显示区域AA中形成栅极绝缘层和栅极的叠层。此外，在形成栅极绝缘层和栅极的叠层之后，对有源层的露出部分进行等离子体处理，这有利于提高后续形成的薄膜晶体管的沟道区的电气性能。
如图2C所示，形成层间电介质层112，并且形成电连接到有源层106的源漏导电层114。
在一实施例中，通过等离子体化学气相沉积等方法，形成覆盖栅极110和栅极绝缘层108的层间电介质层112。对该层间电介质层112进行构图工艺，形成贯穿层间电介质层112和栅极绝缘层108的接触孔，使有源层106部分露出。接着，通过溅射或蒸镀等方法形成源漏导电层114。源漏导电层114通过该接触孔电连接到有源层106。在一实施例中，层间电介质层112包括双层叠层。
在一实施例中，源漏导电层114为Mo、MoNb、Al、AlNd、Ti、Cu中的一种或多种形成的单层或叠层。例如，源漏导电层114为Ti/Al/Ti叠层，并且每层厚度分别为500埃、6500埃、500埃。
如图2D所示，在源漏导电层114上形成图案化的光致抗蚀剂116。
在一实施例中，在源漏导电层114上形成光致抗蚀剂。利用灰阶掩模版对光致抗蚀剂进行曝光工艺，形成完全曝光区域、部分曝光区域和未曝光区域，移除完全曝光区域的光致抗蚀剂，部分移除部分曝光区域的光致抗蚀剂，并且完全保留未曝光区域的光致抗蚀剂。由此得到的图案化的光致抗蚀剂116示于图2D。
如图2E所示，刻蚀完全曝光区域对应的源漏导电层114。
在一实施例中，利用图案化的光致抗蚀剂116为掩模版，通过刻蚀工艺移除完全曝光区域中的源漏导电层114。藉此在有效显示区域AA中形成源极118和漏极120。源极118和漏极120通过贯穿层间电介质层112和栅极绝缘层108的接触孔，电连接到有源层106。
如图2F所示，利用灰阶掩模版移除部分曝光区域的光致抗蚀剂。
在一实施例中，利用灰阶掩模版，移除部分曝光区域内的光致抗蚀剂，由此露出弯折区域BA中的源漏导电层114的一部分。
如图2G所示，刻蚀部分曝光区域对应的源漏导电层114，在弯折区域BA中形成多个凹槽124。
在一实施例中，利用图案化的光致抗蚀剂116为掩模版，通过刻蚀工艺部分移除部分曝光区域中的源漏导电层114。藉此在弯折区域BA中形成源漏导电层114的多个凹槽124。凹槽124未完全穿透源漏导电层114。
如图2H所示，移除未曝光区域的光致抗蚀剂116，并且形成平坦化层126。
在一实施例中，移除未曝光区域的光致抗蚀剂116，藉此在柔性显示基板的有效显示区域AA中形成薄膜晶体管的源极118和漏极120，并且同时在柔性显示基板的弯折区域BA中形成具有凹槽的导电布线。在此实施例中，该导电布线为与源极118和漏极120同层设置的数据线122，并且数据线122上设置有多个凹槽124。凹槽124未完全穿透数据线122。在一实施例中，凹槽124的深度为数据线122的厚度的10-90％，例如50％。凹槽124未完全穿透数据线122是有利的，因为这减小了数据线122断路的可能性。
如本领域技术人员所知晓，“源漏极和数据线同层设置”是利用同一成膜工艺形成一膜层，并且对该膜层进行一次构图工艺而形成源漏极的图形和数据线的图形。从结构上说，源漏极和数据线在柔性显示基板的各层中位于同一堆叠层级。应指出，同层设置的源漏极和数据线与柔性基板的距离不一定相同。
在一实施例中，在柔性显示基板上形成平坦化层126，以覆盖源极118、漏极120和数据线122。平坦化层126的引入有助于减少或消除柔性基板上由各器件层引入的段差，从而为后续形成的器件层提供相对平整的表面。在一实施例中，平坦化层126由有机树脂形成。有机树脂填充数据线122中的凹槽124，这增加了数据线122在凹槽124处的强度。
在一实施例中，通过诸如旋涂(spin coating)的涂布工艺，在柔性显示基板上形成该平坦化层126。在另一实施例中，通过喷墨打印(inkjet printing)工艺，在柔性显示基板上形成该平坦化层126。此外，在形成平坦化层126时，例如在柔性显示基板上多次执行上述涂布工艺或喷墨打印工艺。这有利于形成表面更平整的平坦化层126。
通过上述工艺步骤，完成本公开实施例的柔性显示基板的制作。应指出，此处的载体基板100是在制作过程中为该柔性显示基板提供支撑和保护的作用。在一实施例中，该载体基板100为玻璃基板，该柔性基板102为聚酰亚胺基板，通过例如激光剥离(laser lift off)工艺将柔性显示基板从载体基板剥离。
在上述实施例中，以栅极位于源极和漏极的下方的底栅型薄膜晶体管为例，描述了该柔性显示基板。然而，本公开实施例不对薄膜晶体管的结构类型进行限定。例如，薄膜晶体管可以为顶栅型，其中栅极位于源极和漏极的上方。在下文中，参考图3简要描述导电布线中形成的凹槽。
图3示意性示出了通过上述工艺步骤形成的多条导电布线。在此情形中，该导电布线为与薄膜晶体管的源极118和漏极120同层设置的数据线122。如所示，在柔性显示基板的弯折区域BA，每条数据线1221、1222...122m上形成有多个凹槽1241、1242、1243、1244...124n。
在一实施例中，在每条数据线1221、1222...122m中，凹槽1241、1242、1243、1244...124n不连续地分布。即，这些凹槽不相互邻接。每条数据线在凹槽的位置处厚度减薄，由此形成交替布置的厚部和薄部。这使得数据线122更耐受无机层的损伤和断裂导致的冲击。
在一实施例中，在每条数据线1221、1222...122m中，凹槽1241、1242、1243、1244...124n沿数据线122的长度方向dL等间距分布。这对于均匀地提高数据线122在弯折时的损伤抗性是有利的。
在一实施例中，凹槽1241、1242、1243、1244...124n的宽度为数据线122的宽度的10-90％，例如50％。此处的宽度定义为沿数据线122的宽度方向dW的宽度。这种情况下，凹槽不跨过数据线122的整个宽度。例如，在数据线122的宽度方向dW上，每个凹槽的最多一条边紧邻数据线的边缘设置。
这避免了数据线的厚部和薄部交接处平行于弯折线时，数据线有可能损伤或断裂的问题。
图3的俯视图仅仅示出了数据线中的凹槽的空间分布和形状的一种示例性情形。本公开实施例不对每条数据线中的凹槽的空间排布进行约束。例如，在每条数据线中，所有凹槽沿数据线的长度方向dL在一条直线上分布，或者随机分布。例如，不同数据线中的凹槽按相同 规律分布，或者按不同规律分布。例如，在图3所示的俯视图中，凹槽的形状为矩形、圆角矩形、正方形、圆角正方形、椭圆形、圆形中的任何一种。
结合图1、2A-2H、3在上文描述的各个实施例中，在弯折区域BA中形成有凹槽的导电布线为与薄膜晶体管的源漏极同层设置的数据线。本公开实施例的构思适用于柔性显示基板中反复弯折时可能损伤和断裂的任何导电布线。
在下文中，结合图4描述该导电布线为与薄膜晶体管的栅极同层设置的栅线的情形。
图4描述根据本公开一实施例的柔性显示基板。在图4中，使用相同或相似的附图标记表示与图1的柔性显示基板相同或相似的部件，并且省略了对这些部件的描述。
如图4所示，柔性显示基板包括多条导电布线(图中仅示出其中之一)，并且每条导电布线在该柔性显示基板的弯折区域BA设有多个凹槽424。在一实施例中，该导电布线为栅线422，其和柔性显示基板中的薄膜晶体管的栅极110同层设置。数据线122在柔性显示基板的弯折区域BA设有多个凹槽424。类似地，关于凹槽424的描述可参考上文有关凹槽124的描述。在此实施例中，栅线422与薄膜晶体管的栅极110例如利用灰阶掩模版形成，如上文结合图2C-2H所描述。
在图1和4中，导电布线中的凹槽的横截面形状被示例性地示为矩形。在其它实施例中，凹槽的横截面形状例如为倒立的梯形或倒立的三角形。应指出，在导电布线中设置任何横截面形状的凹槽，都有利于提高导电布线在弯折时的损伤抗性。
在下文中，结合图5描述根据本公开一实施例的显示装置。如图5所示，在图1所示的柔性显示基板中形成接触孔，该接触孔贯穿平坦化层126，使漏极120部分露出。接着，通过溅射或蒸镀等方法形成金属层，并且通过构图工艺形成第一电极510。第一电极510通过该接触孔电连接到漏极120。在形成有第一电极510的平坦化层126上形成像素定义层520，并且通过构图工艺露出第一电极510的大部分表面区域。接着，在形成有像素定义层520的柔性显示基板上依次形成功能层530和第二电极540。在一实施例中，功能层530包括空穴注入层、空穴传输层、发光层、电子传输层、电子注入层等。第一电极510、功能层 530和第二电极540形成OLED，由此得到一种显示装置。
在上述实施例中，以OLED为例描述了该显示装置。然而，本公开实施例的显示装置不限于此。在其它实施例中，该显示装置例如为采用柔性基板的薄膜晶体管液晶显示装置(TFT LCD)。在这种情形下，该显示装置的制作过程包括在图1所示的柔性显示基板上滴注液晶、与诸如彩膜基板的对置基板对盒等步骤。这些步骤为本领域技术人员所熟知，在此不再赘述。
本公开实施例的显示装置可以是任何具有显示功能的产品或部件，例如液晶面板、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等。
在下文中，结合图6描述根据本公开一实施例的柔性显示基板的制作方法。如图6所示，一种柔性显示基板的制作方法，包括：步骤S610准备柔性基板；步骤S620在所述柔性基板上形成栅极、源漏极和多条导电布线；以及步骤S630在所述柔性显示基板的弯折区域中，在每条导电布线中形成多个凹槽。
在一实施例中，所述凹槽的深度为所述导电布线的厚度的10-90％，例如50％。
在一实施例中，所述凹槽的宽度为所述导电布线的宽度的10-90％，例如50％。
在一实施例中，在所述柔性基板上形成栅极、源漏极和多条导电布线包括：在形成所述源漏极的同时，形成所述多条导电布线。具体步骤例如参考上文结合图2C-2H所描述。
在一实施例中，在所述柔性基板上形成栅极、源漏极和多条导电布线包括：在形成所述栅极的同时，形成所述多条导电布线。具体步骤例如参考上文结合图2C-2H所描述。
在本公开实施例中，每条导电布线在柔性显示基板的弯折区域设有多个凹槽。凹槽的目的是在导电布线中引入不同厚度的部分，例如上文所述的厚部和薄部，使得导电布线在弯折时的损伤抗性提高。如上述实施例所使用的表述，相对于该厚部而言，该薄部被称为凹槽。然而，相对于该薄部而言，该厚部例如被称为凸起部。因此，在本公开上下文中，“导电布线设有凹槽”也可以理解为“导电布线设有凸起部”。
综上所述，本公开实施例提供了一种柔性显示基板及其制作方法、显示装置。该显示基板包括柔性基板，以及设置在所述柔性基板上的栅极、源漏极和多条导电布线，其中每条导电布线在所述柔性显示基板的弯折区域设有多个凹槽。由于每条导电布线在所述柔性显示基板的弯折区域设有多个凹槽，该柔性显示基板在弯折时的变形减小，无机层的变形和裂纹得到抑制，导电布线在弯折时的损伤抗性提高。这改善了柔性显示基板的抗弯折效果，提高柔性显示基板以及显示装置的可靠性和寿命。
需要指出，在附图中，为了图示的清晰可能夸大了层和区域的尺寸。而且可以理解，当元件或层被称为在另一元件或层“上”时，它可以直接在其它元件上，或者可以存在中间的层。另外，可以理解，当元件或层被称为在另一元件或层“下”时，它可以直接在其它元件下，或者可以存在一个以上的中间的层或元件。另外，还可以理解，当层或元件被称为在两层或两个元件“之间”时，它可以为两层或两个元件之间惟一的层，或还可以存在一个以上的中间层或元件。通篇相似的附图标记指示相似的元件。在本公开实施例中，术语“第一”、“第二”、“第三”仅用于描述目的，而不能理解为指示或暗示相对重要性。
仅仅是出于图示和说明的目的而给出对本公开实施例的前述描述。它们不是旨在穷举或者限制本公开实施例的内容。因此，本领域技术人员将容易想到许多调整和变型，而这些调整和变形都落在本公开实施例的保护范围之内。简而言之，本公开实施例的保护范围由所附权利要求定义。

Claims (13)

  1. 一种柔性显示基板，包括：柔性基板，以及设置在所述柔性基板上的栅极、源漏极和多条导电布线，其中每条导电布线在所述柔性显示基板的弯折区域设有多个凹槽。
  2. 根据权利要求1所述的柔性显示基板，其中每条导电布线中的所述多个凹槽不连续地分布。
  3. 根据权利要求1所述的柔性显示基板，其中每条导电布线中的所述多个凹槽沿导电布线的长度方向等间距分布。
  4. 根据权利要求1所述的柔性显示基板，其中所述凹槽的深度为所述导电布线的厚度的10-90％。
  5. 根据权利要求1所述的柔性显示基板，其中所述凹槽的宽度为所述导电布线的宽度的10-90％
  6. 根据权利要求1所述的柔性显示基板，其中所述导电布线与所述源漏极同层设置。
  7. 根据权利要求1所述的柔性显示基板，其中所述导电布线与所述栅极同层设置。
  8. 根据权利要求1所述的柔性显示基板，其中所述柔性显示基板还包括设置在所述栅极和所述源漏极之间的层间电介质层，以及覆盖所述源漏极和所述导电布线的平坦化层。
  9. 一种显示装置，包括根据权利要求1-8中任意一项所述的柔性显示基板。
  10. 一种柔性显示基板的制作方法，包括：
    准备柔性基板；
    在所述柔性基板上形成栅极、源漏极和多条导电布线；以及
    在所述柔性显示基板的弯折区域中，在每条导电布线中形成多个凹槽。
  11. 根据权利要求8所述的制作方法，其中所述凹槽的深度为所述导电布线的厚度的10-90％。
  12. 根据权利要求8所述的制作方法，其中所述凹槽的宽度为所述导电布线的宽度的10-90％。
  13. 根据权利要求8所述的制作方法，其中在所述柔性基板上形成 栅极、源漏极和多条导电布线包括：在形成所述源漏极或所述栅极的同时，形成所述多条导电布线。
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