WO2018223630A1 - 有机发光二极管阵列基板及其制备方法、显示装置 - Google Patents

有机发光二极管阵列基板及其制备方法、显示装置 Download PDF

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Publication number
WO2018223630A1
WO2018223630A1 PCT/CN2017/114554 CN2017114554W WO2018223630A1 WO 2018223630 A1 WO2018223630 A1 WO 2018223630A1 CN 2017114554 W CN2017114554 W CN 2017114554W WO 2018223630 A1 WO2018223630 A1 WO 2018223630A1
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Prior art keywords
power supply
substrate
supply trace
trace
insulating layer
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PCT/CN2017/114554
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English (en)
French (fr)
Inventor
朱升
张正元
随鹏
袁粲
卓晓军
王涛
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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Priority to EP17892067.4A priority Critical patent/EP3637469B1/en
Priority to US16/073,096 priority patent/US11233114B2/en
Priority to JP2018539151A priority patent/JP7033070B2/ja
Publication of WO2018223630A1 publication Critical patent/WO2018223630A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/20—Changing the shape of the active layer in the devices, e.g. patterning

Definitions

  • Embodiments of the present disclosure relate to an organic light emitting diode array substrate, a method of fabricating the same, and a display device.
  • OLED Organic Light Emitting Diode
  • LCD Organic Light Emitting Diode
  • At least one embodiment of the present disclosure provides an OLED array substrate, the OLED array substrate includes: a substrate; a first metal layer disposed on the substrate; and disposed on the first metal layer a first insulating layer away from a side of the substrate substrate; a second metal layer disposed on a side of the first insulating layer away from the substrate substrate; wherein the first metal layer includes a first The power supply traces, the second metal layer includes a second power supply trace; the second power supply trace is connected in parallel with the first power supply trace through a first via structure extending through the first insulating layer.
  • the material of the first metal layer has a resistivity lower than that of the material of the second metal layer.
  • the material of the first metal layer includes at least one of copper, copper alloy, silver, and silver alloy; the material of the second metal layer At least one of alloys formed of nickel, molybdenum, niobium, aluminum, titanium, and any combination thereof.
  • the second power supply trace is connected in parallel with the first power supply trace through at least two of the first via structures extending through the first insulating layer.
  • the width of the first power supply trace is greater than the width of the second power supply trace.
  • the first power supply trace has a planar structure.
  • the organic light emitting diode array substrate provided by at least one embodiment of the present disclosure further includes a pixel structure, wherein the pixel structure includes a driving transistor, and the driving transistor includes a gate, a gate insulating layer, a second insulating layer, and a first electrode.
  • the first electrode is electrically connected to the second power supply trace through a second via structure penetrating the second insulating layer and the gate insulating layer.
  • the material of the gate is the same as the material of the second power supply trace, and the gate is in the same state as the second power supply trace. Layers are spaced apart from each other.
  • the driving transistor further includes an active layer, and the material of the active layer is a transparent conductive material.
  • the transparent conductive material includes indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), gallium zinc oxide (GZO). And at least one of zinc oxide (ZnO), indium oxide (In 2 O 3 ), and aluminum zinc oxide (AZO).
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • IGO indium gallium oxide
  • GZO gallium zinc oxide
  • ZnO zinc oxide
  • indium oxide In 2 O 3
  • AZO aluminum zinc oxide
  • At least one embodiment of the present disclosure further provides a display device including any of the above organic light emitting diode array substrates.
  • At least one embodiment of the present disclosure further provides a method for fabricating an organic light emitting diode array substrate, the method comprising: providing a substrate; depositing a first metal film on the substrate, and patterning the same to form a first metal layer; a first insulating film deposited on a side of the first metal layer away from the substrate; and patterned to form a first insulating layer; away from the first insulating layer Depositing a second metal thin film on one side of the base substrate and patterning the same to form a second metal layer; wherein the first metal layer includes a first power supply trace, and the second metal layer includes a first a second power supply trace; the second power supply trace is connected in parallel with the first power supply trace through a first via structure extending through the first insulating layer.
  • the material of the first metal layer has a resistivity lower than that of the material of the second metal layer.
  • the width of the first power supply trace is greater than the width of the second power supply trace.
  • the preparation method provided by at least one embodiment of the present disclosure further includes forming a pixel structure, wherein forming the pixel structure includes forming a driving transistor, and forming the driving transistor includes forming a gate, a gate insulating layer, a second insulating layer, and a first An electrode; the first electrode is electrically connected to the second power supply trace through a second via structure penetrating the second insulating layer and the gate insulating layer.
  • the material of the gate is the same as the material of the second power supply trace, and the gate is disposed on the same layer as the second power supply trace. Set apart from each other.
  • 1 is a schematic cross-sectional view of an organic light emitting diode array substrate
  • FIG. 2 is a schematic cross-sectional view of an organic light emitting diode array substrate according to an embodiment of the present disclosure
  • 2b is a cross-sectional structural diagram of a second power supply trace connected in parallel with a first power supply line according to an embodiment of the present disclosure
  • FIG. 3 is a schematic plan view showing a planar structure of an organic light emitting diode array substrate according to an embodiment of the present disclosure
  • FIG. 4 is a cross-sectional structural view of the organic light emitting diode array substrate cut along the line A-A' in FIG. 3;
  • FIG. 5 is a schematic cross-sectional view of an organic light emitting diode array substrate according to an embodiment of the present disclosure
  • FIG. 6 is a schematic diagram of a planar structure of a first power supply line disposed in a hollow structure according to an embodiment of the present disclosure
  • FIG. 7 is a schematic diagram of a 3T1C pixel circuit according to an embodiment of the present disclosure.
  • FIG. 8 is a flowchart of a method for fabricating an organic light emitting diode array substrate according to an embodiment of the present disclosure.
  • the organic light emitting diode (OLED) array substrate includes a plurality of pixel units, and each of the pixel units may include a switching transistor, a driving transistor, and an OLED display device.
  • An OLED is a current-type light-emitting device that mainly includes an anode, a cathode, and an organic material functional layer formed between the anode and the cathode.
  • the working principle of OLED is mainly: the functional layer of organic material is driven by the injection and recombination of carriers under the driving of the electric field formed by the anode and the cathode.
  • the driving transistor electrically connected to the anode or the cathode of the OLED functions as a current limiting. If the resistivity of the electrode material of the driving transistor is too large or the resistance of the power supply trace is too large, the voltage drop is large, and the voltage drop is The effect of pixel cells at different locations is different, which adversely affects the uniformity of the display.
  • the OLED array substrate includes a substrate substrate 101 and a driving transistor disposed on the substrate 101.
  • the OLED array substrate further includes An organic light emitting diode (OLED), a storage capacitor, and the like (not shown) connected to the driving transistor are included.
  • the driving transistor includes a gate 102, a source and a drain, the power trace 108 and the gate 102 are formed in the same patterning process, and the power trace 108 and the gate 102 have the same material, for example, the gate 102 and the power source.
  • the material of the traces 108 is aluminum metal material, and the power traces 108 are disposed on the same layer as the gates 102 and spaced apart from each other.
  • the driving transistor further includes a gate insulating layer 103 disposed on the gate electrode 102 and the power supply trace 108, and is disposed on the gate insulating layer.
  • the active layer 104 is provided with an insulating layer 105.
  • the insulating layer 105 is provided with a first source/drain electrode 106 (such as a source or a drain) and a second source/drain electrode 107 (corresponding to Ground, such as the drain or source).
  • a first source/drain electrode 106 of one driving transistor is connected to a first source/drain electrode 106 of another driving transistor, and a first source of one driving transistor is connected
  • the drain electrode 106 and the first source/drain electrode 106 of the other driving transistor are electrically connected to the power supply trace 108 through a via structure penetrating through the insulating layer 105 and the gate insulating layer 103.
  • the process of preparing an electrode for driving a transistor by using a stable aluminum metal material is relatively mature, but the aluminum metal has a high resistivity, and an aluminum metal material is used to form an electrode of the driving transistor (for example, a gate electrode, a first source/drain electrode, and When the second source/drain electrodes and the like are routed, the voltage drop generated is large, and the large voltage drop adversely affects the uniformity of display of the display device.
  • the width of the aluminum metal electrode or the aluminum metal trace is set to be large to reduce the voltage drop, but the electrode or the metal trace having a larger width reduces the aperture ratio and increases the production cost.
  • a copper or silver metal material has a low resistivity
  • a copper metal material or a silver metal material is used to form electrodes of a driving transistor (for example, a gate electrode, a first source drain electrode, and a second source drain electrode)
  • a driving transistor for example, a gate electrode, a first source drain electrode, and a second source drain electrode
  • the voltage drop is small, but the copper metal and the silver metal are easily oxidized, and in the process of patterning the metal film formed by the copper metal material or the silver metal material, the etching liquid is on the copper metal.
  • the etching rate of the material and the silver metal material is low, and the degree of etching is not well controlled, so that the uniformity of the formed copper metal electrode or silver metal electrode is lowered.
  • the inventors of the present disclosure have found that if the electrode of the driving transistor is made of an aluminum metal material, a second power supply trace is formed in the process of preparing the gate of the driving transistor, and the first power supply trace is formed by using a copper metal material.
  • the first power supply trace and the second power supply trace are connected through the via structure to reduce the resistance of the power supply trace (including the first power supply trace and the second power supply trace), thereby reducing the voltage drop as a whole. It is also possible to avoid the problem of large voltage drop when forming a power supply trace by using a metal material such as aluminum having good stability, and to form a metal by using a copper or silver having a low resistivity or a metal alloy containing at least one of copper and silver. The problem of immature process when the electrode is used.
  • At least one embodiment of the present disclosure provides an organic light emitting diode (OLED) array substrate including: a substrate substrate; a first metal layer disposed on the substrate; a first insulating layer on a side of the metal layer away from the substrate substrate; a second metal layer disposed on a side of the first insulating layer away from the substrate substrate; wherein the first A metal layer includes a first power supply trace, and the second metal layer includes a second power supply trace; the second power supply trace is connected in parallel with the first power supply trace through a first via structure extending through the first insulating layer.
  • OLED organic light emitting diode
  • Embodiments of the present disclosure form an electrode of a driving transistor and a second power supply trace by using a metal material such as aluminum having good stability, using copper or silver having a low resistivity or a metal alloy containing at least one of copper and silver.
  • the first power supply is routed, and the first power supply trace and the second power supply trace are connected in parallel through the via structure to reduce the voltage drop.
  • the problem of large voltage drop when the power supply trace is formed by using a metal material such as aluminum having good stability can be avoided at the same time, and copper or silver having a lower resistivity or a metal alloy containing at least one of copper and silver can be used to form a metal electrode.
  • the problem of immature craftsmanship is described in this way, the problem of large voltage drop when the power supply trace is formed by using a metal material such as aluminum having good stability.
  • FIG. 2a is a schematic cross-sectional structural view of an OLED array substrate according to an embodiment of the present disclosure.
  • the organic light emitting diode (OLED) array substrate includes: a substrate substrate 201, a first metal layer 202 disposed on the substrate substrate 201, and a remote substrate disposed on the first metal layer 202.
  • the first metal layer 202 includes a first power trace 205
  • a second The metal layer 204 includes a second power trace 206 that is connected in parallel with the first power trace 205 by a first via structure 207 that extends through the first insulating layer 203.
  • the second metal layer 204 can also include a metal electrode disposed in the same layer as the second power trace 206, which can reduce process steps and reduce process complexity.
  • the second power trace 206 is disposed in the same layer as the gate 208 of the drive transistor.
  • the OLED array substrate includes a display area and a peripheral area other than the display area, wherein the display area is also referred to as an AA (Active Area) area, and is generally used to implement display, and the peripheral area can be used, for example, to set a driving circuit and perform a display panel. Packaging, etc.
  • the first power supply line 205 can be electrically connected to the second power supply line 206.
  • the first power supply line 205 can be electrically connected to the second power supply line 206, such that the first power supply line 205 and the second power supply line 206 are respectively connected at both ends to form a parallel circuit, or the positions at which the first power supply line 205 and the second power supply line 206 are connected to each other may be located in the display area.
  • the first power supply line 205 receives the voltage signal and transmits the voltage signal, and when the voltage signal reaches the second power supply line 206 connected to the first power supply line 205, the second power supply line 206 is transmitted as a voltage signal.
  • the branch circuit and the first power supply line 205 simultaneously transmit a voltage signal, so that the first power supply line 205 and the second power supply line 206 form a parallel circuit, which reduces the electrical signal transmission process.
  • the second power supply line 206 may first receive a voltage signal. When the voltage signal reaches the first power supply line 205 electrically connected to the second power supply line 206, the first power supply line 205 is transmitted as a voltage signal.
  • the branch circuit and the second power supply line 206 simultaneously transmit a voltage signal; or, the first power supply line 205 and the second power supply line 206 simultaneously receive a voltage signal, and the first power supply line 205 and the second power supply line 206 serve as The two branches simultaneously transmit voltage signals.
  • the material of the first metal layer 202 has a resistivity that is less than the resistivity of the material of the second metal layer 204.
  • the metal electrode and the first power supply line 205 formed in the same layer and the same material as the second power supply line 206 can be formed by using different resistivity materials, and the first power supply trace 205 and the second power supply trace 206 are connected in parallel.
  • the problem of immature technology is possible to avoid the problem of large voltage drop when forming a power supply trace by using a metal material such as aluminum having good stability, and when a metal electrode is formed by using a copper alloy having a low resistivity or a metal alloy containing at least one of copper and silver.
  • the material of the first metal layer 202 includes at least one of copper, a copper alloy, silver, and a silver alloy.
  • the material of the second metal layer 204 includes at least one of nickel, molybdenum, niobium, aluminum, titanium, and any combination thereof.
  • the alloy includes a nickel-molybdenum alloy, a nickel-niobium alloy, a tantalum-molybdenum alloy, an aluminum-molybdenum alloy, a titanium-molybdenum alloy, an aluminum-niobium alloy, an aluminum-titanium alloy, a titanium-niobium alloy, a nickel-molybdenum-niobium alloy, or an aluminum-molybdenum-titanium alloy
  • the second power trace 206 is connected in parallel with the first power trace 205 through at least two first via structures 207 extending through the first insulating layer 203, such that the first power trace 205 and the first
  • the parallel connection of the two power traces 206 can further reduce the voltage drop.
  • the plurality of first via structures 207 can be formed in the same patterning process. Compared to forming a first via structure 207, simultaneously forming a plurality of first via structures 207 does not add additional process steps, only Need to choose different masks according to your needs.
  • FIG. 2b is a cross-sectional structural diagram of a second power supply line connected in parallel with a first power supply line according to an embodiment of the present disclosure.
  • the second power supply trace 206 is connected in parallel with the first power supply trace 205 through a first via structure penetrating through the first insulating layer 203.
  • FIG. 3 is a schematic diagram showing a planar structure of an OLED array substrate according to an embodiment of the present disclosure
  • FIG. 4 is a schematic cross-sectional structural view of the OLED array substrate cut along the line A-A' in FIG.
  • the OLED array substrate further includes a data line 210 disposed on the base substrate 201 and a gate line 209 connected to the gate 208, and the gate line 209 and the data line 210 are, for example, Crossing is used to define a region of the pixel unit in which a pixel structure is provided.
  • the pixel structure includes a switching transistor 30, a driving transistor 40, and an OLED device 50 (including a third electrode 501, a fourth electrode 503, and an organic material).
  • the functional layer 502 and the pixel defining layer 504), the gate of the switching transistor 30 and the first electrode of the switching transistor 30 are connected to the gate line 209 and the data line 210, and the second electrode of the switching transistor 30 is connected to the gate of the driving transistor 40;
  • the first and second electrodes of transistor 40 are coupled to first power trace 205, second power trace 206, and OLED device 50.
  • the second power supply line 206 is electrically connected to the first electrode 213 of the driving transistor 40 (ie, the input electrode of the driving transistor 40, such as a source or a drain); the third electrode 501 of the OLED device 50 and the driving transistor 40
  • a third insulating layer 216 (for example, may be a first passivation layer) is disposed therebetween, and the third electrode 501 passes through the third via structure 218 penetrating the third insulating layer 216 and the second electrode 214 of the driving transistor 40 (ie, driving)
  • the output electrode of transistor 40 is electrically connected.
  • the driving transistor is a bottom-gate thin film transistor.
  • the driving transistor 40 includes a gate 208, a gate insulating layer 211 disposed on the gate 208, and is disposed on the gate insulating layer 211.
  • the gate 208 of the driving transistor 40 is disposed in the same layer as the second power supply trace 206; the material of the gate 208 of the driving transistor 40 is the same as the material of the second power supply trace 206, and the gate 208
  • the second power supply traces 206 are disposed on the same layer and spaced apart from each other.
  • the first electrode 213 of the driving transistor 40 is electrically connected to the second power supply line 206 through the second via structure 217 penetrating the second insulating layer 215 and the gate insulating layer 211.
  • the first electrode 213 of the driving transistor 40 and the second power supply line 206 are electrically connected, and the second power supply line 206 is electrically connected to the first power supply line 205, and a three-layer parallel structure can also be formed, thereby further reducing The resistance of the first power trace 205 and the second power trace 206 further reduces the voltage drop.
  • FIG. 5 is a schematic cross-sectional view of an OLED array substrate according to an embodiment of the present disclosure.
  • driving transistors of a plurality of pixel units are arranged side by side, and driving of each pair of adjacent pixel units is provided.
  • a three-layer parallel structure is disposed between the transistors, that is, the first electrode 213 of the driving transistor 40 and the second power supply line 206 are electrically connected, and the second power supply line 206 and the first power supply line 205 are electrically connected to form three layers. Parallel structure.
  • the material of the third electrode 501 in the OLED device 50 may be a transparent conductive material including indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), Gallium zinc oxide (GZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), aluminum zinc oxide (AZO), carbon nanotubes, and the like.
  • the material of the third electrode 501 may also be a metal conductive material including a single metal such as copper (Cu), chromium (Cr), molybdenum (Mo), gold (Au), silver (Ag), and platinum (Pt). Or an alloy material formed of the above metal, for example, a copper chromium alloy (CuCr) or a chromium molybdenum alloy (CrMo).
  • the driving transistor further includes an active layer 212, and the material of the active layer 212 is a transparent conductive material.
  • the material of the active layer 212 is indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), gallium zinc oxide (GZO) zinc oxide (ZnO), indium oxide (In 2 O 3 ). , aluminum zinc oxide (AZO) and carbon nanotubes.
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • IGO indium gallium oxide
  • GZO gallium zinc oxide
  • ZnO zinc oxide
  • In 2 O 3 aluminum zinc oxide
  • AZO aluminum zinc oxide
  • carbon nanotubes carbon nanotubes.
  • the thickness of the third electrode 501 may be 40 to 120 nm, and for example, the thickness of the third electrode 501 is 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, or 120 nm.
  • the material of the fourth electrode 503 in the OLED device 50 includes a single metal such as silver, magnesium, aluminum, lithium, or a magnesium aluminum alloy (MgAl), a lithium aluminum alloy (LiAl), or the like.
  • the thickness of the fourth electrode 503 may be 3 to 30 nm, and for example, the thickness of the fourth electrode 503 is 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, or 30 nm.
  • the pixel defining layer 504 in the OLED device 50 is typically formed of an organic insulating material (eg, an acrylic resin) or an inorganic insulating material (eg, silicon nitride SiN x or silicon oxide SiO x ), the pixel defining layer 504 has the property of being insulating.
  • the pixel defining layer 504 can be regarded as an insulating structure disposed between the third electrode 501 and the fourth electrode 503.
  • the third electrode 501 is an anode
  • the fourth electrode 503 is a cathode
  • the third electrode 501 is a cathode
  • the fourth electrode 503 is an anode
  • the materials and structures of the third electrode 501 and the fourth electrode 503 are only one example in the embodiment of the present disclosure, and the third electrode 501 and the fourth electrode 503 may also be prepared from other materials, according to
  • the material of the third electrode and the fourth electrode can be divided into a single-sided light-emitting array substrate and a double-sided light-emitting array substrate.
  • the array The substrate is a single-sided light-emitting type, and when the materials of the anode and the cathode are both a light-transmitting material and/or a semi-transmissive material, the array substrate is a double-sided light-emitting type.
  • the single-sided light-emitting OLED array substrate depending on the material of the anode and the cathode, it can be further divided into an ejector light type and a bottom light output type.
  • the cathode When the anode is placed close to the substrate, the cathode is away from the substrate The substrate is disposed, and the material of the anode is a light-transmitting conductive material.
  • the OLED array substrate may be referred to as a bottom-emitting type because light is emitted from the anode and then through one side of the substrate.
  • the OLED array substrate when the material of the anode is an opaque conductive material, and the material of the cathode is a transparent or translucent conductive material, the OLED array substrate may be referred to as an ejector optical array because light is emitted from the cathode away from the side of the substrate. Substrate.
  • the relative positions of the anode and the cathode in the above two types of array substrates can also be replaced, and will not be described herein.
  • the display substrate can be referred to as a double-sided light-emitting display substrate when it is emitted through one side of the substrate and on the other hand from the cathode away from the substrate.
  • the anode is disposed away from the substrate, and the cathode is disposed adjacent to the substrate.
  • the organic material functional layer 502 in the OLED device 50 may include a hole transport layer, a light emitting layer, and an electron transport layer, and the organic material functional layer may further include a set in order to improve the efficiency of electron and hole injection into the light emitting layer.
  • the material and size of these organic functional layers can be conventionally designed, and embodiments of the present disclosure are not limited thereto.
  • the fourth electrode 503 of the OLED array substrate may further be provided with a passivation layer 505 and an encapsulation layer 506.
  • the material of the passivation layer 505 may be silicon nitride (SiN x ), silicon oxide (SiO x ), an acrylic resin, or the like.
  • the material of the encapsulation layer 506 includes a single film layer or a composite film layer formed of silicon nitride, silicon oxide or a photosensitive resin.
  • the photosensitive resin may be a polyacrylic resin, a polyimide resin or a polyamide resin. .
  • the driving transistor and the switching transistor provided by the embodiments of the present disclosure may be a bottom gate type structure, a top gate type structure, or a double gate type structure.
  • the driving transistor shown in FIG. 4 is a bottom gate type structure.
  • the top gate and the bottom gate are relative to the positions of the active layer and the gate, that is, the bottom gate is opposite to the base substrate when the gate is close to the substrate and the active layer is away from the substrate.
  • the thin film transistor is a top gate type thin film transistor when the gate is away from the substrate, and the active layer is close to the substrate;
  • the double gate structure includes the gate away from the substrate, and is active The structure of the layer close to the substrate and the gate are close to the substrate, and the active layer is away from the structure of the substrate.
  • the driving transistor is a bottom gate type thin film transistor
  • the second power supply line 206 is disposed between the first power supply line 205 and the first electrode 213 of the driving transistor 40.
  • the driving transistor is a top gate type thin film transistor
  • the first power supply trace may be disposed between the second power supply trace and the first electrode of the driving transistor, and the structure of each layer of the top gate structure and the double gate structure driving transistor may be referred to The related description of the above-described bottom gate type structure will not be described herein.
  • materials of the first insulating layer 203, the second insulating layer 215, and the third insulating layer 216 may include an organic insulating material (for example, an acrylic resin) or an inorganic insulating material (for example, nitriding) Silicon SiN x or silicon oxide SiO x ).
  • an organic insulating material for example, an acrylic resin
  • an inorganic insulating material for example, nitriding
  • materials used as the gate insulating layer 211 include silicon nitride (SiN x ), silicon oxide (SiO x ), aluminum oxide (Al 2 O 3 ), aluminum nitride (AlN), or other suitable materials.
  • the width of the first power trace 205 is greater than the width of the second power trace 206.
  • the relatively small width of the second power supply trace 206 can increase the aperture ratio of the pixel.
  • the relatively large width of the first power supply trace 205 can reduce the resistance of the first power supply trace 205, thereby reducing the voltage drop.
  • the first power supply trace 205 has a planar structure, for example, a flat plate as a whole.
  • the first power trace 205 is a planar electrode structure formed of a metal mesh (rather than a single strip or line), and the planar electrode structure formed by the metal grid includes a plurality of meshes.
  • the planar first power trace can reduce the voltage drop (IR drop), thereby reducing the energy consumption of the OLED array substrate.
  • the first power supply trace of the planar structure means that the power supply trace has a certain size and extension range in the width and length directions of the pixel structure.
  • a planar first power supply line may be disposed correspondingly for each column of pixel structures, so that the plurality of planar first power supply lines may continue to be connected to form an integrated structure, which may make the first
  • the area of the power supply trace is larger, which further reduces the voltage drop of the first power supply trace (IR drop), thereby further reducing the energy consumption of the OLED array substrate.
  • FIG. 6 is a schematic diagram showing a planar structure of a first power supply line disposed in a hollow structure according to an embodiment of the present disclosure.
  • a region of the planar first power supply trace corresponding to the pixel structure, the gate line, and the data line on the OLED array substrate may be disposed as a hollow structure 219.
  • the size of the hollow structure 219 corresponds to the size of the pixel structure, the gate line and the data line, and the size of the hollow structure 219 is larger than the size of the mesh in the metal mesh.
  • the area corresponding to the pixel structure of the first power trace 205 is set to the hollow structure 219 mainly for preventing the metal trace from blocking, which affects the transmittance of the light, that is, in the pixel structure pair.
  • the hollowed-out structure of the area can increase the transmittance of light and make full use of the incident light.
  • the area corresponding to the first power supply line and the gate line and the data line is set to a hollow structure, mainly to prevent the first power supply from going.
  • a capacitance is formed between the line and the gate line and the data line. For example, as shown in FIG.
  • the hollow structure 219 may include a plurality of non-contiguous sub-hollow structures 2191 (ie, a plurality of sub-hollow structures are spaced apart from each other), which is equivalent to dividing the power trace of the planar structure into a plurality of Parallel areas, which can reduce the resistance of the planar power supply traces, thus greatly reducing the voltage drop of the power supply traces.
  • FIG. 7 is a schematic diagram of a 3T1C (3 transistors and 1 capacitor) compensation pixel circuit according to an embodiment of the present disclosure.
  • the compensation pixel circuit is based on a conventional 2T1C pixel circuit to implement an external compensation function.
  • the pixel structure in addition to the switching transistors T1, T2 and the driving transistor T3, the pixel structure further includes a storage capacitor C1, one end of which is electrically connected, for example, to the drain of the switching transistor T1, and One end is electrically connected to the drain of the driving transistor T3.
  • the gate of the switching transistor T1 is for receiving the scan signal G1 and the source is for receiving the data signal DATA; the gate of the switching transistor T2 is for receiving the scan signal G1, and the drain is for outputting the sensing signal to the sensing line SENSE
  • the source is electrically connected to the drain of the driving transistor T2; the gate of the driving transistor T3 is electrically connected to the drain of the switching transistor T1, the source is electrically connected to the power supply voltage VDD; and the anode of the OLED is electrically connected to the drain of the driving transistor T3.
  • the cathode is electrically connected to the power supply voltage VSS.
  • each transistor may be a P-type transistor, but it may also be an N-type transistor, and the driving signal used is changed accordingly.
  • the pixel circuit may also be a 4T2C or the like, and may include a compensation transistor, a reset transistor, and the like in addition to the above-described switching transistor and the driving transistor, which are not limited herein.
  • At least one embodiment of the present disclosure also provides a display device including any of the above OLED array substrates.
  • Other structures in the display device can be found in conventional designs.
  • the display device can be, for example, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like, or any product or component having a display function.
  • FIG. 8 is a flowchart of a method for fabricating an OLED array substrate according to an embodiment of the present disclosure.
  • the preparation method comprises the following steps:
  • Step 101 Providing a substrate.
  • the base substrate may be a glass substrate, a quartz substrate, a plastic substrate, or the like.
  • Step 102 depositing a first metal thin film on the base substrate and patterning the same to form a first metal layer, the first metal layer including a first power supply trace.
  • the material of the first metal layer includes at least one of copper, a copper alloy, silver, and a silver alloy.
  • Step 103 depositing a first insulating film on a side of the first metal layer away from the substrate, and patterning the same to form a first insulating layer.
  • the material of the first insulating layer may comprise an organic insulating material (e.g., acrylic resin) or an inorganic insulating material (e.g., silicon nitride SiN x SiO x or silicon oxide).
  • an organic insulating material e.g., acrylic resin
  • an inorganic insulating material e.g., silicon nitride SiN x SiO x or silicon oxide.
  • Step 104 depositing a second metal film on a side of the first insulating layer away from the substrate, and patterning the same to form a second metal layer, the second metal layer comprising a second power trace, the first The power supply trace is connected in parallel with the second power supply trace through a first via structure extending through the first insulating layer.
  • the second power supply trace is connected in parallel with the first power supply trace through at least two first via structures through the first insulating layer, such that the first power supply trace and the second power supply trace are realized at multiple locations.
  • Parallel connections can further reduce the voltage drop.
  • the plurality of first via structures may be formed in the same patterning process. Compared to forming a first via structure, forming a plurality of first via structures does not add an additional process step, and only needs to be selected according to requirements. Different masks are available.
  • the second metal layer may further include a metal electrode disposed in the same layer as the second power supply trace, which can reduce process steps and reduce process complexity.
  • the second power supply trace is disposed in the same layer as the gate of the drive transistor.
  • the material of the first metal layer has a resistivity lower than that of the material of the second metal layer.
  • the metal electrode and the first power supply trace formed by the same material and the same material as the second power supply trace can be formed by using different resistivity materials, and the first power supply trace and the second power supply trace are connected in parallel to reduce the power supply.
  • the resistance of the trace (including the first power trace and the second power trace), thereby reducing the voltage drop.
  • the material of the second metal layer includes at least one of nickel, molybdenum, niobium, aluminum, titanium, and any alloy thereof.
  • the alloy includes a nickel-molybdenum alloy, a nickel-niobium alloy, a bismuth molybdenum alloy, and an aluminum mo Gold, titanium molybdenum alloy, aluminum tantalum alloy, aluminum titanium alloy, titanium niobium alloy, nickel molybdenum niobium alloy and aluminum molybdenum titanium alloy.
  • the width of the first power supply trace is greater than the width of the second power supply trace.
  • the second power supply trace has a relatively small width to increase the aperture ratio of the pixel.
  • the relatively large width of the first power supply trace can reduce the resistance of the first power supply trace, thereby reducing the voltage drop.
  • the first power trace has a planar structure.
  • the first power trace is a planar electrode structure formed by a metal mesh (rather than a single strip or line), and the planar electrode structure formed by the metal grid includes a plurality of meshes.
  • the planar first power trace can reduce the voltage drop (IR drop), thereby reducing the energy consumption of the OLED array substrate.
  • the first power supply trace of the planar structure means that the power supply trace has a certain size and extension range in the width and length directions of the pixel structure.
  • the preparation method provided by at least one embodiment of the present disclosure further includes forming a driving transistor including a gate, a gate insulating layer, an active layer, a second insulating layer, a first electrode, and a second electrode.
  • the gate of the driving transistor is disposed in the same layer as the second power supply trace, and the gate of the driving transistor and the second power supply trace are formed by the same material in the same patterning process, and the gate and the second power supply are routed. Set apart from each other.
  • the first electrode of the driving transistor (ie, the input electrode of the driving transistor) is electrically connected to the second power supply trace through a second via structure penetrating the second insulating layer and the gate insulating layer.
  • the first electrode of the driving transistor is electrically connected to the second power supply trace
  • the second power supply trace is electrically connected to the first power supply trace to form a three-layer parallel structure, thereby further reducing the first power supply trace.
  • the resistance of the second power supply trace further reduces the voltage drop.
  • the driving transistor when the driving transistor is a bottom gate type thin film transistor, the second power supply trace is disposed between the first power supply trace and the first electrode of the driving transistor.
  • the driving transistor when the driving transistor is a top gate type thin film transistor, the first power supply trace can be disposed between the second power supply trace and the first electrode of the driving transistor, and the structure of each layer of the driving transistor of the top gate type structure can be referred to the bottom gate The related description of the type structure will not be described here.
  • the second power supply trace is electrically connected to the first electrode of the driving transistor through the second via structure of the second insulating layer.
  • OLED organic light emitting diode
  • the electrode of the driving transistor and the second power supply trace are formed by using a metal material such as aluminum having good stability, and a resistivity is low. Copper or silver, or a metal alloy containing at least one of copper and silver to form a first power trace;
  • the first power supply trace and the second power supply trace are connected in parallel by the via structure to reduce the voltage drop, thereby avoiding adopting at the same time.
  • the metal material such as aluminum with good stability forms a large voltage drop when the power supply is formed, and the process is not mature when copper or silver having a low resistivity or a metal alloy containing at least one of copper and silver is used to form a metal electrode. problem.

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Abstract

一种有机发光二极管阵列基板及其制备方法、显示装置，该有机发光二极管阵列基板包括：衬底基板(201)；设置在衬底基板(201)上的第一金属层(202)；设置在第一金属层(202)上的远离衬底基板(201)一侧的第一绝缘层(203)；设置在第一绝缘层(203)上的远离衬底基板(201)一侧的第二金属层(204)；其中，第一金属层(202)包括第一电源走线(205)，第二金属层(204)包括第二电源走线(206)；第二电源走线(206)通过贯穿第一绝缘层(203)的第一过孔结构(207)与第一电源走线(205)并联连接。该阵列基板中第一电源走线和第二电源走线通过第一过孔结构并联连接，可以减小电压降。

Description

有机发光二极管阵列基板及其制备方法、显示装置
本申请要求于2017年6月8日递交的中国专利申请第201710427376.4号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种有机发光二极管阵列基板及其制备方法、显示装置。
背景技术
OLED(Organic Light Emitting Diode，有机发光二极管)显示器是新一代的显示器，与液晶显示器相比，具有自发光，响应速度快以及视角宽等优点，可以用于柔性显示、透明显示和3D显示等。
发明内容
本公开至少一实施例提供一种有机发光二极管阵列基板，该有机发光二极管阵列基板包括：衬底基板；设置在所述衬底基板上的第一金属层；设置在所述第一金属层上的远离所述衬底基板一侧的第一绝缘层；设置在所述第一绝缘层上的远离所述衬底基板一侧的第二金属层；其中，所述第一金属层包括第一电源走线，所述第二金属层包括第二电源走线；所述第二电源走线通过贯穿所述第一绝缘层的第一过孔结构与所述第一电源走线并联连接。
例如，在本公开至少一实施例提供的有机发光二极管阵列基板中，所述第一金属层的材料的电阻率小于所述第二金属层的材料的电阻率。
例如，在本公开至少一实施例提供的有机发光二极管阵列基板中，所述第一金属层的材料包括铜、铜合金、银和银合金中的至少之一；所述第二金属层的材料包括镍、钼、铌、铝、钛及其任意组合形成的合金中的至少之一。
例如，在本公开至少一实施例提供的有机发光二极管阵列基板中，所 述第二电源走线通过贯穿所述第一绝缘层中的至少两个所述第一过孔结构与所述第一电源走线并联连接。
例如，在本公开至少一实施例提供的有机发光二极管阵列基板中，所述第一电源走线的宽度大于所述第二电源走线的宽度。
例如，在本公开至少一实施例提供的有机发光二极管阵列基板中，所述第一电源走线具有面状结构。
例如，本公开至少一实施例提供的有机发光二极管阵列基板还包括像素结构，其中，所述像素结构包括驱动晶体管，所述驱动晶体管包括栅极、栅绝缘层、第二绝缘层和第一电极；所述第一电极通过贯穿所述第二绝缘层和所述栅绝缘层的第二过孔结构与所述第二电源走线电连接。
例如，在本公开至少一实施例提供的有机发光二极管阵列基板中，所述栅极的材料与所述第二电源走线的材料相同，所述栅极与所述第二电源走线位于同一层且相互间隔设置。
例如，在本公开至少一实施例提供的有机发光二极管阵列基板中，所述驱动晶体管还包括有源层，所述有源层的材料为透明导电材料。
例如，在本公开至少一实施例提供的有机发光二极管阵列基板中，所述透明导电材料包括氧化铟锡(ITO)、氧化铟锌(IZO)、氧化铟镓(IGO)、氧化镓锌(GZO)、氧化锌(ZnO)、氧化铟(In2O3)、氧化铝锌(AZO)至少之一。
本公开至少一实施例还提供一种显示装置，包括上述任一有机发光二极管阵列基板。
本公开至少一实施例还提供一种有机发光二极管阵列基板的制备方法，该制备方法包括：提供衬底基板；在所述衬底基板上沉积第一金属薄膜，并对其进行构图工艺以形成第一金属层；在所述第一金属层的远离所述衬底基板的一侧沉积第一绝缘薄膜，并对其进行构图工艺以形成第一绝缘层；在所述第一绝缘层的远离所述衬底基板的一侧沉积第二金属薄膜，并对其进行构图工艺以形成第二金属层；其中，所述第一金属层包括第一电源走线，所述第二金属层包括第二电源走线；所述第二电源走线通过贯穿所述第一绝缘层中的第一过孔结构与所述第一电源走线并联连接。
例如，在本公开至少一实施例提供的制备方法中，所述第一金属层的材料的电阻率小于所述第二金属层的材料的电阻率。
例如，在本公开至少一实施例提供的制备方法中，所述第一电源走线的宽度大于所述第二电源走线的宽度。
例如，本公开至少一实施例提供的制备方法还包括形成像素结构，其中，形成所述像素结构包括形成驱动晶体管，形成所述驱动晶体管包括形成栅极、栅绝缘层、第二绝缘层和第一电极；所述第一电极通过贯穿所述第二绝缘层和所述栅绝缘层的第二过孔结构与所述第二电源走线电连接。
例如，在本公开至少一实施例提供的制备方法中，所述栅极的材料与所述第二电源走线的材料相同，所述栅极与所述第二电源走线设置在同一层且相互间隔设置。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为一种有机发光二极管阵列基板的截面结构示意图；
图2a为本公开一实施例提供的一种有机发光二极管阵列基板的截面结构示意图；
图2b为本公开一实施例提供的一种第二电源走线与第一电源走线并联连接的截面结构示意图；
图3为本公开一实施例提供的一种有机发光二极管阵列基板的平面结构示意图；
图4为图3中沿A-A’剖面线切割形成的有机发光二极管阵列基板的截面结构示意图；
图5为本公开一实施例提供的一种有机发光二极管阵列基板的截面结构示意图；
图6为本公开一实施例提供的一种第一电源走线设置成镂空结构的平面结构示意图；
图7为本公开一实施例提供的一种3T1C像素电路的示意图；以及
图8为本公开一实施例提供的一种有机发光二极管阵列基板的制备方法的流程图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
有机发光二极管(OLED)阵列基板包括多个像素单元，每个像素单元可以包括开关晶体管、驱动晶体管和OLED显示器件。OLED是电流型发光器件，其主要包括阳极、阴极以及形成在阳极和阴极之间的有机材料功能层。OLED的工作原理主要是：有机材料功能层在阳极和阴极形成的电场的驱动下，通过载流子的注入和复合而发光。与OLED的阳极或者阴极电连接的驱动晶体管起着限流的作用，如果驱动晶体管的电极材料的电阻率太大或者电源走线的电阻太大，则电压降会很大，而且该电压降对不同位置处的像素单元的影响不同，从而对显示的均一性产生不利影响。
图1为一种有机发光二极管(OLED)阵列基板的截面结构示意图，如图1所示，该OLED阵列基板包括衬底基板101以及设置在衬底基板101上的驱动晶体管，该OLED阵列基板还包括与该驱动晶体管相连的有机发光二极管(OLED)、存储电容等(未示出)。该驱动晶体管包括栅极102、源极和漏极，电源走线108与栅极102在同一构图工艺中形成，且电源走线108与栅极102具有相同的材料，例如，栅极102和电源走线108的材料均为铝金属材料，该电源走线108与该栅极102设置在同一层且相互间隔。该驱动晶体管还包括设置在栅极102和电源走线108上的栅绝缘层103，设置在栅绝缘 层103上的有源层104，该有源层104上设置有绝缘层105，绝缘层105上设置有第一源漏电极106(例如源极或漏极)和第二源漏电极107(对应地，例如漏极或源极)。在一对相邻的像素单元的驱动晶体管中，一个驱动晶体管的第一源漏电极106和另一个驱动晶体管的第一源漏电极106相连接，且该相连接的一个驱动晶体管的第一源漏电极106和另一个驱动晶体管的第一源漏电极106通过贯穿绝缘层105和栅绝缘层103中的过孔结构与电源走线108电连接。
目前，采用稳定性好的铝金属材料制备驱动晶体管的电极的工艺较为成熟，但是铝金属的电阻率较高，采用铝金属材料形成驱动晶体管的电极(例如，栅极、第一源漏电极和第二源漏电极等)和电源走线时，产生的电压降较大，该较大的电压降会对显示器件显示的均一性产生不利影响。通常，将铝金属电极或者铝金属走线的宽度值设置得很大来减小电压降，但宽度较大的电极或者金属走线会降低开口率，而且还会增加生产成本。
本公开的发明人注意到，铜或者银金属材料的电阻率较低，采用铜金属材料或者银金属材料形成驱动晶体管的电极(例如，栅极、第一源漏电极和第二源漏电极)和电源走线时，产生的电压降较小，但是铜金属和银金属易被氧化，而且在对铜金属材料或者银金属材料形成的金属膜层进行构图的过程中，刻蚀液对铜金属材料和银金属材料的刻蚀速率较低，且刻蚀程度不好控制，这样会使形成的铜金属电极或者银金属电极的均一性降低。基于上述分析，本公开的发明人发现，如果驱动晶体管的电极采用铝金属材料制备，在制备驱动晶体管的栅极的工艺过程中形成第二电源走线，采用铜金属材料形成第一电源走线，第一电源走线和第二电源走线通过过孔结构连接则可以减小电源走线(包括第一电源走线和第二电源走线)的电阻，从而整体上可以减小电压降，还可以同时避免采用稳定性较好的铝等金属材料形成电源走线时电压降较大的问题，以及采用电阻率较低的铜或者银，或者含有铜和银至少之一的金属合金形成金属电极时工艺不成熟的问题。
本公开至少一实施例提供一种有机发光二极管(OLED)阵列基板，该有机发光二极管(OLED)阵列基板包括：衬底基板；设置在该衬底基板上的第一金属层；设置在第一金属层上的远离衬底基板一侧的第一绝缘层；设置在第一绝缘层上的远离衬底基板一侧的第二金属层；其中，该第 一金属层包括第一电源走线，第二金属层包括第二电源走线；第二电源走线通过贯穿第一绝缘层的第一过孔结构与第一电源走线并联连接。
本公开的实施例通过采用稳定性较好的铝等金属材料形成驱动晶体管的电极和第二电源走线，采用电阻率较低的铜或者银，或者含有铜和银至少之一的金属合金形成第一电源走线，且第一电源走线和第二电源走线通过过孔结构并联连接的方式以减小电压降。这样可以同时避免采用稳定性较好的铝等金属材料形成电源走线时电压降较大的问题和采用电阻率较低的铜或者银，或者含有铜和银至少之一的金属合金形成金属电极时工艺不成熟的问题。
本公开至少一实施例提供一种有机发光二极管(OLED)阵列基板，图2a为本公开一实施例提供的一种OLED阵列基板的截面结构示意图。例如，如图2a所示，该有机发光二极管(OLED)阵列基板包括：衬底基板201，设置在该衬底基板201上的第一金属层202、设置在第一金属层202的远离衬底基板201一侧的第一绝缘层203，和设置在第一绝缘层203的远离衬底基板201一侧的第二金属层204，该第一金属层202包括第一电源走线205，第二金属层204包括第二电源走线206，该第二电源走线206通过贯穿第一绝缘层203中的第一过孔结构207与第一电源走线205并联连接。该第二金属层204还可以包括与第二电源走线206同层设置的金属电极，这样可以减少工艺步骤，降低工艺过程的复杂性。示例性地，在图2a中，第二电源走线206与驱动晶体管的栅极208同层设置。
例如，该OLED阵列基板包括显示区域和显示区域之外的外围区域，其中显示区域又称为AA(Active Area)区，一般用于实现显示，外围区域例如可用于设置驱动电路、进行显示面板的封装等。例如，在外围区域，第一电源走线205可以和第二电源走线206电连接，在显示区域，第一电源走线205可以和第二电源走线206电连接，这样第一电源走线205和第二电源走线206在两端分别连接以形成并联电路，或者第一电源走线205和第二电源走线206彼此连接的位置可以都位于显示区域中。当第一电源走线205接受电压信号并将电压信号进行传递，且当电压信号到达和第一电源走线205连接的第二电源走线206时，第二电源走线206作为电压信号传递的支路与第一电源走线205同时传递电压信号，这样相当于第一电源走线205和第二电源走线206形成并联电路，降低了电信号传递过程中的 电阻；或者，也可以是第二电源走线206先接受电压信号，当电压信号到达和第二电源走线206电连接的第一电源走线205时，第一电源走线205作为电压信号传递的支路与第二电源走线206同时传递电压信号；再或者，第一电源走线205和第二电源走线206同时接受电压信号，第一电源走线205和第二电源走线206作为两条支路同时传递电压信号。
例如，第一金属层202的材料的电阻率小于第二金属层204的材料的电阻率。这样，和第二电源走线206同层同材料形成的金属电极和第一电源走线205可以采用不同电阻率的材料形成，且第一电源走线205和第二电源走线206并联连接，可以同时避免采用稳定性较好的铝等金属材料形成电源走线时电压降较大的问题和采用电阻率较低的铜或者银，或者含有铜和银至少之一的金属合金形成金属电极时工艺不成熟的问题。
例如，该第一金属层202的材料包括铜、铜合金、银和银合金中的至少之一。
例如，该第二金属层204的材料包括镍、钼、铌、铝、钛及其任意组合形成的合金中的至少之一。例如，该合金包括镍钼合金、镍铌合金、铌钼合金、铝钼合金、钛钼合金、铝铌合金、铝钛合金、钛铌合金、镍钼铌合金或者铝钼钛合金。
例如，第二电源走线206通过贯穿第一绝缘层203中的至少两个第一过孔结构207与第一电源走线205并联连接，这样通过在多处实现第一电源走线205和第二电源走线206的并联连接可以进一步地减小电压降。例如，该多个第一过孔结构207可以在同一构图工艺中形成，相比于形成一个第一过孔结构207，同时形成多个第一过孔结构207不会增加额外的工艺步骤，只需要根据需求选择不同的掩膜板即可。
例如，图2b为本公开一实施例提供的一种第二电源走线与第一电源走线并联连接的截面结构示意图。如图2b所示，第二电源走线206通过贯穿第一绝缘层203中的第一过孔结构与第一电源走线205并联连接。
例如，图3为本公开一实施例提供的一种OLED阵列基板的平面结构示意图，图4为图3中沿A-A’剖面线切割形成的OLED阵列基板的截面结构示意图。
如图3和图4所示，该OLED阵列基板还包括设置在衬底基板201上的数据线210和与栅极208连接的栅线209，栅线209和数据线210例如 交叉用于限定像素单元的区域，该区域内设置有像素结构，示例性的，该像素结构包括开关晶体管30、驱动晶体管40和OLED器件50(包括第三电极501、第四电极503、有机材料功能层502和像素界定层504)，开关晶体管30的栅极和开关晶体管30的第一电极连接到栅线209和数据线210，开关晶体管30的第二电极连接驱动晶体管40的栅极；驱动晶体管40的第一电极和第二电极连接到第一电源走线205、第二电源走线206和OLED器件50。例如，第二电源走线206与驱动晶体管40的第一电极213(即驱动晶体管40的输入电极，例如为源极或者漏极)电连接；OLED器件50的第三电极501与驱动晶体管40之间设置有第三绝缘层216(例如，可以是第一钝化层)，第三电极501通过贯穿第三绝缘层216的第三过孔结构218与驱动晶体管40的第二电极214(即驱动晶体管40的输出电极)电连接。
例如，如图4所示，以驱动晶体管为底栅型薄膜晶体管为例加以说明，该驱动晶体管40包括栅极208、设置在栅极208上的栅绝缘层211、设置在栅绝缘层211上的有源层212、设置在有源层212上的第二绝缘层215，设置在第二绝缘层215上的第一电极213和第二电极214。
例如，如图4所示，驱动晶体管40的栅极208与第二电源走线206设置在同一层；驱动晶体管40的栅极208的材料与第二电源走线206的材料相同，栅极208与第二电源走线206设置在同一层且相互间隔设置。
例如，如图4所示，驱动晶体管40的第一电极213通过贯穿第二绝缘层215和栅绝缘层211的第二过孔结构217与第二电源走线206电连接。这样，驱动晶体管40的第一电极213和第二电源走线206电连接，第二电源走线206和第一电源走线205电连接，还可以形成三层并联的结构，从而进一步地减小第一电源走线205和第二电源走线206的电阻，进一步地减小电压降。
例如，图5为本公开一实施例提供的一种OLED阵列基板的截面结构示意图，从图5中可以看出，多个像素单元的驱动晶体管并排设置，每一对相邻的像素单元的驱动晶体管之间设置有一个上述三层并联结构，即驱动晶体管40的第一电极213和第二电源走线206电连接，第二电源走线206和第一电源走线205电连接形成的三层并联结构。
例如，如图4所示，OLED器件50中第三电极501的材料可以为透明导电材料，该透明导电材料包括氧化铟锡(ITO)、氧化铟锌(IZO)、氧化 铟镓(IGO)、氧化镓锌(GZO)、氧化锌(ZnO)、氧化铟(In2O3)、氧化铝锌(AZO)和碳纳米管等。第三电极501的材料还可以为金属导电材料，该金属导电材料包括铜(Cu)、铬(Cr)、钼(Mo)、金(Au)、银(Ag)以及铂(Pt)等单金属或者上述金属形成的合金材料，例如，铜铬合金(CuCr)或者铬钼合金(CrMo)等。
例如，该驱动晶体管还包括有源层212，该有源层212的材料为透明导电材料。
例如，有源层212的材料为氧化铟锡(ITO)、氧化铟锌(IZO)、氧化铟镓(IGO)、氧化镓锌(GZO)氧化锌(ZnO)、氧化铟(In2O3)、氧化铝锌(AZO)和碳纳米管等。
例如，第三电极501的厚度可以为40～120nm，例如，第三电极501的厚度为40nm、50nm、60nm、70nm、80nm、90nm、100nm、110nm或者120nm。
例如，OLED器件50中第四电极503的材料包括银、镁、铝、锂等单金属或者镁铝合金(MgAl)、锂铝合金(LiAl)等。
例如，第四电极503的厚度可以为3～30nm，例如，第四电极503的厚度为5nm、10nm、15nm、20nm、25nm或者30nm。
例如，在图4中，OLED器件50中像素界定层504通常采用有机绝缘材料(例如，丙烯酸类树脂)或者无机绝缘材料(例如，氮化硅SiNx或者氧化硅SiOx)形成，像素界定层504具有绝缘的性质。在图4中，像素界定层504可以被看作设置在第三电极501和第四电极503之间的绝缘结构。
例如，第三电极501为阳极，第四电极503为阴极，或者，第三电极501为阴极，第四电极503为阳极。
需要说明的是，上述第三电极501和第四电极503的材料和结构只是本公开的实施例中的一个示例，第三电极501和第四电极503还可以由其他的材料制备而成，根据第三电极和第四电极的材料的不同，可以分为单面出光型阵列基板和双面出光型阵列基板，当阳极和阴极中一个电极的材料为不透光或半透光材料时，阵列基板为单面出光型，当阳极和阴极的材料均为透光材料和/或半透光材料时，该阵列基板为双面出光型。
对于单面出光型OLED阵列基板，根据阳极和阴极的材料的不同，又可以分为顶出光型和底出光型。当阳极靠近衬底基板设置，阴极远离衬底 基板设置，且阳极的材料为透光导电材料，阴极的材料为不透光导电材料时，由于光从阳极、再经衬底基板的一侧出射，则该OLED阵列基板可以称为底出光型阵列基板；当阳极的材料为不透光导电材料，阴极的材料为透明或半透明导电材料时，由于光从阴极远离衬底基板一侧出射，则该OLED阵列基板可以称为顶出光型阵列基板。也可以将上述两种类型的阵列基板中的阳极和阴极的相对位置进行替换，在此不再赘述。
对于双面出光型显示基板，当阳极靠近衬底基板设置，阴极远离衬底基板设置，且阳极和阴极的材料均为透光导电和/或半透光材料时，由于光一方面从阳极、再经衬底基板的一侧出射，另一方面从阴极远离衬底基板一侧出射，则该显示基板可以称为双面出光型显示基板。这里，也可以是阳极远离衬底基板设置，阴极靠近衬底基板设置。
例如，该OLED器件50中有机材料功能层502可以包括：空穴传输层、发光层和电子传输层，为了能够提高电子和空穴注入发光层的效率，该有机材料功能层还可以包括设置在阴极与电子传输层之间的电子注入层，以及设置在阳极与空穴传输层之间的空穴注入层等有机功能层。这些有机功能层的材料以及尺寸等可以采用常规设计，本公开的实施例对此不作限制。
另外，由于水、氧气等对阴极、有机材料功能层的性能的影响较大，如图4所示，该OLED阵列基板的第四电极503上还可以设置有钝化层505和封装层506。
例如，该钝化层505的材料可以为氮化硅(SiNx)、氧化硅(SiOx)以及丙烯酸类树脂等。
例如，封装层506的材料包括氮化硅、氧化硅或者感光树脂形成的单一膜层或者复合膜层，例如，感光树脂可以为聚丙烯酸类树脂、聚酰亚胺类树脂或者聚酰胺类树脂等。
例如，本公开的实施例提供的驱动晶体管和开关晶体管可以为底栅型结构、顶栅型结构或者双栅型结构。例如，图4所示的驱动晶体管为底栅型结构。顶栅、底栅是相对于有源层和栅极的位置而定的，即相对于衬底基板，当栅极靠近衬底基板，有源层远离衬底基板时，该薄膜晶体管为底栅型薄膜晶体管；当栅极远离衬底基板，有源层靠近衬底基板时，该薄膜晶体管为顶栅型薄膜晶体管；双栅型结构同时包括栅极远离衬底基板，有源 层靠近衬底基板的结构和栅极靠近衬底基板，有源层远离衬底基板的结构。
例如，如图4所示，该驱动晶体管为底栅型薄膜晶体管，第二电源走线206设置在第一电源走线205和驱动晶体管40的第一电极213之间。当驱动晶体管为顶栅型薄膜晶体管时，第一电源走线可以设置在第二电源走线和驱动晶体管的第一电极之间，顶栅结构和双栅结构的驱动晶体管的各层结构可以参见上述底栅型结构的相关描述，在此不再赘述。
例如，在本公开的实施例中，第一绝缘层203、第二绝缘层215和第三绝缘层216的材料可以包括有机绝缘材料(例如，丙烯酸类树脂)或者无机绝缘材料(例如，氮化硅SiNx或者氧化硅SiOx)。
例如，被用作栅绝缘层211的材料包括氮化硅(SiNx)、氧化硅(SiOx)、氧化铝(Al2O3)、氮化铝(AlN)或其他适合的材料。
例如，该第一电源走线205的宽度大于第二电源走线206的宽度。第二电源走线206的宽度相对较小可以提高像素的开口率，第一电源走线205的宽度相对较大可以减小第一电源走线205的电阻，进而减小电压降。
例如，第一电源走线205具有面状结构，例如整体上呈平板状。例如，该第一电源走线205为由金属网格形成的面状电极结构(而非单个条状或线状)，该金属网格形成的面状电极结构包括多个网孔。该面状的第一电源走线可以降低电压降(IR drop)，从而可以降低OLED阵列基板的能耗。需要说明的是，面状结构的第一电源走线是指电源走线在像素结构的宽度和长度方向上均有一定的尺寸和延伸范围。
例如，在一个示例中，可以为每一列像素结构对应设置一条面状的第一电源走线，这样可以继续将多条面状的第一电源走线相连，形成一体的结构，可以使得第一电源走线的面积更大，进而使得第一电源走线的电压降(IR drop)进一步降低，从而可以进一步减少OLED阵列基板的能耗。
例如，图6为本公开一实施例提供的一种第一电源走线设置成镂空结构的平面结构示意图。如图6所示，在一个示例中，面状的第一电源走线的与OLED阵列基板上的像素结构、栅线和数据线对应的区域可以设置成镂空结构219。需要说明的是，该镂空结构219的尺寸与像素结构、栅线和数据线的尺寸相对应，该镂空结构219的尺寸大于上述金属网格中网孔的尺寸。例如，第一电源走线205与像素结构对应的区域设置成镂空结构219主要是为了防止金属走线遮光，影响光线的透过率，即在像素结构对 应的区域设置镂空结构可以增大光线的透过率，对入射光线进行充分的利用；第一电源走线与栅线、数据线对应的区域设置成镂空结构，主要是为了防止第一电源走线与栅线、数据线之间形成电容。例如，如图6所示，该镂空结构219可以包括多个非连续的子镂空结构2191(即多个子镂空结构彼此间间隔开)，这样相当于把面状结构的电源走线分割成多个并联的区域，这样可以减小面状电源走线的电阻，从而可以大幅度的减小电源走线的电压降。
例如，图7为本公开一实施例提供的一种3T1C(3个晶体管1个电容)补偿像素电路的示意图。该补偿像素电路基于传统的2T1C像素电路以实现外部补偿功能。结合图4和图7可以看出，除了开关晶体管T1、T2和驱动晶体管T3之外，该像素结构还包括存储电容C1，该存储电容C1的一端例如与开关晶体管T1的漏极电连接，另一端与驱动晶体管T3的漏极电连接。例如，开关晶体管T1的栅极用于接受扫描信号G1而源极用于接收数据信号DATA；开关晶体管T2的栅极用于接受扫描信号G1，漏极用于向感测线SENSE输出感测信号，源极与驱动晶体管T2的漏极电连接；驱动晶体管T3的栅极与开关晶体管T1的漏极电连接，源极与电源电压VDD电连接；OLED的阳极与驱动晶体管T3的漏极电连接，而阴极与电源电压VSS电连接。在上述像素电路中，各晶体管可以为P型晶体管，但也可以为N型晶体管，所采用的驱动信号则进行相应的改变。例如，在本公开的至少一个实施例中，像素电路还可以为4T2C等结构，除上述开关晶体管和驱动晶体管之外，还可以包括补偿晶体管、复位晶体管等，在此不做限制。
本公开至少一实施例还提供一种显示装置，该显示装置包括上述任一OLED阵列基板。显示装置中的其他结构可参见常规设计。该显示装置例如可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开至少一实施例还提供一种有机发光二极管(OLED)阵列基板的制备方法，例如，图8为本公开一实施例提供的一种OLED阵列基板的制备方法的流程图，如图8所示，该制备方法包括如下步骤：
步骤101、提供衬底基板。
例如，该衬底基板可以为玻璃基板、石英基板以及塑料基板等。
步骤102、在衬底基板上沉积第一金属薄膜，并对其进行构图工艺以形成第一金属层，该第一金属层包括第一电源走线。
例如，该第一金属层的材料包括铜、铜合金、银、银合金中的至少之一。
步骤103、在第一金属层的远离衬底基板的一侧沉积第一绝缘薄膜，并对其进行构图工艺以形成第一绝缘层。
例如，该第一绝缘层的材料可以包括有机绝缘材料(例如，丙烯酸类树脂)或者无机绝缘材料(例如，氮化硅SiNx或者氧化硅SiOx)。
步骤104、在第一绝缘层的远离衬底基板的一侧沉积第二金属薄膜，并对其进行构图工艺以形成第二金属层，该第二金属层包括第二电源走线，该第一电源走线通过贯穿第一绝缘层中的第一过孔结构与第二电源走线并联连接。
例如，第二电源走线通过贯穿第一绝缘层中的至少两个第一过孔结构与第一电源走线并联连接，这样通过在多处实现第一电源走线和第二电源走线的并联连接可以进一步地减少电压降。例如，该多个第一过孔结构可以在同一构图工艺中形成，相比于形成一个第一过孔结构，形成多个第一过孔结构不会增加额外的工艺步骤，只需要根据需求选择不同的掩膜板即可。
例如，该第二金属层还可以包括与第二电源走线同层设置的金属电极，这样可以减少工艺步骤，降低工艺过程的复杂性。示例性地，第二电源走线与驱动晶体管的栅极同层设置。
例如，在本公开至少一实施例提供的制备方法中，该第一金属层的材料的电阻率小于该第二金属层的材料的电阻率。这样，和第二电源走线同层同材料形成的金属电极和第一电源走线可以采用不同电阻率的材料形成，将第一电源走线和第二电源走线并联连接，可以减小电源走线(包括第一电源走线和第二电源走线)的电阻，进而减小电压降。同时避免采用稳定性较好的铝等金属材料形成电源走线时电压降较大的问题和采用电阻率较低的铜或者银，或者含有铜和银至少之一的金属合金形成金属电极时工艺不成熟的问题。
例如，该第二金属层的材料包括镍、钼、铌、铝、钛和其任意合金中的至少之一。例如，该合金包括镍钼合金、镍铌合金、铌钼合金、铝钼合 金、钛钼合金、铝铌合金、铝钛合金、钛铌合金、镍钼铌合金和铝钼钛合金。
例如，在本公开的实施例提供的制备方法中，第一电源走线的宽度大于第二电源走线的宽度。
例如，第二电源走线的宽度相对较小可以提高像素的开口率，第一电源走线的宽度相对较大可以减小第一电源走线的电阻，进而减小电压降。
例如，第一电源走线具有面状结构。例如，该第一电源走线为由金属网格形成的面状电极结构(而非单个条状或线状)，该金属网格形成的面状电极结构包括多个网孔。该面状的第一电源走线可以降低电压降(IR drop)，从而可以降低OLED阵列基板的能耗。需要说明的是，面状结构的第一电源走线是指电源走线在像素结构的宽度和长度方向上均有一定的尺寸和延伸范围。
例如，本公开至少一实施例提供的制备方法还包括形成驱动晶体管，该驱动晶体管包括栅极、栅绝缘层、有源层、第二绝缘层、第一电极和第二电极。
例如，驱动晶体管的栅极与第二电源走线设置在同一层，驱动晶体管的栅极与第二电源走线采用相同的材料在相同的构图工艺中形成，且栅极与第二电源走线相互间隔设置。
例如，驱动晶体管的第一电极(即驱动晶体管的输入电极)通过贯穿第二绝缘层和栅绝缘层的第二过孔结构与第二电源走线电连接。这样，驱动晶体管的第一电极和第二电源走线电连接，第二电源走线和第一电源走线电连接，以形成三层并联的结构，从而进一步地减小了第一电源走线和第二电源走线的电阻，进一步地减小了电压降。
例如，在本公开至少一实施例提供的OLED阵列基板中，当驱动晶体管为底栅型薄膜晶体管时，第二电源走线设置在第一电源走线和驱动晶体管的第一电极之间。当驱动晶体管为顶栅型薄膜晶体管时，第一电源走线可以设置在第二电源走线和驱动晶体管的第一电极之间，顶栅型结构的驱动晶体管的各层结构可以参见上述底栅型结构的相关描述，在此不再赘述。
例如，在本公开至少一实施例提供的制备方法中，该第二电源走线通过第二绝缘层的第二过孔结构与驱动晶体管的第一电极电连接。
本公开至少一实施例提供的一种有机发光二极管(OLED)阵列基板 及其制备方法和显示装置具有以下至少一项有益效果：
(1)在公开至少一实施例提供的有机发光二极管(OLED)阵列基板中，通过采用稳定性较好的铝等金属材料形成驱动晶体管的电极和第二电源走线，采用电阻率较低的铜或者银，或者含有铜和银至少之一的金属合金形成第一电源走线；
(2)在公开至少一实施例提供的有机发光二极管(OLED)阵列基板中，第一电源走线和第二电源走线通过过孔结构并联连接的方式来减小电压降，以同时避免采用稳定性较好的铝等金属材料形成电源走线时电压降较大的问题和采用电阻率较低的铜或者银，或者含有铜和银至少之一的金属合金形成金属电极时工艺不成熟的问题。
有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (16)

  1. 一种有机发光二极管阵列基板，包括：
    衬底基板；
    设置在所述衬底基板上的第一金属层；
    设置在所述第一金属层上的远离所述衬底基板一侧的第一绝缘层；
    设置在所述第一绝缘层上的远离所述衬底基板一侧的第二金属层；其中，
    所述第一金属层包括第一电源走线，所述第二金属层包括第二电源走线；
    所述第二电源走线通过贯穿所述第一绝缘层的第一过孔结构与所述第一电源走线并联连接。
  2. 根据权利要求1所述的有机发光二极管阵列基板，其中，所述第一金属层的材料的电阻率小于所述第二金属层的材料的电阻率。
  3. 根据权利要求2所述的有机发光二极管阵列基板，其中，所述第一金属层的材料包括铜、铜合金、银和银合金中的至少之一；
    所述第二金属层的材料包括镍、钼、铌、铝、钛及其任意组合形成的合金中的至少之一。
  4. 根据权利要求1所述的有机发光二极管阵列基板，其中，所述第二电源走线通过贯穿所述第一绝缘层中的至少两个所述第一过孔结构与所述第一电源走线并联连接。
  5. 根据权利要求1～4中任一项所述的有机发光二极管阵列基板，其中，所述第一电源走线的宽度大于所述第二电源走线的宽度。
  6. 根据权利要求5所述的有机发光二极管阵列基板，其中，所述第一电源走线具有面状结构。
  7. 根据权利要求6所述的有机发光二极管阵列基板，还包括像素结构，其中，所述像素结构包括驱动晶体管，所述驱动晶体管包括栅极、栅绝缘层、第二绝缘层和第一电极；所述第一电极通过贯穿所述第二绝缘层和所述栅绝缘层的第二过孔结构与所述第二电源走线电连接。
  8. 根据权利要求7所述的有机发光二极管阵列基板，其中，所述栅极的材料与所述第二电源走线的材料相同，所述栅极与所述第二电源走线 位于同一层且相互间隔设置。
  9. 根据权利要求7所述的有机发光二极管阵列基板，其中，所述驱动晶体管还包括有源层，所述有源层的材料为金属氧化物材料。
  10. 根据权利要求9所述的有机发光二极管阵列基板，其中，所述金属氧化物材料包括氧化铟锡(ITO)、氧化铟锌(IZO)、氧化铟镓(IGO)、氧化镓锌(GZO)、氧化锌(ZnO)、氧化铟(In2O3)、氧化铝锌(AZO)至少之一。
  11. 一种显示装置，包括权利要求1～10中任一项所述的有机发光二极管阵列基板。
  12. 一种有机发光二极管阵列基板的制备方法，包括：
    提供衬底基板；
    在所述衬底基板上沉积第一金属薄膜，并对其进行构图工艺以形成第一金属层；
    在所述第一金属层的远离所述衬底基板的一侧沉积第一绝缘薄膜，并对其进行构图工艺以形成第一绝缘层；
    在所述第一绝缘层的远离所述衬底基板的一侧沉积第二金属薄膜，并对其进行构图工艺以形成第二金属层；其中，
    所述第一金属层包括第一电源走线，所述第二金属层包括第二电源走线；
    所述第二电源走线通过贯穿所述第一绝缘层中的第一过孔结构与所述第一电源走线并联连接。
  13. 根据权利要求12所述的制备方法，其中，所述第一金属层的电阻率小于所述第二金属层的电阻率。
  14. 根据权利要求12或13所述的制备方法，其中，所述第一电源走线的宽度大于所述第二电源走线的宽度。
  15. 根据权利要求14所述的制备方法，还包括形成像素结构，其中，形成所述像素结构包括形成驱动晶体管，形成所述驱动晶体管包括形成栅极、栅绝缘层、第二绝缘层和第一电极；所述第一电极通过贯穿所述第二绝缘层和所述栅绝缘层的第二过孔结构与所述第二电源走线电连接。
  16. 根据权利要求15所述的制备方法，其中，所述栅极的材料与所述第二电源走线的材料相同，所述栅极与所述第二电源走线位于同一层且 相互间隔设置。
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