WO2018227456A1 - 噪声整形电路与三角积分数模转换器 - Google Patents

噪声整形电路与三角积分数模转换器 Download PDF

Info

Publication number
WO2018227456A1
WO2018227456A1 PCT/CN2017/088388 CN2017088388W WO2018227456A1 WO 2018227456 A1 WO2018227456 A1 WO 2018227456A1 CN 2017088388 W CN2017088388 W CN 2017088388W WO 2018227456 A1 WO2018227456 A1 WO 2018227456A1
Authority
WO
WIPO (PCT)
Prior art keywords
filter
shaping circuit
digital
noise shaping
noise
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2017/088388
Other languages
English (en)
French (fr)
Inventor
王文祺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen Goodix Technology Co Ltd
Original Assignee
Shenzhen Goodix Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen Goodix Technology Co Ltd filed Critical Shenzhen Goodix Technology Co Ltd
Priority to EP17800989.0A priority Critical patent/EP3447922A4/en
Priority to KR1020177036107A priority patent/KR102096294B1/ko
Priority to PCT/CN2017/088388 priority patent/WO2018227456A1/zh
Priority to CN201780000513.4A priority patent/CN109690955A/zh
Priority to US15/822,190 priority patent/US10084474B1/en
Publication of WO2018227456A1 publication Critical patent/WO2018227456A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M3/368—Continuously compensating for, or preventing, undesired influence of physical parameters of noise other than the quantisation noise already being shaped inherently by delta-sigma modulators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/50—Digital/analogue converters using delta-sigma modulation as an intermediate step
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/412—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution
    • H03M3/414—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having multiple quantisers arranged in cascaded loops, each of the second and further loops processing the quantisation error of the loop preceding it, i.e. multiple stage noise shaping [MASH] type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/412—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution
    • H03M3/414—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having multiple quantisers arranged in cascaded loops, each of the second and further loops processing the quantisation error of the loop preceding it, i.e. multiple stage noise shaping [MASH] type
    • H03M3/416—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having multiple quantisers arranged in cascaded loops, each of the second and further loops processing the quantisation error of the loop preceding it, i.e. multiple stage noise shaping [MASH] type all these quantisers being multiple bit quantisers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/436—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type
    • H03M3/438—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type the modulator having a higher order loop filter in the feedforward path

Definitions

  • the present application relates to a noise shaping circuit and a triangular integral digital-to-analog converter, and more particularly to a noise shaping circuit and a triangular integral digital-to-analog converter capable of reducing noise energy.
  • Oversampling Triangulation (Sigma Delta, ⁇ ) modulator (Modulator) is currently the most suitable for high resolution (Resolution) analog-to-digital converter (ADC) or digital-to-analog converter (Digital-to-Analog Convertor, DAC).
  • ADC analog-to-digital converter
  • DAC Digital-to-Analog Convertor
  • a triangular integral digital-to-analog converter as an example, it includes an upsampling circuit, a filter, a quantizer, a digital-to-analog converter, and a low-pass filter.
  • the oversampling ratio can be increased, or the order of the filter can be increased, or even the number of bits of the quantizer can be increased.
  • Increasing the oversampling rate, while accelerating the sampling frequency, has the disadvantage of increasing power consumption.
  • Increasing the filter order results in an increase in the noise energy of the out-of-band noise, resulting in a significant increase in the cost of the back-end analog low-pass filter (Analog LPF).
  • the low-pass filter is generally composed of an operational amplifier and a resistor capacitor. Since the noise is proportional to the resistance in the low-pass filter, if the signal-to-noise ratio (SNR) is reached, the resistance of the resistor needs to be very high. Small, however, in order to maintain the angular frequency of the low-pass filter, the low-pass filter requires a large capacitance and makes the circuit area too large.
  • SNR signal-to-noise ratio
  • the present application provides a noise shaping circuit including a first modulating unit for generating a first digital output signal according to a first digital input signal, the first modulating unit comprising: a first filter, Having a first conversion function; and a first quantizer coupled to the first filter; a first subtractor coupled to the input and output of the first quantizer for generating a first quantization noise And a second modulating unit configured to generate a second digital output signal according to the second digital input signal, the second digital input signal is related to the first quantization noise, and the second modulating unit comprises: a second filter Having a second conversion function; and a second quantizer coupled to the second filter; wherein the noise shaping circuit generates an overall simulation based on the first digital output signal and the second digital output signal output signal.
  • the noise shaping circuit includes a third filter having a third conversion function coupled to the second modulation unit for generating a filtering result; wherein the noise shaping circuit is configured according to the first number And outputting the signal and the filtering result to generate the overall analog output signal.
  • the noise shaping circuit includes a fourth filter having a fourth transfer function coupled between the first subtractor and the second modulation unit for using the first quantization noise according to the first quantization noise. Generating the second digital input signal.
  • the fourth transfer function is related to the first transfer function and the third transfer function.
  • the fourth transfer function is related to a reciprocal of the third transfer function.
  • the third filter has a DC gain, the DC gain being less than one.
  • the third filter is a high pass filter.
  • the third filter includes an operational amplifier including a first input end and an output end; a first resistor coupled between the first input end and the output end of the operational amplifier, having a first a resistor; and a second resistor having a second resistor; wherein the capacitor and the second resistor are coupled to the first input terminal and the second modulation unit of the operational amplifier
  • the second resistance value is a multiple of the first resistance value, and the multiple is a reciprocal of the DC gain of the third filter.
  • the noise shaping circuit includes a first digital to analog converter coupled to the first modulation unit for converting the first digital output signal into a first analog output signal; and a second digital analog a converter coupled between the second modulation unit and the third filter for converting the second digital output signal into a second analog output signal; wherein the third filter is The second analog output signal is generated to generate the filtering result; wherein the noise shaping circuit outputs the overall analog output signal as a sum of the first analog output signal and the filtering result.
  • the first filtering order of the first filter is greater than or equal to the second filtering order of the second filter.
  • the present application further provides a delta-sigma digital-to-analog converter including an up-sampling circuit for generating a first digital input signal; and a noise shaping circuit including a first modulating unit for generating a first digital input signal a digital output signal, the first modulating unit includes: a first filter having a first transfer function; and a first quantizer coupled to the first filter; a first subtractor coupled to the An input end and an output end of the first quantizer for generating a first quantization noise; and a second modulation unit for generating a second digital output signal according to the second digital input signal, wherein the second digital input signal is related to The first quantization unit, the second modulation unit includes: a second filter having a second conversion function; and a second quantizer coupled to the second filter; wherein the noise shaping circuit is The first digital output signal and the second digital output signal produce an overall analog output signal.
  • the present application utilizes two modulation units and an analog high-pass filter to form a post-shaping noise spectrum with different slopes, which has the advantages of reducing noise energy, improving signal-to-noise ratio, and reducing circuit area.
  • FIG. 1 is a schematic diagram of a triangular integral digital-to-analog converter according to an embodiment of the present application.
  • FIG. 2 is a schematic diagram of an equivalent circuit model of a noise shaping circuit according to an embodiment of the present application.
  • Figure 3 is a schematic diagram of the spectrum of the noise after shaping.
  • FIG. 4 is a schematic diagram of a conventional oversampling delta-sigma digital-to-analog converter.
  • FIG. 5 is a schematic diagram of a triangular integral digital-to-analog converter according to an embodiment of the present application.
  • FIG. 1 is a schematic diagram of a delta-integrated (Sigma Delta, ⁇ ) digital-to-analog converter (DAC) 10 according to an embodiment of the present application.
  • the triangular-integral digital-to-analog converter 10 is an oversampling (Oversampling) a triangular integral digital-to-analog converter for converting the digital signal OD into an overall analog output signal OAA, which includes an upsampling circuit 12 and a noise shaping circuit 14 .
  • the up-sampling sampling circuit 12 is operative to perform an up-sampling operation on the digital signal OD to generate a digital input signal ID1.
  • the noise shaping circuit 14 includes modulation units NS1, NS2, digital-to-analog converters DAC1, DAC2, a subtractor SUB1, and filters F3, F4.
  • the modulating unit NS1 is coupled to the up-sampling sampling circuit 12 for receiving the digital input signal ID1 and generating the digital output signal OD1.
  • the modulating unit NS1 includes a filter F1 and a quantizer Q1, and the quantizer Q1 is coupled to the filter F1, and the filter F1 has a conversion function H1.
  • the subtracter SUB1 is coupled to the input end and the output end of the quantizer Q1 for generating the quantization noise e1 corresponding to the quantizer Q1.
  • the modulating unit NS2 is coupled to the subtracter SUB1 for generating a digital output signal OD2 according to the digital input signal ID2, wherein the digital input signal ID2 is related to the quantization noise e1, and further, the modulating unit NS2 includes the filter F2 and the quantizer Q2, and the quantizer Q2 is coupled to filter F2, which has a conversion function H2.
  • the noise shaping circuit 14 generates an overall analog output signal OAA based on the digital output signal OD1 and the digital output signal OD2.
  • the filtering order of the filter F1 may be greater than or equal to the filtering order of the filter F2.
  • the filter F1 may be a second-order ( 2nd Order) filter
  • filter F2 is a first order (1 st Order) filter
  • the filter F3 is an analog filter having a DC gain (1/G) and a transfer function Ha, wherein the transfer function Ha corresponds to a value of 1 for the DC frequency.
  • the filter F3 is coupled to the modulation unit NS2 for generating the filtering result OA3, and the noise shaping circuit 14 generates the overall analog output signal OAA according to the digital output signal OD1 and the filtering result OA3.
  • the DC gain (1/G) of the filter F3 is less than 1.
  • the filter F3 is a High Pass Filter (HPF) having a Corner Frequency Fc.
  • HPF High Pass Filter
  • the filter F3 filters out signals having a frequency less than the angular frequency Fc. A signal having a frequency greater than the angular frequency Fc is passed.
  • Filter F4 is a digital filter with a DC reverse gain (-G) and a transfer function Hc.
  • the filter F4 is coupled to the subtractor SUB1 for filtering the quantization noise e1 to generate the digital input signal ID2.
  • the filtering operation performed by the filter F4 on the quantization noise e1 is equivalent to multiplying the quantization noise e1 by the inverse.
  • Gain (-G) and conversion function Hc are related to the transfer function H1 of the filter F1 and the transfer function Ha of the filter F3.
  • the transfer function Hc is related to the reciprocal of the transfer function Ha.
  • s ⁇ z represents the function of the transformation function Ha in the z domain, that is, Ha(s)
  • the digital-to-analog converters DAC1 and DAC2 are respectively coupled to the modulation units NS1 and NS2 for converting the digital output signals OD1 and OD2 into analog output signals OA1 and OA2, respectively.
  • the filter F3 is coupled to the digital-to-analog converter DAC2 for filtering the analog output signal OA2, wherein the filtering operation performed by the filter F3 on the analog output signal OA2 is equivalent to multiplying the analog output signal OA2 by a DC gain ( 1/G) and the conversion function Ha to produce a filtered result OA3.
  • the noise shaping circuit 14 outputs the total analog output signal OAA as the sum of the analog output signal OA1 and the filtering result OA3.
  • FIG. 2 is a schematic diagram of an equivalent circuit model of another noise shaping circuit 24 according to an embodiment of the present application
  • FIG. 3 is a schematic diagram of frequency spectrum of the shaped noise.
  • the noise shaping circuit 24 includes modulation units NS1", NS2" and filters F3", F4".
  • s is used to represent the digital input signal ID1
  • e1 represents the quantization noise introduced by the quantizer Q1
  • e2 represents the quantization noise introduced by the quantizer Q2.
  • the broken line represents the noise spectrum of the noise undergoing first-order shaping
  • the dotted line represents the noise spectrum of the noise through the second-order shaping
  • the solid line represents the noise spectrum after the noise is shaped by the noise shaping circuit 24.
  • the following description will ignore the effects of the digital-to-analog converters DAC1, DAC2 on the noise shaping circuit 14.
  • the modulation unit NS1" receives the digital input signal ID1 (corresponding to the signal s) and performs noise shaping on the quantization noise e1.
  • the signal output by the modulation unit NS1" can be expressed as s+e1*(1-H1).
  • the filter F4" performs a filtering operation on the quantization noise e1, and therefore the signal output from the filter F4" can be expressed as G ⁇ Hc ⁇ e1.
  • the signal G ⁇ Hc ⁇ e1 outputted by the modulation unit NS2 “reception filter F4” performs noise shaping on the quantization noise e2, and the signal output from the modulation unit NS2” can be expressed as –G ⁇ Hc ⁇ e1+e2 ⁇ (1- H2)
  • the relationship, and the DC gain of the filter F3" is (1/G).
  • the component of the output signal of the modulation unit NS1" related to the quantization noise e1 may be offset from the component of the output signal of the modulation unit NS2" related to the quantization noise e1, and therefore, the signal output by the noise shaping circuit 24 (corresponding Overall mode
  • the filter F3" is a first-order high-pass filter having an angular frequency Fc, in other words, when the frequency is less than the angular frequency Fc, the transfer function Ha approaches The first order attenuation is presented; and when the frequency is greater than the angular frequency Fc, the transfer function Ha is one.
  • the noise shaping circuit 24 uses the DC reverse gain (-G) of the filter F4 to quantize the noise e2 introduced by the modulation unit NS2" (i.e., (1/G)e2 ⁇ Ha ⁇ (1-H2)) Instead of the quantization noise e1 (ie, e1 ⁇ (1-H1)) introduced by the modulation unit NS1", since the quantization noise e2 passes through the conversion functions H2, Ha of the filters F2", F3", the shaped noise can have The spectrum shown by the solid line in Figure 3.
  • FIG. 4 is a schematic diagram of a conventional oversampling delta-sigma digital-to-analog converter 40.
  • the oversampling delta-sigma digital-to-analog converter 40 includes a noise shaping circuit 44, and the noise shaping circuit 44 includes a filter F.
  • the filter F is a second-order filter
  • the noise spectrum after the shaping by the noise shaping circuit 44 is the dotted line in FIG. 3, and the slope of the noise spectrum is large.
  • the advantage of the filter F being a second-order filter is that The signal band SB has a lower noise energy, and the disadvantage is that it has excessive noise energy at a high frequency.
  • the filter F is a first-order filter
  • the noise spectrum after being shaped by the noise shaping circuit 44 is a broken line in FIG. 3, and the slope of the noise spectrum is small, wherein the advantage of the filter F as a first-order filter is high.
  • the frequency has a lower noise energy, and the disadvantage is that there is a larger noise energy in the signal band SB.
  • the noise spectrum shaped by the noise shaping circuit 24 has a second-order noise shaping characteristic within the signal band SB (ie, the noise energy in the signal band SB is low), and the signal frequency is Features with first-order noise shaping at high frequencies outside the SB (ie, low noise energy at high frequencies). That is to say, the noise shaping circuit 24 can have the advantages of first-order noise shaping and second-order noise shaping at the same time, that is, the noise spectrum shaped by the noise shaping circuit 24 has low noise energy in the signal frequency band SB and at high frequencies. Further, since the filter F3 has a DC gain (1/G) and the DC gain (1/G) is less than 1, the noise spectrum (corresponding to the solid line in FIG. 3) shaped by the noise shaping circuit 24 is larger than that of the The first-order shaped post-shaping noise spectrum (corresponding to the dashed line in Figure 3) is further shifted down by a factor of G to further reduce the noise energy.
  • FIG. 5 is a schematic diagram of a triangular integral digital-to-analog converter 50 according to an embodiment of the present application.
  • the triangular-integrated digital-to-analog converter 50 includes a noise shaping circuit 54 that includes a modulation unit NS1', NS2' and filters F3', F4', modulation units NS1', NS2' and filters F3', F4' are used to implement modulation units NS1, NS2 and filters F3, F4, respectively, in noise shaping circuit 14 of FIG.
  • the filter F3' is an analog high-pass first-order filter, which includes an operational amplifier OP, a capacitor C, a resistor R, and a resistor G*R, wherein the resistor G*R represents a resistance value of the resistor R. G times, the resistor R is coupled between the negative input terminal of the operational amplifier OP (labeled with a "-" sign) and the output terminal, and the resistor R and the resistor G*R are coupled to the negative input terminal of the operational amplifier OP and digital-to-analog conversion. Between the outputs of DAC2.
  • the resistance value of the resistor G*R is G times the resistance value of the resistor R
  • the DC gain of the filter F3' is (1/G), so that the noise spectrum after shaping by the noise shaping circuit 54 can be downward. Shift G times.
  • the angular frequency Fc of the filter F3' can be expressed as 1/(2 ⁇ GRC), and when G is large enough, the capacitance C having a large capacitance value is not required, and the angular frequency Fc can be maintained at a specific value. In other words, the noise shaping circuit 54 does not require the capacitance C having a large capacitance value, and thus the circuit area can be reduced.
  • the noise shaping circuit 24 uses the subtractor to extract the quantization noise e1 corresponding to the quantizer Q1; and uses the filters F3", F4" to correlate the signal output from the modulation unit NS2" with the quantization noise e1. Restore to e1 ⁇ (1-H1) to offset the correlation in the output signal of modulation unit NS1” For quantizing the component of the noise e1; using the filters F2", F3", shaping the quantization noise e2 to have a spectrum as shown by the solid line in FIG. 3; using the resistor G*R, reducing the noise spectrum and improving the signal-to-noise ratio ( Signal-to-Noise Ratio (SNR), while reducing the circuit area.
  • SNR Signal-to-Noise Ratio
  • the filter F1 is not limited to a second-order filter, and the filter F1 may be a higher-order filter, which is also within the scope of the present application.
  • the present application utilizes two modulation units and an analog high-pass filter to form a post-shaping noise spectrum with different slopes, and has characteristics of low-order noise shaping spectrum and high-order noise shaping spectrum, and has reduced noise energy and improved. Signal to noise ratio and the advantage of reducing the circuit area.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

本申请提供了一种噪声整形电路，包括第一调制单元，用来根据第一数字输入信号产生第一数字输出信号，所述第一调制单元包括第一量化器；第一减法器，耦接于所述第一量化器的输入端及输出端，用来产生第一量化噪声；以及第二调制单元，用来根据第二数字输入信号产生第二数字输出信号，所述第二数字输入信号相关于所述第一量化噪声；其中，所述噪声整形电路根据所述第一数字输出信号及所述第二数字输出信号，产生整体模拟输出信号。

Description

噪声整形电路与三角积分数模转换器 技术领域
本申请涉及一种噪声整形电路与三角积分数模转换器，尤其涉及一种可降低噪声能量的噪声整形电路与三角积分数模转换器。
背景技术
超取样(Oversampling)三角积分(Sigma Delta，ΣΔ)调制器(Modulator)是目前最适合用于高分辨率(Resolution)的模数转换器(Analog-to-Digital Convertor，ADC)或数模转换器(Digital-to-Analog Convertor，DAC)。以三角积分数模转换器为例，其包括升频取样(Upsampling)电路、滤波器、量化器、数字仿真转换器以及低通滤波器。
为了提升三角积分数模转换器的分辨率，可提高超取样倍率，或是提高滤波器阶数(Order)，甚至是提升量化器的位数。提高超取样倍率虽然加速取样频率，但缺点是增加耗电。提高滤波器阶数会导致频带外噪声(Out-of-band Noise)的噪声能量变大，造成后端模拟低通滤波器(Analog LPF)成本大为增加。另外，虽然增加量化器位数降低频带外噪声，然而，在有限的量化器位数的情况下，频带外的噪声能量仍是很高，因此需要具有特定角频率(Corner Frequency)的低通滤波器来滤除频带外噪声。
低通滤波器一般由运算放大器和电阻电容组成，因噪声与低通滤波器中的电阻成正比，若达到高信噪比(Signal-to-Noise Ratio，SNR)，则电阻的阻值需要很小，然而，为了维持低通滤波器的角频率，而低通滤波器就需要很大的电容，而使电路面积过大。
因此，现有技术实有改进的必要。
发明内容
因此，本申请的主要目的即在于提供一种可降低噪声能量的噪声整形电路与三角积分数模转换器，以改善现有技术的缺点。
为了解决上述技术问题，本申请提供了一种噪声整形电路，包括第一调制单元，用来根据第一数字输入信号产生第一数字输出信号，所述第一调制单元包括：第一滤波器，具有第一转换函数；以及第一量化器，耦接于所述第一滤波器；第一减法器，耦接于所述第一量化器的输入端及输出端，用来产生第一量化噪声；以及第二调制单元，用来根据第二数字输入信号产生第二数字输出信号，所述第二数字输入信号相关于所述第一量化噪声，所述第二调制单元包括：第二滤波器，具有第二转换函数；以及第二量化器，耦接于所述第二滤波器；其中，所述噪声整形电路根据所述第一数字输出信号及所述第二数字输出信号，产生整体模拟输出信号。
优选地，所述的噪声整形电路包括第三滤波器，具有第三转换函数，耦接于所述第二调制单元，用来产生滤波结果；其中，所述噪声整形电路根据所述第一数字输出信号及所述滤波结果，产生所述整体模拟输出信号。
优选地，所述的噪声整形电路包括第四滤波器，具有第四转换函数，耦接于所述第一减法器与所述第二调制单元之间，用来根据所述第一量化噪声，产生所述第二数字输入信号。
优选地，所述第四转换函数相关于所述第一转换函数以及所述第三转换函数。
优选地，所述第四转换函数相关于所述第三转换函数的倒数。
优选地，所述第三滤波器具有直流增益，所述直流增益小于1。
优选地，所述第三滤波器为高通滤波器。
优选地，所述第三滤波器包括运算放大器，包括第一输入端以及输出端；第一电阻，耦接于所述运算放大器的所述第一输入端与所述输出端之间，具有第一电阻值；电容；以及第二电阻，具有第二电阻值；其中，所述电容及所述第二电阻耦接于所述运算放大器的所述第一输入端与所述第二调制单元之间，所述第二电阻值为所述第一电阻值的倍数，所述倍数为所述第三滤波器的直流增益的倒数。
优选地，所述的噪声整形电路包括第一数模转换器，耦接于所述第一调制单元，用来将所述第一数字输出信号转换成为第一模拟输出信号；以及第二数模转换器，耦接于所述第二调制单元与所述第三滤波器之间，用来将所述第二数字输出信号转换成为第二模拟输出信号；其中，所述第三滤波器根据所述第二模拟输出信号，产生所述滤波结果；其中，所述噪声整形电路输出所述整体模拟输出信号为所述第一模拟输出信号及所述滤波结果的总和。
优选地，所述第一滤波器的第一滤波阶数大于或等于所述第二滤波器的第二滤波阶数。
本申请另提供了一种三角积分数模转换器，包括升频取样电路，用来产生第一数字输入信号；以及噪声整形电路，包括第一调制单元，用来根据第一数字输入信号产生第一数字输出信号，所述第一调制单元包括：第一滤波器，具有第一转换函数；以及第一量化器，耦接于所述第一滤波器；第一减法器，耦接于所述第一量化器的输入端及输出端，用来产生第一量化噪声；以及第二调制单元，用来根据第二数字输入信号产生第二数字输出信号，所述第二数字输入信号相关于所述第一量化噪声，所述第二调制单元包括：第二滤波器，具有第二转换函数；以及第二量化器，耦接于所述第二滤波器；其中，所述噪声整形电路根据所述第一数字输出信号及所述第二数字输出信号，产生整体模拟输出信号。
本申请利用二个调制单元以及模拟高通滤波器，形成不同斜率的整形后噪声频谱，具有降低噪声能量、提高信噪比以及缩小电路面积的优点。
附图说明
图1为本申请实施例一三角积分数模转换器的示意图。
图2为本申请实施例一噪声整形电路的等效电路模型示意图。
图3为整形后噪声的频谱示意图。
图4为现有一超取样三角积分数模转换器的示意图。
图5为本申请实施例一三角积分数模转换器的示意图。
具体实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
请参考图1，图1为本申请实施例一三角积分(Sigma Delta，ΣΔ)数模转换器(Digital-to-Analog Convertor，DAC)10的示意图，三角积分数模转换器10为一超取样(Oversampling)三角积分数模转换器，三角积分数模转换器10用来将数字信号OD转换成为整体模拟输出信号OAA，其包括升频取样(Upsampling)电路12以及噪声整形(Noise Shaping)电路14。升频取样电路12用来将数字信号OD进行升频取样操作，以产生数字输入信号ID1。噪声整形电路14包括调制单元NS1、NS2、数模转换器DAC1、DAC2、减法器SUB1以及滤波器F3、F4。调制单元NS1耦接于升频取样电路12，用来接收数字输入信号ID1并产生数字输出信号OD1，调制单元NS1包括滤波器F1以及量化器Q1，量化器Q1耦接于滤波器F1，滤波器F1具有转换函数H1。减法器SUB1耦接于量化器Q1的输入端及输出端，用来产生对应于量化器Q1的量化噪声e1。调制单元NS2耦接于减法器SUB1，用来根据数字输入信号ID2产生数字输出信号OD2，其中数字输入信号ID2相关于量化噪声e1，另外，调制单元NS2包括滤波器F2以及量化器Q2，量化器Q2耦接于滤波器F2，滤波器F2 具有转换函数H2。噪声整形电路14根据数字输出信号OD1以及数字输出信号OD2，产生整体模拟输出信号OAA。另外，滤波器F1的滤波阶数可大于或等于滤波器F2的滤波阶数，于一实施例中，滤波器F1可为二阶(2nd Order)滤波器，滤波器F1的转换函数H1可表示为H1(z)＝z-1/(1-z-1)2，优选地，滤波器F2为一阶(1st Order)滤波器，而滤波器F2的转换函数H2可表示为H2(z)＝z-1/(1-z-1)。
滤波器F3为模拟滤波器，其具有直流增益(1/G)以及转换函数Ha，其中转换函数Ha对应于直流频率的值为1。滤波器F3耦接于调制单元NS2，用来产生滤波结果OA3，而噪声整形电路14根据数字输出信号OD1以及滤波结果OA3，产生整体模拟输出信号OAA。其中，滤波器F3的直流增益(1/G)小于1。于一实施例中，滤波器F3为高通滤波器(High Pass Filter，HPF)，其具有角频率(Corner Frequency)Fc，换句话说，滤波器F3将滤掉频率小于角频率Fc的信号，而使频率大于角频率Fc的信号通过。
滤波器F4为数字滤波器，其具有直流反向增益(－G)以及转换函数Hc。滤波器F4耦接于减法器SUB1，用来对量化噪声e1进行滤波运算，以产生数字输入信号ID2，滤波器F4对量化噪声e1所进行的滤波运算等效于将量化噪声e1乘以反向增益(－G)以及转换函数Hc。其中，转换函数Hc相关于滤波器F1的转换函数H1以及滤波器F3的转换函数Ha，优选地，转换函数Hc相关于转换函数Ha的倒数(Reciprocal)，对于图1来说，转换函数Hc、H1、Ha具有1/(1+H1)＝Hc*Ha的关系式，更精确地说，转换函数Hc可表示成Hc(z)＝1/(1+H1(z))/Ha(s)|s→z，其中Hc(z)代表转换函数Hc于z域(z-Domain)的函数，H1(z)代表转换函数H1于z域的函数，Ha(s)代表转换函数Ha于s域(s-Domain)的函数，Ha(s)|s→z代表转换函数Ha于z域的函数，即Ha(s)|s→z为将Ha(s)由s域转换至z域的函数。为了方便后续说明，转换函数Hc可简单表示为Hc＝1/(1+H1)/Ha＝1/[(1+H1)·Ha]。
另外，数模转换器DAC1、DAC2分别耦接于调制单元NS1、NS2，分别用来将数字输出信号OD1、OD2转换成为模拟输出信号OA1、OA2。滤波器F3耦接于数模转换器DAC2，用来对模拟输出信号OA2进行滤波运算，其中滤波器F3对模拟输出信号OA2所进行的滤波运算等效于将模拟输出信号OA2乘以直流增益(1/G)以及转换函数Ha，以产生滤波结果OA3。于此实施例中，噪声整形电路14输出整体模拟输出信号OAA为模拟输出信号OA1及滤波结果OA3的总和。
另外，请参考图2及图3，图2为本申请实施例另一噪声整形电路24的等效电路模型示意图，图3为整形后噪声的频谱示意图。噪声整形电路24包括调制单元NS1”、NS2”以及滤波器F3”、F4”。于图2中，s用来代表数字输入信号ID1，e1代表量化器Q1所引入的量化噪声，e2代表量化器Q2所引入的量化噪声。于图3中，虚线代表噪声经过一阶整形的噪声频谱，点线代表噪声经过二阶整形的噪声频谱，实线代表噪声经过噪声整形电路24整形过后的噪声频谱。为了方便说明，以下说明将忽略数模转换器DAC1、DAC2对噪声整形电路14所造成的影响。
调制单元NS1”接收数字输入信号ID1(对应信号s)后对量化噪声e1进行噪声整形，调制单元NS1”所输出的信号可表示为s+e1*(1-H1)。另外，滤波器F4”对量化噪声e1进行滤波运算，因此滤波器F4”所输出的信号可表示为G·Hc·e1。调制单元NS2”接收滤波器F4”所输出的信号G·Hc·e1对量化噪声e2进行噪声整形，而调制单元NS2”所输出的信号可表示为-G·Hc·e1+e2·(1-H2)。滤波器F3”对调制单元NS2”所输出的信号进行滤波运算，由于滤波器F4”的转换函数Hc与滤波器F3”的转换函数Ha之间具有Hc＝(1-H1)/Ha的关系式，且滤波器F3”的直流增益为(1/G)。其中，调制单元NS1”的输出信号中相关于量化噪声e1的成份可与调制单元NS2”的输出信号中相关于量化噪声e1的成份相互抵销，因此，噪声整形电路24所输出的信号(对应整体模 拟输出信号OAA)可表示为s+e1·(1-H1)-e1·Hc*Ha+(1/G)e2·Ha·(1-H2)＝s+(1/G)e2·Ha·(1-H2)。
需注意的是，噪声整形电路24所输出信号中相关于量化噪声的成份为(1/G)e2·Ha·H2，其中，滤波器F2”可为一阶滤波器，即转换函数H2可表示为H2(z)＝z-1。于一实施例中，滤波器F3”为具有角频率Fc的一阶高通滤波器，换句话说，当频率小于角频率Fc时，转换函数Ha趋近于呈现一阶衰减；而当频率大于角频率Fc时，转换函数Ha为1。在此情形下，当频率小于角频率Fc时，因滤波器F2为一阶滤波器，且转换函数Ha对信号e2·H2进行一阶衰减，因此噪声整形电路24可对量化噪声进行二阶噪声整形；而当频率大于角频率Fc时，因转换函数Ha为1，而滤波器F2仍为一阶滤波器，因此噪声整形电路24对量化噪声进行一阶噪声整形。换句话说，噪声整形电路24利用滤波器F4的直流反向增益(－G)，将调制单元NS2”所引入的量化噪声e2(即(1/G)e2·Ha·(1-H2))取代调制单元NS1”所引入的量化噪声e1(即e1·(1-H1))，因量化噪声e2经过滤波器F2”、F3”的转换函数H2、Ha，而整形后的噪声即可具有如图3中实线所绘示的频谱。
相较之下，请参考图4，图4为现有一超取样三角积分数模转换器40的示意图，超取样三角积分数模转换器40包括噪声整形电路44，噪声整形电路44包括滤波器F。当滤波器F为二阶滤波器时，经噪声整形电路44整形后的噪声频谱为图3中的点线，其噪声频谱的斜率较大，其中滤波器F为二阶滤波器的优点为于信号频带SB内具有较低的噪声能量，而缺点为于高频处具有过大的噪声能量。当滤波器F为一阶滤波器时，经噪声整形电路44整形后的噪声频谱为图3中的虚线，其噪声频谱的斜率较小，其中滤波器F为一阶滤波器的优点为于高频处具有较低的噪声能量，而缺点为于信号频带SB内具有较大的噪声能量。
需注意的是，经噪声整形电路24整形后的噪声频谱于信号频带SB以内具有二阶噪声整形的特性(即于信号频带SB内的噪声能量较低)，而于信号频 带SB以外甚至高频处具有一阶噪声整形的特性(即于高频处的噪声能量较低)。也就是说，噪声整形电路24可同时具有一阶噪声整形及二阶噪声整形的优点，即经噪声整形电路24整形后的噪声频谱于信号频带SB内及高频处皆具有低噪声能量。更进一步地，因滤波器F3具有直流增益(1/G)且直流增益(1/G)小于1，经噪声整形电路24整形后的噪声频谱(对应于图3中的实线)较于经一阶整形后噪声频谱(对应于图3中的虚线)又更向下平移G倍，进一步降低噪声能量。
另外，图1中的噪声整形电路14不限于利用特定电路结构来实现。举例来说，请参考图5，图5为本申请实施例一三角积分数模转换器50的示意图，三角积分数模转换器50包括噪声整形电路54，噪声整形电路54包括调制单元NS1’、NS2’以及滤波器F3’、F4’，调制单元NS1’、NS2’及滤波器F3’、F4’分别用来实现图1噪声整形电路14中的调制单元NS1、NS2及滤波器F3、F4。噪声整形电路54的操作原理与噪声整形电路14相同，故于此不再赘述。需注意的是，滤波器F3’为模拟高通一阶滤波器，其包括运算放大器OP、电容C、电阻R以及电阻G*R，其中电阻G*R代表其电阻值为电阻R的电阻值的G倍，电阻R耦接于运算放大器OP的负输入端(标示有「－」号)与输出端之间，电阻R及电阻G*R耦接于运算放大器OP的负输入端与数模转换器DAC2的输出端之间。另外，因电阻G*R的电阻值为电阻R的电阻值的G倍，因此滤波器F3’的直流增益为(1/G)，而使得经噪声整形电路54整形后的噪声频谱可向下平移G倍。更进一步地，滤波器F3’的角频率Fc可表示为1/(2πGRC)，在G够大的情况下，不需要具有大电容值的电容C，即可维持角频率Fc为一特定值。换句话说，噪声整形电路54不需要具有大电容值的电容C，因此可缩小电路面积。
由上述可知，噪声整形电路24利用减法器，撷取对应于量化器Q1的量化噪声e1；利用滤波器F3”、F4”，将调制单元NS2”所输出的信号中相关于量化噪声e1的成份还原成为e1·(1-H1)，以抵销调制单元NS1”的输出信号中相关 于量化噪声e1的成份；利用滤波器F2”、F3”，将量化噪声e2整形成为具有如图3中实线所绘示的频谱；利用电阻G*R，降低噪声频谱，提高信噪比(Signal-to-Noise Ratio，SNR)，同时缩小电路面积。
需注意的是，前述实施例用以说明本申请之概念，本领域具通常知识者当可据以做不同的修饰，而不限于此。举例来说，滤波器F1不限于为二阶滤波器，滤波器F1可为更高阶的滤波器，亦属于本申请的范畴。
综上所述，本申请利用二个调制单元以及模拟高通滤波器，形成不同斜率的整形后噪声频谱，同时有低阶噪声整形频谱与高阶噪声整形频谱的特性，而具有降低噪声能量、提高信噪比以及缩小电路面积的优点。
以上所述仅为本申请的较佳实施例而已，并不用以限制本申请，凡在本申请的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本申请的保护范围之内。

Claims (12)

  1. 一种噪声整形电路，其中，包括：
    第一调制单元，用来根据第一数字输入信号产生第一数字输出信号，所述第一调制单元包括：
    第一滤波器，具有第一转换函数；以及
    第一量化器，耦接于所述第一滤波器；
    第一减法器，耦接于所述第一量化器的输入端及输出端，用来产生第一量化噪声；以及
    第二调制单元，用来根据第二数字输入信号产生第二数字输出信号，所述第二数字输入信号相关于所述第一量化噪声，所述第二调制单元包括：
    第二滤波器，具有第二转换函数；以及
    第二量化器，耦接于所述第二滤波器；
    其中，所述噪声整形电路根据所述第一数字输出信号及所述第二数字输出信号，产生整体模拟输出信号。
  2. 如权利要求1所述的噪声整形电路，其中，另包括：
    第三滤波器，具有第三转换函数，耦接于所述第二调制单元，用来产生滤波结果；
    其中，所述噪声整形电路根据所述第一数字输出信号及所述滤波结果，产生所述整体模拟输出信号。
  3. 如权利要求2所述的噪声整形电路，其中，还包括：
    第四滤波器，具有第四转换函数，耦接于所述第一减法器与所述第二调制单元之间，用来根据所述第一量化噪声，产生所述第二数字输入信号。
  4. 如权利要求3所述的噪声整形电路，其中，所述第四转换函数相关于所述第一转换函数以及所述第三转换函数。
  5. 如权利要求3所述的噪声整形电路，其中，所述第四转换函数相关于所述第三转换函数的倒数。
  6. 如权利要求3所述的噪声整形电路，其中，所述第四滤波器具有直流反向增益。
  7. 如权利要求2所述的噪声整形电路，其中，所述第三滤波器具有直流增益，所述直流增益小于1。
  8. 如权利要求2所述的噪声整形电路，其中，所述第三滤波器为高通滤波器。
  9. 如权利要求7所述的噪声整形电路，其中，所述第三滤波器包括：
    运算放大器，包括第一输入端以及输出端；
    第一电阻，耦接于所述运算放大器的所述第一输入端与所述输出端之间，具有第一电阻值；
    电容；以及
    第二电阻，具有第二电阻值；
    其中，所述电容及所述第二电阻耦接于所述运算放大器的所述第一输入端与所述第二调制单元之间，所述第二电阻值为所述第一电阻值的倍数，所述倍数为所述第三滤波器的直流增益的倒数。
  10. 如权利要求2所述的噪声整形电路，其中，还包括：
    第一数模转换器，耦接于所述第一调制单元，用来将所述第一数字输出信号转换成为第一模拟输出信号；以及
    第二数模转换器，耦接于所述第二调制单元与所述第三滤波器之间，用来将所述第二数字输出信号转换成为第二模拟输出信号；
    其中，所述第三滤波器根据所述第二模拟输出信号，产生所述滤波结果；
    其中，所述噪声整形电路输出所述整体模拟输出信号为所述第一模拟输出信号及所述滤波结果的总和。
  11. 如权利要求1所述的噪声整形电路，其中，所述第一滤波器的第一滤波阶数大于或等于所述第二滤波器的第二滤波阶数。
  12. 一种三角积分数模转换器，包括：
    升频取样电路，用来产生第一数字输入信号；以及
    噪声整形电路，所述噪声整形电路为权利要求1-11中任意一项所述的噪声整形电路。
PCT/CN2017/088388 2017-06-15 2017-06-15 噪声整形电路与三角积分数模转换器 Ceased WO2018227456A1 (zh)

Priority Applications (5)

Application Number Priority Date Filing Date Title
EP17800989.0A EP3447922A4 (en) 2017-06-15 2017-06-15 NOISE SWITCHING AND SIGMA DELTA DIGITAL ANALOGUE TRANSDUCER
KR1020177036107A KR102096294B1 (ko) 2017-06-15 2017-06-15 노이즈 셰이핑 회로 및 시그마-델타 디지털-아날로그 컨버터
PCT/CN2017/088388 WO2018227456A1 (zh) 2017-06-15 2017-06-15 噪声整形电路与三角积分数模转换器
CN201780000513.4A CN109690955A (zh) 2017-06-15 2017-06-15 噪声整形电路与三角积分数模转换器
US15/822,190 US10084474B1 (en) 2017-06-15 2017-11-26 Noise shaping circuit and sigma-delta digital-to-analog converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2017/088388 WO2018227456A1 (zh) 2017-06-15 2017-06-15 噪声整形电路与三角积分数模转换器

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US15/822,190 Continuation US10084474B1 (en) 2017-06-15 2017-11-26 Noise shaping circuit and sigma-delta digital-to-analog converter

Publications (1)

Publication Number Publication Date
WO2018227456A1 true WO2018227456A1 (zh) 2018-12-20

Family

ID=63556826

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/088388 Ceased WO2018227456A1 (zh) 2017-06-15 2017-06-15 噪声整形电路与三角积分数模转换器

Country Status (5)

Country Link
US (1) US10084474B1 (zh)
EP (1) EP3447922A4 (zh)
KR (1) KR102096294B1 (zh)
CN (1) CN109690955A (zh)
WO (1) WO2018227456A1 (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10979030B2 (en) * 2017-08-25 2021-04-13 Mediatek Inc. System improving signal handling
US10341148B2 (en) * 2017-08-25 2019-07-02 Mediatek Inc. Sigma-delta modulator and associated system improving spectrum efficiency of wired interconnection
DE102021100771A1 (de) 2021-01-15 2022-07-21 Universität Stuttgart, Körperschaft Des Öffentlichen Rechts Mischsignal-Schaltungsanordnung und Verfahren zur effizienten Pulsformung digitaler Signale
US12126363B2 (en) * 2022-07-29 2024-10-22 Cisco Technology, Inc. Error cancellation delta-sigma DAC with an inverting amplifier-based filter
CN116593764B (zh) * 2023-03-29 2024-06-25 浙江朗德电子科技有限公司 高精度自标定电流传感器模块及其标定方法
US12525984B2 (en) * 2024-02-14 2026-01-13 Qualcomm Incorporated Noise-shaping ADC with overload recovery

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020171572A1 (en) * 2001-05-16 2002-11-21 Pioneer Corporation Delta sigma type AD converter
CN204559547U (zh) * 2015-06-04 2015-08-12 福州大学 一种高二阶级联结构Sigma-Delta调制器系统

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3642168A1 (de) * 1986-12-10 1988-06-16 Philips Patentverwaltung Digitale schaltungsanordnung zur verringerung des quantisierungsrauschens
US4862169A (en) * 1988-03-25 1989-08-29 Motorola, Inc. Oversampled A/D converter using filtered, cascaded noise shaping modulators
JPH07118652B2 (ja) * 1990-10-12 1995-12-18 ヤマハ株式会社 Ｄａ変換装置
GB9109637D0 (en) * 1991-05-03 1991-06-26 Marconi Gec Ltd Analogue-to-digital and digital-to-analogue converters
US5369403A (en) * 1992-09-01 1994-11-29 The State Of Oregon Acting By And Through The State Board Of Higher Education On Behalf Of Oregon State University Dual quantization oversampling digital-to-analog converter
US5870048A (en) * 1997-08-13 1999-02-09 National Science Council Oversampling sigma-delta modulator
US6373417B1 (en) * 1999-02-23 2002-04-16 Cirrus Logic, Inc. Digital to analog converter using level and timing control signals to cancel noise
EP1335494A1 (de) * 2001-12-19 2003-08-13 Siemens Aktiengesellschaft Sigma-Delta-Wandler mit Rauschunterdrückung
JP3718706B2 (ja) 2003-10-28 2005-11-24 松下電器産業株式会社 デルタ・シグマ変調装置
EP1712004A2 (en) * 2004-01-28 2006-10-18 Koninklijke Philips Electronics N.V. A da-converter system and a method for converting a multi-bit digital signal to an analog signal
GB0611639D0 (en) * 2006-06-12 2006-07-19 Global Silicon Ltd A sigma-delta modulator
US7903015B1 (en) * 2009-08-24 2011-03-08 Texas Instruments Incorporated Cascaded DAC architecture with pulse width modulation
US8031096B2 (en) * 2010-02-18 2011-10-04 Taiwan Semiconductor Manufacturing Company, Ltd. High resolution delta-sigma digital-to-analog converter
US8228221B2 (en) 2010-09-28 2012-07-24 Taiwan Semiconductor Manufacturing Co., Ltd. Method and apparatus for calibrating sigma-delta modulator
US8284085B2 (en) * 2010-10-06 2012-10-09 Texas Instruments Incorporated Pipelined continuous-time sigma delta modulator
US8325074B2 (en) * 2011-03-22 2012-12-04 Taiwan Semiconductor Manufacturing Co., Ltd. Method and circuit for continuous-time delta-sigma DAC with reduced noise
EP2936688B1 (en) * 2012-12-21 2017-05-03 Teledyne Dalsa B.V. Sigma-delta analog-to-digital converter
US8952837B2 (en) * 2013-02-28 2015-02-10 Broadcom Corporation Multi-rate sigma delta digital-to-analog converter
KR101485467B1 (ko) * 2013-05-24 2015-01-22 네오피델리티 주식회사 시그마-델타 변조부를 포함하는 양자화 장치, 이를 포함하는 adc 및 이를 이용한 양자화 방법
US9166615B2 (en) * 2013-12-13 2015-10-20 Taiwan Semiconductor Manufacturing Co., Ltd. System and method for cascaded PWM digital-to-analog converter with hybrid DAC interface

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020171572A1 (en) * 2001-05-16 2002-11-21 Pioneer Corporation Delta sigma type AD converter
CN204559547U (zh) * 2015-06-04 2015-08-12 福州大学 一种高二阶级联结构Sigma-Delta调制器系统

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
HUANG, XIAOWEI: "A High-Performance Audio SIGMA - DELTA Digital-to-Analog Converter", ELECTRONIC TECHNOLOGY & INFORMATION SCIENCE , CHINA DOCTORAL DISSERTATIONS FULL-TEXT DATABASE, 15 June 2009 (2009-06-15), pages 16 - 19 and 41-43, XP009507426, ISSN: 1674-022X *
See also references of EP3447922A4 *

Also Published As

Publication number Publication date
KR20190010397A (ko) 2019-01-30
CN109690955A (zh) 2019-04-26
EP3447922A1 (en) 2019-02-27
EP3447922A4 (en) 2019-02-27
KR102096294B1 (ko) 2020-04-03
US10084474B1 (en) 2018-09-25

Similar Documents

Publication Publication Date Title
WO2018227456A1 (zh) 噪声整形电路与三角积分数模转换器
US8325074B2 (en) Method and circuit for continuous-time delta-sigma DAC with reduced noise
US9065471B1 (en) Delta-sigma modulator
JP4908548B2 (ja) ハイブリッドデルタシグマａｄｃ
CN102882528B (zh) Sigma-delta调制器
JP2009303157A (ja) デルタシグマ変調器
CN102386929B (zh) Sigma-Delta调制器及包括该调制器的Sigma-Delta模数转换器
JP2011507425A (ja) フィードバックパスにおいてビット数の減少したマルチビットシグマ・デルタ変調器
CN102725963B (zh) 一种多位δ-σ调制器
CN115603755A (zh) ∑δ调制器及其方法
CN104883189B (zh) 包含级间路径的级联结构Sigma-Delta调制器
CN107222216B (zh) 采用自噪声耦合的二阶连续时间sd模数转换器
Zhang et al. A multi-rate hybrid DT/CT MASH ΔΣ modulator with high tolerance to noise leakage
US6956513B1 (en) Error feedback structure for delta-sigma modulators with improved stability
CN116054835B (zh) 一种用于sigma-delta ADC的参考电压发生器的斩波时序控制方法及系统
CN112953533B (zh) 一种改进型低失真Sigma-Delta调制器
TWI395413B (zh) 帶通三角積分調變器
Boncu et al. A second order discrete-time ΔA analog to digital converter for audio applications
Colodro et al. Continuous-time sigma–delta modulator with a fast tracking quantizer and reduced number of comparators
Mohammadi et al. On the design of a 2-2-0 MASH delta-sigma-pipeline modulator
US10892770B2 (en) Noise shaping in a digital-to-analog convertor
Chiang et al. A low-distortion and swing-suppression sigma-delta modulator with extended dynamic range
TWI382671B (zh) 可重新組態之積分三角調變模組
Hassan et al. Performance Improvement of 18-bit ΣΔ A/D Convertor
Munshi et al. A Higher Order ADC Using Multi bit Quantizer and Noise Cancellation

Legal Events

Date Code Title Description
ENP Entry into the national phase

Ref document number: 20177036107

Country of ref document: KR

Kind code of ref document: A

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17800989

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE