WO2018233374A1 - 驱动电路板和显示装置 - Google Patents

驱动电路板和显示装置 Download PDF

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Publication number
WO2018233374A1
WO2018233374A1 PCT/CN2018/084519 CN2018084519W WO2018233374A1 WO 2018233374 A1 WO2018233374 A1 WO 2018233374A1 CN 2018084519 W CN2018084519 W CN 2018084519W WO 2018233374 A1 WO2018233374 A1 WO 2018233374A1
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WIPO (PCT)
Prior art keywords
protective layer
circuit board
test circuit
substrate
driving circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2018/084519
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English (en)
French (fr)
Inventor
张金方
张露
韩珍珍
胡思明
王向前
刘青刚
朱晖
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kunshan Govisionox Optoelectronics Co Ltd
Original Assignee
Kunshan Govisionox Optoelectronics Co Ltd
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Publication date
Application filed by Kunshan Govisionox Optoelectronics Co Ltd filed Critical Kunshan Govisionox Optoelectronics Co Ltd
Priority to KR1020197024331A priority Critical patent/KR102230486B1/ko
Priority to US16/326,912 priority patent/US20200105800A1/en
Priority to JP2019544611A priority patent/JP7038131B2/ja
Priority to EP18819669.5A priority patent/EP3573046B1/en
Publication of WO2018233374A1 publication Critical patent/WO2018233374A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/70—Testing, e.g. accelerated lifetime tests
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
    • G01R31/2825—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere in household appliances or professional audio/video equipment
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0212—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or coating of substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H10D86/443—Interconnections, e.g. scanning lines adapted for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/27—Structural arrangements therefor
    • H10P74/277—Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/60—Arrangements for protection of devices protecting against electrostatic charges or discharges, e.g. Faraday shields

Definitions

  • the present invention relates to the field of display, and in particular to a driving circuit board and a display device.
  • a mounting circuit is provided in a substrate non-display area of the screen of the display device.
  • the mounting circuit typically includes an oppositely disposed input pad and output pad with a bare test circuit between the input pad and the output pad.
  • An input pin and an output pin of the integrated circuit chip are respectively connected to the input pad and the output pad, so that the integrated circuit chip is electrically connected to the substrate.
  • test circuit In the prior art, the test circuit is easily damaged, and is particularly susceptible to electrostatic breakdown. When the test circuit is damaged, it may cause an erroneous determination as to whether the screen body is good. This is very disadvantageous for the production of the screen body.
  • a driving circuit board comprising: a substrate; a test circuit disposed on the substrate; and a top surface disposed over the test circuit and covering the test circuit Protective layer.
  • the test circuit is covered by the protective layer.
  • the protective layer In this way, static electricity accumulation on the driving circuit can be avoided, thereby preventing the thin film transistor of the test circuit from being broken down. This makes the test circuit in an intact state, thereby avoiding the adverse effect on the screen test junction caused by the damage of the test circuit, which contributes to the production of the screen body.
  • the protective layer is made of an organic material.
  • the protective layer made of an organic material has a viscous property which facilitates the covering and fixing of the protective layer to the surface of the test circuit.
  • the organic material has strength characteristics that prevent the test circuit from being damaged by external stress.
  • the upper surface of the protective layer includes a roughened area.
  • the rough region may increase an area when the integrated circuit chip is pasted with the protective layer, and at the same time, enhance adhesion between the integrated circuit chip and the protective layer.
  • the roughened region is a combination of any one or more of a corrugation, a plurality of dimples, a plurality of protrusions, interdigitated gullies, and a grid.
  • the combination of various structures can flexibly increase the area when the protective layer is bonded to enhance the firmness of the sticking.
  • the pits, the bumps or the corrugations may enhance adhesion between the integrated circuit chip and the protective layer.
  • the upper surface of the protective layer further includes a flat region at a central region of the upper surface, the rough region surrounding the flat region.
  • the driving circuit board further includes a display region thin film transistor array having a planarization layer disposed on the substrate, the protective layer being integrally formed with the planarization layer of the display region thin film transistor array .
  • the protective layer is integrally formed with the planarization layer of the thin film transistor array of the display region to reduce the number of processes and improve work efficiency.
  • the protective layer is made of an inorganic material.
  • Inorganic materials have a certain strength and have certain wear and compression properties.
  • At least one connecting unit is further disposed on the substrate, and the connecting unit is adjacent to the test circuit.
  • the test circuit is capable of issuing a test signal to the screen through the connecting unit.
  • the substrate is provided with two connecting units, and the two connecting units are located on both sides of the protective layer.
  • the two connecting units are symmetrically disposed on both sides of the protective layer.
  • test circuit and the connecting unit are in a non-display area of the substrate, and on either side of the test circuit, a non-display area edge of the substrate is connected to the connecting unit The distance of the side is equal to the distance from the other side of the connecting unit to the side of the protective layer close to the connecting unit.
  • the equidistant arrangement of the connecting unit and the protective layer can maintain uniformity of force on the substrate, and can avoid the problem of imbalance of force when the integrated circuit chip is crimped.
  • a display device includes: a driving circuit board including: a substrate including a non-display area and a display area; and a test circuit disposed on the substrate a test circuit is disposed in the non-display area; a protective layer disposed over the upper surface of the test circuit and covering the test circuit; a display area thin film transistor array disposed in the display area; wherein the test The circuit is electrically connected to the display area thin film transistor array of the display area.
  • the test circuit Due to the protective layer on the surface of the test circuit, the test circuit has reliable working performance and does not affect the use of the display device due to damage of the test circuit when the display device is in normal use, the display device has a longer life. .
  • FIG. 1 is a schematic structural view of a display device according to an embodiment of the present invention.
  • FIG. 2 is a schematic cross-sectional view of a driving circuit board in accordance with an embodiment of the present invention
  • FIG. 3 is a schematic diagram showing the positional relationship between a protective layer and a connecting unit in a driving circuit board according to an embodiment of the present invention
  • FIG. 4 is a schematic structural view of a surface of a protective layer according to an embodiment of the present invention.
  • Figure 5 is a schematic view showing the structure of a surface of a protective layer according to another embodiment of the present invention.
  • Figure 6 is a schematic view showing the structure of the surface of a corrugated protective layer according to an embodiment of the present invention.
  • FIG. 1 illustrates a display device 30 in accordance with one embodiment of the present invention.
  • the display device 30 includes a drive circuit board 10, and a data drive circuit 20, a scan drive circuit 40, and a display area thin film transistor array 410 on the drive circuit board 10.
  • the display area thin film transistor array 410 is electrically connected to the data driving circuit 20 and the scan driving circuit 40.
  • the data driving circuit 20 and the scan driving circuit 40 can control the operation of the display region thin film transistor array 410.
  • the drive circuit board 10 includes a display area 500 and a non-display area 600.
  • the display area thin film transistor array 410 is located in the display area 500.
  • the non-display area 600 includes a protective layer 300 covering a test circuit (not shown), and a connection unit 210 on both sides of the protective layer.
  • FIG. 2 illustrates a drive circuit board 10 in accordance with one embodiment of the present invention.
  • the driving circuit board 10 includes a substrate 100, a test circuit 200 disposed on the substrate 100, and a protective layer 300 disposed over the upper surface of the test circuit 200 and covering the test circuit 200.
  • the test circuit 200 is disposed in the non-display area 600.
  • the substrate 100 may be a glass substrate, a flexible plastic substrate, or a substrate made of other organic materials having a certain strength.
  • the drive circuit board 10 further includes two connection units 210 disposed on the surface of the substrate 100 in the non-display area 600.
  • the two connection units 210 are respectively disposed on two sides of the test circuit 200 and adjacent to the test circuit 200. In use, the two connection units 210 serve as input pads and output pads for the integrated circuit chip, respectively.
  • an integrated circuit chip (not shown) may be electrically coupled to the input pad and the output pad through input and output pins, and the integrated circuit chip may be above the test circuit 200.
  • the integrated circuit chip thus communicates with the drive circuit board 10 through the input pads, output pads, input pins, and output pins and controls the display device 30.
  • a conductive paste is also applied between the respective input pads, output pads, input pins, and output pins to enhance electrical connection between each other and to secure the integrated circuit chip to the test circuit 200.
  • the specific working process of the integrated circuit chip is well known to those skilled in the art and will not be described herein.
  • the two connection units 210 are symmetrically disposed on both sides of the test circuit 200.
  • the connection unit 210 is symmetrically disposed on both sides of the test circuit 200 to balance the force when the integrated circuit chip is crimped, thereby ensuring the chip crimping effect, thereby enhancing the service life of the substrate 100.
  • the edges 601, 602 of the non-display area 600 are separated from the respective sides of the connecting unit 210 by a, d, and the two connecting units 210 to the protection.
  • edges 601, 602 of the non-display area 600 may be boundaries of an organic glue layer, preferably formed together with the protective layer 300. It can be understood that the equidistant arrangement of the connecting unit 210 and the testing circuit 200 can maintain the uniformity of the force of the substrate 100, and the substrate 100 can be more effectively prevented from being damaged due to uneven force.
  • the test circuit 200 is used to test whether the screen body displays good.
  • the test circuit 200 can be used to test whether the communication line of the screen and/or the pixel of the screen is damaged.
  • the test circuit 200 can include a thin film transistor 230 including a source 231, a drain 232, and a gate 233, and associated circuitry.
  • a test signal can be input to the screen through the test circuit 200.
  • the test circuit 200 can include a test unit.
  • the test unit may be connected to the thin film transistor 230 through a plurality of signal channels.
  • the test circuit 200 is used as follows: The test unit supplies a gate-on voltage to the gate 233 such that the source 231 and the drain 232 are turned on, and the thin film transistor 230 is turned on. Next, the test unit may input a test signal to the screen through the thin film transistor 230 to test whether the communication line of the screen body and the display pixels of the screen body are damaged.
  • a protective layer 300 covering the test circuit 200 is formed over the test circuit 200.
  • the protective layer 300 is used to protect the test circuit 200.
  • the protective layer 200 can isolate the test circuit 200 from the external environment, thereby avoiding the generation of static electricity at the thin film transistor 230 of the test circuit 200, thereby preventing the thin film transistor 230 from being electrostatically broken down. Electrostatic breakdown can cause damage to the test circuit 200, causing trouble for subsequent work. For example, after the thin film transistor 230 is broken down, the test result of the screen body is adversely affected and the screen body is erroneously judged to be good.
  • the protective layer 300 can protect the test circuit 200 from accidental corrosion to ensure that the test circuit 200 is functioning properly during testing.
  • the protective layer 300 may be made of an organic material or an inorganic material. In a preferred embodiment, the protective layer 300 may be made of the same material as the planarization layer of the display region 500. In another embodiment, the protective layer 300 may be a SiO X film or a SiN X film. In the case where the protective layer 300 is formed of an organic material, the protective layer 300 may also have a certain buffering property, so that the integrated circuit chip from the surface of the test circuit 200 or the protective layer 300 may be avoided. The test circuit 200 is damaged due to excessive pressure. In one embodiment, the protective layer 300 has a thickness of 1.5 mm to 2 mm. The protective layer 300 having a thickness of 1.5 mm to 2 mm can solve not only the electrostatic problem of the test circuit 200 but also sufficient buffering performance.
  • a conductive paste is disposed between the protective layer 300 and the integrated circuit chip to further fix the integrated circuit chip.
  • the surface of the protective layer 300 remote from the substrate 100 has a roughened area.
  • a rough region or a mesh may be formed by photolithography; in the case where the protective layer 300 is an inorganic material, the protective layer 300 may be etched.
  • a rough area is formed.
  • the roughened regions can be any of densely packed dimples, projections, intertwined gullies, corrugations, and various combinations thereof.
  • the roughened area can also be constructed in any suitable other topography.
  • the inventors have found that with this configuration, the lower surface of the integrated circuit chip can be bonded or pasted together with the rough region of the protective layer 300 during assembly of the integrated circuit chip. In this way, the rough region can increase the bonding force of the integrated circuit chip and the protective layer 300, so that the integrated circuit chip and the protective layer 300 are firmly bonded together.
  • the position of the rough region may be adjusted according to different force capabilities of different positions of the test circuit 200.
  • the rough region may be the entire outer surface of the protective layer 300 or a partial region of the outer surface of the protective layer 300.
  • the rough region may be disposed around the protective layer 300.
  • the central region of the protective layer 300 is a flat region 301, and the surrounding portion is the rough region.
  • the glue not only can well fix the integrated circuit chip, but also can avoid excessively pressing down the central region of the gate 233 corresponding to the protective layer 300. Thereby, the amount of the conductive paste used is reduced, and the thin film transistor 230 is protected.
  • the roughened surface of the outer surface of the protective layer 300 is corrugated.
  • the protective layer 300 is an organic material
  • the roughened region in the form of corrugations is preferable because the configuration of the corrugations can be relatively gentle, the amount of conductive paste can be reduced, and the integration can be firmly adhered.
  • the purpose of the circuit chip and the protective layer 300 is not limited to the shape of the circuit chip.
  • the test circuit 200 is electrically coupled to circuitry of the display area 500.
  • the protective layer 300 covered by the surface of the test circuit 200 can prevent the test circuit 200 from being corroded or damaged. During the fabrication of the driver circuit board 10, there are other manufacturing processes after the test circuit 200 is fabricated.
  • the protective layer 300 can prevent the test circuit 200 from being scratched or corroded by other chemical agents in other fabrication processes. Therefore, the test circuit 200 does not have an open circuit phenomenon, and thus the screen test does not cause a bad misjudgment due to damage of the test circuit.
  • the protective layer 300 can be formed in the following manner:
  • the formation process of the protective layer 300 may be: laying flat on the display region 500 and the non-display region 600 a layer; then portions of the corresponding two connection units 210 of the planarization layer are removed by etching.
  • the planarization layer above the test circuit 200 forms the protective layer 300. It can be understood that the rough region on the protective layer 300 can also be formed by etching.
  • the protective layer 300 is an inorganic material, it can be formed by depositing a film layer of an inorganic material on the test circuit 200.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Multimedia (AREA)
  • General Engineering & Computer Science (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Power Engineering (AREA)
  • Automation & Control Theory (AREA)

Abstract

一种驱动电路板和显示装置。所述驱动电路板包括基板（100）、设置于G09基板（100）上的测试电路（200）和两个连接单元（210）。两个连接单元（210）分别设置于测试电路（200）的两侧。驱动电路板还包括设置于测试电路（200）的上表面上方并且覆盖测试电路的保护层（300）。通过设置保护层（300）可以达到避免测试电路（200）线路被腐蚀或损坏的目的。

Description

驱动电路板和显示装置 技术领域
本发明涉及显示领域，特别是涉及一种驱动电路板和显示装置。
背景技术
在显示装置的屏体的基板非显示区设置有安装电路。安装电路通常包括相对设置的输入垫和输出垫，在输入垫和输出垫之间设有裸露的测试电路。集成电路芯片的输入引脚和输出引脚分别对应所述输入垫和所述输出垫连接，从而使得所述集成电路芯片与所述基板电相连。
在现有技术中，测试电路容易被损坏，尤其容易被静电击穿。所述测试电路被损坏后，会导致错误地判断屏体是否良好。这对于屏体的生产是非常不利的。
发明内容
基于此，有必要针对电路基板的测试电路容易被损坏的问题，提供一种驱动电路板和显示装置。
根据本发明的一个方面，提供了一种驱动电路板，其特征在于，包括：基板；设置于所述基板上的测试电路；和设置于所述测试电路的上表面上方并且覆盖所述测试电路的保护层。
根据本发明的上述方面的驱动电路板，测试电路由保护层覆盖。这样，可以避免静电在驱动电路上出现静电积累，进而避免了测试电路的薄膜晶体管被击穿。这就使得测试电路处于完好的状态，进而避免了由测试电路的损坏导致的对屏体测试结的不良影响，这有助于屏体的生产。
在其中一个实施例中，所述保护层由有机材料制成。
由有机材料制成的保护层具有的粘性特性有利于所述保护层覆盖并固定于所述测试电路的表面。所述有机材料具有的强度特性可以避免所述测试电路受到外在应力的破坏。
在其中一个实施例中，所述保护层的上表面包括粗糙区域。
所述粗糙区域可以增加集成电路芯片与所述保护层粘贴时的面积，同时可以增强所述集成电路芯片和所述保护层之间的粘附性。
在其中一个实施例中，所述粗糙区域为波纹、多个凹坑、多个凸起、相互交错的沟壑和网格中任意一种或多种的组合。
多种结构的配合方式可以灵活增加保护层粘合时的面积以增强粘贴的牢固程度。所述凹坑、所述凸起或所述波纹可以增强所述集成电路芯片和所述保护层之间的粘附性。
在其中一个实施例中，所述保护层的上表面还包括位于所述上表面的中心区域的平坦区，所述粗糙区域围绕所述平坦区。
所述集成电路芯片在粘贴于所述保护层表面时，在所述保护层的四周使用更多的导电胶，而在保护层的中心区域使用少量的导电胶，不但能够良好地固定集成电路芯片，而且能够避免过度向下挤压保护层的对应栅极的中心区域。
在其中一个实施例中，所述驱动电路板还包括设置在所述基板上的具有平坦化层的显示区薄膜晶体管阵列，所述保护层与所述显示区薄膜晶体管阵列的平坦化层一体形成。
保护层与所述显示区薄膜晶体管阵列的平坦化层一体形成可以减少工序，提高工作效率。
在其中一个实施例中，所述保护层由无机材料制成。
无机材料具有一定的强度，具有一定的耐磨和抗压性能。
在其中一个实施例中，所述基板上还设置有至少一个连接单元，所述连接单元与所述测试电路相邻。所述测试电路能够通过所述连接单元向屏体发出测试信号。
在其中一个实施例中，所述基板上设置有两个连接单元，所述两个连接单元位于所述保护层两侧。优选地，所述两个连接单元在所述保护层两侧对称设置。
在其中一个实施例中，所述测试电路和所述连接单元处于所述基板的非显示区内，在所述测试电路的任意一侧，所述基板的非显示区边缘到所述连接单 元一侧的距离，与所述连接单元的另一侧到所述保护层靠近所述连接单元的一侧的距离相等。
所述连接单元、所述保护层等距离布置可以保持所述基板受力的均匀性，可以避免集成电路芯片压接时受力失衡的问题。
根据本发明的另一方面，提供了一种显示装置，包括：驱动电路板，所述驱动电路板包括：基板，其包括非显示区和显示区；设置于所述基板上的测试电路，所述测试电路位于所述非显示区内；设置于所述测试电路的上表面上方并且覆盖所述测试电路的保护层；设置于所述显示区内的显示区薄膜晶体管阵列；其中，所述测试电路与所述显示区的显示区薄膜晶体管阵列电连接。
由于所述测试电路表面上的保护层，因此所述测试电路具有可靠的工作性能，并且在显示装置正常使用时不会因为测试电路损坏影响显示装置的使用，所述显示装置具有更长的寿命。
附图说明
图1为根据本发明的一个实施例的显示装置的结构示意图；
图2为根据本发明的一个实施例的驱动电路板的截面示意图；
图3为根据本发明的一个实施例的驱动电路板中保护层和连接单元位置关系示意图；
图4为根据本发明的一个实施例的保护层表面的结构示意图；
图5为根据本发明的另一个实施例的保护层表面的结构示意图；
图6为根据本发明的一个实施例的波纹状保护层表面的结构示意图。
具体实施方式
为了使本发明的发明目的、技术方案及技术效果更加清楚明白，以下结合附图对本发明的具体实施例进行描述。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
图1展示了根据本发明的一个实施例的显示装置30。如图1所示。显示装置30包括驱动电路板10，以及设置驱动电路板10上的数据驱动电路20、扫描 驱动电路40和显示区薄膜晶体管阵列410。所述显示区薄膜晶体管阵列410与所述数据驱动电路20和所述扫描驱动电路40电连接。所述数据驱动电路20和所述扫描驱动电路40可以控制所述显示区薄膜晶体管阵列410的工作。所述驱动电路板10包括显示区500和非显示区600。所述显示区薄膜晶体管阵列410位于显示区500内。所述非显示区600包括覆盖测试电路(未图示)的保护层300，以及位于保护层两侧的连接单元210。
图2展示了根据本发明的一个实施例的驱动电路板10。所述驱动电路板10包括基板100、设置于所述基板100上的测试电路200、以及设置于所述测试电路200的上表面上方并且覆盖所述测试电路200的保护层300。结合图1，所述测试电路200设置于所述非显示区600。
所述基板100可以为玻璃基板、也可以为柔性的塑料基板，或者为具有一定强度的其他有机材料制成的基板。
在其中一个实施例中，所述驱动电路板10还包括设置于所述基板100表面上处于非显示区600的两个连接单元210。所述两个连接单元210分别设置于所述测试电路200的两侧，并与所述测试电路200相邻。在使用过程中，两个连接单元210分别作为集成电路芯片的输入垫和输出垫。
在一个实施例中，集成电路芯片(未图示)可以通过输入引脚和输出引脚电连接到输入垫和输出垫上，并且所述集成电路芯片可以处于所述测试电路200的上方。这样所述集成电路芯片通过输入垫、输出垫、输入引脚和输出引脚与驱动电路板10通信并控制显示装置30。在一个实施例中，还在相应的输入垫、输出垫、输入引脚和输出引脚之间涂覆有导电胶，以加强彼此之间的电连接并且便于将集成电路芯片固定在测试电路200上方。所述集成电路芯片的具体工作过程是本领域的技术人员所熟知的，这里不再赘述。
在其中一个实施例中，所述两个连接单元210对称地设置在所述测试电路200的两侧。所述连接单元210在所述测试电路200两侧对称设置可以使所述集成电路芯片压接时受力平衡，确保芯片压接效果，从而增强所述基板100的使用寿命。在一个优选的实施例中，如图3所示，所述非显示区600的边缘601、602到所述连接单元210相应侧的距离a、d以及两个所述连接单元210到所述 保护层300的相应边缘距离b、c都相等，即，a＝b＝c＝d。所述非显示区600的边缘601、602可以是有机胶层的边界，优选地与所述保护层300一同形成。可以理解，所述连接单元210、所述测试电路200等距离布置可以保持所述基板100受力的均匀性，可以更为有效地避免所述基板100由于受力不均匀造成损坏。
所述测试电路200用于测试屏体是否显示良好。所述测试电路200可以用以测试屏体的通信线路和/或屏体像素点是否损坏。再参照图2，所述测试电路200可以包括薄膜晶体管230以及相关电路，所述薄膜晶体管230包括源极231、漏极232和栅极233。通过所述测试电路200可以向屏体输入测试信号。所述测试电路200可以包括测试单元。所述测试单元可以通过多个信号通道与所述薄膜晶体管230连接。所述测试电路200的使用方法如下：所述测试单元向所述栅极233提供栅极导通电压以使得所述源极231和所述漏极232导通，所述薄膜晶体管230开启。接下来，所述测试单元可以通过所述薄膜晶体管230向屏体输入测试信号以测试屏体的通信线路和屏体的显示像素是否损坏。
为了保证测试电路200中的薄膜晶体管230以及导电线路完好，在制作完成测试电路200之后，在测试电路200上方形成覆盖所述测试电路200的保护层300。所述保护层300用以保护所述测试电路200。例如，所述保护层200可以将测试电路200与外界环境绝缘地隔离开，从而避免在所述测试电路200的薄膜晶体管230处产生静电积累，进而避免所述薄膜晶体管230被静电击穿。静电击穿会导致所述测试电路200损坏，从而给后续工作带来麻烦。例如，所述薄膜晶体管230被击穿后会不良地影响屏体的测试结果并且会误判屏体是否良好。进而，在后续步骤中，需要更复杂的复检步骤，以从被误判为坏屏中找出良好的屏。此外，所述保护层300可以保护测试电路200以避免其意外受到腐蚀，以确保测试电路200在测试期间能够正常工作。
在一个实施例中，所述保护层300可以由有机材料或无机材料制成。在一个优选的实施例中，所述保护层300可以由与所述显示区500的平坦化层相同的材料制成。在另一个实施例中，所述保护层300可以为SiO X膜或SiN X膜。在所述保护层300由有机材料形成的情况下，所述保护层300还可以具有一定的缓冲性能，这样可以避免来自所述测试电路200表面或所述保护层300上的所 述集成电路芯片由于压力过大对所述测试电路200造成损坏。在一个实施例中，所述保护层300的厚度为1.5mm-2mm。厚度为1.5mm-2mm的保护层300不但能够解决测试电路200的静电问题，而且具有足够的缓冲性能。
优选地，在保护层300和集成电路芯片之间设置导电胶以进一步固定所述集成电路芯片。在图4所示的优选实施例中，保护层300的远离所述基板100的表面具有粗糙区域。例如，在所述保护层300为有机物的情况下，可以通过光刻的方式形成粗糙区域或网格；在所述保护层300为无机物的情况下，可通过蚀刻所述保护层300的方式形成粗糙区域。在另一个实施例中，所述粗糙区域可以为密集排布的凹坑、凸起、相互交错的沟壑、波纹以及其各种组合中的任一种。实际上，粗糙区域还可以构造为任何适当的其它形貌。发明人发现，通过这种结构，在所述集成电路芯片的组装过程中，可以使所述集成电路芯片的下表面与所述保护层300的粗糙区域贴合或粘贴在一起。这样，所述粗糙区域可以增加所述集成电路芯片与所述保护层300结合力，从而使得集成电路芯片与保护层300牢固地接合在一起。
所述粗糙区域的位置可以根据所述测试电路200不同位置的不同受力能力进行调整。例如，所述粗糙区域可以是保护层300的整个外表面，也可以是保护层300的外表面的部分区域。优选地，所述粗糙区域可以设置在所述保护层300的四周。请参见图5，在其中一个实施例中，所述保护层300的中心区域为平坦区301，周围部分为所述粗糙区域。发明人发现：所述集成电路芯片在粘贴于所述保护层300表面时，在所述保护层300的四周使用更多的导电胶，而在保护层300的所述平坦区301使用少量的导电胶，不但能够良好地固定所述集成电路芯片，而且能够避免过度向下挤压所述保护层300对应的栅极233的中心区域。由此，就减少了导电胶的使用量，而且对薄膜晶体管230起到保护作用。
在图6所示的实施例中，所述保护层300外表面的所述粗糙区域为波纹。在所述保护层300为有机材料的情况下，波纹形式的所述粗糙区域是优选的，这是由于所述波纹的构造可以较平缓，可以减少导电胶的使用量并且达到牢固粘贴所述集成电路芯片和所述保护层300的目的。
在一个实施例中，所述测试电路200与所述显示区500的电路电连接。所述测试电路200表面覆盖的所述保护层300可以避免所述测试电路200被腐蚀或损坏。所述驱动电路板10制作的过程中，在所述测试电路200制成后还有其它制造工序。所述保护层300能够避免在其它制成工序中所述测试电路200被刮蹭或被其它化学试剂腐蚀。因此所述测试电路200就不会出现断路现象，进而在屏体测试时不会因为测试电路的损坏而造成不良误判。
所述保护层300可通过以下方式形成：
当所述保护层300与所述显示区500的平坦化层为相同材料制成时，所述保护层300的形成过程可以为：在所述显示区500和所述非显示区600上铺设平坦化层；然后将所述平坦化层的对应的两个连接单元210的部分通过蚀刻的方式去除。这样，所述测试电路200的上方的平坦化层就形成了保护层300。可以理解的是，所述保护层300上的所述粗糙区域也可以通过蚀刻的方式形成。
当所述保护层300为无机材料时，可通过在所述测试电路200上沉积无机材料膜层而形成。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (12)

  1. 一种驱动电路板，其特征在于，包括：
    基板(100)；
    设置于所述基板(100)上的测试电路(200)；和
    设置于所述测试电路(200)的上表面上方并且覆盖所述测试电路(200)的保护层(300)。
  2. 如权利要求1所述的驱动电路板，其特征在于，所述保护层(300)由有机材料制成。
  3. 如权利要求1所述的驱动电路板，其特征在于，所述保护层(300)的上表面包括粗糙区域。
  4. 如权利要求3所述的驱动电路板，其特征在于，所述粗糙区域为波纹、多个凹坑、多个凸起、相互交错的沟壑和网格中任意一种或多种的组合。
  5. 如权利要求3所述的驱动电路板，其特征在于，所述保护层(300)的上表面还包括处于所述上表面的中心区域的平坦区(301)，所述粗糙区域围绕所述平坦区(301)。
  6. 如权利要求1到5中任一项所述的驱动电路板，其特征在于，所述驱动电路板还包括设置在所述基板(100)上的具有平坦化层的显示区薄膜晶体管阵列(500)，所述保护层(300)与所述显示区薄膜晶体管阵列(410)的平坦化层一体形成。
  7. 如权利要求1到5中任一项所述的驱动电路板，其特征在于，所述保护层(300)由无机材料制成。
  8. 如权利要求1到5中任一项所述的驱动电路板，其特征在于，所述基板(100)上还设置有至少一个连接单元(210)，所述连接单元(210)与所述测试电路(200)相邻。
  9. 如权利要求8所述的驱动电路板，其特征在于，所述基板(100)上设置有两个连接单元(210)，所述两个连接单元(210)位于所述保护层(300)两侧。
  10. 如权利要求9所述的驱动电路板，其特征在于，所述两个连接单元(210) 在所述保护层(300)两侧对称设置。
  11. 如权利要求8所述的驱动电路板，其特征在于，所述测试电路(200)和所述连接单元(210)处于所述基板(100)的非显示区(600)内；在所述测试电路(200)的任意一侧，所述基板(100)的非显示区(600)的边缘到所述连接单元(210)一侧的距离，与所述连接单元(210)的另一侧到所述保护层(300)靠近所述连接单元(210)的一侧的距离相等。
  12. 一种显示装置，包括：
    驱动电路板，所述驱动电路板包括：
    基板(100)，其包括非显示区(600)和显示区(500)；
    设置于所述基板(100)上的测试电路(200)，所述测试电路(200)位于所述非显示区(600)内；
    设置于所述测试电路(200)的上表面上方并且覆盖所述测试电路(200)的保护层(300)；
    设置于所述显示区(500)内的显示区薄膜晶体管阵列(410)；
    其中，所述测试电路(200)与所述显示区薄膜晶体管阵列(410)电连接。
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