WO2019019590A1 - 像素电路、显示基板和显示装置 - Google Patents

像素电路、显示基板和显示装置 Download PDF

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Publication number
WO2019019590A1
WO2019019590A1 PCT/CN2018/074694 CN2018074694W WO2019019590A1 WO 2019019590 A1 WO2019019590 A1 WO 2019019590A1 CN 2018074694 W CN2018074694 W CN 2018074694W WO 2019019590 A1 WO2019019590 A1 WO 2019019590A1
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Prior art keywords
node
electrode
power source
transistor
light emitting
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Ceased
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PCT/CN2018/074694
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English (en)
French (fr)
Inventor
玄明花
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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Priority to US16/081,458 priority Critical patent/US11127346B2/en
Priority to KR1020187025499A priority patent/KR102084464B1/ko
Priority to EP18758529.4A priority patent/EP3660826A4/en
Priority to EP23160653.4A priority patent/EP4220618B1/en
Priority to JP2018546502A priority patent/JP7055748B2/ja
Publication of WO2019019590A1 publication Critical patent/WO2019019590A1/zh
Anticipated expiration legal-status Critical
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Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a pixel circuit, a display substrate, and a display device.
  • parasitic capacitance In a display panel such as an organic light emitting diode display panel, parasitic capacitance (coupling capacitance) often exists between different wires due to limitation of layout design and thus signal crosstalk is present. When the level of the signal in one of the wires jumps, the level of the signal in the other wire may also change, thereby affecting the display effect.
  • Fig. 1 schematically shows how crosstalk is generated in a display panel.
  • the reference voltage Vref is supplied to all of the pixels, which together with the corresponding data voltage Vdata can determine the pixel current for the corresponding pixel.
  • the data voltage Vdata of the pixel will jump, causing the reference voltage Vref which should be stable. Jumping.
  • other pixels in the lighting stage may suffer from an undesired display effect such as flicker, that is, affected by crosstalk.
  • a pixel circuit comprising: a light emitting device; a driving circuit for controlling a magnitude of a driving current supplied from the first power source to the light emitting device in response to a potential at the first node a storage capacitor for causing a change in potential at the first node in response to a change in potential at the second node, wherein the potential at the second node is at a first reference voltage from the first reference power supply Switching with a data voltage from the data line; and a compensation capacitor for suppressing a change in the drive current caused by a change in the first reference voltage.
  • the light emitting device is coupled between the first power source and a second power source;
  • the driving circuit includes a driving transistor connected in series with the light emitting device, wherein the driving transistor has a connection a gate to the first node;
  • the storage capacitor is coupled between the second node and the first node; and
  • the compensation capacitor is coupled to one of the first node or the second node Between the third node and the third node.
  • the driving transistor is a P-type transistor connected between the first power source and the third node, and the light emitting device is connected to the third node and the Between the second power sources.
  • the driving transistor is an N-type transistor connected between the third node and the second power source, and the light emitting device is connected to the first power source and the Between the third nodes.
  • the pixel circuit further includes: a reset circuit configured to supply the first reference voltage from the first reference power source to the signal valid on the first scan line
  • the second node supplies a second reference voltage from the second reference power supply to the first node
  • the write circuit is configured to be responsive to the signal on the second scan line to be valid from the data line
  • the data voltage is supplied to the second node and the first node is electrically coupled to the third node
  • an illumination control circuit configured to be responsive to the signal on the illumination control line being valid
  • the first reference voltage of a reference power source is supplied to the second node and provides a path that allows the drive current to flow from the first power source to the second power source via the light emitting device and the drive transistor.
  • the reset circuit includes: a first transistor having a gate connected to the first scan line, a first electrode connected to the first reference power source, and a connection to the a second electrode of the second node; and a second transistor having a gate connected to the first scan line, a first electrode connected to the second reference power source, and a first electrode connected to the first node Second electrode.
  • the write circuit includes a third transistor having a gate connected to the second scan line, a first electrode connected to the data line, and connected to the a second electrode of the second node; and a fourth transistor having a gate connected to the second scan line, a first electrode connected to the first node, and a second connected to the third node electrode.
  • the illumination control circuit includes: a fifth transistor having a gate connected to the illumination control line, a first electrode connected to the first reference power source, and a connection to the a second electrode of the second node; and a sixth transistor having a gate connected to the light emission control line, a first electrode connected to the light emitting device, and a second electrode connected to the third node .
  • the light emitting device is selected from the group consisting of an organic light emitting diode and a micro inorganic light emitting diode.
  • a display substrate including: a plurality of scan lines for transmitting scan signals; a plurality of light emission control lines for transmitting light emission control signals; and a plurality of data lines for transmitting data a voltage; and a plurality of pixels arranged in the array, each of the pixels comprising: a light emitting device; a driving circuit for controlling supply from the first power source to the light emitting device in response to a potential at the first node a magnitude of the drive current; a storage capacitor for causing a change in potential at the first node in response to a change in potential at the second node, wherein the potential of the second node is at a potential from the first reference power source Switching between a first reference voltage and a data voltage from a corresponding one of the plurality of data lines; and a compensation capacitor for suppressing a change in the drive current caused by a change in the first reference voltage.
  • the display substrate further includes a substrate on which the plurality of pixels are formed.
  • the driving circuit includes a driving transistor having a source region, a drain region, and an active region formed on the substrate, and a gate region spaced apart from the active region in a vertical direction, the source The region and the drain region are separated by the active region.
  • the storage capacitor has first and second electrodes disposed opposite to each other in the vertical direction.
  • the compensation capacitor has a first electrode and a second electrode disposed opposite to each other in a vertical direction, and the first electrode of the compensation capacitor is disposed at the first electrode or the second electrode with the storage capacitor One of the same layers.
  • the second electrode of the compensation capacitor is formed by a connection line to the drain region of the drive transistor.
  • the first electrode of the compensation capacitor is disposed in the same layer as the first electrode of the storage capacitor and is coupled to the first electrode of the storage capacitor.
  • the first electrode of the compensation capacitor is disposed in the same layer as the second electrode of the storage capacitor and is coupled to the second electrode of the storage capacitor.
  • connection line is made of a doped semiconductor material and is disposed in the same layer as the active region of the drive transistor.
  • a display device comprising: a display substrate as described above; a first scan driver for supplying the scan signal to the plurality of scan lines; and a second scan driver, And the data driver is configured to supply the data voltage to the plurality of data lines.
  • Figure 1 schematically illustrates how crosstalk is generated in a display panel
  • FIG. 2 is a circuit diagram of a pixel circuit in accordance with an embodiment of the present disclosure
  • FIG. 3 is a circuit diagram of another pixel circuit in accordance with an embodiment of the present disclosure.
  • FIG. 4 is a timing chart for the pixel circuit shown in FIG. 2 or FIG. 3;
  • FIG. 5 is a circuit diagram of still another pixel circuit in accordance with an embodiment of the present disclosure.
  • FIG. 6 schematically illustrates a partial cross-sectional view of a display substrate in accordance with an embodiment of the present disclosure
  • FIG. 7 schematically illustrates a partial cross-sectional view of another display substrate in accordance with an embodiment of the present disclosure
  • FIG. 8 is a block diagram of a display device in accordance with an embodiment of the present disclosure.
  • first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/ Some should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer Thus, a first element, component, region, layer, or section, which is discussed below, may be referred to as a second element, component, region, layer or section without departing from the teachings of the disclosure.
  • under and under can encompass both the ⁇ RTIgt;
  • the device can be oriented in other ways (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein interpreted accordingly.
  • a layer is referred to as “between two layers,” it may be a single layer between the two layers, or one or more intermediate layers may be present.
  • the pixel circuit 200 includes a light emitting device (an organic light emitting diode OLED in FIG. 2), a driving circuit shown as a driving transistor T0, a storage capacitor Cst, and a compensation capacitor Cco.
  • the light emitting device illustrated as an organic light emitting diode OLED, is connected between the first power source ELVDD and the second power source ELVSS.
  • the light emitting device is not limited to an organic light emitting diode, and may be other types of light emitting elements such as a micro light emitting diode (Micro-LED).
  • Micro-LED micro light emitting diode
  • miniature light emitting diodes use inorganic materials as luminescent materials and typically have dimensions on the order of microns.
  • the drive circuit controls the magnitude of the drive current supplied from the first power source ELVDD to the light emitting device OLED in response to the potential at the first node N1.
  • the drive circuit includes a drive transistor T0.
  • the driving transistor T0 is connected in series with the light emitting device OLED. More specifically, in this example, the driving transistor T0 is shown as a P-type transistor having a gate connected to the first node N1, a source connected to the first power source ELVDD, and a drain connected to the third node N3. pole.
  • the drive circuit can take other forms.
  • the storage capacitor Cst causes a change in the potential at the first node N1 in response to a change in the potential at the second node N2.
  • the storage capacitor Cst is connected between the second node N2 and the first node N1.
  • the potential at the second node N2 may be selectively set to a first reference voltage from the first reference power source VREF (via the first transistor T1 or the fifth transistor T5) or a data voltage from the data line D[m].
  • the potential at the second node N2 is switched between the first reference voltage and the data voltage.
  • the compensation capacitor Cco is for suppressing a change in the drive current flowing through the light emitting device OLED caused by a change in the first reference voltage.
  • the compensation capacitor Cco is connected between the second node N2 and the third node N3.
  • the compensation capacitor Cco enables a negative feedback control of the potential at the first node N1.
  • the potential at the second node N2 is set at a first reference voltage from the first reference voltage source VREF, as will be described later
  • the first reference voltage is due to, for example, crosstalk
  • the potential at the second node N2 increases, and the potential at the first node N1 also increases correspondingly due to the bootstrap effect of the storage capacitor Cst, that is, the gate-source voltage of the driving transistor T0 increases, This results in a decrease in the drive current of the P-type drive transistor and thus a decrease in the potential at the third node N3.
  • the decrease in the potential at the third node N3 causes a decrease in the potential at the second node N2 due to the bootstrap effect of the compensation capacitor Cco, which in turn causes the potential at the first node N1 due to the bootstrap effect of the storage capacitor Cst The decrease. Therefore, negative feedback control of the potential at the first node N1 is achieved.
  • this negative feedback control ensures a potential at the first node N1 and thus a relatively stable gate-source voltage of the drive transistor T0, thereby reducing the effect of crosstalk on the drive current and thus improving the display quality.
  • FIG. 3 shows an alternative to pixel circuit 300 as pixel circuit 200 shown in FIG. 2.
  • the compensation capacitor Cco is connected between the first node N1 (instead of the second node N2) and the third node N3.
  • the negative feedback control described above remains true, except that the compensation capacitor Cco now provides direct negative feedback of the potential at the first node N1 without passing through the storage capacitor Cst.
  • the pixel circuits 200 and 300 each further include a reset circuit including the first transistor T1 and the second transistor T2, a write circuit including the third transistor T3 and the fourth transistor T4, And an illumination control circuit including the fifth transistor T5 and the sixth transistor T6.
  • the first transistor T1 has a gate connected to the first scan line S[n-1], a first electrode connected to the first reference power source VREF, and a second electrode connected to the second node N2,
  • the second transistor T2 has a gate connected to the first scan line S[n-1], a first electrode connected to the second reference power source VINT, and a second electrode connected to the first node N1.
  • the first transistor T1 is configured to supply a first reference voltage from the first reference power source VREF to the second node N2 in response to the signal on the first scan line S[n-1] being active.
  • the second transistor T2 is configured to supply the second reference voltage Vint from the second reference power source VINT to the first node N1 in response to the signal on the first scan line S[n-1] being active.
  • the third transistor T3 has a gate connected to the second scan line S[n], a first electrode connected to the data line D[m], and a second connected to the second node N2 An electrode, and the fourth transistor T4 has a gate connected to the second scan line S[n], a first electrode connected to the first node N1, and a second electrode connected to the third node N3.
  • the third transistor T3 is configured to supply the data voltage from the data line D[m] to the second node N2 in response to the signal on the second scan line S[n] being active.
  • the fourth transistor T4 is configured to turn on the first node N1 and the third node N3 in response to the signal on the second scan line S[n] being active.
  • the fifth transistor T5 has a gate connected to the light emission control line EM[n], a first electrode connected to the first reference power source VREF, and a second electrode connected to the second node N2, and
  • the six transistor T6 has a gate connected to the light emission control line EM[n], a first electrode connected to the light emitting device OLED, and a second electrode connected to the third node N3.
  • the fifth transistor T5 is configured to supply the first reference voltage from the first reference power source VREF to the second node N2 in response to the signal on the light emission control line EM[n] being active.
  • the sixth transistor T6 is configured to be turned on in response to the signal on the light emission control line EM[n] being active, thereby providing the drive current from the first power source via the light emitting device OLED and the driving transistor T0 ELVDD flows to the path of the second power source ELVSS.
  • FIG. 4 shows a timing diagram for the pixel circuit 200 or 300.
  • the operation of the pixel circuit 200 or 300 will be described in detail below with reference to FIG. It is assumed that the first reference power source VREF supplies the first reference voltage Vref, the second reference power source VINT supplies the second reference voltage Vint, the first power source ELVDD supplies the first power source voltage Vdd, and the second power source ELVSS supplies the second power source voltage Vss.
  • the signal on the first scan line S[n-1] is valid
  • the signal on the second scan line S[n] is invalid
  • the signal on the illumination control line EM[n] is invalid.
  • the first transistor T1 and the second transistor T2 are turned on such that the first reference voltage Vref supplied from the first reference voltage source VREF and the second reference voltage Vinit supplied from the second reference voltage source VINT are respectively transferred to the ends of the storage capacitor Cst ( That is, the second node N2 and the first node N1). Therefore, the voltage across the storage capacitor Cst is reset.
  • the first and second reference voltages Vref and Vint may be equal or unequal as long as they do not turn on the driving transistor T0. In general, the difference between Vref and Vint should not be too large to avoid overcharging the storage capacitor Cst.
  • the signal on the first scan line S[n-1] is invalid
  • the signal on the second scan line S[n] is valid
  • the signal on the light emission control line EM[n] is invalid.
  • the third transistor T3 is turned on to transfer the data voltage Vdata on the data line D[m] to the second node N2.
  • the fourth transistor T4 is also turned on, and the first node N1 is turned on with the third node N3. Therefore, the driving transistor T0 is in a diode-connected state in which its gate-source voltage Vgs is equal to its threshold voltage Vth. Since the source voltage Vs is the first power supply voltage Vdd supplied from the first power source ELVDD, the gate voltage Vg of the driving transistor T0 (that is, the potential at the first node N1) is (Vdd + Vth).
  • the signal on the first scan line S[n-1] is invalid
  • the signal on the second scan line S[n] is invalid
  • the signal on the light-emitting control line EM[n] is valid.
  • the fifth transistor T5 is turned on, and the first reference voltage Vref supplied from the first reference voltage source VREF is transmitted to the second node N2. Therefore, the potential at the second node N2 jumps from Vdata during the writing phase P2 to Vref, and the amount of change is (Vref - Vdata). Due to the bootstrap effect of the storage capacitor Cst, the potential at the first node N1 also undergoes the same degree of change, that is, it becomes (Vdd + Vth + Vref - Vdata).
  • the sixth transistor T6 is also turned on, providing a current flow path from the first power source ELVDD to the second power source ELVSS.
  • the drive current Id flowing through the light emitting device OLED is calculated as:
  • K is a predetermined coefficient, which can typically be considered a constant.
  • the drive current Id is related to the reference voltage Vref supplied from the first reference power source VREF. Therefore, the transition of the reference level Vref due to the crosstalk can cause a corresponding change in the driving current Id and thus the luminance of the light emitting device OLED, which affects the display effect.
  • the change of the drive current Id caused by the change of the reference level Vref is suppressed by providing the compensation capacitor Cco, thereby reducing the crosstalk effect.
  • each transistor can be a thin film transistor that is typically fabricated such that their first and second electrodes are used interchangeably.
  • FIG. 5 shows one possible pixel circuit 500 in which each transistor is an N-type transistor.
  • the same reference numerals denote the same elements.
  • the configuration of the pixel circuit 500 is similar to those of the pixel circuit 200 previously described with respect to FIGS. 2 and 4, except that in the pixel circuit 500, the driving transistor T0 is connected between the third node N3 and the second power source ELVSS (its The drain is connected to the third node N3 and its source is connected to the second power source ELVSS) and the light emitting device OLED is connected between the first power source ELVDD and the third node N3.
  • the compensation capacitor Cco may be connected between the first node N1 and the third node N3 in the pixel circuit 500.
  • FIG. 6 illustrates a partial cross-sectional view of a display substrate 600 in accordance with an embodiment of the present disclosure.
  • a substrate 610 is shown in FIG. Formed on the substrate 610 is a source region 622, an active region 624, and a drain region 626 of the drive transistor T0, wherein the source region 622 and the drain region 626 are spaced apart by the active region 624.
  • the drive transistor T0 also has a gate region 628 that is vertically spaced from the active region 624.
  • a storage capacitor Cst having a first electrode 632 and a second electrode 634 disposed opposite to each other in the vertical direction and a compensation having a first electrode 642 and a second electrode 644 disposed opposite to each other in the vertical direction. Capacitor Cco.
  • FIG. 6 corresponds to the pixel circuit 200 shown in FIG. 2, although other elements than the driving transistor T0, the storage capacitor Cst, and the compensation capacitor Cco are not shown for convenience of illustration.
  • the second electrode 644 of the compensation capacitor Cst is disposed in the same layer as the drain region 626 of the driving transistor T0, and is coupled to other elements (in the pixel) for coupling the drain region 626 into the pixel circuit.
  • a connection wire of the sixth transistor T6) is formed in the circuit 200.
  • connection line as the second electrode 644 of the compensation capacitor Cco, since the second electrode 644 can then be located within the layout area of the original pixel circuit (ie, the pixel circuit without the compensation capacitor Cco), such that compensation
  • the presence of the capacitor Cco does not result in an increase in the layout area of the pixel circuit, thereby promoting an increase in resolution.
  • This also eliminates the need for additional wires, thereby reducing crosstalk due to, for example, wire overlap.
  • the first electrode 642 of the compensation capacitor Cst is disposed in the same layer as the first electrode 632 of the storage capacitor Cst, and the electrodes 642 and 632 may or may not be directly connected to each other.
  • the first electrode 632 may have an extension portion corresponding to the second electrode 644 as the first electrode 642, wherein the extension portion and the connection line 644 constitute a compensation capacitor Cco.
  • FIG. 7 illustrates a partial cross-sectional view of another display substrate 700 in accordance with an embodiment of the present disclosure.
  • Substrate 710 is shown in FIG. Similar to the configuration shown in FIG. 6, formed on the substrate 710 is a source region 722, an active region 724, a drain region 726, and a gate region 728 of the driving transistor T0.
  • a storage capacitor Cst having a first electrode 732 and a second electrode 734 and a compensation capacitor Cco having a first electrode 742 and a second electrode 744.
  • the display substrate 700 is different from the display substrate 600 in that the display substrate 700 corresponds to the pixel circuit 300 shown in FIG. As shown in FIG. 7, the first electrode 742 of the compensation capacitor Cco is disposed in the same layer as the second electrode 734 of the storage capacitor Cst. Other configurations of the display substrate 700 may be the same as those of the display substrate 600 described above with respect to FIG. 6, and thus are omitted herein for the sake of brevity.
  • the second electrode 634 or 734 of the storage capacitor Cst is exemplarily shown as being disposed in the same layer as the gate region 628 or 728 of the driving transistor T0, although the present disclosure is not limited thereto.
  • the second electrode 634 or 734 may be disposed in the same layer as other structures of the pixel circuit such as the source and drain of the driving transistor.
  • the second electrode 634 or 734 can be directly coupled to the gate region 628 or 728 of the drive transistor T0.
  • a connection line serving as the second electrode 644 or 744 of the storage capacitor Cco may be made of a doped semiconductor material.
  • the semiconductor layer is also left outside the active region and doped (eg, lightly doped) to have good conductivity.
  • the doped semiconductor layer can be used as a connection line, that is, a second electrode 644 or 744.
  • FIG. 8 is a block diagram of a display device 800 in accordance with an embodiment of the present disclosure.
  • the display device 800 includes a display substrate 810, a first scan driver 802, a second scan driver 804, a data driver 806, and a voltage generator 808.
  • the display substrate 810 includes n ⁇ m pixels P. Each pixel P may take the form of, for example, the pixel circuit 200, 300 or 500 described above with respect to Figures 2 to 5.
  • the display substrate 810 includes n+1 scanning lines S1, S2, . . .
  • n and m are natural numbers.
  • the first scan driver 802 is connected to the scan lines S1, S2, . . . , Sn, Sn+1 to apply a scan signal to the display substrate 810.
  • the second scan driver 804 is connected to the light emission control lines EM1, EM2, . . . , EMn to apply the light emission control signals to the display substrate 810.
  • the data driver 806 is connected to the data lines D1, D2, . . . , Dm to apply the data signals to the display substrate 810.
  • the data driver 106 supplies data voltages to the respective pixels P in the display substrate 810 during the writing phase P2, as described above with respect to FIG.
  • a voltage generator 808, which can function as the first power source ELVDD, the second power source ELVSS, the first reference power source VREF, and the second reference power source VINT as described in the above embodiments, generates a first power source voltage Vdd required for each pixel P, The second power source voltage Vss, the first reference voltage Vref, and the second reference voltage Vinit.
  • Examples of voltage generator 808 include, but are not limited to, a DC/DC converter and a low dropout regulator (LDO).
  • the display device 800 can be any product or component having a display function such as a display panel, an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.

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Abstract

一种像素电路(200,300,500)，包括：发光器件(OLED)；驱动电路(T0)，用于响应于第一节点(N1)处的电位而控制从第一电源(ELVDD)供应给发光器件(OLED)的驱动电流（Id）的量值；存储电容器(Cst)，用于响应于第二节点(N2)处的电位的改变而引起第一节点(N1)处的电位的改变，其中第二节点(N2)处的电位可在来自第一参考电源(VREF)的第一参考电压(Vref)与来自数据线(D(m))的数据电压(Vdata)之间切换；以及补偿电容器(Cco)，用于抑制由第一参考电压(Vref)的改变引起的驱动电流（Id）的改变。

Description

像素电路、显示基板和显示装置 技术领域
本公开涉及显示技术领域，具体涉及一种像素电路、显示基板和显示装置。
背景技术
在显示面板(如有机发光二极管显示面板)中，因版图设计的限制，不同导线之间往往存在寄生电容(耦合电容)并且因此存在信号串扰。当某导线中的信号的电平发生跳变时，另一导线中的信号的电平也可能产生变化，从而影响显示效果。
图1示意性地示出了在显示面板中如何产生串扰。在该显示面板中，参考电压Vref被供给所有的像素，其可以与相应的数据电压Vdata一起确定用于相应的像素的像素电流。如图1所示，当由A区域扫描到位于B区域的像素，以及由位于B区域的像素扫描到C区域时，该像素的数据电压Vdata会发生跳变，引起本应稳定的参考电压Vref的跳变。此时，处于发光阶段的其它像素可能会遭受闪烁等不期望的显示效果，即受到串扰影响。
发明内容
提供一种可以缓解、减轻或消除上述问题中的一个或多个的机制将是有利的。
根据本公开的一个方面，提供了一种像素电路，包括：发光器件；驱动电路，用于响应于第一节点处的电位而控制从第一电源供应给所述发光器件的驱动电流的量值；存储电容器，用于响应于第二节点处的电位的改变而引起所述第一节点处的电位的改变，其中所述第二节点处的电位可在来自第一参考电源的第一参考电压与来自数据线的数据电压之间切换；以及补偿电容器，用于抑制由所述第一参考电压的改变引起的所述驱动电流的改变。
在某些示例性实施例中，所述发光器件连接在所述第一电源与第二电源之间；所述驱动电路包括与所述发光器件串联连接的驱动晶体管，其中所述驱动晶体管具有连接到所述第一节点的栅极；所述存储 电容器连接在所述第二节点与所述第一节点之间；并且所述补偿电容器连接在所述第一节点或所述第二节点之一与所述第三节点之间。
在某些示例性实施例中，所述驱动晶体管为P型晶体管，其连接在所述第一电源与所述第三节点之间，并且所述发光器件连接在所述第三节点与所述第二电源之间。
在某些示例性实施例中，所述驱动晶体管为N型晶体管，其连接在所述第三节点与所述第二电源之间，并且所述发光器件连接在所述第一电源与所述第三节点之间。
在某些示例性实施例中，所述像素电路还包括：复位电路，被配置成响应于第一扫描线上的信号有效而将来自所述第一参考电源的所述第一参考电压供应给所述第二节点并且将来自第二参考电源的第二参考电压供应给所述第一节点；写入电路，被配置成响应于第二扫描线上的信号有效而将来自所述数据线的所述数据电压供应给所述第二节点并且将所述第一节点与所述第三节点导通；以及发光控制电路，被配置成响应于发光控制线上的信号有效而将来自所述第一参考电源的所述第一参考电压供应给所述第二节点并且提供允许所述驱动电流经由所述发光器件和所述驱动晶体管从所述第一电源流动到所述第二电源的路径。
在某些示例性实施例中，所述复位电路包括：第一晶体管，其具有连接到所述第一扫描线的栅极、连接到所述第一参考电源的第一电极、以及连接到所述第二节点的第二电极；和第二晶体管，其具有连接到所述第一扫描线的栅极、连接到所述第二参考电源的第一电极、以及连接到所述第一节点的第二电极。
在某些示例性实施例中，所述写入电路包括：第三晶体管，其具有连接到所述第二扫描线的栅极、连接到所述数据线的第一电极、以及连接到所述第二节点的第二电极；和第四晶体管，其具有连接到所述第二扫描线的栅极、连接到所述第一节点的第一电极、以及连接到所述第三节点的第二电极。
在某些示例性实施例中，所述发光控制电路包括：第五晶体管，其具有连接到所述发光控制线的栅极、连接到所述第一参考电源的第一电极、以及连接到所述第二节点的第二电极；和第六晶体管，其具有连接到所述发光控制线的栅极、连接到所述发光器件的第一电极、 以及连接到所述第三节点的第二电极。
在某些示例性实施例中，所述发光器件选自由有机发光二极管和微型无机发光二极管组成的组。
根据本公开的另一方面，提供了一种显示基板，包括：多条扫描线，用于传送扫描信号；多条发光控制线，用于传送发光控制信号；多条数据线，用于传送数据电压；以及多个像素，布置在阵列中，所述像素中的每一个包括：发光器件；驱动电路，用于响应于第一节点处的电位而控制从第一电源供应给所述发光器件的驱动电流的量值；存储电容器，用于响应于第二节点处的电位的改变而引起所述第一节点处的电位的改变，其中所述第二节点的电位可在来自第一参考电源的第一参考电压与来自所述多条数据线中的对应一条数据线的数据电压之间切换；以及补偿电容器，用于抑制由所述第一参考电压的改变引起的所述驱动电流的改变。
在某些示例性实施例中，所述显示基板，还包括其上形成所述多个像素的基底。所述驱动电路包括驱动晶体管，其具有形成在所述基底上的源极区、漏极区和有源区以及与所述有源区在垂直方向上间隔开的栅极区，所述源极区和所述漏极区由所述有源区间隔开。所述存储电容器具有在垂直方向上彼此相对设置的第一电极和第二电极。所述补偿电容器具有在垂直方向上彼此相对设置的第一电极和第二电极，所述补偿电容器的所述第一电极设置在与所述存储电容器的所述第一电极或所述第二电极之一相同的层。所述补偿电容器的所述第二电极由到所述驱动晶体管的所述漏极区的连接线形成。
在某些示例性实施例中，所述补偿电容器的所述第一电极设置在与所述存储电容器的所述第一电极相同的层并且连接到所述存储电容器的所述第一电极。
在某些示例性实施例中，所述补偿电容器的所述第一电极设置在与所述存储电容器的所述第二电极相同的层并且连接到所述存储电容器的所述第二电极。
在某些示例性实施例中，所述连接线由掺杂半导体材料制成并且设置在与所述驱动晶体管的所述有源区相同的层。
根据本公开的又另一方面，提供了一种显示装置，包括：如上所述的显示基板；第一扫描驱动器，用于向所述多条扫描线供应所述扫 描信号；第二扫描驱动器，用于向所述多条发光控制线供应所述发光控制信号；以及数据驱动器，用于向所述多条数据线供应所述数据电压。
根据在下文中所描述的实施例，本公开的这些和其它方面将是清楚明白的，并且将参考在下文中所描述的实施例而被阐明。
附图说明
图1示意性地示出了在显示面板中如何产生串扰；
图2为根据本公开实施例的一种像素电路的电路图；
图3为根据本公开实施例的另一种像素电路的电路图；
图4为用于图2或图3所示的像素电路的时序图；
图5为根据本公开实施例的又另一种像素电路的电路图；
图6示意性地示出了根据本公开实施例的一种显示基板的局部剖面视图；
图7示意性地示出了根据本公开实施例的另一种显示基板的局部剖面视图；并且
图8为根据本公开实施例的一种显示装置的框图。
具体实施方式
将理解的是，尽管术语第一、第二、第三等等在本文中可以用来描述各种元件、部件、区、层和/或部分，但是这些元件、部件、区、层和/或部分不应当由这些术语限制。这些术语仅用来将一个元件、部件、区、层或部分与另一个相区分。因此，下面讨论的第一元件、部件、区、层或部分可以被称为第二元件、部件、区、层或部分而不偏离本公开的教导。
诸如“在…下面”、“在…之下”、“较下”、“在…下方”、“在…之上”、“较上”等等之类的空间相对术语在本文中可以为了便于描述而用来描述如图中所图示的一个元件或特征与另一个(些)元件或特征的关系。将理解的是，这些空间相对术语意图涵盖除了图中描绘的取向之外在使用或操作中的器件的不同取向。例如，如果翻转图中的器件，那么被描述为“在其他元件或特征之下”或“在其他元件或特征下面”或“在其他元件或特征下方”的元件将取向为“在 其他元件或特征之上”。因此，示例性术语“在…之下”和“在…下方”可以涵盖在…之上和在…之下的取向两者。器件可以取向为其他方式(旋转90度或以其他取向)并且相应地解释本文中使用的空间相对描述符。另外，还将理解的是，当层被称为“在两个层之间”时，其可以是在该两个层之间的唯一的层，或者也可以存在一个或多个中间层。
本文中使用的术语仅出于描述特定实施例的目的并且不意图限制本公开。如本文中使用的，单数形式“一个”、“一”和“该”意图也包括复数形式，除非上下文清楚地另有指示。将进一步理解的是，术语“包括”和/或“包含”当在本说明书中使用时指定所述及特征、整体、步骤、操作、元件和/或部件的存在，但不排除一个或多个其他特征、整体、步骤、操作、元件、部件和/或其群组的存在或添加一个或多个其他特征、整体、步骤、操作、元件、部件和/或其群组。如本文中使用的，术语“和/或”包括相关联的列出项目中的一个或多个的任意和全部组合。
将理解的是，当元件或层被称为“在另一个元件或层上”、“连接到另一个元件或层”或“耦合到另一个元件或层”时，其可以直接在另一个元件或层上、直接连接到另一个元件或层或者直接耦合到另一个元件或层，或者可以存在中间元件或层。相反，当元件被称为“直接在另一个元件或层上”、“直接连接到另一个元件或层”或“直接耦合到另一个元件或层”时，没有中间元件或层存在。然而，在任何情况下“在…上”或“直接在…上”都不应当被解释为要求一个层完全覆盖下面的层。
本文中参考本公开的理想化实施例的示意性图示(以及中间结构)描述本公开的实施例。正因为如此，应预期例如作为制造技术和/或公差的结果而对于图示形状的变化。因此，本公开的实施例不应当被解释为限于本文中图示的区的特定形状，而应包括例如由于制造导致的形状偏差。因此，图中图示的区本质上是示意性的，并且其形状不意图图示器件的区的实际形状并且不意图限制本公开的范围。
除非另有定义，本文中使用的所有术语(包括技术术语和科学术语)具有与本公开所属领域的普通技术人员所通常理解的相同含义。将进一步理解的是，诸如那些在通常使用的字典中定义的之类的术语 应当被解释为具有与其在相关领域和/或本说明书上下文中的含义相一致的含义，并且将不在理想化或过于正式的意义上进行解释，除非本文中明确地如此定义。为使本领域技术人员更好地理解本公开的技术方案，在本文中，两个元件“设置在同一层”可以是指它们是在基底上由同一个材料层经构图工艺后形成的，但并不表示它们与基底间的距离必然相等。
下面结合附图对本公开的实施例进行详细描述。
图2为根据本公开实施例的一种像素电路200的电路图。如图2所示，像素电路200包括发光器件(在图2中为有机发光二极管OLED)、被示出为驱动晶体管T0的驱动电路、存储电容器Cst以及补偿电容器Cco。
发光器件，被图示为有机发光二极管OLED，连接在第一电源ELVDD与第二电源ELVSS之间。发光器件不限于有机发光二极管，并且可以是其他类型的发光元件，例如微型发光二极管(Micro-LED)。如已知的，微型发光二极管采用无机物作为发光材料并且典型地具有微米级的尺寸。
驱动电路响应于第一节点N1处的电位而控制从第一电源ELVDD供应给发光器件OLED的驱动电流的量值。在该示例中，驱动电路包括驱动晶体管T0。具体地，驱动晶体管T0与发光器件OLED串联连接。更具体地，在该示例中，驱动晶体管T0被示出为P型晶体管，其具有连接到第一节点N1的栅极、连接到第一电源ELVDD的源极和连接到第三节点N3的漏极。在其他实施例中，驱动电路可以采取其他形式。
存储电容器Cst响应于第二节点N2处的电位的改变而引起第一节点N1处的电位的改变。具体地，存储电容器Cst连接在第二节点N2与第一节点N1之间。第二节点N2处的电位可以被选择性地设定为来自第一参考电源VREF的第一参考电压(经由第一晶体管T1或第五晶体管T5)或来自数据线D[m]的数据电压。如后面将描述的，当像素电路200在操作中时，第二节点N2处的电位在所述第一参考电压与所述数据电压之间切换。
补偿电容器Cco用于抑制由所述第一参考电压的改变引起的流过发光器件OLED的所述驱动电流的改变。在该示例中，补偿电容器Cco 连接在第二节点N2与第三节点N3之间。补偿电容器Cco使得能够实现对第一节点N1处的电位的负反馈控制。例如，在发光阶段(其中第二节点N2处的电位被设定在来自第一参考电压源VREF的第一参考电压，如后面将描述的)中，当所述第一参考电压因例如串扰而增大时，第二节点N2处的电位增大，并且第一节点N1处的电位由于存储电容器Cst的自举效应也相应地增大，也即，驱动晶体管T0的栅-源电压增大，导致该P型驱动晶体管的驱动电流的减小以及因此第三节点N3处的电位的减小。第三节点N3处的电位的减小由于补偿电容器Cco的自举效应而引起第二节点N2处的电位的减小，这进而由于存储电容器Cst的自举效应而引起第一节点N1处的电位的减小。因此，实现了对第一节点N1处的电位的负反馈控制。有利地，该负反馈控制确保了第一节点N1处的电位并且因此驱动晶体管T0的栅-源电压的相对稳定，从而减小串扰对驱动电流的影响并且进而改善显示质量。
图3示出了像素电路300作为图2中所示的像素电路200的替换方案。如图3所示，在像素电路300中，补偿电容器Cco连接在第一节点N1(而非第二节点N2)与第三节点N3之间。上面描述的负反馈控制仍然成立，只不过补偿电容器Cco现在提供对第一节点N1处的电位的直接负反馈，而不经由存储电容器Cst。
在图2或图3的示例中，像素电路200和300每个还包括包括所述第一晶体管T1和第二晶体管T2的复位电路、包括第三晶体管T3和第四晶体管T4的写入电路、以及包括所述第五晶体管T5和第六晶体管T6的发光控制电路。
在复位电路中，第一晶体管T1具有连接到第一扫描线S[n-1]的栅极、连接到第一参考电源VREF的第一电极、以及连接到第二节点N2的第二电极，并且第二晶体管T2具有连接到所述第一扫描线S[n-1]的栅极、连接到第二参考电源VINT的第一电极、以及连接到第一节点N1的第二电极。第一晶体管T1被配置成响应于所述第一扫描线S[n-1]上的信号有效而将来自第一参考电源VREF的第一参考电压供应给第二节点N2。第二晶体管T2被配置成响应于第一扫描线S[n-1]上的信号有效而将来自所述第二参考电源VINT的第二参考电压Vint供应给第一节点N1。
在写入电路中，第三晶体管T3具有连接到第二扫描线S[n]的栅极、 连接到所述数据线D[m]的第一电极、以及连接到第二节点N2的第二电极，并且第四晶体管T4具有连接到所述第二扫描线S[n]的栅极、连接到第一节点N1的第一电极、以及连接到第三节点N3的第二电极。第三晶体管T3被配置成响应于所述第二扫描线S[n]上的信号有效而将来自所述数据线D[m]的所述数据电压供应给第二节点N2。第四晶体管T4被配置成响应于所述第二扫描线S[n]上的信号有效而将第一节点N1与第三节点N3导通。
在发光控制电路中，第五晶体管T5具有连接到发光控制线EM[n]的栅极、连接到第一参考电源VREF的第一电极、以及连接到第二节点N2的第二电极，并且第六晶体管T6具有连接到所述发光控制线EM[n]的栅极、连接到发光器件OLED的第一电极、以及连接到第三节点N3的第二电极。第五晶体管T5被配置成响应于所述发光控制线EM[n]上的信号有效而将来自所述第一参考电源VREF的所述第一参考电压供应给第二节点N2。第六晶体管T6被配置成响应于所述发光控制线EM[n]上的信号有效而开启，从而提供允许所述驱动电流经由所述发光器件OLED和所述驱动晶体管T0从所述第一电源ELVDD流动到所述第二电源ELVSS的路径。
图4示出了用于像素电路200或300的时序图。下面将结合图4详细描述像素电路200或300的操作。假定：第一参考电源VREF供应第一参考电压Vref，第二参考电源VINT供应第二参考电压Vint，第一电源ELVDD供应第一电源电压Vdd，并且第二电源ELVSS供应第二电源电压Vss。
在复位阶段P1期间，第一扫描线S[n-1]上信号有效，第二扫描线S[n]上的信号无效，并且发光控制线EM[n]上的信号无效。第一晶体管T1和第二晶体管T2被开启，使得第一参考电压源VREF供应的第一参考电压Vref和第二参考电压源VINT供应的第二参考电压Vinit被分别传送到存储电容器Cst两端(即，第二节点N2和第一节点N1)。因此，跨存储电容器Cst的电压被复位。第一和第二参考电压Vref和Vint可以相等或不相等，只要其不使驱动晶体管T0开启即可。一般地，Vref和Vint之间的差值不应太大，以避免对存储电容器Cst的过度充电。
在写入阶段P2期间，第一扫描线S[n-1]上信号无效，第二扫描线S[n]上的信号有效，并且发光控制线EM[n]上的信号无效。第三晶体管 T3被开启，将数据线D[m]上的数据电压Vdata传送至第二节点N2。同时，第四晶体管T4也被开启，将第一节点N1与第三节点N3相导通。因此，驱动晶体管T0处于二极管连接状态，其中其栅-源电压Vgs等于其阈值电压Vth。由于其源极电压Vs为第一电源ELVDD供应的第一电源电压Vdd，故驱动晶体管T0的栅极电压Vg(即，第一节点N1处的电位)为(Vdd+Vth)。
在发光阶段P3期间，第一扫描线S[n-1]上信号无效，第二扫描线S[n]上的信号无效，并且发光控制线EM[n]上的信号有效。第五晶体管T5被开启，将第一参考电压源VREF供应的第一参考电压Vref传送到第二节点N2。因此，第二节点N2处的电位从写入阶段P2期间的Vdata跳变至Vref，变化量为(Vref-Vdata)。由于存储电容器Cst的自举效应，第一节点N1处的电位也会产生相同程度的变化，也即，其变为(Vdd+Vth+Vref-Vdata)。同时，第六晶体管T6也被开启，提供从第一电源ELVDD到第二电源ELVSS的电流流动路径。流过发光器件OLED的驱动电流Id计算为：
Id＝K(Vgs-Vth) 2
＝K(Vdd+Vth+Vref-Vdata-Vdd-Vth) 2
＝K(Vref-Vdata) 2                         (1)
其中，K为预定的系数，其典型地可以被认为是常数。从等式(1)可见，驱动电流Id与第一参考电源VREF供应的参考电压Vref有关。因此，参考电平Vref因串扰而发生的跳变可以引起驱动电流Id和因此发光器件OLED的发光亮度的相应变化，对显示效果造成影响。然而，如上所述的，在像素电路200或300中，参考电平Vref的改变所引起的驱动电流Id的改变通过提供补偿电容器Cco而被抑制，从而降低串扰影响。
将理解的是，虽然在上面的实施例中各晶体管被图示和描述为P型晶体管，但是N型晶体管是可能的。在N型晶体管的情况下，栅极开启电压具有高电平，并且栅极关断电压具有低电平。作为示例，各晶体管可以是薄膜晶体管，其典型地被制作使得它们的第一和第二电极可互换地使用。
图5示出了一种可能的像素电路500，其中各晶体管为N型晶体管。在图2、图3和图5中，相同的参考符号指示相同的元件。像素电 路500的配置与前面关于图2和图4描述的像素电路200的那些是类似的，只不过在像素电路500中，驱动晶体管T0连接在第三节点N3与第二电源ELVSS之间(其漏极连接到第三节点N3并且其源极连接到第二电源ELVSS)并且发光器件OLED连接在第一电源ELVDD与第三节点N3之间。替换地，类似于像素电路300，在像素电路500中补偿电容器Cco可以连接在第一节点N1与第三节点N3之间。
还将理解的是，本公开的概念不仅仅适用于像素电路200、300和500，而是适用于任何其他具体的像素电路，只要它的发光器件、存储电容器、驱动电路和补偿电容器遵循本文描述的要求。
图6示出了根据本公开实施例的一种显示基板600的局部剖面视图。图6中示出了基底610。形成在基底610上的是驱动晶体管T0的源极区622、有源区624和漏极区626，其中源极区622和漏极区626由有源区624间隔开(spaced apart)。驱动晶体管T0还具有栅极区628，其与有源区624在垂直方向上(vertically)间隔开。图6中还示出了具有在垂直方向上彼此相对设置的第一电极632和第二电极634的存储电容器Cst和具有在垂直方向上彼此相对设置的第一电极642和第二电极644的补偿电容器Cco。
图6所示的布置对应于图2所示的像素电路200，尽管为了图示的方便没有示出除了驱动晶体管T0、存储电容器Cst和补偿电容器Cco之外的其他元件。在图6的示例中，补偿电容器Cst的第二电极644设置在与驱动晶体管T0的漏极区626相同的层，并且由用于将漏极区626耦合到像素电路中的其他元件(在像素电路200中为第六晶体管T6)的连接线(connection wire)形成。将该连接线用作补偿电容器Cco的第二电极644可以是有利的，因为第二电极644于是可以位于原有像素电路(即不含补偿电容器Cco的像素电路)的布图面积内，使得补偿电容器Cco的存在不会导致像素电路布图面积的增加，从而促进分辨率的提高。这也可以消除对于附加导线的需要，从而减少由于例如导线重叠所致的串扰。
此外，补偿电容器Cst的第一电极642设置在与存储电容器Cst的第一电极632相同的层，并且电极642和632可以或可以不与彼此直接连接。在前者的情况下，第一电极632可以具有对应第二电极644的延伸部分作为第一电极642，其中该延伸部分与连接线644构成补偿 电容器Cco。这样，就不必为形成补偿电容器Cco而增加制备工序，从而简化工艺。
图7示出了根据本公开实施例的另一种显示基板700的局部剖面视图。图7中示出了基底710。与图6所示的配置类似，形成在基底710上的是驱动晶体管T0的源极区722、有源区724、漏极区726和栅极区728。图7中还示出了具有第一电极732和第二电极734的存储电容器Cst和具有第一电极742和第二电极744的补偿电容器Cco。
显示基板700不同于显示基板600在于，显示基板700对应于图3所示的像素电路300。如图7所示，补偿电容器Cco的第一电极742设置在与存储电容器Cst的第二电极734相同的层。显示基板700的其他配置可以与上面关于图6描述的显示基板600的那些相同，并且因此为了简洁起见在此被省略。
在显示基板600或700中，存储电容器Cst的第二电极634或734被示例性地示出为设置在与驱动晶体管T0的栅极区628或728相同的层，尽管本公开不限于此。例如，第二电极634或734可以设置在与像素电路的其它结构(如驱动晶体管的源漏极)相同的层。又例如，第二电极634或734可与驱动晶体管T0的栅极区628或728直接相连。
在显示基板600或700中，充当存储电容器Cco的第二电极644或744的连接线可以由掺杂半导体材料制成。在一个实现方式中，在形成驱动晶体管T0的有源区624或724时，在该有源区外部也保留半导体层并进行掺杂(如轻掺杂)，使其具有良好的导电性。于是，该掺杂的半导体层可以用作为连接线，也就是第二电极644或744。
将理解的是，虽然在图6或7中未指示出，在栅极区728与有源区724之间、在存储电容器Cst的第一和第二电极之间、以及在补偿电容器Cco的第一和第二电极之间存在绝缘层，其详细描述出于简洁起见在此被省略。
图8为根据本公开实施例的一种显示装置800的框图。参见图8，显示装置800包括显示基板810、第一扫描驱动器802、第二扫描驱动器804、数据驱动器806和电压生成器808。
显示基板810包括n×m个像素P。每个像素P可以采取例如上面关于图2至5描述的像素电路200、300或500的形式。显示基板810包括以第一方向(在图中为行方向)布置以传送扫描信号的n+1条扫 描线S1，S2，…，Sn，Sn+1；以与第一方向交叉的第二方向(在图中为列方向)布置以传送数据信号的m条数据线D1，D2，…，Dm；以第一方向布置以传送发光控制信号的n条发光控制线EM1，EM2，…，EMn；以及用于施加第一和第二电源电压Vdd，Vss以及第一和第二参考电压Vref，Vinit的电线(未示出)。n和m是自然数。
第一扫描驱动器802连接至扫描线S1，S2，…，Sn，Sn+1，以将扫描信号施加至显示基板810。
第二扫描驱动器804连接至发光控制线EM1，EM2，…，EMn，以将发光控制信号施加至显示基板810。
数据驱动器806连接至数据线D1，D2，…，Dm，以将数据信号施加至显示基板810。这里，数据驱动器106在写入阶段P2期间将数据电压供给显示基板810中的各像素P，如上面关于图4描述的。
电压生成器808，其可以充当如上面实施例中描述的第一电源ELVDD、第二电源ELVSS、第一参考电源VREF和第二参考电源VINT，生成各个像素P所需的第一电源电压Vdd、第二电源电压Vss、第一参考电压Vref和第二参考电压Vinit。电压生成器808的示例包括但不限于DC/DC转换器和低压差稳压器(LDO)。
该显示装置800可以是显示面板、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
虽然在附图和和前面的描述中已经详细地说明和描述了本公开，但是这样的说明和描述应当被认为是说明性的和示意性的，而非限制性的；本公开不限于所公开的实施例。

Claims (15)

  1. 一种像素电路，包括：
    发光器件；
    驱动电路，用于响应于第一节点处的电位而控制从第一电源供应给所述发光器件的驱动电流的量值；
    存储电容器，用于响应于第二节点处的电位的改变而引起所述第一节点处的电位的改变，其中所述第二节点处的电位可在来自第一参考电源的第一参考电压与来自数据线的数据电压之间切换；以及
    补偿电容器，用于抑制由所述第一参考电压的改变引起的所述驱动电流的改变。
  2. 根据权利要求1所述的像素电路，其中：
    所述发光器件连接在所述第一电源与第二电源之间；
    所述驱动电路包括与所述发光器件串联连接的驱动晶体管，其中所述驱动晶体管具有连接到所述第一节点的栅极；
    所述存储电容器连接在所述第二节点与所述第一节点之间；并且
    所述补偿电容器连接在所述第一节点或所述第二节点之一与所述第三节点之间。
  3. 根据权利要求2所述的像素电路，其中所述驱动晶体管为P型晶体管，其连接在所述第一电源与所述第三节点之间，并且其中所述发光器件连接在所述第三节点与所述第二电源之间。
  4. 根据权利要求2所述的像素电路，其中所述驱动晶体管为N型晶体管，其连接在所述第三节点与所述第二电源之间，并且其中所述发光器件连接在所述第一电源与所述第三节点之间。
  5. 根据权利要求2所述的像素电路，还包括：
    复位电路，被配置成响应于第一扫描线上的信号有效而将来自所述第一参考电源的所述第一参考电压供应给所述第二节点并且将来自第二参考电源的第二参考电压供应给所述第一节点；
    写入电路，被配置成响应于第二扫描线上的信号有效而将来自所述数据线的所述数据电压供应给所述第二节点并且将所述第一节点与所述第三节点导通；以及
    发光控制电路，被配置成响应于发光控制线上的信号有效而将来 自所述第一参考电源的所述第一参考电压供应给所述第二节点并且提供允许所述驱动电流经由所述发光器件和所述驱动晶体管从所述第一电源流动到所述第二电源的路径。
  6. 根据权利要求5所述的像素电路，其中所述复位电路包括：
    第一晶体管，其具有连接到所述第一扫描线的栅极、连接到所述第一参考电源的第一电极、以及连接到所述第二节点的第二电极；和
    第二晶体管，其具有连接到所述第一扫描线的栅极、连接到所述第二参考电源的第一电极、以及连接到所述第一节点的第二电极。
  7. 根据权利要求5所述的像素电路，其中所述写入电路包括：
    第三晶体管，其具有连接到所述第二扫描线的栅极、连接到所述数据线的第一电极、以及连接到所述第二节点的第二电极；和
    第四晶体管，其具有连接到所述第二扫描线的栅极、连接到所述第一节点的第一电极、以及连接到所述第三节点的第二电极。
  8. 根据权利要求5所述的像素电路，其中所述发光控制电路包括：
    第五晶体管，其具有连接到所述发光控制线的栅极、连接到所述第一参考电源的第一电极、以及连接到所述第二节点的第二电极；和
    第六晶体管，其具有连接到所述发光控制线的栅极、连接到所述发光器件的第一电极、以及连接到所述第三节点的第二电极。
  9. 根据前述权利要求中任一项所述的像素电路，其中所述发光器件选自由有机发光二极管和微型无机发光二极管组成的组。
  10. 一种显示基板，包括：
    多条扫描线，用于传送扫描信号；
    多条发光控制线，用于传送发光控制信号；
    多条数据线，用于传送数据电压；以及
    多个像素，布置在阵列中，所述像素中的每一个包括：
    发光器件；
    驱动电路，用于响应于第一节点处的电位而控制从第一电源供应给所述发光器件的驱动电流的量值；
    存储电容器，用于响应于第二节点处的电位的改变而引起所述第一节点处的电位的改变，其中所述第二节点的电位可在来自第一参考电源的第一参考电压与来自所述多条数据线中的对应一条数据线的数据电压之间切换；以及
    补偿电容器，用于抑制由所述第一参考电压的改变引起的所述驱动电流的改变。
  11. 根据权利要求10所述的显示基板，还包括其上形成所述多个像素的基底，
    其中所述驱动电路包括驱动晶体管，其具有形成在所述基底上的源极区、漏极区和有源区以及与所述有源区在垂直方向上间隔开的栅极区，所述源极区和所述漏极区由所述有源区间隔开，
    其中所述存储电容器具有在垂直方向上彼此相对设置的第一电极和第二电极，
    其中所述补偿电容器具有在垂直方向上彼此相对设置的第一电极和第二电极，所述补偿电容器的所述第一电极设置在与所述存储电容器的所述第一电极或所述第二电极之一相同的层，并且
    其中所述补偿电容器的所述第二电极由到所述驱动晶体管的所述漏极区的连接线形成。
  12. 根据权利要求11所述的显示基板，其中所述补偿电容器的所述第一电极设置在与所述存储电容器的所述第一电极相同的层并且连接到所述存储电容器的所述第一电极。
  13. 根据权利要求11所述的显示基板，其中所述补偿电容器的所述第一电极设置在与所述存储电容器的所述第二电极相同的层并且连接到所述存储电容器的所述第二电极。
  14. 根据权利要求11所述的显示基板，其中所述连接线由掺杂半导体材料制成并且设置在与所述驱动晶体管的所述有源区相同的层。
  15. 一种显示装置，包括：
    如权利要求10所述的显示基板；
    第一扫描驱动器，用于向所述多条扫描线供应所述扫描信号；
    第二扫描驱动器，用于向所述多条发光控制线供应所述发光控制信号；以及
    数据驱动器，用于向所述多条数据线供应所述数据电压。
PCT/CN2018/074694 2017-07-27 2018-01-31 像素电路、显示基板和显示装置 Ceased WO2019019590A1 (zh)

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CN116547740A (zh) * 2021-09-29 2023-08-04 京东方科技集团股份有限公司 像素驱动电路及像素驱动方法、显示面板
CN116547740B (zh) * 2021-09-29 2026-03-10 京东方科技集团股份有限公司 像素驱动电路及像素驱动方法、显示面板
US12579941B2 (en) 2021-09-29 2026-03-17 Boe Technology Group Co., Ltd. Pixel driving circuit and display panel

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CN109308872B (zh) 2021-08-24
EP3660826A4 (en) 2021-07-14
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US20210183308A1 (en) 2021-06-17
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