WO2019019865A1 - 一种多分区动态背光驱动方法及显示装置 - Google Patents

一种多分区动态背光驱动方法及显示装置 Download PDF

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Publication number
WO2019019865A1
WO2019019865A1 PCT/CN2018/093847 CN2018093847W WO2019019865A1 WO 2019019865 A1 WO2019019865 A1 WO 2019019865A1 CN 2018093847 W CN2018093847 W CN 2018093847W WO 2019019865 A1 WO2019019865 A1 WO 2019019865A1
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Prior art keywords
signal
level signal
level
frame synchronization
change edge
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English (en)
French (fr)
Inventor
杜强
张玉欣
蔡廷柯
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Qingdao Hisense Electronics Co Ltd
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Qingdao Hisense Electronics Co Ltd
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Priority to EP18839023.1A priority Critical patent/EP3660830B1/en
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/3406—Control of illumination source
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/12—Synchronisation between the display unit and other units, e.g. other display units, video-disc players
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0626—Adjustment of display parameters for control of overall brightness
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0626—Adjustment of display parameters for control of overall brightness
    • G09G2320/064—Adjustment of display parameters for control of overall brightness by time modulation of the brightness of the illumination source
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas
    • G09G2340/0435—Change or adaptation of the frame rate of the video stream

Definitions

  • the present disclosure relates to the field of backlight display technologies, and in particular, to a multi-partition dynamic backlight driving method and a display device.
  • the backlight is divided into a plurality of independent partitions, and the backlight of each partition can be adjusted in real time according to the brightness and darkness of the picture, so that the displayed picture is bright and dark, and the picture is clearer and brighter.
  • a multi-partition dynamic backlight driving method including:
  • the driving chip receives the first level signal and the second level signal, and generates a PWM signal according to the first level signal and the second level signal.
  • another multi-partition dynamic backlight driving method including:
  • the total duration of the first level signal and the second level signal is the change edge and the change 1/m along the length of the previous first change edge, wherein the change edge is a same direction change edge as the first change edge before the change edge; m is a positive integer;
  • the driving chip receives the first level signal and the second level signal, and generates a PWM signal according to the first level signal and the second level signal.
  • a multi-partition dynamic backlight driving method including:
  • a first level signal having a duration of nT1 is generated, and a second level is generated during a period from the end of the first level signal to the next detection of the change edge.
  • T1 is a period of the target signal, and n is determined by a multiple relationship between the third frame synchronization signal and a period of the target signal;
  • a display device including:
  • nonvolatile memory a nonvolatile memory, a scan chip, a frequency multiplier processor, and a driver chip storing a computer readable program
  • the scan chip is configured to: read a computer readable program in the nonvolatile memory and perform receiving a frame sync signal corresponding to the input image signal;
  • the frequency multiplier processor is configured to: read a computer readable program in the nonvolatile memory and execute a first level signal that outputs a first duration to the driver chip in response to a change edge of the first frame sync signal And outputting a second second time to the driving chip alternately after generating the first level signal in response to the change edge until the first change edge after the change edge in the first frame synchronization signal is detected a level signal and a first level signal of a first duration, a signal frequency of the signal formed by the first level signal and the second level signal alternately outputting is the change in the first frame synchronization signal a m-fold of a frequency formed along a first change edge before the change edge, wherein the change edge is a same-direction change edge with the first change edge before the change edge; m is a positive integer;
  • the driving chip is configured to receive the first level signal and the second level signal, and generate a PWM signal according to the first level signal and the second level signal.
  • a display device including:
  • nonvolatile memory a nonvolatile memory, a scan chip, a frequency multiplier processor, and a driver chip storing a computer readable program
  • the scan chip is configured to: read a computer readable program in the nonvolatile memory and perform receiving a frame sync signal corresponding to the input image signal;
  • the frequency multiplier processor is configured to: read a computer readable program in the non-volatile memory and perform alternately outputting the first level signal and the second level signal in response to a change edge of the first frame synchronization signal And the total duration of the first level signal and the second level signal is 1/m of the duration between the change edge and the first change edge before the change edge, wherein the change edge The first change edge before the change along the change is the same direction change edge; m is a positive integer;
  • the driving chip is configured to receive the first level signal and the second level signal, and generate a PWM signal according to the first level signal and the second level signal.
  • a display device including:
  • a nonvolatile memory a frequency multiplier processor storing a computer readable program
  • the frequency multiplier processor is configured to: read a computer readable program in the non-volatile memory and perform acquisition of a frame synchronization signal conforming to a processor output standard; generate a change edge of the frame synchronization signal when generated a first level signal having a duration of nT1, generating a second level signal during a period from the end of the first level signal to the next detection of the change edge, wherein T1 is a period of the target signal, n is the frame Determining a relationship between a synchronization signal and a period of the target signal; transmitting the first level signal and the second level signal to a driving chip, so that the driving chip is based on the first level signal and the second The level signal generates a PWM signal.
  • 1 is a schematic diagram of signal timing disclosed by the related art
  • FIG. 2 is a schematic diagram of a working flow of a multi-partition dynamic backlight driving method according to an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of a workflow of another multi-partition dynamic backlight driving method according to an embodiment of the present disclosure
  • FIG. 4 is a schematic diagram of signal timing in a multi-partition dynamic backlight driving method according to an embodiment of the present disclosure
  • FIG. 5 is a schematic diagram of a working flow of still another multi-partition dynamic backlight driving method according to an embodiment of the present disclosure
  • FIG. 6 is a schematic diagram of a workflow of another multi-partition dynamic backlight driving method according to an embodiment of the present disclosure
  • FIG. 7 is a schematic diagram of signal timing in the multi-partition dynamic backlight driving method shown in FIG. 6;
  • FIG. 8 is a schematic structural diagram of a display device according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of a signal acquisition module in a display device according to an embodiment of the present disclosure.
  • the frequency multiplier processor acquires a frame synchronization signal (ie, a vertical synchronization, a Vsync signal) transmitted by the scan chip, and performs corresponding processing thereon, and then processes the image.
  • the frame synchronization signal generated by the multiplier processor is transmitted to the driving chip; after receiving the frame synchronization signal output by the multiplier processor, the driving chip generates a corresponding PWM (Pulse Width Modulation) according to the frame synchronization signal output by the frequency multiplier processor. Width modulation) signal, and drive the display to perform corresponding backlight display according to the PWM signal, thereby realizing the playback of the television.
  • PWM Pulse Width Modulation
  • the first row of waveforms is a waveform of a first frame synchronization signal output by the scan chip to the frequency multiplier processor, wherein the frequency of the signal is 50/60 Hz, which shows a process of converting from 60 Hz to 50 Hz;
  • the waveform of the second frame is the waveform of the second frame synchronization signal outputted by the frequency multiplying processor to the PWM driving chip, and the waveform is transmitted to the driving chip by the frequency multiplying processor, wherein the second frame synchronization after the frequency multiplication processing
  • the frequency of the signal is usually above 100/120 Hz.
  • the multiplier processor is triggered by the first frame synchronization signal to generate a second frame synchronization signal.
  • the frequency multiplier processor receives the first frame. After the rising edge or falling edge of the sync signal, the pulse of the second frame sync signal is output within the preset time, so the system is switched during the TV playback, resulting in large frequency interference between the signals of 100 Hz and 120 Hz.
  • Figure 1 shows the process of converting from 120HZ to 100HZ; this greatly reduces the period between the last pulse of the 120HZ signal and the first pulse of 100HZ, the corresponding frequency is higher, the first
  • the three-line waveform is the PWM signal generated by the driving chip, and the PWM signal between the last pulse corresponding to the 120HZ signal and the first pulse of 100HZ has the last pulse of the 120HZ signal and the first pulse of 100HZ.
  • the frequency corresponding to the period forms a sudden change in the duty cycle. In this case, the PWM signal of the abrupt area causes the backlight to flash back.
  • Some embodiments of the present disclosure disclose a multi-partition dynamic backlight driving method to solve the problem in the related art that a backlight flicker occurs during playback of a television.
  • a first embodiment of the present disclosure discloses a multi-partition dynamic backlight driving method, which is generally applied to a frequency multiplier processor provided in a television, which uses a multi-partition dynamic backlight technology.
  • the frequency multiplier processor is connected to a scan chip and a driver chip mounted in the television.
  • the multiplier processor is usually an MCU (Microcontroller Unit). Of course, the multiplier processor can also be other devices.
  • the multi-partition dynamic backlight driving method disclosed in the embodiment of the present disclosure includes the following steps:
  • Step S11 Acquire a third frame synchronization signal that conforms to the output standard of the frequency multiplier processor.
  • the scan chip connected to the frequency multiplier processor transmits a first frame sync signal to the frequency multiplier processor, and the frequency multiplier processor acquires a third frame sync signal conforming to the output standard of the frequency multiplier processor according to the first frame sync signal .
  • the frequency of the frame synchronization signal conforming to the output standard of the multi-frequency processor is usually 100/120 Hz or more.
  • the scan chip may be a SoC (System on Chip) for acquiring a first frame synchronization signal according to the input image and transmitting the first frame synchronization signal to the frequency multiplier processor.
  • SoC System on Chip
  • the scanning chip can also be other types of chips, which are not limited by the embodiments of the present disclosure.
  • Step S12 When detecting a change edge of the third frame synchronization signal, outputting a first level signal with a duration of nT1, generating a first time period from the end of the first level signal to the next detection of the change edge A two-level signal, wherein T1 is a period of the target signal, and n is determined by a multiple relationship between the third frame synchronization signal and a period of the target signal.
  • the frequency multiplier processor can acquire the first frame synchronization signal through the scan chip, and the frequency multiplier processor can also acquire other types of signals.
  • the target signal can be selected from other types of signals, and the period of the target signal is There is a fixed multiple relationship between the periods of the third frame sync signal that conform to the multiplier processor output standard.
  • the period of the third frame synchronization signal that meets the output standard of the multiplier processor is set to be n times the period of the target signal.
  • the first level signal is generated from the time period from the first time to the second time, wherein the first time The duration to the second moment is nT1.
  • the first level signal is typically a level signal that is maintained for a longer time in the second frame sync signal.
  • the signal of the same period is composed of a high level signal and a low level signal, and the time of the two level signals is often different.
  • a level signal in which a longer time is maintained is generally used as the first level signal, and the first level signal is different from the second level signal. That is to say, if the high level of the second frame sync signal output by the frequency multiplier processor is longer, the first level signal is a high level signal, and correspondingly, the second level signal is a low level signal. If the hold time of the low level in the second frame sync signal is long, the first level signal is a low level signal, and correspondingly, the second level signal is a high level signal.
  • the total duration of the adjacent one of the first level signal and the second level signal is nT1.
  • the varying edge is a rising or falling edge.
  • the frame synchronization signal is sometimes interspersed with an interference signal, which usually has a large frequency and a small period.
  • an interference signal which usually has a large frequency and a small period.
  • the period of setting the frame synchronization signal is n times of the period of the target signal, and T1 is the period of the target signal, nT1 should be the frame synchronization signal in the normal state (ie, the frame synchronization signal). The period in the case where no interference signal occurs.
  • the duration of the second level has a small influence on the signal period, and in some embodiments, the duration of one first level and the adjacent one second level may also be made.
  • the sum of the durations is taken as a cycle.
  • the first level signal and the second level signal together constitute a second frame synchronization signal.
  • step S12 when the change edge of the third frame synchronization signal is detected, timing is started, and the first level signal is started to be generated, and the first level signal is maintained for a duration of nT1, and the second time to the next time.
  • a second level signal is generated during a period in which a change edge of the third frame sync signal is detected.
  • the first level signal and the second level signal are periodically generated, and the duration of the first level signal is maintained (ie, nT1) is the period of the third frame synchronization signal in the normal state, and thus the first The period of the level signal and the second level signal is close to the period of the third frame sync signal in the normal state, and the influence of the interference signal can be avoided.
  • the third frame synchronization signal corresponding to the first frame synchronization signal (60HZ) before the change is 1/120 second, and the duration of the first level signal and the duration of the second level signal are continued. And equal to or close to 1/120 second.
  • the third frame synchronization signal corresponding to the changed first frame synchronization signal (50HZ) is 1/100 second, and the sum of the duration of the first level signal and the duration of the second level signal is equal to or close to 1/. 100 seconds.
  • Step S13 transmitting the first level signal and the second level signal to the driving chip, so that the driving chip generates a PWM signal according to the first level signal and the second level signal.
  • the first level signal and the second level signal are generated according to the third frame synchronization signal that meets the output standard of the frequency multiplier processor, and the first level signal and the second level signal are transmitted to The chip is driven so that the driving chip generates a corresponding PWM signal according to the first level signal and the second level signal.
  • the period of the first level signal and the second level signal is close to the period of the third frame synchronization signal in the normal state, so that the influence of the interference signal can be avoided, and the phenomenon of backlight flicker is reduced.
  • step S11 the operation of acquiring the frame synchronization signal conforming to the output standard of the frequency multiplier processor is disclosed by step S11.
  • the operation generally includes the following steps:
  • Step S111 Receive a first frame synchronization signal transmitted by the scan chip.
  • Step S112 determining whether the frequency of the first frame synchronization signal meets the frequency multiplier output standard, and if not, performing the operation of step S113, and if yes, performing the operation of step S12;
  • Step S113 If the frequency of the first frame synchronization signal does not meet the output frequency multiplier output standard, perform frequency multiplication processing on the first frame synchronization signal, so that the third frame synchronization signal generated after the frequency multiplication processing conforms to the The frequency multiplier processor outputs a standard, and then the operation of step S12 is performed.
  • the scan frequency of the scan chip is generally 50/60 Hz, and in the TV using the multi-partition dynamic backlight technology, the frame sync signal output by the multiplier processor is usually 100/120 Hz or above, that is, the multi-frequency processor output is met.
  • the frequency of a standard frame sync signal is typically 100/120 Hz or above.
  • the frequency multiplier processor can determine that the frequency of the first frame synchronization signal does not conform to the frequency multiplier output standard, thereby performing frequency multiplication processing.
  • step S12 if the first frame synchronization signal transmitted by the scan chip to the multiplier processor conforms to the multi-frequency processor output standard, the multi-frequency processor does not need to perform frequency multiplication processing, and performs the first frame synchronization signal as the third frame synchronization signal. The operation of step S12 is sufficient.
  • the first row of waveforms is a first frame synchronization signal transmitted by the scan chip to the frequency multiplier processor, and the frequency of the first frame synchronization signal is 50/60 Hz.
  • the frequency multiplier processor After receiving the first frame synchronization signal, the frequency multiplier processor multiplies the first frame synchronization signal to conform to the multiplier processor output standard, and the third frame synchronization signal after the frequency multiplication processing (ie, conforms to the multiplication frequency
  • the processor outputs a standard frame sync signal) of 100/120 Hz to form a second line of waveform.
  • an interference signal is also included.
  • the level signal whose duration is long in the third frame synchronization signal is a low level signal, and the first level signal is usually selected as a low level signal.
  • the change edge of the third frame sync signal is set as the rising edge of the third frame sync signal.
  • a low level signal i.e., the first level signal
  • the low level signal is maintained for nT1.
  • a high level signal i.e., a second level signal
  • the waveform of the third row is the waveform of the first level signal and the second level signal, and the waveform of the third row is also the waveform output by the frequency multiplier processor to the driving chip, that is, the second frame synchronization signal.
  • the interference signal is not interposed in the first level signal and the second level signal, so that the influence of the interference signal can be avoided.
  • the waveform of the PWM signal generated by the driving chip is as shown in the waveform of the fourth row in FIG. 4, and the region where the duty ratio is abrupt is no longer present in the waveform of the fourth row, so that the phenomenon of backlight flicker can be reduced.
  • the frequency multiplier processor can acquire the first frame synchronization signal through the scan chip, and the frequency multiplication processor can also acquire other various types of signals.
  • the target signal can be selected from other types of signals.
  • the period of the target signal has a fixed multiple relationship with the period of the frame sync signal that conforms to the output of the multiplier processor.
  • the target signal can be a line sync signal (ie, an Hsync signal).
  • the period of the third frame synchronization signal conforming to the output standard of the multiplier processor is usually 4096 times the period of the line synchronization signal.
  • the value of n is 4096.
  • the Hsync line sync signal refers to a sync signal that controls each row of liquid crystal molecules during display.
  • the multi-partition dynamic backlight driving method includes the following steps:
  • Step S21 Acquire a third frame synchronization signal that conforms to the output standard of the frequency multiplier processor.
  • Step S22 After acquiring the third frame synchronization signal that meets the output standard of the frequency multiplier processor, detecting whether there is an interference signal in the third frame synchronization signal, and if yes, performing the operation of step S23, and if not, performing the operation of step S25. .
  • Step S23 If it is determined that there is an interference signal in the third frame synchronization signal, when detecting a change edge of the third frame synchronization signal, generating a first level signal with a duration of nT1, ending at the first level signal A second level signal is generated during a time period in which the change edge is detected next, wherein T1 is a period of the target signal, and n is determined by a multiple relationship between the third frame synchronization signal and a period of the target signal.
  • Step S24 transmitting the first level signal and the second level signal to the driving chip, so that the driving chip generates a PWM signal according to the first level signal and the second level signal.
  • step S23 to the step S24 is the same as the implementation process of the step S12 to the step S13 in the foregoing embodiment, and may be referred to each other, and details are not described herein again.
  • Step S25 ending the operation.
  • the subsequent operation is performed, thereby reducing the burden on the frequency multiplier processor.
  • the frequency of the interference signal is usually greater than the frequency multiplier output standard. In this case, in the embodiment of the present disclosure, if it is detected that the third frame synchronization signal has a signal with a large frequency, it is generally determined that the interference signal is detected.
  • the first level signal and the second level signal have not been generated after the third frame sync signal is acquired, and before the change edge of the third frame sync signal is detected.
  • the multiplier processor generates an initial level signal that conforms to the output standard of the multiplier processor. For example, if the output standard of the multiplier processor is 100/120 Hz, the frequency of the initial level signal may be 100 or 120 Hz.
  • FIG. 6 the method includes the following steps:
  • Step S31 Receive a first frame synchronization signal corresponding to the input image signal.
  • Step S32 Output a third level signal of the first duration to the driving chip in response to the changing edge of the first frame synchronization signal.
  • Step S33 alternately output the second duration to the driving chip after generating the third level signal in response to the change, until the first change edge after the change edge in the first frame synchronization signal is detected a fourth level signal and a third level signal of the first duration, the signal frequencies of the signals formed by the third level signal and the fourth level signal alternately outputted are in the first frame synchronization signal
  • the change is m times the frequency formed by the first change edge before the change edge, wherein the change edge is the same change edge along the first change edge before the change edge; m is a positive integer .
  • steps S32, S33 may be further replaced by: sequentially outputting a third level signal and a fourth level signal in response to a change edge of the first frame synchronization signal, the third power
  • the total duration of the flat signal and the fourth level signal is 1/m of the duration between the change edge in the first frame sync signal and the first change edge before the change edge, wherein The change edge is the same change edge along the first change edge before the change edge; m is a positive integer.
  • the third level signal may be a high level signal or a low level signal and is not limited by its duration.
  • the change edge in the same direction as the change edge before the change edge refers to a change trend of the change edge and a first change before the change edge.
  • the trend along the same trend is the same.
  • Step S34 The driving chip receives the third level signal and the fourth level signal, and generates a PWM signal according to the third level signal and the fourth level signal.
  • generating the PWM signal according to the third level signal and the fourth level signal includes: generating a second frame synchronization signal formed by the frequency and the third level signal and the fourth level signal PWM signals of the same frequency.
  • the method before the change edge of the first frame synchronization signal is detected for the first time, the method further includes: outputting an initial level signal to the driving chip; and driving the chip to receive the initial level signal, and A corresponding PWM signal is generated based on the initial level signal.
  • the level of the initial level signal is different from the level of the third level signal. In some embodiments of the present disclosure, the level of the initial level signal is a low level, the level of the third level signal is a high level, and the level of the fourth level signal is a low level Level.
  • a third level signal of the first duration is then output in response to the subsequent change along the change of the frame sync signal.
  • the embodiments of the present disclosure are described below: Referring to FIG. 7, three rows of waveforms are included in FIG. Wherein, the first row of waveforms is a first frame synchronization signal (Vsync signal) corresponding to the input image signal, and in some embodiments, the frequency of the first frame synchronization signal is 50/60 Hz.
  • Vsync signal first frame synchronization signal
  • the third level signal as a high level and the fourth level signal being a low level as an example
  • responding to the change edge of the first frame synchronization signal may be a falling edge or a rising edge of the pulse b, here taking a rising edge as an example
  • outputting a high level signal b of a first duration to the driving chip after generating a high level signal d in response to a rising edge of the pulse b, a pulse is detected
  • the driving chip alternately outputs a low level e, a high level f, etc., wherein the low level e, the low level g, and the low
  • the level i is a low level that lasts for the same duration
  • the high level d, the high level f, and the high level h are high levels of the same duration
  • the high level signal d and the low level e of the alternate output are
  • the signal frequency of the signal is m times the frequency formed by the change edge (ie, the rising edge of the pulse b) and the first change edge (ie, the rising edge of the pulse a) before the change edge, wherein the change edge
  • the first change edge before the change edge is a change in the same direction;
  • m is a positive integer.
  • m has a value of 2. Thereby a second line of waveform is formed.
  • the waveform of the second row is the waveform of the third level signal and the fourth level signal, and the waveform of the second row is also the waveform of the second frame synchronization signal output by the frequency multiplier processor to the driving chip;
  • the frequency of the one frame sync signal changes, in response to the change edge of the first frame sync signal (which may be the falling edge or the rising edge of the pulse c, here taking the rising edge as an example), the low level i of the previous cycle is followed.
  • the high-level signal j of the first duration is output to the driving chip; the first change edge after the rising edge of the pulse c is detected after the high-level signal j is generated in response to the rising edge of the pulse c (ie, the rising edge of the pulse l), the low-level k and the high level are alternately output to the driving chip, and the signal frequency of the signal composed of the high-level signal j and the low-level k which are alternately outputted is the changed edge (ie, The rising edge of the pulse c is m times the frequency formed by the first change edge (i.e., the rising edge of the pulse b) before the change edge.
  • the waveform of the PWM signal generated by the driving chip is as shown in the waveform of the third row in Fig. 7, and the region where the duty ratio is abrupt is no longer present in the waveform of the third row, so that the phenomenon of backlight flicker can be reduced.
  • the display device includes: a signal acquisition module 100, a signal generation module 200, and a driving chip 300.
  • the signal acquisition module 100 and the signal generation module 200 are both located in a frequency multiplier processor.
  • the signal acquisition module 100 is configured to acquire a third frame synchronization signal that meets an output standard of the frequency multiplier processor.
  • the signal acquisition module 100 acquires a third frame synchronization signal that conforms to the output standard of the frequency multiplier processor according to the first frame synchronization signal.
  • the frequency of the third frame synchronization signal conforming to the output standard of the frequency multiplier processor is usually above 100/120 Hz.
  • the signal generating module 200 is configured to generate a first level signal with a duration of nT1 when detecting a change edge of the third frame synchronization signal, and ending the first level signal until the next detection of the change edge During the time period, a second level signal is generated, wherein T1 is a period of the target signal, and n is determined by a multiple relationship between the third frame synchronization signal and a period of the target signal.
  • the signal acquisition module 100 can acquire a first frame synchronization signal, and the signal acquisition module 100 can also acquire other types of signals.
  • a target signal can be selected from other types of signals, the target signal
  • the period has a fixed multiple relationship with the period of the third frame sync signal that conforms to the multiplier processor output standard.
  • the signal generating module 200 is further configured to set a period of the third frame synchronization signal that meets the output standard of the frequency multiplier processor to be n times of a period of the target signal. In addition, if it is set that the time when the change edge of the third frame synchronization signal is detected is the first time, the signal generating module 200 generates the first level signal from the time period from the first time to the second time. Wherein, the duration from the first moment to the second moment is nT1.
  • the first level signal is typically a level signal that is maintained for a longer time in the second frame sync signal.
  • the signal of the same period is composed of a high level signal and a low level signal, and the time of the two level signals is often different.
  • a level signal in which a longer time is maintained is generally used as the first level signal, and the first level signal is different from the second level signal. That is, if the high level of the second frame sync signal is longer, the first level signal is a high level signal, and correspondingly, the second level signal is a low level signal; if the second frame is synchronized When the low level of the signal is maintained for a long time, the first level signal is a low level signal, and correspondingly, the second level signal is a high level signal.
  • the varying edge is a rising or falling edge.
  • the third frame synchronization signal is sometimes interspersed with an interference signal, which usually has a large frequency and a small period.
  • an interference signal which usually has a large frequency and a small period.
  • the period of setting the third frame synchronization signal is n times of the period of the target signal, and T1 is the period of the target signal, nT1 should be the third frame synchronization signal in a normal state (ie, The period in the case where no interference signal appears in the frame synchronization signal.
  • the driving chip 300 is configured to generate a PWM signal according to the first level signal and the second level signal.
  • the signal acquisition module 100 disclosed in the embodiment of the present disclosure includes:
  • the receiving unit 101 is configured to receive a first frame synchronization signal transmitted by the scan chip.
  • the determining unit 102 is configured to determine whether the frequency of the first frame synchronization signal meets a frequency multiplier output standard
  • the frequency multiplication processing unit 103 is configured to perform frequency multiplication processing on the first frame synchronization signal if the frequency of the first frame synchronization signal does not meet the frequency multiplication processor output standard, so that the third frame after the frequency multiplication processing The sync signal conforms to the multiplier processor output standard.
  • the scanning frequency of the scanning chip is generally 50/60 Hz, and in the television using the multi-partition dynamic backlight technology, the third frame synchronization signal output by the frequency multiplier processor is usually 100/120 Hz or more, that is, the frequency doubling processing is satisfied.
  • the frequency at which the standard frame sync signal is output is typically 100/120 Hz or higher.
  • the frequency multiplier processor can determine that the frequency of the original frame synchronization signal does not conform to the frequency multiplier output standard, thereby performing frequency multiplication processing.
  • the target signal may be the same as the display panel scanning frequency, and the target signal may be a horizontal synchronization signal (ie, an Hsync signal).
  • the period of the frame synchronization signal conforming to the output standard of the frequency multiplier processor is usually 4096 times the period of the line synchronization signal.
  • the value of n is 4096.
  • the multiple relationship may be different, and the value of the corresponding n may also change.
  • the target signal may be other types of signals.
  • the value of n is adjusted accordingly, which is not limited by the embodiment of the present disclosure.
  • the display device disclosed in the embodiment of the present disclosure further includes: an interference detecting module.
  • the interference detecting module is configured to detect whether an interference signal exists in the third frame synchronization signal after acquiring a third frame synchronization signal that meets an output standard of the frequency multiplier processor;
  • the interference detection module determines that an interference signal exists in the third frame synchronization signal
  • the interference detection module triggers the signal generation module to perform a corresponding operation. That is, the interference detecting module triggers the signal generating module to execute a first level signal with a duration of nT1 when the change edge of the third frame synchronization signal is detected, at the end of the first level signal to The operation of generating the second level signal during the period in which the change edge is detected next time.
  • the frequency of the interference signal is usually greater than the frequency multiplier output standard. In this case, if the interference detection module detects that the frame synchronization signal has a signal with a large frequency, it is generally determined that the interference signal is detected.
  • the method further includes:
  • An initial signal generating module configured to generate an initial level signal after acquiring a third frame synchronization signal conforming to the frequency multiplier output standard, and before detecting a change edge of the third frame synchronization signal, where The frequency of the initial level signal conforms to the output standard of the frequency multiplier processor;
  • an initial signal transmission module configured to transmit the initial level signal to the driving chip, so that the driving chip generates a corresponding PWM signal according to the initial level signal.
  • the first level signal and the second level signal have not been generated after the third frame sync signal is acquired, and before the change edge of the third frame sync signal is detected.
  • an initial level signal conforming to the output standard of the frequency multiplier processor is generated by the initial signal generation module. For example, if the output standard of the multiplier processor is 100/120 Hz, the frequency of the initial level signal may be 100 or 120 Hz.
  • a multi-partition dynamic backlight display device comprising: a non-volatile memory storing a computer readable program, at least one frequency doubling processor and a driving chip .
  • the multiplier processor is configured to execute the computer readable program to:
  • the driving chip is configured to generate a PWM signal according to the first level signal and the second level signal.
  • the frequency doubling processor executes the computer readable program to acquire a third frame synchronization signal that conforms to a frequency multiplier output standard based on the first frame synchronization signal.
  • the frequency of the frame synchronization signal conforming to the output standard of the multi-frequency processor is usually 100/120 Hz or more.
  • the frequency multiplier processor can control the scan chip to acquire an original frame synchronization signal by executing the computer readable process, and the frequency multiplier processor can also acquire other types of signals by executing the computer readable program.
  • the target signal can be selected from other types of signals having a fixed multiple relationship between the period of the target signal and the period of the frame synchronization signal conforming to the output of the frequency multiplier processor.
  • the frequency multiplier processor is further configured to execute the computer readable program to set a period of the third frame synchronization signal conforming to the frequency multiplier output standard to be n times a period of the target signal.
  • the frequency multiplier processor generates the first level signal from the time period from the first time to the second time
  • the duration from the first moment to the second moment is nT1.
  • the first level signal is typically a level signal that is maintained for a longer time in the frame sync signal.
  • the signal of the same period is composed of a high level signal and a low level signal, and the time of the two level signals is often different.
  • a level signal in which a longer time is maintained is generally used as the first level signal, and the first level signal is different from the second level signal. That is, if the high level of the second frame sync signal is longer, the first level signal is a high level signal, and correspondingly, the second level signal is a low level signal; if the second frame is synchronized When the low level of the signal is maintained for a long time, the first level signal is a low level signal, and correspondingly, the second level signal is a high level signal.
  • the varying edge is a rising or falling edge.
  • the third frame synchronization signal is sometimes interspersed with an interference signal, which usually has a large frequency and a small period.
  • an interference signal which usually has a large frequency and a small period.
  • the period of setting the third frame synchronization signal is n times of the period of the target signal, and T1 is the period of the target signal, nT1 should be the third frame synchronization signal in a normal state (ie, The period in the case where no interference signal appears in the frame synchronization signal.
  • the drive device further includes a scan chip.
  • the frequency multiplier processor is further configured to execute the computer readable program to obtain the following operations before acquiring the frame synchronization signal conforming to the frequency doubling processor output standard:
  • the first frame synchronization signal is subjected to frequency multiplication processing, so that the third frame synchronization signal generated after the frequency multiplication processing conforms to the frequency multiplication Processor output standard.
  • the scan frequency of the scan chip is generally 50/60 Hz.
  • the frame sync signal output by the multiplier processor is usually above 100/120 Hz, that is, it conforms to the output standard of the multiplier processor.
  • the frequency of the frame sync signal is usually above 100/120 Hz.
  • the frequency multiplier processor can determine that the frequency of the first frame synchronization signal does not conform to the frequency multiplier output standard, thereby performing frequency multiplication processing.
  • the target signal can be a line sync signal (ie, an Hsync signal).
  • the period of the frame synchronization signal conforming to the output standard of the frequency multiplier processor is usually 4096 times the period of the line synchronization signal.
  • the value of n is 4096.
  • the multiple relationship may be different, and the value of the corresponding n may also change.
  • the target signal may be other types of signals.
  • the value of n is adjusted accordingly, which is not limited by the embodiment of the present disclosure.
  • the frequency multiplier processor is further configured to execute the computer readable program to detect whether an interference signal exists in the third frame synchronization signal ;
  • the frequency multiplier processor performs a first level signal with a duration of nT1 when the change edge of the third frame synchronization signal is detected, at the first The operation of generating the second level signal during the period from the end of the level signal to the next detection of the change edge.
  • the frequency of the interference signal is usually greater than the frequency multiplier output standard. In this case, if the interference detection module detects that the third frame synchronization signal has a large frequency signal, it is generally determined that the interference signal is detected.
  • the frequency multiplying processor is further configured to execute the computer readable program to obtain the third frame synchronization signal that meets the output frequency standard of the frequency multiplier processor. And generating an initial level signal before detecting a change edge of the third frame synchronization signal, wherein the frequency of the initial level signal conforms to an output standard of the frequency multiplier processor;
  • the driving chip is further configured to generate a corresponding PWM signal according to the initial level signal.
  • the first level signal and the second level signal have not been generated after the third frame sync signal is acquired, and before the change edge of the third frame sync signal is detected.
  • the frequency doubling processor executes the computer readable program to generate an initial level signal that conforms to the output standard of the frequency doubling processor. For example, if the output standard of the multiplier processor is 100/120 Hz, the frequency of the initial level signal may be 100 or 120 Hz.
  • another display device including a non-volatile memory, a frequency multiplying processor and a driving chip storing a computer readable program; wherein the frequency doubling processor comprises Scan chip, multiplier processing chip.
  • the scan chip is configured to execute the computer readable program to: output a first frame synchronization signal corresponding to the input image signal to the frequency doubling processing chip according to the input image signal;
  • the frequency doubling processing chip is configured to execute the computer readable program to: output a first level of the third level signal to the driving chip in response to the changing edge of the first frame synchronization signal;
  • the changing edge alternately outputs a fourth level signal of a second duration to the driving chip after generating the third level signal and before detecting the first changing edge after the changing edge in the first frame synchronization signal a third level signal of the first duration, a signal frequency of the signal formed by the third level signal and the fourth level signal alternately outputting is the change edge in the first frame synchronization signal and the Changing the frequency of the first change edge before the change is m times, wherein the change edge is the same change edge along the first change edge before the change edge, and m is a positive integer;
  • the driving chip receives the third level signal and the fourth level signal, and generates a PWM signal according to the third level signal and the fourth level signal.
  • the driving chip generates a PWM signal according to the third level signal and the fourth level signal, including: generating a frequency equal to a frequency formed by the third level signal and the fourth level signal PWM signal.
  • the frequency doubling processing chip is further configured to execute the computer readable program to:
  • the driving chip receives the initial level signal and generates a corresponding PWM signal according to the initial level signal.
  • the level of the initial level signal is different from the level of the third level signal.
  • the level of the initial level signal is a low level
  • the level of the third level signal is a high level
  • the level of the fourth level signal is a low level.
  • the frequency doubling processing chip is further configured to execute the computer readable program to:
  • the third change signal of the first duration is output along the next change edge after the change edge.
  • the techniques in the embodiments of the present disclosure can be implemented by means of software plus the necessary general hardware platform. Based on such understanding, the technical solution in the embodiments of the present disclosure may be embodied in the form of a software product in essence or in the form of a software product, which may be stored in a storage medium such as a ROM/RAM. , a diskette, an optical disk, etc., including instructions for causing a computer device (which may be a personal computer, server, or network device, etc.) to perform the methods described in various embodiments of the present disclosure or portions of the embodiments.
  • a computer device which may be a personal computer, server, or network device, etc.

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Abstract

一种多分区动态背光驱动方法及显示装置。该方法中，接收与输入的图像信号相对应的帧同步信号；响应所述帧同步信号的变化沿，交替输出第一电平信号和第二电平信号，第一电平信号和第二电平信号持续的总时长为所述变化沿和所述变化沿之前的第一个变化沿之间的时长的1/m,其中，所述变化沿与所述变化沿之前的第一个变化沿为同向变化沿；m为正整数；驱动芯片接收所述第一电平信号和第二电平信号，并根据所述第一电平信号和第二电平信号生成PWM信号。

Description

一种多分区动态背光驱动方法及显示装置
本申请要求在2017年7月27日提交中国专利局、申请号为201710623557.4、申请名称为“一种多分区动态背光驱动方法及电视”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及背光显示技术领域，尤其涉及一种多分区动态背光驱动方法及显示装置。
背景技术
随着电视技术的发展，应用多分区动态背光技术的电视迅速成为各大电视品牌的旗舰产品。这种类型的电视中，将背光划分成多个独立的分区，每个分区的背光能够根据画面的亮暗实时调整，从而显示的画面亮暗对比明显，画面更清晰亮丽。
发明内容
根据本公开实施例的第一方面，提供一种多分区动态背光驱动方法，包括：
接收与输入的图像信号相对应的第一帧同步信号；
响应所述帧同步信号的变化沿，向驱动芯片输出第一时长的第一电平信号；
在响应于所述变化沿生成第一电平信号以后至检测到所述第一帧同步信号中所述变化沿之后的第一个变化沿之前，向驱动芯片交替输出第二时长的第二电平信号和第一时长的第一电平信号，交替输出的所述第一电平信号和所述第二电平信号所构成信号的信号频率为所述第一帧同步信号中所述变化沿与所述变化沿之前的第一个变化沿构成的频率的m倍，其中，所述变化沿与所述变化沿之前的第一个变化沿为同向变化沿；m为正整数；
驱动芯片接收所述第一电平信号和第二电平信号，并根据所述第一电平信号和第二电平信号生成PWM信号。
根据本公开实施例的第二方面，提供另一种多分区动态背光驱动方法，包括：
接收与输入的图像信号相对应的帧同步信号；
响应所述第一帧同步信号的变化沿，交替输出第一电平信号和第二电平信号，第一电平信号和第二电平信号持续的总时长为所述变化沿和所述变化沿之前的第一个变化沿之间的时长的1/m,其中，所述变化沿与所述变化沿之前的第一个变化沿为同向变 化沿；m为正整数；
驱动芯片接收所述第一电平信号和第二电平信号，并根据所述第一电平信号和第二电平信号生成PWM信号。
根据本公开实施例的第三方面，提供了一种多分区动态背光驱动方法，包括：
获取符合处理器输出标准的帧同步信号；
当检测到所述第三帧同步信号的变化沿时，生成时长为nT1的第一电平信号，在第一电平信号结束至下一次检测到变化沿的时间段内，生成第二电平信号，其中，T1为目标信号的周期，n由所述第三帧同步信号与所述目标信号的周期间的倍数关系确定；
将所述第一电平信号和第二电平信号传输至驱动芯片，以便所述驱动芯片根据所述第一电平信号和第二电平信号生成PWM信号。
根据本公开实施例的第四方面，提供一种显示装置，包括：
存储有计算机可读程序的非易失性存储器、扫描芯片、倍频处理器和驱动芯片；其中，
所述扫描芯片被配置为：读取非易失性存储器中的计算机可读程序并执行接收与输入的图像信号相对应的帧同步信号；
所述倍频处理器被配置为：读取非易失性存储器中的计算机可读程序并执行响应所述第一帧同步信号的变化沿，向驱动芯片输出第一时长的第一电平信号；在响应于所述变化沿生成第一电平信号以后至检测到所述第一帧同步信号中所述变化沿之后的第一个变化沿之前，向驱动芯片交替输出第二时长的第二电平信号和第一时长的第一电平信号，交替输出的所述第一电平信号和所述第二电平信号所构成信号的信号频率为所述第一帧同步信号中所述变化沿与所述变化沿之前的第一个变化沿构成的频率的m倍，其中，所述变化沿与所述变化沿之前的第一个变化沿为同向变化沿；m为正整数；
所述驱动芯片被配置为：接收所述第一电平信号和第二电平信号，并根据所述第一电平信号和第二电平信号生成PWM信号。
根据本公开实施例的第五方面，提供一种显示装置，包括：
存储有计算机可读程序的非易失性存储器、扫描芯片、倍频处理器和驱动芯片；其中，
所述扫描芯片被配置为：读取非易失性存储器中的计算机可读程序并执行接收与 输入的图像信号相对应的帧同步信号；
所述倍频处理器被配置为：读取非易失性存储器中的计算机可读程序并执行响应所述第一帧同步信号的变化沿，交替输出第一电平信号和第二电平信号，第一电平信号和第二电平信号持续的总时长为所述变化沿和所述变化沿之前的第一个变化沿之间的时长的1/m,其中，所述变化沿与所述变化沿之前的第一个变化沿为同向变化沿；m为正整数；
所述驱动芯片被配置为：接收所述第一电平信号和第二电平信号，并根据所述第一电平信号和第二电平信号生成PWM信号。
根据本公开实施例的第六方面，提供一种显示装置，包括：
存储有计算机可读程序的非易失性存储器、倍频处理器；其中，
所述倍频处理器被配置为：读取非易失性存储器中的计算机可读程序并执行获取符合处理器输出标准的帧同步信号；当检测到所述帧同步信号的变化沿时，生成时长为nT1的第一电平信号，在第一电平信号结束至下一次检测到变化沿的时间段内，生成第二电平信号，其中，T1为目标信号的周期，n由所述帧同步信号与所述目标信号的周期间的倍数关系确定；将所述第一电平信号和第二电平信号传输至驱动芯片，以便所述驱动芯片根据所述第一电平信号和第二电平信号生成PWM信号。
附图说明
为了更清楚地说明本公开的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，对于本领域普通技术人员而言，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为相关技术公开的一种信号时序示意图；
图2为本公开实施例公开的一种多分区动态背光驱动方法的工作流程示意图；
图3为本公开实施例公开的又一种多分区动态背光驱动方法的工作流程示意图；
图4为本公开实施例公开的一种多分区动态背光驱动方法中的信号时序示意图；
图5为本公开实施例公开的又一种多分区动态背光驱动方法的工作流程示意图；
图6为本公开实施例公开的又一种多分区动态背光驱动方法的工作流程示意图；
图7为图6所示的多分区动态背光驱动方法中的信号时序示意图；
图8为本公开实施例公开的一种显示装置的结构示意图；
图9为本公开实施例公开的一种显示装置中的信号获取模块的结构示意图。
具体实施方式
相关技术中，应用多分区动态背光技术的电视在显示画面时，倍频处理器获取扫描芯片传输的帧同步信号(即vertical synchronization，Vsync信号)，并对其进行相应的处理，然后将处理后生成倍频处理器输出的帧同步信号传输至驱动芯片；驱动芯片接收到倍频处理器输出的帧同步信号后，根据倍频处理器输出的帧同步信号生成相应的PWM(Pulse Width Modulation，脉冲宽度调制)信号，并驱动显示屏根据该PWM信号进行相应的背光显示，从而实现电视的播放。
但是，在本公开的研究过程中发现，在需要动态背光控制的电视播放过程中，有时需要在不同帧频制式下切换，无论采用还是不采用多分区，在切换过程中，会导致倍频处理器输出的帧同步信号中夹杂有大频率的干扰信号，这种情况下，驱动器在接收到倍频处理器输出的带有干扰信号的帧同步信号后，生成的PWM信号中会出现占空比突变区域，导致电视出现背光闪烁的现象。
在研究过程中发现如下情形，例如，参见图1信号时序图中所示的波形示意图。该图中，第一行波形为扫描芯片向倍频处理器输出的第一帧同步信号的波形，其中，该信号的频率为50/60Hz，示出的是由60HZ转换成50HZ的过程；第二行波形为倍频处理器进行倍频处理后向PWM驱动芯片输出的第二帧同步信号的波形，该波形被倍频处理器传输至驱动芯片，其中，倍频处理后的第二帧同步信号的频率通常在100/120Hz以上，另外，倍频处理器受第一帧同步信号的触发产生第二帧同步信号，在相关技术的一些实现方式中，倍频处理器在接收到第一帧同步信号的上升沿或下降沿后，会在预设时间内输出第二帧同步信号的脉冲，因此在电视播放过程中进行制式切换，导致在100Hz和120Hz的信号之间，出现大频率的干扰信号，图1示出的是由120HZ转换成100HZ的过程；这使得120HZ信号的最后一个脉冲和100HZ的第一个脉冲之间的周期大大减少，对应的频率较高，第三行波形为驱动芯片生成的PWM信号，对应120HZ信号的最后一个脉冲和100HZ的第一个脉冲之间这段时间的PWM信号具有120HZ信号的最后一个脉冲和100HZ的第一个脉冲之间的周期对应的频率，形成了占空比突变区域，这种情况下突变区域的PWM信号会导致显示屏出现背光闪烁。
下面结合附图，对本公开的实施例进行描述。
本公开一些实施例公开一种多分区动态背光驱动方法，以解决相关技术中，电视在播放过程中出现背光闪烁的问题。
本公开的第一实施例公开一种多分区动态背光驱动方法，该方法通常应用于电视中设置的倍频处理器，该电视采用多分区动态背光技术。该倍频处理器与电视中安装的扫描芯片和驱动芯片相连接。其中，该倍频处理器通常为MCU(Microcontroller Unit，微控制单元)，当然，该倍频处理器也可以为其他装置，本公开实施例对此不作限定。
参见图2所示的工作流程示意图，本公开实施例公开的多分区动态背光驱动方法包括以下步骤：
步骤S11、获取符合倍频处理器输出标准的第三帧同步信号。
与倍频处理器相连接的扫描芯片，会向倍频处理器传输第一帧同步信号，倍频处理器根据该第一帧同步信号，获取符合倍频处理器输出标准的第三帧同步信号。
其中，在应用多分区动态背光技术的电视中，符合倍频处理器输出标准的帧同步信号的频率通常在100/120Hz或以上。
在本公开一些实施例中，该扫描芯片可以为SoC(System on Chip，系统级芯片)，用于根据输入的图像获取第一帧同步信号，并向倍频处理器传输第一帧同步信号。当然，该扫描芯片也可以为其他类型的芯片，本公开实施例对此不作限定。
步骤S12、当检测到所述第三帧同步信号的变化沿时，输出时长为nT1的第一电平信号，在第一电平信号结束至下一次检测到变化沿的时间段内，生成第二电平信号，其中，T1为目标信号的周期，n由所述第三帧同步信号与所述目标信号的周期间的倍数关系确定。
倍频处理器能够通过扫描芯片获取第一帧同步信号，并且，倍频处理器还能够获取其他类型的信号，这种情况下，可以从其他类型的信号中选择目标信号，该目标信号的周期与符合倍频处理器输出标准的第三帧同步信号的周期之间具有固定的倍数关系。
该步骤中，设定符合倍频处理器输出标准的第三帧同步信号的周期为所述目标信号的周期的n倍。另外，若设定检测到所述第三帧同步信号的变化沿的时刻为第一时刻，从所述第一时刻至第二时刻的时间段内生成第一电平信号，其中，第一时刻至第二时刻的时长为nT1。第一电平信号通常为第二帧同步信号中维持时间较长的电平信号。
在倍频处理器输出的第二帧同步信号中，同一周期的信号由高电平信号和低电平信号构成，两种电平信号维持的时间往往不同。在本公开实施中，通常将其中维持时间较长的电平信号作为第一电平信号，并且第一电平信号与第二电平信号不同。也就是说，若倍频处理器输出的第二帧同步信号中高电平的维持时间较长，则第一电平信号为高电平信号，相应的，第二电平信号为低电平信号；若第二帧同步信号中低电平的维持时间较长，则第一电平信号为低电平信号，相应的，第二电平信号为高电平信号。
在一些实施例中,相邻的一个第一电平信号和一个第二电平信号的总时长为nT1.
另外，在本公开实施中，变化沿为上升沿或下降沿。
受到制式切换等原因的影响，帧同步信号中有时夹杂有干扰信号，该干扰信号通常频率较大，周期较小。本公开实施例中，由于设定帧同步信号的周期为目标信号的周期的n倍，且T1为所述目标信号的周期，则nT1应该为帧同步信号在正常状态下(即帧同步信号中未出现干扰信号的情况下)的周期。
在本申请一些实施例的表述中，认为第二电平的时长对信号周期的影响较小，在一些实施例中也可以使一个第一电平的时长和相邻的一个第二电平的时长之和作为一个周期。第一电平信号和第二电平信号共同构成了第二帧同步信号。
在步骤S12中，当检测到第三帧同步信号的变化沿时开始计时，并开始生成第一电平信号，且该第一电平信号维持的时长为nT1，并在第二时刻至下一次检测到所述第三帧同步信号的变化沿的时间段内生成第二电平信号。这种情况下，第一电平信号和第二电平信号周期性的产生，且第一电平信号维持的时长(即nT1)为第三帧同步信号在正常状态下的周期，因此第一电平信号和第二电平信号的周期接近第三帧同步信号在正常状态下的周期，能够避免干扰信号的影响。在一些实施例中，变化前的第一帧同步信号(60HZ)对应的第三帧同步信号为1/120秒，此时第一电平信号持续的时长和第二电平信号持续的时长之和等于或接近1/120秒。变化后的第一帧同步信号(50HZ)对应的第三帧同步信号为1/100秒，此时第一电平信号持续的时长和第二电平信号持续的时长之和等于或接近1/100秒.
步骤S13、将所述第一电平信号和第二电平信号传输至驱动芯片，以便所述驱动芯片根据所述第一电平信号和第二电平信号生成PWM信号。
而本公开实施例中，根据符合倍频处理器输出标准的第三帧同步信号，生成第一 电平信号和第二电平信号，并将第一电平信号和第二电平信号传输至驱动芯片，以便驱动芯片根据该第一电平信号和第二电平信号生成相应的PWM信号。该第一电平信号和第二电平信号的周期接近第三帧同步信号在正常状态下的周期，从而能够避免干扰信号的影响，减少背光闪烁的现象。
在上述实施例中，通过步骤S11，公开了获取符合倍频处理器输出标准的帧同步信号的操作，参见图3所示的工作流程示意图，该操作通常包括以下步骤：
步骤S111、接收扫描芯片传输的第一帧同步信号；
步骤S112、判断所述第一帧同步信号的频率是否符合倍频处理器输出标准，若否，执行步骤S113的操作，若是，执行步骤S12的操作；
步骤S113、若所述第一帧同步信号的频率不符合倍频处理器输出标准，对所述第一帧同步信号进行倍频处理，以使倍频处理后生成的第三帧同步信号符合所述倍频处理器输出标准，然后执行步骤S12的操作。
扫描芯片的扫描频率一般为50/60Hz，而在应用多分区动态背光技术的电视中，倍频处理器输出的帧同步信号通常在100/120Hz或以上，也就是说，符合倍频处理器输出标准的帧同步信号的频率通常在100/120Hz或以上。这种情况下，倍频处理器在接收到扫描芯片传输的第一帧同步信号后，能够确定第一帧同步信号的频率不符合倍频处理器输出标准，从而对其进行倍频处理。
另外，若扫描芯片传输至倍频处理器的第一帧同步信号符合倍频处理器输出标准，则倍频处理器无需进行倍频处理，通过将第一帧同步信号作为第三帧同步信号执行步骤S12的操作即可。
为了明确本公开实施例中各个步骤的作用，以下以一个具体的实例对本公开实施例进行说明：
参见图4，在图4中包含四行波形。其中，第一行波形为扫描芯片传输至倍频处理器的第一帧同步信号，该第一帧同步信号的频率为50/60Hz。
倍频处理器接收到第一帧同步信号后，对第一帧同步信号进行倍频处理，以使其符合倍频处理器输出标准，倍频处理后的第三帧同步信号(即符合倍频处理器输出标准的帧同步信号)为100/120Hz，从而形成第二行波形。另外，在第二行波形中，还包括有干扰信号。
根据第二行波形，可知，第三帧同步信号中维持时间较长的电平信号为低电平信号，则通常选择第一电平信号为低电平信号。另外，图4中，将第三帧同步信号的变化沿设定为第三帧同步信号的上升沿。这种情况下，在检测到第三帧同步信号的上升沿后，生成低电平信号(即第一电平信号)，且低电平信号维持的时间为nT1。然后，在第二时刻至下一次检测到第三帧同步信号的上升沿的时间段内，生成高电平信号(即第二电平信号)，从而形成第三行波形。其中，第三行波形即为第一电平信号和第二电平信号的波形，并且，第三行波形也是倍频处理器输出至驱动芯片的波形，也即第二帧同步信号。
根据图4可知，第三波形中不存在频率极大的波形，也就是说，第一电平信号和第二电平信号中未夹杂干扰信号，从而能够避免干扰信号的影响。
这种情况下，驱动芯片生成的PWM信号的波形如图4中的第四行波形所示，第四行波形中不再出现占空比突变的区域，从而能够减少背光闪烁的现象出现。
倍频处理器能够通过扫描芯片获取第一帧同步信号，并且，倍频处理器还能够获取其他各种类型的信号，在本公开实施例中，可以从其他类型的信号中选择目标信号，该目标信号的周期与符合倍频处理器输出标准的帧同步信号的周期之间具有固定的倍数关系。
通过分析对LED驱动芯片控制方式的大量实验数据后发现，如果输出至驱动芯片第二帧同步信号和Hsync(horizontal synchronization)行同步信号可以实时保持稳定的倍数关系，那么，背光PWM的占空比会保持稳定，也就不会出现闪烁现象。在其中一个具体实施方式中，该目标信号可以为行同步信号(即Hsync信号)。当前智能电视中，符合倍频处理器输出标准的第三帧同步信号的周期通常为行同步信号的周期的4096倍，这种情况下，n的取值为4096。当然，在不同规格的智能电视中，该倍数关系可能不同，相应的n的取值也会发生变化。其中，Hsync行同步信号是指显示过程中控制每一行液晶分子的一种同步信号。
本公开另一实施例还公开一种多分区动态背光驱动方法。参见图5所示的工作流程示意图，该多分区动态背光驱动方法包括以下步骤：
步骤S21、获取符合倍频处理器输出标准的第三帧同步信号。
步骤S22、在获取符合倍频处理器输出标准的第三帧同步信号之后，检测所述第三帧同步信号中是否存在干扰信号，若是，执行步骤S23的操作，若否，执行步骤S25 的操作。
步骤S23、若确定所述第三帧同步信号中存在干扰信号，当检测到所述第三帧同步信号的变化沿时，生成时长为nT1的第一电平信号，在第一电平信号结束至下一次检测到变化沿的时间段内，生成第二电平信号，其中，T1为目标信号的周期，n由所述第三帧同步信号与所述目标信号的周期间的倍数关系确定。
步骤S24、将所述第一电平信号和第二电平信号传输至驱动芯片，以便所述驱动芯片根据所述第一电平信号和第二电平信号生成PWM信号。
步骤S23至步骤S24的具体实施过程与上述实施例中步骤S12至步骤S13的实施过程相同，可相互参照，此处不再赘述。
步骤S25、结束本次操作。
本公开实施例中，在获取符合倍频处理器输出标准的第三帧同步信号后，检测所述第三帧同步信号中是否存在干扰信号，若确定所述第三帧同步信号中存在干扰信号，再执行所述当检测到所述第三帧同步信号的变化沿时，生成时长为nT1的第一电平信号，在第一电平信号结束至下一次检测到变化沿的时间段内，生成第二电平信号的操作。这种情况下，在确定第三帧同步信号中存在干扰信号的情况下，才执行后续操作，从而减少倍频处理器的负担。
另外，干扰信号的频率通常大于倍频处理器输出标准，这种情况下，在本公开实施例中，若检测到第三帧同步信号存在较大频率的信号，通常可确定检测到干扰信号。
进一步的，在本公开实施例所公开的多分区动态背光驱动方法中，还包括以下操作：
在获取到符合倍频处理器输出标准的第三帧同步信号之后，并在检测到所述第三帧同步信号的变化沿之前，生成初始电平信号，其中，所述初始电平信号的频率符合倍频处理器的输出标准；
将所述初始电平信号传输至所述驱动芯片，以便所述驱动芯片根据所述初始电平信号生成相应的PWM信号。
在获取到所述第三帧同步信号之后，并在检测到所述第三帧同步信号的变化沿之前，还未生成第一电平信号和第二电平信号。这种情况下，倍频处理器生成符合倍频处理器的输出标准的初始电平信号。例如，若倍频处理器的输出标准为100/120Hz， 则初始电平信号的频率可以为100或120Hz。
本公开的另一些实施例提供另一种多分区动态背光驱动方法。如图6所示，该方法包括以下步骤：
步骤S31：接收与输入的图像信号相对应的第一帧同步信号。
步骤S32：响应所述第一帧同步信号的变化沿，向驱动芯片输出第一时长的第三电平信号。
步骤S33：在响应于所述变化沿生成第三电平信号以后至检测到所述第一帧同步信号中所述变化沿之后的第一个变化沿之前，向驱动芯片交替输出第二时长的第四电平信号和第一时长的第三电平信号，交替输出的所述第三电平信号和所述第四电平信号所构成信号的信号频率为所述第一帧同步信号中所述变化沿与所述变化沿之前的第一个变化沿构成的频率的m倍，其中，所述变化沿与所述变化沿之前的第一个变化沿为同向变化沿；m为正整数。
在本公开的一些实施例中，还可有由以下步骤替换步骤S32、S33：响应所述第一帧同步信号的变化沿，交替输出第三电平信号和第四电平信号，第三电平信号和第四电平信号持续的总时长为所述第一帧同步信号中所述变化沿和所述变化沿之前的第一个变化沿之间的时长的1/m,其中，所述变化沿与所述变化沿之前的第一个变化沿为同向变化沿；m为正整数。
在本申请的一些实施例中，第三电平信号可以是高电平信号也可以是低电平信号，且不受其占用时长的限制。
在本公开的一些实施例中，所述变化沿与所述变化沿之前的第一个变化沿为同向变化沿是指所述变化沿的变化趋势与所述变化沿之前的第一个变化沿的变化趋势相同。
步骤S34：驱动芯片接收所述第三电平信号和第四电平信号，并根据所述第三电平信号和第四电平信号生成PWM信号。
在本公开的一些实施例中，根据所述第三电平信号和第四电平信号生成PWM信号包括：生成频率与第三电平信号和第四电平信号所构成的第二帧同步信号频率相同的PWM信号。
在本公开的一些实施例中，首次检测到所述第一帧同步信号的变化沿之前，所述方法还包括：向驱动芯片输出初始电平信号；驱动芯片接收所述初始电平信号，并根据所述初始电平信号生成相应的PWM信号。
在本公开的一些实施例中，所述初始电平信号的电平与所述第三电平信号的电平 不同。在本公开的一些实施例中，所述初始电平信号的电平为低电平，所述第三电平信号的电平为高电平，所述第四电平信号的电平为低电平。
在本公开的一些实施例中，在检测到所述第一帧同步信号的变化沿之后的下一个变化沿时，在该时刻对应的第三电平信号或第四电平信号完全输出后，再响应于所述帧同步信号的变化沿之后的下一个变化沿输出第一时长的第三电平信号。
为了明确本公开实施例中各个步骤的作用，以下对本公开实施例进行说明：参见图7，在图7中包含三行波形。其中，第一行波形为与输入的图像信号相对应的第一帧同步信号(Vsync信号)，在一些实施例中，第一帧同步信号的频率为50/60Hz。
以第三电平信号是高电平，第四电平信号是低电平为例，在检测到第一帧同步信号的频率变化前，响应所述第一帧同步信号的变化沿(可以是脉冲b的下降沿或上升沿，此处以上升沿为例)，向驱动芯片输出第一时长的高电平信号b；在响应于脉冲b的上升沿生成高电平信号d以后至检测到脉冲b的上升沿之后的第一个变化沿(即脉冲c的上升沿)之前，向驱动芯片交替输出低电平e、高电平f等，其中，低电平e、低电平g、低电平i是持续相同时长的低电平；高电平d、高电平f、高电平h是持续时长相同的高电平，交替输出的高电平信号d和低电平e所构成信号的信号频率为所述变化沿(即脉冲b的上升沿)与所述变化沿之前的第一个变化沿(即脉冲a的上升沿)构成的频率的m倍，其中，所述变化沿与所述变化沿之前的第一个变化沿为同向变化沿；m为正整数。在图7所示实例中，m的取值为2。由此形成第二行波形。其中，第二行波形即为第三电平信号和第四电平信号的波形，并且，第二行波形也是倍频处理器输出至驱动芯片的第二帧同步信号的波形；在检测到第一帧同步信号的频率变化后，响应所述第一帧同步信号的变化沿(可以是脉冲c的下降沿或上升沿，此处以上升沿为例)，待上一周期的低电平i按照对应时长输出完成后，向驱动芯片输出第一时长的高电平信号j；在响应于脉冲c的上升沿生成高电平信号j以后至检测到脉冲c的上升沿之后的第一个变化沿(即脉冲l的上升沿)之前，向驱动芯片交替输出低电平k和高电平，交替输出的高电平信号j和低电平k所构成信号的信号频率为所述变化沿(即脉冲c的上升沿)与所述变化沿之前的第一个变化沿(即脉冲b的上升沿)构成的频率的m倍。
根据图7可知，第三行的波形中不存在频率极大的波形，也就是说，第三电平信号和第四电平信号中未夹杂干扰信号，从而能够避免干扰信号的影响。
这种情况下，驱动芯片生成的PWM信号的波形如图7中的第三行波形所示，第 三行波形中不再出现占空比突变的区域，从而能够减少背光闪烁的现象出现。
相应的，在本公开另一实施例中，还公开一种显示装置，参见图8所示的结构示意图，该显示装置包括：信号获取模块100、信号生成模块200和驱动芯片300。在一些实施例中，信号获取模块100、信号生成模块200均位于倍频处理器中。
其中，所述信号获取模块100，用于获取符合倍频处理器输出标准的第三帧同步信号。
在一实施例中，所述信号获取模块100根据第一帧同步信号，获取符合倍频处理器输出标准的第三帧同步信号。
其中，在应用多分区动态背光技术的电视中，符合倍频处理器输出标准的第三帧同步信号的频率通常在100/120Hz以上。
所述信号生成模块200，用于当检测到所述第三帧同步信号的变化沿时，生成时长为nT1的第一电平信号，在第一电平信号结束至下一次检测到变化沿的时间段内，生成第二电平信号，其中，T1为目标信号的周期，n由所述第三帧同步信号与所述目标信号的周期间的倍数关系确定。
所述信号获取模块100能够获取第一帧同步信号，并且，所述信号获取模块100还能够获取其他类型的信号，这种情况下，可以从其他类型的信号中选择目标信号，该目标信号的周期与符合倍频处理器输出标准的第三帧同步信号的周期之间具有固定的倍数关系。
所述信号生成模块200还用于设定符合倍频处理器输出标准的第三帧同步信号的周期为所述目标信号的周期的n倍。另外，若设定检测到所述第三帧同步信号的变化沿的时刻为第一时刻，所述信号生成模块200从所述第一时刻至第二时刻的时间段内生成第一电平信号，其中，第一时刻至第二时刻的时长为nT1。第一电平信号通常为第二帧同步信号中维持时间较长的电平信号。
在第二帧同步信号中，同一周期的信号由高电平信号和低电平信号构成，两种电平信号维持的时间往往不同。在本公开实施中，通常将其中维持时间较长的电平信号作为第一电平信号，并且第一电平信号与第二电平信号不同。也就是说，若第二帧同步信号中高电平的维持时间较长，则第一电平信号为高电平信号，相应的，第二电平信号为低电平信号；若第二帧同步信号中低电平的维持时间较长，则第一电平信号为低电平信号，相应的，第二电平信号为高电平信号。
另外，在本公开实施中，变化沿为上升沿或下降沿。
受到制式切换等原因的影响，第三帧同步信号中有时夹杂有干扰信号，该干扰信号通常频率较大，周期较小。本公开实施例中，由于设定第三帧同步信号的周期为目标信号的周期的n倍，且T1为所述目标信号的周期，则nT1应该为第三帧同步信号在正常状态下(即帧同步信号中未出现干扰信号的情况下)的周期。
所述驱动芯片300，用于根据所述第一电平信号和第二电平信号生成PWM信号。
另外，参见图9所示的结构示意图，本公开实施例公开的所述信号获取模块100包括：
接收单元101，用于接收扫描芯片传输的第一帧同步信号；
判断单元102，用于判断所述第一帧同步信号的频率是否符合倍频处理器输出标准；
倍频处理单元103，用于若所述第一帧同步信号的频率不符合倍频处理器输出标准，对所述第一帧同步信号进行倍频处理，以使倍频处理后的第三帧同步信号符合所述倍频处理器输出标准。
扫描芯片的扫描频率一般为50/60Hz，而在应用多分区动态背光技术的电视中，倍频处理器输出的第三帧同步信号通常在100/120Hz或以上，也就是说，符合倍频处理器输出标准的帧同步信号的频率通常在100/120Hz或以上。这种情况下，倍频处理器在接收到扫描芯片传输的第一帧同步信号后，能够确定原始的帧同步信号的频率不符合倍频处理器输出标准，从而对其进行倍频处理。
在其中一实施方式中，该目标信号可以是与显示器面板扫描频率一样的信号，所述目标信号可以为行同步信号(即Hsync信号)。在所述驱动装置所在的当前智能电视中，符合倍频处理器输出标准的帧同步信号的周期通常为行同步信号的周期的4096倍，这种情况下，n的取值为4096。当然，在不同规格的智能电视中，该倍数关系可能不同，相应的n的取值也会发生变化。
当然，除了行同步信号外，目标信号还可以为其他类型的信号，这种情况下，需要相应的调整n的取值，本公开实施例对此不作限定。
进一步的，本公开实施例公开的所述显示装置，还包括：干扰检测模块。
其中，所述干扰检测模块用于在获取符合倍频处理器输出标准的第三帧同步信号 之后，检测所述第三帧同步信号中是否存在干扰信号；
若所述干扰检测模块确定所述第三帧同步信号中存在干扰信号，所述干扰检测模块触发所述信号生成模块执行相应操作。也就是说，所述干扰检测模块触发所述信号生成模块执行当检测到所述第三帧同步信号的变化沿时，生成时长为nT1的第一电平信号，在第一电平信号结束至下一次检测到变化沿的时间段内，生成第二电平信号的操作。
通过本公开实施例公开的显示装置，能够在确定帧同步信号中存在干扰信号的情况下，才执行后续操作，从而减少不必要的负担。
另外，干扰信号的频率通常大于倍频处理器输出标准，这种情况下，若干扰检测模块检测到帧同步信号存在较大频率的信号，通常可确定检测到干扰信号。
进一步的，在本公开实施例公开的所述显示装置中，还包括：
初始信号生成模块，用于在获取到符合倍频处理器输出标准的第三帧同步信号之后，并在检测到所述第三帧同步信号的变化沿之前，生成初始电平信号，其中，所述初始电平信号的频率符合倍频处理器的输出标准；
初始信号传输模块，用于将所述初始电平信号传输至所述驱动芯片，以便所述驱动芯片根据所述初始电平信号生成相应的PWM信号。
在获取到所述第三帧同步信号之后，并在检测到所述第三帧同步信号的变化沿之前，还未生成第一电平信号和第二电平信号。这种情况下，通过初始信号生成模块生成符合倍频处理器的输出标准的初始电平信号。例如，若倍频处理器的输出标准为100/120Hz，则初始电平信号的频率可以为100或120Hz。
相应的，在本公开另一实施例中，还公开一种多分区动态背光显示装置，该显示装置包括：存储有计算机可读程序的非易失性存储器、至少一个倍频处理器和驱动芯片。
其中，所述倍频处理器用于执行所述计算机可读程序，以实现以下操作：
获取符合倍频处理器输出标准的第三帧同步信号；
当检测到所述第三帧同步信号的变化沿时，输出时长为nT1的第一电平信号，在第一电平信号结束至下一次检测到变化沿的时间段内，生成第二电平信号，其中，T1为目标信号的周期，n由所述第三帧同步信号与所述目标信号的周期间的倍数关系确 定。
所述驱动芯片用于根据所述第一电平信号和第二电平信号生成PWM信号。
在一实施例中，所述倍频处理器执行所述计算机可读程序以根据第一帧同步信号，获取符合倍频处理器输出标准的第三帧同步信号。
其中，在应用多分区动态背光技术的电视中，符合倍频处理器输出标准的帧同步信号的频率通常在100/120Hz或以上。
所述倍频处理器通过执行所述计算机可读程能够控制扫描芯片获取原始的帧同步信号，并且，所述倍频处理器通过执行所述计算机可读程序还能够获取其他类型的信号，这种情况下，可以从其他类型的信号中选择目标信号，该目标信号的周期与符合倍频处理器输出标准的帧同步信号的周期之间具有固定的倍数关系。
所述倍频处理器还用于执行所述计算机可读程序以设定符合倍频处理器输出标准的第三帧同步信号的周期为所述目标信号的周期的n倍。另外，若设定检测到所述第三帧同步信号的变化沿的时刻为第一时刻，所述倍频处理器从所述第一时刻至第二时刻的时间段内生成第一电平信号，其中，第一时刻至第二时刻的时长为nT1。第一电平信号通常为帧同步信号中维持时间较长的电平信号。
在第二帧同步信号中，同一周期的信号由高电平信号和低电平信号构成，两种电平信号维持的时间往往不同。在本公开实施中，通常将其中维持时间较长的电平信号作为第一电平信号，并且第一电平信号与第二电平信号不同。也就是说，若第二帧同步信号中高电平的维持时间较长，则第一电平信号为高电平信号，相应的，第二电平信号为低电平信号；若第二帧同步信号中低电平的维持时间较长，则第一电平信号为低电平信号，相应的，第二电平信号为高电平信号。
另外，在本公开实施中，变化沿为上升沿或下降沿。
受到制式切换等原因的影响，第三帧同步信号中有时夹杂有干扰信号，该干扰信号通常频率较大，周期较小。本公开实施例中，由于设定第三帧同步信号的周期为目标信号的周期的n倍，且T1为所述目标信号的周期，则nT1应该为第三帧同步信号在正常状态下(即帧同步信号中未出现干扰信号的情况下)的周期。
另外，所述驱动装置还包括扫描芯片。在获取符合倍频处理器输出标准的帧同步信号之前，所述倍频处理器还用于执行所述计算机可读程序，以实现以下操作：
接收扫描芯片传输的第一帧同步信号；
判断所述第一帧同步信号的频率是否符合倍频处理器输出标准；
若所述第一帧同步信号的频率不符合倍频处理器输出标准，对所述第一帧同步信号进行倍频处理，以使倍频处理后生成的第三帧同步信号符合所述倍频处理器输出标准。
扫描芯片的扫描频率一般为50/60Hz，而在应用多分区动态背光技术的电视中，倍频处理器输出的帧同步信号通常在100/120Hz以上，也就是说，符合倍频处理器输出标准的帧同步信号的频率通常在100/120Hz以上。这种情况下，倍频处理器在接收到扫描芯片传输的第一帧同步信号后，能够确定第一帧同步信号的频率不符合倍频处理器输出标准，从而对其进行倍频处理。
在其中一个具体实施方式中，该目标信号可以为行同步信号(即Hsync信号)。在所述驱动装置所在的当前智能电视中，符合倍频处理器输出标准的帧同步信号的周期通常为行同步信号的周期的4096倍，这种情况下，n的取值为4096。当然，在不同规格的智能电视中，该倍数关系可能不同，相应的n的取值也会发生变化。
当然，除了行同步信号外，目标信号还可以为其他类型的信号，这种情况下，需要相应的调整n的取值，本公开实施例对此不作限定。
进一步的，在获取符合倍频处理器输出标准的第三帧同步信号之后，所述倍频处理器还用于执行所述计算机可读程序以检测所述第三帧同步信号中是否存在干扰信号；
若确定所述第三帧同步信号中存在干扰信号，所述倍频处理器执行当检测到所述第三帧同步信号的变化沿时，生成时长为nT1的第一电平信号，在第一电平信号结束至下一次检测到变化沿的时间段内，生成第二电平信号的操作。
通过本公开实施例公开的驱动装置，能够在确定第三帧同步信号中存在干扰信号的情况下，才执行后续操作，从而减少倍频处理器的负担。
另外，干扰信号的频率通常大于倍频处理器输出标准，这种情况下，若干扰检测模块检测到第三帧同步信号存在较大频率的信号，通常可确定检测到干扰信号。
进一步的，在本公开实施例公开的所述驱动装置中，所述倍频处理器还用于执行所述计算机可读程序以在获取到符合倍频处理器输出标准的第三帧同步信号之后，并 在检测到所述第三帧同步信号的变化沿之前，生成初始电平信号，其中，所述初始电平信号的频率符合倍频处理器的输出标准；
所述驱动芯片还用于根据所述初始电平信号生成相应的PWM信号。
在获取到所述第三帧同步信号之后，并在检测到所述第三帧同步信号的变化沿之前，还未生成第一电平信号和第二电平信号。这种情况下，所述倍频处理器执行所述计算机可读程序生成符合倍频处理器的输出标准的初始电平信号。例如，若倍频处理器的输出标准为100/120Hz，则初始电平信号的频率可以为100或120Hz。
相应的，在本公开另一实施例中，公开了另一种显示装置，包括存储有计算机可读程序的非易失性存储器、倍频处理器和驱动芯片；其中，其中倍频处理器包括扫描芯片、倍频处理芯片。
所述扫描芯片用于执行所述计算机可读程序以实现以下操作：根据输入的图像信号，向倍频处理芯片输出与输入的图像信号相对应的第一帧同步信号；
所述倍频处理芯片用于执行所述计算机可读程序以实现以下操作：响应于所述第一帧同步信号的变化沿，向驱动芯片输出第一时长的第三电平信号；在响应于所述变化沿生成第三电平信号以后至检测到所述第一帧同步信号中所述变化沿之后的第一个变化沿之前，向驱动芯片交替输出第二时长的第四电平信号和第一时长的第三电平信号，交替输出的所述第三电平信号和所述第四电平信号所构成信号的信号频率为所述第一帧同步信号中所述变化沿与所述变化沿之前的第一个变化沿构成的频率的m倍，其中，所述变化沿与所述变化沿之前的第一个变化沿为同向变化沿，m为正整数；
驱动芯片接收所述第三电平信号和第四电平信号，并根据所述第三电平信号和第四电平信号生成PWM信号。
在一些实施例中，所述驱动芯片根据所述第三电平信号和第四电平信号生成PWM信号，包括：生成频率与第三电平信号和第四电平信号所构成的频率相同的PWM信号。
在一些实施例中，所述倍频处理芯片还用于执行所述计算机可读程序以实现以下操作：
首次检测到所述第一帧同步信号的变化沿之前，向驱动芯片输出初始电平信号；
驱动芯片接收所述初始电平信号，并根据所述初始电平信号生成相应的PWM信号。
在一些实施例中，所述初始电平信号的电平与所述第三电平信号的电平不同。所 述初始电平信号的电平为低电平，所述第三电平信号的电平为高电平，所述第四电平信号的电平为低电平。
在一些实施例中，所述倍频处理芯片还用于执行所述计算机可读程序以实现以下操作：
在检测到所述第一帧同步信号的变化沿之后的下一个变化沿时，在该时刻对应的第三电平信号或第四电平信号完全输出后，在响应于所述帧同步信号的变化沿之后的下一个变化沿输出第一时长的第三电平信号。
本领域的技术人员可以清楚地了解到本公开实施例中的技术可借助软件加必需的通用硬件平台的方式来实现。基于这样的理解，本公开实施例中的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品可以存储在存储介质中，如ROM/RAM、磁碟、光盘等，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本公开各个实施例或者实施例的某些部分所述的方法。
本说明书中各个实施例之间相同相似的部分互相参见即可。尤其，对于本公开中多分区动态背光驱动方法的实施例而言，由于其基本相似于方法实施例，所以描述的比较简单，相关之处参见方法实施例中的说明即可。
以上所述的本公开仅给出了可实现本公开的一些实施方式，并不构成对本公开保护范围的限定。

Claims (21)

  1. 一种多分区动态背光驱动方法，其特征在于，包括：
    接收与输入的图像信号相对应的帧同步信号；
    响应所述第一帧同步信号的变化沿，向驱动芯片输出第一时长的第一电平信号；
    在响应于所述变化沿生成第一电平信号以后至检测到所述第一帧同步信号中所述变化沿之后的第一个变化沿之前，向驱动芯片交替输出第二时长的第二电平信号和第一时长的第一电平信号，交替输出的所述第一电平信号和所述第二电平信号所构成信号的信号频率为所述第一帧同步信号中所述变化沿与所述变化沿之前的第一个变化沿构成的频率的m倍，其中，所述变化沿与所述变化沿之前的第一个变化沿为同向变化沿；m为正整数；
    驱动芯片接收所述第一电平信号和第二电平信号，并根据所述第一电平信号和第二电平信号生成PWM信号。
  2. 根据权利要求1所述的多分区动态背光驱动方法，其特征在于，根据所述第一电平信号和第二电平信号生成PWM信号包括：
    生成频率与第一电平信号和第二电平信号所构成的信号频率相同的PWM信号。
  3. 根据权利要求1所述的多分区动态背光驱动方法，其特征在于，还包括：
    首次检测到所述帧同步信号的变化沿之前，向驱动芯片输出初始电平信号；
    驱动芯片接收所述初始电平信号并根据所述初始电平信号生成相应的PWM信号。
  4. 根据权利要求3所述的多分区动态背光驱动方法，其特征在于，所述初始电平信号的电平与所述第一电平信号的电平不同。
  5. 根据权利要求4所述的多分区动态背光驱动方法，其特征在于，所述初始电平信号的电平为低电平，所述第一电平信号的电平为高电平，所述第二电平信号的电平为低电平。
  6. 根据权利要求1所述的多分区动态背光驱动方法，其特征在于，所述第一电平信号的电平为高电平，所述第二电平信号的电平为低电平。
  7. 根据权利要求1所述的多分区动态背光驱动方法，其特征在于，在检测到所述帧同步信号的变化沿之后的下一个变化沿时，在该时刻对应的第一电平信号或第二电平信号完全输出后，在响应于所述帧同步信号的变化沿之后的下一个变化沿输出第一时长的第一电平信号。
  8. 一种多分区动态背光驱动方法，其特征在于，包括：
    接收与输入的图像信号相对应的帧同步信号；
    响应所述第一帧同步信号的变化沿，交替输出第一电平信号和第二电平信号，第一电平信号和第二电平信号持续的总时长为所述变化沿和所述变化沿之前的第一个变化沿之间的时长的1/m,其中，所述变化沿与所述变化沿之前的第一个变化沿为同向变化沿；m为正整数；
    驱动芯片接收所述第一电平信号和第二电平信号，并根据所述第一电平信号和第二电平信号生成PWM信号。
  9. 根据权利要求8所述的多分区动态背光驱动方法，其特征在于，根据所述第一电平信号和第二电平信号生成PWM信号包括：
    生成频率与第一电平信号和第二电平信号所构成的频率相同的PWM信号。
  10. 根据权利要求8所述的多分区动态背光驱动方法，其特征在于，还包括：
    首次检测到所述帧同步信号的变化沿之前，向驱动芯片输出初始电平信号；
    驱动芯片接收所述初始电平信号，并根据所述初始电平信号生成相应的PWM信号。
  11. 根据权利要求10所述的多分区动态背光驱动方法，其特征在于，所述初始电平信号的电平与所述第一电平信号的电平不同。
  12. 根据权利要求11所述的多分区动态背光驱动方法，其特征在于，所述第一电平信号的电平为高电平，所述第二电平信号的电平为低电平。
  13. 根据权利要求8所述的多分区动态背光驱动方法，其特征在于，在检测到所述帧同步信号的变化沿之后的下一个变化沿时，在该时刻对应的第一电平信号或第二电平信号完全输出后，在响应于所述帧同步信号的变化沿之后的下一个变化沿输出第一时长的第一电平信号。
  14. 一种显示装置，其特征在于，包括：存储有计算机可读程序的非易失性存储器、扫描芯片、倍频处理器和驱动芯片；其中，
    所述扫描芯片被配置为：读取非易失性存储器中的计算机可读程序并执行接收与输入的图像信号相对应的帧同步信号；
    所述倍频处理器被配置为：读取非易失性存储器中的计算机可读程序并执行响应所述第一帧同步信号的变化沿，向驱动芯片输出第一时长的第一电平信号；在响应于所述变化沿生成第一电平信号以后至检测到所述第一帧同步信号中所述变化沿之后的第一个变化沿之前，向驱动芯片交替输出第二时长的第二电平信号和第一时长的第一电平信号，交替输出的所述第一电平信号和所述第二电平信号所构成信号的信号频率 为所述第一帧同步信号中所述变化沿与所述变化沿之前的第一个变化沿构成的频率的m倍，其中，所述变化沿与所述变化沿之前的第一个变化沿为同向变化沿；m为正整数；
    所述驱动芯片被配置为：接收所述第一电平信号和第二电平信号，并根据所述第一电平信号和第二电平信号生成PWM信号。
  15. 一种显示装置，其特征在于，包括：存储有计算机可读程序的非易失性存储器、扫描芯片、倍频处理器和驱动芯片；其中，
    所述扫描芯片被配置为：读取非易失性存储器中的计算机可读程序并执行接收与输入的图像信号相对应的帧同步信号；
    所述倍频处理器被配置为：读取非易失性存储器中的计算机可读程序并执行响应所述第一帧同步信号的变化沿，交替输出第一电平信号和第二电平信号，第一电平信号和第二电平信号持续的总时长为所述变化沿和所述变化沿之前的第一个变化沿之间的时长的1/m,其中，所述变化沿与所述变化沿之前的第一个变化沿为同向变化沿；m为正整数；
    所述驱动芯片被配置为：接收所述第一电平信号和第二电平信号，并根据所述第一电平信号和第二电平信号生成PWM信号。
  16. 一种多分区动态背光驱动方法，其特征在于，包括：
    获取符合处理器输出标准的帧同步信号；
    当检测到所述帧同步信号的变化沿时，生成时长为nT1的第一电平信号，在第一电平信号结束至下一次检测到变化沿的时间段内，生成第二电平信号，其中，T1为目标信号的周期，n由所述帧同步信号与所述目标信号的周期间的倍数关系确定；
    将所述第一电平信号和第二电平信号传输至驱动芯片，以便所述驱动芯片根据所述第一电平信号和第二电平信号生成PWM信号。
  17. 根据权利要求16所述的多分区动态背光驱动方法，其特征在于，所述获取符合处理器输出标准的帧同步信号，包括：
    接收扫描芯片传输的帧同步信号；
    判断所述扫描芯片传输的帧同步信号的频率是否符合处理器输出标准；
    若所述扫描芯片传输的帧同步信号的频率不符合处理器输出标准，对所述扫描芯片传输的帧同步信号进行倍频处理，以使倍频处理后生成的帧同步信号符合所述处理器输出标准。
  18. 根据权利要求16所述的多分区动态背光驱动方法，其特征在于，
    所述目标信号为行同步信号。
  19. 根据权利要求16所述的多分区动态背光驱动方法，其特征在于，还包括：
    在获取符合处理器输出标准的帧同步信号之后，检测所述帧同步信号中是否存在干扰信号；
    若确定所述帧同步信号中存在干扰信号，再执行所述当检测到所述第三帧同步信号的变化沿时，生成时长为nT1的第一电平信号，在第一电平信号结束至下一次检测到变化沿的时间段内，生成第二电平信号的操作。
  20. 根据权利要求16至18任一项所述的多分区动态背光驱动方法，其特征在于，还包括：
    在获取到符合处理器输出标准的帧同步信号之后，并在检测到所述符合处理器输出标准的帧同步信号的变化沿之前，生成初始电平信号，其中，所述初始电平信号的频率符合处理器的输出标准；
    将所述初始电平信号传输至所述驱动芯片，以便所述驱动芯片根据所述初始电平信号生成相应的PWM信号。
  21. 一种显示装置，其特征在于，包括：存储有计算机可读程序的非易失性存储器、倍频处理器；其中，
    所述倍频处理器被配置为：读取非易失性存储器中的计算机可读程序并执行获取符合处理器输出标准的帧同步信号；当检测到所述帧同步信号的变化沿时，生成时长为nT1的第一电平信号，在第一电平信号结束至下一次检测到变化沿的时间段内，生成第二电平信号，其中，T1为目标信号的周期，n由所述帧同步信号与所述目标信号的周期间的倍数关系确定；将所述第一电平信号和第二电平信号传输至驱动芯片，以便所述驱动芯片根据所述第一电平信号和第二电平信号生成PWM信号。
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