WO2019029566A1 - 循环冗余校验的方法和设备 - Google Patents

循环冗余校验的方法和设备 Download PDF

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Publication number
WO2019029566A1
WO2019029566A1 PCT/CN2018/099382 CN2018099382W WO2019029566A1 WO 2019029566 A1 WO2019029566 A1 WO 2019029566A1 CN 2018099382 W CN2018099382 W CN 2018099382W WO 2019029566 A1 WO2019029566 A1 WO 2019029566A1
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WIPO (PCT)
Prior art keywords
information
bits
field
control information
bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2018/099382
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English (en)
French (fr)
Inventor
沈晓冬
潘学明
纪子超
孙鹏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Vivo Mobile Communication Co Ltd
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Vivo Mobile Communication Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CN201710672362.9A external-priority patent/CN109391348B/zh
Priority claimed from CN201710672808.8A external-priority patent/CN109391349B/zh
Application filed by Vivo Mobile Communication Co Ltd filed Critical Vivo Mobile Communication Co Ltd
Priority to US16/637,243 priority Critical patent/US11563518B2/en
Priority to EP18843017.7A priority patent/EP3667962B1/en
Priority to ES18843017T priority patent/ES2931080T3/es
Publication of WO2019029566A1 publication Critical patent/WO2019029566A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0072—Error control for data other than payload data, e.g. control data
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0078—Avoidance of errors by organising the transmitted data in a format specifically designed to deal with errors, e.g. location
    • H04L1/0079—Formats for control data

Definitions

  • the present disclosure relates to the field of communications technology, and more particularly to a method and apparatus for cyclic redundancy checking.
  • Cyclic Redundancy Check is the most commonly used verification method in the field of data communication.
  • CRC is essentially a data transmission error detection function.
  • the transmitting device performs polynomial calculation on the data and the result is obtained. Attached to the frame to be transmitted, the receiving device also performs similar polynomial calculation on the data to ensure the correctness and integrity of the data transmission.
  • the CRC check mode of the control information in the Physical Downlink Control Channel is not interrupted when the information bit is transmitted but the pad bit transmission error occurs.
  • the receiving device also considers that the control information is transmitted incorrectly.
  • the link performance of the communication system is poor, and the related CRC check method cannot meet the individualized requirements of different control information for Block Error Rate (BLER) and False Alarm, affecting the control information. Receive performance.
  • BLER Block Error Rate
  • the present disclosure provides methods and apparatus for cyclic redundancy checking.
  • the present disclosure provides a method of cyclic redundancy check, the method being applied to a transmitting device, the method comprising: determining a payload portion, the payload portion including at least one information field, the at least one information a field for carrying information bits; determining input bits for generating a cyclic redundancy check CRC bit, the input bits including information bits carried in some or all of the information fields in the at least one information field; The bit generates a target CRC bit; generating control information including the payload portion and the target CRC bit.
  • the present disclosure provides a method for cyclic redundancy check, the method being applied to a receiving end device, the method comprising: receiving control information; verifying the location according to the input bit and the target CRC bit Control information; wherein the control information includes a payload portion and a target cyclic redundancy check CRC bit, the payload portion including at least one information field, the at least one information field for carrying information bits, the target CRC bit
  • the transmitting device is generated according to an input bit for generating a CRC bit, the input bit including information bits carried in some or all of the information fields in the at least one information field.
  • the present disclosure provides a transmitting device, where the device includes: a first processing module, configured to determine a payload portion, the payload portion includes at least one information field, and the at least one information field is configured to carry information bits
  • the first processing module is further configured to determine an input bit for generating a cyclic redundancy check CRC bit, where the input bit includes information bits carried in part or all of the information fields in the at least one information field;
  • a second processing module configured to generate a target CRC bit according to the input bit; the second processing module is further configured to generate control information including the payload portion and the target CRC bit.
  • the disclosure provides a receiving end device, the device includes: a transceiver module, configured to receive control information, and a processing module, configured to verify the control information according to the input bit and the target CRC bit
  • the control information includes a payload portion and a target cyclic redundancy check CRC bit
  • the payload portion includes at least one information field
  • the at least one information field is for carrying information bits
  • the target CRC bit is a transmitting end
  • the device is generated according to an input bit for generating a CRC bit, the input bit comprising information bits carried in some or all of the information fields in the at least one information field.
  • the present disclosure provides a transmitting end device, the device comprising: a memory, a processor, and a cyclic redundancy check program stored on the memory and operable on the processor, the loop redundancy
  • the processor implements the steps of the method of cyclic redundancy check as described in the first aspect when the remainder check procedure is executed by the processor.
  • the present disclosure provides a receiving end device, the device comprising: a memory, a processor, and a cyclic redundancy check program stored on the memory and operable on the processor, the loop redundancy
  • the processor implements the steps of the method of cyclic redundancy check as described in the second aspect when the remainder check procedure is executed by the processor.
  • the present disclosure provides a computer readable storage medium having a cyclic redundancy check program stored thereon, the processor being executed by a processor when the cyclic redundancy check program is executed by a processor The steps of the method of implementing the cyclic redundancy check as described in the first aspect.
  • the present disclosure provides a computer readable storage medium having a cyclic redundancy check program stored thereon, the processor being executed by a processor when the cyclic redundancy check program is executed by a processor The steps of the method of implementing the cyclic redundancy check as described in the second aspect.
  • the present disclosure provides a computer program product comprising instructions for performing the method of cyclic redundancy check of the first aspect described above when the computer executes the instructions of the computer program product.
  • the computer program product can be run on the transmitting device of the above third aspect.
  • the present disclosure provides a computer program product comprising instructions for performing the method of cyclic redundancy check of the second aspect described above when the computer runs the instructions of the computer program product.
  • the computer program product can be run on the receiving end device of the fourth aspect described above.
  • the present disclosure provides a method of cyclic redundancy check, the method being applied to a transmitting device, the method comprising: determining a payload portion, the payload portion including at least one information field, the at least one An information field is used to carry information bits; a target cyclic redundancy check CRC bit generation manner is determined, and the target CRC bit generation manner is one of a plurality of CRC bit generation manners; according to the payload portion and the target CRC bit Generating a method to generate a CRC bit; generating control information including the payload portion and the CRC bit.
  • the present disclosure provides a method for cyclic redundancy check, the method being applied to a receiving end device, the method comprising: receiving control information; and generating, according to the plurality of CRC bits, the CRC bit And verifying the control information; wherein the control information includes a payload portion and a cyclic redundancy check CRC bit, the payload portion includes at least one information field, and the at least one information field is configured to carry information bits,
  • the CRC bit is generated by the source device according to the target CRC bit generation manner and the payload portion, and the target CRC bit generation manner is one of a plurality of CRC bit generation modes.
  • the present disclosure provides a transmitting device, where the device includes: a first processing module, configured to determine a payload portion, the payload portion includes at least one information field, and the at least one information field is used to carry information
  • the first processing module is further configured to determine a target cyclic redundancy check CRC bit generation manner, where the target CRC bit generation manner is one of multiple CRC bit generation manners; and a second processing module is configured to: Generating a CRC bit according to the payload portion and the target CRC bit generation manner; the second processing module is further configured to generate control information including the payload portion and the CRC bit.
  • the present disclosure provides a receiving end device, the device comprising: a transceiver module, configured to receive control information, and a processing module, configured to perform verification according to the multiple CRC bit generation manners and the CRC bits The control information; wherein the control information includes a payload portion and a cyclic redundancy check CRC bit, the payload portion includes at least one information field, the at least one information field is for carrying information bits, and the CRC bit is The source device generates, according to the target CRC bit generation manner and the payload portion, the target CRC bit generation manner is one of multiple CRC bit generation modes.
  • the present disclosure provides a transmitting device, the device comprising: a memory, a processor, and a cyclic redundancy check program stored on the memory and operable on the processor, the loop
  • the processor implements the steps of the method of cyclic redundancy check as described in the eleventh aspect when the redundancy check procedure is executed by the processor.
  • the present disclosure provides a receiving end device, the device comprising: a memory, a processor, and a cyclic redundancy check program stored on the memory and operable on the processor, the loop
  • the processor implements the steps of the method of cyclic redundancy check as described in the twelfth aspect when the redundancy check procedure is executed by the processor.
  • the present disclosure provides a computer readable storage medium having a cyclic redundancy check program stored thereon, the process being performed when the cyclic redundancy check program is executed by a processor The steps of the method of cyclic redundancy check as described in the eleventh aspect are implemented.
  • the present disclosure provides a computer readable storage medium having a cyclic redundancy check program stored thereon, the process being performed when the cyclic redundancy check program is executed by a processor
  • the steps of the method of cyclic redundancy check as described in the twelfth aspect are implemented.
  • the present disclosure provides a computer program product comprising instructions for performing the method of cyclic redundancy check of the eleventh aspect of the invention when the computer executes the instructions of the computer program product.
  • the computer program product can be run on the transmitting device of the thirteenth aspect.
  • the present disclosure provides a computer program product comprising instructions for performing the method of cyclic redundancy check of the twelfth aspect described above when the computer executes the instructions of the computer program product.
  • the computer program product can be run on the receiving end device of the fourteenth aspect.
  • FIG. 1 is a schematic flow chart 1 of a method of cyclic redundancy check according to some embodiments of the present disclosure
  • FIG. 2 is a schematic flow chart 2 of a method of cyclic redundancy check according to some embodiments of the present disclosure
  • FIG. 3 is a first schematic diagram of an information field, a padding field, and a location of a CRC bit in control information, in accordance with some embodiments of the present disclosure
  • FIG. 4 is a second schematic diagram of information fields, padding fields, and locations of CRC bits in control information, in accordance with some embodiments of the present disclosure
  • FIG. 5 is a schematic flow chart 3 of a method of cyclic redundancy check, in accordance with some embodiments of the present disclosure
  • FIG. 6 is a third schematic diagram of information fields, padding fields, and locations of CRC bits in control information, in accordance with some embodiments of the present disclosure
  • FIG. 7 is a schematic flow chart 4 of a method of cyclic redundancy check, in accordance with some embodiments of the present disclosure.
  • FIG. 9 is a comparison diagram 2 of link performance of a cyclic redundancy check method and a cyclic redundancy check method in the related art according to some embodiments of the present disclosure
  • FIG. 10 is a schematic structural diagram 1 of a transmitting end device according to some embodiments of the present disclosure.
  • FIG. 11 is a second schematic structural diagram of a receiving end device according to some embodiments of the present disclosure.
  • FIG. 12 is a second schematic structural diagram of a transmitting end device according to some embodiments of the present disclosure.
  • FIG. 13 is a second schematic structural diagram of a receiving end device according to some embodiments of the present disclosure.
  • FIG. 14 is a schematic flowchart 5 of a method of cyclic redundancy check, in accordance with some embodiments of the present disclosure.
  • 15 is a schematic flow chart 6 of a method of cyclic redundancy check, in accordance with some embodiments of the present disclosure.
  • 16 is a schematic flowchart 7 of a method of cyclic redundancy check according to some embodiments of the present disclosure
  • 17 is a schematic flowchart of a method of cyclic redundancy check according to some embodiments of the present disclosure
  • FIG. 18 is a third schematic structural diagram of a transmitting end device according to some embodiments of the present disclosure.
  • FIG. 19 is a third schematic structural diagram of a receiving end device according to some embodiments of the present disclosure.
  • 20 is a schematic structural diagram 4 of a transmitting device according to some embodiments of the present disclosure.
  • 21 is a fourth structural diagram of a receiving end device, in accordance with some embodiments of the present disclosure.
  • GSM Global System of Mobile communication
  • CDMA Code Division Multiple Access
  • WCDMA Wideband Code Division Multiple Access
  • GPRS General Packet Radio Service
  • LTE Long Term Evolution
  • FDD Frequency Division Duplex
  • TDD Time Division Duplex
  • UMTS Universal Mobile Telecommunication System
  • WiMAX Worldwide Interoperability for Microwave Access
  • the sender device may be a network device, and correspondingly, the receiver device is a terminal device.
  • the sending end device may be a terminal device, and correspondingly, the receiving end device is a network device.
  • the terminal device may include, but is not limited to, a mobile station (Mobile Station, MS), a mobile terminal (Mobile Terminal), a mobile phone (Mobile Telephone), a user equipment (User Equipment, UE), a mobile phone ( Handset) and portable equipment, vehicle, etc.
  • the terminal device can communicate with one or more core networks via a Radio Access Network (RAN), for example, the terminal device can be a mobile phone (or "cellular" telephone), a computer with wireless communication capabilities, etc., the terminal device can also be a portable, pocket-sized, handheld, computer-integrated or in-vehicle mobile device.
  • RAN Radio Access Network
  • a network device is a device deployed in a wireless access network to provide wireless communication functionality to a terminal device.
  • the network device may be a base station, and the base station may include various forms of macro base stations, micro base stations, relay stations, access points, and the like.
  • the names of devices with base station functionality may vary.
  • an Evolved NodeB eNB or eNodeB
  • 3G 3rd Generation
  • the method and apparatus for cyclic redundancy check may address the problem of poor link performance of a communication system.
  • the check code of the K-bit information code can be produced according to G(x), and G(x) is called the generator polynomial of the CRC code.
  • the specific process of generating the CRC code is as follows: suppose the information to be transmitted is represented by a polynomial C(x), and C(x) is shifted to the left by R bits (which can be expressed as C(x)*2 R ), so that the right side of C(x) The R bit is vacated, and the remainder of the CRC code, divided by C(x)*2 R by the generator polynomial G(x), is the CRC code.
  • FIG. 1 illustrates a method 100 of cyclic redundancy check, which may be performed by a source device, in accordance with some embodiments of the present disclosure. As shown in FIG. 1, method 100 includes steps S110-S140.
  • the payload part includes at least one information field, and at least one information field is used to carry information bits.
  • NR New Radio
  • there are multiple formats of control information and the size of the control information in different formats may be different. If the receiving device is required to blindly detect the format of the control information. In this case, the receiving device has a higher complexity. Therefore, in some embodiments of the present disclosure, different formats are aligned by padding bits at the end of some shorter control information. Control information to reduce the complexity of the receiving device. Padding Bits are usually "0" or “nil” or "1", nil is equal to null, and is "empty” or "invalid".
  • the transmitting device determines whether there is Padding Bits according to the format of the control information to be generated. If it is determined that there is Padding Bits, the payload portion further includes a padding field, and the padding field is used to carry Padding Bits.
  • S120 Determine an input bit for generating a cyclic redundancy check CRC bit, where the input bit includes information bits carried in part or all of the information fields in the at least one information field.
  • the payload portion includes only one information field in S110, in S120, the information bits included in the input bits including some or all of the information fields in at least one information field should be understood as: the input bits include this The information bits carried in an information field.
  • Cyclic Redundancy Check (CRC) bit may also be referred to as a "CRC code.”
  • the source device may generate a target CRC bit according to the manner in which the CRC code described above is generated.
  • S140 Generate control information including a payload portion and a target CRC bit.
  • the CRC bit generation includes the necessary scrambling for the check bits in addition to generating the check bits from the information bits.
  • the RNTI is a 16-bit sequence that is scrambled (ie, XORed) with each bit of the 16-bit RNTI and the 16-bit CRC. Then, at the receiving end, different states use different RNTIs to descramble the CRC, acquire the content on the PDCCH, and finally identify the information belonging to itself on the PDSCH.
  • the source device generates a target CRC bit according to information bits carried in some or all of the information fields in the at least one information field, so that the receiving device performs the control information.
  • the receiving device considers the control information If the transmission error occurs, or if the information bits are not correctly transmitted and the important information bits are not wrong, and the part of the error-transmitting information bits can be tolerated, the receiving device considers that the control information is transmitted incorrectly, and improves the link of the communication system. performance.
  • FIG. 2 is a method of cyclic redundancy check, as shown in FIG. 2, in which method 200 includes steps S210-S270, in accordance with some embodiments of the present disclosure.
  • the source device determines that there are padding bits, and the source device supplements the padding bits to form a payload portion (Information Packs).
  • the information Bits to be sent are carried in at least one information field, and the Padding Bits are carried in the padding field.
  • the transmitting device calculates the CRC bit according to all Information Bits.
  • the source device determines, as specified by the protocol, that all Information Bits need to be used as input bits (Input Bits) for calculating CRC bits.
  • the transmitting device determines, according to the agreement with the receiving device, that all Information Bits need to be used as input bits for calculating the CRC bits.
  • the transmitting device decides to use all Information Bits as input bits for calculating the CRC bits.
  • the transmitting device needs to send configuration information to the receiving device, and informs the receiving device through configuration information that the CRC bit needs to be calculated. All Information Bits are used as input bits.
  • the sending device can send the configuration information to the receiving device in the high layer signaling.
  • the transmitting device attaches the CRC bit to the payload portion to form control information.
  • the position of the CRC bit and payload portion in the control information is as shown in FIG. 3 or 4.
  • the location of the padding field is between the location of at least one information field and the location of the CRC bits.
  • the location of the CRC bits is between the location of at least one information field and the location of the padding bits.
  • the location of the CRC bit and the payload part in the control information may be specified by the protocol, or may be agreed by the sender device and the receiver device in advance, or may be notified by the sender device through configuration information. Receiver device.
  • the first information field in the at least one information field is used to indicate the format of the control information
  • the receiving device parses the control information according to the format of the control information indicated by the first information field, that is, the control information may be obtained.
  • the first information field used to indicate the format of the control information takes a different value to indicate a different format. For example, suppose that there are four types of control information in the communication system, which are format AA, format BB, format CC, and format DD.
  • the first information field for indicating the format of the control information includes 2 bits, and then " 00" indicates that the format of the control information is “format AA”, "01” indicates that the format of the control information is "format BB”, the format of the control information is indicated by "10” as “format CC”, and the control information is indicated by "11”
  • the format is "Format DD".
  • the format of the control information is used by the receiving end device to determine the total length of the at least one information field.
  • the length of the Payload and the length of the CRC bit can be known by pre-configuration or prior agreement.
  • the format and control of the configuration information of the transmitting device can be specified by the protocol.
  • the total length of the at least one information field included in the information has a corresponding relationship, and the receiving end device may determine, according to the format of the received control information and the foregoing correspondence, the total length of the received control information including at least one information field, and then obtain Information Bits carried in all information fields in at least one information field.
  • the sending end device sends control information to the receiving end device.
  • the sending end device may use a Radio Network Temporary Identity (RNTI) to scramble the control information, and send the scrambled control information to the receiving end device.
  • RNTI Radio Network Temporary Identity
  • the receiving end device determines a total length of the at least one information field and a location of the at least one information field in the control information.
  • the receiving end device may acquire the information bits carried in all the information fields in the at least one information field according to the total length of the at least one information field and the position of the at least one information field in the control information.
  • the receiving end device determines a format of the received control information according to a field in the at least one information field for indicating a format of the control information, and then according to the format of the control information and at least the control information.
  • the correspondence between the total length of an information field and the format of the received control information determines the total length of at least one information field included in the received control information.
  • the receiving end device may determine the location of the at least one information field in the control information according to the protocol, and the receiving end device may determine that at least one information field is controlled according to an agreement with the transmitting device. The location in the information, the receiving device may also determine the location of the at least one information field in the control information according to the configuration information sent by the sending device.
  • the receiving end device performs verification according to information bits and CRC bits carried in all information fields in the at least one information field.
  • the receiving end device performs verification according to information bits and CRC bits carried in all information fields in at least one information field, which can be understood as: the receiving end device bears according to all information fields in at least one information field.
  • the information bits and the CRC bits check the control information, or can be understood as: the receiving end device verifies all the information bits in the control information according to the information bits and CRC bits carried in all the information fields in the at least one information field. .
  • the receiving end device calculates a CRC bit according to the information bits carried in all the information fields in the at least one information field, and compares the calculated CRC bits with the CRC bits in the control information.
  • S270 Determine, according to the result of the verification, whether the control information is correctly transmitted.
  • control information transmission is considered to be correct in S270, otherwise the control information transmission error is considered.
  • FIG. 5 is a schematic flow diagram of a method of cyclic redundancy check, in accordance with some embodiments of the present disclosure. As shown in FIG. 5, method 300 includes steps S310-S370.
  • the sending end device determines that there is Padding Bits, and the sending end device supplements the Padding Bits to the Information Bits to be sent to form a Payload.
  • the information Bits to be sent are carried in at least one information field, and the Padding Bits are carried in the padding field.
  • the sender device calculates a CRC bit according to part of the Information Bits in the Information Bits.
  • the transmitting device calculates the CRC bit according to the Information Bits carried in the partial information field in the at least one information field.
  • the transmitting device determines, as specified by the protocol, that part of the Information Bits needs to be input bits (Input Bits) for calculating CRC bits. Or the transmitting device determines, according to the agreement with the receiving device, that part of the Information Bits needs to be used as an input bit for calculating the CRC bits. Or the transmitting device decides to use part of the Information Bits as the input bit for calculating the CRC bit. In this case, the transmitting device needs to send configuration information to the receiving device, and informs the receiving device through the configuration information that the CRC bit needs to be calculated. Part of the Information Bits as input bits. The sending device can send the configuration information to the receiving device in the high layer signaling.
  • the transmitting device and the receiving device may agree in advance to generate CRC bits according to information bits carried in which information fields in the control information.
  • the uplink control information (UCI) is taken as an example. It is assumed that the UCI includes a field of Acknowledgement (ACK)/Non-Acknowledgement (NACK) information and a Scheduling Request (SR).
  • ACK Acknowledgement
  • NACK Non-Acknowledgement
  • SR Scheduling Request
  • the field and the field carrying the channel state information (CSI) the transmitting device and the receiving device may implement a convention to generate a CRC bit according to the field carrying the ACK/NACK and the information bit carried in the field carrying the SR.
  • the sending end device may notify, by using configuration information, that the receiving end device needs to generate CRC bits according to which information bits are carried in the field, that is, when the configuration information indicates that the input bit includes the part information field.
  • the configuration information is also used to indicate partial information fields.
  • the UCI in the above example may be used by the sending end device to indicate that the CRC bit needs to be generated according to the field carrying the ACK/NACK and the information bit carried in the field carrying the SR.
  • the transmitting device attaches the CRC code to the payload portion to form control information.
  • the location of the CRC bits and payload portion in the control information is as shown in FIG.
  • the location of the CRC bit and payload portion in the control information is shown in Figure 6.
  • the position of the CRC bit is after the position of the partial information field for generating the CRC bit and before the position of the other information field, the padding field is located at the end of the control information.
  • the sending end device sends control information to the receiving end device.
  • the sending end device may use the RNTI to scramble the control information, and send the scrambled control information to the receiving end device.
  • the receiving end device determines a total length of the at least one information field and a location of the at least one information field in the control information.
  • the receiving end device may acquire the information bits carried in all the information fields in the at least one information field according to the total length of the at least one information field and the position of the at least one information field in the control information, and then The information bits carried in the partial information field serve as input bits for generating CRC bits.
  • the receiving end device performs verification according to the information bits and the CRC bits carried in the partial information field in the at least one information field.
  • the receiving end device performs verification according to the information bits and CRC bits carried in the partial information field in the at least one information field, which can be understood as: the receiving end device carries the information according to the partial information field in the at least one information field.
  • the information bits and the CRC bits check the control information, or can be understood as: the receiving device checks the partial information bits in the control information according to the information bits and CRC bits carried in the partial information fields in the at least one information field. .
  • the receiving end device may determine the partial information field according to the specification or protocol of the sending end device, and the receiving end device may further determine the partial information field according to the configuration information of the sending end device.
  • the information bits carried in the second information field in the at least one information field are predetermined bits (or fixed bits), and the receiving end device may determine, according to the transmission condition of the predetermined bits, whether the control information is It is effective to judge whether the transmission of control information is a false alarm, which can meet the requirements of the control information for false alarms. In this case, if the receiving device checks the control information successfully, the receiving device further determines the transmission condition of the predetermined bit.
  • the predetermined bit transmission determines that the control information is valid, and the transmission of the control information is not a false alarm; if it is determined If the predetermined bit transmission error occurs, it is determined that the control information is invalid, and the transmission of the control information is a false alarm.
  • FIG. 7 illustrates a method 400 of cyclic redundancy check, which may be performed by a sink device, in accordance with some embodiments of the present disclosure. It can be understood that the interaction between the sender device and the receiver device described on the receiving device side is the same as that on the device at the transmitting end. To avoid repetition, the related description is omitted as appropriate. As shown in FIG. 7, method 400 includes steps S410-S420.
  • the control information includes a payload portion and a target cyclic redundancy check CRC bit, the payload portion includes at least one information field, the at least one information field is used to carry information bits, and the target CRC bit is a sender device.
  • the input bits include information bits carried in some or all of the information fields in the at least one information field.
  • the CRC bit in the control signal received by the receiving end device is generated by the transmitting end device according to information bits carried in part or all of the information fields in the at least one information field.
  • the control device checks the control information, it only checks the information bits carried in some or all of the information fields in the at least one information field, so as to avoid the information bit transmission in the control information without error and padding the bits.
  • the transmission error occurs, or if the information bits are not correctly transmitted and the important information bits are not wrong, and the part of the information bit receiving the error can be tolerated, the receiving device considers that the control information is transmitted incorrectly, and the receiving device considers that the control information is transmitted. In the case of an error, the link performance of the communication system is improved.
  • the payload portion further includes a padding field, where the padding field is used to carry padding bits; wherein the input bit includes all information fields in the at least one information field Information bits carried in the location of the padding field in the control information between a location of the at least one information field and a location of the target CRC bit, or the target CRC bit is in the control information The location in is between the location of the at least one information field and the location of the padding field.
  • the payload portion further includes a padding field, where the padding field is used to carry padding bits; wherein the input bit includes a partial information field in the at least one information field Information bits carried in the location of the padding field in the control information between a location of the at least one information field and a location of the target CRC bit, or the target CRC bit is in the control The location in the information is between the location of the partial information field and the other information fields in the at least one information field and the location of the padding field.
  • the first information field in the at least one information field is used to indicate a format of the control information; wherein, according to the input bit and the target CRC bit, Before verifying the control information, the receiving end device acquires the input bit according to the format of the control information.
  • the receiving end device obtains input bits by parsing the control information according to a format of the control information.
  • the format of the control information is used by the receiving end device to determine a total length of the at least one information field.
  • the receiving end device determines the total length of the at least one information field according to the format of the control information, and acquires the input bit according to the total length of the at least one information field.
  • the information bits carried in the second information field in the at least one information field are predetermined bits, and the predetermined bits are used for transmission by the receiving end device according to the predetermined bit. Determining whether the control information is valid, and if the receiving end device verifies that the control information is successful, the receiving end device determines whether the control information is valid according to the transmission condition of the predetermined bit; if the predetermined bit If the transmission is correct, it is determined that the control information is valid; if the predetermined bit transmission is incorrect, it is determined that the control information is invalid.
  • the receiving end device receives configuration information sent by the sending end device, before the verifying the control information according to the input bit and the target CRC bit, the configuration information. And indicating that the input bit includes information bits carried in a part or all of the information fields in the at least one information field. The receiving device acquires the input bit according to the configuration information.
  • the configuration information is used to indicate that the input bit includes information bits carried in a partial information field in the at least one information field
  • the configuration information is further used. Indicating the partial information field.
  • the receiving end device determines, according to the configuration information, that the CRC bits are generated according to information bits carried in which information fields in the at least one information field.
  • the number of Information Bits is 40, and the number of Padding Bits is 20.
  • the circled solid line in FIG. 8 is the relationship between the block error rate and the signal-to-noise ratio obtained by the method according to some embodiments of the present disclosure.
  • the dotted dotted line is a relationship between the block error rate and the signal-to-noise ratio obtained according to the method in the related art.
  • the number of Information Bits is 50, and the number of Padding Bits is 10.
  • the circled solid line in FIG. 9 is the relationship between the block error rate and the signal-to-noise ratio obtained by the method according to some embodiments of the present disclosure.
  • the broken line is a relationship between the block error rate and the signal-to-noise ratio obtained according to the method in the related art. It can be seen that the link performance of the cyclic redundancy check method using some embodiments of the present disclosure is better than the link gain of the method using the cyclic check in the related art, specifically, the required block error rate is 1%.
  • the method of some embodiments of the present disclosure has a link gain of about 0.25 dB relative to the related art method.
  • FIG. 10 is a schematic structural diagram of a transmitting device according to some embodiments of the present disclosure. As shown in FIG. 10, the transmitting device 10 includes a first processing module 11 and a second processing module 12.
  • the first processing module 11 is configured to determine a payload portion, where the payload portion includes at least one information field, where the at least one information field is used to carry information bits, and the first processing module 11 is further configured to determine a loop for generating The input bits of the CRC bits are redundantly checked, the input bits comprising information bits carried in some or all of the information fields in the at least one information field.
  • the second processing module 12 is configured to generate a target CRC bit according to the input bit, and the second processing module 12 is further configured to generate control information including the payload portion and the target CRC bit.
  • the transmitting end device generates a target CRC bit according to information bits carried in some or all of the information fields in the at least one information field, so that the receiving end device only checks at least one when verifying the control information.
  • the information bits carried in some or all of the information fields in the information field are checked to avoid that when the information bit transmission in the control information is not errored and the bit transmission error occurs, the receiving device considers that the control information is transmitted incorrectly, or avoids Some information bits are misrouted and important information bits are not error.
  • the receiving device considers that the control information is transmitted incorrectly, and improves the link performance of the communication system.
  • the payload part further includes a padding field, where the padding field is used to carry padding bits, where the input bit includes information bits carried in all information fields in the at least one information field. And a location of the padding field in the control information between a location of the at least one information field and a location of the target CRC bit, or a location of the target CRC bit in the control information Between the location of the at least one information field and the location of the padding field.
  • the payload part further includes a padding field, where the padding field is used to carry padding bits, where the input bit includes information bits carried in a part of the information field in the at least one information field.
  • a position of the padding field in the control information is between a location of the at least one information field and a location of the target CRC bit, or a location of the target CRC bit in the control information is The location of the partial information field and the other information field in the at least one information field and the location of the padding field.
  • the first information field in the at least one information field is used to indicate a format of the control information.
  • the format of the control information is used by the receiving end device to determine a total length of the at least one information field.
  • the information bit carried in the second information field in the at least one information field is a predetermined bit, where the predetermined bit is used by the receiving end device to determine the control according to the transmission condition of the predetermined bit. Whether the information is valid.
  • the first processing module 11 is further configured to: send configuration information to the receiving end device, where the configuration information is used to indicate that the input bit includes part or all of the at least one information field. Information bits carried in the information field.
  • the configuration information when the configuration information indicates that the input bit includes an information bit carried in a partial information field in the at least one information field, the configuration information is further used to indicate the partial information field.
  • the transmitting device may refer to the processes of the method 100 to the method 300 corresponding to some embodiments of the present disclosure, and the respective units/modules in the transmitting device and the above other operations and/or functions respectively In order to implement the corresponding processes in the method 100 to the method 300, for brevity, details are not described herein again.
  • the receiving end device 20 includes a transceiver module 21 and a processing module 22.
  • the transceiver module 21 is configured to receive control information
  • the processing module 22 is configured to verify the control information according to the input bit and the target CRC bit.
  • the control information includes a payload portion and a target cyclic redundancy check CRC bit, the payload portion includes at least one information field, the at least one information field is used to carry information bits, and the target CRC bit is a sender device.
  • the input bits include information bits carried in some or all of the information fields in the at least one information field.
  • the CRC bit in the control signal received by the receiving end device is generated by the transmitting end device according to information bits carried in part or all of the information fields in the at least one information field, and the receiving end device is in the control of the pair.
  • the receiving end device When the information is verified, only the information bits carried in some or all of the information fields in at least one information field are verified, so as to avoid that the information bit transmission in the control information is not errored and the bit transmission error occurs, the receiving device considers Control the transmission of information, or avoid the error of some information bits and the error of important information bits.
  • the receiving device considers that the control information is transmitted incorrectly, and improves the communication system. Link performance.
  • the payload part further includes a padding field, where the padding field is used to carry padding bits, where the input bit includes information bits carried in all information fields in the at least one information field. And a location of the padding field in the control information between a location of the at least one information field and a location of the CRC bit, or a location of the CRC bit in the control information at the at least Between the location of an information field and the location of the padding field.
  • the payload part further includes a padding field, where the padding field is used to carry padding bits, where the input bit includes information bits carried in a part of the information field in the at least one information field. a location of the padding field in the control information between a location of the at least one information field and a location of the CRC bit, or a location of the CRC bit in the control information in the The location of the partial information field and the other information field in the at least one information field and the location of the padding field.
  • the first information field in the at least one information field is used to indicate a format of the control information
  • the processing module 22 is further configured to: obtain, according to a format of the control information, The input bit.
  • the format of the control information is used by the receiving end device to determine a total length of the at least one information field, where the processing module 22 is specifically configured to: determine, according to a format of the control information, The total length of the at least one information field; the input bit is obtained according to a total length of the at least one information field.
  • the information bit carried in the second information field in the at least one information field is a predetermined bit, where the predetermined bit is used by the receiving end device to determine the control according to the transmission condition of the predetermined bit.
  • the processing module 22 is further configured to: if the control information is successful, determine whether the control information is valid according to the transmission condition of the predetermined bit; if the predetermined bit transmission is correct, determine The control information is valid; if the predetermined bit transmission is incorrect, it is determined that the control information is invalid.
  • the transceiver module 21 is further configured to: receive configuration information sent by the sending end device, where the configuration information is used to indicate that the input bit includes some or all of the information in the at least one information field.
  • the information bits carried in the field wherein the processing module 22 is further configured to: acquire the input bit according to the configuration information.
  • the configuration information when the configuration information is used to indicate that the input bit includes an information bit carried in a partial information field in the at least one information field, the configuration information is further used to indicate the part. Information field.
  • the receiving end device may refer to the flow of the method 200 to the method 400 corresponding to some embodiments of the present disclosure, and the respective units/modules in the receiving end device and the other operations and/or functions described above respectively In order to implement the corresponding processes in the method 200 to the method 400, for brevity, details are not described herein again.
  • FIG. 12 shows a schematic structural diagram of a transmitting end device, which can implement the details of the method of cyclic redundancy check in the method 100 to the method 300, and can achieve the same effect, according to some embodiments of the present disclosure.
  • the source device 100 includes a processor 110, a transceiver 120, a memory 130, and a bus interface.
  • the source device 100 further includes: a computer program stored on the memory 130 and operable on the processor 110, the computer program being executed by the processor 110 to perform the following Step: determining a payload portion, the payload portion including at least one information field, the at least one information field for carrying information bits; determining input bits for generating a cyclic redundancy check CRC bit, the input bits including the Information bits carried in some or all of the information fields in at least one information field; generating a target CRC bit according to the input bits; generating control information including the payload portion and the target CRC bits.
  • the bus architecture can include any number of interconnected buses and bridges, specifically linked by one or more processors represented by processor 110 and various circuits of memory represented by memory 130.
  • the bus architecture can also link various other circuits such as peripherals, voltage regulators, and power management circuits, which are well known in the art and, therefore, will not be further described herein.
  • the bus interface provides an interface.
  • Transceiver 120 can be a plurality of components, including a transmitter and a receiver, providing means for communicating with various other devices on a transmission medium.
  • the processor 110 is responsible for managing the bus architecture and general processing, and the memory 130 can store data used by the processor 110 in performing operations.
  • the following steps may be further: sending configuration information to the receiving device, where the configuration information is used to indicate that the input bit includes some or all of the information in the at least one information field.
  • the information bits carried in the field may be further: sending configuration information to the receiving device, where the configuration information is used to indicate that the input bit includes some or all of the information in the at least one information field.
  • the information bits carried in the field may be further: sending configuration information to the receiving device, where the configuration information is used to indicate that the input bit includes some or all of the information in the at least one information field.
  • the payload part further includes a padding field, where the padding field is used to carry padding bits, where the input bit includes information bits carried in all information fields in the at least one information field. And a location of the padding field in the control information between a location of the at least one information field and a location of the target CRC bit, or a location of the target CRC bit in the control information Between the location of the at least one information field and the location of the padding field.
  • the payload part further includes a padding field, where the padding field is used to carry padding bits, where the input bit includes information bits carried in a part of the information field in the at least one information field.
  • a position of the padding field in the control information is between a location of the at least one information field and a location of the target CRC bit, or a location of the target CRC bit in the control information is The location of the partial information field and the other information field in the at least one information field and the location of the padding field.
  • the first information field in the at least one information field is used to indicate a format of the control information.
  • the format of the control information is used by the receiving end device to determine a total length of the at least one information field.
  • the information bit carried in the second information field in the at least one information field is a predetermined bit, where the predetermined bit is used by the receiving end device to determine the control according to the transmission condition of the predetermined bit. Whether the information is valid.
  • the configuration information when the configuration information indicates that the input bit includes an information bit carried in a partial information field in the at least one information field, the configuration information is further used to indicate the partial information field.
  • the transmitting end device generates a target CRC bit according to information bits carried in some or all of the information fields in the at least one information field, so that the receiving end device only checks at least one when verifying the control information.
  • the information bits carried in some or all of the information fields in the information field are checked to avoid that when the information bit transmission in the control information is not errored and the bit transmission error occurs, the receiving device considers that the control information is transmitted incorrectly, or avoids Some information bits are mis-transmitted and important information bits are not error. When the error-transmitting part of the information bit can be tolerated, the receiving end device considers that the control information transmission error occurs, and improves the link performance of the communication system.
  • the transmitting device 100 may refer to the transmitting device 10 corresponding to some embodiments of the present disclosure, and the respective units/modules in the transmitting device and the other operations and/or functions described above are respectively implemented
  • the corresponding processes in the method 100 to the method 300 are not described herein for the sake of brevity.
  • the receiving end device 200 includes: at least one processor 210, a memory 220, at least one network interface 230, and a user interface 240. .
  • the various components in the sink device 200 are coupled together by a bus system 250.
  • bus system 250 is used to implement connection communication between these components.
  • the bus system 250 includes, in addition to the data bus, a power bus, a control bus, and a status signal bus. However, for clarity of description, various buses are labeled as bus system 250 in FIG.
  • the user interface 240 may include a display, a keyboard, or a pointing device (eg, a mouse, a trackball, a touchpad, or a touch screen, etc.).
  • a pointing device eg, a mouse, a trackball, a touchpad, or a touch screen, etc.
  • the memory 220 in some embodiments of the present disclosure may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memory.
  • the non-volatile memory may be a read-only memory (ROM), a programmable read only memory (PROM), an erasable programmable read only memory (Erasable PROM, EPROM), or an electric Erase programmable read only memory (EEPROM) or flash memory.
  • the volatile memory can be a Random Access Memory (RAM) that acts as an external cache.
  • RAM Random Access Memory
  • many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (Synchronous DRAM, SDRAM).
  • Double data rate synchronous dynamic random access memory Double Data Rate SDRAM, DDRSDRAM
  • enhanced synchronous dynamic random access memory ESDRAM
  • synchronously connected dynamic random access memory Synchronization RAM, SLDRAM
  • Direct memory bus random access memory DirectRambus RAM, DRRAM.
  • the memory 220 of the systems and methods described in some embodiments of the present disclosure is intended to comprise, without being limited to, these and any other suitable types of memory.
  • memory 220 stores elements, executable modules or data structures, or a subset thereof, or their extended set: operating system 221 and application 222.
  • the operating system 221 includes various system programs, such as a framework layer, a core library layer, a driver layer, and the like, for implementing various basic services and processing hardware-based tasks.
  • the application 222 includes various applications, such as a Media Player, a Browser, etc., for implementing various application services. Programs that implement some of the embodiment methods of the present disclosure may be included in the application 222.
  • the sink device 200 further includes a computer program stored on the memory 220 and executable on the processor 210.
  • the processor 210 implements the following steps: receiving control Information; verifying the control information according to the input bit and the target CRC bit; wherein the control information includes a payload portion and a target cyclic redundancy check CRC bit, the payload portion including at least one information field, The at least one information field is for carrying information bits, and the target CRC bit is generated by the transmitting end device according to an input bit for generating a CRC bit, the input bit including some or all of the information in the at least one information field The information bits carried in the field.
  • Processor 210 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the foregoing method may be completed by an integrated logic circuit of hardware in the processor 210 or an instruction in a form of software.
  • the processor 210 may be a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or the like. Programmable logic devices, discrete gates or transistor logic devices, discrete hardware components.
  • the methods, steps, and logical block diagrams disclosed in some embodiments of the present disclosure may be implemented or performed.
  • the general purpose processor may be a microprocessor or the processor or any conventional processor or the like.
  • the steps of the method disclosed in connection with some embodiments of the present disclosure may be directly embodied by the hardware decoding processor, or by a combination of hardware and software modules in the decoding processor.
  • the software modules can be located in a conventional computer readable storage medium of the art, such as random access memory, flash memory, read only memory, programmable read only memory or electrically erasable programmable memory, registers, and the like.
  • the computer readable storage medium is located in the memory 220, and the processor 210 reads the information in the memory 220 and, in conjunction with its hardware, performs the steps of the above method.
  • the computer readable storage medium stores a computer program, and when the computer program is executed by the processor 210, the processor 210 implements the steps of the method embodiment in the method 200 to the method 400 described above.
  • the processing unit can be implemented in one or more Application Specific Integrated Circuits (ASICs), Digital Signal Processing (DSP), Digital Signal Processing Equipment (DSP Device, DSPD), programmable Programmable Logic Device (PLD), Field-Programmable Gate Array (FPGA), general purpose processor, controller, microcontroller, microprocessor, other for performing the functions described in this disclosure In an electronic unit or a combination thereof.
  • ASICs Application Specific Integrated Circuits
  • DSP Digital Signal Processing
  • DSP Device Digital Signal Processing Equipment
  • PLD programmable Programmable Logic Device
  • FPGA Field-Programmable Gate Array
  • the techniques described in some embodiments of the present disclosure may be implemented by modules (e.g., procedures, functions, etc.) that perform the functions described in some embodiments of the present disclosure.
  • the software code can be stored in memory and executed by the processor.
  • the memory can be implemented in the processor or external to the processor.
  • the following steps may be implemented: receiving configuration information sent by the sending device, where the configuration information is used to indicate that the input bit includes some or all of the at least one information field. Information bits carried in the information field; the input bits are obtained according to the configuration information.
  • the payload part further includes a padding field, where the padding field is used to carry padding bits, where the input bit includes information bits carried in all information fields in the at least one information field. And a location of the padding field in the control information between a location of the at least one information field and a location of the target CRC bit, or a location of the target CRC bit in the control information Between the location of the at least one information field and the location of the padding field.
  • the payload part further includes a padding field, where the padding field is used to carry padding bits, where the input bit includes information bits carried in a part of the information field in the at least one information field.
  • a position of the padding field in the control information is between a location of the at least one information field and a location of the target CRC bit, or a location of the target CRC bit in the control information is The location of the partial information field and the other information field in the at least one information field and the location of the padding field.
  • the first information field in the at least one information field is used to indicate a format of the control information; wherein, when the computer program is executed by the processor 210, the processor 210 may further implement the following steps: The format of the control information acquires the input bit.
  • the format of the control information is used by the receiving end device to determine a total length of the at least one information field; wherein, when the computer program is executed by the processor 210, the processor 210 may further implement the following steps: Formatting the control information, determining a total length of the at least one information field; acquiring the input bit according to a total length of the at least one information field.
  • the information bit carried in the second information field in the at least one information field is a predetermined bit, where the predetermined bit is used by the receiving end device to determine the control according to the transmission condition of the predetermined bit.
  • the processor 210 may further implement the following steps: if the control information is successfully verified, determining whether the control information is valid according to the transmission condition of the predetermined bit; If the predetermined bit transmission is correct, it is determined that the control information is valid; if the predetermined bit transmission is incorrect, it is determined that the control information is invalid.
  • the configuration information when the configuration information is used to indicate that the input bit includes an information bit carried in a partial information field in the at least one information field, the configuration information is further used to indicate the part. Information field.
  • the CRC bit in the control signal received by the receiving end device is generated by the transmitting end device according to information bits carried in part or all of the information fields in the at least one information field, and the receiving end device is in the control of the pair.
  • the receiving end device When the information is verified, only the information bits carried in some or all of the information fields in at least one information field are verified, so as to avoid that the information bit transmission in the control information is not errored and the bit transmission error occurs, the receiving device considers Control the transmission of information error, or avoid the error of some information bits and the important information bits are not wrong.
  • the receiving part of the error is tolerable, the receiving device considers that the control information is transmitted incorrectly, and improves the chain of the communication system. Road performance.
  • the receiving end device 200 may refer to the receiving end device 20 corresponding to some embodiments of the present disclosure, and the respective units/modules in the receiving end device and the other operations and/or functions described above are respectively implemented
  • the corresponding processes in the method 200 to the method 400 are not described herein for the sake of brevity.
  • the transmitting end device generates a CRC bit according to all the information bits or partial information bits in the control information, and the transmitting end device may only use all the information bits in the control information when verifying the control information. Or some information bits are verified. Therefore, the method disclosed in the above embodiment of the present disclosure avoids the case where the receiving end device considers that the control information transmission is in error when the information bit transmission is not erroneous and the padding bit transmission error occurs, or avoids the partial information bit being transmitted and the important information bit is not. Error, when the part of the error-transmitting information bit can be tolerated, the receiving end device considers that the control information transmission error occurs, and improves the link performance of the communication system.
  • FIG. 14 illustrates a method 1400 of cyclic redundancy check performed by a source device in accordance with some embodiments of the present disclosure. As shown in FIG. 14, method 1400 includes steps S1410-S1440.
  • S1410 Determine a payload portion, where the payload portion includes at least one information field, and at least one information field is used to carry information bits.
  • the size of the control information in different formats may be different. If the receiving device is required to blindly detect the format of the control information. This will result in higher complexity for the receiving device. Therefore, in some embodiments of the present disclosure, the control information of different formats is aligned by adding Padding Bits at the end of some shorter control information to reduce the complexity of the receiving device. Padding Bits are usually "0".
  • the transmitting device determines whether there is Padding Bits according to the format of the control information to be generated. If it is determined that there is Padding Bits, the payload portion further includes a padding field, and the padding field is used to carry Padding Bits.
  • S1420 Determine a target cyclic redundancy check CRC bit generation manner, and the target CRC bit generation manner is one of multiple CRC bit generation modes.
  • a Cyclic Redundancy Check (CRC) bit may also be referred to as a “CRC code”, and a difference in different CRC bit generation manners is a process of generating a CRC bit.
  • the difference between the input bits Input Bits).
  • the multiple CRC bit generation manners include at least two of the following manners: using information bits carried in all information fields in the at least one information field as input of a process of generating the CRC bits a bit; an information bit carried in a partial information field in the at least one information field as an input bit of a process of generating the CRC bit; all bits carried in the payload portion as a process of generating the CRC bit Enter the bit.
  • the transmitting end device and the receiving end device may agree in advance on the control information.
  • the information bits carried in the information fields are used as input bits of the process of generating the CRC bits, or the transmitting device can inform the receiving end device of which information bits carried in the fields as the input bits of the process of generating the CRC bits through the configuration information.
  • the uplink control information is taken as an example. It is assumed that the UCI includes a field of Acknowledgement (ACK)/Non-Acknowledgement (NACK) information and a Scheduling Request (SR).
  • the field and the field of the channel state information (CSI), the transmitting device and the receiving device may pre-arrange the process of carrying the ACK/NACK field and the information bit carried in the field carrying the SR as the process of generating the CRC bit. Input bit.
  • the sending end device may indicate, by using the configuration information, that the receiving end device uses the information bit carried in the field carrying the ACK/NACK and the field carrying the SR as the input bit of the process of generating the CRC bit.
  • the information bits carried by all the information fields in the at least one information field are used as input bits of the process of generating the CRC bits, or the information bits carried by the partial information fields in the at least one information field are used as the process of generating the CRC bits.
  • the input bit is compared with the input bit of the related art in which all the bits carried by the entire payload portion are used as the input bits of the process of generating the CRC bit, and the receiving end device can be avoided when the information bit transmission in the control information is not errored and the bit transmission error occurs. It is considered that the control information transmission error occurs, and the link performance of the communication system is improved.
  • the transmitting device determines the target CRC bit generation manner according to the format of the control information; and/or the type of the wireless network temporary identifier used by the transmitting device according to the scrambling control information. Determine the target CRC bit generation method.
  • S1430 Generate a CRC bit according to the payload part and the target CRC bit generation manner.
  • the transmitting end device determines, according to the target CRC bit generation manner, a bit of an input bit of a process of generating a CRC bit among all bits carried in the payload portion, and generates a CRC according to the determined bit as an input bit. Bit.
  • S1440 Generate control information including the payload portion and the CRC bit.
  • the payload portion further includes a padding field in S1410, and the position of the CRC bit and the payload portion in the control information is as shown in Fig. 3 or Fig. 4.
  • the location of the padding field is between the location of at least one information field and the location of the CRC bits.
  • the location of the CRC bits is between the location of at least one information field and the location of the padding field.
  • the location of the CRC bit and the payload part in the control information may be specified by the protocol, or may be agreed by the sender device and the receiver device in advance, or may be notified by the sender device through configuration information. Receiver device.
  • one of the at least one information field included in the payload portion of the control information is used to indicate a format of the control information, and the receiving device performs the control information according to the format of the control information indicated by the information field. Parsing, that is, all the bits carried by the payload part can be obtained.
  • the information field used to indicate the format of the control information takes a different value to indicate a different format. For example, suppose that there are four types of control information in the communication system, which are format AA, format BB, format CC, and format DD.
  • the information field for indicating the format of the control information includes 2 bits, and then "00" can be used.
  • the format of the indication control information is “format AA”, “01” indicates that the format of the control information is “format BB”, the format of the control information is indicated by “10” is “format CC”, and the format of the control information indicated by “11” is "Format DD".
  • the length of the Payload and the length of the CRC bit may be known by pre-configuration or prior agreement.
  • the format and control of the configuration information of the transmitting device may be specified by the protocol.
  • the total length of the at least one information field included in the information has a corresponding relationship, and the receiving end device may determine, according to the format of the received control information and the foregoing correspondence, the total length of the received control information including at least one information field, and then obtain Information Bits carried in all information fields in at least one information field.
  • the information bits carried in one information field of the at least one information field are predetermined bits (or fixed bits), and the receiving end device may determine, according to the transmission condition of the predetermined bits, whether the control information is valid, thereby It is judged whether the transmission of the control information is a false alarm, and can satisfy the requirement of the control information for the false alarm. In this case, if the receiving device checks the control information successfully, the receiving device further determines the transmission condition of the predetermined bit.
  • the predetermined bit transmission error If it is determined that the predetermined bit transmission is correct, it is determined that the control information is valid, and the transmission of the control information is not a false alarm (False Alarm) If the predetermined bit transmission error is determined, it is determined that the control information is invalid, and the transmission of the control information is a false alarm.
  • 15 is a method of cyclic redundancy check, as shown in FIG. 15, the method 1500 includes steps S1510-S1590, in accordance with some embodiments of the present disclosure.
  • the sender device determines the format of the control information to be sent.
  • control information is Downlink Control Information (DCI), and the format of the control information is one of the following formats: “0”, “1”, “1A”, “1B”, “1C”, “1D”, “2", “2A”, “2B”, “3”, “3A”.
  • DCI Downlink Control Information
  • the sender device determines that there is Padding Bits, and the sender device supplements the Padding Bits to the Information Bits to be sent to form a Payload.
  • the source device determines a target CRC bit generation manner according to a format of the control information, and generates a CRC bit according to the target CRC bit generation manner.
  • the target CRC bit generation manner is one of a plurality of CRC bit generation manners described in method 1400.
  • the sending end device selects different target CRC bit generating manners for different format control information of the same payload part length.
  • DCI DCI
  • the DCI of the format "1A” and the DCI of the format “0” may have the same size, but the contents are different.
  • the DCI of the format “1A” is used for scheduling of downlink data, and is not sensitive to False Alarm
  • the DCI of format "0" is used for scheduling of uplink data, and is sensitive to False Alarm.
  • the target CRC bit determined by the source device is generated by using information bits carried by all information fields in at least one information field as input bits of a process of generating CRC bits, or at least The information bits carried by the partial information fields in one information field serve as input bits for the process of generating CRC bits.
  • the target CRC bit determined by the source device is generated by using all bits carried in the payload portion as input bits of a process of generating the CRC bits.
  • the information bits generated in the control information generated in S1540 are carried in at least one information field, and the Padding Bits are carried in the padding field, and the location of the at least one information field, the padding field, and the CRC bit in the control information is as shown in FIG. 3 and Figure 4 shows.
  • S1550 The sending end device sends control information to the receiving end device.
  • the sending device is a network device
  • the receiving device is a terminal device
  • the network device sends the DCI to the terminal device on a Physical Downlink Control Channel (PDCCH).
  • the control information is UCI
  • the transmitting end is set as the terminal device
  • the receiving end device is the network device
  • the terminal device sends the UCI to the network device on the physical downlink control channel (PDCCH).
  • the receiving end device determines multiple candidate formats of the control information.
  • the receiving end device determines multiple candidate formats of the control information according to the protocol, or the receiving end device determines multiple candidate formats of the control information according to the configuration information of the transmitting device.
  • the receiving end device determines multiple CRC bit generation modes according to multiple candidate formats of the control information.
  • each candidate format of the control information corresponds to a CRC bit generation manner, or several candidate formats correspond to the same CRC bit generation manner, and the correspondence between the candidate format and the CRC bit generation manner may be specified by the protocol. It can also be configured by the sending device through configuration information.
  • S1580 The receiving end device verifies the control information according to multiple CRC bit generation modes and CRC bits in the control information.
  • the receiving end device calculates a CRC bit according to each CRC bit generation manner of the multiple CRC bit generation manners, and compares the calculated multiple CRC bits with the CRC bits in the control information, If the calculated CRC bits are the same as the CRC bits in the control information, the control information is verified successfully; otherwise, the control information verification fails.
  • S1590 The receiving end device determines, according to the verification result, whether the control information is correctly transmitted.
  • control information transmission is considered correct in S1590. If the control information verification fails in S1580, the control information transmission error is considered in S1590.
  • method 1600 is a method of cyclic redundancy check, in accordance with some embodiments of the present disclosure. As shown in FIG. 16, method 1600 includes steps S1610-S1690.
  • the source device determines a Radio Network Temporary Identity (RNTI) for scrambling control information to be sent.
  • RNTI Radio Network Temporary Identity
  • the control information is DCI
  • the RNTI is one of the following RNTIs: SI-RNTI, P-RNTI, RA-RNTI, C-RNTI, TPC-PUCCH-RNTI, TPC-PUSCH-RNTI, and SPS S-RNTI.
  • the sender device determines that there is Padding Bits, and the sender device supplements the Padding Bits to the Information Bits to be sent to form a Payload.
  • the source device determines a target CRC bit generation manner according to the RNTI used to scramble the control information to be sent, and generates a CRC bit according to the target CRC bit generation manner.
  • the target CRC bit generation manner is one of a plurality of CRC bit generation manners described in method 1400.
  • the sending end device selects different target CRC bit generating manners for the control information with the same payload portion and the different RNTI scrambling.
  • DCI DCI as an example, in order to reduce the complexity of blind detection at the receiving end device, DCI scrambled with Semi-Persistent Scheduling-RNTI (SPS-RNTI) and DCI scrambled with C-RNTI
  • SPS-RNTI Semi-Persistent Scheduling-RNTI
  • C-RNTI DCI scrambled with C-RNTI
  • the payload portion can be the same size, but the content is different. Therefore, the transmitting device can select different target CRC bit generation modes for the DCI scrambled with the SPS-RNTI and with the C-RNTI.
  • the predetermined bit is included, and when the receiving device judges whether the control information is valid, it is necessary to determine whether the control information is valid according to the check result and the transmission condition of the predetermined bit.
  • S1650 The sending end device sends control information to the receiving end device.
  • the receiving end device determines multiple candidate RNTIs of the control information.
  • the receiving end device determines multiple candidate RNTIs of the control information according to the protocol, or the receiving end device determines multiple candidate RNTIs of the control information according to the configuration information of the sending end device.
  • the receiving end device determines multiple CRC bit generation modes according to multiple candidate RNTIs of the control information.
  • each candidate RNTI of the control information corresponds to one CRC bit generation manner, or several candidate RNTIs correspond to the same CRC bit generation manner, and the correspondence between the candidate RNTI and the CRC bit generation manner may be specified by the protocol. It can also be configured by the sending device through configuration information.
  • S1680 The receiving end device verifies the control information according to multiple CRC bit generation modes and CRC bits in the control information.
  • the receiving end device calculates a CRC bit according to each CRC bit generation manner of the multiple CRC bit generation manners, and compares the calculated multiple CRC bits with the CRC bits in the control information, If the calculated CRC bits are the same as the CRC bits in the control information, the control information is verified to be successful, and the CRC bit corresponding to the CRC bits in the control information corresponds to the CRC bit generation mode.
  • the RNTI is the RNTI used to scramble control information. If there is no CRC bit identical to the CRCF bit in the control information among the plurality of calculated CRC bits, the control information verification is considered to have failed.
  • S1690 The receiving end device determines, according to the verification result, whether the control information is correctly transmitted.
  • control information transmission is considered correct in S1690. If the control information verification fails in S1680, the control information transmission error is considered in S1690.
  • the transmitting device may be in accordance with a format of control information to be transmitted and a method for scrambling the control information
  • the RNTI determines a target CRC bit generation manner from a plurality of CRC bit generation modes, and generates a CRC bit according to a target CRC bit generation manner.
  • the receiving end device determines a plurality of CRC bit generation manners according to multiple candidate formats of control information and multiple RNTIs for scrambling control information, and The control information is verified according to the determined CRC bit generation manner and the CRC bits in the control information.
  • FIG. 17 illustrates a method 1700 of cyclic redundancy check, which may be performed by a sink device, in accordance with some embodiments of the present disclosure. It can be understood that the interaction between the sender device and the receiver device described on the receiving device side is the same as that on the device at the transmitting end. To avoid repetition, the related description is omitted as appropriate. As shown in FIG. 17, method 1700 includes steps S1710-S1720.
  • S1720 Verify the control information according to the multiple CRC bit generation manners and the CRC bits, where the control information includes a payload portion and a cyclic redundancy check CRC bit, and the payload portion includes at least one information. a field, the at least one information field is used to carry information bits, and the CRC bit is generated by the source device according to the target CRC bit generation manner and the payload portion, and the target CRC bit generation manner is multiple CRC bit generation manners. One of them.
  • the receiving end device generates multiple CRC bits according to multiple CRC bit generation manners, and compares the generated multiple CRC bits with the CRC bits in the control information, according to the comparison result. Determine if the control information is transmitted correctly.
  • the CRC bit in the control information received by the receiving end device is generated by the transmitting end device according to the target CRC bit generating manner in multiple CRC bit generating manners, and is received.
  • the end device verifies the control information according to the CRC bits in the various CRC bit generation modes and the control information, thereby improving the reception performance of the control information.
  • the multiple CRC bit generation manners include at least two of the following CRC code generation manners: information bits carried in all information fields in the at least one information field As an input bit for generating the CRC bit process; using an information bit carried in a partial information field in the at least one information field as an input bit of a process of generating the CRC bit; using all bits carried in the payload portion as The input bits of the CRC bit process are generated.
  • the receiving end device determines the multiple CRC bit generation manner according to multiple candidate formats of the control information; and/or according to the information used to scramble the control information.
  • the plurality of candidate wireless network temporary identifiers RNTI determine the plurality of CRC bit generation modes.
  • the information bits carried in the first information field in the at least one information field are predetermined bits, and the predetermined bits are used for transmission by the receiving end device according to the predetermined bit. Determining whether the control information is valid. If the receiving device successfully verifies the control information according to the multiple CRC bit generation manners and the CRC bits, the receiving device determines the location according to the transmission condition of the predetermined bit. Whether the control information is valid; if the predetermined bit transmission is correct, determining that the control information is valid; if the predetermined bit transmission is incorrect, determining that the control information is invalid.
  • the second information field in the at least one information field is used to indicate a format of the control information; and the receiving end device acquires all the bearer carried in the payload part according to the format of the control information. Bits, which are then verified according to the plurality of CRC bit generation modes, some or all of all bits carried by the payload portion, and the CRC bits.
  • the payload portion further includes a padding field for carrying padding bits.
  • the location of the padding field in the control information is between a location of the at least one information field and a location of the CRC bit; or the CRC bit
  • the location in the control information is between the location of the at least one information field and the location of the padding field.
  • a method of cyclic redundancy check according to some embodiments of the present disclosure is described in detail above with reference to FIG. 3, FIG. 4, FIG. 14 to FIG. 17, which will be described in detail below in conjunction with FIG. A transmitting end device of some embodiments disclosed.
  • FIG. 18 is a schematic structural diagram of a transmitting device according to some embodiments of the present disclosure. As shown in FIG. 18, the transmitting device 1800 includes a first processing module 1801 and a second processing module 1802.
  • the first processing module 1801 is configured to determine a payload portion, where the payload portion includes at least one information field, where the at least one information field is used to carry information bits, and the first processing module 1801 is further configured to determine target cyclic redundancy.
  • the CRC bit generation mode is checked, and the target CRC bit generation mode is one of a plurality of CRC bit generation modes.
  • a second processing module 1802 configured to generate a CRC bit according to the payload portion and the target CRC bit generation manner; the second processing module 1802 is further configured to generate a control including the payload portion and the CRC bit information.
  • a transmitting end device determines a target CRC bit generation manner from a plurality of CRC bit generation manners, generates a CRC bit according to the determined payload portion and a target CRC bit generation manner, and generates a payload portion and a target according to the target Control information of CRC bits produced by the CRC bit generation method.
  • the transmitting device can select different target CRC bit generation modes for different control information, satisfy the requirements of the control information for the block error rate and the false alarm, and improve the receiving performance of the control information.
  • the multiple CRC bit generation manners include at least two of the following manners: using information bits carried in all information fields in the at least one information field as a process of generating the CRC bits Input bit; an information bit carried in a partial information field in the at least one information field as an input bit of a process of generating the CRC bit; using all bits carried in the payload portion as generating the CRC bit The input bit of the process.
  • the first processing module 1801 is specifically configured to: determine, according to a format of the control information, the target CRC bit generation manner; and/or, according to the method for scrambling the control information.
  • the wireless network temporarily identifies the type of RNTI and determines the target CRC bit generation mode.
  • the information bit carried in the first information field in the at least one information field is a predetermined bit, where the predetermined bit is used by the receiving end device to determine the control according to the transmission condition of the predetermined bit. Whether the information is valid.
  • the second information field in the at least one information field is used to indicate a format of the control information.
  • the payload portion further includes a padding field, where the padding field is used to carry padding bits.
  • the location of the padding field in the control information is between a location of the at least one information field and a location of the CRC bit; or the CRC bit is in the control information
  • the location in is between the location of the at least one information field and the location of the padding field.
  • the transmitting device may refer to the flow of the method 1400-method 1600 corresponding to some embodiments of the present disclosure, and the respective units/modules in the transmitting device and the other operations and/or functions described above respectively In order to implement the corresponding processes in the method 1400-method 1600, for brevity, no further details are provided herein.
  • the receiving end device 1900 includes a transceiver module 1901 and a processing module 1902.
  • the transceiver module 1901 is configured to receive control information
  • the processing module 1902 is configured to check the control information according to the multiple CRC bit generation manners and the CRC bits, where the control information includes a payload portion and a cyclic redundancy And verifying the CRC bit
  • the payload portion includes at least one information field, where the at least one information field is used to carry information bits
  • the CRC bit is generated by the source device according to the target CRC bit generation manner and the payload portion
  • the target CRC bit generation manner is one of multiple CRC bit generation modes.
  • the CRC bit in the control information received by the receiving end device is generated by the transmitting end device according to a target CRC bit generating manner in multiple CRC bit generating manners, and the receiving end device generates according to multiple CRC bits.
  • the CRC bits in the mode and control information verify the control information, which can improve the reception performance of the control information.
  • the multiple CRC bit generation manners include at least two of the following CRC code generation manners: using information bits carried in all information fields in the at least one information field as generating the CRC An input bit of a bit process; an information bit carried in a partial information field in the at least one information field as an input bit of a process of generating the CRC bit; all bits carried in the payload portion are used as a generation CRC bit The input bit of the process.
  • the processing module 1902 is further configured to: determine, according to multiple candidate formats of the control information, the multiple CRC bit generation manners; and/or, according to the control for scrambling A plurality of candidate wireless network temporary identification RNTIs of information determine the plurality of CRC bit generation modes.
  • the information bit carried in the first information field in the at least one information field is a predetermined bit, where the predetermined bit is used by the receiving end device to determine the control according to the transmission condition of the predetermined bit. If the information is valid, the processing module 1902 is further configured to: if the control information is successfully verified according to the multiple CRC bit generation manner and the CRC bit, determine the control according to the transmission condition of the predetermined bit Whether the information is valid; if the predetermined bit transmission is correct, it is determined that the control information is valid; if the predetermined bit transmission is incorrect, it is determined that the control information is invalid.
  • the second information field in the at least one information field is used to indicate a format of the control information
  • the processing module 1902 is specifically configured to: acquire all bits carried by the payload part according to a format of the control information; and generate, according to the multiple CRC bit generation manner, part of all bits carried by the payload part The control information is verified or all bits and the CRC bits.
  • the payload portion further includes a padding field, where the padding field is used to carry padding bits.
  • the location of the padding field in the control information is between a location of the at least one information field and a location of the CRC bit; or the CRC bit is in the control information
  • the location in is between the location of the at least one information field and the location of the padding field.
  • a receiving end device may refer to a method 1500-method 1700 corresponding to some embodiments of the present disclosure, and each unit/module in the receiving end device and the other operations and/or functions described above respectively In order to implement the corresponding processes in the method 1500-method 1700, for brevity, no further details are provided herein.
  • the transmitting device 2000 includes a processor 2010, a transceiver 2020, a memory 2030, and a bus interface. among them:
  • the transmitting device 2000 further includes: a computer program stored on the memory 2030 and operable on the processor 2010, the computer program being executed by the processor 2010 when the processor 2010 Performing the steps of: determining a payload portion, the payload portion including at least one information field, the at least one information field is for carrying information bits; determining a target cyclic redundancy check CRC bit generation manner, where the target CRC bit generation manner is One of a plurality of CRC bit generation modes; generating a CRC bit according to the payload portion and the target CRC bit generation manner; and generating control information including the payload portion and the CRC bit.
  • the bus architecture may include any number of interconnected buses and bridges, specifically linked by one or more processors represented by processor 2010 and various circuits of memory represented by memory 2030.
  • the bus architecture can also link various other circuits such as peripherals, voltage regulators, and power management circuits, which are well known in the art and, therefore, will not be further described herein.
  • the bus interface provides an interface.
  • Transceiver 2020 can be a plurality of components, including a transmitter and a receiver, providing means for communicating with various other devices on a transmission medium.
  • the processor 2010 is responsible for managing the bus architecture and general processing, and the memory 2030 can store data used by the processor 2010 in performing operations.
  • the following steps may be further: determining the target CRC bit generation manner according to the format of the control information; and/or, according to the wireless used to scramble the control information
  • the network temporarily identifies the type of RNTI and determines the target CRC bit generation mode.
  • the multiple CRC bit generation manners include at least two of the following manners: using information bits carried in all information fields in the at least one information field as a process of generating the CRC bits Input bit; an information bit carried in a partial information field in the at least one information field as an input bit of a process of generating the CRC bit; all bits carried in the payload portion as a process of generating the CRC bit Input bit.
  • the information bit carried in the first information field in the at least one information field is a predetermined bit, where the predetermined bit is used by the receiving end device to determine the control according to the transmission condition of the predetermined bit. Whether the information is valid.
  • the second information field in the at least one information field is used to indicate a format of the control information.
  • the payload portion further includes a padding field, where the padding field is used to carry padding bits.
  • the location of the padding field in the control information is between a location of the at least one information field and a location of the CRC bit; or the CRC bit is in the control information
  • the location in is between the location of the at least one information field and the location of the padding field.
  • a transmitting end device determines a target CRC bit generation manner from a plurality of CRC bit generation manners, generates a CRC bit according to the determined payload portion and a target CRC bit generation manner, and generates a payload portion and a target according to the target Control information of CRC bits produced by the CRC bit generation method.
  • the transmitting device can select different target CRC bit generation modes for different control information, satisfy the requirements of the control information for the block error rate and the false alarm, and improve the receiving performance of the control information.
  • the transmitting device 2000 may refer to the transmitting device 1900 corresponding to some embodiments of the present disclosure, and the respective units/modules in the transmitting device and the other operations and/or functions described above are respectively implemented
  • the corresponding flow in the method 1400-method 1600 is not repeated here for brevity.
  • the receiving end device 2100 includes: at least one processor 2110, a memory 2120, at least one network interface 2130, and a user interface 2140. .
  • the various components in the receiving end device 2100 are coupled together by a bus system 2150.
  • the bus system 2150 is used to implement connection communication between these components.
  • the bus system 2150 includes a power bus, a control bus, and a status signal bus in addition to the data bus.
  • various buses are labeled as bus system 2150 in FIG.
  • the user interface 2140 may include a display, a keyboard, or a pointing device (eg, a mouse, a trackball, a touchpad, or a touch screen, etc.).
  • a pointing device eg, a mouse, a trackball, a touchpad, or a touch screen, etc.
  • the memory 2120 in some embodiments of the present disclosure may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memory.
  • the non-volatile memory may be a read-only memory (ROM), a programmable read only memory (PROM), an erasable programmable read only memory (Erasable PROM, EPROM), or an electric Erase programmable read only memory (EEPROM) or flash memory.
  • the volatile memory can be a Random Access Memory (RAM) that acts as an external cache.
  • RAM Random Access Memory
  • many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (Synchronous DRAM, SDRAM).
  • Double data rate synchronous dynamic random access memory Double Data Rate SDRAM, DDRSDRAM
  • enhanced synchronous dynamic random access memory ESDRAM
  • synchronously connected dynamic random access memory Synchronization RAM, SLDRAM
  • Direct memory bus random access memory DirectRambus RAM, DRRAM.
  • the memory 220 of the systems and methods described in some embodiments of the present disclosure is intended to comprise, without being limited to, these and any other suitable types of memory.
  • the memory 2120 stores elements, executable modules or data structures, or a subset thereof, or their extended set: an operating system 2121 and an application 2122.
  • the operating system 2121 includes various system programs, such as a framework layer, a core library layer, a driver layer, and the like, for implementing various basic services and processing hardware-based tasks.
  • the application 2122 includes various applications, such as a media player (Media Player), a browser (Browser), etc., for implementing various application services. Programs that implement some of the embodiment methods of the present disclosure may be included in the application 222.
  • the sink device 2100 further includes a computer program stored on the memory 2120 and executable on the processor 2110.
  • the processor 2110 implements the following steps: receiving control Information; verifying the control information according to the plurality of CRC bit generation manners and the CRC bits; wherein the control information includes a payload portion and a cyclic redundancy check CRC bit, the payload portion including at least one information a field, the at least one information field is used to carry information bits, and the CRC bit is generated by the source device according to the target CRC bit generation manner and the payload portion, and the target CRC bit generation manner is multiple CRC bit generation manners. One of them.
  • the methods disclosed in some embodiments of the present disclosure described above may be applied to or implemented by the processor 2110.
  • the processor 2110 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the foregoing method may be completed by an integrated logic circuit of hardware in the processor 210 or an instruction in a form of software.
  • the processor 210 may be a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or the like. Programmable logic devices, discrete gates or transistor logic devices, discrete hardware components.
  • the methods, steps, and logical block diagrams disclosed in some embodiments of the present disclosure may be implemented or performed.
  • the general purpose processor may be a microprocessor or the processor or any conventional processor or the like.
  • the steps of the method disclosed in connection with some embodiments of the present disclosure may be directly embodied by the hardware decoding processor, or by a combination of hardware and software modules in the decoding processor.
  • the software modules can be located in a conventional computer readable storage medium of the art, such as random access memory, flash memory, read only memory, programmable read only memory or electrically erasable programmable memory, registers, and the like.
  • the computer readable storage medium is located in the memory 2120, and the processor 2110 reads the information in the memory 2120 and performs the steps of the above method in combination with its hardware.
  • the computer readable storage medium stores a computer program, and when the computer program is executed by the processor 2110, the processor 2110 implements the steps of the method embodiment in the method 1500 to the method 1700 described above.
  • the processing unit can be implemented in one or more Application Specific Integrated Circuits (ASICs), Digital Signal Processing (DSP), Digital Signal Processing Equipment (DSP Device, DSPD), programmable Programmable Logic Device (PLD), Field-Programmable Gate Array (FPGA), general purpose processor, controller, microcontroller, microprocessor, other for performing the functions described in this disclosure In an electronic unit or a combination thereof.
  • ASICs Application Specific Integrated Circuits
  • DSP Digital Signal Processing
  • DSP Device Digital Signal Processing Equipment
  • PLD programmable Programmable Logic Device
  • FPGA Field-Programmable Gate Array
  • the techniques described in some embodiments of the present disclosure may be implemented by modules (e.g., procedures, functions, etc.) that perform the functions described in some embodiments of the present disclosure.
  • the software code can be stored in memory and executed by the processor.
  • the memory can be implemented in the processor or external to the processor.
  • the processor 2110 may further implement the following steps: determining, according to the multiple candidate formats of the control information, the multiple CRC bit generation manners; and/or, according to And determining, by the plurality of candidate wireless network temporary identifiers RNTI of the control information, the multiple CRC bit generation manners.
  • the multiple CRC bit generation manners include at least two of the following CRC code generation manners: using information bits carried in all information fields in the at least one information field as generating the CRC An input bit of a bit process; an information bit carried in a partial information field in the at least one information field as an input bit of a process of generating the CRC bit; all bits carried in the payload portion are used as a generation CRC bit The input bit of the process.
  • the information bit carried in the first information field in the at least one information field is a predetermined bit, where the predetermined bit is used by the receiving end device to determine the control according to the transmission condition of the predetermined bit.
  • the following steps may be further implemented: if the control information is successfully verified according to the multiple CRC bit generation manners and the CRC bits, according to the predetermined bits And determining, by the transmission condition, whether the control information is valid; if the predetermined bit transmission is correct, determining that the control information is valid; and if the predetermined bit transmission is incorrect, determining that the control information is invalid.
  • the second information field in the at least one information field is used to indicate the format of the control information; wherein when the computer program is executed by the processor 2110, the processor 2110 may further implement the following steps: Formatting the control information, acquiring all bits carried by the payload portion; verifying according to the multiple CRC bit generation manner, some or all bits of all bits carried by the payload portion, and the CRC bits The control information.
  • the payload portion further includes a padding field, where the padding field is used to carry padding bits.
  • the location of the padding field in the control information is between a location of the at least one information field and a location of the CRC bit; or the CRC bit is in the control information
  • the location in is between the location of the at least one information field and the location of the padding field.
  • the CRC bit in the control information received by the receiving end device is generated by the transmitting end device according to a target CRC bit generating manner in multiple CRC bit generating manners, and the receiving end device generates according to multiple CRC bits.
  • the CRC bits in the mode and control information verify the control information, which can improve the reception performance of the control information.
  • the receiving end device 2100 may refer to the receiving end device 1900 corresponding to some embodiments of the present disclosure, and the respective units/modules in the receiving end device and the other operations and/or functions described above are respectively implemented
  • the corresponding process in the method 1500-method 1700 is not described here for brevity.
  • the source device determines a target CRC bit generation manner from multiple CRC bit generation manners, generates a CRC bit according to the determined payload portion and the target CRC bit generation manner, and generates a payload portion. And control information of CRC bits produced according to the target CRC bit generation manner. Therefore, the transmitting device can select different target CRC bit generation modes for different control information, satisfy the personalized requirement of the control information for the block error rate (BLER) and the false alarm (False Alarm), and improve the control information. Receive performance.
  • BLER block error rate
  • False Alarm false alarm
  • Some embodiments of the present disclosure also provide a computer program product comprising instructions for performing a method of cyclic redundancy check of the above method embodiments when the computer executes the instructions of the computer program product.
  • the computer program product can run on the above-mentioned sender device and receiver device.
  • the disclosed systems, devices, and methods may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in various embodiments of the present disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the functions may be stored in a computer readable storage medium if implemented in the form of a software functional unit and sold or used as a standalone product. Based on such understanding, a portion of the technical solution of the present disclosure that contributes in essence or to the related art or a part of the technical solution may be embodied in the form of a software product stored in a storage medium, including several The instructions are for causing a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present disclosure.
  • the foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like, which can store program codes. .

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Abstract

本公开提供循环冗余校验的方法和设备。该方法包括：确定载荷部分，载荷部分包括至少一个信息字段，至少一个信息字段用于承载信息比特；确定用于生成循环冗余校验CRC比特的输入比特，输入比特包括至少一个信息字段中的部分或全部信息字段中承载的信息比特；根据输入比特生成目标CRC比特；生成包括载荷部分和目标CRC比特的控制信息。

Description

循环冗余校验的方法和设备
相关申请的交叉引用
本申请主张在2017年8月8日在中国提交的中国专利申请号No.201710672362.9的优先权和在2017年8月8日在中国提交的中国专利申请号No.201710672808.8的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及通信技术领域，更具体地涉及循环冗余校验的方法和设备。
背景技术
循环冗余校验(Cyclic Redundancy Check，CRC)是数据通信领域中最常用的校验方式，CRC本质上是一种数据传输检错功能，发送端设备对数据进行多项式计算，并将得到的结果附在待传输的帧的后面，接收端设备也对数据进行类似的多项式计算，以保证数据传输的正确性和完整性。
相关的对物理下行控制信道(Physical Downlink Control Channel，PDCCH)中的控制信息的CRC校验方式在信息比特的传输没有出错但填充比特传输出错时，接收端设备也会认为控制信息传输出错，导致通信系统的链路性能较差，并且相关的CRC校验方法不能够满足不同的控制信息对误块率(Block Error Rate，BLER)和虚警(False Alarm)的个性化要求，影响控制信息的接收性能。
发明内容
本公开提供循环冗余校验的方法和设备。
第一方面，本公开提供了一种循环冗余校验的方法，该方法应用于发送端设备，所述方法包括：确定载荷部分，所述载荷部分包括至少一个信息字段，所述至少一个信息字段用于承载信息比特；确定用于生成循环冗余校验CRC比特的输入比特，所述输入比特包括所述至少一个信息字段中的部分或全部信息字段中承载的信息比特；根据所述输入比特生成目标CRC比特；生 成包括所述载荷部分和所述目标CRC比特的控制信息。
第二方面，本公开提供了一种循环冗余校验的方法，该方法应用于接收端设备，所述方法包括：接收控制信息；根据所述输入比特和所述目标CRC比特，校验所述控制信息；其中，所述控制信息包括载荷部分和目标循环冗余校验CRC比特，所述载荷部分包括至少一个信息字段，所述至少一个信息字段用于承载信息比特，所述目标CRC比特是发送端设备根据用于生成CRC比特的输入比特生成的，所述输入比特包括所述至少一个信息字段中的部分或全部信息字段中承载的信息比特。
第三方面，本公开提供了一种发送端设备，该设备包括：第一处理模块，用于确定载荷部分，所述载荷部分包括至少一个信息字段，所述至少一个信息字段用于承载信息比特；所述第一处理模块，还用于确定用于生成循环冗余校验CRC比特的输入比特，所述输入比特包括所述至少一个信息字段中的部分或全部信息字段中承载的信息比特；第二处理模块，用于根据所述输入比特生成目标CRC比特；所述第二处理模块，还用于生成包括所述载荷部分和所述目标CRC比特的控制信息。
第四方面，本公开提供了一种接收端设备，该设备包括：收发模块，用于接收控制信息；处理模块，用于根据所述输入比特和所述目标CRC比特，校验所述控制信息；其中，所述控制信息包括载荷部分和目标循环冗余校验CRC比特，所述载荷部分包括至少一个信息字段，所述至少一个信息字段用于承载信息比特，所述目标CRC比特是发送端设备根据用于生成CRC比特的输入比特生成的，所述输入比特包括所述至少一个信息字段中的部分或全部信息字段中承载的信息比特。
第五方面，本公开提供了一种发送端设备，该设备包括：存储器、处理器及存储在所述存储器上并可在所述处理器上运行的循环冗余校验程序，所述循环冗余校验程序被所述处理器执行时所述处理器实现如第一方面所述的循环冗余校验的方法的步骤。
第六方面，本公开提供了一种接收端设备，该设备包括：存储器、处理器及存储在所述存储器上并可在所述处理器上运行的循环冗余校验程序，所述循环冗余校验程序被所述处理器执行时所述处理器实现如第二方面所述的 循环冗余校验的方法的步骤。
第七方面，本公开提供了一种计算机可读存储介质，所述计算机可读存储介质上存储有循环冗余校验程序，所述循环冗余校验程序被处理器执行时所述处理器实现如第一方面所述的循环冗余校验的方法的步骤。
第八方面，本公开提供了一种计算机可读存储介质，所述计算机可读存储介质上存储有循环冗余校验程序，所述循环冗余校验程序被处理器执行时所述处理器实现如第二方面所述的循环冗余校验的方法的步骤。
第九方面，本公开提供了一种包括指令的计算机程序产品，当计算机运行所述计算机程序产品的所述指令时，所述计算机执行上述第一方面的循环冗余校验的方法。具体地，该计算机程序产品可以运行于上述第三方面的发送端设备上。
第十方面，本公开提供了一种包括指令的计算机程序产品，当计算机运行所述计算机程序产品的所述指令时，所述计算机执行上述第二方面的循环冗余校验的方法。具体地，该计算机程序产品可以运行于上述第四方面的接收端设备上。
第十一方面，本公开提供了一种循环冗余校验的方法，该方法应用于发送端设备，所述方法包括：确定载荷部分，所述载荷部分包括至少一个信息字段，所述至少一个信息字段用于承载信息比特；确定目标循环冗余校验CRC比特生成方式，所述目标CRC比特生成方式为多种CRC比特生成方式中的一种；根据所述载荷部分和所述目标CRC比特生成方式，生成CRC比特；生成包括所述载荷部分和所述CRC比特的控制信息。
第十二方面，本公开提供了一种循环冗余校验的方法，该方法应用于接收端设备，所述方法包括：接收控制信息；根据所述多种CRC比特生成方式和所述CRC比特，校验所述控制信息；其中，所述控制信息包括载荷部分和循环冗余校验CRC比特，所述载荷部分包括至少一个信息字段，所述至少一个信息字段用于承载信息比特，所述CRC比特是发送端设备根据目标CRC比特生成方式和所述载荷部分生成的，所述目标CRC比特生成方式为多种CRC比特生成方式中的一种。
第十三方面，本公开提供了一种发送端设备，该设备包括：第一处理模 块，用于确定载荷部分，所述载荷部分包括至少一个信息字段，所述至少一个信息字段用于承载信息比特；所述第一处理模块，还用于确定目标循环冗余校验CRC比特生成方式，所述目标CRC比特生成方式为多种CRC比特生成方式中的一种；第二处理模块，用于根据所述载荷部分和所述目标CRC比特生成方式，生成CRC比特；所述第二处理模块，还用于生成包括所述载荷部分和所述CRC比特的控制信息。
第十四方面，本公开提供了一种接收端设备，该设备包括：收发模块，用于接收控制信息；处理模块，用于根据所述多种CRC比特生成方式和所述CRC比特，校验所述控制信息；其中，所述控制信息包括载荷部分和循环冗余校验CRC比特，所述载荷部分包括至少一个信息字段，所述至少一个信息字段用于承载信息比特，所述CRC比特是发送端设备根据目标CRC比特生成方式和所述载荷部分生成的，所述目标CRC比特生成方式为多种CRC比特生成方式中的一种。
第十五方面，本公开提供了一种发送端设备，该设备包括：存储器、处理器及存储在所述存储器上并可在所述处理器上运行的循环冗余校验程序，所述循环冗余校验程序被所述处理器执行时所述处理器实现如第十一方面所述的循环冗余校验的方法的步骤。
第十六方面，本公开提供了一种接收端设备，该设备包括：存储器、处理器及存储在所述存储器上并可在所述处理器上运行的循环冗余校验程序，所述循环冗余校验程序被所述处理器执行时所述处理器实现如第十二方面所述的循环冗余校验的方法的步骤。
第十七方面，本公开提供了一种计算机可读存储介质，所述计算机可读存储介质上存储有循环冗余校验程序，所述循环冗余校验程序被处理器执行时所述处理器实现如第十一方面所述的循环冗余校验的方法的步骤。
第十八方面，本公开提供了一种计算机可读存储介质，所述计算机可读存储介质上存储有循环冗余校验程序，所述循环冗余校验程序被处理器执行时所述处理器实现如第十二方面所述的循环冗余校验的方法的步骤。
第十九方面，本公开提供了一种包括指令的计算机程序产品，当计算机运行所述计算机程序产品的所述指令时，所述计算机执行上述第十一方面的 循环冗余校验的方法。具体地，该计算机程序产品可以运行于上述第十三方面的发送端设备上。
第二十方面，本公开提供了一种包括指令的计算机程序产品，当计算机运行所述计算机程序产品的所述指令时，所述计算机执行上述第十二方面的循环冗余校验的方法。具体地，该计算机程序产品可以运行于上述第十四方面的接收端设备上。
附图说明
为了更清楚地说明本公开的一些实施例或相关技术中的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作简单地介绍。显而易见地，下面描述中的附图仅仅是本公开中记载的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1是根据本公开的一些实施例的循环冗余校验的方法的示意性流程图一；
图2是根据本公开的一些实施例的循环冗余校验的方法的示意性流程图二；
图3是根据本公开的一些实施例的信息字段、填充字段和CRC比特在控制信息中的位置的示意图一；
图4是根据本公开的一些实施例的信息字段、填充字段和CRC比特在控制信息中的位置的示意图二；
图5是根据本公开的一些实施例的循环冗余校验的方法的示意性流程图三；
图6是根据本公开的一些实施例的信息字段、填充字段和CRC比特在控制信息中的位置的示意图三；
图7是根据本公开的一些实施例的循环冗余校验的方法的示意性流程图四；
图8是根据本公开的一些实施例的循环冗余校验方法与相关技术中的循环冗余校验方法的链路性能的对比图一；
图9是根据本公开的一些实施例的循环冗余校验方法与相关技术中的循环冗余校验方法的链路性能的对比图二；
图10是根据本公开的一些实施例的发送端设备的结构示意图一；
图11是根据本公开的一些实施例的接收端设备的结构示意图二；
图12是根据本公开的一些实施例的发送端设备的结构示意图二；
图13是根据本公开的一些实施例的接收端设备的结构示意图二。
图14是根据本公开的一些实施例的循环冗余校验的方法的示意性流程图五；
图15是根据本公开的一些实施例的循环冗余校验的方法的示意性流程图六；
图16是根据本公开的一些具体实施例的循环冗余校验的方法的示意性流程图七；
图17是根据本公开的一些实施例的循环冗余校验的方法的示意性流程图八；
图18是根据本公开的一些实施例的发送端设备的结构示意图三；
图19是根据本公开的一些实施例的接收端设备的结构示意图三；
图20是根据本公开的一些实施例的发送端设备的结构示意图四；以及
图21是根据本公开的一些实施例的接收端设备的结构示意图四。
具体实施方式
为了使本技术领域的人员更好地理解本公开中的技术方案，下面将结合本公开的一些实施例中的附图，对本公开的一些实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都应当属于本公开保护的范围。
应理解，本公开的一些实施例的技术方案可以应用于各种通信系统，例如：全球移动通信(Global System of Mobile communication，GSM)系统、码分多址(Code Division Multiple Access，CDMA)系统、宽带码分多址(Wideband Code Division Multiple Access，WCDMA)系统、通用分组无线 业务(General Packet Radio Service，GPRS)、长期演进(Long Term Evolution，LTE)系统、LTE频分双工(Frequency Division Duplex，FDD)系统、LTE时分双工(Time Division Duplex，TDD)、通用移动通信系统(Universal Mobile Telecommunication System，UMTS)或全球互联微波接入(Worldwide Interoperability for Microwave Access，WiMAX)通信系统、5G系统，或者说新无线(New Radio,NR)系统。
在本公开的一些实施例中，发送端设备可以为网络设备，相对应地，接收端设备为终端设备。或者发送端设备可以为终端设备，相对应地，接收端设备为网络设备。
在本公开的一些实施例中，终端设备可以包括但不限于移动台(Mobile Station，MS)、移动终端(Mobile Terminal)、移动电话(Mobile Telephone)、用户设备(User Equipment，UE)、手机(handset)及便携设备(portable equipment)、车辆(vehicle)等，该终端设备可以经无线接入网(Radio Access Network，RAN)与一个或多个核心网进行通信，例如，终端设备可以是移动电话(或称为“蜂窝”电话)、具有无线通信功能的计算机等，终端设备还可以是便携式、袖珍式、手持式、计算机内置的或者车载的移动装置。
在本公开的一些实施例中，网络设备是一种部署在无线接入网中用以为终端设备提供无线通信功能的装置。所述网络设备可以为基站，所述基站可以包括各种形式的宏基站，微基站，中继站，接入点等。在采用不同的无线接入技术的系统中，具有基站功能的设备的名称可能会有所不同。例如在LTE网络中，称为演进的节点B(Evolved NodeB，eNB或eNodeB)，在第三代(3rd Generation，3G)网络中，称为节点B(Node B)等等。
本公开的一些实施例提供的循环冗余校验的方法和设备可以解决通信系统的链路性能差的问题。
在描述具体实施例之前，先介绍一下循环冗余校验(Cycle Redundancy Check，CRC)的基本原理。CRC校验在K位信息码后拼接R位的CRC码，整个编码长度为N，这种编码也叫(N，K)码。对于一个给定的(N，K)码，可以证明存在一个最高次幂为N-K＝R的多项式G(x)。根据G(x)可以生产K位信息码的校验码，而G(x)叫做CRC码的生成多项式。CRC码 的具体生成过程为：假设要发送的信息用多项式C(x)表示，将C(x)左移R位(可表示成C(x)*2 R)，这样C(x)的右边就会空出R位，这就时CRC码的位置，用C(x)*2 R除以生成多项式G(x)得到的余数就是CRC码。
图1示出了根据本公开的一些实施例的循环冗余校验的方法100，该方法100可以由发送端设备执行。如图1所示，方法100包括步骤S110-S140。
S110，确定载荷部分，载荷部分包括至少一个信息字段，至少一个信息字段用于承载信息比特。
可选地，在新无线(New Radio，NR)系统中会有多种格式的控制信息，不同格式的控制信息的大小(Size)会有差别，如果要求接收端设备盲检测这些控制信息的格式的话，会导致接收端设备具有较高的复杂度，因此，在本公开的一些实施例中，通过在某些较短的控制信息的尾部填加填充比特(Padding Bits)的方法对齐不同格式的控制信息，以降低接收端设备的复杂度，其中，Padding Bits通常为“0”或者“nil”或者“1”，nil等于null,为“空”或“无效”之义。
具体地，在一些实施例中，发送端设备根据要生成的控制信息的格式，确定是否有Padding Bits，如果确定有Padding Bits，载荷部分还包括填充字段，填充字段用于承载Padding Bits。
S120，确定用于生成循环冗余校验CRC比特的输入比特，输入比特包括至少一个信息字段中的部分或全部信息字段中承载的信息比特。
需要说明的是，如果在S110中，载荷部分只包括一个信息字段，则在S120中，输入比特包括至少一个信息字段中的部分或全部信息字段中承载的信息比特应该理解为：输入比特包括这一个信息字段中承载的信息比特。
还需要说明的是，在本公开的一些实施例中，循环冗余校验(Cyclic Redundancy Check，CRC)比特也可以被称为“CRC码”。
S130，根据输入比特生成目标CRC比特。
具体地，在一些实施例中，发送端设备可以根据上文中描述的CRC码的生成方式生成目标CRC比特。
S140，生成包括载荷部分和目标CRC比特的控制信息。
CRC比特生成除了根据信息比特生成校验比特，也包括对于校验比特进行必要的加扰。如在LTE的实现中，RNTI是一个16bits的序列，用16-bit RNTI和16-bit CRC的每一个比特进行加扰(即异或运算)。然后在接收端，不同状态用不同的RNTI去解扰CRC，获取PDCCH上的内容，并最终识别PDSCH上属于自己的信息。
根据本公开的一些实施例的循环冗余校验的方法，发送端设备根据至少一个信息字段中的部分或全部信息字段中承载的信息比特生成目标CRC比特，使得接收端设备在对控制信息进行校验时，只对至少一个信息字段中的部分或全部信息字段中承载的信息比特进行校验，避免在控制信息中的信息比特传输没有出错而填充比特传输出错时，接收端设备认为控制信息传输出错的情况，或者避免在部分信息比特传错而重要信息比特没有错误，传错的部分信息比特接收端设备可以容忍时，接收端设备认为控制信息传输出错的情况，提高通信系统的链路性能。
下面将结合具体的例子描述根据本公开的一些实施例的循环冗余校验的方法。图2是根据本公开的一些实施例的循环冗余校验的方法，如图2所示，方法200包括步骤S210-S270。
S210，发送端设备确定有填充比特(Padding Bits)，发送端设备对要发送的信息比特(Information Bits)补充填充比特构成载荷部分(Payload)。
可选地，在S210中，要发送的信息Information Bits被承载在至少一个信息字段中，Padding Bits被承载在填充字段中。
S220，发送端设备根据全部Information Bits计算CRC比特。
具体地，在一些实施例中，发送端设备根据协议的规定确定需要将全部Information Bits作为计算CRC比特的输入比特(Input Bits)。或者发送端设备根据与接收端设备的约定确定需要将全部Information Bits作为计算CRC比特的输入比特。或者发送端设备自行决定将全部Information Bits作为计算CRC比特的输入比特，在这种情况下，发送端设备需要向接收端设备发送配置信息，通过配置信息告知接收端设备在计算CRC比特时需要将全部Information Bits作为输入比特。发送端设备可以将配置信息承载在高层信令中发送给接收端设备。
S230，发送端设备将CRC比特附着到载荷部分构成控制信息。
可选地，作为一个例子，CRC比特和载荷部分在控制信息中的位置如图3或图4所示。在图3中，填充字段的位置在至少一个信息字段的位置和CRC比特的位置之间。在图4中，CRC比特的位置在至少一个信息字段的位置和填充比特的位置之间。在本公开的一些实施例中，CRC比特和载荷部分在控制信息中的位置可以是协议规定的，也可以是发送端设备和接收端设备事先约定的，还可以是发送端设备通过配置信息告知接收端设备的。
可选地，作为一个例子，至少一个信息字段中的第一信息字段用于指示控制信息的格式，接收端设备根据第一信息字段指示的控制信息的格式对控制信息进行解析，即可以获取到至少一个信息字段中的全部信息字段中承载的Information Bits。
举例来说，用于指示控制信息的格式的第一信息字段取不同的值指示不同的格式。例如，假设通信系统中的控制信息的格式有4种，依次为格式AA、格式BB、格式CC和格式DD，用于指示控制信息的格式的第一信息字段包括2个比特，则可以用“00”指示控制信息的格式为“格式AA”，“01”指示控制信息的格式为“格式BB”、用“10”指示控制信息的格式为“格式CC”、用“11”指示控制信息的格式为“格式DD”。
进一步地，控制信息的格式用于接收端设备确定至少一个信息字段的总长度。具体地，Payload的长度和CRC比特的长度可以通过预配置或者事先约定得知，为了便于接收端设备获知至少一个信息字段的总长度，可以通过协议规定或者发送端设备配置控制信息的格式与控制信息中包括的至少一个信息字段的总长度具有对应关系，接收端设备可以根据接收到的控制信息的格式和上述对应关系，确定接收到的控制信息中包括至少一个信息字段的总长度，进而获取到至少一个信息字段中的全部信息字段中承载的Information Bits。
S240，发送端设备向接收端设备发送控制信息。
可选地，发送端设备可以采用无线网络临时标识(Radio Network Temporary Identity，RNTI)对控制信息进行加扰，向接收端设备发送加扰后的控制信息。
S250，接收端设备确定至少一个信息字段的总长度和至少一个信息字段在控制信息中的位置。
具体地，在S250中，接收端设备根据至少一个信息字段的总长度和至少一个信息字段在控制信息中的位置，即可以获取到至少一个信息字段中的全部信息字段中承载的信息比特。
可选地，在一些实施例中，接收端设备根据至少一个信息字段中用于指示控制信息的格式的字段确定接收到的控制信息的格式，之后根据控制信息的格式与控制信息中包括的至少一个信息字段的总长度之间的对应关系以及接收到的控制信息的格式，确定接收到的控制信息中包括的至少一个信息字段的总长度。
可选地，在另一些实施例中，接收端设备可以根据协议规定确定至少一个信息字段在控制信息中的位置，接收端设备可以根据与发送端设备之间的约定确定至少一个信息字段在控制信息中的位置，接收端设备还可以根据发送端设备发送的配置信息，确定至少一个信息字段在控制信息中的位置。
S260，接收端设备根据至少一个信息字段中的全部信息字段中承载的信息比特和CRC比特进行校验。
需要说明的是，在这里接收端设备根据至少一个信息字段中的全部信息字段中承载的信息比特和CRC比特进行校验可以理解为：接收端设备根据至少一个信息字段中的全部信息字段中承载的信息比特和CRC比特对控制信息进行校验，或者可以理解为：接收端设备根据至少一个信息字段中的全部信息字段中承载的信息比特和CRC比特对控制信息中的全部信息比特进行校验。
可选地，在S260中，接收端设备根据至少一个信息字段中的全部信息字段中承载的信息比特计算CRC比特，将计算得到的CRC比特和控制信息中的CRC比特进行比对。
S270，根据校验的结果，判断控制信息是否传输正确。
可选地，如果在S260中，接收端设备计算得到的CRC比特和控制信息中的CRC比特一致，则在S270中，认为控制信息传输正确，否则认为控制信息传输错误。
图5是根据本公开的一些实施例的循环冗余校验的方法的示意性流程图。如图5所示，方法300包括步骤S310-S370。
S310，发送端设备确定有Padding Bits，发送端设备对要发送的Information Bits补充Padding Bits构成Payload。
可选地，在S310中，要发送的信息Information Bits被承载在至少一个信息字段中，Padding Bits被承载在填充字段中。
S320，发送端设备根据Information Bits中的部分Information Bits计算CRC比特。
也就是说，在S320中，发送端设备根据至少一个信息字段中的部分信息字段中承载的Information Bits计算CRC比特。
具体地，在一些实施例中，发送端设备根据协议的规定确定需要将部分Information Bits作为计算CRC比特的输入比特(Input Bits)。或者发送端设备根据与接收端设备的约定确定需要将部分Information Bits作为计算CRC比特的输入比特。或者发送端设备自行决定将部分Information Bits作为计算CRC比特的输入比特，在这种情况下，发送端设备需要向接收端设备发送配置信息，通过配置信息告知接收端设备在计算CRC比特时需要将部分Information Bits作为输入比特。发送端设备可以将配置信息承载在高层信令中发送给接收端设备。
可选地，作为一个例子，发送端设备和接收端设备可以事先约定根据控制信息中的哪些信息字段中承载的信息比特生成CRC比特。以上行控制信息(Uplink Control Information，UCI)为例，假设UCI中包括承载确认(Acknowledgement，ACK)/否定确认(Non-Acknowledgement，NACK)信息的字段、承载上行调度请求(Scheduling Request，SR)的字段和承载信道状态指示信息(Channel State Information，CSI)的字段，发送端设备和接收端设备可以实现约定根据承载ACK/NACK的字段和承载SR的字段中承载的信息比特生成CRC比特。
可选地，作为另一个例子，发送端设备可以通过配置信息告知接收端设备需要根据哪些字段中承载的信息比特生成CRC比特，也就是说，当配置信息指示输入比特包括部分信息字段中承载的信息比特时，配置信息还用于指 示部分信息字段。以上文中的UCI为例，发送端设备可以通过配置信息指示需要根据承载ACK/NACK的字段和承载SR的字段中承载的信息比特生成CRC比特。
S330，发送端设备将CRC码附着到载荷部分构成控制信息。
可选地，作为一个例子，CRC比特和载荷部分在控制信息中的位置如图3所示。或者CRC比特和载荷部分在控制信息中的位置如图6所示。在如6中，CRC比特的位置在用于生成CRC比特的部分信息字段的位置之后且在其他信息字段的位置之前，填充字段位于控制信息的尾部。
S340，发送端设备向接收端设备发送控制信息。
可选地，发送端设备可以采用RNTI对控制信息进行加扰，向接收端设备发送加扰后的控制信息。
S350，接收端设备确定至少一个信息字段的总长度和至少一个信息字段在控制信息中的位置。
具体地，在S350中，接收端设备根据至少一个信息字段的总长度和至少一个信息字段在控制信息中的位置即可以获取到至少一个信息字段中的全部信息字段中承载的信息比特，进而将部分信息字段中承载的信息比特作为用于生成CRC比特的输入比特。
S360，接收端设备根据至少一个信息字段中的部分信息字段中承载的信息比特和CRC比特进行校验。
需要说明的是，在这里接收端设备根据至少一个信息字段中的部分信息字段中承载的信息比特和CRC比特进行校验可以理解为：接收端设备根据至少一个信息字段中的部分信息字段中承载的信息比特和CRC比特对控制信息进行校验，或者可以理解为：接收端设备根据至少一个信息字段中的部分信息字段中承载的信息比特和CRC比特对控制信息中的部分信息比特进行校验。
可选地，在S360中，接收端设备可以根据与发送端设备的约定或协议的规定确定上述的部分信息字段，接收端设备还可以根据发送端设备的配置信息确定上述的部分信息字段。
S370，根据校验的结果，判断控制信息是否传输正确。
在上述所有实施例中，可选地，至少一个信息字段中的第二信息字段中承载的信息比特为预定比特(或者说固定比特)，接收端设备可以根据预定比特的传输情况判断控制信息是否有效，从而判断控制信息的传输是否是虚警，能够满足控制信息对虚警的要求。在这种情况下，如果接收端设备校验控制信息成功，接收端设备进一步判断预定比特的传输情况，如果确定预定比特传输正确，则确定控制信息有效，控制信息的传输不是虚警；如果确定预定比特传输错误，则确定控制信息无效，控制信息的传输是虚警。
图7示出了根据本公开的一些实施例的循环冗余校验的方法400，该方法400可以由接收端设备执行。可以理解的是，从接收端设备侧描述的发送端设备与接收端设备的交互与发送端设备侧的描述相同，为避免重复，适当省略相关描述。如图7所示，方法400包括步骤S410-S420。
S410，接收控制信息；
S420，根据所述输入比特和所述目标CRC比特，校验所述控制信息；
其中，所述控制信息包括载荷部分和目标循环冗余校验CRC比特，所述载荷部分包括至少一个信息字段，所述至少一个信息字段用于承载信息比特，所述目标CRC比特是发送端设备根据用于生成CRC比特的输入比特生成的，所述输入比特包括所述至少一个信息字段中的部分或全部信息字段中承载的信息比特。
根据本公开的一些实施例的循环冗余校验的方法，接收端设备接收到的控制信中的CRC比特是发送端设备根据至少一个信息字段中的部分或全部信息字段中承载的信息比特生成的，接收端设备在对控制信息进行校验时，只对至少一个信息字段中的部分或全部信息字段中承载的信息比特进行校验，避免在控制信息中的信息比特传输没有出错而填充比特传输出错时，或者避免在部分信息比特传错而重要信息比特没有错误，传错的部分信息比特接收端设备可以容忍时，接收端设备认为控制信息传输出错的情况，接收端设备认为控制信息传输出错的情况，提高通信系统的链路性能。
在本公开的一些实施例中，可选地，所述载荷部分还包括填充字段，所述填充字段用于承载填充比特；其中，所述输入比特包括所述至少一个信息字段中的全部信息字段中承载的信息比特，所述填充字段在所述控制信息中 的位置在所述至少一个信息字段的位置和所述目标CRC比特的位置之间，或，所述目标CRC比特在所述控制信息中的位置在所述至少一个信息字段的位置和所述填充字段的位置之间。
在本公开的一些实施例中，可选地，所述载荷部分还包括填充字段，所述填充字段用于承载填充比特；其中，所述输入比特包括所述至少一个信息字段中的部分信息字段中承载的信息比特，所述填充字段的在所述控制信息中的位置在所述至少一个信息字段的位置和所述目标CRC比特的位置之间，或，所述目标CRC比特在所述控制信息中的位置在所述部分信息字段的位置和所述至少一个信息字段中的其他信息字段以及所述填充字段的位置之间。
在本公开的一些实施例中，可选地，所述至少一个信息字段中的第一信息字段用于指示所述控制信息的格式；其中，在根据所述输入比特和所述目标CRC比特，校验所述控制信息之前，接收端设备根据所述控制信息的格式，获取所述输入比特。
可选地，在一些实施例中，接收端设备通过根据控制信息的格式对控制信息进行解析，获取输入比特。
在本公开的一些实施例中，可选地，所述控制信息的格式用于接收端设备确定所述至少一个信息字段的总长度。接收端设备根据控制信息的格式，确定至少一个信息字段的总长度，根据至少一个信息字段的总长度获取输入比特。
在本公开的一些实施例中，可选地，所述至少一个信息字段中的第二信息字段中承载的信息比特为预定比特，所述预定比特用于接收端设备根据所述预定比特的传输情况判断所述控制信息是否有效，若所述接收端设备校验所述控制信息成功，则所述接收端设备根据所述预定比特的传输情况判断所述控制信息是否有效；若所述预定比特传输正确，则确定所述控制信息有效；若所述预定比特传输错误，则确定所述控制信息无效。
在本公开的一些实施例中，可选地，接收端设备在根据所述输入比特和所述目标CRC比特，校验所述控制信息之前，接收发送端设备发送的配置信息，所述配置信息用于指示所述输入比特包括所述至少一个信息字段中的部分或全部信息字段中承载的信息比特。接收端设备根据配置信息获取输入比 特。
在本公开的一些实施例中，可选地，当所述配置信息用于指示所述输入比特包括所述至少一个信息字段中的部分信息字段中承载的信息比特时，所述配置信息还用于指示所述部分信息字段。接收端设备根据配置信息确定具体是根据至少一个信息字段中的哪些信息字段中承载的信息比特生成CRC比特。
图8和图9示出了根据本公开的一些实施例的循环冗余校验的方法与相关技术中的循环冗余校验的方法对应的链路性能。表1是进行性能仿真时采用的参数。
表1
Figure PCTCN2018099382-appb-000001
Figure PCTCN2018099382-appb-000002
在图8中Information Bits的个数为40，Padding Bits的个数为20，图8中带圆圈的实线为根据本公开的一些实施例的方法得到的误块率与信噪比的关系曲线，带圆圈的虚线为根据相关技术中的方法得到的误块率与信噪比的关系曲线。在图9中Information Bits的个数为50，Padding Bits的个数为10，图9中带圆圈的实线为根据本公开的一些实施例的方法得到的误块率与信噪比的关系曲线，虚线为根据相关技术中的方法得到的误块率与信噪比的关系曲线。可以看出，采用本公开的一些实施例的循环冗余校验方法的链路性能优于采用相关技术中的循环校验的方法的链路增益，具体地，在要求误块率为1％的条件下，本公开的一些实施例的方法相对于相关技术的方法有约0.25dB的链路增益。
以上结合图1至图9详细描述了根据本公开的一些实施例的循环冗余校验的方法，下面将结合图10详细描述根据本公开的一些实施例的发送端设备。
图10是根据本公开的一些实施例的发送端设备的结构示意图。如图10所示，发送端设备10包括第一处理模块11和第二处理模块12。
第一处理模块11，用于确定载荷部分，所述载荷部分包括至少一个信息字段，所述至少一个信息字段用于承载信息比特；所述第一处理模块11，还用于确定用于生成循环冗余校验CRC比特的输入比特，所述输入比特包括所述至少一个信息字段中的部分或全部信息字段中承载的信息比特。
第二处理模块12，用于根据所述输入比特生成目标CRC比特；所述第二处理模块12，还用于生成包括所述载荷部分和所述目标CRC比特的控制信息。
根据本公开的一些实施例的发送端设备根据至少一个信息字段中的部分或全部信息字段中承载的信息比特生成目标CRC比特，使得接收端设备在对控制信息进行校验时，只对至少一个信息字段中的部分或全部信息字段中承载的信息比特进行校验，避免在控制信息中的信息比特传输没有出错而填充比特传输出错时，接收端设备认为控制信息传输出错的情况，或者避免在部分信息比特传错而重要信息比特没有错误，传错的部分信息比特接收端设备可以容忍时，接收端设备认为控制信息传输出错的情况，提高通信系统的链路性能。
可选地，作为一个例子，所述载荷部分还包括填充字段，所述填充字段用于承载填充比特；其中，所述输入比特包括所述至少一个信息字段中的全部信息字段中承载的信息比特，所述填充字段在所述控制信息中的位置在所述至少一个信息字段的位置和所述目标CRC比特的位置之间，或，所述目标CRC比特在所述控制信息中的位置在所述至少一个信息字段的位置和所述填充字段的位置之间。
可选地，作为一个例子，所述载荷部分还包括填充字段，所述填充字段用于承载填充比特；其中，所述输入比特包括所述至少一个信息字段中的部分信息字段中承载的信息比特，所述填充字段的在所述控制信息中的位置在所述至少一个信息字段的位置和所述目标CRC比特的位置之间，或，所述目标CRC比特在所述控制信息中的位置在所述部分信息字段的位置和所述至少一个信息字段中的其他信息字段以及所述填充字段的位置之间。
可选地，作为一个例子，所述至少一个信息字段中的第一信息字段用于指示所述控制信息的格式。
可选地，作为一个例子，所述控制信息的格式用于接收端设备确定所述至少一个信息字段的总长度。
可选地，作为一个例子，所述至少一个信息字段中的第二信息字段中承载的信息比特为预定比特，所述预定比特用于接收端设备根据所述预定比特的传输情况判断所述控制信息是否有效。
可选地，作为一个例子，所述第一处理模块11还用于：向接收端设备发送配置信息，所述配置信息用于指示所述输入比特包括所述至少一个信息字 段中的部分或全部信息字段中承载的信息比特。
可选地，作为一个例子，当所述配置信息指示所述输入比特包括所述至少一个信息字段中的部分信息字段中承载的信息比特时，所述配置信息还用于指示所述部分信息字段。
根据本公开的一些实施例的发送端设备可以参照对应本公开的一些实施例的方法100至方法300的流程，并且，该发送端设备中的各个单元/模块和上述其他操作和/或功能分别为了实现方法100至方法300中的相应流程，为了简洁，在此不再赘述。
图11是根据本公开的一些实施例的接收端设备的结构示意图。如图11所示，接收端设备20包括收发模块21和处理模块22。
收发模块21，用于接收控制信息；处理模块22，用于根据所述输入比特和所述目标CRC比特，校验所述控制信息。
其中，所述控制信息包括载荷部分和目标循环冗余校验CRC比特，所述载荷部分包括至少一个信息字段，所述至少一个信息字段用于承载信息比特，所述目标CRC比特是发送端设备根据用于生成CRC比特的输入比特生成的，所述输入比特包括所述至少一个信息字段中的部分或全部信息字段中承载的信息比特。
根据本公开的一些实施例的接收端设备接收到的控制信中的CRC比特是发送端设备根据至少一个信息字段中的部分或全部信息字段中承载的信息比特生成的，接收端设备在对控制信息进行校验时，只对至少一个信息字段中的部分或全部信息字段中承载的信息比特进行校验，避免在控制信息中的信息比特传输没有出错而填充比特传输出错时，接收端设备认为控制信息传输出错的情况，或者避免在部分信息比特传错而重要信息比特没有错误，传错的部分信息比特接收端设备可以容忍时，接收端设备认为控制信息传输出错的情况，提高通信系统的链路性能。
可选地，作为一个例子，所述载荷部分还包括填充字段，所述填充字段用于承载填充比特；其中，所述输入比特包括所述至少一个信息字段中的全部信息字段中承载的信息比特，所述填充字段在所述控制信息中的位置在所述至少一个信息字段的位置和所述CRC比特的位置之间，或，所述CRC比 特在所述控制信息中的位置在所述至少一个信息字段的位置和所述填充字段的位置之间。
可选地，作为一个例子，所述载荷部分还包括填充字段，所述填充字段用于承载填充比特；其中，所述输入比特包括所述至少一个信息字段中的部分信息字段中承载的信息比特，所述填充字段的在所述控制信息中的位置在所述至少一个信息字段的位置和所述CRC比特的位置之间，或，所述CRC比特在所述控制信息中的位置在所述部分信息字段的位置和所述至少一个信息字段中的其他信息字段以及所述填充字段的位置之间。
可选地，作为一个例子，所述至少一个信息字段中的第一信息字段用于指示所述控制信息的格式；其中，所述处理模块22还用于：根据所述控制信息的格式，获取所述输入比特。
可选地，作为一个例子，所述控制信息的格式用于接收端设备确定所述至少一个信息字段的总长度；其中，所述处理模块22具体用于：根据所述控制信息的格式，确定所述至少一个信息字段的总长度；根据所述至少一个信息字段的总长度，获取所述输入比特。
可选地，作为一个例子，所述至少一个信息字段中的第二信息字段中承载的信息比特为预定比特，所述预定比特用于接收端设备根据所述预定比特的传输情况判断所述控制信息是否有效，所述处理模块22还用于：若校验所述控制信息成功，则根据所述预定比特的传输情况，判断所述控制信息是否有效；若所述预定比特传输正确，则确定所述控制信息有效；若所述预定比特传输错误，则确定所述控制信息无效。
可选地，作为一个例子，所述收发模块21还用于：接收发送端设备发送的配置信息，所述配置信息用于指示所述输入比特包括所述至少一个信息字段中的部分或全部信息字段中承载的信息比特；其中，所述处理模块22还用于：根据所述配置信息获取所述输入比特。
可选地，作为一个例子，当所述配置信息用于指示所述输入比特包括所述至少一个信息字段中的部分信息字段中承载的信息比特时，所述配置信息还用于指示所述部分信息字段。
根据本公开的一些实施例的接收端设备可以参照对应本公开的一些实施 例的方法200至方法400的流程，并且，该接收端设备中的各个单元/模块和上述其他操作和/或功能分别为了实现方法200至方法400中的相应流程，为了简洁，在此不再赘述。
图12示出了根据本公开的一些实施例的发送端设备的结构示意图，能够实现方法100至方法300中的循环冗余校验的方法的细节，并能达到相同的效果。如图12所示，发送端设备100包括处理器110、收发机120、存储器130和总线接口。其中：在本公开的一些实施例中，发送端设备100还包括：存储在存储器130上可在所述处理器110上运行的计算机程序，所述计算机程序被所述处理器110执行时执行以下步骤：确定载荷部分，所述载荷部分包括至少一个信息字段，所述至少一个信息字段用于承载信息比特；确定用于生成循环冗余校验CRC比特的输入比特，所述输入比特包括所述至少一个信息字段中的部分或全部信息字段中承载的信息比特；根据所述输入比特生成目标CRC比特；生成包括所述载荷部分和所述目标CRC比特的控制信息。
在图12中，总线架构可以包括任意数量的互联的总线和桥，具体由处理器110代表的一个或多个处理器和存储器130代表的存储器的各种电路链接在一起。总线架构还可以将诸如外围设备、稳压器和功率管理电路等之类的各种其他电路链接在一起，这些都是本领域所公知的，因此，本文不再对其进行进一步描述。总线接口提供接口。收发机120可以是多个元件，即包括发送机和接收机，提供用于在传输介质上与各种其他装置通信的单元。
处理器110负责管理总线架构和通常的处理，存储器130可以存储处理器110在执行操作时所使用的数据。
可选的，计算机程序被处理器110执行时还可实现如下步骤：向接收端设备发送配置信息，所述配置信息用于指示所述输入比特包括所述至少一个信息字段中的部分或全部信息字段中承载的信息比特。
可选地，作为一个例子，所述载荷部分还包括填充字段，所述填充字段用于承载填充比特；其中，所述输入比特包括所述至少一个信息字段中的全部信息字段中承载的信息比特，所述填充字段在所述控制信息中的位置在所述至少一个信息字段的位置和所述目标CRC比特的位置之间，或，所述目标CRC比特在所述控制信息中的位置在所述至少一个信息字段的位置和所述填 充字段的位置之间。
可选地，作为一个例子，所述载荷部分还包括填充字段，所述填充字段用于承载填充比特；其中，所述输入比特包括所述至少一个信息字段中的部分信息字段中承载的信息比特，所述填充字段的在所述控制信息中的位置在所述至少一个信息字段的位置和所述目标CRC比特的位置之间，或，所述目标CRC比特在所述控制信息中的位置在所述部分信息字段的位置和所述至少一个信息字段中的其他信息字段以及所述填充字段的位置之间。
可选地，作为一个例子，所述至少一个信息字段中的第一信息字段用于指示所述控制信息的格式。
可选地，作为一个例子，所述控制信息的格式用于接收端设备确定所述至少一个信息字段的总长度。
可选地，作为一个例子，所述至少一个信息字段中的第二信息字段中承载的信息比特为预定比特，所述预定比特用于接收端设备根据所述预定比特的传输情况判断所述控制信息是否有效。
可选地，作为一个例子，当所述配置信息指示所述输入比特包括所述至少一个信息字段中的部分信息字段中承载的信息比特时，所述配置信息还用于指示所述部分信息字段。
根据本公开的一些实施例的发送端设备根据至少一个信息字段中的部分或全部信息字段中承载的信息比特生成目标CRC比特，使得接收端设备在对控制信息进行校验时，只对至少一个信息字段中的部分或全部信息字段中承载的信息比特进行校验，避免在控制信息中的信息比特传输没有出错而填充比特传输出错时，接收端设备认为控制信息传输出错的情况，或者避免在部分信息比特传错而重要信息比特没有错误，传错的部分信息比特接收端可以容忍时，接收端设备认为控制信息传输出错的情况，提高通信系统的链路性能。
根据本公开的一些实施例的发送端设备100可以参照对应本公开的一些实施例的发送端设备10，并且，该发送端设备中的各个单元/模块和上述其他操作和/或功能分别为了实现方法100至方法300中的相应流程，为了简洁，在此不再赘述。
图13示出了根据本公开的一些实施例的接收端设备的结构示意图，如图13所示，接收端设备200包括：至少一个处理器210、存储器220、至少一个网络接口230和用户接口240。接收端设备200中的各个组件通过总线系统250耦合在一起。可理解，总线系统250用于实现这些组件之间的连接通信。总线系统250除包括数据总线之外，还包括电源总线、控制总线和状态信号总线。但是为了清楚说明起见，在图13中将各种总线都标为总线系统250。
其中，用户接口240可以包括显示器、键盘或者点击设备(例如，鼠标，轨迹球(trackball)、触感板或者触摸屏等。
可以理解，本公开的一些实施例中的存储器220可以是易失性存储器或非易失性存储器，或可包括易失性和非易失性存储器两者。其中，非易失性存储器可以是只读存储器(Read-Only Memory，ROM)、可编程只读存储器(Programmable ROM，PROM)、可擦除可编程只读存储器(Erasable PROM，EPROM)、电可擦除可编程只读存储器(Electrically EPROM，EEPROM)或闪存。易失性存储器可以是随机存取存储器(Random Access Memory，RAM)，其用作外部高速缓存。通过示例性但不是限制性说明，许多形式的RAM可用，例如静态随机存取存储器(StaticRAM，SRAM)、动态随机存取存储器(Dynamic RAM，DRAM)、同步动态随机存取存储器(Synchronous DRAM，SDRAM)、双倍数据速率同步动态随机存取存储器(Double Data Rate SDRAM，DDRSDRAM)、增强型同步动态随机存取存储器(Enhanced SDRAM，ESDRAM)、同步连接动态随机存取存储器(Synchlink DRAM，SLDRAM)和直接内存总线随机存取存储器(DirectRambus RAM，DRRAM)。本公开的一些实施例描述的系统和方法的存储器220旨在包括但不限于这些和任意其它适合类型的存储器。
在一些实施方式中，存储器220存储了如下的元素，可执行模块或者数据结构，或者他们的子集，或者他们的扩展集：操作系统221和应用程序222。
其中，操作系统221，包含各种系统程序，例如框架层、核心库层、驱动层等，用于实现各种基础业务以及处理基于硬件的任务。应用程序222，包含各种应用程序，例如媒体播放器(Media Player)、浏览器(Browser)等，用 于实现各种应用业务。实现本公开的一些实施例方法的程序可以包含在应用程序222中。
在本公开的一些实施例中，接收端设备200还包括：存储在存储器上220并可在处理器210上运行的计算机程序，计算机程序被处理器210执行时处理器210实现如下步骤：接收控制信息；根据所述输入比特和所述目标CRC比特，校验所述控制信息；其中，所述控制信息包括载荷部分和目标循环冗余校验CRC比特，所述载荷部分包括至少一个信息字段，所述至少一个信息字段用于承载信息比特，所述目标CRC比特是发送端设备根据用于生成CRC比特的输入比特生成的，所述输入比特包括所述至少一个信息字段中的部分或全部信息字段中承载的信息比特。
上述本公开的一些实施例揭示的方法可以应用于处理器210中，或者由处理器210实现。处理器210可能是一种集成电路芯片，具有信号的处理能力。在实现过程中，上述方法的各步骤可以通过处理器210中的硬件的集成逻辑电路或者软件形式的指令完成。上述的处理器210可以是通用处理器、数字信号处理器(Digital Signal Processor，DSP)、专用集成电路(Application Specific Integrated Circuit，ASIC)、现场可编程门阵列(Field Programmable Gate Array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件。可以实现或者执行本公开的一些实施例中的公开的各方法、步骤及逻辑框图。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。结合本公开的一些实施例所公开的方法的步骤可以直接体现为硬件译码处理器执行完成，或者用译码处理器中的硬件及软件模块组合执行完成。软件模块可以位于随机存储器，闪存、只读存储器，可编程只读存储器或者电可擦写可编程存储器、寄存器等本领域成熟的计算机可读存储介质中。该计算机可读存储介质位于存储器220，处理器210读取存储器220中的信息，结合其硬件完成上述方法的步骤。具体地，该计算机可读存储介质上存储有计算机程序，计算机程序被处理器210执行时处理器210实现如上述方法200至方法400中的方法实施例的各步骤。
可以理解的是，本公开的一些实施例描述的这些实施例可以用硬件、软件、固件、中间件、微码或其组合来实现。对于硬件实现，处理单元可以实 现在一个或多个专用集成电路(Application Specific Integrated Circuits，ASIC)、数字信号处理器(Digital Signal Processing，DSP)、数字信号处理设备(DSP Device，DSPD)、可编程逻辑设备(Programmable Logic Device，PLD)、现场可编程门阵列(Field-Programmable Gate Array，FPGA)、通用处理器、控制器、微控制器、微处理器、用于执行本公开所述功能的其它电子单元或其组合中。
对于软件实现，可通过执行本公开的一些实施例所述功能的模块(例如过程、函数等)来实现本公开的一些实施例所述的技术。软件代码可存储在存储器中并通过处理器执行。存储器可以在处理器中或在处理器外部实现。
可选的，计算机程序被处理器210执行时还可实现如下步骤：接收发送端设备发送的配置信息，所述配置信息用于指示所述输入比特包括所述至少一个信息字段中的部分或全部信息字段中承载的信息比特；根据所述配置信息获取所述输入比特。
可选地，作为一个例子，所述载荷部分还包括填充字段，所述填充字段用于承载填充比特；其中，所述输入比特包括所述至少一个信息字段中的全部信息字段中承载的信息比特，所述填充字段在所述控制信息中的位置在所述至少一个信息字段的位置和所述目标CRC比特的位置之间，或，所述目标CRC比特在所述控制信息中的位置在所述至少一个信息字段的位置和所述填充字段的位置之间。
可选地，作为一个例子，所述载荷部分还包括填充字段，所述填充字段用于承载填充比特；其中，所述输入比特包括所述至少一个信息字段中的部分信息字段中承载的信息比特，所述填充字段的在所述控制信息中的位置在所述至少一个信息字段的位置和所述目标CRC比特的位置之间，或，所述目标CRC比特在所述控制信息中的位置在所述部分信息字段的位置和所述至少一个信息字段中的其他信息字段以及所述填充字段的位置之间。
可选地，作为一个例子，所述至少一个信息字段中的第一信息字段用于指示所述控制信息的格式；其中，计算机程序被处理器210执行时处理器210还可实现如下步骤：根据所述控制信息的格式，获取所述输入比特。
可选地，作为一个例子，所述控制信息的格式用于接收端设备确定所述至少一个信息字段的总长度；其中，计算机程序被处理器210执行时处理器 210还可实现如下步骤：根据所述控制信息的格式，确定所述至少一个信息字段的总长度；根据所述至少一个信息字段的总长度，获取所述输入比特。
可选地，作为一个例子，所述至少一个信息字段中的第二信息字段中承载的信息比特为预定比特，所述预定比特用于接收端设备根据所述预定比特的传输情况判断所述控制信息是否有效，计算机程序被处理器210执行时处理器210还可实现如下步骤：若校验所述控制信息成功，则根据所述预定比特的传输情况，判断所述控制信息是否有效；若所述预定比特传输正确，则确定所述控制信息有效；若所述预定比特传输错误，则确定所述控制信息无效。
可选地，作为一个例子，当所述配置信息用于指示所述输入比特包括所述至少一个信息字段中的部分信息字段中承载的信息比特时，所述配置信息还用于指示所述部分信息字段。
根据本公开的一些实施例的接收端设备接收到的控制信中的CRC比特是发送端设备根据至少一个信息字段中的部分或全部信息字段中承载的信息比特生成的，接收端设备在对控制信息进行校验时，只对至少一个信息字段中的部分或全部信息字段中承载的信息比特进行校验，避免在控制信息中的信息比特传输没有出错而填充比特传输出错时，接收端设备认为控制信息传输出错的情况，或者避免在部分信息比特传错而重要信息比特没有错误，传错的部分信息比特接收端可以容忍时，接收端设备认为控制信息传输出错的情况，提高通信系统的链路性能。
根据本公开的一些实施例的接收端设备200可以参照对应本公开的一些实施例的接收端设备20，并且，该接收端设备中的各个单元/模块和上述其他操作和/或功能分别为了实现方法200至方法400中的相应流程，为了简洁，在此不再赘述。
在本公开的上述实施例中，发送端设备根据控制信息中的全部信息比特或部分信息比特生成CRC比特，发送端设备在对控制信息进行校验时，可以只对控制信息中的全部信息比特或部分信息比特进行校验。因此，本公开的上述实施例公开的方法，避免在信息比特传输没有出错而填充比特传输出错时，接收端设备认为控制信息传输出错的情况，或者避免在部分信息比特传 错而重要信息比特没有错误，传错的部分信息比特接收端可以容忍时，接收端设备认为控制信息传输出错的情况，提高了通信系统的链路性能。
下面提供本公开的一些实施例的循环冗余校验的方法的其他示例。本公开的下面的实施例提供的循环冗余校验的方法和设备可以解决控制信息接收性能差的问题。
图14示出了根据本公开的一些实施例的循环冗余校验的方法1400，该方法1400由发送端设备执行。如图14所示，方法1400包括步骤S1410-S1440。
S1410，确定载荷部分，载荷部分包括至少一个信息字段，至少一个信息字段用于承载信息比特。
可选地，在新无线(New Radio，NR)系统中会有多种格式的控制信息，不同格式的控制信息的大小(Size)会有差别，如果要求接收端设备盲检测这些控制信息的格式的话，会导致接收端设备具有较高的复杂度。因此，在本公开的一些实施例中，通过在某些较短的控制信息的尾部填加填充比特(Padding Bits)的方法对齐不同格式的控制信息，以降低接收端设备的复杂度，其中，Padding Bits通常为“0”。
具体地，在一些实施例中，发送端设备根据要生成的控制信息的格式，确定是否有Padding Bits，如果确定有Padding Bits，载荷部分还包括填充字段，填充字段用于承载Padding Bits。
S1420，确定目标循环冗余校验CRC比特生成方式，目标CRC比特生成方式为多种CRC比特生成方式中的一种。
需要说明的是，本公开的一些实施例中，循环冗余校验(Cyclic Redundancy Check，CRC)比特也可以被称为“CRC码”，不同的CRC比特生成方式的差别在于生成CRC比特的过程的输入比特(Input Bits)的差别。
可选地，作为一个例子，多种CRC比特生成方式包括下列方式中的至少两种：将所述至少一个信息字段中的全部信息字段中承载的信息比特作为生成所述CRC比特的过程的输入比特；将所述至少一个信息字段中的部分信息字段中承载的信息比特作为生成所述CRC比特的过程的输入比特；将所述载荷部分中承载的所有比特作为生成所述CRC比特的过程的输入比特。
可选地，针对将至少一个信息字段中的部分信息字段中承载的信息比特 作为生成CRC比特的过程的输入比特的CRC比特生成方式，发送端设备和接收端设备可以事先约定将控制信息中的哪些信息字段中承载的信息比特作为生成CRC比特的过程的输入比特，或者发送端设备可以通过配置信息告知接收端设备需要将哪些字段中承载的信息比特作为生成CRC比特的过程的输入比特。
以上行控制信息(Uplink Control Information，UCI)为例，假设UCI中包括承载确认(Acknowledgement，ACK)/否定确认(Non-Acknowledgement，NACK)信息的字段、承载上行调度请求(Scheduling Request，SR)的字段和承载信道状态指示信息(Channel State Information，CSI)的字段，发送端设备和接收端设备可以事先约定将承载ACK/NACK的字段和承载SR的字段中承载的信息比特作为生成CRC比特的过程的输入比特。或者发送端设备可以通过配置信息指示接收端设备将据承载ACK/NACK的字段和承载SR的字段中承载的信息比特作为生成CRC比特的过程的输入比特。
可以理解的是，将至少一个信息字段中的全部信息字段承载的信息比特作为生成CRC比特的过程的输入比特，或者将至少一个信息字段中的部分信息字段承载的信息比特作为生成CRC比特的过程的输入比特，与相关技术中将整个载荷部分承载的所有比特作为生成CRC比特的过程的输入比特相比，能够避免在控制信息中的信息比特传输没有出错而填充比特传输出错时，接收端设备认为控制信息传输出错的情况，提高通信系统的链路性能。
在本公开的一些实施例中，可选地，发送端设备根据控制信息的格式，确定目标CRC比特生成方式；和/或发送端设备根据用于加扰控制信息的无线网络临时标识的类型，确定目标CRC比特生成方式。
S1430，根据所述载荷部分和所述目标CRC比特生成方式，生成CRC比特。
具体地，在S1430中，发送端设备根据目标CRC比特生成方式确定所述载荷部分中承载的所有比特中作为生成CRC比特的过程的输入比特的比特，并根据确定的作为输入比特的比特生成CRC比特。
S1440，生成包括所述载荷部分和所述CRC比特的控制信息。
可选地，在S1410中载荷部分还包括填充字段，CRC比特和载荷部分在 控制信息中的位置如图3或图4所示。在图3中，填充字段的位置在至少一个信息字段的位置和CRC比特的位置之间。在图4中，CRC比特的位置在至少一个信息字段的位置和填充字段的位置之间。在本公开的一些实施例中，CRC比特和载荷部分在控制信息中的位置可以是协议规定的，也可以是发送端设备和接收端设备事先约定的，还可以是发送端设备通过配置信息告知接收端设备的。
可选地，作为一个例子，控制信息中的载荷部分包括的至少一个信息字段中的一个信息字段用于指示控制信息的格式，接收端设备根据这个信息字段指示的控制信息的格式对控制信息进行解析，即可以获取到载荷部分承载的所有比特。
举例来说，用于指示控制信息的格式的信息字段取不同的值指示不同的格式。例如，假设通信系统中的控制信息的格式有4种，依次为格式AA、格式BB、格式CC和格式DD，用于指示控制信息的格式的信息字段包括2个比特，则可以用“00”指示控制信息的格式为“格式AA”，“01”指示控制信息的格式为“格式BB”、用“10”指示控制信息的格式为“格式CC”、用“11”指示控制信息的格式为“格式DD”。
进一步地，Payload的长度和CRC比特的长度可以通过预配置或者事先约定得知，为了便于接收端设备获知至少一个信息字段的总长度，可以通过协议规定或者发送端设备配置控制信息的格式与控制信息中包括的至少一个信息字段的总长度具有对应关系，接收端设备可以根据接收到的控制信息的格式和上述对应关系，确定接收到的控制信息中包括至少一个信息字段的总长度，进而获取到至少一个信息字段中的全部信息字段中承载的Information Bits。
可选地，作为另一个例子，至少一个信息字段中的一个信息字段中承载的信息比特为预定比特(或者说固定比特)，接收端设备可以根据预定比特的传输情况判断控制信息是否有效，从而判断控制信息的传输是否是虚警，能够满足控制信息对虚警的要求。在这种情况下，如果接收端设备校验控制信息成功，接收端设备进一步判断预定比特的传输情况，如果确定预定比特传输正确，则确定控制信息有效，控制信息的传输不是虚警(False Alarm)；如 果确定预定比特传输错误，则确定控制信息无效，控制信息的传输是虚警。
下面将结合具体的例子描述根据本公开的一些实施例的循环冗余校验的方法。图15是根据本公开的一些实施例的循环冗余校验的方法，如图15所示，方法1500包括步骤S1510-S1590。
S1510，发送端设备确定要发送的控制信息的格式。
可选地，作为一个例子，控制信息为下行控制信息(Downlink Control Information，DCI)，控制信息的格式为下列格式中的一种：“0”、“1”、“1A”、“1B”、“1C”、“1D”、“2”、“2A”、“2B”、“3”、“3A”。
S1520，发送端设备确定有Padding Bits，发送端设备对要发送的Information Bits补充Padding Bits构成Payload。
S1530，发送端设备根据控制信息的格式，确定目标CRC比特生成方式，根据目标CRC比特生成方式生成CRC比特。
可选地，目标CRC比特生成方式为方法1400中描述的多种CRC比特生成方式中的一种。
可选地，发送端设备为载荷部分长度相同的不同格式的控制信息选择不同的目标CRC比特生成方式。以DCI为例，为了降低接收端设备盲检的复杂度，格式为“1A”的DCI和格式为“0”的DCI的载荷部分的大小可以相同，但内容不相同。格式为“1A”的DCI用于下行数据的调度，对于False Alarm不敏感，而格式为“0”的DCI用于上行数据的调度，对False Alarm敏感。因此，当DCI的格式为“1A”时，发送端设备确定的目标CRC比特生成方式为将至少一个信息字段中的全部信息字段承载的信息比特作为生成CRC比特的过程的输入比特，或者将至少一个信息字段中的部分信息字段承载的信息比特作为生成CRC比特的过程的输入比特。当DCI的格式为“0”时，发送端设备确定的目标CRC比特生成方式为将所述载荷部分中承载的所有比特作为生成所述CRC比特的过程的输入比特。
S1540，将CRC比特附着到载荷部分构成控制信息。
可选地，在S1540中生成的控制信息中Information Bits承载在至少一个信息字段中，Padding Bits承载在填充字段中，至少一个信息字段、填充字段和CRC比特在控制信息中的位置如图3和图4所示。
S1550，发送端设备向接收端设备发送控制信息。
可选地，在S1550中，如果控制信息为DCI，则发送端设备为网络设备，接收端设备为终端设备，网络设备在物理下行控制信道(Physical Downlink Control Channel，PDCCH)上向终端设备发送DCI。如果控制信息为UCI，则发送端设为终端设备，接收端设备为网络设备，终端设备在物理上行控制信道(Physical Downlink Control Channel，PDCCH)上向网络设备发送UCI。
S1560，接收端设备确定控制信息的多种候选格式。
具体地，在S1560中，接收端设备根据协议的规定确定控制信息的多种候选格式，或者接收端设备根据发送端设备的配置信息确定控制信息的多种候选格式。
S1570，接收端设备根据控制信息的多种候选格式，确定多种CRC比特生成方式。
可选地，控制信息的每种候选格式对应一种CRC比特生成方式，或者几种候选格式对应同一种CRC比特生成方式，候选格式与CRC比特生成方式之间的对应关系可以是协议规定的，也可以是发送端设备通过配置信息配置的。
S1580，接收端设备根据多种CRC比特生成方式和控制信息中的CRC比特，校验控制信息。
可选地，在S1580中，接收端设备根据多种CRC比特生成方式中的每一种CRC比特生成方式计算CRC比特，并将计算出的多种CRC比特与控制信息中的CRC比特进行比较，如果计算出的多种CRC比特中存在与控制信息中的CRC比特相同的CRC比特，则控制信息校验成功，否则，控制信息校验失败。
S1590，接收端设备根据校验结果，判断控制信息是否传输正确。
具体地，如果在S1580中控制信息校验成功，则在S1590中认为控制信息传输正确。如果在S1580中控制信息校验失败，则在S1590中认为控制信息传输错误。
图16是根据本公开的一些实施例的循环冗余校验的方法。如图16所示，方法1600包括步骤S1610-S1690。
S1610，发送端设备确定用于加扰要发送的控制信息的无线网络临时标识RNTI(Radio Network Temporary Identity，RNTI)。
可选地，在S1610中，控制信息为DCI，RNTI为下列RNTI中的一种：SI-RNTI、P-RNTI、RA-RNTI、C-RNTI、TPC-PUCCH-RNTI、TPC-PUSCH-RNTI和SPS S-RNTI。
S1620，发送端设备确定有Padding Bits，发送端设备对要发送的Information Bits补充Padding Bits构成Payload。
S1630，发送端设备根据用于加扰要发送的控制信息的RNTI，确定目标CRC比特生成方式，根据目标CRC比特生成方式生成CRC比特。
可选地，目标CRC比特生成方式为方法1400中描述的多种CRC比特生成方式中的一种。
可选地，发送端设备为载荷部分长度相同的采用不同RNTI加扰的控制信息选择不同的目标CRC比特生成方式。以DCI为例，为了降低接收端设备盲检的复杂度，用半持续性-无线网络临时标识(Semi-Persistent Scheduling-RNTI，SPS-RNTI)加扰的DCI和用C-RNTI加扰的DCI的载荷部分的大小可以相同，但内容不相同。因此发送端设备可以为用SPS-RNTI和用C-RNTI加扰的DCI选择不同的目标CRC比特生成方式。
进一步地，在用SPS-RNTI加扰的DCI中的Information Bits中包括预定比特，接收端设备判断控制信息是否有效时，需要根据校验结果和预定比特的传输情况判断控制信息是否有效。
S1640，将CRC比特附着到载荷部分构成控制信息。
S1650，发送端设备向接收端设备发送控制信息。
S1660，接收端设备确定控制信息的多种候选RNTI。
具体地，在S1660中，接收端设备根据协议的规定确定控制信息的多种候选RNTI，或者接收端设备根据发送端设备的配置信息确定控制信息的多种候选RNTI。
S1670，接收端设备根据控制信息的多种候选RNTI，确定多种CRC比特生成方式。
可选地，控制信息的每种候选RNTI对应一种CRC比特生成方式，或者 几种候选RNTI对应同一种CRC比特生成方式，候选RNTI与CRC比特生成方式之间的对应关系可以是协议规定的，也可以是发送端设备通过配置信息配置的。
S1680，接收端设备根据多种CRC比特生成方式和控制信息中的CRC比特，校验控制信息。
可选地，在S1680中，接收端设备根据多种CRC比特生成方式中的每一种CRC比特生成方式计算CRC比特，并将计算出的多种CRC比特与控制信息中的CRC比特进行比较，如果计算出的多种CRC比特中存在与控制信息中的CRC比特相同的CRC比特，则认为控制信息校验成功，并且与控制信息中的CRC比特相同的CRC比特对应的CRC比特生成方式对应的RNTI即为用于加扰控制信息的RNTI。如果计算出的多种CRC比特中不存在与控制信息中的CRCF比特相同的CRC比特，则认为控制信息校验失败。
S1690，接收端设备根据校验结果，判断控制信息是否传输正确。
具体地，如果在S1680中控制信息校验成功，则在S1690中认为控制信息传输正确。如果在S1680中控制信息校验失败，则在S1690中认为控制信息传输错误。
在本公开的一些实施例中，可选地，在方法1500中的S1530中和在方法1600中的S1630中，发送端设备可以根据要发送的控制信息的格式和用于加扰该控制信息的RNTI从多种CRC比特生成方式中确定目标CRC比特生成方式，并根据目标CRC比特生成方式生产CRC比特。相对应地，在方法1500中的S1570中和方法1600中的S1670中，接收端设备根据控制信息的多种候选格式和用于加扰控制信息的多种RNTI确定多种CRC比特生成方式，并根据确定出的多种CRC比特生成方式和控制信息中的CRC比特校验控制信息。
图17示出了根据本公开的一些实施例的循环冗余校验的方法1700，该方法1700可以由接收端设备执行。可以理解的是，从接收端设备侧描述的发送端设备与接收端设备的交互与发送端设备侧的描述相同，为避免重复，适当省略相关描述。如图17所示，方法1700包括步骤S1710-S1720。
S1710，接收控制信息。
S1720，根据所述多种CRC比特生成方式和所述CRC比特，校验所述控 制信息；其中，所述控制信息包括载荷部分和循环冗余校验CRC比特，所述载荷部分包括至少一个信息字段，所述至少一个信息字段用于承载信息比特，所述CRC比特是发送端设备根据目标CRC比特生成方式和所述载荷部分生成的，所述目标CRC比特生成方式为多种CRC比特生成方式中的一种。
可选地，作为一个例子，在S1720中，接收端设备根据多种CRC比特生成方式生成多种CRC比特，并将生成的多种CRC比特与控制信息中的CRC比特进行比较，根据比较的结果判断控制信息是否传输正确。
根据本公开的一些实施例的循环冗余校验的方法，接收端设备接收到的控制信息中的CRC比特是发送端设备根据多种CRC比特生成方式中的目标CRC比特生成方式生成的，接收端设备根据多种CRC比特生成方式和控制信息中的CRC比特对控制信息进行校验，能够提高控制信息的接收性能。
在本公开的一些实施例中，可选地，所述多种CRC比特生成方式包括下列CRC码生成方式中的至少两种：将所述至少一个信息字段中的全部信息字段中承载的信息比特作为生成所述CRC比特过程的输入比特；将所述至少一个信息字段中的部分信息字段中承载的信息比特作为生成所述CRC比特过程的输入比特；将所述载荷部分中承载的所有比特作为生成所述CRC比特过程的输入比特。
在本公开的一些实施例中，可选地，接收端设备根据所述控制信息的多种候选格式，确定所述多种CRC比特生成方式；和/或，根据用于加扰所述控制信息的多种候选无线网络临时标识RNTI，确定所述多种CRC比特生成方式。
在本公开的一些实施例中，可选地，所述至少一个信息字段中的第一信息字段中承载的信息比特为预定比特，所述预定比特用于接收端设备根据所述预定比特的传输情况判断所述控制信息是否有效，若接收端设备根据所述多种CRC比特生成方式和所述CRC比特校验所述控制信息成功，则接收端设备根据所述预定比特的传输情况，判断所述控制信息是否有效；若所述预定比特传输正确，则确定所述控制信息有效；若所述预定比特传输错误，则确定所述控制信息无效。
在本公开的一些实施例中，可选地，所述至少一个信息字段中的第二信 息字段用于指示所述控制信息的格式；接收端设备根据控制信息的格式，获取载荷部分承载的所有比特，之后根据所述多种CRC比特生成方式、所述载荷部分承载的所有比特中的部分或全部比特以及所述CRC比特，校验所述控制信息。
在本公开的一些实施例中，可选地，所述载荷部分还包括填充字段，所述填充字段用于承载填充比特。
在本公开的一些实施例中，可选地，所述填充字段在所述控制信息中的位置在所述至少一个信息字段的位置和所述CRC比特的位置之间；或，所述CRC比特在所述控制信息中的位置在所述至少一个信息字段的位置和所述填充字段的位置之间。
在本公开的一些实施例中，以上结合图3、图4、图14至图17详细描述了根据本公开的一些实施例的循环冗余校验的方法，下面将结合图18详细描述根据本公开的一些实施例的发送端设备。
图18是根据本公开的一些实施例的发送端设备的结构示意图。如图18所示，发送端设备1800包括第一处理模块1801和第二处理模块1802。
第一处理模块1801，用于确定载荷部分，所述载荷部分包括至少一个信息字段，所述至少一个信息字段用于承载信息比特；所述第一处理模块1801，还用于确定目标循环冗余校验CRC比特生成方式，所述目标CRC比特生成方式为多种CRC比特生成方式中的一种。
第二处理模块1802，用于根据所述载荷部分和所述目标CRC比特生成方式，生成CRC比特；所述第二处理模块1802，还用于生成包括所述载荷部分和所述CRC比特的控制信息。
根据本公开的一些实施例的发送端设备从多种CRC比特生成方式中确定出目标CRC比特生成方式，根据确定的载荷部分和目标CRC比特生成方式生成CRC比特，并生成包括载荷部分和根据目标CRC比特生成方式生产的CRC比特的控制信息。发送端设备可以为不同的控制信息选择不同的目标CRC比特生成方式，满足控制信息对误块率和虚警的要求，提高控制信息的接收性能。
可选地，作为一个例子，所述多种CRC比特生成方式包括下列方式中的 至少两种：将所述至少一个信息字段中的全部信息字段中承载的信息比特作为生成所述CRC比特的过程的输入比特；将所述至少一个信息字段中的部分信息字段中承载的信息比特作为生成所述CRC比特的过程的输入比特；将所述载荷部分中承载的所有比特作为生成所述CRC比特的过程的输入比特。
可选地，作为一个例子，所述第一处理模块1801具体用于：根据所述控制信息的格式，确定所述目标CRC比特生成方式；和/或，根据用于加扰所述控制信息的无线网络临时标识RNTI的类型，确定所述目标CRC比特生成方式。
可选地，作为一个例子，所述至少一个信息字段中的第一信息字段中承载的信息比特为预定比特，所述预定比特用于接收端设备根据所述预定比特的传输情况判断所述控制信息是否有效。
可选地，作为一个例子，所述至少一个信息字段中的第二信息字段用于指示所述控制信息的格式。
可选地，作为一个例子，所述载荷部分还包括填充字段，所述填充字段用于承载填充比特。
可选地，作为一个例子，所述填充字段在所述控制信息中的位置在所述至少一个信息字段的位置和所述CRC比特的位置之间；或，所述CRC比特在所述控制信息中的位置在所述至少一个信息字段的位置和所述填充字段的位置之间。
根据本公开的一些实施例的发送端设备可以参照对应本公开的一些实施例的方法1400-方法1600的流程，并且，该发送端设备中的各个单元/模块和上述其他操作和/或功能分别为了实现方法1400-方法1600中的相应流程，为了简洁，在此不再赘述。
图19是根据本公开的一些实施例的接收端设备的结构示意图。如图19所示，接收端设备1900包括收发模块1901和处理模块1902。
收发模块1901，用于接收控制信息；处理模块1902，用于根据所述多种CRC比特生成方式和所述CRC比特，校验所述控制信息；其中，所述控制信息包括载荷部分和循环冗余校验CRC比特，所述载荷部分包括至少一个信息字段，所述至少一个信息字段用于承载信息比特，所述CRC比特是发送端 设备根据目标CRC比特生成方式和所述载荷部分生成的，所述目标CRC比特生成方式为多种CRC比特生成方式中的一种。
根据本公开的一些实施例的接收端设备接收到的控制信息中的CRC比特是发送端设备根据多种CRC比特生成方式中的目标CRC比特生成方式生成的，接收端设备根据多种CRC比特生成方式和控制信息中的CRC比特对控制信息进行校验，能够提高控制信息的接收性能。
可选地，作为一个例子，所述多种CRC比特生成方式包括下列CRC码生成方式中的至少两种：将所述至少一个信息字段中的全部信息字段中承载的信息比特作为生成所述CRC比特过程的输入比特；将所述至少一个信息字段中的部分信息字段中承载的信息比特作为生成所述CRC比特过程的输入比特；将所述载荷部分中承载的所有比特作为生成所述CRC比特过程的输入比特。
可选地，作为一个例子，所述处理模块1902还用于：根据所述控制信息的多种候选格式，确定所述多种CRC比特生成方式；和/或，根据用于加扰所述控制信息的多种候选无线网络临时标识RNTI，确定所述多种CRC比特生成方式。
可选地，作为一个例子，所述至少一个信息字段中的第一信息字段中承载的信息比特为预定比特，所述预定比特用于接收端设备根据所述预定比特的传输情况判断所述控制信息是否有效，所述处理模块1902还用于：若根据所述多种CRC比特生成方式和所述CRC比特校验所述控制信息成功，则根据所述预定比特的传输情况，判断所述控制信息是否有效；若所述预定比特传输正确，则确定所述控制信息有效；若所述预定比特传输错误，则确定所述控制信息无效。
可选地，作为一个例子，所述至少一个信息字段中的第二信息字段用于指示所述控制信息的格式；
其中，所述处理模块1902具体用于：根据所述控制信息的格式，获取所述载荷部分承载的所有比特；根据所述多种CRC比特生成方式、所述载荷部分承载的所有比特中的部分或全部比特以及所述CRC比特，校验所述控制信息。
可选地，作为一个例子，所述载荷部分还包括填充字段，所述填充字段用于承载填充比特。
可选地，作为一个例子，所述填充字段在所述控制信息中的位置在所述至少一个信息字段的位置和所述CRC比特的位置之间；或，所述CRC比特在所述控制信息中的位置在所述至少一个信息字段的位置和所述填充字段的位置之间。
根据本公开的一些实施例的接收端设备可以参照对应本公开的一些实施例的方法1500-方法1700的流程，并且，该接收端设备中的各个单元/模块和上述其他操作和/或功能分别为了实现方法1500-方法1700中的相应流程，为了简洁，在此不再赘述。
图20示出了根据本公开的一些实施例的发送端设备的结构示意图，能够实现方法1400至方法1600中的循环冗余校验的方法的细节，并能达到相同的效果。如图20所示，发送端设备2000包括处理器2010、收发机2020、存储器2030和总线接口。其中：
在本公开的一些实施例中，发送端设备2000还包括：存储在存储器2030上并可在所述处理器2010上运行的计算机程序，所述计算机程序被所述处理器2010执行时处理器2010执行以下步骤：确定载荷部分，所述载荷部分包括至少一个信息字段，所述至少一个信息字段用于承载信息比特；确定目标循环冗余校验CRC比特生成方式，所述目标CRC比特生成方式为多种CRC比特生成方式中的一种；根据所述载荷部分和所述目标CRC比特生成方式，生成CRC比特；生成包括所述载荷部分和所述CRC比特的控制信息。
在图20中，总线架构可以包括任意数量的互联的总线和桥，具体由处理器2010代表的一个或多个处理器和存储器2030代表的存储器的各种电路链接在一起。总线架构还可以将诸如外围设备、稳压器和功率管理电路等之类的各种其他电路链接在一起，这些都是本领域所公知的，因此，本文不再对其进行进一步描述。总线接口提供接口。收发机2020可以是多个元件，即包括发送机和接收机，提供用于在传输介质上与各种其他装置通信的单元。
处理器2010负责管理总线架构和通常的处理，存储器2030可以存储处理器2010在执行操作时所使用的数据。
可选的，计算机程序被处理器2010执行时还可实现如下步骤：根据所述控制信息的格式，确定所述目标CRC比特生成方式；和/或，根据用于加扰所述控制信息的无线网络临时标识RNTI的类型，确定所述目标CRC比特生成方式。
可选地，作为一个例子，所述多种CRC比特生成方式包括下列方式中的至少两种：将所述至少一个信息字段中的全部信息字段中承载的信息比特作为生成所述CRC比特的过程的输入比特；将所述至少一个信息字段中的部分信息字段中承载的信息比特作为生成所述CRC比特的过程的输入比特；所述载荷部分中承载的所有比特作为生成所述CRC比特的过程的输入比特。
可选地，作为一个例子，所述至少一个信息字段中的第一信息字段中承载的信息比特为预定比特，所述预定比特用于接收端设备根据所述预定比特的传输情况判断所述控制信息是否有效。
可选地，作为一个例子，所述至少一个信息字段中的第二信息字段用于指示所述控制信息的格式。
可选地，作为一个例子，所述载荷部分还包括填充字段，所述填充字段用于承载填充比特。
可选地，作为一个例子，所述填充字段在所述控制信息中的位置在所述至少一个信息字段的位置和所述CRC比特的位置之间；或，所述CRC比特在所述控制信息中的位置在所述至少一个信息字段的位置和所述填充字段的位置之间。
根据本公开的一些实施例的发送端设备从多种CRC比特生成方式中确定出目标CRC比特生成方式，根据确定的载荷部分和目标CRC比特生成方式生成CRC比特，并生成包括载荷部分和根据目标CRC比特生成方式生产的CRC比特的控制信息。发送端设备可以为不同的控制信息选择不同的目标CRC比特生成方式，满足控制信息对误块率和虚警的要求，提高控制信息的接收性能。
根据本公开的一些实施例的发送端设备2000可以参照对应本公开的一些实施例的发送端设备1900，并且，该发送端设备中的各个单元/模块和上述其他操作和/或功能分别为了实现方法1400-方法1600中的相应流程，为了简 洁，在此不再赘述。
图21示出了根据本公开的一些实施例的接收端设备的结构示意图，如图21所示，接收端设备2100包括：至少一个处理器2110、存储器2120、至少一个网络接口2130和用户接口2140。接收端设备2100中的各个组件通过总线系统2150耦合在一起。可理解，总线系统2150用于实现这些组件之间的连接通信。总线系统2150除包括数据总线之外，还包括电源总线、控制总线和状态信号总线。但是为了清楚说明起见，在图21中将各种总线都标为总线系统2150。
其中，用户接口2140可以包括显示器、键盘或者点击设备(例如，鼠标，轨迹球(trackball)、触感板或者触摸屏等。
可以理解，本公开的一些实施例中的存储器2120可以是易失性存储器或非易失性存储器，或可包括易失性和非易失性存储器两者。其中，非易失性存储器可以是只读存储器(Read-Only Memory，ROM)、可编程只读存储器(Programmable ROM，PROM)、可擦除可编程只读存储器(Erasable PROM，EPROM)、电可擦除可编程只读存储器(Electrically EPROM，EEPROM)或闪存。易失性存储器可以是随机存取存储器(Random Access Memory，RAM)，其用作外部高速缓存。通过示例性但不是限制性说明，许多形式的RAM可用，例如静态随机存取存储器(StaticRAM，SRAM)、动态随机存取存储器(Dynamic RAM，DRAM)、同步动态随机存取存储器(Synchronous DRAM，SDRAM)、双倍数据速率同步动态随机存取存储器(Double Data Rate SDRAM，DDRSDRAM)、增强型同步动态随机存取存储器(Enhanced SDRAM，ESDRAM)、同步连接动态随机存取存储器(Synchlink DRAM，SLDRAM)和直接内存总线随机存取存储器(DirectRambus RAM，DRRAM)。本公开的一些实施例描述的系统和方法的存储器220旨在包括但不限于这些和任意其它适合类型的存储器。
在一些实施方式中，存储器2120存储了如下的元素，可执行模块或者数据结构，或者他们的子集，或者他们的扩展集：操作系统2121和应用程序2122。
其中，操作系统2121，包含各种系统程序，例如框架层、核心库层、驱 动层等，用于实现各种基础业务以及处理基于硬件的任务。应用程序2122，包含各种应用程序，例如媒体播放器(Media Player)、浏览器(Browser)等，用于实现各种应用业务。实现本公开的一些实施例方法的程序可以包含在应用程序222中。
在本公开的一些实施例中，接收端设备2100还包括：存储在存储器上2120并可在处理器2110上运行的计算机程序，计算机程序被处理器2110执行时处理器2110实现如下步骤：接收控制信息；根据所述多种CRC比特生成方式和所述CRC比特，校验所述控制信息；其中，所述控制信息包括载荷部分和循环冗余校验CRC比特，所述载荷部分包括至少一个信息字段，所述至少一个信息字段用于承载信息比特，所述CRC比特是发送端设备根据目标CRC比特生成方式和所述载荷部分生成的，所述目标CRC比特生成方式为多种CRC比特生成方式中的一种。
上述本公开的一些实施例揭示的方法可以应用于处理器2110中，或者由处理器2110实现。处理器2110可能是一种集成电路芯片，具有信号的处理能力。在实现过程中，上述方法的各步骤可以通过处理器210中的硬件的集成逻辑电路或者软件形式的指令完成。上述的处理器210可以是通用处理器、数字信号处理器(Digital Signal Processor，DSP)、专用集成电路(Application Specific Integrated Circuit，ASIC)、现场可编程门阵列(Field Programmable Gate Array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件。可以实现或者执行本公开的一些实施例中的公开的各方法、步骤及逻辑框图。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。结合本公开的一些实施例所公开的方法的步骤可以直接体现为硬件译码处理器执行完成，或者用译码处理器中的硬件及软件模块组合执行完成。软件模块可以位于随机存储器，闪存、只读存储器，可编程只读存储器或者电可擦写可编程存储器、寄存器等本领域成熟的计算机可读存储介质中。该计算机可读存储介质位于存储器2120，处理器2110读取存储器2120中的信息，结合其硬件完成上述方法的步骤。具体地，该计算机可读存储介质上存储有计算机程序，计算机程序被处理器2110执行时处理器2110实现如上述方法1500至方法1700中的方法实施例的各步骤。
可以理解的是，本公开的一些实施例描述的这些实施例可以用硬件、软件、固件、中间件、微码或其组合来实现。对于硬件实现，处理单元可以实现在一个或多个专用集成电路(Application Specific Integrated Circuits，ASIC)、数字信号处理器(Digital Signal Processing，DSP)、数字信号处理设备(DSP Device，DSPD)、可编程逻辑设备(Programmable Logic Device，PLD)、现场可编程门阵列(Field-Programmable Gate Array，FPGA)、通用处理器、控制器、微控制器、微处理器、用于执行本公开所述功能的其它电子单元或其组合中。
对于软件实现，可通过执行本公开的一些实施例所述功能的模块(例如过程、函数等)来实现本公开的一些实施例所述的技术。软件代码可存储在存储器中并通过处理器执行。存储器可以在处理器中或在处理器外部实现。
可选的，计算机程序被处理器2110执行时处理器2110还可实现如下步骤：根据所述控制信息的多种候选格式，确定所述多种CRC比特生成方式；和/或，根据用于加扰所述控制信息的多种候选无线网络临时标识RNTI，确定所述多种CRC比特生成方式。
可选地，作为一个例子，所述多种CRC比特生成方式包括下列CRC码生成方式中的至少两种：将所述至少一个信息字段中的全部信息字段中承载的信息比特作为生成所述CRC比特过程的输入比特；将所述至少一个信息字段中的部分信息字段中承载的信息比特作为生成所述CRC比特过程的输入比特；将所述载荷部分中承载的所有比特作为生成所述CRC比特过程的输入比特。
可选地，作为一个例子，所述至少一个信息字段中的第一信息字段中承载的信息比特为预定比特，所述预定比特用于接收端设备根据所述预定比特的传输情况判断所述控制信息是否有效，所述计算机程序被处理器210执行时还可实现如下步骤：若根据所述多种CRC比特生成方式和所述CRC比特校验所述控制信息成功，则根据所述预定比特的传输情况，判断所述控制信息是否有效；若所述预定比特传输正确，则确定所述控制信息有效；若所述预定比特传输错误，则确定所述控制信息无效。
可选地，作为一个例子，所述至少一个信息字段中的第二信息字段用于指示所述控制信息的格式；其中，计算机程序被处理器2110执行时处理器 2110还可实现如下步骤：根据所述控制信息的格式，获取所述载荷部分承载的所有比特；根据所述多种CRC比特生成方式、所述载荷部分承载的所有比特中的部分或全部比特、以及所述CRC比特，校验所述控制信息。
可选地，作为一个例子，所述载荷部分还包括填充字段，所述填充字段用于承载填充比特。
可选地，作为一个例子，所述填充字段在所述控制信息中的位置在所述至少一个信息字段的位置和所述CRC比特的位置之间；或，所述CRC比特在所述控制信息中的位置在所述至少一个信息字段的位置和所述填充字段的位置之间。根据本公开的一些实施例的接收端设备接收到的控制信息中的CRC比特是发送端设备根据多种CRC比特生成方式中的目标CRC比特生成方式生成的，接收端设备根据多种CRC比特生成方式和控制信息中的CRC比特对控制信息进行校验，能够提高控制信息的接收性能。
根据本公开的一些实施例的接收端设备2100可以参照对应本公开的一些实施例的接收端设备1900，并且，该接收端设备中的各个单元/模块和上述其他操作和/或功能分别为了实现方法1500-方法1700中的相应流程，为了简洁，在此不再赘述。
本公开的上述实施例提供的方法中，发送端设备从多种CRC比特生成方式中确定出目标CRC比特生成方式，根据确定的载荷部分和目标CRC比特生成方式生成CRC比特，并生成包括载荷部分和根据目标CRC比特生成方式生产的CRC比特的控制信息。因此，发送端设备可以为不同的控制信息选择不同的目标CRC比特生成方式，满足控制信息对误块率(Block Error Rate，BLER)和虚警(False Alarm)的个性化要求，提高控制信息的接收性能。
本公开的一些实施例还提供一种包括指令的计算机程序产品，当计算机运行所述计算机程序产品的所述指令时，所述计算机执行上述方法实施例的循环冗余校验的方法。具体地，该计算机程序产品可以运行于上述发送端设备和接收端设备上。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特 定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本公开的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本公开所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本公开各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本公开的技术方案本质上或者说对相关技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本公开各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限 于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应所述以权利要求的保护范围为准。

Claims (42)

  1. 一种循环冗余校验的方法，应用于发送端设备，所述方法包括：
    确定载荷部分，所述载荷部分包括至少一个信息字段，所述至少一个信息字段用于承载信息比特；
    确定用于生成循环冗余校验CRC比特的输入比特，所述输入比特包括所述至少一个信息字段中的部分或全部信息字段中承载的信息比特；
    根据所述输入比特生成目标CRC比特；
    生成包括所述载荷部分和所述目标CRC比特的控制信息。
  2. 根据权利要求1所述的方法，其中，所述载荷部分还包括填充字段，所述填充字段用于承载填充比特；
    其中，所述输入比特包括所述至少一个信息字段中的全部信息字段中承载的信息比特，所述填充字段在所述控制信息中的位置在所述至少一个信息字段的位置和所述目标CRC比特的位置之间，或，所述目标CRC比特在所述控制信息中的位置在所述至少一个信息字段的位置和所述填充字段的位置之间。
  3. 根据权利要求1所述的方法，其中，所述载荷部分还包括填充字段，所述填充字段用于承载填充比特；
    其中，所述输入比特包括所述至少一个信息字段中的部分信息字段中承载的信息比特，所述填充字段的在所述控制信息中的位置在所述至少一个信息字段的位置和所述目标CRC比特的位置之间，或，所述目标CRC比特在所述控制信息中的位置在所述部分信息字段的位置和所述至少一个信息字段中的其他信息字段以及所述填充字段的位置之间。
  4. 根据权利要求1至3中任一项所述的方法，其中，所述至少一个信息字段中的第一信息字段用于指示所述控制信息的格式。
  5. 根据权利要求4所述的方法，其中，所述控制信息的格式用于接收端设备确定所述至少一个信息字段的总长度。
  6. 根据权利要求中1至5中任一项所述的方法，其中，所述至少一个信息字段中的第二信息字段中承载的信息比特为预定比特，所述预定比特用于 接收端设备根据所述预定比特的传输情况判断所述控制信息是否有效。
  7. 根据权利要求1至6中任一项所述的方法，其中，所述方法还包括：
    向接收端设备发送配置信息，所述配置信息用于指示所述输入比特包括所述至少一个信息字段中的部分或全部信息字段中承载的信息比特。
  8. 根据权利要求7所述的方法，其中，当所述配置信息指示所述输入比特包括所述至少一个信息字段中的部分信息字段中承载的信息比特时，所述配置信息还用于指示所述部分信息字段。
  9. 一种循环冗余校验的方法，应用于接收端设备，所述方法包括：
    接收控制信息；
    根据所述输入比特和所述目标CRC比特，校验所述控制信息；
    其中，所述控制信息包括载荷部分和目标循环冗余校验CRC比特，所述载荷部分包括至少一个信息字段，所述至少一个信息字段用于承载信息比特，所述目标CRC比特是发送端设备根据用于生成CRC比特的输入比特生成的，所述输入比特包括所述至少一个信息字段中的部分或全部信息字段中承载的信息比特。
  10. 根据权利要求9所述的方法，其中，所述载荷部分还包括填充字段，所述填充字段用于承载填充比特；
    其中，所述输入比特包括所述至少一个信息字段中的全部信息字段中承载的信息比特，所述填充字段在所述控制信息中的位置在所述至少一个信息字段的位置和所述目标CRC比特的位置之间，或，所述目标CRC比特在所述控制信息中的位置在所述至少一个信息字段的位置和所述填充字段的位置之间。
  11. 根据权利要求9所述的方法，其中，所述载荷部分还包括填充字段，所述填充字段用于承载填充比特；
    其中，所述输入比特包括所述至少一个信息字段中的部分信息字段中承载的信息比特，所述填充字段的在所述控制信息中的位置在所述至少一个信息字段的位置和所述目标CRC比特的位置之间，或，所述目标CRC比特在所述控制信息中的位置在所述部分信息字段的位置和所述至少一个信息字段中的其他信息字段以及所述填充字段的位置之间。
  12. 根据权利要求9至11中任一项所述的方法，其中，所述至少一个信息字段中的第一信息字段用于指示所述控制信息的格式；
    其中，在根据所述输入比特和所述目标CRC比特，校验所述控制信息之前，所述方法还包括：
    根据所述控制信息的格式，获取所述输入比特。
  13. 根据权利要求12所述的方法，其中，所述控制信息的格式用于接收端设备确定所述至少一个信息字段的总长度；
    其中，所述根据所述控制信息的格式，获取所述输入比特，包括：
    根据所述控制信息的格式，确定所述至少一个信息字段的总长度；
    根据所述至少一个信息字段的总长度，获取所述输入比特。
  14. 根据权利要求9至13中任一项所述的方法，其中，所述至少一个信息字段中的第二信息字段中承载的信息比特为预定比特，所述预定比特用于接收端设备根据所述预定比特的传输情况判断所述控制信息是否有效，所述方法还包括：
    若校验所述控制信息成功，则根据所述预定比特的传输情况，判断所述控制信息是否有效；
    若所述预定比特传输正确，则确定所述控制信息有效；
    若所述预定比特传输错误，则确定所述控制信息无效。
  15. 根据权利要求9至14中任一项所述的方法，其中，在根据所述输入比特和所述目标CRC比特，校验所述控制信息之前，所述方法还包括：
    接收发送端设备发送的配置信息，所述配置信息用于指示所述输入比特包括所述至少一个信息字段中的部分或全部信息字段中承载的信息比特；
    根据所述配置信息获取所述输入比特。
  16. 根据权利要求15所述的方法，其中，当所述配置信息用于指示所述输入比特包括所述至少一个信息字段中的部分信息字段中承载的信息比特时，所述配置信息还用于指示所述部分信息字段。
  17. 一种发送端设备，包括：
    第一处理模块，用于确定载荷部分，所述载荷部分包括至少一个信息字段，所述至少一个信息字段用于承载信息比特；
    所述第一处理模块，还用于确定用于生成循环冗余校验CRC比特的输入比特，所述输入比特包括所述至少一个信息字段中的部分或全部信息字段中承载的信息比特；
    第二处理模块，用于根据所述输入比特生成目标CRC比特；
    所述第二处理模块，还用于生成包括所述载荷部分和所述目标CRC比特的控制信息。
  18. 一种接收端设备，包括：
    收发模块，用于接收控制信息；
    处理模块，用于根据所述输入比特和所述目标CRC比特，校验所述控制信息；
    其中，所述控制信息包括载荷部分和目标循环冗余校验CRC比特，所述载荷部分包括至少一个信息字段，所述至少一个信息字段用于承载信息比特，所述目标CRC比特是发送端设备根据用于生成CRC比特的输入比特生成的，所述输入比特包括所述至少一个信息字段中的部分或全部信息字段中承载的信息比特。
  19. 一种发送端设备，包括：存储器、处理器及存储在所述存储器上并可在所述处理器上运行的循环冗余校验程序，所述循环冗余校验程序被所述处理器执行时所述处理器实现如权利要求1至8中任一项所述的循环冗余校验的方法的步骤。
  20. 一种接收端设备，包括：存储器、处理器及存储在所述存储器上并可在所述处理器上运行的循环冗余校验程序，所述循环冗余校验程序被所述处理器执行时所述处理器实现如权利要求9至16中任一项所述的循环冗余校验的方法的步骤。
  21. 一种计算机可读存储介质，所述计算机可读存储介质上存储有循环冗余校验程序，所述循环冗余校验程序被处理器执行时所述处理器实现如权利要求1至8中任一项所述的循环冗余校验的方法的步骤。
  22. 一种计算机可读存储介质，其中，所述计算机可读存储介质上存储有循环冗余校验程序，所述循环冗余校验程序被处理器执行时所述处理器实现如权利要求9至16中任一项所述的循环冗余校验的方法的步骤。
  23. 一种循环冗余校验的方法，应用于发送端设备，所述方法包括：
    确定载荷部分，所述载荷部分包括至少一个信息字段，所述至少一个信息字段用于承载信息比特；
    确定目标循环冗余校验CRC比特生成方式，所述目标CRC比特生成方式为多种CRC比特生成方式中的一种；
    根据所述载荷部分和所述目标CRC比特生成方式，生成CRC比特；
    生成包括所述载荷部分和所述CRC比特的控制信息。
  24. 根据权利要求23所述的方法，其中，所述多种CRC比特生成方式包括下列方式中的至少两种：
    将所述至少一个信息字段中的全部信息字段中承载的信息比特作为生成所述CRC比特的过程的输入比特；
    将所述至少一个信息字段中的部分信息字段中承载的信息比特作为生成所述CRC比特的过程的输入比特；
    将所述载荷部分中承载的所有比特作为生成所述CRC比特的过程的输入比特。
  25. 根据权利要求23或24所述的方法，其中，所述确定目标循环冗余校验CRC码生成方式，包括：
    根据所述控制信息的格式，确定所述目标CRC比特生成方式；和/或，
    根据用于加扰所述控制信息的无线网络临时标识RNTI的类型，确定所述目标CRC比特生成方式。
  26. 根据权利要求23至25中任一项所述的方法，其中，所述至少一个信息字段中的第一信息字段中承载的信息比特为预定比特，所述预定比特用于接收端设备根据所述预定比特的传输情况判断所述控制信息是否有效。
  27. 根据权利要求23至26中任一项所述的方法，其中，所述至少一个信息字段中的第二信息字段用于指示所述控制信息的格式。
  28. 根据权利要求23至27中任一项所述的方法，其中，所述载荷部分还包括填充字段，所述填充字段用于承载填充比特。
  29. 根据权利要求28所述的方法，其中，所述填充字段在所述控制信息中的位置在所述至少一个信息字段的位置和所述CRC比特的位置之间；或， 所述CRC比特在所述控制信息中的位置在所述至少一个信息字段的位置和所述填充字段的位置之间。
  30. 一种循环冗余校验的方法，应用于接收端设备，所述方法包括：
    接收控制信息；
    根据所述多种CRC比特生成方式和所述CRC比特，校验所述控制信息；
    其中，所述控制信息包括载荷部分和循环冗余校验CRC比特，所述载荷部分包括至少一个信息字段，所述至少一个信息字段用于承载信息比特，所述CRC比特是发送端设备根据目标CRC比特生成方式和所述载荷部分生成的，所述目标CRC比特生成方式为多种CRC比特生成方式中的一种。
  31. 根据权利要求30所述的方法，其中，所述多种CRC比特生成方式包括下列CRC码生成方式中的至少两种：
    将所述至少一个信息字段中的全部信息字段中承载的信息比特作为生成所述CRC比特过程的输入比特；
    将所述至少一个信息字段中的部分信息字段中承载的信息比特作为生成所述CRC比特过程的输入比特；
    将所述载荷部分中承载的所有比特作为生成所述CRC比特过程的输入比特。
  32. 根据权利要求30或31所述的方法，还包括：
    根据所述控制信息的多种候选格式，确定所述多种CRC比特生成方式；和/或，
    根据用于加扰所述控制信息的多种候选无线网络临时标识RNTI，确定所述多种CRC比特生成方式。
  33. 根据权利要求30至32中任一项所述的方法，其中，所述至少一个信息字段中的第一信息字段中承载的信息比特为预定比特，所述预定比特用于接收端设备根据所述预定比特的传输情况判断所述控制信息是否有效，所述方法还包括：
    若根据所述多种CRC比特生成方式和所述CRC比特校验所述控制信息成功，则根据所述预定比特的传输情况，判断所述控制信息是否有效；
    若所述预定比特传输正确，则确定所述控制信息有效；
    若所述预定比特传输错误，则确定所述控制信息无效。
  34. 根据权利要求30至33中任一项所述的方法，其中，所述至少一个信息字段中的第二信息字段用于指示所述控制信息的格式；
    其中，所述根据所述多种CRC比特生成方式和所述CRC比特，校验所述控制信息，包括：
    根据所述控制信息的格式，获取所述载荷部分承载的所有比特；
    根据所述多种CRC比特生成方式、所述载荷部分承载的所有比特中的部分或全部比特、以及所述CRC比特，校验所述控制信息。
  35. 根据权利要求30至34中任一项所述的方法，其中，所述载荷部分还包括填充字段，所述填充字段用于承载填充比特。
  36. 根据权利要求35所述的方法，其中，所述填充字段在所述控制信息中的位置在所述至少一个信息字段的位置和所述CRC比特的位置之间；或，所述CRC比特在所述控制信息中的位置在所述至少一个信息字段的位置和所述填充字段的位置之间。
  37. 一种发送端设备，包括：
    第一处理模块，用于确定载荷部分，所述载荷部分包括至少一个信息字段，所述至少一个信息字段用于承载信息比特；
    所述第一处理模块，还用于确定目标循环冗余校验CRC比特生成方式，所述目标CRC比特生成方式为多种CRC比特生成方式中的一种；
    第二处理模块，用于根据所述载荷部分和所述目标CRC比特生成方式，生成CRC比特；
    所述第二处理模块，还用于生成包括所述载荷部分和所述CRC比特的控制信息。
  38. 一种接收端设备，包括：
    收发模块，用于接收控制信息；
    处理模块，用于根据所述多种CRC比特生成方式和所述CRC比特，校验所述控制信息；
    其中，所述控制信息包括载荷部分和循环冗余校验CRC比特，所述载荷部分包括至少一个信息字段，所述至少一个信息字段用于承载信息比特，所 述CRC比特是发送端设备根据目标CRC比特生成方式和所述载荷部分生成的，所述目标CRC比特生成方式为多种CRC比特生成方式中的一种。
  39. 一种发送端设备，包括：存储器、处理器及存储在所述存储器上并可在所述处理器上运行的循环冗余校验程序，所述循环冗余校验程序被所述处理器执行时所述处理器实现如权利要求23至29中任一项所述的循环冗余校验的方法的步骤。
  40. 一种接收端设备，包括：存储器、处理器及存储在所述存储器上并可在所述处理器上运行的循环冗余校验程序，所述循环冗余校验程序被所述处理器执行时所述处理器实现如权利要求30至36中任一项所述的循环冗余校验的方法的步骤。
  41. 一种计算机可读存储介质，所述计算机可读存储介质上存储有循环冗余校验程序，所述循环冗余校验程序被处理器执行时所述处理器实现如权利要求23至29中任一项所述的循环冗余校验的方法的步骤。
  42. 一种计算机可读存储介质，其中，所述计算机可读存储介质上存储有循环冗余校验程序，所述循环冗余校验程序被处理器执行时所述处理器实现如权利要求30至36中任一项所述的循环冗余校验的方法的步骤。
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