WO2019042474A1 - 阵列基板及显示装置 - Google Patents

阵列基板及显示装置 Download PDF

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Publication number
WO2019042474A1
WO2019042474A1 PCT/CN2018/103994 CN2018103994W WO2019042474A1 WO 2019042474 A1 WO2019042474 A1 WO 2019042474A1 CN 2018103994 W CN2018103994 W CN 2018103994W WO 2019042474 A1 WO2019042474 A1 WO 2019042474A1
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Prior art keywords
thin film
repair
film transistor
oled
pixel
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PCT/CN2018/103994
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English (en)
French (fr)
Inventor
程鸿飞
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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Priority to KR1020197031467A priority Critical patent/KR102277886B1/ko
Priority to JP2019527804A priority patent/JP7212617B2/ja
Priority to US16/489,165 priority patent/US10991917B2/en
Priority to EP18849825.7A priority patent/EP3680935B1/en
Publication of WO2019042474A1 publication Critical patent/WO2019042474A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/81—Anodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8051—Anodes
    • H10K59/80515—Anodes characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/861—Repairing

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to an array substrate and a display device.
  • OLED Organic Light Emitting Diode
  • AMOLED Active-matrix Organic Light Emitting Diode
  • a first aspect of the present disclosure provides an array substrate, a substrate substrate, and a plurality of pixel units arranged on the substrate, each of the pixel units including: an open circuit repair structure, an OLED, and a pixel driving circuit, wherein the open circuit repair structure is provided with a repair line; an orthographic projection of the repair line on the base substrate and an orthographic projection of an anode of the OLED on the base substrate partially or completely The ground coincides to form a coincidence zone; the break repair point is located in the coincidence zone.
  • the pixel driving circuit includes at least one thin film transistor; the at least one thin film transistor is a driving thin film transistor, or the at least one thin film transistor is a driving thin film transistor and a switching thin film transistor.
  • an insulating film layer is disposed between the repair line and the anode of the OLED.
  • the repair line in any one of the adjacent two pixel units is the phase And a drain extension line of the driving thin film transistor in another one of the two of the plurality of pixel units.
  • a drain extension line of a driving thin film transistor in each pixel unit is orthographically projected on the substrate substrate, and an extension line of the OLED anode in the pixel unit is in the lining
  • the orthographic projections of the base substrate partially or completely overlap to form a coincident region.
  • a drain extension line of the driving thin film transistor in each pixel unit is disposed adjacent to a surface of an anode extension line of the OLED in the pixel unit, and a passivation layer and a planarization layer are disposed;
  • the planarization layer is provided with a groove corresponding to the region of the break repair point, and the anode extension line covers the groove.
  • the passivation layer and the planarization layer are provided with via holes, and a drain of the driving thin film transistor is connected to an anode of the LOED through the via.
  • the repair line and the phase in the any one of the adjacent two pixel units is insulated from the same layer, and the repair line is disposed between the drain of the driving thin film transistor and the drain of the driving thin film transistor. Interlayer insulation layer.
  • the interlayer insulating layer is provided with a via hole through which the drain of the driving thin film transistor is connected to the repair line.
  • an interlayer insulating layer, a passivation layer, and a planarization layer are stacked between a repair line in each pixel unit and an anode of the OLED in the pixel unit; a region of the circuit breaker repairing point is provided with a groove, an OLED anode in the pixel unit covers the groove; or a region where the planarization layer and the passivation layer correspond to the circuit breaker repair point are concave a trench in which the OLED anode of the pixel unit covers the recess.
  • the gate of the thin film transistor for switching is connected to a gate line, and a source of the thin film transistor for the switch is connected to the data line.
  • the plurality of pixel units in the same row correspond to the same gate line; the orthographic projection of the repair line in the each pixel unit in the base substrate, and the corresponding gate line in the The orthographic projection of the base substrate intersects.
  • some embodiments of the present disclosure provide a display device, comprising the array substrate according to the first aspect, the array substrate comprises: a substrate substrate; and the array is arranged on the substrate substrate a pixel unit, each of the pixel units includes: an open circuit repair structure, an OLED and a pixel driving circuit, wherein the circuit repairing structure is provided with a repair line; an orthographic projection of the repair line on the base substrate The orthographic projections of the anodes of the OLEDs on the substrate substrate partially or completely overlap to form a coincident region; the break repair points are located in the overlap region.
  • FIG. 1 is a circuit schematic diagram of a pixel driving circuit in the related art
  • FIG. 2 is a schematic top plan view of an array substrate according to some embodiments of the present disclosure.
  • FIG. 3 is a cross-sectional view of the array substrate shown in FIG. 2 along a fold line A-A';
  • FIG. 4 is another schematic top view of an array substrate according to some embodiments of the present disclosure.
  • Figure 5 is a cross-sectional view of the array substrate shown in Figure 4 taken along line B-B'.
  • a plurality of pixel units are arranged in an array on an array substrate using an active-matrix organic light emitting diode (AMOLED), wherein the same row
  • AMOLED active-matrix organic light emitting diode
  • Each pixel unit shares one gate line, and each pixel unit of the same column shares one data line.
  • Each pixel unit includes an Organic Light Emitting Diode (OLED) and a pixel driving circuit connected to the anode of the OLED.
  • OLED Organic Light Emitting Diode
  • the circuit schematic diagram of the pixel driving circuit is as shown in FIG. 1.
  • the pixel driving circuit includes a thin film transistor T1 for switching, a thin film transistor T2 for driving, and a storage capacitor.
  • the gate of the thin film transistor T1 for switching is connected to the gate line Gate, and the switch
  • the source of the thin film transistor T1 is connected to the data line Data
  • the drain of the switching thin film transistor T1 is connected to the gate of the driving thin film transistor T2 and one plate C1 of the storage capacitor, respectively
  • the source of the driving thin film transistor T2 is respectively
  • the other electrode plate C2 of the storage capacitor and the power supply line Vdd are connected, and the drain of the driving thin film transistor T2 is connected to the anode of the OLED.
  • the structure of the pixel driving circuit in each pixel unit is relatively complicated, so that the preparation process of the array substrate in which each pixel unit is located is also complicated, which leads to the defect of partial wiring disconnection in the pixel driving circuit during the preparation process of the array substrate.
  • the location of the defect that appears is the break point X'.
  • an array substrate provided by some embodiments of the present disclosure includes a substrate substrate 1; and a plurality of pixel units arrayed on the substrate substrate 1, as shown in FIG. unit.
  • Each pixel unit includes: an open circuit repair structure 2, an OLED 3, and a pixel drive circuit 4.
  • the open circuit repair structure 2 is provided with a repair line 22, an orthographic projection of the repair line 22 on the base substrate 1 and an orthographic projection of the anode 301 of the OLED on the base substrate 1 partially or completely
  • the ground coincides to form a coincidence zone; the break repair point X is located in the coincidence zone.
  • the breaking repair point X since the pixel driving structure is relatively complicated, defects are easily generated, that is, the breaking repair point X, and the repairing line 22 has an overlapping portion with the OLED anode 301, and the overlapping portion is embodied in the above two
  • the break repair point X is placed in the overlap region, and the OLED anode 301 of any one of the two adjacent pixel units and the other pixel of the two adjacent pixel units can be made.
  • the drive of the unit is connected by the drain 4011 of the thin film transistor 401, thereby repairing the break repair point without affecting other components.
  • the driving thin film transistor 401 cannot communicate with the OLED anode. 301. Therefore, the pixel unit cannot emit light.
  • the pixel unit is referred to as a pixel unit to be repaired.
  • the pixel unit around it is an adjacent pixel unit.
  • the drain 4011 of the driving thin film transistor 401 in the adjacent pixel unit adjacent to the pixel unit to be repaired is connected to the OLED anode 301 in the pixel unit to be repaired by being connected to the repair line 22. In this way, the break repair point X is repaired, so that the line in the pixel unit to be repaired is restored, so that the pixel unit resumes illumination.
  • a plurality of pixel units are arranged on the base substrate 1 of the array substrate in an array arrangement.
  • the pixel unit is defined as The pixel unit is repaired, and the pixel unit around the pixel unit is defined as an adjacent pixel unit when arranged on the substrate base 1.
  • the pixel unit to be repaired and the adjacent pixel unit belong to the same pixel unit, and both have the same structure and function.
  • the partitioning is only for the purpose of clearly explaining the specific structure of the array substrate, that is, defining the target pixel unit that may require the repair of the broken circuit as the pixel unit to be repaired, and defining other pixel units adjacent to the pixel unit to be repaired as the phase.
  • a neighboring pixel unit in some embodiments of the present disclosure, when any one of the adjacent two pixel units is referred to as a pixel unit to be repaired, the other pixel unit of the adjacent two pixel units is called Is an adjacent pixel unit.
  • the anode 301 of the above OLED and the repair line 22 are located in the same pixel unit.
  • the array substrate having the pixel unit should be an OLED substrate, that is, each pixel unit of the array substrate is correspondingly provided with the OLED 3, and the pixel driving connected to the OLED anode 301. Circuit 4.
  • the OLED 3 may be any one of a top-emitting OLED, a bottom-emitting OLED, or a two-sided OLED.
  • FIG. 2 Only four arrays of pixel units are illustrated in FIG. 2, which are respectively used to emit light of the same or different colors, but those skilled in the art should understand that the embodiments of the present disclosure provide
  • the number of pixel units provided in the array substrate is not limited to the four shown, and may include more, and the color of the light emission thereof is not limited.
  • the pixel driving circuit 4 includes at least one thin film transistor; the at least one thin film transistor is a driving thin film transistor 401 and a switching thin film transistor 402.
  • the pixel driving circuit 4 of the OLED 3 may include at least one thin film transistor.
  • the thin film transistor is a driving thin film transistor 401; when the pixel driving circuit 4 includes a plurality of thin film transistors, the driving thin film transistor 401 refers to a drain 4011 connected to the OLED anode 301.
  • the thin film transistor, the drain electrode 4011 of the driving thin film transistor 401, and the OLED anode 301 may be electrically connected.
  • a repair line 22 connected to the drain 4011 of the driving thin film transistor 401 in an adjacent pixel unit is disposed between the repair line 22 and the OLED anode 301.
  • the insulating film layer is disposed and the orthographic projection of the repair line 22 on the base substrate 1 has a coincident region with the orthographic projection of the OLED anode 301 in the pixel unit to be repaired.
  • the insulating film layer between the repair line 22 and the OLED anode 301 can prevent a short circuit between the drain electrode 4011 and the anode when the drain electrode 4011 of the driving thin film transistor 401 is connected to the repair line 22 and contact the OLED anode 301.
  • a film layer for insulation is disposed between the OLED anode 301 and the repair line 22 in the pixel unit to be repaired, and the portion of the OLED anode 301 corresponding to the overlap region in the pixel unit to be repaired corresponds to the repair line 22.
  • the relative arrangement of the overlapping areas thus, when repairing the pixel unit to be repaired in which the pixel driving circuit is broken, the circuit repairing point X will be correspondingly located in the overlapping area.
  • the laser immersion soldering at the break repair point X is used to connect the OLED anode 301 and the repair line 22 in the pixel unit to be repaired, so that the OLED anode 301 and the repair line 22 in the pixel unit to be repaired can be used to realize the pixel to be repaired.
  • the pixel driving circuit 4 of the OLED 3 includes two thin film transistors, a switching thin film transistor 402 and a driving thin film transistor 401, and a gate 4021 and a gate of the switching thin film transistor 402.
  • the line 6 is connected, the source 4022 of the switching thin film transistor 402 is connected to the data line 7, and the drain 4023 of the switching thin film transistor 402 is connected to the gate 4013 of the driving thin film transistor 401 and the first plate C1 of the storage capacitor, respectively.
  • the source 4012 of the driving thin film transistor 401 is connected to the second plate C2 and the power supply line Vdd of the storage capacitor, respectively, and the drain 4011 of the driving thin film transistor 401 is connected to the anode 301 of the OLED.
  • the gate line 6 and the data line 7 may be made of a metal material such as copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), chromium (Cr), and tungsten (W).
  • a metal material such as copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), chromium (Cr), and tungsten (W).
  • the alloy materials or their alloy materials are prepared. For example, a single-layer metal wire made of copper, a laminated metal wire formed of Mo ⁇ Al ⁇ Mo, a laminated metal wire formed of Ti ⁇ Cu ⁇ Ti, and a laminated metal wire formed of MoTi ⁇ Cu.
  • the circuit repairing structure 2 in the pixel unit to be repaired can be effectively repaired to implement the pixel unit to be repaired.
  • the connection of the OLED anode 301 to the drain 4011 of the driving thin film transistor 401 in the adjacent pixel unit enables the OLED 3 in the pixel unit to be repaired to be driven by the driving thin film transistor 401 in the adjacent pixel unit, thereby ensuring the normality of the array substrate use.
  • each pixel unit in the array substrate is generally distributed in an array on the base substrate 1.
  • Each pixel unit in the same row is provided with a control signal by the same gate line 6, the same column.
  • Each pixel unit is supplied with a data signal from the same data line 7.
  • the gate line 6 is generally disposed in the same layer as the gate of the thin film transistor in the pixel unit
  • the data line 7 is generally disposed in the same layer as the source and drain of the thin film transistor in the pixel unit.
  • Each of the gate lines and each of the data lines are alternately formed into a grid structure such that one pixel unit is correspondingly located in one grid.
  • Each pixel unit may be a pixel unit to be repaired, or may be an adjacent pixel unit around the pixel unit to be repaired.
  • each of the pixel units generally includes a driving thin film transistor 401 disposed on the base substrate 1, and the driving thin film transistor 401 is disposed away from the base substrate. 1 side of OLED3.
  • the OLED 3 typically includes an oppositely disposed OLED anode 301 and OLED cathode 303, and an OLED luminescent layer 302 between the OLED anode 301 and the OLED cathode 303.
  • the OLED cathode 303 is usually formed of a metal material such as aluminum (Al)
  • the OLED anode 301 is usually formed of an Indium Tin Oxide (ITO) material.
  • the OLED light-emitting layer 303 may be a single-layer organic light-emitting layer, or a multilayer structure formed of a hole transport layer, an organic light-emitting layer, an electron transport layer, or the like.
  • the driving thin film transistor 401 may be any one of an oxide semiconductor thin film transistor, a polysilicon thin film transistor, or an amorphous silicon thin film transistor according to a working principle of the thin film transistor;
  • the driving thin film transistor 3 may be any one of a top gate thin film transistor or a bottom gate thin film transistor, which is not specifically limited in the embodiment of the present disclosure.
  • some embodiments of the present disclosure provide a top gate thin film transistor structure including an active layer 4014, a gate insulating layer 901, and a gate stacked on a base substrate 1. 4013 and an interlayer insulating layer 902.
  • the interlayer insulating layer 902 is respectively provided with a drain electrode 4011 and a source electrode 4012.
  • the drain electrode 0411 and the source electrode 4012 are respectively disposed in the interlayer insulating layer 902 and the gate insulating layer 901.
  • the via is connected to the active layer 4014.
  • the active layer 4014 may be an indium gallium zinc oxide (IGZO) layer;
  • the gate insulating layer 901 may be a single layer structure, such as a silicon nitride layer or a silicon oxide layer. It may also be a multilayer structure such as a laminate structure formed of a silicon nitride layer and a silicon oxide layer.
  • the drain 4011 of the driving thin film transistor 401 faces the surface of the OLED anode 301, and a passivation layer 903, a planarization layer 904, and a pixel defining layer 905 are generally stacked.
  • the OLED 3 is disposed in an open area of the pixel defining layer 905.
  • the passivation layer 903 may be a single layer structure, such as a silicon nitride layer or a silicon oxide layer, or may be a multilayer structure, such as a stacked structure formed of a silicon nitride layer and a silicon oxide layer.
  • the planarization layer 904 is generally a resin layer having a thickness of 1 ⁇ m to 4 ⁇ m prepared using an organic resin material.
  • the passivation layer 903 and the planarization layer 904 are provided with via holes, and the OLED anode 301 passes through the via holes provided in the planarization layer 904 and the passivation layer 903, and the drain of the driving thin film transistor 401. 4011 connection.
  • This enables the distance between the OLED anode 301 and the repair line 22 in the pixel unit to be repaired to be further shortened, so that the OLED anode 301 and the repair line 22 are welded more quickly during the repair process.
  • a passivation layer 903 and a planarization layer 904 are also present between the repair line 22 and the OLED anode 301 of the pixel unit to be repaired.
  • the adjacent pixel unit of the pixel unit to be repaired is the same row of adjacent pixel unit of the pixel unit to be repaired, that is, located in the pixel unit to be repaired.
  • the repair line 22 may be provided as an extension line of the drain 4011 of the driving thin film transistor 401 in the pixel unit of the adjacent row in the same column.
  • the repair line 22 and the drain 4011 of the driving thin film transistor 401 are integrally formed, which not only simplifies the fabrication process of the pixel repairing structure 2 to be repaired, but also facilitates the fabrication of the array substrate, and ensures the repair line 22 and the same column.
  • the drains 4011 of the driving thin film transistor 401 in the adjacent row pixel units are reliably connected.
  • the repair line 22 uses an extension line of the drain 4011 of the driving thin film transistor 401 in the adjacent row of pixel units.
  • the orthographic projection of the base substrate 1 coincides partially or wholly with the orthographic projection of the anode extension line 3011 of the OLED anode 301 in the pixel unit to be repaired, forming a coincident region.
  • the anode extension line 3011 of the OLED anode 301 refers to a portion of the OLED anode 301 corresponding to the extension line of the drain electrode 4011, that is, the anode extension line 3011 is a OLED anode 301. component.
  • the anode extension line 3011 of the OLED anode 301 in the pixel unit to be repaired, and the extension line of the drain 4011 of the driving thin film transistor 401 in the adjacent row of pixel units can be formed in the pixel to be repaired. While the unit interrupts the road repair structure 2, optimizing the space occupation of the open circuit repair structure 2 is beneficial to improving the space utilization ratio of the array substrate.
  • a groove 8 may be provided in a region of the planarization layer 904 corresponding to the break repair point X.
  • the groove depth of the groove 8 may be less than or equal to the thickness of the planarization layer 904.
  • the spacing is such that when the anode extension wire 3011 and the repair wire 22 are welded by laser deep-fusion welding, the anode extension wire 3011 and the repair wire 22 are reliably welded, thereby improving the anode extension wire 3011 and the repair wire 22 after repairing the connection.
  • the reliability of conduction is improved, that is, the repair reliability of the open circuit repair structure 5 is improved.
  • the gate line 6 is generally disposed in the same layer as the gate of the thin film transistor in the pixel unit
  • the data line 7 is generally disposed in the same layer as the source and drain of the thin film transistor in the pixel unit. And each gate line and each data line are interlaced.
  • the orthographic projection of the repair line 22 on the base substrate 1 intersects with the orthographic projection of the corresponding gate line 6 on the base substrate 1.
  • FIG. 4 and FIG. 5 of the present disclosure provide another arrangement of pixel units to be repaired and adjacent pixel units on the array substrate.
  • FIG. 4 is another schematic top view of an array substrate according to some embodiments of the present disclosure.
  • the array substrate shown in FIGS. 4 and 5 differs from the array substrate shown in FIGS. 2 and 3 mainly in the arrangement of the repair line 22 in the open circuit repair structure 2.
  • the other structures of the pixel unit such as the structure of the OLED or the driving thin film transistor, are the same as or similar to those in the array substrate shown in FIG. 2 and FIG. 3, and therefore will not be described again. See FIG. 2 and FIG. The description of the part of the array substrate shown in Fig. 3 is sufficient.
  • each adjacent two pixel units are adjacent column pixel units, that is, adjacent pixel units of the pixel unit to be repaired are pixel units to be repaired.
  • the peers are adjacent to the column of pixel units.
  • the repair line 22 in the open circuit repair structure 2 of the pixel unit to be repaired is connected to the drain 4011 of the driving thin film transistor 401 of the adjacent column pixel unit, so that the laser repair method is used in the open repair point X.
  • the OLED anode 301 of the repairing pixel unit After the OLED anode 301 of the repairing pixel unit is connected to the repair line 22, the OLED anode 301 and the repair line 22 of the pixel unit to be repaired can be used to drive the OLED anode 301 and the adjacent column pixel unit in the pixel unit to be repaired.
  • the connection of the drain electrode 4011 of the thin film transistor 401 is utilized to drive the OLED 3 in the pixel unit to be repaired by the driving thin film transistor 401 in the adjacent column pixel unit.
  • each pixel unit in the array substrate is generally distributed in an array on the base substrate, and each pixel unit in the same row is provided with a control signal by the same gate line 6 in the same column.
  • Each pixel unit is supplied with a data signal from the same data line 7.
  • the gate line 6 is generally disposed in the same layer as the gate of the thin film transistor in the pixel unit
  • the data line 7 is generally disposed in the same layer as the source and drain of the thin film transistor in the pixel unit.
  • Each of the gate lines and each of the data lines are alternately formed into a grid structure such that one pixel unit is correspondingly located in one grid.
  • Each pixel unit may be a pixel unit to be repaired, or may be an adjacent pixel unit around the pixel unit to be repaired.
  • FIG. 4 only four arrays of pixel units are shown in FIG. 4, which are respectively used to emit light of the same or different colors, but those skilled in the art should understand that embodiments of the present disclosure
  • the number of pixel units provided by the array substrate provided is not limited to the four shown, and may include more, and the color of the light emission thereof is not limited.
  • the data line 7 is generally disposed in the same layer as the source and drain of the thin film transistor in the pixel unit, when the repair line 22 is connected to the drain 4011 of the driving thin film transistor 401 in the adjacent column pixel unit
  • the repair line 22 needs to correspond to the area passing through the set data line 7. Therefore, in order to prevent the repair line 22 from being connected to the data line 7, some embodiments of the present disclosure insulate the repair line 22 from the gate 4013 of the driving thin film transistor 401 in the adjacent column of pixel units.
  • the gate 4013 of the driving thin film transistor 401 of each pixel unit is disposed on a side of the drain 4011 away from the OLED anode 301, and the gate An interlayer insulating layer 902 is provided between 4013 and the drain 4011.
  • the repair line 22 is provided in the same layer as the gate 4013 of the driving thin film transistor 401.
  • the repair line 22 and the gate electrode 4013 of the driving thin film transistor 401 can be formed in one patterning process, which is advantageous for simplifying the fabrication process of the pixel unit interrupt path repair structure 2 to improve the production efficiency of the array substrate.
  • the interlayer insulating layer 902 is provided with a via hole.
  • the drain electrode 4011 of the driving thin film transistor 401 in the adjacent column pixel unit passes through the via hole provided in the interlayer insulating layer 902. Connected to the repair line 22.
  • the orthographic projection of the repair line 22 on the base substrate crosses the orthographic projection of the corresponding data line 7 on the base substrate.
  • the drain electrode 4011 of the driving thin film transistor 401 is close to the surface of the OLED anode 301, and is generally provided with a passivation layer 903 and a planarization layer 904; the OLED anode 301 is disposed on the flat surface.
  • the via holes of the formation layer 904 and the passivation layer 903 are connected to the drain electrode 4011 of the driving thin film transistor 401.
  • the repair line 22 is insulated from the gate 4013 of the driving thin film transistor 401 in the adjacent column pixel unit, so that the repair line 22 and the pixel to be repaired
  • An interlayer insulating layer 902, a passivation layer 903, and a planarization layer 904 are sequentially present between the OLED anodes 301 in the cell.
  • the planarization layer 904 is corresponding to the region setting groove 8 of the circuit breaker repair point X; and the planarization layer 904 and the passivation layer 903 may also correspond to the circuit breaker repair point.
  • a groove 8 is provided in the area of X. At this time, the groove depth of the groove 8 is less than or equal to the total thickness of the planarization layer 904 plus the passivation layer 903.
  • the OLED anode 301 When depositing the OLED anode 301 in the pixel unit to be repaired, the OLED anode 301 covers the filling of the recess 8 , which can effectively shorten the OLED anode 301 and the repair line 22 in the pixel unit to be repaired in the corresponding region of the open repair point X.
  • the spacing between the OLED anode 301 and the repair line 22 in the pixel unit to be repaired by laser deep-fusion welding ensures that the OLED anode 301 and the repair line 22 in the pixel unit to be repaired are reliably soldered, thereby improving the OLED anode in the pixel unit to be repaired.
  • the conduction reliability of the 301 and the repair line 22 after repairing the connection that is, the repair reliability of the open circuit repair structure 2 is improved.
  • the surface of the planarization layer 904 away from the substrate 1 is generally provided with a pixel defining layer 905
  • the pixel defining layer 905 is generally made of an organic resin material.
  • a resin layer having a thickness of 1 ⁇ m to 3 ⁇ m was prepared.
  • the OLED 3 is usually disposed in the open area of the pixel defining layer 905.
  • the portion of the OLED anode 301 corresponding to the open repair point X is covered with the pixel defining layer 905 corresponding to the open circuit repairing structure of the pixel unit to be repaired, so as to utilize the pixel defining layer 905.
  • the insulation repair structure of the normal array substrate is insulated.
  • Some embodiments of the present disclosure further provide a display device including the above array substrate; the array substrate includes: a substrate substrate; and a plurality of pixel units arrayed on the substrate substrate, each The pixel unit includes: an open circuit repair structure, an OLED and a pixel driving circuit, wherein the circuit breaking repair structure is provided with a repair line; an orthographic projection of the repair line on the base substrate is opposite to an anode of the OLED The orthographic projections on the substrate substrate partially or completely overlap to form a coincident region; the break repair point is located in the coincident region.
  • the array substrate in the display device has the same advantages as the array substrate in the above embodiment, and details are not described herein.
  • the display device may be a product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, or a navigator.
  • a display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, or a navigator.

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Abstract

本公开提供一种阵列基板，包括：衬底基板；以及阵列排布在所述衬底基板上的多个像素单元，每个所述像素单元包括：断路修复结构、OLED及像素驱动电路，其中，所述断路修复结构设置有修复线；所述修复线在所述衬底基板上的正投影与所述OLED的阳极在所述衬底基板上的正投影部分地或全部地重合，形成重合区；断路修复点位于所述重合区。

Description

阵列基板及显示装置
本申请要求于2017年9月4日提交中国专利局、申请号为201721127658.4、名称为“一种阵基板及显示装置”的中国专利申请的优先权和权益，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板及显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称为OLED)，特别是有源矩阵有机发光二极管(Active-matrix Organic Light Emitting Diode，简称为AMOLED)，因具有高亮度、全视角、响应速度快以及可柔性显示等优点，已在显示领域得到广泛应用。
公开内容
第一方面本公开一些实施例提供了一种阵列基板，衬底基板；以及阵列排布在所述衬底基板上的多个像素单元，每个所述像素单元包括：断路修复结构、OLED及像素驱动电路，其中，所述断路修复结构设置有修复线；所述修复线在所述衬底基板上的正投影与所述OLED的阳极在所述衬底基板上的正投影部分地或全部地重合，形成重合区；断路修复点位于所述重合区。
在本公开一些实施例中，所述像素驱动电路包括至少一个薄膜晶体管；所述至少一个薄膜晶体管为驱动用薄膜晶体管，或所述至少一个薄膜晶体管为驱动用薄膜晶体管及开关用薄膜晶体管。
在本公开一些实施例中，每相邻两个像素单元中的任意一个像素单元中的修复线与所述相邻两个像素单元中的另一个像素单元的所述驱动用薄膜晶体管的漏极相连接。
在本公开一些实施例中，所述修复线与所述OLED的阳极之间设有绝缘膜层。
在本公开一些实施例中，当所述每相邻两个像素单元为同列相邻行像素 单元时，所述每相邻两个像素单元中的任意一个像素单元中的修复线为所述相邻两个所述多个像素单元中的另一个像素单元中的所述驱动用薄膜晶体管的漏极延伸线。
在本公开一些实施例中，每个像素单元中的驱动用薄膜晶体管的漏极延伸线在所述衬底基板的正投影，与该所述像素单元中的OLED阳极的延伸线在所述衬底基板的正投影部分地或全部地重合，形成重合区。
在本公开一些实施例中，所述每个像素单元中的驱动用薄膜晶体管的漏极延伸线靠近所述像素单元中的OLED的阳极延伸线的表面层叠设置有钝化层和平坦化层；所述平坦化层对应所述断路修复点的区域设置有凹槽，所述阳极延伸线覆盖所述凹槽。
在本公开一些实施例中，所述钝化层和所述平坦化层上设有过孔，所述驱动用薄膜晶体管的漏极通过所述过孔与所述LOED的阳极连接。
在本公开一些实施例中，当所述每相邻两个像素单元为同行相邻列像素单元时，所述每相邻两个像素单元中的任意一个像素单元中的修复线与所述相邻两个所述多个像素单元中的另一个像素单元中的所述驱动用薄膜晶体管的栅极同层绝缘设置，且所述修复线与所述驱动用薄膜晶体管的漏极之间设有层间绝缘层。
在本公开一些实施例中，所述层间绝缘层上设有过孔，所述驱动用薄膜晶体管的漏极通过所述过孔与所述修复线连接。
在本公开一些实施例中，每个像素单元中的修复线与所述像素单元中的OLED的阳极之间层叠设置有层间绝缘层、钝化层和平坦化层；所述平坦化层对应所述断路修复点的区域设有凹槽，所述像素单元中的OLED阳极覆盖所述凹槽；或所述平坦化层和所述钝化层对应所述断路修复点的区域均设有凹槽，所述像素单元中的OLED阳极覆盖所述凹槽。
在本公开一些实施例中，所述开关用薄膜晶体管的栅极与栅线连接，所述开关用薄膜晶体管的源极与所述数据线连接。
在本公开一些实施例中，同一行的所述多个像素单元对应同一条栅线；所述每个像素单元中的修复线在所述衬底基板的正投影，与对应栅线在所述衬底基板的正投影交叉。
另一方面，本公开一些实施例提供了一种显示装置，包括如第一方面所述的阵列基板，所述阵列基板包括：衬底基板；以及阵列排布在所述衬底基板上的多个像素单元，每个所述像素单元包括：断路修复结构、OLED及像素驱动电路，其中，所述断路修复结构设置有修复线；所述修复线在所述衬底基板上的正投影与所述OLED的阳极在所述衬底基板上的正投影部分地或全部地重合，形成重合区；断路修复点位于所述重合区。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为相关技术中像素驱动电路的电路原理图；
图2为本公开一些实施例提供的阵列基板的俯视示意图；
图3为图2所示的阵列基板沿折线A-A’的剖视示意图；
图4为本公开一些实施例提供的阵列基板的另一种俯视示意图；
以及
图5为图4所示的阵列基板沿折线B-B’的剖视示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
如前所述，在显示领域中，在采用有源矩阵有机发光二极管(Active-matrix Organic Light Emitting Diode，简称为AMOLED)的阵列基板上呈阵列状设置有多个像素单元，其中，同一行的各像素单元共用一条栅线，同一列的各像素单元共用一条数据线。每个像素单元包括 有机发光二极管(Organic Light Emitting Diode，简称为OLED)以及与OLED阳极连接的像素驱动电路。
所述像素驱动电路的电路原理图如图1所示，该像素驱动电路包括开关用薄膜晶体管T1、驱动用薄膜晶体管T2以及存储电容；开关用薄膜晶体管T1的栅极与栅线Gate连接，开关用薄膜晶体管T1的源极与数据线Data连接，开关用薄膜晶体管T1的漏极分别与驱动用薄膜晶体管T2的栅极以及存储电容的一个极板C1连接，驱动用薄膜晶体管T2的源极分别与存储电容的另一个极板C2以及电源线Vdd连接，驱动用薄膜晶体管T2的漏极与OLED的阳极连接。
然而，各像素单元中像素驱动电路的结构较为复杂，使得各像素单元所在阵列基板的制备工艺也较为复杂，导致在阵列基板的制备过程中，难免产生像素驱动电路中部分接线断路的缺陷，该出现的缺陷的位置即为断路点X’。此时对于具有复杂结构的像素驱动电路，采用现有的故障检测技术往往难以精确判断出其断路点X’的位置，因此无法对存在像素驱动电路断路缺陷的阵列基板进行有效修复。
基于上述问题，本公开实施例将结合其附图，对本公开实施例中的技术方案进行详细描述。
图2和图3为本公开一些实施例提供的阵列基板。参见图2和图3，本公开一些实施例提供的阵列基板包括衬底基板1；以及阵列排布在所述衬底基板1上的多个像素单元，如图2中示出了4个像素单元。每个像素单元包括：断路修复结构2、OLED 3及像素驱动电路4。所述断路修复结构2设置有修复线22，所述修复线22在所述衬底基板1上的正投影与所述OLED的阳极301在所述衬底基板1上的正投影部分地或全部地重合，形成重合区；断路修复点X位于所述重合区。
上述阵列基板，在制备过程中，由于其像素驱动结构较为复杂，容易产生缺陷，即断路修复点X，修复线22与OLED阳极301具有交叠部分，该交叠部分具体体现在上述二者在衬底基板上的正投影上，使断路修复点X处于重合区内，能够使得两个相邻的像素单元中任意一个像素单元的OLED阳极301与该两个相邻的像素单元中另一个像素单元的驱动用薄膜晶体管401 的漏极4011连接，从而对断路修复点进行修复，而不影响其他部件。
在本公开一些实施例中，在一个像素单元中，当驱动用薄膜晶体管401的漏极4011与OLED的阳极301之间出现断路，即断路点X’，该驱动用薄膜晶体管401无法连通OLED阳极301，因此该像素单元无法发光，此时，称该像素单元为待修复像素单元。那么，其周围的像素单元则为相邻像素单元。与待修复像素单元相邻的相邻像素单元中的驱动用薄膜晶体管401的漏极4011由于连接在修复线22上，因而将修复线22与待修复像素单元中的OLED阳极301连通。通过此方式对断路修复点X进行修复，使得待修复像素单元中的线路恢复连接，从而使该像素单元恢复发光。
目前，所有平板显示的驱动均采用矩阵驱动方式。多个像素单元以阵列排布的方式位于阵列基板的衬底基板1上，为方便描述，当多个像素单元中的一个像素单元的像素驱动电路4出现断路时，将该像素单元定义为待修复像素单元，将该像素单元在衬底基1上排布时四周的像素单元定义为相邻像素单元。
需要说明的是，上述待修复像素单元与相邻像素单元均属于同一种像素单元，二者具有相同的结构和功能。对其进行划分只是为了清楚说明阵列基板的具体结构，即，将可能需要断路修复的目标像素单元限定为待修复像素单元，而将相邻设在待修复像素单元四周的其他像素单元限定为相邻像素单元；在本公开一些实施例中，将相邻的两个像素单元中的任意一个像素单元称为待修复像素单元时，则将该相邻两个像素单元中的另一个像素单元称为相邻像素单元。
22可以理解的是，上述OLED的阳极301与修复线22位于同一个像素单元中。同时，由于像素单元中设有OLED阳极301，因此说明具有该像素单元的阵列基板应为OLED基板，即该阵列基板的各像素单元均对应设有OLED 3，以及与OLED阳极301连接的像素驱动电路4。
在本公开一些实施例中，OLED 3可以为顶发光OLED、底发光OLED或两面发光OLED中任意一种。
需要说明的是，在图2中仅示出了四个阵列排布的像素单元，其分别用于发出相同或者不同颜色的光，但本领域的技术人员应该理解的是，本公开实施例提供的阵列基板所设置的像素单元的数量不限于所示出的四个，可以包括更多，而且对其发光的颜色不做限制。
在本公开一些实施例中，所述像素驱动电路4包括至少一个薄膜晶体管；所述至少一个薄膜晶体管为驱动用薄膜晶体管401及开关用薄膜晶体管402。
在本公开一些实施例中，OLED 3的像素驱动电路4可以包括至少一个薄膜晶体管。当像素驱动电路4包括一个薄膜晶体管时，该薄膜晶体管为驱动用薄膜晶体管401；当像素驱动电路4包括多个薄膜晶体管时，驱动用薄膜晶体管401是指其漏极4011与OLED阳极301连接的薄膜晶体管，驱动用薄膜晶体管401的漏极4011与OLED阳极301也可以是电性连接。
在本公开一些实施例中，如图2和图3所示，设置一条与相邻像素单元中驱动用薄膜晶体管401的漏极4011连接的修复线22，在修复线22与OLED阳极301之间设置绝缘膜层且修复线22在衬底基板1的正投影，与待修复像素单元中的OLED阳极301在衬底基板1的正投影具有重合区。修复线22与OLED阳极301之间的绝缘膜层能够防止驱动用薄膜晶体管401的漏极4011与修复线22连接后，接触到OLED阳极301时，漏极4011与阳极之间形成短路。
换句话说，也就是使得待修复像素单元中的OLED阳极301与修复线22之间设有绝缘用的膜层，且待修复像素单元中的OLED阳极301对应重合区的部分与修复线22对应重合区的部分相对设置。这样在修复存在像素驱动电路断路缺陷的待修复像素单元时，其断路修复点X将对应位于该重合区。
在断路修复点X采用激光深熔焊接，将待修复像素单元中的OLED阳极301与修复线22连接导通，便能够利用待修复像素单元中的OLED阳极301和修复线22，实现待修复像素单元中OLED阳极301与相邻像素单元中驱动用薄膜晶体管401漏极4011的连接。
在本公开一些实施例中，请参阅图2和图3，OLED3的像素驱动电路4包括开关用薄膜晶体管402和驱动用薄膜晶体管401两个薄膜晶体管；开关用薄膜晶体管402的栅极4021与栅线6连接，开关用薄膜晶体管402的源极4022与数据线7连接，开关用薄膜晶体管402的漏极4023分别与驱动用薄膜晶体管401的栅极4013以及存储电容的第一极板C1连接，驱动用薄膜晶体管401的源极4012分别与存储电容的第二极板C2以及电源线Vdd连接，驱动用薄膜晶体管401的漏极4011与OLED的阳极301连接。
在本公开一些实施例中，栅线6和数据线7均可采用铜(Cu)、铝(Al)、钼(Mo)、钛(Ti)、铬(Cr)以及钨(W)等金属材料或其合金材料中的一种或几种制备形成。比如由铜制作的单层金属线，由Mo\Al\Mo形成的叠层金属线，由Ti\Cu\Ti形成的叠层金属线，以及由MoTi\Cu形成的叠层金属线等。
基于上述实施例提供的阵列基板，当像素单元中出现驱动电路断路时，即存在待修复像素单元的情况下，能够利用待修复像素单元中的断路修复结构2进行有效修复，实现待修复像素单元中OLED阳极301与相邻像素单元中驱动用薄膜晶体管401漏极4011的连接，使得待修复像素单元中的OLED3能被相邻像素单元中的驱动用薄膜晶体管401驱动，从而确保阵列基板的正常使用。
在本公开一些实施例中，请参阅图2，阵列基板中的各像素单元通常呈阵列状分布在衬底基板1上，同一行的各像素单元由同一条栅线6提供控制信号，同一列的各像素单元由同一条数据线7提供数据信号。
因此，栅线6一般与像素单元中薄膜晶体管的栅极同层设置，数据线7一般与像素单元中薄膜晶体管的源漏极同层设置。各栅线和各数据线交错形成网格状结构，使得一个像素单元对应位于一个网格中。各像素单元即可以为待修复像素单元，也可以为待修复像素单元周边的相邻像素单元。
在本公开一些实施例中，请参阅图2和图3，上述各像素单元通常 均包括有设在衬底基板1上的驱动用薄膜晶体管401，以及设在驱动用薄膜晶体管401远离衬底基板1一侧的OLED3。
OLED3通常包括相对设置的OLED阳极301和OLED阴极303，以及位于OLED阳极301和OLED阴极303之间的OLED发光层302。当OLED3为底发光OLED时，其OLED阴极303通常采用金属材料比如铝(Al)制作形成，OLED阳极301通常采用铟锡氧化物(Indium Tin Oxide，简称ITO)材料制作形成。另外，OLED发光层303可以采用单层的有机发光层，也可以采用由空穴传输层、有机发光层以及电子传输层等形成的多层结构。
在本公开一些实施例中，按照薄膜晶体管的工作原理划分，上述驱动用薄膜晶体管401通常可以为氧化物半导体薄膜晶体管、多晶硅薄膜晶体管或非晶硅薄膜晶体管中任意一种；按照薄膜晶体管中栅极的设置位置，上述驱动用薄膜晶体管3通常可以为顶栅薄膜晶体管或底栅薄膜晶体管中任意一种，本公开实施例对此并不作具体限定。
示例性的，请参阅图3，本公开一些实施例给出一种顶栅薄膜晶体管结构，该顶栅薄膜晶体管包括层叠设在衬底基板1的有源层4014、栅绝缘层901、栅极4013以及层间绝缘层902，层间绝缘层902上分别设置有漏极4011和源极4012，该漏极0411和源极4012分别通过对应设在层间绝缘层902和栅绝缘层901中的过孔与有源层4014连接。在本公开一些实施例中，有源层4014可以为铟镓锌氧化物层(indium gallium zinc oxide，简称IGZO)；栅绝缘层901可以为单层结构，比如氮化硅层或氧化硅层，也可以为多层结构，比如由氮化硅层和氧化硅层形成的叠层结构。
在本公开一些实施例中，请继续参阅图3，在驱动用薄膜晶体管401的漏极4011面向OLED阳极301的表面，一般层叠设置有钝化层903、平坦化层904以及像素界定层905，OLED3设在像素界定层905的开口区域。在本公开一些实施例中，钝化层903可以为单层结构，比如氮化硅层或氧化硅层，也可以为多层结构，比如由氮化硅层和氧化硅层形成的叠层结构；而平坦化层904一般为采用有机树脂材料制 备的厚度为1μm-4μm的树脂层。
本公开一些实施例中，钝化层903和平坦化层904上设有过孔，OLED阳极301通过设在平坦化层904和钝化层903的过孔，与驱动用薄膜晶体管401的漏极4011连接。这样能够使得待修复像素单元中的OLED阳极301与修复线22之间的距离进一步缩短，从而在修复过程中，更快地使OLED阳极301与修复线22熔接。此时对应在待修复像素单元的断路修复结构2中，其修复线22与待修复像素单元的OLED阳极301之间也同样存在有钝化层903和平坦化层904。
为了方便制作断路修复结构，本公开一些实施例中，请参阅图2，上述待修复像素单元的相邻像素单元为待修复像素单元的同列相邻行像素单元，也就是与待修复像素单元位于同一列且相邻两行中的任一个像素单元。此时，修复线22还可以设置为同列相邻行像素单元中驱动用薄膜晶体管401的漏极4011延伸线。这样修复线22与驱动用薄膜晶体管401的漏极4011一体成型，不仅能够简化待修复像素单元中断路修复结构2的制作工艺，方便于阵列基板的制作，而且，还能确保修复线22与同列相邻行像素单元中驱动用薄膜晶体管401的漏极4011可靠连接。
可以理解的是，在本公开一些实施例中，请继续参阅图2，修复线22采用同列相邻行像素单元中驱动用薄膜晶体管401的漏极4011延伸线时，该漏极4011的延伸线在衬底基板1的正投影，与待修复像素单元中的OLED阳极301的阳极延伸线3011在衬底基板的正投影部分地或全部地重合，形成重合区。
在本公开一些实施例中，如图3所示，OLED阳极301的阳极延伸线3011是指OLED阳极301与上述漏极4011延伸线相对应的一部分，即阳极延伸线3011是OLED阳极301的一组成部分。
在阵列基板有限的空间内，利用待修复像素单元中的OLED阳极301的阳极延伸线3011，以及同列相邻行像素单元中驱动用薄膜晶体管401的漏极4011延伸线，可以在形成待修复像素单元中断路修复结构2的同时，优化断路修复结构2的空间占用，有利于提高阵列基板 的空间利用率。
为了提高断路修复结构的修复可靠性，在本公开一些实施例中，参考图3所示，在平坦化层904对应断路修复点X的区域可以设置凹槽8。凹槽8的槽深可以小于或等于平坦化层904的厚度。这样在沉积形成待修复像素单元中的OLED阳极301的阳极延伸线3011时，阳极延伸线3011覆盖填满凹槽8，从而有效缩短阳极延伸线3011与修复线22在断路修复点X对应区域内的间距，以在采用激光深熔焊接方式将阳极延伸线3011与修复线22焊接时，确保阳极延伸线3011与修复线22可靠焊接，从而提高阳极延伸线3011与修复线22在修复连接后的导通可靠性，即提高断路修复结构5的修复可靠性。
在本公开一些实施例中，请继续参阅图2，由于栅线6一般与像素单元中薄膜晶体管的栅极同层设置，数据线7一般与像素单元中薄膜晶体管的源漏极同层设置，且各栅线和各数据线相互交错。当相邻像素单元选用同列相邻行像素单元时，修复线22在衬底基板1的正投影，与对应栅线6在衬底基板1的正投影交叉。
基于上述实施例，本公开图4和图5提供了阵列基板上的待修复像素单元及相邻像素单元的另一排布方式。
在本公开一些实施例中，如图4所示，图4为本公开一些实施例提供的阵列基板的另一种俯视示意图。
图4和图5所示的阵列基板与图2和图3所示的阵列基板的不同之处主要在于断路修复结构2中修复线22的设置。而像素单元的其他结构，比如OLED或驱动用薄膜晶体管等的结构，均与图2和图3所示阵列基板中的结构相同或相似，所以不再赘述，其相关之处参见图2和图3所示阵列基板的部分说明即可。
请参阅图4和图5，在本公开一些实施例提供的阵列基板中，每相邻两个像素单元为同行相邻列像素单元，即待修复像素单元的相邻像素单元为待修复像素单元的同行相邻列像素单元。待修复像素单元的断路修复结构2中的修复线22，与同行相邻列像素单元的驱动用薄膜晶体管401的漏极4011连接，这样在断路修复点X采用激光深熔焊 接的方式，将待修复像素单元的OLED阳极301与修复线22连接导通后，便能够利用待修复像素单元的OLED阳极301和修复线22，实现待修复像素单元中OLED阳极301与同行相邻列像素单元中驱动用薄膜晶体管401漏极4011的连接，从而利用同行相邻列像素单元中的驱动用薄膜晶体管401驱动待修复像素单元中的OLED3。
可以理解的是，如图4和图5所示，在此排布方式下，当任意一个像素单元的驱动用薄膜晶体管401的漏极4011与该像素单元中的OLED阳极301之间出现断路，即断路点X’时，该像素单元即为待修复像素单元，其周围的像素单元则为相邻像素单元。与上一像素单元排布方式相类似的，相邻像素单元的驱动用薄膜晶体管401的漏极4011由于与待修复像素单元中的修复线22连接，通过修复线22与待修复像素单元中的OLED阳极301连通，从而对断路进行修复，待修复像素单元重新发光。
在本公开一些实施例中，请参阅图4，阵列基板中的各像素单元通常呈阵列状分布在衬底基板上，同一行的各像素单元由同一条栅线6提供控制信号，同一列的各像素单元由同一条数据线7提供数据信号。在本公开一些实施例中，栅线6一般与像素单元中薄膜晶体管的栅极同层设置，数据线7一般与像素单元中薄膜晶体管的源漏极同层设置。各栅线和各数据线交错形成网格状结构，使得一个像素单元对应位于一个网格中。各像素单元即可以为待修复像素单元，也可以为待修复像素单元周边的相邻像素单元。
如图4所示，在图4中仅示出了四个阵列排布的像素单元，其分别用于发出相同或者不同颜色的光，但本领域的技术人员应该理解的是，本公开实施例提供的阵列基板所设置的像素单元的数量不限于所示出的四个，可以包括更多，而且对其发光的颜色不做限制。
在本公开一些实施例中，由于数据线7通常与像素单元中薄膜晶体管的源漏极同层设置，当修复线22与同行相邻列像素单元中驱动用薄膜晶体管401的漏极4011连接时，修复线22需要对应穿过设置数据线7的区域。因此，为了避免修复线22与数据线7连接，本公开一 些实施例将修复线22与同行相邻列像素单元中驱动用薄膜晶体管401的栅极4013同层绝缘设置。
示例性的，请参阅图4和图5，在本公开一些实施例中，各像素单元的驱动用薄膜晶体管401的栅极4013设在其漏极4011远离OLED阳极301的一侧，且栅极4013与漏极4011之间设有层间绝缘层902。修复线22与驱动用薄膜晶体管401的栅极4013同层绝缘设置。这样，修复线22和驱动用薄膜晶体管401的栅极4013可以在一次构图工艺中形成，有利于简化像素单元中断路修复结构2的制作工艺，以提高阵列基板的生产效率。
在本公开一些实施例中，层间绝缘层902上设有过孔，此时，同行相邻列像素单元中驱动用薄膜晶体管401的漏极4011通过设在层间绝缘层902的过孔，与修复线22连接。当数据线7与驱动用薄膜晶体管401的漏极4011同层设置时，修复线22在衬底基板的正投影，将与对应数据线7在衬底基板的正投影交叉。
在本公开一些实施例中，请继续参阅图5，驱动用薄膜晶体管401漏极4011靠近OLED阳极301的表面，一般层叠设置有钝化层903和平坦化层904；OLED阳极301通过设在平坦化层904和钝化层903的过孔，与驱动用薄膜晶体管401的漏极4011连接。此时对应在待修复像素单元的断路修复结构2中，因修复线22与同行相邻列像素单元中的驱动用薄膜晶体管401的栅极4013同层绝缘设置，使得修复线22与待修复像素单元中的OLED阳极301之间依次存在有层间绝缘层902、钝化层903以及平坦化层904。
为了提高断路修复结构的修复可靠性，在本公开一些实施例中，平坦化层904对应断路修复点X的区域设置凹槽8；也可以在平坦化层904和钝化层903对应断路修复点X的区域均设置凹槽8。此时，凹槽8的槽深小于或等于平坦化层904加钝化层903的总厚度。
在沉积形成待修复像素单元中的OLED阳极301时，该OLED阳极301覆盖填满凹槽8，这样能够有效缩短待修复像素单元中的OLED阳极301与修复线22在断路修复点X对应区域内的间距，以在采用 激光深熔焊接方式将其OLED阳极301与修复线22焊接时，确保待修复像素单元中的OLED阳极301与修复线22可靠焊接，从而提高待修复像素单元中的OLED阳极301与修复线22在修复连接后的导通可靠性，即提高断路修复结构2的修复可靠性。
请继续参阅图3和图5，在本公开一些实施例提供的阵列基板中，平坦化层904远离衬底基板1的表面通常设有像素界定层905，像素界定层905一般为采用有机树脂材料制备的厚度为1μm-3μm的树脂层。OLED3通常设在像素界定层905的开口区域，此时对应在待修复像素单元的断路修复结构中，其OLED阳极301对应断路修复点X的部分覆盖有像素界定层905，以便利用像素界定层905，对正常阵列基板的断路修复结构进行绝缘保护。
本公开一些实施例还提供了一种显示装置，所述显示装置包括上述阵列基板；所述阵列基板包括：衬底基板；以及阵列排布在所述衬底基板上的多个像素单元，每个所述像素单元包括：断路修复结构、OLED及像素驱动电路，其中，所述断路修复结构设置有修复线；所述修复线在所述衬底基板上的正投影与所述OLED的阳极在所述衬底基板上的正投影部分地或全部地重合，形成重合区；断路修复点位于所述重合区。所述显示装置中的阵列基板与上述实施例中的阵列基板具有的优势相同，此处不做赘述。
示例性的，本公开一些实施例提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或导航仪等具有显示功能的产品或部件。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本实用新型的具体实施方式，但本实用新型的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本实用新型揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本实用新型的保护范围之内。因此，本实用新型的保护范围应以所述权利要求的保护范围为准。

Claims (16)

  1. 一种阵列基板，包括：
    衬底基板；以及
    阵列排布在所述衬底基板上的多个像素单元，每个所述像素单元包括：断路修复结构、OLED及像素驱动电路，其中，
    所述断路修复结构设置有修复线；
    所述修复线在所述衬底基板上的正投影与所述OLED的阳极在所述衬底基板上的正投影部分地或全部地重合，形成重合区；
    断路修复点位于所述重合区。
  2. 根据权利要求1所述的阵列基板，其中，所述像素驱动电路包括至少一个薄膜晶体管；所述至少一个薄膜晶体管为驱动用薄膜晶体管，或所述至少一个薄膜晶体管为驱动用薄膜晶体管及开关用薄膜晶体管。
  3. 根据权利要求2所述的阵列基板，其中，每相邻两个像素单元中的任意一个像素单元中的修复线与所述相邻两个像素单元中的另一个像素单元的所述驱动用薄膜晶体管的漏极相连接。
  4. 根据权利要求1所述的阵列基板，其中，所述修复线与所述OLED的阳极之间设有绝缘膜层。
  5. 根据权利要求3所述的阵列基板，其中，当所述每相邻两个像素单元为同列相邻行像素单元时，所述每相邻两个像素单元中的任意一个像素单元中的修复线为所述相邻两个像素单元中的另一个像素单元中的所述驱动用薄膜晶体管的漏极延伸线。
  6. 根据权利要求5所述的阵列基板，其中，所述每相邻两个像素单元中的任意一个像素单元中的OLED阳极的延伸线在所述衬底基板的正投影，与所述相邻两个像素单元中的另一个像素单元中的驱动用薄膜晶体管的漏极延伸线在所述衬底基板的正投影部分地或全部地重合，形成重合区。
  7. 根据权利要求6所述的阵列基板，其中，所述每个像素单元中的驱动用 薄膜晶体管的漏极延伸线靠近所述像素单元中的OLED的阳极延伸线的表面层叠设置有钝化层和平坦化层；
    所述平坦化层对应所述断路修复点的区域设置有凹槽，所述阳极延伸线覆盖所述凹槽。
  8. 根据权利要求7所述的阵列基板，其中，所述钝化层和所述平坦化层上设有过孔，所述驱动用薄膜晶体管的漏极通过所述过孔与所述OLED的阳极连接。
  9. 根据权利要求3所述的阵列基板，其中，当所述每相邻两个像素单元为同行相邻列像素单元时，所述每相邻两个像素单元中的任意一个像素单元中的修复线与所述相邻两个像素单元中的另一个像素单元中的所述驱动用薄膜晶体管的栅极同层绝缘设置，且所述修复线与所述驱动用薄膜晶体管的漏极之间设有层间绝缘层。
  10. 根据权利要求9所述的阵列基板，其中，所述层间绝缘层上设有过孔，所述驱动用薄膜晶体管的漏极通过所述过孔与所述修复线连接。
  11. 根据权利要求9所述的阵列基板，其中，
    每个像素单元中的修复线与所述像素单元中的OLED的阳极之间层叠设置有层间绝缘层、钝化层和平坦化层；
    所述平坦化层对应所述断路修复点的区域设有凹槽，所述像素单元中的OLED阳极覆盖所述凹槽；或
    所述平坦化层和所述钝化层对应所述断路修复点的区域均设有凹槽，所述像素单元中的OLED阳极覆盖所述凹槽。
  12. 根据权利要求2所述的阵列基板，其中，所述开关用薄膜晶体管的栅极与栅线连接，所述开关用薄膜晶体管的源极与所述数据线连接。
  13. 根据权利要求1所述的阵列基板，其中，同一行的所述多个像素单元对应同一条栅线；
    所述每个像素单元中的修复线在所述衬底基板的正投影，与对应栅线在所 述衬底基板的正投影交叉。
  14. 根据权利要求1所述的阵列基板，其中，同一列的所述多个像素单元对应同一条数据线；
    所述修复线在所述衬底基板的正投影，与对应数据线在所述衬底基板的正投影交叉。
  15. 根据权利要求1所述的阵列基板，其中，所述多个像素单元中的OLED阳极对应所述断路修复点的部分覆盖有像素界定层。
  16. 一种显示装置，包括如权利要求1-15任一项所述的阵列基板，其中，所述阵列基板包括：
    衬底基板；以及
    阵列排布在所述衬底基板上的多个像素单元，每个所述像素单元包括：断路修复结构、OLED及像素驱动电路，其中，
    所述断路修复结构设置有修复线；所述修复线在所述衬底基板上的正投影与所述OLED的阳极在所述衬底基板上的正投影部分地或全部地重合，形成重合区；
    断路修复点位于所述重合区。
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