WO2019047584A1 - 像素补偿电路单元、像素电路和显示装置 - Google Patents

像素补偿电路单元、像素电路和显示装置 Download PDF

Info

Publication number
WO2019047584A1
WO2019047584A1 PCT/CN2018/091292 CN2018091292W WO2019047584A1 WO 2019047584 A1 WO2019047584 A1 WO 2019047584A1 CN 2018091292 W CN2018091292 W CN 2018091292W WO 2019047584 A1 WO2019047584 A1 WO 2019047584A1
Authority
WO
WIPO (PCT)
Prior art keywords
pixel compensation
node
control
circuit
switch tube
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2018/091292
Other languages
English (en)
French (fr)
Inventor
冯佑雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to JP2018562951A priority Critical patent/JP7203611B2/ja
Priority to EP18804219.6A priority patent/EP3680886A4/en
Priority to US16/305,426 priority patent/US11107405B2/en
Publication of WO2019047584A1 publication Critical patent/WO2019047584A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0465—Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a pixel compensation circuit unit, a pixel circuit, and a display device.
  • An active-matrix organic light emitting diode (AMOLED) display device has a wider viewing angle, a higher refresh rate, and a thinner size than a conventional liquid crystal display, so its application More and more extensive.
  • AMOLED display devices are provided with pixel compensation circuits, and voltage compensation circuits are widely used.
  • the data direct charge compensation circuit is suitable for small-sized products, especially high-PPI products, because of its low requirements on the storage capacitor Cst.
  • the present disclosure provides a pixel compensation circuit unit, a pixel circuit, and a display device, which can simplify the structure of the pixel compensation circuit.
  • a pixel compensation circuit unit includes: a reset power supply line, a reset control circuit, a bridge circuit, and at least two pixel compensation circuits, and the at least two pixel compensation circuits are connected to the reset power supply a line, the reset control circuit is connected to the reset power line at one end, the other end of the reset control circuit is connected to the bridge circuit, and the at least two pixel compensation circuits are connected by the bridge circuit.
  • the number of the pixel compensation circuits is two, and the two pixel compensation circuits comprise a first pixel compensation circuit and a second pixel compensation circuit; the bridge circuit is connected to the first node, and the first pixel compensation circuit is connected to a first node; the bridge circuit is coupled to the second node, and the second pixel compensation circuit is coupled to the second node.
  • the bridge circuit includes a first switch tube; a control pole of the first switch tube is connected to the first control power line, and a first pole of the first switch tube is connected to the first node, where the A second pole of a switch is coupled to the second node; the reset control circuit is coupled to the first node.
  • the bridge circuit includes a first switch tube; a control pole of the first switch tube is connected to the first control power line, and a first pole of the first switch tube is connected to the first node, where the A second pole of a switch transistor is coupled to the second node; the reset control circuit is coupled to the second node.
  • the bridge circuit includes a second switch tube and a third switch tube; a control pole of the second switch tube is connected to the first control power line, and a first pole of the second switch tube is connected to the first a second pole of the second switch is connected to the third node; a control pole of the third switch is connected to the first control power line, and a first pole of the third switch is connected to the node a third node, the second pole of the third switch is connected to the second node; the reset control circuit is connected to the third node.
  • the first switch transistor is a dual gate thin film transistor.
  • the reset control circuit includes a fourth switch tube; a control pole of the fourth switch tube is connected to the first control power line, and a first pole of the fourth switch tube is connected to the first node, The second pole of the fourth switching transistor is connected to the reset power line.
  • the reset control circuit includes a fourth switch tube; a control pole of the fourth switch tube is connected to the first control power line, and a first pole of the fourth switch tube is connected to the second node, The second pole of the fourth switching transistor is connected to the reset power line.
  • the reset control circuit includes a fourth switch tube; a control pole of the fourth switch tube is connected to the first control power line, and a first pole of the fourth switch tube is connected to the third node, The second pole of the fourth switching transistor is connected to the reset power line.
  • a pixel circuit including a plurality of pixel compensation circuit units that are sequentially disposed, and the pixel compensation circuit unit may employ the above-described pixel compensation circuit unit.
  • a display device including the above pixel circuit is provided.
  • FIG. 1 is a schematic structural diagram of a pixel compensation circuit unit according to an embodiment of the present disclosure
  • FIG. 2 is a detailed structural diagram of the pixel compensation circuit unit of FIG. 1;
  • FIG. 3 is a driving timing diagram of the pixel complementary circuit unit of FIG. 1;
  • FIG. 4 is a schematic structural diagram of a pixel compensation circuit unit according to another embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of a pixel compensation circuit unit according to still another embodiment of the present disclosure.
  • the pixel compensation circuit unit includes: a reset power line Vint, a reset control circuit 1, a bridge circuit 2, and at least two pixel compensations.
  • the pixel compensation circuit unit includes: a reset power line Vint, a reset control circuit 1, a bridge circuit 2, and at least two pixel compensations.
  • at least two pixel compensation circuits are connected to the reset power supply line Vint, one end of the reset control circuit 1 is connected to the reset power supply line Vint, the other end is connected to the bridge circuit 2, and at least two pixel compensation circuits are connected by the bridge circuit 2.
  • the number of pixel compensation circuits is two, and the two pixel compensation circuits include a first pixel compensation circuit 3 and a second pixel compensation circuit 4. That is, one of the pixel compensation circuits is the first pixel compensation circuit 3, and the other pixel compensation circuit is the second pixel compensation circuit 4.
  • the bridge circuit 2 is connected to the first node N1
  • the first pixel compensation circuit 3 is connected to the first node N1
  • the bridge circuit 2 is connected to the second node N2
  • the second pixel compensation circuit 4 is connected to the second node. N2, thereby achieving connection between the first pixel compensation circuit 3 and the second pixel compensation circuit 4 through the bridge circuit 2.
  • the first pixel compensation circuit is the previous row of pixel compensation circuits of the second pixel compensation circuit.
  • the second pixel compensation circuit is the current row of pixel compensation circuits.
  • the bridge circuit 2 can serve as a bridge connecting the first node N1 and the second node N2.
  • the pixel compensation circuit unit provided in this embodiment, at least two pixel compensation circuits are connected to the reset power line, and the reset control circuit is connected to the reset power line and the bridge circuit, and at least two pixel compensation circuits pass between The bridge circuit is connected.
  • the plurality of pixel compensation circuits share a reset power line, which reduces the number of reset power lines, thereby simplifying the structure of the pixel compensation circuit.
  • the bridge circuit 2 includes a first switch tube T1.
  • the control pole of the first switching transistor T1 is connected to the first control power supply line Sn1, the first pole of the first switching transistor T1 is connected to the first node N1, and the second pole of the first switching transistor T1 is connected to the second node N2.
  • the reset control circuit 1 is connected to the first node N1.
  • the first switching transistor T1 is a dual gate TFT, and the double gate TFT can effectively reduce leakage current, so that the voltages of the first node N1 and the second node N2 can be kept in a predetermined frame time. At the level, there is no problem that the voltages of the first node N1 and the second node N2 are excessively lowered due to excessive leakage current.
  • the reset control circuit 1 includes a fourth switch tube T4.
  • the control pole of the fourth switching transistor T4 is connected to the first control power supply line Sn1
  • the first pole of the fourth switching transistor T4 is connected to the first node N1
  • the second pole of the fourth switching transistor T4 is connected to the reset power supply line Vint.
  • the first pixel compensation circuit 3 includes a reset circuit, a charge control circuit, a drive circuit, a memory module, a switch module, and a light emitting device.
  • the reset circuit includes a fifth switching transistor T5.
  • the control electrode of the fifth switching transistor T5 is connected to the first control power supply line Sn1, the first electrode of the fifth switching transistor T5 is connected to the fourth node N4, and the second electrode of the fifth switching transistor T5 is connected to the reset power supply line Vint.
  • the charge control circuit includes a sixth switch tube T6 and a seventh switch tube T7.
  • the control pole of the sixth switching transistor T6 is connected to the second control power supply line Sn2, the first pole of the sixth switching transistor T6 is connected to the data line Data, and the second pole of the sixth switching transistor T6 is connected to the fifth node N5.
  • the control electrode of the seventh switch tube T7 is connected to the second control power line Sn2, the first pole of the seventh switch tube T7 is connected to the sixth node N6, and the second pole of the seventh switch tube T7 is connected to the first node N1.
  • the drive circuit includes an eighth switch tube T8.
  • the control pole of the eighth switch transistor T8 is connected to the first node N1
  • the first pole of the eighth switch transistor T8 is connected to the fifth node N5
  • the second pole of the eighth switch transistor T8 is connected to the sixth node N6.
  • the storage circuit includes a storage capacitor Cst.
  • the first end of the storage capacitor Cst is connected to the first voltage source, and the second end of the storage capacitor Cst is connected to the first node N1.
  • the voltage output by the first voltage source is VDD.
  • the switch circuit includes a ninth switch tube T9 and a tenth switch tube T10.
  • the control electrode of the ninth switch T9 is connected to the switch control power line EM, the first pole of the ninth switch T9 is connected to the first voltage source, and the second pole of the ninth switch T9 is connected to the fifth node N5.
  • the control electrode of the tenth switch tube T10 is connected to the switch control power line EM, the first pole of the tenth switch tube T10 is connected to the sixth point N6, and the second pole of the tenth switch tube T10 is connected to the fourth node N4.
  • a first end of the light emitting device is coupled to the fourth node N4, and a second end of the light emitting device is coupled to the second voltage source.
  • the light emitting device comprises an OLED, the first end of the OLED is connected to a fourth node N4, and the second end of the OLED is connected to a second voltage source.
  • the voltage output by the second voltage source is VSS.
  • the second pixel compensation circuit 4 is an adjacent row pixel compensation circuit of the first pixel compensation circuit 3.
  • Each functional module in the second pixel compensation circuit 4 is identical to each functional module in the first pixel compensation circuit 3, with the difference that the connection relationship is different.
  • the control electrode of the sixth switch tube T6 is connected to the third control power line Sn3, the first pole of the sixth switch tube T6 is connected to the data line Data, and the sixth switch tube T6
  • the second pole is connected to the fifth node N5;
  • the control pole of the seventh switch transistor T7 is connected to the third control power line Sn3, the first pole of the seventh switch transistor T7 is connected to the sixth node N6, and the seventh switch tube T7 is The two poles are connected to the second node N2.
  • the remaining structures in the second pixel compensation circuit 4 reference may be made to the first pixel compensation circuit 3, and the description thereof will not be repeated here.
  • the third control power line Sn3 is connected to the current gate drive circuit (Gate Driver on Array, GOA for short), and the current stage GOA passes the third control power line Sn3 to the sixth of the second pixel compensation circuit 4.
  • the switch tube T6 and the seventh switch tube T7 output a third control voltage; the upper stage GOA of the current stage GOA is connected to the second control power line Sn2, and the upper stage GOA passes the second control power line Sn2 to the first pixel compensation circuit 3.
  • the sixth switch tube T6 and the seventh switch tube T7 output a second control voltage; the upper two stages of the GOA of the current stage GOA are connected to the first control power line Sn1, and the upper two stages of the GOA are first through the first control power line Sn1.
  • the switch tube T1, the fourth switch tube T4, the fifth switch tube T5 of the first pixel compensation circuit 3, and the fifth switch tube T5 of the second pixel compensation circuit 4 output a first control voltage.
  • the first to eleventh switch tubes T1 to T11 are all TFTs.
  • FIG. 3 is a timing chart of driving of the pixel complementary circuit unit of FIG. 2.
  • FIG. 3 The driving process of the pixel compensation circuit will be described in detail below with reference to FIGS. 2 and 3.
  • the first control voltage output by the first control power line Sn1 is a low level voltage.
  • the first control power supply line Sn1 outputs a first control voltage to the control pole of the first switching transistor T1 to turn on the first switching transistor T1; the first control power supply line Sn1 outputs a first control voltage to the control electrode of the fourth switching transistor T4. So that the fourth switching transistor T4 is turned on; the first control power supply line Sn1 outputs a first control voltage to each of the first pixel compensation circuit 3 and the second pixel compensation circuit 4 to make the first pixel compensation Each of the fifth switching tube T5 of the circuit 3 and the second pixel compensation circuit 4 is turned on.
  • the reset power line Vint outputs a reset voltage to the first node N1 through the turned-on fourth switch tube T4 to reset the first node N1; the reset power line Vint passes through the turned-on fourth switch tube T4 and the first switch tube T1
  • the second node N2 outputs a reset voltage to reset the second node N2; the reset power line Vint outputs a reset voltage to the fourth node N4 through the fifth switch T5 of the first pixel compensation circuit 3 to implement the fourth node.
  • N4 performs resetting;
  • the reset power supply line Vint outputs a reset voltage to the fourth node N4 through the fifth switching transistor T5 of the second pixel compensation circuit 4 to implement resetting of the fourth node N4.
  • the reset voltage is a low level voltage, and after reset, the voltages of the first node N1, the second node N2, and the two fourth nodes N4 are all low level voltages.
  • the second control voltage output by the second control power line Sn2 is a low level voltage.
  • the second control power line Sn2 outputs a second control voltage to the sixth switch tube T6 in the first pixel compensation circuit 3 to turn on the sixth switch tube T6.
  • the second control power line Sn2 outputs a second control voltage to the seventh switch tube T7 of the first pixel compensation circuit 3 to turn on the seventh switch tube T7.
  • the eighth switch tube T8 functions as a diode, and the data line Data charges the first node N1 through the opened sixth switch tube T6 and the eighth switch tube T8, and the energy storage In the storage capacitor Cst, the voltage of the first node N1 is Vdata+Vth, where Vdata is the data voltage output by the data line Data, and Vth is the threshold voltage of the eighth switching transistor T8.
  • the charging process of the first pixel compensation circuit 3 is completed in the first charging phase.
  • the third control voltage output by the third control power line Sn3 is a low level voltage.
  • the third control power supply line Sn3 outputs a third control voltage to the sixth switching transistor T6 of the second pixel compensation circuit 4 to turn on the sixth switching transistor T6.
  • the third control power line Sn3 outputs a third control voltage to the seventh switch tube T7 of the second pixel compensation circuit 4 to turn on the seventh switch tube T7.
  • the eighth switch tube T8 functions as a diode, and the data line Data charges the second node N2 through the opened sixth switch tube T6 and the eighth switch tube T8, and the energy storage In the storage capacitor Cst, the voltage of the second node N2 is Vdata+Vth, where Vdata is the data voltage output by the data line Data, and Vth is the threshold voltage of the eighth switching transistor T8.
  • the charging process of the second pixel compensation circuit 4 is completed in the first charging phase.
  • the switch control voltage output by the switch control power line EM is a low level voltage.
  • the switch control power supply line EM outputs a switch control voltage to the control terminals of the ninth switch tube T9 and the tenth switch tube T10 in the first pixel compensation circuit 3 to turn on the ninth switch tube T9 and the tenth switch tube T10.
  • the switch control power supply line EM outputs a switch control voltage to the control terminals of the ninth switch T9 and the tenth switch T10 of the second pixel compensation circuit 4 to turn on the ninth switch T9 and the tenth switch T10.
  • the drive current is not affected by Vth, which improves the uniformity of pixel display.
  • the OLEDs in the first pixel compensation circuit 3 and the second pixel compensation circuit 4 emit light at the same time.
  • the voltage VDD output by the first voltage source is a high level signal
  • the VSS output by the second voltage source is a low level signal.
  • the first pixel compensation circuit 3 since the switch control voltage output by the switch control power supply line EM is a high level voltage, the first pixel compensation circuit 3
  • the ninth switch tube T9 and the tenth switch tube T10 are turned off and the ninth switch tube T9 and the tenth switch tube T10 of the second pixel compensation circuit 4 are turned off.
  • the pixel compensation circuit unit In the technical solution of the pixel compensation circuit unit provided in this embodiment, at least two pixel compensation circuits are connected to the reset power line, the reset control circuit is connected to the reset power line and the bridge circuit, and at least two pixel compensation circuits are bridged
  • the plurality of pixel compensation circuits share a reset power line, which reduces the number of reset power lines, thereby simplifying the structure of the pixel compensation circuit.
  • the first pixel compensation circuit and the second pixel compensation circuit share the switch control signal output by the switch control power supply line, thereby simplifying the signal input in the layout.
  • the voltage output by the first control power line Sn1 is used as the first control voltage of the first pixel compensation circuit and the second pixel compensation circuit to reset the first pixel compensation circuit and the second pixel compensation circuit. This allows the GOA to output a control voltage to the two pixel compensation circuits, thereby reducing the number of stages of the GOA.
  • FIG. 4 is a detailed structural diagram of a pixel compensation circuit unit according to another embodiment of the present disclosure.
  • the pixel compensation circuit unit in this embodiment is different from the above embodiment in that the bridge circuit 2 includes a first switch tube T1.
  • the control pole of the first switching transistor T1 is connected to the first control power supply line Sn1
  • the first pole of the first switching transistor T1 is connected to the first node N1
  • the second pole of the first switching transistor T2 is connected to the second node N2.
  • the reset control circuit 1 is connected to the second node N2.
  • the first switching transistor T1 is a double-gate TFT
  • the double-gate TFT can effectively reduce leakage current, so that the voltages of the first node N1 and the second node N2 can be kept constant for one frame time.
  • the level there is no problem that the voltages of the first node N1 and the second node N2 are excessively reduced due to excessive leakage current.
  • the reset control circuit 1 includes a fourth switching transistor T4.
  • the control pole of the fourth switching transistor T4 is connected to the first control power supply line Sn1, the first pole of the fourth switching transistor T4 is connected to the second node N2, and the second pole of the fourth switching transistor T4 is connected to the reset power supply line Vint.
  • the first control voltage output by the first control power line Sn1 is a low level voltage.
  • the first control power supply line Sn1 outputs a first control voltage to the control pole of the first switching transistor T1 to turn on the first switching transistor T1; the first control power supply line Sn1 outputs a first control voltage to the control electrode of the fourth switching transistor T4. So that the fourth switching transistor T4 is turned on; the first control power supply line Sn1 outputs a first control voltage to each of the first pixel compensation circuit 3 and the second pixel compensation circuit 4 to make the first pixel compensation Each of the fifth switching tube T5 of the circuit 3 and the second pixel compensation circuit 4 is turned on.
  • the reset power line Vint outputs a reset voltage to the second node N2 through the turned-on fourth switch tube T4 to reset the second node N2; the reset power line Vint passes through the turned-on fourth switch tube T4 and the first switch tube T1
  • the first node N1 outputs a reset voltage to reset the first node N1; the reset power line Vint outputs a reset voltage to the fourth node N4 through the fifth switch T5 of the first pixel compensation circuit 3 to implement the fourth node.
  • N4 performs resetting;
  • the reset power supply line Vint outputs a reset voltage to the fourth node N4 through the fifth switching transistor T5 of the second pixel compensation circuit 4 to implement resetting of the fourth node N4.
  • the reset voltage is a low level voltage, and after reset, the voltages of the first node N1, the second node N2, and the two fourth nodes N4 are all low level voltages.
  • the pixel compensation circuit unit In the technical solution of the pixel compensation circuit unit provided in this embodiment, at least two pixel compensation circuits are connected to the reset power line, the reset control circuit is connected to the reset power line and the bridge circuit, and at least two pixel compensation circuits are bridged
  • the plurality of pixel compensation circuits share a reset power line, which reduces the number of reset power lines, thereby simplifying the structure of the pixel compensation circuit.
  • the first pixel compensation circuit and the second pixel compensation circuit share the switch control signal output by the switch control power supply line, thereby simplifying the signal input in the layout.
  • the pixel compensation circuit unit provided in this embodiment is different from the above embodiments in that the bridge circuit 2 includes a second switch. Tube T2 and third switch tube T3.
  • the control pole of the second switch T2 is connected to the first control power line Sn1, the first pole of the second switch T2 is connected to the first node N1, and the second pole of the second switch T2 is connected to the third node N3
  • the third pole of the third switch tube T3 is connected to the third node N3, the second pole of the third switch tube T3 is connected to the second node N2;
  • the reset control circuit 1 is connected to the third node N3.
  • the second switching transistor T2 and the third switching transistor T3 are both single-gate TFTs, and the effect of the two single-gate TFTs reaching one double-gate TFT.
  • a double-gate TFT formed by two single-gate TFTs can effectively reduce leakage current, so that the voltages of the first node N1 and the second node N2 can be maintained at a certain level within one frame time without occurrence of leakage current.
  • the reset control circuit 1 includes a fourth switching transistor T4.
  • the control pole of the fourth switching transistor T4 is connected to the first control power supply line Sn1, the first pole of the fourth switching transistor T4 is connected to the third node N3, and the second pole of the fourth switching transistor T4 is connected to the reset power supply line Vint.
  • the first control voltage output by the first control power line Sn1 is a low level voltage.
  • the first control power supply line Sn1 outputs a first control voltage to the control electrode of the second switching transistor T2 to turn on the second switching transistor T2; the first control power supply line Sn1 outputs a first control voltage to the control electrode of the third switching transistor T3.
  • the third switch tube T3 is turned on; the first control power line Sn1 outputs a first control voltage to the control electrode of the fourth switch tube T4 to turn on the fourth switch tube T4; the first control power line Sn1 is turned to the first pixel
  • Each of the fifth switching tube T5 of the compensation circuit 3 and the second pixel compensation circuit 4 outputs a first control voltage to turn on each of the fifth switching tube T5 of the first pixel compensation circuit 3 and the second pixel compensation circuit 4.
  • the reset power line Vint outputs a reset voltage to the first node N1 through the turned-on fourth switch tube T4 and the second switch tube T2 to reset the first node N1; the reset power line Vint passes through the turned-on fourth switch tube T4 and The third switch T3 outputs a reset voltage to the second node N2 to reset the second node N2; the reset power line Vint outputs a reset voltage to the fourth node N4 through the fifth switch T5 of the first pixel compensation circuit 3, To reset the fourth node N4; the reset power line Vint outputs a reset voltage to the fourth node N4 through the fifth switching transistor T5 of the second pixel compensation circuit 4 to implement resetting of the fourth node N4.
  • the reset voltage is a low level voltage, and after reset, the voltages of the first node N1, the second node N2, and the two fourth nodes N4 are all low level voltages.
  • the pixel compensation circuit unit In the technical solution of the pixel compensation circuit unit provided in this embodiment, at least two pixel compensation circuits are connected to the reset power line, the reset control circuit is connected to the reset power line and the bridge circuit, and at least two pixel compensation circuits are bridged
  • the plurality of pixel compensation circuits share a reset power line, which reduces the number of reset power lines, thereby simplifying the structure of the pixel compensation circuit.
  • the first pixel compensation circuit and the second pixel compensation circuit share the switch control signal output by the switch control power supply line, thereby simplifying the signal input in the layout.
  • Embodiments of the present disclosure provide a pixel circuit including a plurality of pixel compensation circuit units that are sequentially disposed.
  • the pixel compensation circuit unit may include any one of the pixel circuit compensation units in the above embodiments.
  • the pixel circuit In the technical solution of the pixel circuit provided in this embodiment, at least two pixel compensation circuits are connected to the reset power line, the reset control circuit is connected to the reset power line and the bridge circuit, and at least two pixel compensation circuits are connected by a bridge circuit.
  • the plurality of pixel compensation circuits share a reset power line, which reduces the number of reset power lines, thereby simplifying the structure of the pixel compensation circuit.
  • the first pixel compensation circuit and the second pixel compensation circuit share the switch control signal output by the switch control power supply line, thereby simplifying the signal input in the layout.
  • Embodiments of the present disclosure provide a display device including the above pixel circuit.
  • At least two pixel compensation circuits are connected to the reset power line, the reset control circuit is connected to the reset power line and the bridge circuit, and at least two pixel compensation circuits are connected by a bridge circuit.
  • the plurality of pixel compensation circuits share a reset power line, which reduces the number of reset power lines, thereby simplifying the structure of the pixel compensation circuit.
  • the first pixel compensation circuit and the second pixel compensation circuit share a switch control signal output by the switch control power supply line, thereby simplifying signal input on the layout.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Control Of El Displays (AREA)

Abstract

一种像素补偿电路单元、像素电路和显示装置。像素补偿电路单元包括：复位电源线（Vint）、复位控制电路（1）、桥接电路（2）和至少二个像素补偿电路，至少二个像素补偿电路连接至复位电源线（Vint），复位控制电路（1）连接至复位电源线（Vint）和桥接电路（2），至少二个像素补偿电路之间通过桥接电路（2）连接。多个像素补偿电路公用一条复位电源线（Vint），减少了复位电源线（Vint）的数量，从而简化了像素补偿电路的结构。

Description

像素补偿电路单元、像素电路和显示装置
相关申请的交叉引用
本申请要求2017-9-8日提交给中国专利局的第201710805843.2号专利申请的优先权，其全部内容通过引用合并于此。
技术领域
本公开涉及显示技术领域，特别涉及一种像素补偿电路单元、像素电路和显示装置。
背景技术
有源矩阵有机发光二极体(Active-matrix organic light emitting diode，简称AMOLED)显示装置与传统的液晶显示器相比，具有更宽的视角、更高的刷新率和更薄的尺寸，因此其应用越来越广泛。
目前，AMOLED显示装置均设置有像素补偿电路，而应用较为广泛的是电压式补偿电路。而在电压式补偿电路中，数据(data)直充式补偿电路由于对存储电容Cst的要求较低，因此较适合应用在小尺寸产品，特别是高PPI产品中。
发明内容
本公开提供一种像素补偿电路单元、像素电路和显示装置，能够简化像素补偿电路的结构。
根据本公开的一个方面，提供一种像素补偿电路单元，其包括：复位电源线、复位控制电路、桥接电路和至少二个像素补偿电路，所述至少二个像素补偿电路连接至所述复位电源线，所述复位控制电路一端连接至所述复位电源线，所述复位控制电路的另一端连接至所述桥接电路，所述至少二个像素补偿电路之间通过所述桥接电路连接。
可选地，所述像素补偿电路的数量为二个，二个像素补偿电路包括第 一像素补偿电路和第二像素补偿电路；所述桥接电路连接至第一节点，第一像素补偿电路连接至第一节点；所述桥接电路连接至第二节点，第二像素补偿电路连接至第二节点。
可选地，所述桥接电路包括第一开关管；所述第一开关管的控制极连接至第一控制电源线，所述第一开关管的第一极连接至第一节点，所述第一开关管的第二极连接至第二节点；所述复位控制电路连接至第一节点。
可选地，所述桥接电路包括第一开关管；所述第一开关管的控制极连接至第一控制电源线，所述第一开关管的第一极连接至第一节点，所述第一开关管的第二极连接至第二节点；所述复位控制电路连接至第二节点。
可选地，所述桥接电路包括第二开关管和第三开关管；所述第二开关管的控制极连接至第一控制电源线，所述第二开关管的第一极连接至第一节点，所述第二开关管的第二极连接至第三节点；所述第三开关管的控制极连接至所述第一控制电源线，所述第三开关管的第一极连接至所述第三节点，所述第三开关管的第二极连接至第二节点；所述复位控制电路连接至第三节点。
可选地，所述第一开关管为双栅薄膜晶体管。
可选地，所述复位控制电路包括第四开关管；所述第四开关管的控制极连接至第一控制电源线，所述第四开关管的第一极连接至第一节点，所述第四开关管的第二极连接至复位电源线。
可选地，所述复位控制电路包括第四开关管；所述第四开关管的控制极连接至第一控制电源线，所述第四开关管的第一极连接至第二节点，所述第四开关管的第二极连接至复位电源线。
可选地，所述复位控制电路包括第四开关管；所述第四开关管的控制极连接至第一控制电源线，所述第四开关管的第一极连接至第三节点，所述第四开关管的第二极连接至复位电源线。
根据本公开的一个方面，提供一种像素电路，其包括依次设置的多个像素补偿电路单元，所述像素补偿电路单元可采用上述像素补偿电路单元。
根据本公开的一个方面，提供一种显示装置，其包括上述像素电路。
附图说明
图1为本公开实施例提供的一种像素补偿电路单元的结构示意图；
图2为图1的像素补偿电路单元的详细结构示意图；
图3为图1的像素补充电路单元的驱动时序图；
图4为本公开另一个实施例的一种像素补偿电路单元的详细结构示意图；以及
图5为本公开又一个实施例的一种像素补偿电路单元的详细结构示意图。
具体实施方式
为使本领域的技术人员更好地理解本公开的技术方案，下面结合附图对本公开提供的像素补偿电路单元、像素电路和显示装置进行详细描述。
图1为本公开实施例的一种像素补偿电路单元的结构示意图，如图1所示，该像素补偿电路单元包括：复位电源线Vint、复位控制电路1、桥接电路2和至少二个像素补偿电路，至少二个像素补偿电路连接至复位电源线Vint，复位控制电路1一端连接至复位电源线Vint，另一端连接至桥接电路2，至少二个像素补偿电路之间通过桥接电路2连接。
本一个实施例中，像素补偿电路的数量为二个，二个像素补偿电路包括第一像素补偿电路3和第二像素补偿电路4。也就是说，其中一个像素补偿电路为第一像素补偿电路3，另一个像素补偿电路为第二像素补偿电路4。如图2所示，桥接电路2连接至第一节点N1，第一像素补偿电路3连接至第一节点N1，桥接电路2连接至第二节点N2，第二像素补偿电路4连接至第二节点N2，从而实现了第一像素补偿电路3和第二像素补偿电路4之间通过桥接电路2连接。本实施例中，第一像素补偿电路为第二像素补偿电路的上一行像素补偿电路，例如，若第一像素补偿电路为上一行像素补偿电路时，第二像素补偿电路为当前行像素补偿电路。本实施例中，桥接电路2可以作为连接第一节点N1和第二节点N2的桥梁。
根据本实施例提供的像素补偿电路单元的技术方案中，至少二个像素补偿电路连接至复位电源线，复位控制电路连接至所述复位电源线和桥接电路，至少二个像素补偿电路之间通过桥接电路连接，本实施例中多个像素补偿电路公用一条复位电源线，减少了复位电源线的数量，从而简化了 像素补偿电路的结构。
图2为图1的像素补偿电路单元的详细结构示意图，如图2所示，在本实施例的像素补偿电路单元中，桥接电路2包括第一开关管T1。第一开关管T1的控制极连接至第一控制电源线Sn1，第一开关管T1的第一极连接至第一节点N1，第一开关管T1的第二极连接至第二节点N2。复位控制电路1连接至第一节点N1。本实施例中，例如，第一开关管T1为双栅TFT，采用双栅TFT可有效减少漏电流，从而使得第一节点N1和第二节点N2的电压能够在一帧画面时间内保持在预定电平，不会出现由于漏电流过大而导致的第一节点N1和第二节点N2的电压降低过大的问题。
本实施例中，复位控制电路1包括第四开关管T4。第四开关管T4的控制极连接至第一控制电源线Sn1，第四开关管T4的第一极连接至第一节点N1，第四开关管T4的第二极连接至复位电源线Vint。
本实施例中，第一像素补偿电路3包括复位电路、充电控制电路、驱动电路、存储模块、开关模块和发光器件。
复位电路包括第五开关管T5。第五开关管T5的控制极连接至第一控制电源线Sn1，第五开关管T5的第一极连接至第四节点N4，第五开关管T5的第二极连接至复位电源线Vint。
充电控制电路包括第六开关管T6和第七开关管T7。第六开关管T6的控制极连接至第二控制电源线Sn2，第六开关管T6的第一极连接至数据线Data，第六开关管T6的第二极连接至第五节点N5。第七开关管T7的控制极连接至第二控制电源线Sn2，第七开关管T7的第一极连接至第六节点N6，第七开关管T7的第二极连接至第一节点N1。
驱动电路包括第八开关管T8。第八开关管T8的控制极连接至第一节点N1，第八开关管T8的第一极连接至第五节点N5，第八开关管T8的第二极连接至第六节点N6。
存储电路包括存储电容Cst。存储电容Cst的第一端连接至第一电压源，存储电容Cst的第二端连接至第一节点N1。其中，第一电压源输出的电压为VDD。
开关电路包括第九开关管T9和第十开关管T10。第九开关管T9的控制极连接至开关控制电源线EM，第九开关管T9的第一极连接至第一电压 源，第九开关管T9的第二极连接至第五节点N5。第十开关管T10的控制极连接至开关控制电源线EM，第十开关管T10的第一极连接至第六点N6，第十开关管T10的第二极连接至第四节点N4。
发光器件的第一端连接至第四节点N4，发光器件的第二端连接至第二电压源。例如，发光器件包括OLED，OLED的第一端连接至第四节点N4，OLED的第二端连接至第二电压源。第二电压源输出的电压为VSS。
本实施例中，第二像素补偿电路4为第一像素补偿电路3的相邻行像素补偿电路。第二像素补偿电路4中各个功能模块和第一像素补偿电路3中的各个功能模块相同，区别在于连接关系不同。具体地，在第二像素补偿电路4中，第六开关管T6的控制极连接至第三控制电源线Sn3，第六开关管T6的第一极连接至数据线Data，第六开关管T6的第二极连接至第五节点N5；第七开关管T7的控制极连接至第三控制电源线Sn3，第七开关管T7的第一极连接至第六节点N6，第七开关管T7的第二极连接至第二节点N2。对第二像素补偿电路4中其余结构的描述可参见第一像素补偿电路3，此处不再重复描述。
本实施例中，第三控制电源线Sn3与当前级栅极驱动电路(Gate Driver on Array，简称GOA)连接，当前级GOA通过第三控制电源线Sn3向第二像素补偿电路4中的第六开关管T6和第七开关管T7输出第三控制电压；当前级GOA的上一级GOA与第二控制电源线Sn2连接，上一级GOA通过第二控制电源线Sn2向第一像素补偿电路3中的第六开关管T6和第七开关管T7输出第二控制电压；当前级GOA的上两级GOA与第一控制电源线Sn1连接，上两级GOA通过第一控制电源线Sn1向第一开关管T1、第四开关管T4、第一像素补偿电路3中的第五开关管T5和第二像素补偿电路4中的第五开关管T5输出第一控制电压。
本实施例中，第一开关管T1至第十一开关管T11均为TFT。
图3为图2的像素补充电路单元的驱动时序图。下面结合图2和图3，对像素补偿电路的驱动过程进行详细描述。
在复位阶段T1，第一控制电源线Sn1输出的第一控制电压为低电平电压。第一控制电源线Sn1向第一开关管T1的控制极输出第一控制电压，以使第一开关管T1开启；第一控制电源线Sn1向第四开关管T4的控制极输 出第一控制电压，以使第四开关管T4开启；第一控制电源线Sn1向第一像素补偿电路3和第二像素补偿电路4中的各第五开关管T5输出第一控制电压，以使第一像素补偿电路3和第二像素补偿电路4中的各第五开关管T5均开启。复位电源线Vint通过开启的第四开关管T4向第一节点N1输出复位电压，以实现对第一节点N1进行复位；复位电源线Vint通过开启的第四开关管T4和第一开关管T1向第二节点N2输出复位电压，以实现对第二节点N2进行复位；复位电源线Vint通过第一像素补偿电路3的第五开关管T5对第四节点N4输出复位电压，以实现对第四节点N4进行复位；复位电源线Vint通过第二像素补偿电路4的第五开关管T5对第四节点N4输出复位电压，以实现对第四节点N4进行复位。其中，复位电压为低电平电压，则复位后，第一节点N1、第二节点N2和两个第四节点N4的电压均为低电平电压。
在第一充电阶段T2，第二控制电源线Sn2输出的第二控制电压为低电平电压。第二控制电源线Sn2向第一像素补偿电路3中的第六开关管T6输出第二控制电压，以使第六开关管T6开启。第二控制电源线Sn2向第一像素补偿电路3中的第七开关管T7输出第二控制电压，以使第七开关管T7开启。在开启的第七开关管T7的作用下，第八开关管T8起到二极管的作用，数据线Data通过开启的第六开关管T6和第八开关管T8对第一节点N1进行充电，能量存储在存储电容Cst中，以使第一节点N1的电压为Vdata+Vth，其中，Vdata为数据线Data输出的数据电压，Vth为第八开关管T8的阈值电压。本实施例中，在第一充电阶段完成了对第一像素补偿电路3的充电过程。
在第二充电阶段T3，第三控制电源线Sn3输出的第三控制电压为低电平电压。第三控制电源线Sn3向第二像素补偿电路4中的第六开关管T6输出第三控制电压，以使第六开关管T6开启。第三控制电源线Sn3向第二像素补偿电路4中的第七开关管T7输出第三控制电压，以使第七开关管T7开启。在开启的第七开关管T7的作用下，第八开关管T8起到二极管的作用，数据线Data通过开启的第六开关管T6和第八开关管T8对第二节点N2进行充电，能量存储在存储电容Cst中，以使第二节点N2的电压为Vdata+Vth，其中，Vdata为数据线Data输出的数据电压，Vth为第八开关 管T8的阈值电压。本实施例中，在第一充电阶段完成了对第二像素补偿电路4的充电过程。
在发光阶段T4，开关控制电源线EM输出的开关控制电压为低电平电压。开关控制电源线EM向第一像素补偿电路3中的第九开关管T9和第十开关管T10的控制极输出开关控制电压，以使第九开关管T9和第十开关管T10开启。开关控制电源线EM向第二像素补偿电路4中的第九开关管T9和第十开关管T10的控制极输出开关控制电压，以使第九开关管T9和第十开关管T10开启。在第一像素补偿电路3以及第二像素补偿电路4中，第八开关管T8将存储电容Cst存储的电压转化为驱动电流，该驱动电流用于驱动OLED发光，驱动电流I＝1/2*μ p*C ox*W/L*(Vgs-Vth)，其中，μ p为空穴迁移率，C ox为绝缘层电容率，W/L为宽长比，由于Vgs＝Vdata+Vth-VDD，因此I＝1/2*μ*C*W/L*(Vdata+Vth-VDD-Vth)＝1/2*μ*C*W/L*(Vdata-VDD)，从上述公式可以看出，驱动电流不受Vth影响，从而提高了像素显示的均匀性。在发光阶段T4，第一像素补偿电路3以及第二像素补偿电路4中的OLED同时发光。本实施例中，第一电压源输出的电压VDD为高电平信号，第二电压源输出的VSS为低电平信号。
需要说明的是：在上述复位阶段T1、第一充电阶段T2和第二充电阶段T3中，由于开关控制电源线EM输出的开关控制电压为高电平电压，因此第一像素补偿电路3中的第九开关管T9和第十开关管T10关闭且第二像素补偿电路4中的第九开关管T9和第十开关管T10关闭。
本实施例提供的像素补偿电路单元的技术方案中，至少二个像素补偿电路连接至复位电源线，复位控制电路连接至所述复位电源线和桥接电路，至少二个像素补偿电路之间通过桥接电路连接，本实施例中多个像素补偿电路公用一条复位电源线，减少了复位电源线的数量，从而简化了像素补偿电路的结构。本实施例中，第一像素补偿电路和第二像素补偿电路共享开关控制电源线输出的开关控制信号，从而在设计(layout)简化了信号输入。本实施例中，采用第一控制电源线Sn1输出的电压作为第一像素补偿电路和第二像素补偿电路的第一控制电压，以实现对第一像素补偿电路和第二像素补偿电路进行复位，使得GOA向两个像素补偿电路输出一个控制电压即可，从而减少了GOA的级数。
图4为本公开的另一个实施例的像素补偿电路单元的详细结构示意图。如图4所示，本实施例中的像素补偿电路单元与上述实施例的区别在于，桥接电路2包括第一开关管T1。第一开关管T1的控制极连接至第一控制电源线Sn1，第一开关管T1的第一极连接至第一节点N1，第一开关管T2的第二极连接至第二节点N2。复位控制电路1连接至第二节点N2。本实施例中，例如，第一开关管T1为双栅TFT，采用双栅TFT可有效减少漏电流，从而使得第一节点N1和第二节点N2的电压能够在一帧画面时间内保持在一定的水平，不会出现由于漏电流过大而导致的第一节点N1和第二节点N2的电压降低过大的问题。
复位控制电路1包括第四开关管T4。第四开关管T4的控制极连接至第一控制电源线Sn1，第四开关管T4的第一极连接至第二节点N2，第四开关管T4的第二极连接至复位电源线Vint。
在复位阶段T1，第一控制电源线Sn1输出的第一控制电压为低电平电压。第一控制电源线Sn1向第一开关管T1的控制极输出第一控制电压，以使第一开关管T1开启；第一控制电源线Sn1向第四开关管T4的控制极输出第一控制电压，以使第四开关管T4开启；第一控制电源线Sn1向第一像素补偿电路3和第二像素补偿电路4中的各第五开关管T5输出第一控制电压，以使第一像素补偿电路3和第二像素补偿电路4中的各第五开关管T5均开启。复位电源线Vint通过开启的第四开关管T4向第二节点N2输出复位电压，以实现对第二节点N2进行复位；复位电源线Vint通过开启的第四开关管T4和第一开关管T1向第一节点N1输出复位电压，以实现对第一节点N1进行复位；复位电源线Vint通过第一像素补偿电路3的第五开关管T5对第四节点N4输出复位电压，以实现对第四节点N4进行复位；复位电源线Vint通过第二像素补偿电路4的第五开关管T5对第四节点N4输出复位电压，以实现对第四节点N4进行复位。其中，复位电压为低电平电压，则复位后，第一节点N1、第二节点N2和两个第四节点N4的电压均为低电平电压。
本实施例中对其余结构以及其余工作阶段的描述均与图2所示相同，具体描述可参见图2的实施例，此处不再重复描述。
本实施例提供的像素补偿电路单元的技术方案中，至少二个像素补偿 电路连接至复位电源线，复位控制电路连接至所述复位电源线和桥接电路，至少二个像素补偿电路之间通过桥接电路连接，本实施例中多个像素补偿电路公用一条复位电源线，减少了复位电源线的数量，从而简化了像素补偿电路的结构。本实施例中，第一像素补偿电路和第二像素补偿电路共享开关控制电源线输出的开关控制信号，从而在设计(layout)简化了信号输入。
图5为本公开的又实施例的像素补偿电路单元的详细结构示意图，如图5所示，本实施例提供的像素补偿电路单元与上述各实施例的区别在于，桥接电路2包括第二开关管T2和第三开关管T3。第二开关管T2的控制极连接至第一控制电源线Sn1，所述第二开关管T2的第一极连接至第一节点N1，第二开关管T2的第二极连接至第三节点N3；第三开关管T3的控制极连接至第一控制电源线Sn1，第三开关管T3的第一极连接至第三节点N3，第三开关管T3的第二极连接至第二节点N2；复位控制电路1连接至第三节点N3。本实施例中，第二开关管T2和第三开关管T3均为单栅TFT，两个单栅TFT达到一个双栅TFT的效果。采用两个单栅TFT形成的双栅TFT可有效减少漏电流，从而使得第一节点N1和第二节点N2的电压能够在一帧画面时间内保持在一定的水平，不会出现由于漏电流过大而导致的第一节点N1和第二节点N2的电压降低过大的问题；此外，两个单栅TFT在像素补偿电路单元中对称设置，两个单栅TFT中漏电流无差别，使得两端的电容能够保持相同的电位，从而使得像素补偿电路单元中的两个像素补偿电路显示时的灰阶相同。
复位控制电路1包括第四开关管T4。第四开关管T4的控制极连接至第一控制电源线Sn1，第四开关管T4的第一极连接至第三节点N3，第四开关管T4的第二极连接至复位电源线Vint。
在复位阶段T1，第一控制电源线Sn1输出的第一控制电压为低电平电压。第一控制电源线Sn1向第二开关管T2的控制极输出第一控制电压，以使第二开关管T2开启；第一控制电源线Sn1向第三开关管T3的控制极输出第一控制电压，以使第三开关管T3开启；第一控制电源线Sn1向第四开关管T4的控制极输出第一控制电压，以使第四开关管T4开启；第一控制电源线Sn1向第一像素补偿电路3和第二像素补偿电路4中的各第五开关 管T5输出第一控制电压，以使第一像素补偿电路3和第二像素补偿电路4中的各第五开关管T5均开启。复位电源线Vint通过开启的第四开关管T4和第二开关管T2向第一节点N1输出复位电压，以实现对第一节点N1进行复位；复位电源线Vint通过开启的第四开关管T4和第三开关管T3向第二节点N2输出复位电压，以实现对第二节点N2进行复位；复位电源线Vint通过第一像素补偿电路3的第五开关管T5对第四节点N4输出复位电压，以实现对第四节点N4进行复位；复位电源线Vint通过第二像素补偿电路4的第五开关管T5对第四节点N4输出复位电压，以实现对第四节点N4进行复位。其中，复位电压为低电平电压，则复位后，第一节点N1、第二节点N2和两个第四节点N4的电压均为低电平电压。
本实施例中对其余结构以及其余工作阶段的描述均与如图2所示相同，具体描述可参见图2的实施例，此处不再重复描述。
本实施例提供的像素补偿电路单元的技术方案中，至少二个像素补偿电路连接至复位电源线，复位控制电路连接至所述复位电源线和桥接电路，至少二个像素补偿电路之间通过桥接电路连接，本实施例中多个像素补偿电路公用一条复位电源线，减少了复位电源线的数量，从而简化了像素补偿电路的结构。本实施例中，第一像素补偿电路和第二像素补偿电路共享开关控制电源线输出的开关控制信号，从而在设计(layout)简化了信号输入。
本公开实施例提供了一种像素电路，该像素电路包括依次设置的多个像素补偿电路单元。其中，像素补偿电路单元可包括上述各实施例中的任一像素电路补偿单元。
本实施例提供的像素电路的技术方案中，至少二个像素补偿电路连接至复位电源线，复位控制电路连接至所述复位电源线和桥接电路，至少二个像素补偿电路之间通过桥接电路连接，本实施例中多个像素补偿电路公用一条复位电源线，减少了复位电源线的数量，从而简化了像素补偿电路的结构。本实施例中，第一像素补偿电路和第二像素补偿电路共享开关控制电源线输出的开关控制信号，从而在设计(layout)简化了信号输入。
本公开实施例提供了一种显示装置，该显示装置包括上述像素电路。
本实施例提供的显示装置的技术方案中，至少二个像素补偿电路连 接至复位电源线，复位控制电路连接至所述复位电源线和桥接电路，至少二个像素补偿电路之间通过桥接电路连接，本实施例中多个像素补偿电路公用一条复位电源线，减少了复位电源线的数量，从而简化了像素补偿电路的结构。本实施例中，第一像素补偿电路和第二像素补偿电路共享开关控制电源线输出的开关控制信号，从而在设计(layout)上简化了信号输入。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (11)

  1. 一种像素补偿电路单元，包括：复位电源线、复位控制电路、桥接电路和至少二个像素补偿电路，所述至少二个像素补偿电路连接至所述复位电源线，所述复位控制电路一端连接至所述复位电源线，所述复位控制电路的另一端连接至所述桥接电路，所述至少二个像素补偿电路之间通过所述桥接电路连接。
  2. 根据权利要求1所述的像素补偿电路单元，其中，所述像素补偿电路的数量为二个，二个像素补偿电路包括第一像素补偿电路和第二像素补偿电路；
    所述桥接电路连接至第一节点，第一像素补偿电路连接至第一节点；
    所述桥接电路连接至第二节点，第二像素补偿电路连接至第二节点。
  3. 根据权利要求2所述的像素补偿电路单元，其中，所述桥接电路包括第一开关管；
    所述第一开关管的控制极连接至第一控制电源线，所述第一开关管的第一极连接至第一节点，所述第一开关管的第二极连接至第二节点；
    所述复位控制电路连接至第一节点。
  4. 根据权利要求2所述的像素补偿电路单元，其中，所述桥接电路包括第一开关管；
    所述第一开关管的控制极连接至第一控制电源线，所述第一开关管的第一极连接至第一节点，所述第一开关管的第二极连接至第二节点；
    所述复位控制电路连接至第二节点。
  5. 根据权利要求2所述的像素补偿电路单元，其中，所述桥接电路包括第二开关管和第三开关管；
    所述第二开关管的控制极连接至第一控制电源线，所述第二开关管的第一极连接至第一节点，所述第二开关管的第二极连接至第三节点；
    所述第三开关管的控制极连接至所述第一控制电源线，所述第三开关管的第一极连接至所述第三节点，所述第三开关管的第二极连接至第二节点；
    所述复位控制电路连接至第三节点。
  6. 根据权利要求3或4所述的像素补偿电路单元，其中，所述第一开关管为双栅薄膜晶体管。
  7. 根据权利要求3所述的像素补偿电路单元，其中，所述复位控制电路包括第四开关管；
    所述第四开关管的控制极连接至第一控制电源线，所述第四开关管的第一极连接至第一节点，所述第四开关管的第二极连接至复位电源线。
  8. 根据权利要求4所述的像素补偿电路单元，其中，所述复位控制电路包括第四开关管；
    所述第四开关管的控制极连接至第一控制电源线，所述第四开关管的第一极连接至第二节点，所述第四开关管的第二极连接至复位电源线。
  9. 根据权利要求5所述的像素补偿电路单元，其中，所述复位控制电路包括第四开关管；
    所述第四开关管的控制极连接至第一控制电源线，所述第四开关管的第一极连接至第三节点，所述第四开关管的第二极连接至复位电源线。
  10. 一种像素电路，包括依次设置的多个像素补偿电路单元，所述像素补偿电路单元可采用上述权利要求1至9任一所述的像素补偿电路单元。
  11. 一种显示装置，包括权利要求10所述的像素电路。
PCT/CN2018/091292 2017-09-08 2018-06-14 像素补偿电路单元、像素电路和显示装置 Ceased WO2019047584A1 (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2018562951A JP7203611B2 (ja) 2017-09-08 2018-06-14 画素補償回路ユニット、画素回路および表示装置
EP18804219.6A EP3680886A4 (en) 2017-09-08 2018-06-14 PIXEL COMPENSATION CIRCUIT UNIT, PIXEL CIRCUIT AND DISPLAY DEVICE
US16/305,426 US11107405B2 (en) 2017-09-08 2018-06-14 Pixel compensation circuit unit, pixel circuit and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710805843.2A CN109473061A (zh) 2017-09-08 2017-09-08 像素补偿电路单元、像素电路和显示装置
CN201710805843.2 2017-09-08

Publications (1)

Publication Number Publication Date
WO2019047584A1 true WO2019047584A1 (zh) 2019-03-14

Family

ID=65633480

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/091292 Ceased WO2019047584A1 (zh) 2017-09-08 2018-06-14 像素补偿电路单元、像素电路和显示装置

Country Status (5)

Country Link
US (1) US11107405B2 (zh)
EP (1) EP3680886A4 (zh)
JP (1) JP7203611B2 (zh)
CN (1) CN109473061A (zh)
WO (1) WO2019047584A1 (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110599963A (zh) * 2019-09-25 2019-12-20 京东方科技集团股份有限公司 像素驱动电路、阵列基板、显示装置及像素驱动方法
CN111063301B (zh) 2020-01-09 2024-04-12 京东方科技集团股份有限公司 像素电路及其驱动方法、阵列基板及显示装置
CN112002284A (zh) * 2020-08-07 2020-11-27 武汉华星光电半导体显示技术有限公司 显示面板和显示装置
CN113487998A (zh) * 2021-07-22 2021-10-08 合肥维信诺科技有限公司 像素电路及其驱动方法、显示面板
CN114023262B (zh) * 2021-11-25 2023-12-29 武汉华星光电半导体显示技术有限公司 像素驱动电路及显示面板
CN116312336B (zh) * 2021-12-21 2025-08-12 厦门市芯颖显示科技有限公司 一种发光元件补偿电路、驱动电路及led显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20090043301A (ko) * 2007-10-29 2009-05-06 엘지디스플레이 주식회사 유기전계발광표시장치 및 이의 구동방법
CN103474024A (zh) * 2013-09-06 2013-12-25 京东方科技集团股份有限公司 一种像素电路及显示器
CN103578411A (zh) * 2012-07-19 2014-02-12 乐金显示有限公司 用于感测像素电流的显示装置及其像素电流感测方法
US20150348464A1 (en) * 2014-05-29 2015-12-03 Samsung Display Co., Ltd. Pixel circuit and electroluminescent display including the same
CN105575331A (zh) * 2015-11-25 2016-05-11 友达光电股份有限公司 像素电压补偿电路
CN106710516A (zh) * 2015-08-26 2017-05-24 上海和辉光电有限公司 显示装置、像素驱动电路及其驱动方法

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100926634B1 (ko) 2008-05-26 2009-11-11 삼성모바일디스플레이주식회사 유기 전계발광 표시장치
KR101762344B1 (ko) * 2010-07-27 2017-07-31 삼성디스플레이 주식회사 유기 전계 발광 표시 장치
TWI427597B (zh) * 2011-08-11 2014-02-21 Innolux Corp 顯示器及其驅動方法
KR102038076B1 (ko) 2013-04-04 2019-10-30 삼성디스플레이 주식회사 유기 발광 표시 장치
CN104424880A (zh) * 2013-08-21 2015-03-18 昆山工研院新型平板显示技术中心有限公司 有机发光显示装置、显示器及减少漏电流的方法
US9293083B2 (en) 2013-09-06 2016-03-22 Boe Technology Group Co., Ltd. Pixel circuit and display
CN103474027B (zh) * 2013-09-06 2015-09-09 京东方科技集团股份有限公司 一种像素电路及显示器
CN103474025B (zh) 2013-09-06 2015-07-01 京东方科技集团股份有限公司 一种像素电路及显示器
CN103474026B (zh) 2013-09-06 2015-08-19 京东方科技集团股份有限公司 一种像素电路及显示器
JP2015125366A (ja) * 2013-12-27 2015-07-06 株式会社ジャパンディスプレイ 表示装置
CN203950535U (zh) * 2014-07-10 2014-11-19 京东方科技集团股份有限公司 像素电路和显示装置
KR101639977B1 (ko) * 2014-07-10 2016-07-18 엘지디스플레이 주식회사 표시 장치와 표시 패널
JP2016075787A (ja) 2014-10-06 2016-05-12 株式会社Ｊｏｌｅｄ 表示装置
KR102230928B1 (ko) 2014-10-13 2021-03-24 삼성디스플레이 주식회사 유기 발광 표시 장치 및 이의 구동 방법
JP6518471B2 (ja) 2015-03-19 2019-05-22 株式会社ジャパンディスプレイ 発光素子表示装置
KR102339649B1 (ko) * 2015-08-31 2021-12-16 엘지디스플레이 주식회사 유기 발광 표시장치와 그 구동 방법
CN106023898B (zh) 2016-07-26 2018-07-24 京东方科技集团股份有限公司 像素电路、显示面板及驱动方法
CN106991966A (zh) * 2017-05-27 2017-07-28 京东方科技集团股份有限公司 阵列基板及驱动方法、显示面板和显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20090043301A (ko) * 2007-10-29 2009-05-06 엘지디스플레이 주식회사 유기전계발광표시장치 및 이의 구동방법
CN103578411A (zh) * 2012-07-19 2014-02-12 乐金显示有限公司 用于感测像素电流的显示装置及其像素电流感测方法
CN103474024A (zh) * 2013-09-06 2013-12-25 京东方科技集团股份有限公司 一种像素电路及显示器
US20150348464A1 (en) * 2014-05-29 2015-12-03 Samsung Display Co., Ltd. Pixel circuit and electroluminescent display including the same
CN106710516A (zh) * 2015-08-26 2017-05-24 上海和辉光电有限公司 显示装置、像素驱动电路及其驱动方法
CN105575331A (zh) * 2015-11-25 2016-05-11 友达光电股份有限公司 像素电压补偿电路

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3680886A4 *

Also Published As

Publication number Publication date
EP3680886A4 (en) 2021-04-14
US11107405B2 (en) 2021-08-31
CN109473061A (zh) 2019-03-15
JP2020533615A (ja) 2020-11-19
EP3680886A1 (en) 2020-07-15
JP7203611B2 (ja) 2023-01-13
US20210225285A1 (en) 2021-07-22

Similar Documents

Publication Publication Date Title
US11393373B2 (en) Gate drive circuit and drive method thereof, display device and control method thereof
CN107358915B (zh) 一种像素电路、其驱动方法、显示面板及显示装置
CN104867442B (zh) 一种像素电路及显示装置
CN104318897B (zh) 一种像素电路、有机电致发光显示面板及显示装置
CN103680406B (zh) 一种像素电路及显示装置
JP7203611B2 (ja) 画素補償回路ユニット、画素回路および表示装置
CN109509430B (zh) 像素驱动电路及方法、显示装置
CN103927981B (zh) 像素电路及其驱动方法、显示装置
CN104021763B (zh) 像素电路、显示装置和像素电路的驱动方法
WO2018076719A1 (zh) 像素驱动电路及其驱动方法、显示面板和显示装置
WO2016173124A1 (zh) 像素电路、其驱动方法及相关装置
WO2014176834A1 (zh) 像素电路及其驱动方法、显示装置
WO2017031909A1 (zh) 像素电路及其驱动方法、阵列基板、显示面板及显示装置
WO2015014025A1 (zh) 像素驱动电路及其驱动方法、显示装置
WO2015169006A1 (zh) 一种像素驱动电路及其驱动方法和显示装置
WO2016011714A1 (zh) 像素电路、像素电路的驱动方法和显示装置
WO2018214533A1 (zh) 显示装置以及像素电路及其控制方法
WO2015188533A1 (zh) 像素驱动电路、驱动方法、阵列基板及显示装置
CN106971691A (zh) 一种像素电路、驱动方法及显示装置
CN112037713A (zh) 像素电路及其驱动方法、显示装置
WO2015003434A1 (zh) 发光二极管像素单元电路、其驱动方法及显示面板
CN104134425A (zh) 一种oled反相电路和显示面板
KR20190112876A (ko) 주사 구동부
WO2016119305A1 (zh) Amoled像素驱动电路及像素驱动方法
WO2017004946A1 (zh) 像素驱动电路、显示基板及其驱动方法、显示装置

Legal Events

Date Code Title Description
ENP Entry into the national phase

Ref document number: 2018562951

Country of ref document: JP

Kind code of ref document: A

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18804219

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 2018804219

Country of ref document: EP

Effective date: 20200408

WWW Wipo information: withdrawn in national office

Ref document number: 2018804219

Country of ref document: EP