WO2019052284A1 - 阵列基板、显示面板及显示装置 - Google Patents

阵列基板、显示面板及显示装置 Download PDF

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WO2019052284A1
WO2019052284A1 PCT/CN2018/098286 CN2018098286W WO2019052284A1 WO 2019052284 A1 WO2019052284 A1 WO 2019052284A1 CN 2018098286 W CN2018098286 W CN 2018098286W WO 2019052284 A1 WO2019052284 A1 WO 2019052284A1
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Prior art keywords
substrate
layer
array substrate
gate
orthographic projection
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PCT/CN2018/098286
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English (en)
French (fr)
Inventor
程鸿飞
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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Priority to KR1020197014155A priority Critical patent/KR102192976B1/ko
Priority to EP18855818.3A priority patent/EP3683834B1/en
Priority to BR112019011946-9A priority patent/BR112019011946B1/pt
Priority to MX2019006652A priority patent/MX2019006652A/es
Priority to US16/325,908 priority patent/US10950676B2/en
Priority to AU2018331064A priority patent/AU2018331064B2/en
Priority to JP2019534930A priority patent/JP7199357B2/ja
Priority to RU2019118617A priority patent/RU2745921C1/ru
Publication of WO2019052284A1 publication Critical patent/WO2019052284A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to an array substrate, a display panel, and a display device.
  • the array substrate generally includes a base substrate and a plurality of pixel units arranged in an array disposed on the base substrate.
  • Each of the pixel units includes a thin film transistor (TFT) and a pixel circuit electrically connected to the TFT.
  • TFT thin film transistor
  • the TFT generally includes an active layer, a drain disposed above the active layer with respect to the base substrate, and an insulating layer between the active layer and the drain.
  • the drain may be electrically connected to the active layer through via holes in the insulating layer.
  • the pixel circuit includes a pixel electrode that forms one of the two electrodes of the liquid crystal capacitor.
  • the pixel circuit also includes a pixel electrode (eg, an anode electrode of an OLED device) on which a pixel defining layer is also typically disposed. In either case, the pixel electrode can be electrically connected to the drain of the TFT through the via.
  • an array substrate including: a substrate substrate including a plurality of pixel regions arranged in an array; and a plurality of thin film transistors distributed in respective ones of the plurality of pixel regions
  • Each of the thin film transistors includes: an active layer on the base substrate; a gate on the base substrate, the active layer and the gate stacked on each other; a source, located above the gate, the source being electrically connected to the active layer through a first via; and a drain above the gate, the drain passing through the second via
  • the active layer is electrically connected, the drain includes a first portion located in the second via; a passivation layer is disposed on each source and each drain, and the passivation layer covers the drains a first portion; and a plurality of pixel electrodes distributed in respective ones of the plurality of pixel regions and on the passivation layer, each of the pixel electrodes passing through a corresponding portion of the passivation layer
  • the three vias are electrically connected to a corresponding one of the drains
  • the drain further includes a second portion outside the second via, and the pixel electrode is electrically coupled to the second portion of the drain through the third via.
  • the array substrate further includes a planar layer on the passivation layer.
  • the flat layer is provided with a plurality of fourth via holes, and an orthographic projection of each of the fourth via holes on the substrate substrate completely covers a corresponding one of the third via holes on the substrate Orthographic projection on the substrate.
  • Each of the pixel electrodes includes a first portion located within the respective third via, a second portion located within a respective one of the fourth vias, and a third portion located on the planar layer.
  • the orthographic projection of each of the fourth vias on the substrate further covers a positive of a respective one of the second vias on the substrate projection.
  • the orthographic projection of each of the fourth vias on the substrate has a shape selected from the group consisting of a circle and a square.
  • the geometric center of the orthographic projection of the fourth via on the substrate substrate and the positive of the corresponding third via on the substrate overlap.
  • the planar layer has a thickness of 1 to 4 ⁇ m.
  • an orthographic projection of the third via on the substrate substrate surrounds an orthographic projection of the second via on the substrate.
  • the orthographic projection of the third via on the substrate substrate has an annular shape.
  • a geometric center of the orthographic projection of the third via on the substrate substrate overlaps a geometric center of the orthographic projection of the second via on the substrate .
  • the orthographic projection of the third via on the substrate substrate overlaps with the orthographic projection of the second via on the substrate.
  • the array substrate further includes: a pixel defining layer on the plurality of pixel electrodes and disposed with a plurality of openings, each of the plurality of openings extending through the pixel defining layer Exposing a region of a respective one of the plurality of pixel electrodes; a plurality of organic light emitting layers each located within a respective one of the openings and covering an exposed region of the corresponding one of the pixel electrodes; and a complementary pixel electrode, Covering the plurality of organic light emitting layers and the pixel defining layer.
  • the pixel defining layer has a thickness of 1 to 3 ⁇ m.
  • the second via is tapered toward the substrate substrate.
  • the second via has a minimum aperture that is greater than three times the depth of the second via.
  • the array substrate further includes a gate insulating layer sandwiched between each of the gate electrodes and each of the active layers.
  • the gate in each of the plurality of thin film transistors, is located further from the base substrate than the active layer.
  • the gate in each of the plurality of thin film transistors, the gate is located closer to the substrate substrate than the active layer.
  • a display panel comprising the array substrate as described above.
  • a display device including the display panel as described above.
  • FIG. 1 is a schematic top plan view of a partial region of an array substrate in accordance with an embodiment of the present disclosure
  • FIG. 2 is a circuit schematic diagram of a partial region of the array substrate of FIG. 1;
  • FIG. 3 is a schematic cross-sectional view taken along line A-A' of FIG. 1, illustrating an exemplary structure of a partial region of the array substrate of FIG. 1;
  • FIG. 4 is a schematic cross-sectional view taken along line A-A' of FIG. 1, illustrating another exemplary structure of a partial region of the array substrate of FIG. 1;
  • Figure 5 is a schematic cross-sectional view taken along line A-A' of Figure 1, illustrating yet another exemplary structure of a partial region of the array substrate of Figure 1;
  • Figure 6 is a schematic cross-sectional view taken along line A-A' of Figure 1, illustrating another exemplary structure of a partial region of the array substrate of Figure 1;
  • FIG. 7 is a schematic diagram of a display device in accordance with an embodiment of the present disclosure.
  • first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/ Some should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer Thus, a first element, component, region, layer, or section, which is discussed below, may be referred to as a second element, component, region, layer or section without departing from the teachings of the disclosure.
  • under and under can encompass both the ⁇ RTIgt; Terms such as “before” or “before” and “after” or “following” may be used, for example, to indicate the order in which light passes through the elements.
  • the device can be oriented in other ways (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein interpreted accordingly.
  • a layer is referred to as “between two layers,” it may be a single layer between the two layers, or one or more intermediate layers may be present.
  • FIG. 1 is a schematic top plan view of a partial region of an array substrate including an exemplary pixel unit in accordance with an embodiment of the present disclosure. It will be understood that although only a single pixel region is shown in FIG. 1 for convenience of illustration, the array substrate includes a plurality of such pixel regions arranged in an array.
  • the gate lines 10 extend in the row direction
  • the data lines 11 extend in the column direction
  • the power supply lines 12 extend in parallel with the data lines 11.
  • the power line 12 includes a first electrode 120 that extends perpendicular to its length.
  • the thin film transistor T 1 is disposed at the intersection of the gate line 10 and the data line 11, and includes a gate G 1 connecting the gate lines 10, a source S 1 connecting the data lines 11, and an interlayer insulation through extending through
  • the layer 4 and the fifth via V 5 of the gate insulating layer 3 are electrically connected to the drain D 1 of the gate G 2 of the other thin film transistor T 2 .
  • the gate G 2 of the thin film transistor T 2 includes an extended portion forming the second electrode 130, wherein the second electrode 130 is disposed opposite to the first electrode 120 to form a storage capacitor.
  • the thin film transistor T 2 further including an active layer L2, the drain D V 2 connected to the electrically active layer L 2 by a second through hole 2, and a source connected to a power line 12 pole S 2.
  • the drain D 2 is also electrically connected to the pixel electrode 2 through the third via V 3 .
  • FIG. 2 shows an equivalent circuit of the pixel region of FIG. 1, which is a pixel circuit including an organic light emitting diode (OLED).
  • the pixel electrode 2 in FIG. 1 may be, for example, an anode electrode of an OLED.
  • the pixel circuit of Figure 2 is merely exemplary and that other embodiments are possible. It will also be understood that the concepts of the present disclosure are not limited to OLED array substrates, but may also be applied to liquid crystal display (LCD) array substrates.
  • LCD liquid crystal display
  • the thin film transistor T 1 T 2 may be an amorphous silicon TFT, a polysilicon TFT, or as an oxide semiconductor and TFT.
  • a portion of the thin film transistor T 1, the gate G 1 may be a part of the gate line 10 (i.e., no separate gate pattern extending from the gate 10), and the source S may also be a data line 11 is (ie, there are no separate source patterns extending from the data 11).
  • Embodiments of the present disclosure are not limited to TFTs of a particular kind and/or structure.
  • the gate line 10, the gates G 1 and G 2 , the power supply line 12 , the sources S 1 and S 2 , the drains D 1 and D 2 , and the data line 11 may be Cu (copper), Al.
  • a metal material such as (aluminum), Mo (molybdenum), Ti (titanium), Cr (chromium), and W (tungsten) or an alloy thereof.
  • they may be a single layer structure or a multilayer structure, such as a stacked design of Mo ⁇ Al ⁇ Mo, Ti ⁇ Cu ⁇ Ti, and Mo ⁇ Ti ⁇ Cu.
  • FIG. 3 is a schematic cross-sectional view taken along line A-A' of FIG. 1, illustrating an exemplary structure of a partial region of the array substrate of FIG. 1.
  • the array substrate comprises a substrate 1, on which a thin film transistor T 2 L 2 of the active layer and the gate insulating layer 3.
  • the gate insulating layer 3 is sandwiched between the thin film transistor T 2 and the gate electrode G 2 of the active layer L 2.
  • the active layer L 2 and the gate G 2 are stacked on each other.
  • the thin film transistor T 2 is a top gate type transistor in which the gate G 2 is located farther from the substrate 1 than the active layer L 2 .
  • the gate insulating layer 3 covers the active layer L 2 and the gate G 2 is located on the gate insulating layer 3.
  • the interlayer insulating layer 4 is disposed on the gate G 2 .
  • the source S 2 and the drain D 2 of the thin film transistor T 2 are located on the interlayer insulating layer 4.
  • the source S 2 is electrically connected to the active layer L 2 through the first via hole V 1 penetrating the interlayer insulating layer 4 and the gate insulating layer 3, and the drain D 2 passes through the interlayer insulating layer 4 and the gate insulating layer
  • the second via V 2 of 3 is electrically connected to the active layer L 2 . It comprises a second drain electrode D 2 2 V via the first portion and in the second D 2-1 via the second portion of the outer V 2 D 2-2.
  • a passivation layer 5 is disposed on the source S 2 and the drain D 2 .
  • the passivation layer 5 includes a portion 51 covering the first portion D 2-1 of the drain D 2 .
  • portion 51 of passivation layer 5 is directly on first portion D 2-1 of drain D 2 .
  • the pixel electrode 2 is located on the passivation layer 5 and is electrically connected to the drain D 2 through a third via hole V 3 penetrating through the passivation layer 5.
  • the array substrate further includes a pixel defining layer 6 disposed on the pixel electrode 2.
  • the pixel defining layer 6 is provided with an opening 61 penetrating the pixel defining layer 6 to expose a region of the pixel electrode 2.
  • the organic light-emitting layer 7 is disposed inside the opening 61 and covers the exposed region of the pixel electrode 2.
  • the array substrate further includes a complementary pixel electrode 8 covering the organic light-emitting layer 7 and the pixel defining layer 6.
  • the complementary pixel electrode 8, the organic light-emitting layer 7, and the pixel electrode 2 constitute an OLED device.
  • pixel electrode 2 is the anode of the OLED device and complementary pixel electrode 8 is the cathode of the OLED device.
  • the pixel defining layer 6 may have a thickness of, for example, 1 to 3 ⁇ m. This allows the organic light-emitting layer 7 to be provided with a deposition space having a sufficient depth.
  • the pixel defining layer 6 is generally prepared from an organic resin material. During the luminescence of the OLED device, residual gas in the resin material escapes from the pixel defining layer 6 due to heat generated by the luminescence.
  • the gas escaping from the pixel defining layer 6 may pass through a via structure between the pixel electrode 2 and the active layer L 2 (eg, The two via holes V 2 and the third via holes V 3 ) penetrate into the active layer L 2 . This will affect the stability of the active layer and change the electrical characteristics of the thin film transistor T 2 .
  • the orthographic projection of the third via hole V 3 on the base substrate 1 may not overlap with the orthographic projection of the second via hole V 2 on the base substrate 1.
  • the pixel electrode 2 V 3 third through hole and the drain D of the second part 2 are electrically connected via 2-2 D (i.e., a portion of the pixel electrode 2 is deposited in the third through hole and the drain D and V 3 2
  • the orthographic projection of the third via hole V 3 on the substrate substrate 1 surrounds the second via hole V 2 on the substrate
  • the orthogonal projection of the third via hole V 3 in an annular shape on the base substrate 1.
  • the orthogonal projection of the third via hole V 3 on the base substrate 1 in the geometric center of the second via hole V 2 orthogonal projection on the base substrate 1 in the geometric center of the overlap since the orthogonal projection of the third via hole V 3 in an annular shape on the base substrate 1, the orthogonal projection of the geometric center (or the center of the shape) that is composed of two circular annular Center of the circle (the centers of the two circles coincide).
  • FIG. 4 is a schematic cross-sectional view taken along line A-A' of FIG. 1, illustrating another exemplary structure of a partial region of the array substrate of FIG. 1.
  • the same reference numerals as in Fig. 3 denote the same elements.
  • the orthographic projection of the third via hole V 3 on the substrate substrate 1 may completely cover the orthographic projection of the second via hole V 2 on the substrate substrate 1. This allows an increase in the contact area between the pixel electrode 2 and the second portion D 2-2 of the drain D 2 , thereby improving the reliability of the electrical contact.
  • the second via hole V 2 is tapered toward the base substrate 1. That is, the aperture of the second via hole V 2 gradually becomes smaller from the top to the bottom.
  • the smallest diameter of the second via hole is larger than the second through V 2 V 3 times the depth of the hole 2, such that when the metal is deposited on the drain of the second via hole V 2 can follow the second through hole
  • the shape of V 2 forms a recessed portion.
  • the portion 51 of the passivation layer 5 covering the drain D 2 may be formed on the recessed portion of the drain D 2 in the second via hole V 2 to provide better gas permeation to the active layer L 2 . Barrier effect.
  • FIG. 5 is a schematic cross-sectional view taken along line A-A' of FIG. 1, illustrating still another exemplary structure of a partial region of the array substrate of FIG. 1.
  • the same reference numerals as in Fig. 3 denote the same elements.
  • the gate insulating layer 3 is only located in the region of the active layer L 2 corresponding to the gate G 2 , that is, the gate insulating layer 3 Only below the gate G 2 .
  • the source S 2 is connected to the active layer L 2 through the first via hole V 1 penetrating the interlayer insulating layer 4, and the drain D 2 passes through the interlayer insulating layer 4
  • the second via hole V 2 is connected to the active layer L 2 .
  • Figure 6 is a schematic cross-sectional view taken along line A-A' of Figure 1, illustrating another exemplary structure of a partial region of the array substrate of Figure 1.
  • the same reference numerals as in Fig. 3 denote the same elements.
  • the array substrate further includes a flat layer 9 (having a thickness of, for example, 1 to 4 ⁇ m) provided on the passivation layer 5.
  • the flat layer 9 is provided with a fourth via hole V 4 corresponding to the third via hole V 3 .
  • the fourth via hole V 4 corresponds to the third via hole V 3 , which means that after the fourth via hole V 4 is formed in the flat layer 9 and the pixel electrode 2 has not been deposited, the fourth via hole V 4 may be exposed below.
  • the third via V 3 .
  • the pixel electrode 2 is disposed on the flat layer 9.
  • the pixel electrode 2 includes a first portion 21 located in the third via hole V 2 , a second portion 22 located in the fourth via hole V 4 , and a third portion 23 located on the flat layer 9 .
  • the first portion 21 of the pixel electrode 2 is in direct electrical contact with the drain second portion D 2-2 . Since a portion of the pixel electrode 2 is deposited in the third via V 3 and the fourth via V 4 , a reliable connection between the first portion 21 of the pixel electrode 2 and the second portion D 2-2 of the drain D 2 can be achieved. .
  • the pixel defining layer 6 is disposed above the pixel electrode 2.
  • a plurality of openings 61 are provided on the pixel defining layer 6 (only one of them is shown in FIG. 6). Each of the plurality of openings 61 extends through the pixel defining layer 6 to expose a region of a corresponding pixel electrode 2.
  • the organic light-emitting layer 7 is disposed inside the opening 61 to cover the exposed region of the pixel electrode 2, and the complementary pixel electrode 8 is provided to cover the organic light-emitting layer 7 and the pixel defining layer 6.
  • the complementary pixel electrode 8, the organic light-emitting layer 7, and the pixel electrode 2 constitute an OLED device.
  • V 4 via a fourth orthogonal projection on the base substrate 1 is completely covered by a third via hole V 3 in orthogonal projection on the base substrate 1. Further, the orthographic projection of the fourth via hole V 4 on the base substrate 1 also completely covers the orthographic projection of the second via hole V 2 on the substrate substrate 1. The area of the fourth via hole V4 is large, providing a good electrical connection between the pixel electrode 2 and the drain D 2 .
  • the orthographic projection of the fourth via hole V 4 on the base substrate 1 may be circular or square.
  • each of the gate insulating layer 3, the interlayer insulating layer 4, and the passivation layer 5 may be made of a silicon nitride or silicon oxide material. Each of them may be a single layer structure or a multilayer structure such as silicon oxide and silicon nitride in a stacked design.
  • the flat layer 9 can be prepared using an organic resin material.
  • the pixel electrode 2 can be prepared by using transparent metal oxide conductive materials such as ITO (Indium Tin Oxide, Indium Tin Oxide), IZO (Indium Zinc Oxide, Indium Zinc Oxide), and FTO (Fluorine-Doped Tin Oxide). .
  • the pixel electrode 2 can be fabricated using a transparent metal oxide conductive material.
  • the pixel electrode 2 may also adopt a laminated structure of a transparent metal oxide conductive material and a metal material such as silver (Ag).
  • the pixel electrode 2 may be a three-layer structure of ITO ⁇ Ag ⁇ ITO.
  • the complementary pixel electrode 8 may be made of a metal material such as aluminum (A1) and/or silver (Ag), and may be a single layer or a laminated structure. Other embodiments are also contemplated.
  • each thin film transistor is shown and described as a top gate transistor in the above embodiments, each of them may also be a bottom gate transistor in which the gate is located closer than the active layer L 2 .
  • the base substrate 1 At the base substrate 1.
  • FIG. 7 is a block diagram showing a display device 70 in accordance with an embodiment of the present disclosure.
  • the display device 70 can be any product or component having a display function, such as a cell phone, tablet, television, display, notebook computer, digital photo frame, navigator, and the like.
  • the display device 70 includes a display panel 100 for displaying an image, a gate driver 200 for outputting a gate scan signal to the display panel 100, a data driver 300 for outputting a data voltage to the display panel 100, and The timing controller 400 controls the gate driver 200 and the data driver 300.
  • the display panel 100 includes an array substrate 101 and an opposite substrate 102 opposite to the array substrate 101.
  • the display panel 100 further includes a liquid crystal layer (not shown) sandwiched between the array substrate 101 and the opposite substrate 102, and the opposite substrate 102 may be a color filter substrate.
  • the opposite substrate 102 may be a cover.
  • the array substrate 101 includes a plurality of pixel regions PX arranged in an array. Each of the pixel regions PX is located at a corresponding intersection of the plurality of gate lines GL and the plurality of data lines DL. Each pixel region includes a pixel that includes a thin film transistor (not shown) and other associated components.
  • the gate driver 200 is electrically connected to the first ends of the respective gate lines GL, thereby sequentially applying gate scan signals to the respective gate lines GL.
  • the gate driver 200 may be directly mounted (eg, integrated) in the array substrate 101.
  • the gate driver 200 may be connected to the display panel 100 through a Tape Carrier Package (TCP).
  • TCP Tape Carrier Package
  • the data driver 300 is electrically connected to the first ends of the respective data lines DL to output data voltages to the respective data lines DL.
  • data driver 300 can include a plurality of data driven chips operating in parallel.
  • the timing controller 400 controls the operation of each of the gate driver 200 and the data driver 300. Specifically, the timing controller 400 outputs a data control signal and image data to control a driving operation of the data driver 300, and outputs a gate control signal to control a driving operation of the gate driver 200. Data control signals and image data are applied to the data driver 300. A gate control signal is applied to the gate driver 200.

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Abstract

一种阵列基板，包括：衬底基板，包括呈阵列排布的多个像素区域；多个薄膜晶体管，分布在所述多个像素区域中的相应像素区域内，所述薄膜晶体管中的每一个包括：有源层、栅极、源极和漏极，所述漏极包括位于第二过孔内的第一部分；钝化层，位于各源极和各漏极上，所述钝化层覆盖各漏极的所述第一部分；以及多个像素电极，分布在所述多个像素区域中的相应像素区域内且位于所述钝化层上，所述像素电极中的每一个通过贯穿所述钝化层的相应第三过孔与各漏极中的相应一个漏极电连接。

Description

阵列基板、显示面板及显示装置
相关申请的交叉引用
本申请要求2017年9月12日提交的中国专利申请No.201721170305.2的权益，其全部公开内容通过引用合并于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板、显示面板及显示装置。
背景技术
阵列基板通常包括衬底基板和设置在衬底基板上的呈阵列排布的多个像素单元。所述像素单元中的每一个包括薄膜晶体管(TFT)和与该TFT电连接的像素电路。
TFT通常包括有源层、相对于衬底基板设置在有源层上方的漏极、以及位于有源层与漏极之间的绝缘层。漏极可以通过绝缘层中的过孔与有源层电连接。在液晶显示器的情况下，像素电路包括像素电极，其形成液晶电容器的两个电极中的一个。在有机发光二极管(OLED)显示器的情况下，像素电路也包括像素电极(例如，OLED器件的阳极电极)，其上通常还设置有像素界定层。在任一情况下，像素电极可以通过过孔与TFT的漏极电连接。
发明内容
根据本公开的一方面，提供了一种阵列基板，包括：衬底基板，包括呈阵列排布的多个像素区域；多个薄膜晶体管，分布在所述多个像素区域中的相应像素区域内，所述薄膜晶体管中的每一个包括：有源层，位于所述衬底基板上；栅极，位于所述衬底基板上，所述有源层和所述栅极堆叠于彼此之上；源极，位于所述栅极上方，所述源极通过第一过孔与所述有源层电连接；以及漏极，位于所述栅极上方，所述漏极通过第二过孔与所述有源层电连接，所述漏极包括位于所述第二过孔内的第一部分；钝化层，位于各源极和各漏极上，所述钝化层覆盖各漏极的所述第一部分；以及多个像素电极，分布在所述多个像素区域中的相应像素区域内且位于所述钝化层上，所述像素电极中的每一个通过贯穿所述钝化层的相应第三过孔与各漏极中的相应一个漏极电连接。
在一些实施例中，所述漏极还包括位于所述第二过孔外的第二部分，并且所述像素电极通过所述第三过孔电连接到所述漏极的第二部分。
在一些实施例中，所述的阵列基板还包括位于所述钝化层上的平坦层。所述平坦层设置有多个第四过孔，所述第四过孔中的每一个在所述衬底基板上的正投影完全覆盖所述第三过孔中的相应一个在所述衬底基板上的正投影。所述像素电极中的每一个包括位于所述相应第三过孔内的第一部分、位于所述第四过孔中的相应一个内的第二部分和位于所述平坦层上的第三部分。
在一些实施例中，所述第四过孔中的每一个在所述衬底基板上的所述正投影还完全覆盖所述第二过孔中的相应一个在所述衬底基板上的正投影。
在一些实施例中，所述第四过孔中的每一个在所述衬底基板上的所述正投影具有从圆形和方形所组成的组中选择的形状。
在一些实施例中，所述第四过孔中的每一个在所述衬底基板上的所述正投影的几何中心与所述相应第三过孔在所述衬底基板上的所述正投影的几何中心重叠。
在一些实施例中，所述平坦层具有1～4μm的厚度。
在一些实施例中，所述第三过孔在所述衬底基板上的正投影环绕所述第二过孔在所述衬底基板上的正投影。
在一些实施例中，所述第三过孔在所述衬底基板上的所述正投影具有圆环状形状。
在一些实施例中，所述第三过孔在所述衬底基板上的所述正投影的几何中心与所述第二过孔在所述衬底基板上的所述正投影的几何中心重叠。
在一些实施例中，所述第三过孔在所述衬底基板上的所述正投影与所述第二过孔在所述衬底基板上的所述正投影部分重叠。
在一些实施例中，所述的阵列基板，还包括：像素界定层，位于所述多个像素电极上并且设置有多个开口，所述多个开口中的每一个贯穿所述像素界定层以暴露所述多个像素电极中的相应一个的区域；多个有机发光层，每个位于所述开口中的相应一个内并且覆盖所述相应一个像素电极的被暴露的区域；以及互补像素电极，覆盖所述多个 有机发光层与所述像素界定层。
在一些实施例中，所述像素界定层具有1～3μm的厚度。
在一些实施例中，所述第二过孔朝向所述衬底基板逐渐变细。
在一些实施例中，所述第二过孔具有大于所述第二过孔深度的3倍的最小孔径。
在一些实施例中，所述的阵列基板还包括夹在各栅极与各有源层之间的栅极绝缘层。
在一些实施例中，在所述多个薄膜晶体管中的每一个中，所述栅极位于比所述有源层更远离所述衬底基板处。
在一些实施例中，在所述多个薄膜晶体管中的每一个中，所述栅极位于比所述有源层更靠近所述衬底基板处。
根据本公开的另一方面，提供了一种显示面板，包括如上所述的阵列基板。
根据本公开的又另一方面，提供了一种显示装置，包括如上所述的显示面板。
根据在下文中所描述的实施例，本公开的这些和其它方面将是清楚明白的，并且将参考在下文中所描述的实施例而被阐明。
附图说明
在下面结合附图对于示例性实施例的描述中，本公开的更多细节、特征和优点被公开，在附图中：
图1为根据本公开实施例的阵列基板的一局部区域的示意性俯视图；
图2为图1的阵列基板的局部区域的电路原理图；
图3为沿图1中A-A′线截取的示意性剖面图，其图示出图1的阵列基板的局部区域的示例性结构；
图4为沿图1中A-A′线截取的示意性剖面图，其图示出图1的阵列基板的局部区域的另一示例性结构；
图5为沿图1中A-A′线截取的示意性剖面图，其图示出图1的阵列基板的局部区域的又另一示例性结构；
图6为沿图1中A-A′线截取的示意性剖面图，其图示出图1的阵列基板的局部区域的再另一示例性结构；并且
图7为根据本公开实施例的显示装置的示意图。
具体实施方式
将理解的是，尽管术语第一、第二、第三等等在本文中可以用来描述各种元件、部件、区、层和/或部分，但是这些元件、部件、区、层和/或部分不应当由这些术语限制。这些术语仅用来将一个元件、部件、区、层或部分与另一个区、层或部分相区分。因此，下面讨论的第一元件、部件、区、层或部分可以被称为第二元件、部件、区、层或部分而不偏离本公开的教导。
诸如“在...下面”、“在...之下”、“较下”、“在...下方”、“在...之上”、“较上”等等之类的空间相对术语在本文中可以为了便于描述而用来描述如图中所图示的一个元件或特征与另一个(些)元件或特征的关系。将理解的是，这些空间相对术语意图涵盖除了图中描绘的取向之外在使用或操作中的器件的不同取向。例如，如果翻转图中的器件，那么被描述为“在其他元件或特征之下”或“在其他元件或特征下面”或“在其他元件或特征下方”的元件将取向为“在其他元件或特征之上”。因此，示例性术语“在...之下”和“在...下方”可以涵盖在...之上和在...之下的取向两者。诸如“在...之前”或“在...前”和“在...之后”或“接着是”之类的术语可以类似地例如用来指示光穿过元件所依的次序。器件可以取向为其他方式(旋转90度或以其他取向)并且相应地解释本文中使用的空间相对描述符。另外，还将理解的是，当层被称为“在两个层之间”时，其可以是在该两个层之间的唯一的层，或者也可以存在一个或多个中间层。
本文中使用的术语仅出于描述特定实施例的目的并且不意图限制本公开。如本文中使用的，单数形式“一个”、“一”和“该”意图也包括复数形式，除非上下文清楚地另有指示。将进一步理解的是，术语“包括”和/或“包含”当在本说明书中使用时指定所述及特征、整体、步骤、操作、元件和/或部件的存在，但不排除一个或多个其他特征、整体、步骤、操作、元件、部件和/或其群组的存在或添加一个或多个其他特征、整体、步骤、操作、元件、部件和/或其群组。如本文中使用的，术语“和/或”包括相关联的列出项目中的一个或多个的任意和全部组合。
将理解的是，当元件或层被称为“在另一个元件或层上”、“连接到另一个元件或层”、“耦合到另一个元件或层”或“邻近另一个 元件或层”时，其可以直接在另一个元件或层上、直接连接到另一个元件或层、直接耦合到另一个元件或层或者直接邻近另一个元件或层，或者可以存在中间元件或层。相反，当元件被称为“直接在另一个元件或层上”、“直接连接到另一个元件或层”、“直接耦合到另一个元件或层”、“直接邻近另一个元件或层”时，没有中间元件或层存在。然而，在任何情况下“在...上”或“直接在...上”都不应当被解释为要求一个层完全覆盖下面的层。
本文中参考本公开的理想化实施例的示意性图示(以及中间结构)描述本公开的实施例。正因为如此，应预期例如作为制造技术和/或公差的结果而对于图示形状的变化。因此，本公开的实施例不应当被解释为限于本文中图示的区的特定形状，而应包括例如由于制造导致的形状偏差。因此，图中图示的区本质上是示意性的，并且其形状不意图图示器件的区的实际形状并且不意图限制本公开的范围。
除非另有定义，本文中使用的所有术语(包括技术术语和科学术语)具有与本公开所属领域的普通技术人员所通常理解的相同含义。将进一步理解的是，诸如那些在通常使用的字典中定义的之类的术语应当被解释为具有与其在相关领域和/或本说明书上下文中的含义相一致的含义，并且将不在理想化或过于正式的意义上进行解释，除非本文中明确地如此定义。
下面将结合附图详细本公开的实施例。
图1为根据本公开实施例的阵列基板的一局部区域的示意性俯视图，该局部区域包括一个示例性的像素单元。将理解的是，虽然为了图示的方便，仅单个像素区域在图1中被示出，但是阵列基板包括呈阵列排布的多个这样的像素区域。
参考图1，在所示出的该像素区域中，栅线10沿行方向延伸，数据线11沿列方向延伸，与栅线10交叉，并且电源线12与数据线11平行地延伸。电源线12包括垂直于其长度方向延伸的第一电极120。薄膜晶体管T 1被设置在栅线10与数据线11的交叉处，并且包括连接栅线10的栅极G 1、连接数据线11的源极S 1、以及通过贯穿(extending through)层间绝缘层4和栅极绝缘层3的第五过孔V 5电连接另一薄膜晶体管T 2的栅极G 2的漏极D 1。薄膜晶体管T 2的栅极G 2包括形成第二电极130的延伸部分，其中第二电极130被设置成与第一电极120 相对以形成存储电容器。薄膜晶体管T 2还包括有源层L2、通过第二过孔V 2与有源层L 2电连接的漏极D 2、以及连接到电源线12的源极S 2。漏极D 2还通过第三过孔V 3与像素电极2电连接。
图2示出了图1的像素区域的等效电路，其是包括有机发光二极管(OLED)的像素电路。在该示例中，图1中的像素电极2可以例如是OLED的阳极电极。将理解的是，图2的像素电路仅仅是示例性的，并且其他实施例是可能的。还将理解的是，本公开的概念不限于OLED阵列基板，而是也可以应用于液晶显示器(LCD)阵列基板。
返回参考图1，薄膜晶体管T 1和T 2可以为非晶硅TFT、多晶硅TFT、或氧化物半导体TFT。在薄膜晶体管T 1中，栅极G 1也可以为栅线10的一部分(即，没有从栅10上延伸出的独立的栅极图案)，并且源极S 1也可以为数据线11的一部分(即，没有从数据11上延伸出的独立的源极图案)。本公开实施例不限于特定种类和/或结构的TFT。作为示例而非限制，栅线10、栅极G 1和G 2、电源线12、源极S 1和S 2、漏极D 1和D 2、以及数据线11可以采用Cu(铜)、Al(铝)、Mo(钼)、Ti(钛)、Cr(铬)以及W(钨)等金属材料或其合金制备。此外，它们可以是单层结构或多层结构，如层叠设计的Mo\Al\Mo、Ti\Cu\Ti以及Mo\Ti\Cu等结构。
图3为沿图1中A-A′线截取的示意性剖面图，其图示出图1的阵列基板的局部区域的示例性结构。
如图3所示，阵列基板包括衬底基板1，其上设置有薄膜晶体管T 2的有源层L 2和栅极绝缘层3。栅极绝缘层3夹在薄膜晶体管T 2的栅极G 2与有源层L 2之间。有源层L 2和栅极G 2堆叠于彼此之上。在图3的示例中，薄膜晶体管T 2为顶栅型晶体管，其中栅极G 2位于比有源层L 2更远离衬底基板1处。具体地，栅极绝缘层3覆盖有源层L 2，并且栅极G 2位于栅极绝缘层3上。层间绝缘层4被设置在栅极G 2上。薄膜晶体管T 2的源极S 2和漏极D 2位于层间绝缘层4上。源极S 2通过贯穿层间绝缘层4和栅极绝缘层3的第一过孔V 1与有源层L 2电连接，并且漏极D 2通过贯穿层间绝缘层4和栅极绝缘层3的第二过孔V 2与有源层L 2电连接。漏极D 2包括位于第二过孔V 2内的第一部分D 2-1和位于第二过孔V 2外的第二部分D 2-2。钝化层5被设置在源极S 2和漏极D 2上。钝化层5包括覆盖漏极D 2的第一部分D 2-1的部分51。在该示 例中，钝化层5的部分51直接位于漏极D 2的第一部分D 2-1上。像素电极2位于钝化层5上，并且通过贯穿钝化层5的第三过孔V 3与漏极D 2电连接。
在该实施例中，阵列基板还包括设置在像素电极2上的像素界定层6。像素界定层6设置有开口61，其贯穿所述像素界定层6以暴露像素电极2的区域。有机发光层7被设置在开口61内并且覆盖像素电极2的被暴露的区域。阵列基板还包括互补像素电极8，其覆盖有机发光层7与像素界定层6。互补像素电极8、有机发光层7和像素电极2构成了OLED器件。例如，像素电极2为OLED器件的阳极，并且互补像素电极8为OLED器件的阴极。在一些示例中，像素界定层6可以具有例如为1～3μm的厚度。这允许为有机发光层7提供具有足够深度的沉积空间。
像素界定层6一般由有机树脂材料制备。在OLED器件的发光过程中，由于发光产生的热量，树脂材料中残留的气体会从像素界定层6逸出。
在没有钝化层5(尤其是钝化层的部分51)的情况下，从像素界定层6逸出的气体可能通过像素电极2与有源层L 2之间的过孔结构(例如，第二过孔V 2和第三过孔V 3)渗透到有源层L 2。这将影响有源层的稳定性，改变薄膜晶体管T 2的电学特性。
相比之下，由于在像素界定层6与有源层L 2之间钝化层5(尤其是钝化层5的部分51)的存在，到有源层L 2的气体渗透可以被阻隔，从而改善薄膜晶体管T 2的电学稳定性。如前所述，这一概念同样适用于LCD阵列基板。此外，其他绝缘层(例如，栅极绝缘层3和层间绝缘层4)也可起到阻隔到有源层L 2的气体渗透的作用。
第三过孔V 3在衬底基板1上的正投影可以与第二过孔V 2在衬底基板1上的正投影不重叠。考虑到像素电极2通过第三过孔V 3与漏极D 2的第二部分D 2-2电连接(即，像素电极2的一部分沉积在第三过孔V 3内并与漏极D 2的第二部分D 2-2直接接触)的事实，在图1和图3所示的示例中，第三过孔V 3在衬底基板1上的正投影环绕第二过孔V 2在基板1上的正投影，从而提供像素电极2与漏极D 2的第二部分D 2-2之间的较大的接触面积。这可以促进电接触的可靠性。特别地，在图3的示例中，第三过孔V 3在衬底基板1上的正投影呈圆环状。
在该实施例中，第三过孔V 3在衬底基板1上的正投影的几何中心与第二过孔V 2在衬底基板1上的正投影的几何中心重叠。在图3的示例中，由于第三过孔V 3在衬底基板1上的正投影呈圆环状，该正投影的几何中心(或形状中心)即为构成圆环状的两个圆的圆心(两个圆的圆心重合)。
图4为沿图1中A-A′线截取的示意性剖面图，其图示出图1的阵列基板的局部区域的另一示例性结构。与图3相同的参考符号指示相同的元件。
如图4所示，第三过孔V 3在衬底基板1上的正投影与第二过孔V 2在衬底基板1上的正投影部分重叠。具体地，第三过孔V 3在衬底基板1上的正投影可以完全覆盖第二过孔V 2在衬底基板1上的正投影。这允许增大像素电极2与漏极D 2的第二部分D 2-2之间的接触面积，从而改善电接触的可靠性。
在该实施例中，第二过孔V 2朝向衬底基板1逐渐变细。也即，第二过孔V 2的孔径从上到下逐渐变小。在一些示例中，第二过孔V 2的最小孔径大于第二过孔V 2的深度的3倍，以使得当漏极金属被沉积在第二过孔V 2处时能跟随第二过孔V 2的形状形成一个凹陷部分。这样，钝化层5的覆盖漏极D 2的部分51可形成在漏极D 2在第二过孔V 2内的凹陷部分上，提供对于到有源层L 2的气体渗透的更好的阻隔效果。
图5为沿图1中A-A′线截取的示意性剖面图，其图示出图1的阵列基板的局部区域的又另一示例性结构。与图3相同的参考符号指示相同的元件。
与前面关于图3和4描述的实施例不同，在图5的实施例中，栅极绝缘层3仅位于有源层L 2上对应于栅极G 2的区域内，即栅极绝缘层3仅位于栅极G 2下方。在这种情况下，如图5所示，源极S 2通过贯穿层间绝缘层4的第一过孔V 1与有源层L 2连接，并且漏极D 2通过贯穿层间绝缘层4的第二过孔V 2与有源层L 2连接。
阵列基板的其他配置与前面关于图3描述的实施例类似，此处不再赘述。
图6为沿图1中A-A′线截取的示意性剖面图，其图示出图1的阵列基板的局部区域的再另一示例性结构。与图3相同的参考符号指示相同的元件。
如图6所示，阵列基板还包括设置在钝化层5上的平坦层9(具有例如为1～4μm的厚度)。该平坦层9上设置有对应于第三过孔V 3的第四过孔V 4。这里，第四过孔V 4对应于第三过孔V 3，是指在平坦层9中形成第四过孔V 4后且还未沉积像素电极2时，第四过孔V 4可露出下方的第三过孔V 3。
像素电极2设置在平坦层9上。像素电极2包括位于第三过孔V 2内的第一部分21、位于第四过孔V 4内的第二部分22和位于平坦层9上的第三部分23。像素电极2的第一部分21与漏极第二部分D 2-2直接电接触。由于像素电极2的一部分沉积在第三过孔V 3和第四过孔V 4内，可实现像素电极2的第一部分21与漏极D 2的第二部分D 2-2之间的可靠连接。
像素界定层6设置在像素电极2上方。像素界定层6上设置有多个开口61(图6中仅示出它们中的一个)。多个开口61中的每一个贯穿像素界定层6以暴露一个相应的像素电极2的区域。在图6所示的像素区域中，有机发光层7被设置在开口61内以覆盖像素电极2的被暴露的区域，并且互补像素电极8被提供以覆盖有机发光层7与像素界定层6。互补像素电极8、有机发光层7和像素电极2构成了OLED器件。
在图6的示例中，第四过孔V 4在衬底基板1上的正投影完全覆盖第三过孔V 3在衬底基板1上的正投影。进一步的，第四过孔V 4在衬底基板1上的正投影还完全覆盖第二过孔V 2在衬底基板1上的正投影。第四过孔V4的面积较大，提供了像素电极2与漏极D 2之间的良好电性连接。这里，第四过孔V 4在衬底基板1上的正投影可以呈圆形或方形。并且，第四过孔V 4在衬底基板1上的正投影的几何中心与第三过孔V 3在衬底基板1上的正投影的几何中心重叠。
在上面描述的各实施例中，栅极绝缘层3、层间绝缘层4和钝化层5中的每一个可以采用氮化硅或氧化硅材料制备。它们中的每一个可以是单层结构或多层结构，例如层叠设计的氧化硅和氮化硅。平坦层9可以采用有机树脂材料制备。像素电极2可采用ITO(Indium Tin Oxide、氧化铟锡)、IZO(Indium Zinc Oxide、氧化铟锌)以及FTO(Fluorine-Doped Tin Oxide、氟掺杂二氧化锡)等透明金属氧化物导电材料制备。在像素电极2具体为OLED器件的阳极的实施例中，像素 电极2可以采用透明金属氧化物导电材料制备。替换地，像素电极2还可以采用透明金属氧化物导电材料与金属材料(例如银(Ag))的层叠结构。例如，像素电极2可以是ITO\Ag\ITO三层结构。互补像素电极8可以采用铝(A1)和/或银(Ag)等金属材料制备，并且可以为单层或层叠结构。还设想了其他实施例。
将理解的是，虽然各薄膜晶体管在上面的实施例中被示出和描述为顶栅型晶体管，但是它们每一个也可以是底栅型晶体管，其中栅极位于比有源层L 2更靠近衬底基板1处。
图7为示出根据本公开实施例的显示装置70的框图。作为示例而非限制，该显示装置70可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
参照图7，显示装置70包括用于显示图像的显示面板100、用于向显示面板100输出栅极扫描信号的栅极驱动器200、用于向显示面板100输出数据电压的数据驱动器300、以及用于控制栅极驱动器200和数据驱动器300的时序控制器400。
显示面板100包括阵列基板101和与阵列基板101相对的对向基板102。在液晶显示装置的情况下，显示面板100还包括夹在阵列基板101和对向基板102之间的液晶层(未示出)，并且对向基板102可以是彩膜基板。在有机发光二极管显示装置的情况下，对向基板102可以是盖板。
阵列基板101包括呈阵列排布的多个像素区域PX。各像素区域PX位于多条栅极线GL和多条数据线DL的相应交叉处。每个像素区域都包括像素，该像素包括薄膜晶体管(未示出)和其他相关联的元件。
栅极驱动器200电连接到各栅极线GL的第一端，从而顺序地向各栅极线GL施加栅极扫描信号。在一些示例性实施例中，栅极驱动器200可以被直接安装(例如，集成)在阵列基板101中。替换地，栅极驱动器200可以通过带式载体封装(Tape Carrier Package，TCP)连接至显示面板100。
数据驱动器300电连接至各数据线DL的第一端，以将数据电压输出至各数据线DL。在一些实施例中，数据驱动器300可以包括多个并行操作的数据驱动芯片。
时序控制器400控制栅极驱动器200和数据驱动器300中的每一 个的操作。具体地，时序控制器400输出数据控制信号和图像数据以控制数据驱动器300的驱动操作，以及输出栅极控制信号以控制栅极驱动器200的驱动操作。数据控制信号和图像数据被施加至数据驱动器300。栅极控制信号被施加至栅极驱动器200。
虽然在附图和和前面的描述中已经详细地说明和描述了本公开，但是这样的说明和描述应当被认为是说明性的和示意性的，而非限制性的；本公开不限于所公开的实施例。通过研究附图、公开内容和所附的权利要求书，本领域技术人员在实践所要求保护的主题时，能够理解和实现对于所公开的实施例的变型。在权利要求书中，词语“包括”不排除其他元件或步骤，并且不定冠词“一”或“一个”不排除多个。在相互不同的从属权利要求中记载了某些措施的仅有事实并不表明这些措施的组合不能用来获利。

Claims (20)

  1. 一种阵列基板，包括：
    衬底基板，包括呈阵列排布的多个像素区域；
    多个薄膜晶体管，分布在所述多个像素区域中的相应像素区域内，所述薄膜晶体管中的每一个包括：
    有源层，位于所述衬底基板上；
    栅极，位于所述衬底基板上，所述有源层和所述栅极堆叠于彼此之上；
    源极，位于所述栅极上方，所述源极通过第一过孔与所述有源层电连接；以及
    漏极，位于所述栅极上方，所述漏极通过第二过孔与所述有源层电连接，所述漏极包括位于所述第二过孔内的第一部分；
    钝化层，位于各源极和各漏极上，所述钝化层覆盖各漏极的所述第一部分；以及
    多个像素电极，分布在所述多个像素区域中的相应像素区域内且位于所述钝化层上，所述像素电极中的每一个通过贯穿所述钝化层的相应第三过孔与各漏极中的相应一个漏极电连接。
  2. 根据权利要求1所述的阵列基板，其中所述漏极还包括位于所述第二过孔外的第二部分，并且其中所述像素电极通过所述第三过孔电连接到所述漏极的第二部分。
  3. 根据权利要求2所述的阵列基板，还包括位于所述钝化层上的平坦层，
    其中所述平坦层设置有多个第四过孔，所述第四过孔中的每一个在所述衬底基板上的正投影完全覆盖所述第三过孔中的相应一个在所述衬底基板上的正投影，并且
    其中所述像素电极中的每一个包括位于所述相应第三过孔内的第一部分、位于所述第四过孔中的相应一个内的第二部分和位于所述平坦层上的第三部分。
  4. 根据权利要求3所述的阵列基板，其中所述第四过孔中的每一个在所述衬底基板上的所述正投影还完全覆盖所述第二过孔中的相应一个在所述衬底基板上的正投影。
  5. 根据权利要求4所述的阵列基板，其中所述第四过孔中的每一个在所述衬底基板上的所述正投影具有从圆形和方形所组成的组中选择的形状。
  6. 根据权利要求3所述的阵列基板，其中所述第四过孔中的每一个在所述衬底基板上的所述正投影的几何中心与所述相应第三过孔在所述衬底基板上的所述正投影的几何中心重叠。
  7. 根据权利要求3所述的阵列基板，其中所述平坦层具有1～4μm的厚度。
  8. 根据权利要求1所述的阵列基板，其中所述第三过孔在所述衬底基板上的正投影环绕所述第二过孔在所述衬底基板上的正投影。
  9. 根据权利要求8所述的阵列基板，其中所述第三过孔在所述衬底基板上的所述正投影具有圆环状形状。
  10. 根据权利要求8所述的阵列基板，其中所述第三过孔在所述衬底基板上的所述正投影的几何中心与所述第二过孔在所述衬底基板上的所述正投影的几何中心重叠。
  11. 根据权利要求8所述的阵列基板，其中所述第三过孔在所述衬底基板上的所述正投影与所述第二过孔在所述衬底基板上的所述正投影部分重叠。
  12. 根据权利要求1所述的阵列基板，还包括：
    像素界定层，位于所述多个像素电极上并且设置有多个开口，所述多个开口中的每一个贯穿所述像素界定层以暴露所述多个像素电极中的相应一个的区域；
    多个有机发光层，每个位于所述开口中的相应一个内并且覆盖所述相应一个像素电极的被暴露的区域；以及
    互补像素电极，覆盖所述多个有机发光层与所述像素界定层。
  13. 根据权利要求12所述的阵列基板，其中所述像素界定层具有1～3μm的厚度。
  14. 根据权利要求1所述的阵列基板，其中所述第二过孔朝向所述衬底基板逐渐变细。
  15. 根据权利要求14所述的阵列基板，其中所述第二过孔具有大于所述第二过孔深度的3倍的最小孔径。
  16. 根据权利要求1所述的阵列基板，还包括夹在各栅极与各有源 层之间的栅极绝缘层。
  17. 根据权利要求16所述的阵列基板，其中在所述多个薄膜晶体管中的每一个中，所述栅极位于比所述有源层更远离所述衬底基板处。
  18. 根据权利要求16所述的阵列基板，其中在所述多个薄膜晶体管中的每一个中，所述栅极位于比所述有源层更靠近所述衬底基板处。
  19. 一种显示面板，包括如权利要求1至18任一项所述的阵列基板。
  20. 一种显示装置，包括如权利要求19所述的显示面板。
PCT/CN2018/098286 2017-09-12 2018-08-02 阵列基板、显示面板及显示装置 Ceased WO2019052284A1 (zh)

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Families Citing this family (6)

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Publication number Priority date Publication date Assignee Title
CN207165572U (zh) * 2017-09-12 2018-03-30 京东方科技集团股份有限公司 一种阵列基板及显示装置
CN109119451B (zh) * 2018-09-04 2020-08-25 京东方科技集团股份有限公司 显示基板及其制造方法、显示装置
US11462282B2 (en) * 2020-04-01 2022-10-04 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor memory structure
CN113238418B (zh) 2021-04-14 2022-09-09 深圳市华星光电半导体显示技术有限公司 阵列基板、显示面板及阵列基板的制作方法
CN116018025B (zh) * 2021-10-20 2025-10-28 北京京东方技术开发有限公司 显示基板及显示装置
CN116322151B (zh) * 2021-12-20 2026-05-26 广东聚华印刷显示技术有限公司 阵列基板的电容器组件，阵列基板及制造方法和显示面板

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102751311A (zh) * 2003-08-25 2012-10-24 三星移动显示器株式会社 有机电致发光显示装置
US20140117323A1 (en) * 2012-10-29 2014-05-01 Ki-Wan Ahn Organic light emitting diode display, thin film transitor array panel, and method of manufacturing the same
US20170141172A1 (en) * 2015-11-12 2017-05-18 Samsung Display Co., Ltd., Organic light-emitting display and manufacturing method thereof
CN207165572U (zh) * 2017-09-12 2018-03-30 京东方科技集团股份有限公司 一种阵列基板及显示装置

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000349301A (ja) 1999-04-01 2000-12-15 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
KR100834344B1 (ko) * 2001-12-29 2008-06-02 엘지디스플레이 주식회사 능동행렬 유기전기발광소자 및 그의 제조 방법
KR100653264B1 (ko) * 2002-10-16 2006-12-01 엘지.필립스 엘시디 주식회사 다결정 실리콘 박막트랜지스터를 포함하는 액정표시장치용어레이기판과 그 제조방법
US7224118B2 (en) * 2003-06-17 2007-05-29 Semiconductor Energy Laboratory Co., Ltd. Display device and electronic apparatus having a wiring connected to a counter electrode via an opening portion in an insulating layer that surrounds a pixel electrode
KR100552975B1 (ko) * 2003-11-22 2006-02-15 삼성에스디아이 주식회사 능동 매트릭스 유기전계발광표시장치 및 그의 제조방법
KR100611152B1 (ko) * 2003-11-27 2006-08-09 삼성에스디아이 주식회사 평판표시장치
JP4211674B2 (ja) * 2004-05-12 2009-01-21 セイコーエプソン株式会社 半導体装置及びその製造方法、電気光学装置及びその製造方法、並びに電子機器
KR100590238B1 (ko) * 2004-05-27 2006-06-19 삼성에스디아이 주식회사 유기 전계 발광 표시 장치 및 그 제조방법
KR100611755B1 (ko) * 2004-06-04 2006-08-10 삼성에스디아이 주식회사 유기전계발광소자 및 그의 제조방법
US8278818B2 (en) 2004-06-04 2012-10-02 Samsung Mobile Display Co., Ltd. Electroluminescent display device and method of fabricating the same
KR100683676B1 (ko) * 2004-06-30 2007-02-20 삼성에스디아이 주식회사 개선된 비어홀구조를 갖는 유기전계 발광표시장치
KR100699996B1 (ko) 2004-09-02 2007-03-26 삼성에스디아이 주식회사 회로 측정용 패드를 포함하는 유기전계발광표시장치와 그제조방법
KR100659759B1 (ko) 2004-10-06 2006-12-19 삼성에스디아이 주식회사 바텀 게이트형 박막트랜지스터, 그를 구비하는평판표시장치 및 박막트랜지스터의 제조방법
KR101107682B1 (ko) * 2004-12-31 2012-01-25 엘지디스플레이 주식회사 표시 소자용 박막 트랜지스터 기판 및 그 제조 방법
JP4757550B2 (ja) * 2005-06-30 2011-08-24 株式会社 日立ディスプレイズ 表示装置およびその製造方法
JP2007033786A (ja) 2005-07-26 2007-02-08 Toshiba Matsushita Display Technology Co Ltd 表示装置
JP4802896B2 (ja) * 2005-09-09 2011-10-26 セイコーエプソン株式会社 電気光学装置の製造方法
KR100805154B1 (ko) 2006-09-15 2008-02-21 삼성에스디아이 주식회사 유기 발광 표시 장치 및 그 제조 방법
KR101534006B1 (ko) * 2008-07-29 2015-07-06 삼성디스플레이 주식회사 유기 발광 표시 장치
JP5318888B2 (ja) * 2008-12-09 2013-10-16 シャープ株式会社 液晶パネル、液晶表示ユニット、液晶表示装置、テレビジョン受像機
KR101113394B1 (ko) * 2009-12-17 2012-02-29 삼성모바일디스플레이주식회사 액정표시장치의 어레이 기판
KR101781532B1 (ko) 2011-03-14 2017-10-24 삼성디스플레이 주식회사 유기 발광 표시 장치와 그 제조방법
WO2013093974A1 (ja) * 2011-12-22 2013-06-27 パナソニック株式会社 有機ｅｌ表示パネル
CN202796957U (zh) * 2012-09-28 2013-03-13 京东方科技集团股份有限公司 一种阵列基板及oled显示装置
CN103926760B (zh) * 2013-01-14 2017-08-25 瀚宇彩晶股份有限公司 像素结构及像素阵列基板
KR20150046963A (ko) * 2013-10-23 2015-05-04 삼성디스플레이 주식회사 플렉서블 표시 장치 및 플렉서블 표시 장치의 제조 방법
KR102248641B1 (ko) * 2013-11-22 2021-05-04 엘지디스플레이 주식회사 유기전계 발광소자
KR102315094B1 (ko) * 2014-11-13 2021-10-20 엘지디스플레이 주식회사 고 개구율 유기발광 다이오드 표시장치 및 그 제조방법
CN104538421B (zh) * 2014-12-16 2018-07-13 深圳市华星光电技术有限公司 Oled显示基板及其制造方法
CN104900676B (zh) * 2015-04-29 2018-06-12 京东方科技集团股份有限公司 阵列基板及其制造方法、显示装置
US10411223B2 (en) * 2015-09-08 2019-09-10 Sharp Kabushiki Kaisha Organic electroluminescence device and illumination device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102751311A (zh) * 2003-08-25 2012-10-24 三星移动显示器株式会社 有机电致发光显示装置
US20140117323A1 (en) * 2012-10-29 2014-05-01 Ki-Wan Ahn Organic light emitting diode display, thin film transitor array panel, and method of manufacturing the same
US20170141172A1 (en) * 2015-11-12 2017-05-18 Samsung Display Co., Ltd., Organic light-emitting display and manufacturing method thereof
CN207165572U (zh) * 2017-09-12 2018-03-30 京东方科技集团股份有限公司 一种阵列基板及显示装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3683834A4 *

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CN207165572U (zh) 2018-03-30
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KR102192976B1 (ko) 2020-12-18
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KR20190067874A (ko) 2019-06-17
US10950676B2 (en) 2021-03-16
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EP3683834A1 (en) 2020-07-22
US20200357870A1 (en) 2020-11-12

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