WO2019056895A1 - 校验码处理方法、电子设备及存储介质 - Google Patents

校验码处理方法、电子设备及存储介质 Download PDF

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Publication number
WO2019056895A1
WO2019056895A1 PCT/CN2018/100713 CN2018100713W WO2019056895A1 WO 2019056895 A1 WO2019056895 A1 WO 2019056895A1 CN 2018100713 W CN2018100713 W CN 2018100713W WO 2019056895 A1 WO2019056895 A1 WO 2019056895A1
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WIPO (PCT)
Prior art keywords
code
block
check code
transmission period
nth
Prior art date
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Ceased
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PCT/CN2018/100713
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English (en)
French (fr)
Inventor
程伟强
李晗
王磊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
China Mobile Communications Group Co Ltd
Research Institute of China Mobile Communication Co Ltd
Original Assignee
China Mobile Communications Group Co Ltd
Research Institute of China Mobile Communication Co Ltd
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Application filed by China Mobile Communications Group Co Ltd, Research Institute of China Mobile Communication Co Ltd filed Critical China Mobile Communications Group Co Ltd
Priority to US16/649,010 priority Critical patent/US11546088B2/en
Priority to EP18858973.3A priority patent/EP3675398B1/en
Publication of WO2019056895A1 publication Critical patent/WO2019056895A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0064—Concatenated codes
    • H04L1/0065—Serial concatenated codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/20—Arrangements for detecting or preventing errors in the information received using signal quality detector
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/28—Flow control; Congestion control in relation to timing considerations
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/048—Speed or phase control by synchronisation signals using the properties of error detecting or error correcting codes, e.g. parity as synchronisation signal

Definitions

  • the present disclosure relates to synchronization technologies in the field of communications, but is not limited to synchronization technologies in the field of communications, and more particularly to a check code processing method, an electronic device, and a storage medium.
  • embodiments of the present disclosure are expected to provide a check code processing method, an electronic device, and a storage medium, at least partially solving the above problems.
  • an embodiment of the present disclosure provides a check code processing method, including:
  • the first sequence of code blocks in the same transmission period is operated to obtain a check code.
  • the method when applied to a transmitting device, the method further includes:
  • the check code of the nth transmission period is carried in a code block of the n+mth transmission period, where n and the m are both positive integers.
  • the sending the check code of the nth transmission period in the code block of the n+m transmission period including:
  • the check code is carried in an Operation Management and Maintenance (OAM) block that replaces the idle code in the n+mth transmission period.
  • OAM Operation Management and Maintenance
  • the OAM block includes: a first type of OAM block periodically transmitted and/or a second type of OAM block that is sent as needed;
  • the check code is carried in the first type of OAM in which the n+m transmission period replaces the idle code.
  • the check code is a bit interleaved parity BIP check code.
  • the method when applied to a receiving device, the method further includes:
  • a second aspect of the embodiments of the present disclosure provides an electronic device, including:
  • a first operation unit configured to calculate m bits of the nth byte of the code block to obtain an nth bit of the first sequence
  • the second operation unit is configured to perform a first sequence of code blocks in the same transmission period to obtain a check code.
  • the electronic device when the electronic device is a transmitting device, the electronic device further includes:
  • a sending unit configured to send the check code of the nth transmission period in a code block of the n+m transmission period, where the n and the m are positive integers;
  • the electronic device When the electronic device is a receiving device, the electronic device further includes:
  • a receiving unit configured to receive a check code sent by the n+m transmission period, where the n and the m are both positive integers
  • the comparing unit is configured to compare the received check code with a check code generated by the local code block based on the nth transmission period;
  • a determining unit configured to determine a transmission quality of the code block of the nth transmission period according to the comparison result.
  • a third aspect of the embodiments of the present disclosure provides an electronic device, including: a transceiver, a memory, a processor, and a computer storage medium stored on the memory and executed by the processor;
  • the processor is connected to the memory and the transceiver, respectively, for implementing a check code processing method provided by one or more of the foregoing technical solutions by executing the computer program.
  • a fourth aspect of the embodiments of the present disclosure provides a computer storage medium storing a computer program, which, after being executed, can implement a check code processing method provided by one or more of the foregoing technical solutions.
  • the check code processing method, the electronic device and the storage medium provided by the embodiments of the present disclosure first calculate a check code by first using a bit in one byte of each code block to obtain one check bit, and integrate one code.
  • the parity bit corresponding to each byte of the block obtains the first sequence; then the first parity bit of the code block in one transmission period is operated to obtain a check code.
  • the check code is generated in this manner, and the first sequence is generated in this manner, and the first sequence generated based on the free block is an all-zero check code, so that even if the free block is inserted or deleted in the data stream, It also does not affect the generation of the check code, thereby avoiding the change of the check code caused by the insertion or deletion of the free block, thereby causing the check code generated at both ends of the transceiver to be different, thereby causing the verification based on the check code to fail or
  • the problem of low accuracy of signal transmission quality evaluation based on verification improves the verification success rate or improves the accuracy of calibration evaluation.
  • the check code calculated in this manner is not only caused by the insertion or deletion of the free block, but also the check code calculated by the sender and the check code received by the receiver are different.
  • the check code can also be used for the verification of the free block. If the free block has an error during the transmission process, it can be verified, so that the accuracy of the verification of the transmission quality is improved again from this level.
  • FIG. 1 is a schematic flowchart of a method for processing a check code according to an embodiment of the present disclosure
  • FIG. 2A is a schematic structural diagram of a free block according to an embodiment of the present disclosure.
  • 2B is a schematic diagram of calculating a first sequence based on a free block according to an embodiment of the present disclosure
  • FIG. 3 is a schematic flowchart diagram of another method for processing a check code according to an embodiment of the present disclosure
  • FIG. 4 is a schematic flowchart diagram of still another method for processing a check code according to an embodiment of the present disclosure
  • FIG. 5 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of another electronic device according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic flowchart of a BIP code generation process according to an embodiment of the present disclosure.
  • FIG. 8A is a schematic diagram of generating and transmitting a BIP code according to an embodiment of the present disclosure
  • FIG. 8B is a schematic diagram of generating and transmitting another BIP code according to an embodiment of the present disclosure.
  • FIG. 8C is a schematic diagram of generating and transmitting another BIP code according to an embodiment of the present disclosure.
  • the embodiment of the present disclosure provides a check code processing method. As shown in FIG. 1 , the method includes:
  • Step S110 Perform m operations on the mth bit of the nth byte of the code block to obtain an nth bit of the first sequence
  • Step S120 Perform a first sequence of code blocks in the same transmission period to obtain a check code.
  • the check code processing method may be a method applied to a transmission device in an Ethernet (for example, Flexible Ethernet (FlxeE)), and the transmission device may be a transmitting device or a receiving device.
  • Ethernet for example, Flexible Ethernet (FlxeE)
  • FlxeE Flexible Ethernet
  • data is transmitted in units of code blocks in one data stream.
  • the code blocks included in the data stream may include: a start block, a stop block, a data block, a free block, and the like.
  • the starting block can be used to identify the beginning of a transmission period, the termination block being used to identify the termination of a transmission period.
  • the data block is a code block carrying data content transmitted by both ends of the transceiver.
  • the free block may be an information content code block that does not carry the interaction between the transmitting and receiving parties, and is used to adjust the transmission frequency of the transmitting and receiving double ends.
  • a code block usually includes a plurality of bytes, for example, a 66-bit code block, and includes 64 bits in addition to a fixed bit indicating a code block type of 2 bits, and the 64 bits are divided into 8 including 8 Bytes of bits; at this time, the maximum value of n is 8.
  • step S110 of this embodiment if a code block includes N bytes, the first sequence includes N bits, wherein the generation of the nth bit in the first sequence depends on the bit included in the nth byte. .
  • the nth byte generates the nth bit of the first sequence.
  • the m bits included in the nth byte may be logically operated by an exclusive OR operation to obtain one bit in the first sequence, and then m bits of each byte in one code block are performed. The operation will get a bit of the first sequence.
  • the m bits may be all bits or partial bits in one byte, and may be partial bits of a predetermined position if it is a partial bit.
  • step S120 the first sequence obtained by all the code blocks in one transmission period is subjected to an exclusive OR logical operation, and a check code is obtained.
  • the check code here may be a check code obtained based on all code blocks in one transmission period.
  • 2A is a schematic diagram of generating the first sequence based on a free block; a vertical representation of a byte, a horizontal representation of a bit; apparently, a free block comprising 8 bytes, each byte comprising 8 bits.
  • the first sequence obtained by all the code blocks in one transmission period of the data stream including the free block is XORed bitwise to obtain a check code.
  • the yth bit of the first sequence generated based on the x1th code block is XORed with the yth bit of the first sequence generated based on the x2th bit.
  • the check code will be obtained until the first sequence corresponding to all code blocks in a transmission cycle is completed.
  • Figure 2B is a schematic diagram of a first sequence obtained based on an exclusive OR operation of bits within each byte of a free block. Obviously, the first sequence obtained based on the free block includes bits that are all zero bits.
  • the step S110 may include:
  • a plurality of the first sequences are calculated based on some or all of the code blocks in one transmission period.
  • one transmission period includes X code blocks
  • the step S110 may include calculating the first sequence based on each of the X code blocks.
  • the step S110 may include: calculating the first sequence based on a partial code block.
  • the partial code block may be a code block of a specified type.
  • a transmission period includes: a check code block that specifically carries the check code.
  • the check code block may not participate in the calculation of the first sequence, and all code blocks except the check code block are involved in the calculation of the first sequence.
  • the code block that does not participate in the calculation of the first sequence may be located in a code block at a predetermined position within one transmission period, for example, a code block located at a start position or an end position of one transmission period.
  • the check code is BIP
  • the check code block may be a BIP code block; the BIP code block may be the first code block or the last code block of one transmission cycle, so that the subsequent receiving device is convenient. Code block calculation and verification.
  • the method further includes:
  • Step S130 When applied to the sending device, the check code of the nth transmission period is carried in the code block of the n+m transmission period, where n and the m are both positive integers.
  • step S110 to step S120 are applied to the transmitting device, if the current check code is generated based on the nth transmission period, the currently generated nth transmission period check code, The code block carried in the n+m transmission period is sent to the receiving device.
  • the n and the m are both positive integers.
  • the m can be a value of 1, 2, or 3, etc.
  • the sending device has a duration corresponding to m transmission periods to calculate the check code, thereby reducing the computing capability requirement of the transmitting device and reducing the hardware requirements of the transmitting device.
  • the step S130 may include:
  • the check code is carried in an OAM block that replaces the idle code in the n+m transmission period.
  • a plurality of code blocks are carried in the data stream.
  • the check code may be carried in a free block for transmission.
  • the free block originally inserts a code block for coordinating frequency inconsistencies between the transmitting device and the receiving device.
  • the free block is usually zero bits except that the bit corresponding to its own code block type identifier is not zero.
  • the free block may be modified into a check code block carrying the check code.
  • the check code can be inserted in the free block without causing the transmitting device. And the generation of the check code of the receiving device.
  • the transmission block of the different device is slow, and the insertion and deletion of the free block may be further performed.
  • the check code is calculated by using the method provided in this embodiment. The insertion and deletion of free blocks by the forwarding device, if it is assumed that other code blocks are transmitted correctly, does not cause the problem that the check codes finally obtained by the transmitting device and the receiving device are inconsistent.
  • the transmitting device may need to insert an OAM block to carry before transmitting the data stream.
  • the OAM block may be generated according to an OAM message.
  • the OAM message is various information that the operator needs to transmit during daily operation, management, and maintenance of the network.
  • the OAM block may generally be a code block that replaces the free block in the data stream.
  • the check code is carried by the OAM block.
  • the sending device when the sending device generates the OAM block, the check code is directly added to the OAM block, so that the OAM message is sent by using the OAM block, and the check code is sent.
  • the receiving device after the OAM block is sent to the receiving device, not only the receiving device performs the OAM function pointed by the OAM message carried in the OAM block, but also the code block of the nth transmission period by the check code extraction. The transmission is verified to evaluate the transmission quality.
  • the OAM block includes: a first type of OAM block periodically transmitted and/or a second type of OAM block that is sent as needed;
  • the step S130 may include:
  • the check code is carried in the first type of OAM in which the n+m transmission period replaces the idle code.
  • the OAM block is divided into two types, one is periodically sent, and the other is sent on demand, and the OAM block sent on demand has a large randomness, and the OAM block is periodically sent.
  • the OAM block is sent according to the period of the OAM message.
  • the check code is a check code of a code block for each transmission period in the data stream, and needs to be periodically performed.
  • the first type of OAM block carries the check code for transmission, and a higher probability can be adopted. Realize the periodic transmission of the check code.
  • the first type of OAM block is an OAM block generated based on daily periodic maintenance; the second type of OAM block is an OAM block generated based on a trigger event, or an OAM block generated based on the indication.
  • the first type of OAM block includes: a connectivity detection block, a signal quality check block, an indication block of a failure of a client signal local end, an indication block of a client signal remote failure, a power consumption indication block of a client signal, and a remote end. At least one of the defect indication block and the remote error indication block.
  • the connectivity detection block is configured to trigger the receiving end and/or the transmitting end to perform connectivity detection of the transmission link.
  • the signal quality detecting block is configured to trigger the receiving end and/or the transmitting end to perform signal quality detection, for example, detecting a bit error rate and/or a bit error rate.
  • a client signal type indication block indicating the type of client signal currently being transmitted.
  • the connectivity verification block is used to indicate a code block that performs connectivity verification of a transmission link.
  • the one-way delay measurement block is used to indicate a code block that performs a delay measurement of a unidirectional link from a transmitting end to a receiving end or a receiving end to a transmitting end.
  • the two-way delay measurement block is used for a code block used by the transmitting end to trigger delay measurement of the bidirectional link.
  • the bidirectional link includes: a transmission link from the transmitting end to the receiving end and then from the receiving end to the transmitting end;
  • the bidirectional delay measurement response block is used by the receiving end for the code block of the delay measurement in response to the bidirectional link.
  • the OAM block is divided into a single function OAM block and a multi-function OAM block according to the OAM function that triggers execution.
  • the multi-function OAM block carries multiple fields, and the fields carry fields for triggering to perform different OAM functions.
  • the fields may include: an automatic protection switching field, a client signal type indication field, a connectivity verification field, and a single At least one of a delay measurement field, a two-way delay measurement field, and a two-way delay measurement response block.
  • the check code is a bit interleaved parity (BIP) check code.
  • BIP bit interleaved parity
  • the BIP is a check code including 8 bits, which may also be called BIP8.
  • the method when applied to a receiving device, the method further includes:
  • Step S101 Receive a check code sent by the n+m transmission period, where n and the m are positive integers;
  • Step S102 Comparing the received check code with a check code generated by a local code block based on the nth transmission period;
  • Step S103 Determine, according to the comparison result, the transmission quality of the code block of the nth transmission period.
  • the receiving device receives the check code in a code block transmitted in the n+mth transmission period, for example, extracting a free block or an OAM block from the n+mth transmission period. Said check code.
  • the received check code here is generated by the transmitting device.
  • the receiving device can generate a check code locally based on the code block of the nth transmission period by performing the steps S110 to S120.
  • the embodiment provides an electronic device, including:
  • the first operation unit 110 is configured to calculate m bits of the nth byte of the code block to obtain an nth bit of the first sequence
  • the second operation unit 120 is configured to perform a first sequence of code blocks in the same transmission period to obtain a check code.
  • the first operation unit 110 and the second operation unit 120 in this embodiment may correspond to an operation circuit or a processor, and the operation circuit may include: a logic operation circuit.
  • the first operation unit 110 may be configured to perform calculation of the first sequence; the second operation unit 120 may be configured to generate a check code.
  • the operation may be any logical operation, such as logical operations such as OR, AND, XOR.
  • each bit in the first sequence depends only on all or part of the bits in a certain byte of the code block, and is no longer the value of the corresponding position bit between the two bytes, so that the idle can be solved.
  • the insertion or deletion of the block in the data stream causes the final calculated check code to change, which not only solves the problem of verification failure or high error rate caused by the insertion or deletion of the free block, but also checks
  • the code can also be used for the verification of free blocks, so that free block transmission errors can also be verified, again improving the accuracy of the transmission quality, such as bit error rate or bit error rate.
  • the check code may be a BIP code, but is not limited to a BIP code.
  • the electronic device when the electronic device is a transmitting device, the electronic device further includes:
  • a sending unit configured to send the check code of the nth transmission period in a code block of the n+mth transmission period, where the n and the m are both positive integers;
  • the sending unit may be corresponding to the sending interface, and the sending interface may be an Ethernet interface or a flexible Ethernet interface, and may be used by the sending device to send the check code to the receiving device for the next m transmission periods.
  • the transmitting device may be a source device of the data stream, or may be a transmission device that receives the data stream from the source device and transmits the data to the target device, and is not limited to the source device.
  • the sending unit is configured to transmit the check code in a free block of the n+mth transmission period; and/or carry the check code in the n+m transmission
  • the operation of the periodic replacement idle code is managed to maintain the transmission in the OAM block.
  • the OAM block includes: a first type of OAM block periodically transmitted and/or a second type of OAM block that is sent as needed; and the sending unit is configured to carry the check code in the first The n+m transmission period is replaced by the first type of OAM in which the idle code is replaced.
  • the electronic device when the electronic device is a receiving device, the electronic device further includes:
  • a receiving unit configured to receive a check code sent by the n+m transmission period, where the n and the m are both positive integers
  • the comparing unit is configured to compare the received check code with a check code generated by the local code block based on the nth transmission period;
  • a determining unit configured to determine a transmission quality of the code block of the nth transmission period according to the comparison result.
  • a receiving unit may be disposed, and the receiving unit may be configured to receive the check code transmitted in the n+mth transmission period, and the verification based on the self calculation.
  • the code can obtain a comparison result by comparing the two check codes, and further can estimate the transmission quality of the nth transmission period according to the comparison result.
  • the transmission quality can be represented by parameters such as a bit error rate, an error block rate, or a bit error rate.
  • the embodiment further provides an electronic device, which may be the foregoing sending device or receiving device.
  • the electronic device may include:
  • transceiver 330 a transceiver 330, a memory 310, a processor 320, and a computer program 340 stored on the memory 310 and executed by the processor 320;
  • the processor 320 is connected to the memory 310 and the transceiver 330, respectively, for performing the check code processing method provided by any one or more of the above technical solutions by executing the computer program, for example, as shown in FIG. One or more of the methods illustrated in Figures 3 and 4.
  • the transceiver 330 in this embodiment may correspond to a transceiver antenna, and the transceiver antenna may be information interaction between the base station and the UE.
  • the memory 310 can include various types of storage media that can be used for data storage.
  • the storage medium included in the memory 310 is at least partially a non-volatile storage medium, and can be used to store the computer program 340.
  • the processor 320 can include a central processing unit, a microprocessor, a digital signal processor, an application processor, an application specific integrated circuit or a programmable array, and the like, which can be used to determine the quality of the cell signal by the computer program 340.
  • the processor 320 can be connected to the transceiver 330 and the memory 310 via an in-device bus such as an integrated circuit bus.
  • the embodiment of the present disclosure further provides a computer storage medium storing a computer program, which is executed by a processor, and performs a cell signal quality determining method provided by one or more of the foregoing technical solutions, for example, One or more of the methods shown in FIGS. 1, 3, and 4 can be performed.
  • the computer storage medium includes: a mobile storage device, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like, which can store program codes. Medium.
  • the computer storage medium can be a non-transitory storage medium.
  • the non-transitory storage medium herein may also be referred to as a non-volatile storage medium.
  • This example provides a BIP8 code calculation method.
  • the following example takes 64/66 bits per code block, and 64 bits participate in 64 bits.
  • Each 64-bit code block is actually composed of 8 bytes, which is different from the vertical calculation method of bit-wise XOR of the same position of different bytes.
  • the BIP of this example uses the bitwise bit of different bits of the same byte. XOR.
  • the free block will have a value of 2b'00000000 by such calculation.
  • the addition and deletion of the Idle frame will no longer affect the BIP check of the receiving end.
  • Step 1 Calculate the BIP8 content of each code block, and XOR the 8 bits of the 7th byte in a code block to obtain the BIP[7] content, and the 6th byte of the code block.
  • the 8 bits are XORed bitwise to obtain the BIP[6] content, so analogy, the 8 bits of the 0th byte in the code block are XORed bitwise to obtain the BIP[0] content.
  • Step 2 XOR the BIP information values calculated by all the code blocks to obtain the final BIP8 value.
  • the horizontal calculation method is calculated, and the BIP information values calculated by all the code blocks are obtained, and then XORed by bit to obtain the final BIP8 value.
  • one transmission cycle may include a plurality of blocks, and FIG. 7 shows that n blocks, which are Blk-1 to Blk-, respectively, first perform intra-block XOR to obtain Blk-1[7:0] to Blk-n[7:0]. That is, a bit sequence of one bit in each byte in the block is used to obtain a first sequence of 8 bits.
  • This mechanism solves the problem that the BIP check mechanism of Idle code block addition and deletion is affected during the transmission process, and provides a basic calculation method and implementation mechanism for BIP calculation based on 64/66B code stream.
  • This example provides several alternative methods for generating and transmitting checksums:
  • the method includes:
  • the Y first sequences are respectively calculated according to all the code blocks in the nth transmission period (for example, including Y code blocks); the Y is a positive integer; and the manner of calculating the first sequence can be referred to the foregoing embodiment.
  • the BIP is transmitted in the (n+1)th transmission period, for example, as shown in FIG. 8A, in the first code block of the (n+1)th transmission period.
  • the code block carrying the BIP is referred to as BIPB;
  • the code block covered by the straight double-headed arrow in FIG. 8A is the code block participating in the calculation of the BIP, and obviously, in the mode shown in FIG. 8A, all codes of one transmission cycle
  • the blocks are all involved in the calculation of BIP.
  • the period indicated by the curved arrow is the correspondence between the BIP transmission period and the transmission period of the transmission BIP, so that the BIP of the nth transmission period can be known to be transmitted in the first code block of the (n+1)th transmission period.
  • the method includes:
  • the BIP is transmitted in the n+mth transmission period, for example, in the n+1th or n+2th transmission period, and the code block participating in the calculation of the BIP in this example excludes the check code block.
  • the code block for transmitting BIP in FIG. 8B is called BIPB.
  • the BIPB itself does not participate in the calculation of BIP, and the BIP of the nth transmission cycle is in the n+2th transmission cycle. Transfer in BIPB.
  • the method includes:
  • the Y first sequences are respectively calculated according to all the code blocks in the nth transmission period (for example, including Y code blocks); the Y is a positive integer; and the manner of calculating the first sequence can be referred to the foregoing embodiment.
  • the BIP is transmitted during the n+2th transmission period.
  • all the code blocks participate in the calculation of the BIP in one transmission period, and the BIP generated based on the code block of the nth transmission period is transmitted in the BIPB of the n+2th transmission period.
  • the disclosed apparatus and method may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner such as: multiple units or components may be combined, or Can be integrated into another system, or some features can be ignored or not executed.
  • the coupling, or direct coupling, or communication connection of the components shown or discussed may be indirect coupling or communication connection through some interfaces, devices or units, and may be electrical, mechanical or other forms. of.
  • the units described above as separate components may or may not be physically separated, and the components displayed as the unit may or may not be physical units, that is, may be located in one place or distributed to multiple network units; Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present disclosure may be integrated into one processing module, or each unit may be separately used as one unit, or two or more units may be integrated into one unit;
  • the unit can be implemented in the form of hardware or in the form of hardware plus software functional units.
  • the foregoing program may be stored in a computer readable storage medium, and the program is executed when executed.
  • the foregoing storage device includes the following steps: the foregoing storage medium includes: a mobile storage device, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.
  • ROM read-only memory
  • RAM random access memory
  • magnetic disk or an optical disk.
  • optical disk A medium that can store program code.

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Abstract

本公开实施例公开了一种校验码处理方法、电子设备及存储介质。所述校验码处理方法，包括：将码块的第n个字节的m个比特进行运算，以得到第一序列的第n个比特；将同一传输周期内码块的第一序列进行运算，以得到校验码。

Description

校验码处理方法、电子设备及存储介质
相关申请的交叉引用
本申请基于申请号为201710861866.5、申请日为2017年09月21日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本公开涉及通信领域的同步技术但不限于通信领域的同步技术，尤其涉及一种校验码处理方法、电子设备及存储介质。
背景技术
在数据传输的过程中，需要对对数据进行校验，例如，完整性校验等。在以太网中，接收端在接收到数据之后进行校验，发现校验后，指示校验错误的概率非常高。
发明内容
有鉴于此，本公开实施例期望提供一种校验码处理方法、电子设备及存储介质，至少部分解决上述问题。
本公开的技术方案是这样实现的：
第一方面，本公开实施例提供一种校验码处理方法，包括：
将码块的第n个字节的m个比特进行运算，以得到第一序列的第n个比特；
将同一传输周期内码块的第一序列进行运算，以得到校验码。
在一些实施例中，当应用于发送设备时，所述方法还包括：
将第n传输周期的校验码携带在第n+m传输周期的码块中发送，其中，所述n和所述m均为正整数。
在一些实施例中，所述将第n传输周期的校验码携带在第n+m传输周期的码块中发送，包括：
将所述校验码携带在第n+m传输周期的空闲块中发送；
和/或，
将所述校验码携带在第n+m传输周期替换空闲码的操作管理维护(OAM)块中发送。
在一些实施例中，所述OAM块包括：周期发送的第一类OAM块和/或，按需发送的第二类OAM块；
所述将所述校验码携带在第n+m传输周期替换空闲码的OAM块中发送，包括：
将所述校验码携带在第n+m传输周期替换空闲码的第一类OAM中发送。
在一些实施例中，所述校验码为比特交织奇偶性BIP校验码。
在一些实施例中，当应用于接收设备中时，所述方法还包括：
接收第n+m传输周期发送的校验码，其中，所述n和所述m均为正整数
将接收的所述校验码，与本地基于第n传输周期的码块生成的校验码进行比对；
根据比对结果，确定所述第n传输周期的码块的传输质量。
本公开实施例第二方面提供一种电子设备，包括：
第一运算单元，配置为将码块的第n个字节的m个比特进行运算，以得到第一序列的第n个比特；
第二运算单元，配置为将同一传输周期内码块的第一序列进行运算，以得到校验码。
在一些实施例中，当所述电子设备为发送设备时，所述电子设备还包括：
发送单元，配置为将第n传输周期的校验码携带在第n+m传输周期的码块中发送，其中，所述n和所述m均为正整数；
或者，
当所述电子设备为接收设备时，所述电子设备还包括：
接收单元，配置为接收第n+m传输周期发送的校验码，其中，所述n和所述m均为正整数
比对单元，配置为将接收的所述校验码，与本地基于第n传输周期的码块生成的校验码进行比对；
确定单元，配置为根据比对结果，确定所述第n传输周期的码块的传输质量。
本公开实施例第三方面提供一种电子设备，包括：收发器、存储器、处理器及存储在所述存储器上且由处理器执行的计算机存储介质；
所述处理器，分别与所述存储器及所述收发器连接，用于通过执行所述计算机程序实现前述一个或多个技术方案提供的校验码处理方法。
本公开实施例第四方面提供一种计算机存储介质，所述计算机存储介质存储有计算机程序，所述计算机程序被执行后，能够实现前述一个或多个技术方案提供的校验码处理方法。
本公开实施例提供的校验码处理方法、电子设备及存储介质，在计算校验码时，首先利用每一个码块的一个字节中的比特进行运算得到1个校验比特，综合一个码块各个字节对应的校验比特得到了第一序列；然后将一个传输周期内的码块的第一校验比特进行运算得到校验码。
第一方面，采用这种方式生成校验码，采用这种方式生成第一序列，则基于空闲块生成的第一序列为全零校验码，这样即便在数据流中插入或删除空闲块，也不会影响校验码的生成，从而避免了因为空闲块的插入或删除导致校验码的变化，从而导致收发两端生成的校验码不同，进而导致基于校验码的校验失败或基于校验的信号传输质量评估精确度低的问题，提升了校验成功率或提升了校验评估精确度。
第二方面，采用这种方式计算的校验码，不仅不会因为空闲块的插入或删除导致发送端计算的校验码，和接收端接收到的校验码的不同的问题，而且这种校验码还可以用于空闲块的校验，若空闲块在传输过程中出现错误也是可以被校验出来的，从而从这一层面再次提升了传输质量的校验评估的精确性。
附图说明
图1为本公开实施例提供的一种校验码处理方法的流程示意图；
图2A为本公开实施例提供的一种空闲块的结构示意图；
图2B为本公开实施例提供的一种基于空闲块计算第一序列的示意图；
图3为本公开实施例提供的另一种校验码处理方法的流程示意图；
图4为本公开实施例提供的又一种校验码处理方法的流程示意图；
图5为本公开实施例提供的一种电子设备的结构示意图；
图6为本公开实施例提供的另一种电子设备的结构示意图；
图7为本公开实施例提供的一种BIP码的生成流程示意图；
图8A为本公开实施例提供的一种BIP码的生成和传输示意图；
图8B为本公开实施例提供的另一种BIP码的生成和传输示意图；
图8C为本公开实施例提供的再一种BIP码的生成和传输示意图。
具体实施方式
以下结合说明书附图及具体实施例对本公开的技术方案做进一步的详细阐述。
研究发现，在以太网中，发送端和接收端不要求完全同步。当发送端的频率比接收端的频率快时，会产生数据堆积，为了不致使数据堆积的溢出，会删除数据流中的闲置块，替换成承载有信息的数据块，减少堆积现象。若发送端的频率比接收端慢时，就会在数据流中增加闲置块，从而避免数据流的中断。但是由于闲置块的加入，会导致原本正确传输的数据流，被校验成错误，从而导致校验错误的概率非常高的现象。有鉴于此，本公开实施例提供一种校验码处理方法，如图1所示，所述方法包括：
步骤S110：将码块的第n个字节的m个比特进行运算，以得到第一序列的第n个比特；
步骤S120：将同一传输周期内码块的第一序列进行运算，以得到校验码。
在本实施例中校验码处理方法可为应用于以太网中(例如灵活以太网(FlxeE))的传输设备中的方法，该传输设备可以发送设备，也可以为接收设备。
在本实施例中，一个数据流中是以码块为单位进行数据传输的。所述数据流中包括的码块可包括：起始块、终止块、数据块及空闲块等。所述起始块可用于标识一个传输周期的起始，所述终止块，用于标识一个传输周期的终止。所述数据块为承载有收发两端传输的数据内容的码块。所述空闲块可为未携带有收发双方交互的信息内容码块，用于调节收发双端的传输频率。
一个码块通常包括多个字节，例如，一个66比特的码块，除了2个比 特的指示码块类型的固定比特以外，还包括64个比特，这64个比特共分为8个包括8个比特的字节；则此时，所述n的最大取值为8。
在本实施例的步骤S110中，若一个码块包括N个字节，则第一序列包括N个比特，其中，第一序列中第n个比特的生成取决与第n个字节包括的比特。例如，将第n个字节则生成第一序列的第n个比特。
在步骤S110中可以将第n个字节包括的m个比特进行异或运算等逻辑运算，得到第一序列中的其中一个比特，然后对一个码块中的每一字节的m个比特进行运算，将会得到第一序列的一个比特。所述m个比特可为一个字节中的所有比特或部分比特，若为部分比特则可为预定位置的部分比特。
在步骤S120中会将一个传输周期内所有码块得到的第一序列进行异或等逻辑运算，会得到校验码。这里的校验码可为基于一个传输周期内所有码块得到的校验码。
图2A是基于空闲块生成所述第一序列的示意图；纵向表示字节，横向表示比特；显然，一个空闲块包括8个字节，每一个字节包括8个比特。
对空闲块的第1个字节的所有比特进行异或运算，生成第一序列的第1个比特，对第2个字节的所有比特进行异或运算，生成第一序列的第2个比特……依次类推，直到空闲块的最后个字节的所有比特进行异或运算，得到第一序列的最后一个比特，组合所有比特得到完整的第一序列。
然后，对包括空闲块的数据流的一个传输周期内的所有码块得到的第一序列进行按位进行异或，得到校验码。例如，将基于第x1码块生成的第一序列的第y比特与基于第x2比特生成的第一序列的第y比特进行异或运算。直到一个传输周期内所有码块对应的第一序列运算完毕，将会得到校验码。
图2B是基于一个空闲块各个字节内的比特的异或运算，得到的第一序 列的示意图，显然这样的话，基于空闲块得到的第一序列包括的比特为全零比特。
在本实施例中，所述步骤S110可包括：
依据一个传输周期内部分或全部码块，计算多个所述第一序列。
例如，在一些实施中，一个传输周期包括X个码块，则所述步骤S110可包括：分别基于X个码块中的每一个码块，计算所述第一序列。
又例如，在另一些实施例中，所述步骤S110可包括：基于部分码块，计算所述第一序列。所述部分码块可为指定类型的码块。例如，一个传输周期中包括：专门携带有所述校验码的校验码块。在计算所述第一序列时，所述校验码块可不参与所述第一序列的计算，除所述校验码块以外的其他码块均是参与所述第一序列的计算的。在本实施例中，不参与所述第一序列计算的码块，可位于一个传输周期内预定位置的码块，例如，位于一个传输周期的开始位置或结束位置的码块。例如，所述校验码为BIP，则所述校验码块可为BIP码块；所述BIP码块可为一个传输周期的首个码块或最后一个码块，这样方便，后续接收设备的码块计算和校验。
在一些实施例中，如图3所示，所述方法还包括：
步骤S130：当应用于发送设备时，将第n传输周期的校验码携带在第n+m传输周期的码块中发送，其中，所述n和所述m均为正整数。
在一些实施例中，若上述步骤S110至步骤S120应用于发送设备中，则若当前校验码是基于第n传输周期的马快生成，则会当前生成的第n传输周期的校验码，携带在第n+m传输周期的码块中发送给接收设备。所述n和所述m均为正整数。
在一些实施例中，所述m可为1、2或3等取值。
这样的话，所述发送设备有m个传输周期对应的时长，来计算所述校验码，从而降低发送设备的计算能力要求，降低了发送设备的硬件要求。
在一些实施例中，所述步骤S130可包括：
将所述校验码携带在第n+m传输周期的空闲块中发送；
和/或，
将所述校验码携带在第n+m传输周期替换空闲码的OAM块中发送。
在数据流中携带有多种码块，在一个实施例中，可以将所述校验码携带在空闲块中传输。所述空闲块原本插入用于协调发送设备和接收设备之间的频率不一致的码块。所述空闲块通常除了自身的码块类型标识对应的比特不为零以外，其他比特都是零比特。在本实施中可以将所述空闲块改造成携带所述校验码的校验码块。
值得注意的是在发送设备中在数据流插入空闲块时，不管是发送设备还是接收色还不中的校验码还未生成，故可以在空闲块中插入校验码，不会导致发送设备和接收设备的校验码的生成。
数据流从发送设备传输到接收设备的过程中，不同设备的传输块慢的问题，还可能会进一步的进行空闲块的插入和删除，由于采用本实施例中提供的方法计算校验码，中间的转发设备进行的空闲块和的插入和删除，若假设其他码块传输正确的情况下，并不会导致发送设备和接收设备最终得到的校验码不一致的问题。
在另一些实施中，发送设备在发送数据流之前，可能需要插入携带有OAM块。所述OAM块可为根据OAM消息生成的。所述OAM消息为运营商对网络进行日常的操作、管理和维护中所需要传输的各种信息。
在一些实施例中，为了减少插入OAM块导致数据流的数据量的增加，占用更多的传输资源，在本实施例中，所述OAM块通常可为替换数据流中空闲块的码块。由OAM块携带所述校验码。这样所述发送设备在生成所述OAM块时，直接将所述校验码添加到所述OAM块中即可，从而实现了利用OAM块发送OAM消息的同时，发送所述校验码。这样的话，当所述 OAM块发送到接收设备之后，不仅会触发接收设备执行OAM块中携带的OAM消息指向的OAM功能，还会通过校验码的提取，对第n个传输周期的码块传输进行校验，从而评估出传输质量。
在一些实施例中，所述OAM块包括：周期发送的第一类OAM块和/或，按需发送的第二类OAM块；
所述步骤S130可包括：
将所述校验码携带在第n+m传输周期替换空闲码的第一类OAM中发送。
在本实施例中，所述OAM块分为两种，一种是周期性发送的，另一种按需发送的，按需发送的OAM块的随机性较大，而周期性发送的OAM块，则会按照OAM消息的周期发送所述OAM块。而校验码是对数据流中每一个传输周期的码块的校验码，是需要周期性进行的，这样的话，利用第一类OAM块携带校验码进行传输，可以采用更高的概率实现校验码的周期性传输。
在一些实施例中，所述第一类OAM块，为基于日常周期性维护产生的OAM块；所述第二类OAM块，为基于触发事件产生的OAM块，或基于指示产生的OAM块。
例如，所述第一类OAM块包括：连通性检测块，信号质量校验块、客户信号本端失效的指示块、客户信号远端失效的指示块、客户信号的功耗指示块、远端缺陷指示块、远端误码指示块的至少其中之一。
所述连通性检测块，用于触发接收端和/或发送端执行传输链路的连通性检测。
信号质量检测块，用于触发接收端和/或发送端执行信号质量的检测，例如，检测误码率和/或误比特率等。
客户信号类型指示块，用于指示当前传输的客户信号的类型。
所述连通性验证块，用于指示进行传输链路的连通性验证的码块。
所述单向时延测量块，用于指示执行发送端到接收端，或者，接收端到发送端中单向链路的延时测量的码块。
所述双向时延测量块，用于由发送端的，用于触发双向链路的延时测量的码块。所述双向链路包括：发送端到接收端再由接收端到发送端的传输链路；
所述双向延时测量响应块，用于由接收端，用于响应双向链路的延时测量的码块。
在一些实施例中，所述OAM块按照触发执行的OAM功能，分为单一功能OAM块，和多功能OAM块。所述多功能OAM块中携带多个字段，这些字段携带用于触发执行不同OAM功能的字段，例如，所述字段可包括：自动保护切换字段、客户信号类型指示字段、连通性验证字段、单向时延测量字段、双向时延测量字段、双向时延测量响应块的至少其中之一。
在一些实施例中，所述校验码为比特交织奇偶性(bit interleaved parity，BIP)校验码。
若所述数据流中的码块为64/66比特的码块，则所述BIP为包括8个比特的校验码，又可以称之为BIP8。
在一些实施例中，如图4所示，当应用于接收设备中时，所述方法还包括：
步骤S101：接收第n+m传输周期发送的校验码，其中，所述n和所述m均为正整数；
步骤S102：将接收的所述校验码，与本地基于第n传输周期的码块生成的校验码进行比对；
步骤S103：根据比对结果，确定所述第n传输周期的码块的传输质量。
在本实施例中，所述接收设备会在第n+m传输周期传输的码块中接收 到所述校验码，例如，从第n+m传输周期的空闲块或OAM块中提取出所述校验码。这里的接收的校验码为发送设备生成的。
接收设备本端可以通过执行所述步骤S110至步骤S120，基于第n传输周期的码块本地生成校验码。
如图5所示，本实施例提供一种电子设备，包括：
第一运算单元110，配置为将码块的第n个字节的m个比特进行运算，以得到第一序列的第n个比特；
第二运算单元120，配置为将同一传输周期内码块的第一序列进行运算，以得到校验码。
本实施例中所述第一运算单元110和第二运算单元120，可对应于运算电路或处理器，所述运算电路可包括：逻辑运算电路。
所述第一运算单元110可配置为进行第一序列的计算；所述第二运算单元120，可配置为校验码的生成。
所述运算可为任意一种逻辑运算，例如，或、与、异或等逻辑运算。
这样的话，第一序列中的每一个比特仅取决于该码块的某一个字节中的全部或部分比特，不再是两个字节之间的对应位置比特的取值，这样可以解决空闲块在数据流中的插入或删除，导致的最终计算出的校验码发生变化的问题，这样不仅解决了因空闲块的插入或删除导致的校验失败或错误率高的问题，而且校验码还可用于空闲块的校验，这样空闲块传输错误也可以被校验出来，从而再次提升了对传输质量，例如，误码率或误比特率等精确度。
在本实施例中所述校验码可为BIP码，但是不局限于BIP码。
在一些实施例中，当所述电子设备为发送设备时，所述电子设备还包括：
发送单元，用于将第n传输周期的校验码携带在第n+m传输周期的码 块中发送，其中，所述n和所述m均为正整数；
所述发送单元可对应于发送接口，所述发送接口，可为以太网接口，或者，灵活以太网接口，可用于发送设备向接收设备发送在后m个传输周期发送所述校验码。所述发送设备可以数据流的源端设备，还可以是从源端设备接收了数据流，向目标设备中转发送的传输设备，不局限于源端设备。
在一些实施例中，所述发送单元，配置为将所述校验码携带在第n+m传输周期的空闲块中发送；和/或，将所述校验码携带在第n+m传输周期替换空闲码的操作管理维护OAM块中发送。
在一些实施例中，所述OAM块包括：周期发送的第一类OAM块和/或，按需发送的第二类OAM块；所述发送单元，配置为将所述校验码携带在第n+m传输周期替换空闲码的第一类OAM中发送。
在一些实施例中，当所述电子设备为接收设备时，所述电子设备还包括：
接收单元，配置为接收第n+m传输周期发送的校验码，其中，所述n和所述m均为正整数
比对单元，配置为将接收的所述校验码，与本地基于第n传输周期的码块生成的校验码进行比对；
确定单元，配置为根据比对结果，确定所述第n传输周期的码块的传输质量。
在本实施例中，若电子设备为接收设备，会设置有接收单元，该接收单元可对应于接收接口，可用于接收第n+m个传输周期传输的校验码，基于自身计算的校验码，通过两个校验码的比对，可以获得一个比对结果，并进一步可以根据该比对结果，评估出第n个传输周期的传输质量。该传输质量可以由误码率、误码块率，或者，误比特率等参数来体现。
本实施例还提供一种电子设备，可为前述的发送设备或接收设备。如图6所示，所述电子设备可包括：
收发器330、存储器310、处理器320及存储在存储器310上并由处理器320运行的计算机程序340；
所述处理器320分别与所述存储器310及收发器330连接，用于通过执行所述计算机程序执行上述任意一个或多个技术方案提供的校验码处理方法，例如，可执行如图1、图3及图4所示的方法的一个或多个。
本实施例中所述收发器330可对应于收发天线，所述收发天线可为基站和UE之间的信息交互。
所述存储器310可包括：各种类型的存储介质，可以用于数据存储。在本实施例中，所述存储器310包括的存储介质至少部分为非易失性存储介质，可以用于存储所述计算机程序340。
所述处理器320可包括：中央处理器、微处理器、数字信号处理器、应用处理器、专用集成电路或可编程阵列等，可以用于通过计算机程序340的执行小区信号质量的确定。
在本实施例中，所述处理器320可通过集成电路总线等设备内总线，与所述收发器330及存储器310连接。
本公开实施例还提供一种计算机存储介质，所述计算机存储介质存储有计算机程序，所述计算机程序被处理器执行后，并执行前述一个或多个技术方案提供的小区信号质量确定方法，例如，可执行如图1、图3及图4所示的方法的一个或多个。
本公开实施例提供的计算机存储介质包括：移动存储设备、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。可选为，所述计算机存储介质可为非瞬间存储介质。这里的非瞬间存储介质又可以称为 非易失性存储介质。
以下结合上述任意一个技术方案提供一个具体示例：
示例1：
本示例提供一种BIP8码计算方法，以下以每个码块为64/66比特为例，66个比特中参与计算为64个比特。每个64比特码块实际上由8个字节构成，与不同字节的同位置的比特按位异或的竖向计算方式不同，本示例的BIP采用同一字节的不同比特的按位进行异或。
例如，空闲块通过这样的计算方式其值将为2b’00000000，通过这种计算方式，Idle帧的增删将不再影响接收端的BIP校验。
对于连续N个被校验的码块的计算过程如下：
第一步：计算每个码块的BIP8内容，将一个码块中第7个字节的8个比特按位进行异或，得到BIP[7]内容，将码块中第6个字节的8个比特按位进行异或，得到BIP[6]内容，因此类推，将码块中第0个字节的8个比特按位进行异或，得到BIP[0]内容
第二步：将所有码块计算出的BIP信息值，按位进行异或，得到最终的BIP8值。
64/66bit码块流进行BIP8计算时，若采用相关算法使得Idle码块的计算为0，将消除传送过程中Idle码块的BIP校验的影响。
通过横向计算，替代竖向计算的方式。计算每个码块的BIP8内容，将一个码块中第7个字节的8个比特按位进行异或，得到BIP[7]内容，将码块中第6个字节的8个比特按位进行异或，得到BIP[6]内容，因此类推，将码块中第0个字节的8个比特按位进行异或，得到BIP[0]内容。
对被校验的连续N个码块，横向计算方式进行计算，得到将所有码块计算出的BIP信息值，然后按位进行异或，得到最终的BIP8值。
如图7所示，一个传输周期可包括多个块，在图7显示有n个块， 分别是Blk-1至Blk-，首先是进行块内异或得到Blk-1[7:0]至Blk-n[7:0]。即通过块内每一个字节内的比特异或得到1个8比特的第一序列。
然后进行块间异或，从而将Blk-1[7:0]至Blk-n[7:0]得到一个传输周期内BIP8[7:0]。
这种机制解决了，传送过程中有Idle码块增删的BIP校验机制受影响的问题，为基于64/66B的码流进行BIP计算提供了基本计算方法及实现机制。
示例3：
本示例提供一种校验码的生成和传输的几种可选方法：
可选方式一：
如图8A所示，所述方法包括：
根据第n个传输周期内所有码块(例如，包括Y个码块)分别计算出Y个第一序列；所述Y为正整数；计算第一序列的方式可以参见前述实施例。
将Y个第一序列异或生成一个BIP；
在第n+1个传输周期发送所述BIP，例如，如图8A所示的，在第n+1个传输周期的首个码块中传输所述BIP。在图8A中，携带BIP的码块称为BIPB；在图8A中直线双向箭头覆盖的码块为参与计算BIP的码块，显然，在图8A所示的方式中，一个传输周期的所有码块都参与BIP的计算。在图8A中弯曲箭头指向的周期为产生BIP传输周期和传输BIP的传输周期的对应关系，故可以知道第n个传输周期的BIP在第n+1个传输周期的首个码块传输。
可选方式二：
如图8B所示，所述方法包括：
根据第n个传输周期内除校验码块以外的码块，分别计算出y个第 一序列，所述y小于Y；所述y正整数；
将y个第一序列异或生成一个BIP；
在第n+m个传输周期发送所述BIP，例如，在第n+1或第n+2个传输周期发送所述BIP，在本示例中参与计算BIP的码块排除了校验码块。
同样的，在图8B中传输BIP的码块称之为BIPB，显然，在本示例中，BIPB自身不参与BIP的计算，且第n个传输周期的BIP的在第n+2个传输周期的BIPB中传输。
可选方式三：
如图8C所示，所述方法包括：
根据第n个传输周期内所有码块(例如，包括Y个码块)分别计算出Y个第一序列；所述Y为正整数；计算第一序列的方式可以参见前述实施例。
在第n+2个传输周期发送所述BIP。在图8C中一个传输周期内所有的码块都参与BIP的计算，且基于第n个传输周期的码块生成的BIP在第n+2个传输周期的BIPB中传输。
在本申请所提供的几个实施例中，应该理解到，所揭露的设备和方法，可以通过其它的方式实现。以上所描述的设备实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，如：多个单元或组件可以结合，或可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示或讨论的各组成部分相互之间的耦合、或直接耦合、或通信连接可以是通过一些接口，设备或单元的间接耦合或通信连接，可以是电性的、机械的或其它形式的。
上述作为分离部件说明的单元可以是、或也可以不是物理上分开的，作为单元显示的部件可以是、或也可以不是物理单元，即可以位于一个 地方，也可以分布到多个网络单元上；可以根据实际的需要选择其中的部分或全部单元来实现本实施例方案的目的。
另外，在本公开各实施例中的各功能单元可以全部集成在一个处理模块中，也可以是各单元分别单独作为一个单元，也可以两个或两个以上单元集成在一个单元中；上述集成的单元既可以采用硬件的形式实现，也可以采用硬件加软件功能单元的形式实现。
本领域普通技术人员可以理解：实现上述方法实施例的全部或部分步骤可以通过程序指令相关的硬件来完成，前述的程序可以存储于一计算机可读取存储介质中，该程序在执行时，执行包括上述方法实施例的步骤；而前述的存储介质包括：移动存储设备、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (10)

  1. 一种校验码处理方法，包括：
    将码块的第n个字节的m个比特进行运算，以得到第一序列的第n个比特；
    将同一传输周期内码块的第一序列进行运算，以得到校验码。
  2. 根据权利要求1所述的方法，其中，
    当应用于发送设备时，所述方法还包括：
    将第n传输周期的校验码携带在第n+m传输周期的码块中发送，其中，所述n和所述m均为正整数。
  3. 根据权利要求2所述的方法，其中，
    所述将第n传输周期的校验码携带在第n+m传输周期的码块中发送，包括：
    将所述校验码携带在第n+m传输周期的空闲块中发送；
    和/或，
    将所述校验码携带在第n+m传输周期替换空闲码的操作管理维护OAM块中发送。
  4. 根据权利要求3所述的方法，其中，
    所述OAM块包括：周期发送的第一类OAM块和/或，按需发送的第二类OAM块；
    所述将所述校验码携带在第n+m传输周期替换空闲码的OAM块中发送，包括：
    将所述校验码携带在第n+m传输周期替换空闲码的第一类OAM中发送。
  5. 根据权利要求1至4任一项所述的方法，其中，
    所述校验码为比特交织奇偶性BIP校验码。
  6. 根据权利要求1至4任一项所述的方法，其中，
    当应用于接收设备中时，所述方法还包括：
    接收第n+m传输周期发送的校验码，其中，所述n和所述m均为正整数
    将接收的所述校验码，与本地基于第n传输周期的码块生成的校验码进行比对；
    根据比对结果，确定所述第n传输周期的码块的传输质量。
  7. 一种电子设备，其中，包括：
    第一运算单元，配置为将码块的第n个字节的m个比特进行运算，以得到第一序列的第n个比特；
    第二运算单元，配置为将同一传输周期内码块的第一序列进行运算，以得到校验码。
  8. 根据权利要求7所述的电子设备，其中，
    当所述电子设备为发送设备时，所述电子设备还包括：
    发送单元，配置为将第n传输周期的校验码携带在第n+m传输周期的码块中发送，其中，所述n和所述m均为正整数；
    或者，
    当所述电子设备为接收设备时，所述电子设备还包括：
    接收单元，配置为接收第n+m传输周期发送的校验码，其中，所述n和所述m均为正整数
    比对单元，配置为将接收的所述校验码，与本地基于第n传输周期的码块生成的校验码进行比对；
    确定单元，配置为根据比对结果，确定所述第n传输周期的码块的传输质量。
  9. 一种电子设备，包括：收发器、存储器、处理器及存储在所述存储器上且由处理器执行的计算机存储介质；
    所述处理器，分别与所述存储器及所述收发器连接，用于通过执行所述计算机程序实现权利要求1至6任一项提供的校验码处理方法。
  10. 一种计算机存储介质，所述计算机存储介质存储有计算机程序，所述计算机程序被执行后，能够实现权利要求1至6任一项提供的校验码处理方法。
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