WO2019109751A1 - 移位寄存器、栅极驱动电路及驱动方法、显示装置 - Google Patents

移位寄存器、栅极驱动电路及驱动方法、显示装置 Download PDF

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Publication number
WO2019109751A1
WO2019109751A1 PCT/CN2018/111954 CN2018111954W WO2019109751A1 WO 2019109751 A1 WO2019109751 A1 WO 2019109751A1 CN 2018111954 W CN2018111954 W CN 2018111954W WO 2019109751 A1 WO2019109751 A1 WO 2019109751A1
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WIPO (PCT)
Prior art keywords
node
pull
voltage
circuit
sub
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2018/111954
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English (en)
French (fr)
Inventor
刘鹏
王珍
张寒
张锴
乔赟
孙建
刘白灵
黄飞
王争奎
张建军
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by BOE Technology Group Co Ltd, Ordos Yuansheng Optoelectronics Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US16/489,185 priority Critical patent/US10902930B2/en
Priority to EP18886888.9A priority patent/EP3723079B1/en
Publication of WO2019109751A1 publication Critical patent/WO2019109751A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a shift register, a gate driving circuit, a driving method, and a display device.
  • GOA Gate Driver on Array
  • the gate driving circuit is integrated on the array substrate of the display panel by using the GOA technology, so that the gate driving IC (Integrated Circuit) can be omitted.
  • Some embodiments of the present disclosure provide a shift register including: a first input sub-circuit, a pull-up control sub-circuit, and a pull-down control sub-circuit; the first input sub-circuit connected to the first signal terminal, the first voltage And the first node, the first input sub-circuit configured to output the voltage of the first signal terminal to the first node under control of a voltage from the first voltage terminal; the pull-up controller a circuit coupled to the first node, the second voltage terminal, and the second node, the pull-up control sub-circuit being configured to be in an on or off state under control of a voltage from the first node, and When the pull-up control sub-circuit is in an on state, outputting the voltage of the second voltage terminal to the second node; the pull-down control sub-circuit is connected to the first node, the third voltage terminal, and the first clock a signal terminal, the signal output terminal, and the pull-down node, the pull-down control sub-circuit configured to output a voltage of the third
  • the pull-up node is configured to control a signal output of the shift register to output a gate scan signal, the pull-down node configured to stop the signal output to output a gate scan signal.
  • the shift register further includes: a filter sub-circuit; the filter sub-circuit connected to the second node, the pull-up node, the second voltage terminal, the filter sub-circuit And configured to filter the clutter in the voltage input by the second node to the filter sub-circuit to be output to the pull-up node under control of a voltage from the second voltage terminal.
  • the shift register further includes: a second input sub-circuit; the second input sub-circuit connected to the second signal terminal, the fourth voltage terminal, and the first node, the second The input sub-circuit is configured to output the voltage of the second signal terminal to the first node under control of a voltage from the fourth voltage terminal.
  • the shift register further includes: a pull-down sub-circuit and an output sub-circuit; the pull-down sub-circuit connected to the pull-down node, the second node, the signal output, and the a three voltage terminal, the pull-down sub-circuit configured to output a voltage of the third voltage terminal to the second node and the signal output terminal under control of a voltage from the pull-down node; the output sub-circuit Connected to the pull-up node, the second clock signal terminal, and the signal output terminal, the output sub-circuit configured to control the voltage of the second clock signal terminal under the control of the voltage from the pull-up node Output to the signal output.
  • the shift register further includes: an initialization sub-circuit; the initialization sub-circuit is connected to the third signal terminal, the second voltage terminal, and the pull-down node, and the initialization sub-circuit is configured to The voltage of the second voltage terminal is output to the pull-down node under control of a voltage from the third signal terminal.
  • the shift register further includes: a residual current cancellation sub-circuit; the residual current cancellation sub-circuit, connected to the fourth signal terminal, the third voltage terminal, the second node, the a pull-down node and the signal output terminal, the residual charge cancellation sub-circuit configured to output a voltage of the third voltage terminal to the second node and the pull-down under control of a voltage from the fourth signal terminal a node, the residual current cancellation sub-circuit is further configured to output a voltage of the fourth signal terminal to the signal output terminal.
  • the first input sub-circuit includes a first transistor; a gate of the first transistor is coupled to the first signal terminal, a first pole is coupled to the first voltage terminal, and a second pole Connected to the first node.
  • the pull-up control sub-circuit includes a second transistor; a gate of the second transistor is coupled to the first node, a first pole is coupled to the second voltage terminal, and a second pole is coupled To the second node.
  • the pull-down control sub-circuit includes a third transistor, a fourth transistor, and a fifth transistor; a gate of the third transistor is coupled to the first clock signal terminal, and a first pole is coupled to the a first clock signal terminal, a second pole connected to the pull-down node; a gate of the fourth transistor connected to the first node, a first pole connected to the pull-down node, and a second pole connected to the first a three voltage terminal; a gate of the fifth transistor is connected to the signal output terminal, a first pole is connected to the pull-down node, and a second pole is connected to the third voltage terminal.
  • the pull-down control sub-circuit further includes a sixth transistor; a gate of the sixth transistor is connected to the second voltage terminal, a first pole is connected to the first clock signal end, and a second The pole is connected to the gate of the third transistor.
  • the pull-down control sub-circuit further includes a first capacitor; a first pole of the first capacitor is coupled to the pull-down node, and a second pole is coupled to the third voltage terminal.
  • the filter sub-circuit includes a seventh transistor; a gate of the seventh transistor is coupled to the second voltage terminal, the first pole Connected to the second node, the second pole is connected to the pull-up node.
  • the shift register further includes a second input sub-circuit
  • the second input sub-circuit includes an eighth transistor; a gate of the eighth transistor is coupled to the second signal terminal The first pole is connected to the first node, and the second pole is connected to the fourth voltage terminal.
  • the pull-down sub-circuit includes a ninth transistor and a tenth transistor, the output sub-circuit including an eleventh transistor and a second capacitor; a gate of the ninth transistor is connected to the pull-down node, a first pole is connected to the second node, a second pole is connected to the third voltage terminal; a gate of the tenth transistor is connected to the pull-down node, and a first pole is connected to the signal output end, a second pole is connected to the third voltage terminal; a first pole of the second capacitor is connected to the pull-up node, and a second pole is connected to the signal output terminal; a gate of the eleventh transistor is connected to The pull-up node has a first pole connected to the second clock signal end and a second pole connected to the signal output end.
  • the shift register further includes an initialization sub-circuit, the initialization sub-circuit includes a twelfth transistor; a gate of the twelfth transistor is connected to the third signal end, One pole is connected to the pull-down node, and a second pole is connected to the second voltage terminal.
  • the initialization sub-circuit includes a twelfth transistor; a gate of the twelfth transistor is connected to the third signal end, One pole is connected to the pull-down node, and a second pole is connected to the second voltage terminal.
  • the residual-cancellation sub-circuit includes a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor; a gate of the transistor is connected to the fourth signal terminal, a first pole is connected to the pull-down node, a second pole is connected to the third voltage terminal; a gate of the fourteenth transistor is connected to the fourth a signal end, a first pole is connected to the signal output end, a second pole is connected to the fourth signal end; a gate of the fifteenth transistor is connected to the fourth signal end, and the first pole is connected to the The second node is connected to the third voltage terminal.
  • Some embodiments of the present disclosure provide a gate driving circuit including at least two stages of the shift register as described in the first aspect; the first signal end of the first stage shift register is connected to the start signal end In addition to the first stage shift register, the first signal terminal of each stage shift register is coupled to the signal output end of the shift register of the previous stage.
  • the shift register further includes a second signal input sub-circuit; except for the last stage shift register, the second signal terminal of each stage shift register and its next stage shift register The signal output ends are connected; the second signal end of the last stage shift register is connected to the start signal end, or the reset signal end.
  • the shift register includes an output sub-circuit; the first clock signal end of the odd-numbered shift register is connected to the first clock signal line, and the second clock signal end and the second clock signal line The first clock signal terminal of the even-numbered shift register is connected to the second clock signal line, and the second clock signal terminal is connected to the first clock signal line.
  • Some embodiments of the present disclosure also provide a display device comprising the gate drive circuit of the second aspect.
  • Some embodiments of the present disclosure provide a driving method for driving the shift register described above, including: an input phase: under control from a first voltage terminal, a first input sub-circuit outputs a voltage input to a first signal terminal to a first node, wherein the voltage of the second voltage terminal is output to the pull-up node via the second node by the voltage control pull-up control sub-circuit through the first node; and at the same time, under the control of the voltage from the first node a pull-down control sub-circuit outputs a voltage of the third voltage terminal to the pull-down node; an output phase: causing the pull-up control sub-circuit to be in a closed state under control of a voltage from the first node; and at a signal output end Under the control of the voltage, the pull-down control sub-circuit outputs the voltage of the third voltage terminal to the pull-down node; and the pull-down phase: the pull-up control sub-circuit is controlled under the control of the voltage from the first node In a
  • the shift register comprises a filter sub-circuit, a pull-down sub-circuit, and an output sub-circuit
  • the method further comprises: the filter sub-circuit to the second node
  • the clutter in the input voltage is filtered out and output to the pull-up node.
  • the method further includes: under the control of the voltage from the pull-up node, the output sub-circuit outputs a clock signal of the second clock signal end to the signal output end, and the signal output end outputs Gate scan signal.
  • the method further includes: under the control of the voltage from the pull-down node, the pull-down sub-circuit outputs a voltage of the third voltage terminal to the second node, and the filter sub-circuit
  • the clutter in the voltage input by the two nodes is filtered and output to the pull-up node, and the output sub-circuit is controlled to be turned off.
  • the pull-down sub-circuit also outputs a voltage of the third voltage terminal to the signal output terminal.
  • the shift register unit includes an initialization sub-circuit and a residual cancellation sub-circuit.
  • the method also includes an initialization phase: the initialization sub-circuit outputs a voltage of the second voltage terminal to the pull-down node under control of a signal from a third signal terminal.
  • a pull-down sub-circuit outputs a voltage of the third voltage terminal to the second node under control of a voltage from the pull-down node, the filter sub-circuit filtering a clutter in a voltage input by the second node After being output, it is output to the pull-up node.
  • the pull-down sub-circuit also outputs a pull-down signal input to the third voltage terminal to the signal output terminal.
  • Residual load elimination phase under the control of the fourth signal terminal, the residual charge cancellation sub-circuit outputs the voltage of the third voltage terminal to the pull-down node and the second node.
  • the filter sub-circuit filters out the clutter in the voltage from the second node and outputs the noise to the pull-up node; the residual-cancellation sub-circuit also outputs the voltage of the fourth signal terminal to the signal Output.
  • Some embodiments of the present disclosure provide a driving method for driving the shift register described above, wherein the shift register includes a second input sub-circuit; the driving method includes: an input stage: at the Under the control of the voltage of the four voltage terminals, the second input sub-circuit outputs the voltage input by the second signal terminal to the first node to open the second sub-voltage by the voltage control pull-up control sub-circuit of the first node The voltage at the terminal is output to the pull-up node via the second node. At the same time, under the control of the voltage from the first node, the pull-down control sub-circuit outputs the voltage of the third voltage terminal to the pull-down node.
  • An output stage the pull-up control sub-circuit is in a closed state under control of a voltage from the first node; and the pull-down control sub-circuit will be the third under control of a voltage from a signal output The voltage at the voltage terminal is output to the pull-down node.
  • a pull-down phase the pull-up control sub-circuit is in a closed state under control of a voltage from the first node; and the pull-down control sub-circuit sets the first clock under control of a first clock signal end The clock signal of the signal terminal is output to the pull-down node.
  • FIG. 1 is a schematic structural diagram of a shift register according to some embodiments of the present disclosure
  • FIG. 2 is a schematic structural diagram of still another shift register according to some embodiments of the present disclosure.
  • FIG. 3 is a schematic structural diagram of another shift register according to some embodiments of the present disclosure.
  • FIG. 4 is a schematic structural diagram of still another shift register according to some embodiments of the present disclosure.
  • FIG. 5 is a schematic structural diagram of still another shift register according to some embodiments of the present disclosure.
  • FIG. 6 is a schematic structural diagram of a gate driving circuit according to some embodiments of the present disclosure.
  • FIG. 7 is a schematic structural diagram of another gate driving circuit according to some embodiments of the present disclosure.
  • FIG. 8 is a timing diagram of control signals of a shift register according to some embodiments of the present disclosure.
  • FIG. 9 is a schematic diagram of potential comparison of pull-down nodes of two shift registers provided by the present disclosure.
  • FIG. 10 is a schematic structural diagram of a shift register provided by the related art.
  • FIG. 11 is a timing diagram of a control signal of a shift register provided by the related art.
  • FIG. 12 is a schematic flowchart diagram of a shift register driving method according to some embodiments of the present disclosure.
  • FIG. 13 is a schematic flowchart diagram of still another shift register driving method according to some embodiments of the present disclosure.
  • FIG. 14 is a schematic flowchart diagram of another shift register driving method according to some embodiments of the present disclosure.
  • the reset signal end of the shift register of the current stage is connected to the signal output end of the shift register of the next stage, which causes the shift register of the stage to be provided by the shift register of the next stage in the pull-down phase.
  • the signal can be completed, and when the output of the next stage shift register is abnormal, the shift register of the stage cannot be completed, and the output of the gate drive circuit is abnormal.
  • Some embodiments of the present disclosure provide a shift register, as shown in FIG. 1, comprising: a first input sub-circuit 10, a pull-up control sub-circuit 20, and a pull-down control sub-circuit 30.
  • the first input sub-circuit 10 is connected to the first signal terminal S1, the first voltage terminal V1 and the first node A.
  • the first input sub-circuit 10 is configured to output the voltage of the first signal terminal S1 to the first node A under the control of the voltage from the first voltage terminal V1.
  • the pull-up control sub-circuit 20 is connected to the first node A, the second voltage terminal V2, and the second node B.
  • the pull-up control sub-circuit 20 is configured to be in an on or off state under the control of the voltage from the first node A, and to output the voltage of the second voltage terminal V2 to the first state when the pull-up control sub-circuit 20 is in the on state.
  • Two-node B Two-node B.
  • the pull-down control sub-circuit 30 is connected to the first node A, the third voltage terminal V3, the first clock signal terminal CKB, the signal output terminal OUTPUT (hereinafter, and the drawings are all represented by Oput) and the pull-down node PD.
  • the pull-down control sub-circuit 30 is configured to output the voltage of the third voltage terminal V3 to the pull-down node PD under the control of the voltage from the first node A.
  • the pull-down control sub-circuit 30 is also configured to output the voltage of the third voltage terminal V3 to the pull-down node PD under the control of the voltage from the signal output terminal Oput.
  • the pull-down control sub-circuit 30 is further configured to output the voltage of the first clock signal terminal CKB to the pull-down node PD under the control of the voltage from the first clock signal terminal CKB.
  • the second node B is connected to the pull-up node PU.
  • the pull-up node PU is configured to control the signal output terminal Oput of the shift register to output a gate scan signal
  • the pull-down node PD is configured to stop the signal output terminal Oput to output a gate scan signal
  • the pull-up node PU is configured to control the signal output terminal Oput to output a gate scan signal, that is, the pull-up node PU is configured to output a high-level signal to the control signal output terminal Oput.
  • the pull-down node PD is configured to stop the signal output terminal Oput to output a gate scan signal, that is, the pull-down node PD is configured to output a low-level signal to the control signal output terminal Oput.
  • the pull-up node PU is configured to output a gate scan signal to the control signal output terminal Oput, that is, the pull-up node PU is configured to output a low-level signal to the control signal output terminal Oput.
  • the pull-down node PD is configured to stop the signal output terminal Oput to output a gate scan signal, that is, the pull-down node PD is configured to output a high-level signal to the control signal output terminal Oput.
  • the pull-up node PU is configured to output a high-level signal to the control signal output terminal Oput
  • the pull-down node PD is configured to control the signal output terminal Oput to output a low-level signal as an example for further explanation of the present disclosure.
  • both the pull up node PU and the pull down node PD in the shift register are generally in opposite states.
  • the pull-up node PU when the pull-up node PU is in an active state (eg, the pull-up node PU outputs a high level signal), the pull-down node PD is in an inactive state (eg, the pull-down node PD outputs a low level signal).
  • the pull-up node PU is in an inactive state (eg, the pull-up node PU outputs a low-level signal)
  • the pull-down node PD is in an active state (eg, the pull-down node PD outputs a high-level signal).
  • the pull-up node PU is connected to the output sub-circuit 70, and the output sub-circuit 70 is turned on by the voltage on the pull-up node PU to pass the signal output terminal Oput.
  • the gate scan signal is output.
  • the pull-down node PD is connected to the pull-down sub-circuit 60, and the pull-down sub-circuit 60 is turned on by the voltage on the pull-down node PD to stop the signal output terminal Oput from outputting the gate scan signal.
  • the second Node B is connected to the pull-up node PU, ie, as shown in Figure 1, the second Node B is directly connected to the pull-up node PU (the two nodes coincide as one node).
  • the second node B is connected to the pull-up node PU, that is, the second node B and the pull-up node PU are connected through other sub-circuits, so that when the sub-circuit is turned on, the second node B is enabled. Connected to the pull-up node PU.
  • the first node A and the first node are made by turning the pull-up control sub-circuit 20 in the off state.
  • the two-node B is disconnected, and the voltage of the first clock signal terminal CKB is output to the pull-down node PD by the pull-down control sub-circuit 30 of the shift register of the current stage, thereby pulling down the potential of the pull-up node PU, and lowering the level
  • the voltage is output to the signal output terminal Oput to complete the pull-down phase of the shift register. Therefore, the pull-down phase of the shift register in the present disclosure is independent of the signals output by the other stage shift registers, so that the stability of the gate driving circuit can be improved to some extent.
  • the shift register further includes a filter sub-circuit 40.
  • the filter sub-circuit 40 is connected to the second node B, the pull-up node PU, and the second voltage terminal V2.
  • the filter sub-circuit 40 is configured to filter out the noise in the voltage input to the filter sub-circuit 40 by the second node B under the control of the voltage from the second voltage terminal V2, and output it to the pull-up node PU.
  • the shift register in order to enable the shift register provided by the present disclosure to enable forward scanning and reverse scanning, as shown in FIGS. 1 and 2, the shift register further includes a second input sub-circuit 50.
  • the second input sub-circuit 50 is connected to the second signal terminal S2, the fourth voltage terminal V4 and the first node A.
  • the second input sub-circuit 50 is configured to output the voltage of the second signal terminal S2 to the first node A under the control of the voltage from the fourth voltage terminal V4.
  • the first input sub-circuit 10 and the second input sub-circuit 50 are turned on only one while the other remains off during the entire driving process.
  • a forward scan is implemented; when the second input sub-circuit 50 is turned on, and the first input sub-circuit 10 is turned off, the reverse is implemented. scanning.
  • the first input sub-circuit 10 is turned on, the second input sub-circuit 50 is turned off, reverse scanning is implemented; when the second input sub-circuit 50 is turned on, and the first input sub-circuit 10 is turned off, realizing positive Scan to.
  • the shift register further includes a pull-down sub-circuit 60 and an output sub-circuit 70.
  • the pull-down sub-circuit 60 is connected to the pull-down node PD, the second node B, the signal output terminal Oput, and the third voltage terminal V3.
  • the pull-down sub-circuit 60 is configured to output the voltage of the third voltage terminal V3 to the second node B and the signal output terminal Oput under the control of the voltage from the pull-down node PD.
  • the output sub-circuit 70 is connected to the pull-up node PU, the second clock signal terminal CK, and the signal output terminal Oput.
  • the output sub-circuit 70 is configured to output the voltage of the second clock signal terminal CK to the signal output terminal Oput under the control of the voltage from the pull-up node PU.
  • the shift register also includes an initialization sub-circuit 80.
  • the initialization sub-circuit 80 is connected to the third signal terminal S3, the second voltage terminal V2, and the pull-down node PD.
  • the initialization sub-circuit 80 is configured to output the voltage of the second voltage terminal V2 to the pull-down node PD under control of the voltage from the third signal terminal S3 for initialization.
  • the shift register provided by the present disclosure further includes a residual cancellation sub-circuit 90.
  • the residual charge eliminating sub-circuit 90 is connected to the fourth signal terminal S4, the third voltage terminal V3, the second node B, the pull-down node PD, and the signal output terminal Oput.
  • the residual current cancellation sub-circuit 90 is configured to output the voltage of the third voltage terminal V3 to the second node B and the pull-down node PD under the control of the voltage from the fourth signal terminal S4; the residual current cancellation sub-circuit 90 is further configured to The voltage of the fourth signal terminal S4 is output to the signal output terminal Oput for residual cancellation.
  • the first input sub-circuit 10 includes a first transistor T1.
  • the first transistor T1 includes a gate, a first pole, and a second pole.
  • the gate of the first transistor T1 is connected to the first signal terminal S1
  • the first electrode of the first transistor T1 is connected to the first voltage terminal V1
  • the second electrode of the first transistor T1 is connected to the first node A.
  • the pull-up control sub-circuit 20 includes a second transistor T2.
  • the second transistor T2 includes a gate, a first pole, and a second pole.
  • the gate of the second transistor T2 is connected to the first node A
  • the first pole of the second transistor T2 is connected to the second voltage terminal V2
  • the second pole of the second transistor T2 is connected to the second node B.
  • the pull-down control sub-circuit 30 includes a third transistor T3, a fourth transistor T4, and a fifth transistor T5.
  • the third transistor T3 includes a gate, a first pole, and a second pole.
  • the gate of the third transistor T3 is connected to the first clock signal terminal CKB
  • the first electrode of the third transistor T3 is connected to the first clock signal terminal CKB
  • the second electrode of the third transistor T3 is connected to the pull-down node PD.
  • the fourth transistor T4 includes a gate, a first pole, and a second pole.
  • the gate of the fourth transistor T4 is connected to the first node A
  • the first electrode of the fourth transistor T4 is connected to the pull-down node PD
  • the second pole of the fourth transistor T4 is connected to the third voltage terminal V3.
  • the fifth transistor T5 includes a gate, a first pole, and a second pole.
  • the gate of the fifth transistor T5 is connected to the signal output terminal Oput
  • the first electrode of the fifth transistor T5 is connected to the pull-down node PD
  • the second electrode of the fifth transistor T5 is connected to the third voltage terminal V3.
  • the pull-down control sub-circuit 30 further includes a sixth transistor T6.
  • the sixth transistor T6 includes a gate, a first pole, and a second pole.
  • the gate of the sixth transistor T6 is connected to the second voltage terminal V2
  • the first electrode of the sixth transistor T6 is connected to the first clock signal terminal CKB
  • the second electrode of the sixth transistor T6 is connected to the gate of the third transistor T3.
  • the pull-down control sub-circuit 30 further includes a first capacitor C1.
  • the first capacitor C1 includes a first pole and a second pole.
  • the first pole of the first capacitor C1 is connected to the pull-down node PD, and the second pole of the first capacitor C1 is connected to the third voltage terminal V3.
  • the filter sub-circuit 40 includes a seventh transistor T7.
  • the seventh transistor T7 includes a gate, a first pole, and a second pole.
  • the gate of the seventh transistor T7 is connected to the second voltage terminal V2
  • the first electrode of the seventh transistor T7 is connected to the second node B
  • the second electrode of the seventh transistor T7 is connected to the pull-up node PU.
  • the second input sub-circuit 50 includes an eighth transistor T8.
  • the eighth transistor T8 includes a gate, a first pole, and a second pole.
  • the gate of the eighth transistor T8 is connected to the second signal terminal S2
  • the first electrode of the eighth transistor T8 is connected to the first node A
  • the second electrode of the eighth transistor T8 is connected to the fourth voltage terminal V4.
  • the pull-down sub-circuit 60 includes a ninth transistor T9 and a tenth transistor T10.
  • the ninth transistor T9 includes a gate, a first pole, and a second pole.
  • the gate of the ninth transistor T9 is connected to the pull-down node PD, the first pole of the ninth transistor T9 is connected to the second node B, and the second pole of the ninth transistor T9 is connected to the third voltage terminal V3.
  • the tenth transistor T10 includes a gate, a first pole, and a second pole.
  • the gate of the tenth transistor T10 is connected to the pull-down node PD
  • the first pole of the tenth transistor T10 is connected to the signal output terminal Oput
  • the second pole of the tenth transistor T10 is connected to the third voltage terminal V3.
  • the output sub-circuit 70 includes an eleventh transistor T11 and a second capacitor C2.
  • the second capacitor C2 includes a first pole and a second pole.
  • the first pole of the second capacitor C2 is connected to the pull-up node PU, and the second pole of the second capacitor C2 is connected to the signal output terminal Oput.
  • the eleventh transistor T11 includes a gate, a first pole, and a second pole.
  • the gate of the eleventh transistor T11 is connected to the pull-up node PU, the first electrode of the eleventh transistor T11 is connected to the second clock signal terminal CK, and the second electrode of the eleventh transistor T11 is connected to the signal output terminal Oput.
  • the initialization sub-circuit 80 includes a twelfth transistor T12.
  • the twelfth transistor T12 includes a gate, a first pole, and a second pole.
  • the gate of the twelfth transistor T12 is connected to the third signal terminal S3, the first electrode of the twelfth transistor T12 is connected to the pull-down node PD, and the second electrode of the twelfth transistor T12 is connected to the second voltage terminal V2.
  • the residuals cancellation sub-circuit 90 includes a thirteenth transistor T13, a fourteenth transistor T14, and a fifteenth transistor T15.
  • the thirteenth transistor T13 includes a gate, a first pole, and a second pole.
  • the gate of the thirteenth transistor T13 is connected to the fourth signal terminal S4, the first pole of the thirteenth transistor T13 is connected to the pull-down node PD, and the second pole of the thirteenth transistor T13 is connected to the third voltage terminal V3.
  • the fourteenth transistor T14 includes a gate, a first pole, and a second pole.
  • the gate of the fourteenth transistor T14 is connected to the fourth signal terminal S4
  • the first electrode of the fourteenth transistor T14 is connected to the signal output terminal Oput
  • the second electrode of the fourteenth transistor T14 is connected to the fourth signal terminal S4.
  • the fifteenth transistor T15 includes a gate, a first pole, and a second pole.
  • the gate of the fifteenth transistor T15 is connected to the fourth signal terminal S4, the first pole of the fifteenth transistor T15 is connected to the second node B, and the second pole of the fifteenth transistor T15 is connected to the third voltage terminal V3.
  • Some embodiments of the present disclosure provide a gate drive circuit, as shown in FIGS. 6 and 7, including the above-described shift register cascaded in at least two stages.
  • the first signal terminal S1 of the first stage shift register RS1 is coupled to the start signal terminal STV.
  • the first signal terminal S1 of each stage shift register RS(n) is connected to the signal output terminal Oput of the previous stage shift register RS(n-1), wherein Is an integer greater than 1.
  • the start signal terminal STV is used to output a start signal
  • the first stage shift register RS1 of the gate drive circuit starts to scan the gate lines (G1, G2, ..., Gn) line by line after receiving the start signal. That is, in this case, the gate driving circuit performs forward scanning on the gate line.
  • the shift register when the shift register further includes the second input sub-circuit 20, as shown in FIG. 7, the second signal terminal of each stage of the shift register RS(m) except for the last stage shift register S2 is connected to the signal output terminal Oput of the next stage shift register RS(m+1), where m is an integer greater than or equal to 1.
  • the second signal terminal S2 of the last stage shift register is connected to the start signal terminal STV or the reset signal terminal (illustrated in FIG. 8 by the second signal terminal S2 of the last stage shift register being connected to the start signal terminal STV) .
  • the start signal terminal STV is used to output the start signal, and the last stage shift register starts after receiving the above start signal.
  • the gate lines (Gm...G2, G1) are progressively scanned. That is, in this case, the gate driving circuit reverse scans the gate lines.
  • the shift register when the shift register includes both the first input sub-circuit 10 and the second input sub-circuit 50, during the entire driving process.
  • the first input sub-circuit 10 and the second input sub-circuit 50 are turned on only one while the other remains off. That is, when the shift register in the gate driving circuit includes both the first input sub-circuit 10 and the second input sub-circuit 50, the gate driving circuit either performs forward scanning on the gate line or on the gate line. Perform a reverse scan (depending on the specific cascading method).
  • the first clock signal terminal CKB in the odd-numbered shift register is connected to the first clock signal line CKB'.
  • the second clock signal terminal CK is connected to the second clock signal line CK.
  • the first clock signal terminal CKB of the even-numbered shift register is connected to the second clock signal line CK', and the second clock signal terminal CK is connected to the first clock signal line CKB'.
  • the first clock signal line CKB' inputs a signal to the first clock signal terminal CKB of the odd-numbered shift register, and inputs a signal to the second clock signal terminal CK of the even-numbered shift register.
  • the second clock signal line CK' is connected to the second clock signal terminal CK input signal of the odd-numbered shift register, and the signal is input to the first clock signal terminal CKB of the even-numbered shift register.
  • Some embodiments of the present disclosure provide a display device including any of the gate drive circuits described above having the same advantageous effects as the aforementioned gate drive circuit. Since the foregoing embodiment has been described in detail for the structure and advantageous effects of the gate driving circuit, details are not described herein again.
  • the display device may at least include a liquid crystal display panel or an organic light emitting diode display panel.
  • the display panel can be applied to any display product or component such as a display, a television, a digital photo frame, a mobile phone, or a tablet.
  • the driving process of the shift register will be further described below in conjunction with the above-described gate driving circuit.
  • the transistors in the sub-circuits of the shift register provided by the embodiments of the present disclosure may be N-type transistors or P-type transistors.
  • the above transistor may be an enhancement transistor or a depletion transistor.
  • the first pole of the transistor may be a source and the second pole may be a drain. Alternatively, the first pole of the transistor may be a drain and the second pole is a source, which is not limited in the disclosure.
  • the shift register shown in FIG. 5 is combined with an image timing chart shown in FIG. 8 in an image frame (for example, U-frame, U ⁇ 1, U is a positive integer)
  • U-frame for example, U-frame, U ⁇ 1, U is a positive integer
  • the first clock signal terminal CKB and the second clock signal terminal CK are complementary signals, and the first voltage terminal V1 and the fourth voltage terminal V4 are high and low levels for controlling forward and backward scanning.
  • the following embodiment is described by taking a case where the second voltage terminal V2 constantly outputs a high level and the third voltage terminal V3 constantly outputs a low level.
  • the following embodiment takes the forward scanning as an example, that is, the first input sub-circuit 10 operates, and the second input sub-circuit 50 does not work as an example for description (ie, the first voltage terminal V1 inputs a high-level signal, and the fourth voltage Terminal V4 inputs a low level signal).
  • the driving method of the shift register in the present disclosure includes an input phase, an output phase, and a pull-down phase.
  • the driving process of the first stage shift register RS1 includes an input stage P1', an output stage P2', and a pull down stage P3'.
  • the driving process of the second stage shift register RS2 includes an input stage P1, an output stage P2, and a pull-down stage P3.
  • the output stage P2' of the first stage shift register RS1 is in the same period as the second stage shift register RS2 input stage P1; the pull-down stage P3' of the first stage shift register RS1 and the output stage of the second stage shift register RS2 P2 is the same time period.
  • the difference between the timing control of the first stage shift register RS1 and the second stage shift register RS2 in the input stage is that the first stage shift register RS1 is in the input stage P1', and the first clock signal end CKB is low, and the first The secondary shift register RS2 is in the input phase P1, and the first clock signal terminal CKB is at a high level, but both can ensure the normal operation of the gate driving circuit.
  • the shift register is in an image frame (for example, U frame, U ⁇ 1)
  • the on and off conditions of the transistors in different stages of the U is a positive integer are exemplified in detail.
  • the first voltage terminal V1 outputs a high level, so the first transistor T1 is turned on, thereby outputting the high level of the first signal terminal S1 to the first node A, controlling the voltage of the second transistor T2 to be turned on, and the voltage of the second voltage terminal V2.
  • the second transistor T2 is transmitted to the second node B. Since the second voltage terminal V2 constantly outputs a high level, the seventh transistor T7 is a normally-on transistor.
  • the high level on the second node B is filtered by the seventh transistor T7 and output to the pull-up node PU, and the high level is stored by the second capacitor C2. Under the control of the pull-up node PU high potential, the eleventh transistor T11 is turned on, the low level of the second clock signal terminal CK is to the signal output terminal Oput, and the fifth transistor T5 is controlled to be turned off.
  • the high level of the first signal terminal S1 is output to the first node A, the high level of the first node A controls the fourth transistor T4 to be turned on, and the low level of the third voltage terminal V3 is transmitted to the pull-down node PD. .
  • the sixth transistor T6 is turned on, and the high level of the first clock signal terminal CKB is output to the gate of the third transistor T3, and the third is controlled.
  • the transistor T3 is turned on, and the high level of the first clock signal terminal CKB is output to the pull-down node PD, but the voltage division of the third transistor T3, the fourth transistor T4, and the sixth transistor T6 at the pull-down node PD makes the ninth transistor T9 and the The ten-transistor T10 is still in an off state, ensuring the state of charge of the pull-up node PU.
  • the third signal terminal S3 inputs a low level to control the twelfth transistor T12 to be turned off.
  • the fourth signal terminal S4 inputs a low level signal, and controls the thirteenth transistor T13, the fourteenth transistor T14, and the fifteenth transistor T15 to be turned off.
  • the first transistor T1 is turned on, the second transistor T2 is turned on, the third transistor T3 is turned off, the fourth transistor T4 is turned on, the fifth transistor T5 is turned off, the sixth transistor T6 is turned on, and the seventh transistor T7 is turned on.
  • the eighth transistor T8 is turned off, the ninth transistor T9 is turned off, the tenth transistor T10 is turned off, the eleventh transistor T11 is turned on, the twelfth transistor T12 is turned off, the thirteenth transistor T13 is turned off, the fourteenth transistor T14 is turned off, tenth The five transistor T15 is turned off, and the signal output terminal Oput outputs a low level in the above input phase P1.
  • the first voltage terminal V1 outputs a high level, so the first transistor T1 is turned on, thereby outputting the low level of the first signal terminal S1 to the first node A, and controlling the second transistor T2 and the fourth transistor T4 to be turned off.
  • the second capacitor C2 charges the pull-up node PU at a high level stored in the input phase P1, thereby causing the eleventh transistor T11 to remain in an on state.
  • the high level of the second clock signal terminal CK is output to the signal output terminal Oput through the eleventh transistor T11, and the fifth transistor T5 is controlled to be turned on, and the low level of the third voltage terminal V3 passes through the fifth transistor T5. Transfer to the drop-down node PD.
  • the low level of the pull-down node PD controls the ninth transistor T9 and the tenth transistor T10 to be turned off.
  • the potential of the pull-up node PU is further increased (the potential of the end of the second capacitor C2 connected to the signal output terminal Oput is changed from 0 to 1 in the second
  • the potential of the pull-up node PU jumps to a high potential 1) on the basis of 1, to maintain the eleventh transistor T11 in an on state.
  • the high level of the second clock signal terminal CK can be output as a gate scan signal to the gate line connected to the signal output terminal Oput.
  • the sixth transistor T6 is turned on under the control of the high level output from the second voltage terminal V2.
  • the low level outputted by the first clock signal terminal CKB controls the third transistor T3 to be turned off.
  • the third signal terminal S3 inputs a low level to control the twelfth transistor T12 to be turned off.
  • the fourth signal terminal S4 inputs a low level, and controls the thirteenth transistor T13, the fourteenth transistor T14, and the fifteenth transistor T15 to be turned off.
  • the first transistor T1 is turned on
  • the second transistor T2 is turned off
  • the third transistor T3 is turned off
  • the fourth transistor T4 is turned off
  • the fifth transistor T5 is turned on
  • the sixth transistor T6 is turned on
  • the seventh transistor T7 is turned on.
  • the eighth transistor T8 is turned off, the ninth transistor T9 is turned off, the tenth transistor T10 is turned off, the eleventh transistor T11 is turned on, the twelfth transistor T12 is turned off, the thirteenth transistor T13 is turned off, the fourteenth transistor T14 is turned off, tenth The five transistor T15 is turned off, and the signal output terminal Oput outputs a high level in the above output phase P2 to output a gate scan signal to the gate line connected to the signal output terminal Oput.
  • the first voltage terminal V1 outputs a high level, and the first transistor T1 is turned on, thereby outputting the low level of the first signal terminal S1 to the first node A, and controlling the second transistor T2 and the fourth transistor T4 to be turned off.
  • the seventh transistor T7 and the sixth transistor T6 are turned on under the control of the high level outputted by the second voltage terminal V2, and the high level of the first clock signal terminal CKB outputs the third transistor T3 to be turned on, and the first clock is turned on.
  • the high level of the signal terminal CKB output is transmitted to the pull-down node PD.
  • the pull-down node PD controls both the ninth transistor T9 and the tenth transistor T10 to be turned on, and the potential of the second node B is pulled down to the low level of the third voltage terminal V3 through the ninth transistor T9.
  • the low level of the second node B is filtered by the seventh transistor T7 and transmitted to the pull-up node PU, that is, the potential of the pull-up node PU is pulled down to the low level of the third voltage terminal V3, and the eleventh is controlled.
  • the transistor T11 is turned off.
  • the potential of the signal output terminal Oput is pulled down to the low level of the third voltage terminal V3 by the tenth transistor T10, and the fifth transistor T5 is controlled to be turned off.
  • the first capacitor C1 stores the high level of the pull-down node PD, so that the pull-down node PD maintains a high level for a long time.
  • the third signal terminal S3 inputs a low level, and controls the twelfth transistor T12 to be turned off.
  • the fourth signal terminal S4 inputs a low level, and controls the thirteenth transistor T13, the fourteenth transistor T14, and the fifteenth transistor T15 to be turned off.
  • the first transistor T1 is turned on, the second transistor T2 is turned off, the third transistor T3 is turned on, the fourth transistor T4 is turned off, the fifth transistor T5 is turned off, the sixth transistor T6 is turned on, and the seventh transistor T7 is turned on.
  • the eighth transistor T8 is turned off, the ninth transistor T9 is turned on, the tenth transistor T10 is turned on, the eleventh transistor T11 is turned off, the twelfth transistor T12 is turned off, the thirteenth transistor T13 is turned off, the fourteenth transistor T14 is turned off, tenth The five-transistor T15 is turned off, and the signal output terminal Oput outputs a low level in the above-described pull-down phase P3.
  • the third level is controlled by the high level of the first clock signal terminal CKB.
  • the transistor T3 is turned on, and the high level of the first clock signal terminal CKB is transmitted to the pull-down node PD.
  • the sixth transistor T6 whose high level of the first clock signal terminal CKB is turned on is transmitted to the gate of the third transistor T3, and the third transistor T3 is controlled to be turned on.
  • a high level of a clock signal terminal CKB is transmitted to the pull-down node PD via the third transistor T3.
  • the voltage of the pull-down node PD is as shown by a broken line in FIG.
  • the voltage of the pull-down node PD is as shown by the solid line in FIG.
  • the pull-down node PD voltage in the shift register cannot completely maintain the high level of the first clock signal (there is a loss) because the N-type transistor is When the output level is high, there is an inevitable threshold loss, which causes the third transistor T3 to fail to reach the full high-level flat amplitude value when charging the pull-down node PD, and there is a certain loss.
  • the pull-down node PD voltage in the shift register can completely maintain the high level of the first clock signal.
  • the sixth transistor T6 and the third transistor T3 are coupled, so that the gate of the third transistor T3 is bootstrapped, so that the high level of the first clock signal terminal CKB can be fully pulled down through the third transistor T3.
  • the node PD is charged to avoid threshold loss, and the high level lossless input of the first clock signal terminal CKB is implemented to the pull-down node PD.
  • the function of boosting the driving voltage and waveform shaping of the voltage signal on the pull-down node PD is ensured, thereby ensuring the continuous stability of the voltage signal on the pull-down node PD, and improving the performance and stability of the display gate driving.
  • the low level output of the shift register in the above-mentioned pull-down phase cannot be realized by the shift register of the current stage, but depends on the shift register of the next stage (ie, OputN+1 end).
  • the high level of the output is completed (ie, transistor M1 in Figure 10 remains on until the high level of the shift register output of the next stage arrives).
  • the reset of the shift register of the current stage in the pull-down phase cannot be realized, resulting in subsequent interlock output abnormality.
  • the signal output terminal OputN-1 of the upper shift register is connected to the gate of the corresponding transistor in the shift register of the present stage in comparison with FIG.
  • the second transistor T2 is added, and the signal output terminal Oput of the previous stage shift register is connected with the shift register of the current stage (the signal output end of the shift register of the previous stage) Oput is not connected to the gate of the first transistor T1 of the shift register of the present stage.)
  • the reset and hold reset of the shift register in the pull-down phase are all completed by the third transistor T3.
  • the fourth transistor T4 of the current stage since the fourth transistor T4 of the current stage remains in the off state after inputting the low level, that is, the first node A maintains the low level after the input phase (as shown in point A in FIG. 8).
  • the timing shows that the high level of the first clock signal terminal CKB can be transmitted from the third transistor T3 to the pull-down node PD to pull up the potential of the pull-down node PD, and pull down the potential of the pull-up node PU, thereby realizing the pull-down The purpose of the phase reset. Avoiding the next level of abnormal output makes this level unable to reset, avoiding subsequent chain abnormal output, and improving the performance and stability of the display gate drive.
  • the third signal terminal S3 outputs a high level, controls the twelfth transistor T12 to be turned on, and outputs the high level of the second voltage terminal V2 to the pull-down node PD.
  • the pull-down node PD controls the ninth transistor T9 and the tenth transistor T10 to be turned on, the ninth transistor T9 outputs the low level of the third voltage terminal V3 to the pull-up node PU, and the tenth transistor T10 outputs the low level of the third voltage terminal V3.
  • the voltages of the pull-up node PU and the signal output terminal Oput are both pulled low, and the initialization of the shift register is completed.
  • the first transistor T1 is turned on, the second transistor T2 is turned off, the third transistor T3 is turned off, the fourth transistor T4 is turned off, the fifth transistor T5 is turned off, the sixth transistor T6 is turned on, and the seventh transistor is turned on.
  • T7 is turned on, the eighth transistor T8 is turned off, the ninth transistor T9 is turned on, the tenth transistor T10 is turned on, the eleventh transistor T11 is turned off, the twelfth transistor T12 is turned on, the thirteenth transistor T13 is turned off, the fourteenth transistor T14 is turned off,
  • the fifteen transistor T15 is turned off, and the signal output terminal Oput outputs a low level in the above initialization phase P4.
  • the fourth signal terminal S4 outputs a high level, and controls the thirteenth transistor T13, the fourteenth transistor T14, and the fifteenth transistor T15 to be turned on.
  • the fourteenth transistor T14 is turned on, and the high level of the fourth signal terminal S4 is output to the signal output terminal Oput, so that the signal output terminal Oput outputs a high level, so that the entire circuit is discharged, and the residual signal remains in the circuit due to the abnormal display.
  • the charge is a high level, and controls the thirteenth transistor T13, the fourteenth transistor T14, and the fifteenth transistor T15 to be turned on.
  • the fourteenth transistor T14 is turned on, and the high level of the fourth signal terminal S4 is output to the signal output terminal Oput, so that the signal output terminal Oput outputs a high level, so that the entire circuit is discharged, and the residual signal remains in the circuit due to the abnormal display. The charge.
  • the fifteenth transistor T15 is turned on, and the low level outputted by the third voltage terminal V3 is output to the pull-up node PU to prevent other signals from affecting the potential of the signal output terminal Oput.
  • the thirteenth transistor T13 is turned on, and the low level output from the third voltage terminal V3 is output to the pull-down node PD to prevent other signals from affecting the potential of the pull-down node PD.
  • the fourteenth transistor T14 can still work alone to complete the residual elimination task.
  • the residual current cancellation sub-circuit 90 provided by the present disclosure includes a thirteenth transistor T13, a fourteenth transistor T14 and a fifteenth transistor T15.
  • the three transistors cooperate to maintain the pull-up node PU at a high level, thereby improving the display. Gate drive performance and stability.
  • the first transistor T1 is turned on, the second transistor T2 is turned off, the third transistor T3 is turned off, the fourth transistor T4 is turned off, the fifth transistor T5 is turned off, the sixth transistor T6 is turned on, and the seventh transistor
  • the transistor T7 is turned on, the eighth transistor T8 is turned off, the ninth transistor T9 is turned off, the tenth transistor T10 is turned off, the eleventh transistor T11 is turned off, the twelfth transistor T12 is turned off, the thirteenth transistor T13 is turned on, and the fourteenth transistor T14 is turned on,
  • the fifteenth transistor T15 is turned on, and the signal output terminal Oput outputs a high level in the above-described residual charge eliminating phase P5.
  • the operation of the shift register described above is an example in which the gate drive circuit formed by cascading the plurality of shift registers is forward-scanned as an example.
  • reverse scanning in the shift register shown in FIGS. 3, 4, and 5, in the input phase P1, the first transistor T1 is turned off, and the eighth transistor T8 is turned on.
  • the driving method includes steps 10-30 (S10-S30):
  • the first input sub-circuit 10 Under the control of the voltage from the first voltage terminal V1, the first input sub-circuit 10 outputs the voltage input by the first signal terminal S1 to the first node A to control the pull-up control sub-circuit 20 through the first node A. Turning on, the voltage of the second voltage terminal V2 is output to the pull-up node PU via the second node B. At the same time, under the control of the voltage from the first node A, the pull-down control sub-circuit 30 outputs the voltage of the third voltage terminal V3 to the pull-down node PD.
  • the shift register unit further includes the filter sub-circuit 40, in the input phase P1:
  • the first input sub-circuit 10 Under the control of the first voltage terminal V1, the first input sub-circuit 10 outputs the voltage input by the first signal terminal S1 to the first node A, and the first node A controls the pull-up control sub-circuit 20 to be turned on, and the second voltage terminal is turned on.
  • the voltage of V2 is output to the second node B, and the filter sub-circuit 40 filters out the noise in the voltage input from the second node B and outputs it to the pull-up node PU.
  • the shift register further includes a pull-down sub-circuit 60, an initialization sub-circuit 80, and a residual-cancellation sub-circuit 90
  • the pull-down sub-circuit 60, the initialization sub-circuit 80, and the residual-cancellation sub-circuit 90 Both are closed.
  • the structure of each sub-circuit in the above shift register is as shown in FIG. 5, and the transistors in each sub-circuit are N-type transistors.
  • the first signal terminal S1 inputs a high level
  • the first clock signal terminal CKB inputs a high level
  • the second clock signal terminal CK inputs a low level
  • the third signal terminal S3 inputs a low level
  • the fourth signal terminal S4 inputs a low level
  • the first voltage terminal V1 inputs a high level
  • the second voltage terminal V2 inputs a high level
  • the third voltage terminal V3 inputs a low level
  • the fourth voltage terminal V4 inputs a low level
  • the fourth voltage terminal V4 inputs a low level
  • the pull node PU is at a high level
  • the pull-down node PD is at a low level
  • the signal output terminal Oput outputs a low level.
  • the first transistor T1 since the first voltage terminal V1 outputs a high level, the first transistor T1 is turned on, thereby outputting the high level of the first signal terminal S1 to the first node A, and controlling the second transistor T2 to be turned on.
  • the voltage of the two voltage terminals V2 is transmitted to the second node B via the second transistor T2.
  • the seventh transistor T7 Since the second voltage terminal V2 outputs a high level, the seventh transistor T7 is a normally-on transistor, and the high level on the second node B is filtered by the seventh transistor T7 and output to the pull-up node PU, and passes through the second capacitor C2. This high level is stored. Under the control of the pull-up node PU high level, the eleventh transistor T11 is turned on, the low level of the second clock signal terminal CK is output to the signal output terminal Oput, and the fifth transistor T5 is controlled to be turned off.
  • the high level of the first node A controls the fourth transistor T4 to be turned on, and the low level of the third voltage terminal V3 is transmitted to the pull-down node PD.
  • the high level is output.
  • the sixth transistor T6 is turned on, outputs the high level of the first clock signal terminal CKB to the gate of the third transistor T3, controls the third transistor T3 to be turned on, and sets the high level of the first clock signal terminal CKB.
  • the third signal terminal S3 is input with a low level to control the twelfth transistor T12 to be turned off, and the fourth signal terminal S4 is input to a low level, and the thirteenth transistor T13, the fourteenth transistor T14, and the fifteenth transistor T15 are controlled to be turned off.
  • the pull-up control sub-circuit 20 under the control of the voltage from the first node A, the pull-up control sub-circuit 20 is turned off; and under the control of the voltage from the signal output terminal Oput, the pull-down control sub-circuit 30 will be the third voltage terminal V3 The voltage is output to the pull-down node PD.
  • the output sub-circuit 70 In the output phase P2, under the control of the voltage from the pull-up node PU, the output sub-circuit 70 outputs the clock signal (high potential) of the second clock signal terminal CK to the signal output terminal Oput, and the signal output terminal Oput outputs Gate scan signal.
  • the pull-down control sub-circuit 30 outputs the low level of the third voltage terminal V3 to the pull-down node PD, and controls the pull-down sub-circuit 60 to be turned off. Both the initialization sub-circuit 80 and the residual cancellation sub-circuit 90 are turned off.
  • each sub-circuit in the above shift register is as shown in FIG. 5, and the transistors in each sub-circuit are N-type transistors.
  • the first signal terminal S1 inputs a low level
  • the second clock signal terminal CK inputs a high level
  • the first clock signal terminal CKB inputs a low level
  • the third signal terminal S3 inputs a low level
  • the fourth signal terminal S4 inputs a low level
  • the first voltage terminal V1 inputs a high level
  • the second voltage terminal V2 inputs a high level
  • the third voltage terminal V3 inputs a low level
  • the fourth voltage terminal V4 inputs a low level
  • the fourth voltage terminal V4 inputs a low level
  • the pull node PU is at a high level
  • the pull-down node PD is at a low level
  • the signal output terminal Oput outputs a high level.
  • the first transistor T1 since the first voltage terminal V1 outputs a high level, the first transistor T1 is turned on, thereby outputting the low level of the first signal terminal S1 to the first node A, and controlling the second transistor T2 and the fourth transistor T4. cutoff.
  • the second capacitor C2 charges the pull-up node PU with a high level stored in the input phase P1, so that the eleventh transistor T11 remains in an on state.
  • the high level of the second clock signal terminal CK is output to the signal output terminal Oput through the eleventh transistor T11, and the fifth transistor T5 is controlled to be turned on, and the low level of the third voltage terminal V3 passes through the fifth transistor T5.
  • the pull-down node PD controls the ninth transistor T9 and the tenth transistor T10 to be turned off.
  • the potential of the pull-up node PU is further increased to maintain the eleventh transistor T11 in an on state, so that the high level of the second clock signal terminal CK can be used as The gate scan signal is output to a gate line connected to the signal output terminal Oput.
  • the sixth transistor T6 is turned on, the first clock signal outputs a low level, and the third transistor T3 is controlled to be turned off.
  • the third signal terminal S3 is input with a low level to control the twelfth transistor T12 to be turned off, and the fourth signal terminal S4 is input to a low level, and the thirteenth transistor T13, the fourteenth transistor T14, and the fifteenth transistor T15 are controlled to be turned off.
  • the pull-up control sub-circuit 20 under the control of the voltage from the first node A, the pull-up control sub-circuit 20 is in a closed state; and under the control of the first clock signal terminal CKB, the pull-down control sub-circuit 30 will be the first clock signal terminal CKB.
  • the clock signal (high potential) is output to the pull-down node PD.
  • the pull-down sub-circuit 60 In the pull-down phase P3, under the voltage control from the pull-down node PD, the pull-down sub-circuit 60 outputs the voltage input from the third voltage terminal V3 to the second node B, and the filter sub-circuit 40 inputs the voltage input to the second node B. After the clutter is filtered, it is output to the pull-up node PU, and the control output sub-circuit 70 is turned off. The pull-down sub-circuit 60 also outputs the voltage input from the third voltage terminal V3 to the signal output terminal Oput.
  • the output sub-circuit 70, the initialization sub-circuit 80, and the residual elimination sub-circuit 90 are all turned off.
  • each sub-circuit in the above shift register is as shown in FIG. 5, and the transistors in each sub-circuit are N-type transistors.
  • the first signal terminal S1 inputs a low level
  • the second clock signal terminal CK inputs a low level
  • the first clock signal terminal CKB inputs a high level
  • the third signal terminal S3 inputs a low level
  • the fourth signal terminal S4 inputs a low level
  • the first voltage terminal V1 inputs a high level
  • the second voltage terminal V2 inputs a high level
  • the third voltage terminal V3 inputs a low level
  • the fourth voltage terminal V4 inputs a low level
  • the fourth voltage terminal V4 inputs a low level
  • the pull node PU is at a low level
  • the pull-down node PD is at a high level
  • the signal output terminal Oput outputs a low level.
  • the first transistor T1 since the first voltage terminal V1 outputs a high level, the first transistor T1 is turned on, thereby outputting the low level of the first signal terminal S1 to the first node A, and controlling the second transistor T2 and the fourth transistor T4. cutoff.
  • the seventh transistor T7 and the sixth transistor T6 are turned on under the control of the high level outputted by the second voltage terminal V2, and the high level of the first clock signal terminal CKB outputs the third transistor T3 to be turned on, and the first clock is turned on.
  • the high level output of the signal terminal CKB is output to the pull-down node PD.
  • the pull-down node PD controls both the ninth transistor T9 and the tenth transistor T10 to be turned on, and the potential of the second node B is pulled down to the low level of the third voltage terminal V3 through the ninth transistor T9.
  • the low level of the second node B is filtered by the seventh transistor T7 and transmitted to the pull-up node PU, that is, the potential of the pull-up node PU is pulled down to the low level of the third voltage terminal V3, and the eleventh transistor T11 is controlled. cutoff.
  • the potential of the signal output terminal Oput is pulled down to the low level of the third voltage terminal V3 by the tenth transistor T10, and the fifth transistor T5 is controlled to be turned off.
  • the first capacitor C1 stores the high level of the pull-down node PD, so that the pull-down node PD maintains a high level for a long time.
  • the third signal terminal S3 inputs a low level to control the twelfth transistor T12 to be turned off
  • the fourth signal terminal S4 inputs a low level, and controls the thirteenth transistor T13, the fourteenth transistor T14, and the fifteenth transistor T15 to be turned off.
  • the driving method of the shift register further includes step 40 (S40):
  • the initialization sub-circuit 80 outputs the voltage of the second voltage terminal V2 to the pull-down node PD; under the control of the voltage from the pull-down node PD, the pull-down sub-circuit 60 will The voltage input from the three voltage terminals V3 is output to the second node B, and the filter sub-circuit 40 filters out the noise in the voltage input by the second node B and outputs it to the pull-up node PU; the pull-down sub-circuit 60 also has the third voltage terminal V3. The input pull-down signal is output to the signal output terminal Oput.
  • the initialization sub-circuit 80, the pull-down sub-circuit 60, and the filter sub-circuit 40 are turned on.
  • each sub-circuit in the above shift register is as shown in FIG. 5, and the transistors in each sub-circuit are N-type transistors.
  • the first signal terminal S1 inputs a low level
  • the second clock signal terminal CK inputs a low level
  • the first clock signal terminal CKB inputs a low level
  • the third signal terminal S3 inputs a high level
  • a fourth signal terminal S3 inputs a high level
  • a fourth The signal terminal S4 inputs a low level
  • the first voltage terminal V1 inputs a high level
  • the second voltage terminal V2 inputs a high level
  • the third voltage terminal V3 inputs a low level
  • the fourth voltage terminal V4 inputs a low level
  • the node PU is at a low level
  • the pull-down node PD is at a high level
  • the signal output terminal Oput outputs a low level.
  • the third signal terminal S3 outputs a high level, controls the twelfth transistor T12 to be turned on, outputs the high level of the second voltage terminal V2 to the pull-down node PD, and the pull-down node PD controls the ninth transistor T9 and the tenth transistor T10. Open.
  • the ninth transistor T9 outputs the low level of the third voltage terminal V3 to the pull-up node PU
  • the tenth transistor T10 outputs the low level of the third voltage terminal V3 to the signal output terminal Oput, and pulls up the node PU and the signal output terminal.
  • the voltage of Oput is pulled low to complete the initialization of the shift register.
  • the gate driving circuit is turned off each time, as shown in FIG. 14, the driving method of the shift register further includes step 50 (S50):
  • the residual current eliminating sub-circuit 90 outputs the voltage of the third voltage terminal V3 to the pull-down node PD and the second node B, and the filter sub-circuit 40 inputs the voltage of the second node B.
  • the clutter in the filter is output to the pull-up node PU; the residual-cancellation sub-circuit 90 also outputs the voltage of the fourth signal terminal S4 to the signal output terminal Oput.
  • the remnant canceling sub-circuit 90, the pull-down sub-circuit 60, and the filter sub-circuit 40 are turned on.
  • each sub-circuit in the above shift register is as shown in FIG. 5, and the transistors in each sub-circuit are N-type transistors.
  • the first signal terminal S1 inputs a low level
  • the second clock signal terminal CK inputs a low level
  • the first clock signal terminal CKB inputs a high level
  • the third signal terminal S3 inputs a low level.
  • the fourth signal terminal S4 inputs a high level
  • the first voltage terminal V1 inputs a high level
  • the second voltage terminal V2 inputs a high level
  • the third voltage terminal V3 inputs a low level
  • the fourth voltage terminal V4 inputs a low level.
  • the fourth signal terminal S4 outputs a high level, and controls the thirteenth transistor T13, the fourteenth transistor T14, and the fifteenth transistor T15 to be turned on.
  • the fourteenth transistor T14 is turned on to output the high level of the fourth signal terminal S4 to the signal output terminal Oput.
  • the fifteenth transistor T15 turns on the output of the low level output from the third voltage terminal V3 to the pull-up node PU.
  • the thirteenth transistor T13 turns on a low level outputted from the third voltage terminal V3 to the pull-down node PD, and the pull-down node PD controls the ninth transistor T9 and the tenth transistor T10 to be turned off.
  • the above is schematically illustrated by the first input sub-circuit 10 being turned on and the gate driving circuit performing forward scanning. At this time, even if the second input sub-circuit 50 is included in the shift register, the first input sub-circuit 10 is turned on. Next, the second input sub-circuit 50 also remains off.
  • the shift register includes the second input sub-circuit 50
  • the first input sub-circuit 10 is turned off, and the second input sub-circuit 50 is turned on, that is, the fourth voltage end.
  • V4 inputs a high level
  • the first voltage terminal V1 inputs a low level
  • other signals do not change.
  • the difference between the reverse scan and the forward scan is that, in the input phase P1, the second input sub-circuit 50 inputs the second signal terminal S2 under the control of the voltage from the fourth voltage terminal V4.
  • the voltage is output to the first node A to be turned on by the voltage control of the first node A by the pull-up control sub-circuit 20, and the voltage of the second voltage terminal V2 is output to the pull-up node PU via the second node B;
  • the pull-down control sub-circuit 30 Under the control of the voltage of a node A, the pull-down control sub-circuit 30 outputs the voltage of the third voltage terminal V3 to the pull-down node PD.
  • the input phase P1, the output phase P2, and the pull-down phase P3 are included in each image frame.
  • the initialization phase it is generally set at the beginning or end of each image frame.
  • the residual elimination phase it is performed each time the gate drive circuit is turned off.
  • the driving method of the shift register provided by the embodiment of the present disclosure has the same beneficial effects as the above-described shift register, and details are not described herein again.

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Abstract

移位寄存器，包括：第一输入子电路10连接到第一信号端S1、第一电压端V1和第一节点A，第一输入子电路10配置为将第一信号端S1的电压输出至第一节点A；上拉控制子电路20连接到第一节点A、第二电压端V2和第二节点B，上拉控制子电路20配置为在第一节点A的电压控制下，处于开启或者关闭状态，且在上拉控制子电路20处于开启状态时，将第二电压端V2的电压输出至第二节点B；下拉控制子电路30连接到第一节点A、第三电压端V3、第一时钟信号端CKB、信号输出端Oput和下拉节点PD，下拉控制子电路30配置为在第一节点A的电压控制下，将第三电压端V3的电压输出至下拉节点PD；在信号输出端Oput的电压控制下，将第三电压端V3的电压输出至下拉节点PD；在第一时钟信号端CKB的电压控制下，将第一时钟信号端CKB的电压输出至下拉节点PD。

Description

移位寄存器、栅极驱动电路及驱动方法、显示装置
本申请要求于2017年12月8日提交中国专利局、申请号为201711299235.5、申请名称为“移位寄存器单元、栅极驱动电路及驱动方法、显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种移位寄存器、栅极驱动电路及驱动方法、显示装置。
背景技术
随着显示技术的不断提高，人们对于显示装置的要求也在不断提高。为了实现低成本和窄边框，通常采用GOA(Gate Driver on Array，集成栅极驱动电路)技术。利用GOA技术将栅极驱动电路集成在显示面板的阵列基板上，从而可以省掉栅极驱动IC(Integrated Circuit，集成电路)。
发明内容
本公开的一些实施例提供一种移位寄存器，包括：第一输入子电路、上拉控制子电路和下拉控制子电路；所述第一输入子电路，连接到第一信号端、第一电压端和第一节点，所述第一输入子电路配置为在来自所述第一电压端的电压的控制下，将所述第一信号端的电压输出至所述第一节点；所述上拉控制子电路，连接到所述第一节点、第二电压端和第二节点，所述上拉控制子电路配置为在来自所述第一节点的电压的控制下，处于开启或者关闭状态，且在所述上拉控制子电路处于开启状态时，将所述第二电压端的电压输出至所述第二节点；所述下拉控制子电路，连接到所述第一节点、第三电压端、第一时钟信号端、所述信号输出端和所述下拉节点，所述下拉控制子电路配置为在来自所述第一节点的电压的控制下，将所述第三电压端的电压输出至所述下拉节点；在来自所述信号输出端的电压的控制下，将所述第三电压端的电压输出至所述下拉节点；在来自所述第一时钟信号端的电压的控制下，将所述第一时钟信号端的电压输出至所述下拉节点；其中，所述第二节点与上拉节点相连接。
在一些实施例中，所述上拉节点配置为控制所述移位寄存器的信号输 出端输出栅极扫描信号，所述下拉节点配置为停止所述信号输出端输出栅极扫描信号。
在一些实施例中，所述移位寄存器还包括：滤波子电路；所述滤波子电路，连接到所述第二节点、所述上拉节点、所述第二电压端，所述滤波子电路配置为在来自所述第二电压端的电压的控制下，将所述第二节点输入至所述滤波子电路的电压中的杂波滤除后输出至所述上拉节点。
在一些实施例中，所述移位寄存器还包括：第二输入子电路；所述第二输入子电路，连接到第二信号端、第四电压端和所述第一节点，所述第二输入子电路配置为在来自所述第四电压端的电压的控制下，将所述第二信号端的电压输出至所述第一节点。
在一些实施例中，所述移位寄存器还包括：下拉子电路和输出子电路；所述下拉子电路，连接到所述下拉节点、所述第二节点、所述信号输出端和所述第三电压端，所述下拉子电路配置为在来自所述下拉节点的电压的控制下，将所述第三电压端的电压输出至所述第二节点和所述信号输出端；所述输出子电路，连接到所述上拉节点、第二时钟信号端、所述信号输出端，所述输出子电路配置为在来自所述上拉节点的电压的控制下，将所述第二时钟信号端的电压输出至所述信号输出端。
在一些实施例中，所述移位寄存器还包括：初始化子电路；所述初始化子电路，连接到第三信号端、所述第二电压端和所述下拉节点，所述初始化子电路配置为在来自所述第三信号端的电压的控制下，将所述第二电压端的电压输出至所述下拉节点。
在一些实施例中，所述移位寄存器还包括：残荷消除子电路；所述残荷消除子电路，连接到第四信号端、所述第三电压端、所述第二节点、所述下拉节点和所述信号输出端，所述残荷消除子电路配置为在来自所述第四信号端的电压的控制下，将所述第三电压端的电压输出至所述第二节点和所述下拉节点，所述残荷消除子电路还配置为将所述第四信号端的电压输出至所述信号输出端。
在一些实施例中，所述第一输入子电路包括第一晶体管；所述第一晶体管的栅极连接到所述第一信号端，第一极连接到所述第一电压端，第二极连接到所述第一节点。
在一些实施例中，所述上拉控制子电路包括第二晶体管；所述第二晶体管的栅极连接到所述第一节点，第一极连接到所述第二电压端，第二极 连接到所述第二节点。
在一些实施例中，所述下拉控制子电路包括第三晶体管、第四晶体管、第五晶体管；所述第三晶体管的栅极连接到所述第一时钟信号端，第一极连接到所述第一时钟信号端，第二极连接到所述下拉节点；所述第四晶体管的栅极连接到所述第一节点，第一极连接到所述下拉节点，第二极连接到所述第三电压端；所述第五晶体管的栅极连接到所述信号输出端，第一极连接到所述下拉节点，第二极连接到所述第三电压端。
在一些实施例中，所述下拉控制子电路还包括第六晶体管；所述第六晶体管的栅极连接到所述第二电压端，第一极连接到所述第一时钟信号端，第二极连接到所述第三晶体管的栅极。
在一些实施例中，所述下拉控制子电路还包括第一电容；所述第一电容的第一极连接到所述下拉节点，第二极连接到所述第三电压端。
在一些实施例中，所述移位寄存器还包括滤波子电路的情况下，所述滤波子电路包括第七晶体管；所述第七晶体管的栅极连接到所述第二电压端，第一极连接到所述第二节点，第二极连接到所述上拉节点。
在一些实施例中，所述移位寄存器还包括第二输入子电路的情况下，所述第二输入子电路包括第八晶体管；所述第八晶体管的栅极连接到所述第二信号端，第一极连接到所述第一节点，第二极连接到所述第四电压端。
在一些实施例中，所述下拉子电路包括第九晶体管和第十晶体管，所述输出子电路包括第十一晶体管和第二电容；所述第九晶体管的栅极连接到所述下拉节点，第一极连接到所述第二节点，第二极连接到所述第三电压端；所述第十晶体管的栅极连接到所述下拉节点，第一极连接到所述信号输出端，第二极连接到所述第三电压端；所述第二电容的第一极连接到所述上拉节点，第二极连接到所述信号输出端；所述第十一晶体管的栅极连接到所述上拉节点，第一极连接到所述第二时钟信号端，第二极连接到所述信号输出端。
在一些实施例中，所述移位寄存器还包括初始化子电路的情况下，所述初始化子电路包括第十二晶体管；所述第十二晶体管的栅极连接到所述第三信号端，第一极连接到所述下拉节点，第二极连接到所述第二电压端。
在一些实施例中，所述移位寄存器还包括残荷消除子电路的情况下，所述残荷消除子电路包括第十三晶体管、第十四晶体管和第十五晶体管；所述第十三晶体管的栅极连接到所述第四信号端，第一极连接到所述下拉 节点，第二极连接到所述第三电压端；所述第十四晶体管的栅极连接到所述第四信号端，第一极连接到所述信号输出端，第二极连接到所述第四信号端；所述第十五晶体管的栅极连接到所述第四信号端，第一极连接到所述第二节点，第二极连接到所述第三电压端。
本公开的一些实施例提供一种栅极驱动电路，包括至少两级级联的如第一方面所述的移位寄存器；第一级移位寄存器的第一信号端与起始信号端相连接；除了所述第一级移位寄存器以外，每一级移位寄存器的第一信号端与其上一级移位寄存器的信号输出端相连接。
在一些实施例中，所述移位寄存器还包括第二信号输入子电路的情况下；除了最后一级移位寄存器以外，每一级移位寄存器的第二信号端与其下一级移位寄存器的信号输出端相连接；所述最后一级移位寄存器的第二信号端连接所述起始信号端，或者复位信号端。在一些实施例中，所述移位寄存器包括输出子电路的情况下；奇数级的移位寄存器中第一时钟信号端与第一时钟信号线连接，第二时钟信号端与第二时钟信号线连接；偶数级的移位寄存器中第一时钟信号端与所述第二时钟信号线连接，第二时钟信号端与所述第一时钟信号线连接。
本公开的一些实施例还提供一种显示装置，包括第二方面所述的栅极驱动电路。
本公开的一些实施例提供一种用于驱动上述的移位寄存器的驱动方法，包括：输入阶段：在来自第一电压端的控制下，第一输入子电路将第一信号端输入的电压输出至第一节点，以通过所述第一节点的电压控制上拉控制子电路开启，将第二电压端的电压经第二节点输出至上拉节点；同时，在来自所述第一节点的电压的控制下，下拉控制子电路将第三电压端的电压输出至下拉节点；输出阶段：在来自所述第一节点的电压的控制下，使所述上拉控制子电路处于关闭状态；并在来自信号输出端的电压的控制下，所述下拉控制子电路将所述第三电压端的电压输出至所述下拉节点；下拉阶段：在来自所述第一节点的电压的控制下，使所述上拉控制子电路处于关闭状态；并在第一时钟信号端的控制下，所述下拉控制子电路将所述第一时钟信号端的时钟信号输出至下拉节点。
在一些实施例中，所述移位寄存器包括滤波子电路、下拉子电路和输出子电路的情况下；在所述输入阶段，所述方法还包括：所述滤波子电路将所述第二节点输入的电压中的杂波滤除后输出至所述上拉节点。在所述 输出阶段，所述方法还包括：在来自所述上拉节点的电压的控制下，所述输出子电路将第二时钟信号端的时钟信号输出至信号输出端，所述信号输出端输出栅极扫描信号。在所述下拉阶段，所述方法还包括：在来自所述下拉节点的电压的控制下，下拉子电路将第三电压端的电压输出至所述第二节点，所述滤波子电路将所述第二节点输入的电压中的杂波滤除后输出至所述上拉节点，控制所述输出子电路关闭。所述下拉子电路还将所述第三电压端的电压输出至所述信号输出端。
在一些实施例中，所述移位寄存器单元包括初始化子电路和残荷消除子电路。所述方法还包括：初始化阶段：在来自第三信号端的信号的控制下，所述初始化子电路将所述第二电压端的电压输出至所述下拉节点。在来自所述下拉节点的电压的控制下，下拉子电路将所述第三电压端的电压输出至所述第二节点，所述滤波子电路将所述第二节点输入的电压中的杂波滤除后输出至所述上拉节点。所述下拉子电路还将所述第三电压端输入的下拉信号输出至所述信号输出端。残荷消除阶段：在第四信号端的控制下，所述残荷消除子电路将所述第三电压端的电压输出至所述下拉节点和所述第二节点。所述滤波子电路将来自所述第二节点的电压中的杂波滤除后输出至所述上拉节点；所述残荷消除子电路还将所述第四信号端的电压输出至所述信号输出端。
本公开的一些实施例提供一种用于驱动上述的移位寄存器的驱动方法，其中，所述移位寄存器包括第二输入子电路的情况下；所述驱动方法包括：输入阶段：在来自第四电压端的电压的控制下，第二输入子电路将第二信号端输入的电压输出至所述第一节点，以通过所述第一节点的电压控制上拉控制子电路开启，将第二电压端的电压经第二节点输出至上拉节点。同时，在来自所述第一节点的电压的控制下，下拉控制子电路将第三电压端的电压输出至下拉节点。输出阶段：在来自所述第一节点的电压的控制下，使所述上拉控制子电路处于关闭状态；并在来自信号输出端的电压的控制下，所述下拉控制子电路将所述第三电压端的电压输出至所述下拉节点。下拉阶段：在来自所述第一节点的电压的控制下，使所述上拉控制子电路处于关闭状态；并在第一时钟信号端的控制下，所述下拉控制子电路将所述第一时钟信号端的时钟信号输出至下拉节点。
附图说明
为了更清楚地说明本公开实施例或相关技术中的技术方案，下面将对 实施例或相关技术描述中所需要使用的附图作简单地介绍。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开的一些实施例提供的一种移位寄存器的结构示意图；
图2为本公开的一些实施例提供的再一种移位寄存器的结构示意图；
图3为本公开的一些实施例提供的另一种移位寄存器的结构示意图；
图4为本公开的一些实施例提供的又一种移位寄存器的结构示意图；
图5为本公开的一些实施例提供的又一种移位寄存器的结构示意图；
图6为本公开的一些实施例提供的一种栅极驱动电路的结构示意图；
图7为本公开的一些实施例提供的另一种栅极驱动电路的结构示意图；
图8为本公开的一些实施例提供的一种移位寄存器的控制信号时序图；
图9为本公开提供的两种移位寄存器的下拉节点的电位对比示意图；
图10为相关技术提供的一种移位寄存器的结构示意图；
图11为相关技术提供的一种移位寄存器的控制信号紊乱时的时序图；
图12为本公开的一些实施例提供的一种移位寄存器驱动方法的流程示意图；
图13为本公开的一些实施例提供的再一种移位寄存器驱动方法的流程示意图；
图14为本公开的一些实施例提供的另一种移位寄存器驱动方法的流程示意图。
具体实施方式
下面将结合附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
相关技术中的栅极驱动电路，本级移位寄存器的复位信号端与下一级移位寄存器的信号输出端相连接，这使得本级移位寄存器在下拉阶段依靠下一级移位寄存器提供的信号才能完成，而当下一级移位寄存器输出异常时，会导致本级移位寄存器无法完成下拉阶段的工作，进而导致栅极驱动 电路输出异常。
本公开的一些实施例提供一种移位寄存器，如图1所示，包括：第一输入子电路10、上拉控制子电路20和下拉控制子电路30。
第一输入子电路10，连接到第一信号端S1、第一电压端V1和第一节点A。第一输入子电路10配置为在来自第一电压端V1的电压的控制下，将第一信号端S1的电压输出至第一节点A。
上拉控制子电路20，连接到第一节点A、第二电压端V2和第二节点B。上拉控制子电路20配置为在来自第一节点A的电压的控制下，处于开启或者关闭状态，且在上拉控制子电路20处于开启状态时，将第二电压端V2的电压输出至第二节点B。
下拉控制子电路30，连接到第一节点A、第三电压端V3、第一时钟信号端CKB、信号输出端OUTPUT(下文以及附图均以Oput表示)和下拉节点PD。下拉控制子电路30配置为在来自第一节点A的电压的控制下，将第三电压端V3的电压输出至下拉节点PD。下拉控制子电路30还配置为在来自信号输出端Oput的电压的控制下，将第三电压端V3的电压输出至下拉节点PD。下拉控制子电路30还配置为在来自第一时钟信号端CKB的电压的控制下，将第一时钟信号端CKB的电压输出至下拉节点PD。
第二节点B与上拉节点PU连接。
上拉节点PU配置为控制移位寄存器的信号输出端Oput输出栅极扫描信号，下拉节点PD配置为停止信号输出端Oput输出栅极扫描信号。
在一些实施例中，上拉节点PU配置为控制信号输出端Oput输出栅极扫描信号，即，上拉节点PU配置为控制信号输出端Oput输出高电平信号。下拉节点PD配置为停止信号输出端Oput输出栅极扫描信号，即，下拉节点PD配置为控制信号输出端Oput输出低电平信号。在另一些实施例中，上拉节点PU配置为控制信号输出端Oput输出栅极扫描信号，即，上拉节点PU配置为控制信号输出端Oput输出低电平信号。下拉节点PD配置为停止信号输出端Oput输出栅极扫描信号，即，下拉节点PD配置为控制信号输出端Oput输出高电平信号。
以下实施例均是以，上拉节点PU配置为控制信号输出端Oput输出高电平信号，下拉节点PD配置为控制信号输出端Oput输出低电平信号为例对本公开做进一步的说明。
本领域的技术人员应当理解到，对于移位寄存器中的上拉节点PU和 下拉节点PD而言，两者一般处于相反的状态。例如，当上拉节点PU处于工作状态(例如，上拉节点PU输出高电平信号)时，下拉节点PD处于非工作状态(例如，下拉节点PD输出低电平信号)。当上拉节点PU处于非工作状态(例如，上拉节点PU输出低电平信号)时，下拉节点PD处于工作状态(例如，下拉节点PD输出高电平信号)。
在一些实施例中，如图1所示，在移位寄存器中，上拉节点PU与输出子电路70相连接，通过上拉节点PU上的电压开启输出子电路70，以通过信号输出端Oput输出栅极扫描信号。下拉节点PD与下拉子电路60相连接，通过下拉节点PD上的电压开启下拉子电路60，以停止信号输出端Oput输出栅极扫描信号。
在一些实施例中，第二节点B与上拉节点PU相连接，即，如图1所示，第二节点B与上拉节点PU直接连接(两个节点重合为一个节点)。在另一些实施例中，第二节点B与上拉节点PU相连接，即，第二节点B与上拉节点PU通过其他子电路连接，从而当该子电路导通时，使第二节点B与上拉节点PU连接。
对于本公开的实施例提供的移位寄存器，在该移位寄存器应用于栅极驱动电路的情况下，在下拉阶段，通过使上拉控制子电路20处于关闭状态而使第一节点A和第二节点B断开，可通过依靠本级移位寄存器的下拉控制子电路30将第一时钟信号端CKB的电压输出至下拉节点PD，从而拉低上拉节点PU的电位，并将低电平电压输出至信号输出端Oput，来完成移位寄存器的下拉阶段。因此，本公开中的移位寄存器的下拉阶段与其他级移位寄存器输出的信号无关，从而可一定程度的提高栅极驱动电路的稳定性。
在此基础上，为了提高输入至上拉节点PU的信号的质量，如图2所示，在一些实施例中，所述移位寄存器还包括滤波子电路40。
滤波子电路40，连接到第二节点B、上拉节点PU、第二电压端V2。滤波子电路40配置为在来自第二电压端V2的电压的控制下，将第二节点B输入至滤波子电路40的电压中的杂波滤除后，输出至上拉节点PU。
在一些实施例中，为了使本公开提供的移位寄存器能够实现正向扫描和反向扫描，如图1和2所示，所述移位寄存器还包括第二输入子电路50。
第二输入子电路50，连接到第二信号端S2、第四电压端V4和第一节点A。第二输入子电路50配置为在来自第四电压端V4的电压的控制下， 将第二信号端S2的电压输出至第一节点A。
此处需要说明的是，无论是进行正向扫描还是反向扫描，在整个驱动过程中，第一输入子电路10和第二输入子电路50只开启一个，而另一个保持关闭。在一些实施例中，当第一输入子电路10开启，第二输入子电路50关闭时，实现正向扫描；当第二输入子电路50开启，第一输入子电路10关闭时，实现反向扫描。在另一些实施例中，当第一输入子电路10开启，第二输入子电路50关闭时，实现反向扫描；当第二输入子电路50开启，第一输入子电路10关闭时，实现正向扫描。
在一些实施例中，如图1和图2所示，所述移位寄存器还包括：下拉子电路60和输出子电路70。
下拉子电路60，连接到下拉节点PD、第二节点B、信号输出端Oput和第三电压端V3。下拉子电路60配置为在来自下拉节点PD的电压的控制下，将第三电压端V3的电压输出至第二节点B和信号输出端Oput。
输出子电路70，连接到上拉节点PU、第二时钟信号端CK、信号输出端Oput。输出子电路70配置为在来自上拉节点PU的电压的控制下，将第二时钟信号端CK的电压输出至信号输出端Oput。
在本公开提供的移位寄存器应用至栅极驱动电路时，为了在能够对本公开提供的移位寄存器进行初始化，以保证稳定的显示，在一些实施例中，如图2所示，本公开提供的移位寄存器还包括初始化子电路80。
初始化子电路80，连接到第三信号端S3、第二电压端V2和下拉节点PD。初始化子电路80配置为在来自第三信号端S3的电压的控制下，将第二电压端V2的电压输出至下拉节点PD，以进行初始化。
当移位寄存器出现故障，为了不影响重新启动后的移位寄存器的使用，在一些实施例中，如图2所示，本公开提供的移位寄存器还包括残荷消除子电路90。
残荷消除子电路90，连接到第四信号端S4、第三电压端V3、第二节点B、下拉节点PD和信号输出端Oput。残荷消除子电路90配置为在来自第四信号端S4的电压的控制下，将第三电压端V3的电压输出至第二节点B和下拉节点PD；残荷消除子电路90还配置为将第四信号端S4的电压输出至信号输出端Oput，以进行残荷消除。
以下，对上述移位寄存器中的各个子电路的具体结构进行详细的说明。
在一些实施例中，如图3、图4、图5所示，第一输入子电路10包括 第一晶体管T1。
第一晶体管T1包括栅极、第一极和第二极。第一晶体管T1的栅极连接到第一信号端S1，第一晶体管T1的第一极连接到第一电压端V1，第一晶体管T1的第二极连接到第一节点A。
在一些实施例中，如图3、图4、图5所示，上拉控制子电路20包括第二晶体管T2。
第二晶体管T2包括栅极、第一极和第二极。第二晶体管T2的栅极连接到第一节点A，第二晶体管T2的第一极连接到第二电压端V2，第二晶体管T2的第二极连接到第二节点B。
在一些实施例中，如图3、图4、图5所示，下拉控制子电路30包括第三晶体管T3、第四晶体管T4、第五晶体管T5。
第三晶体管T3包括栅极、第一极和第二极。第三晶体管T3的栅极到连接第一时钟信号端CKB，第三晶体管T3的第一极连接到第一时钟信号端CKB，第三晶体管T3的第二极连接到下拉节点PD。
第四晶体管T4包括栅极、第一极和第二极。第四晶体管T4的栅极连接到第一节点A，第四晶体管T4的第一极连接到下拉节点PD，第四晶体管T4的第二极连接到第三电压端V3。
第五晶体管T5包括栅极、第一极和第二极。第五晶体管T5的栅极连接到信号输出端Oput，第五晶体管T5的第一极连接到下拉节点PD，第五晶体管T5的第二极连接到第三电压端V3。
在一些实施例中，如图4和图5所示，下拉控制子电路30还包括第六晶体管T6。
第六晶体管T6包括栅极、第一极和第二极。第六晶体管T6的栅极连接到第二电压端V2，第六晶体管T6的第一极连接到第一时钟信号端CKB，第六晶体管T6的第二极连接到第三晶体管T3的栅极。
在一些实施例中，如图4和图5所示，下拉控制子电路30还包括第一电容C1。
第一电容C1包括第一极和第二极。第一电容C1的第一极连接到下拉节点PD，第一电容C1的第二极连接到第三电压端V3。
在一些实施例中，如图4和图5所示，滤波子电路40包括第七晶体管T7。
第七晶体管T7包括栅极、第一极和第二极。第七晶体管T7的栅极连 接到第二电压端V2，第七晶体管T7的第一极连接到第二节点B，第七晶体管T7的第二极连接到上拉节点PU。
在一些实施例中，如图3、图4、图5所示，第二输入子电路50包括第八晶体管T8。
第八晶体管T8包括栅极、第一极和第二极。第八晶体管T8的栅极连接到第二信号端S2，第八晶体管T8的第一极连接到第一节点A，第八晶体管T8的第二极连接到第四电压端V4。
在一些实施例中，如图3、图4、图5所示，下拉子电路60包括第九晶体管T9和第十晶体管T10。
第九晶体管T9包括栅极、第一极和第二极。第九晶体管T9的栅极连接到下拉节点PD，第九晶体管T9的第一极连接到第二节点B，第九晶体管T9的第二极连接到第三电压端V3。
第十晶体管T10包括栅极、第一极和第二极。第十晶体管T10的栅极连接到下拉节点PD，第十晶体管T10的第一极连接到信号输出端Oput，第十晶体管T10的第二极连接到第三电压端V3。
在一些实施例中，如图3、图4、图5所示，输出子电路70包括第十一晶体管T11和第二电容C2。
第二电容C2包括第一极和第二极。第二电容C2的第一极连接到上拉节点PU，第二电容C2的第二极连接到信号输出端Oput。
第十一晶体管T11包括栅极、第一极和第二极。第十一晶体管T11的栅极连接到上拉节点PU，第十一晶体管T11的第一极连接到第二时钟信号端CK，第十一晶体管T11的第二极连接到信号输出端Oput。
在一些实施例中，如图5所示，初始化子电路80包括第十二晶体管T12。
第十二晶体管T12包括栅极、第一极和第二极。第十二晶体管T12的栅极连接到第三信号端S3，第十二晶体管T12的第一极连接到下拉节点PD，第十二晶体管T12的第二极连接到第二电压端V2。
在一些实施例中，如图5所示，残荷消除子电路90包括第十三晶体管T13、第十四晶体管T14和第十五晶体管T15。
第十三晶体管T13包括栅极、第一极和第二极。第十三晶体管T13的栅极连接到第四信号端S4，第十三晶体管T13的第一极连接到下拉节点PD，第十三晶体管T13的第二极连接到第三电压端V3。
第十四晶体管T14包括栅极、第一极和第二极。第十四晶体管T14的栅极连接到第四信号端S4，第十四晶体管T14的第一极连接到信号输出端Oput，第十四晶体管T14的第二极连接到第四信号端S4。
第十五晶体管T15包括栅极、第一极和第二极。第十五晶体管T15的栅极连接到第四信号端S4，第十五晶体管T15的第一极连接到第二节点B，第十五晶体管T15的第二极连接到第三电压端V3。
本公开的一些实施例提供一种栅极驱动电路，如图6和图7所示，包括至少两级级联的上述移位寄存器。
在一些实施例中，第一级移位寄存器RS1的第一信号端S1与起始信号端STV相连接。除了第一级移位寄存器RS1以外，每一级移位寄存器RS(n)的第一信号端S1与其上一级移位寄存器RS(n-1)的信号输出端Oput相连接，其中，n为大于1的整数。起始信号端STV用于输出起始信号，该栅极驱动电路的第一级移位寄存器RS1在接收到上述起始信号后开始对栅线(G1、G2……Gn)进行逐行扫描。即，在此情况下，栅极驱动电路对栅线进行正向扫描。
在一些实施例中，当移位寄存器还包括第二输入子电路20时，如图7所示，除了最后一级移位寄存器以外，每一级移位寄存器RS(m)的第二信号端S2与其下一级移位寄存器RS(m+1)的信号输出端Oput相连接，其中，m为大于等于1的整数。最后一级移位寄存器的第二信号端S2连接起始信号端STV或者复位信号端(图8中以最后一级移位寄存器的第二信号端S2连接起始信号端STV进行示意说明的)。
在最后一级移位寄存器的第二信号端S2连接起始信号端STV的情况下，起始信号端STV用于输出起始信号，最后一级移位寄存器在接收到上述起始信号后开始对栅线(Gm……G2、G1)进行逐行扫描。即，在此情况下，栅极驱动电路对栅线进行反向扫描。
需要说明的是，由上述对栅极驱动电路正向扫描和反向扫描的描述可知，当移位寄存器既包括第一输入子电路10又包括第二输入子电路50时，在整个驱动过程中，第一输入子电路10和第二输入子电路50只开启一个，而另一个保持关闭。也就是说，当栅极驱动电路中的移位寄存器既包括第一输入子电路10又包括第二输入子电路50时，该栅极驱动电路要么对栅线进行正向扫描，要么对栅线进行反向扫描(视具体的级联方式而定)。
在一些实施例中，在移位寄存器包括输出子电路70的情况下，如图6 和图7所示，奇数级的移位寄存器中第一时钟信号端CKB与第一时钟信号线CKB’连接，第二时钟信号端CK与第二时钟信号线CK连接’。偶数级的移位寄存器中第一时钟信号端CKB与所述第二时钟信号线CK’连接，第二时钟信号端CK与第一时钟信号线CKB’连接。即，第一时钟信号线CKB’向奇数级的移位寄存器中第一时钟信号端CKB输入信号，向偶数级的移位寄存器中第二时钟信号端CK输入信号。第二时钟信号线CK’连接向奇数级的移位寄存器中第二时钟信号端CK输入信号，向偶数级的移位寄存器中第一时钟信号端CKB输入信号。本公开的实施例提供的栅极驱动电路的有益效果与上述移位寄存器的有益效果相同，此处不再赘述。
本公开的一些实施例提供一种显示装置，包括如上所述的任意一种栅极驱动电路，具有与前述栅极驱动电路相同的有益效果。由于前述实施例已经对栅极驱动电路的结构和有益效果进行了详细的描述，此处不再赘述。
需要说明的是，在本公开的一些实施例中，显示装置至少可以包括液晶显示面板或有机发光二极管显示面板。例如该显示面板可以应用至显示器、电视、数码相框、手机或平板电脑等任何具有显示功能的产品或者部件中。以下结合上述栅极驱动电路对移位寄存器的驱动过程作进一步的说明。其中，本公开实施例提供的移位寄存器的各子电路中的晶体管可以为N型晶体管，也可以为P型晶体管。此外，上述晶体管可以为增强型晶体管，也可以为耗尽型晶体管。上述晶体管的第一极可以为源极，第二极可以为漏极。或者，上述晶体管的第一极可以为漏极，第二极为源极，本公开对此不作限定。
以下，以上述晶体管均为N型晶体管为例，结合图8所示的信号时序图对图5所示的移位寄存器在一图像帧(例如第U帧，U≥1，U为正整数)的不同的阶段的通断情况进行详细的举例说明。其中，第一时钟信号端CKB和第二时钟信号端CK为互补信号，第一电压端V1和第四电压端V4是控制正反扫描的高低电平。
以下实施例以第二电压端V2恒定输出高电平，第三电压端V3恒定输出低电平为例进行的说明。此外，以下实施例以正向扫描为例，即以第一输入子电路10工作，第二输入子电路50不工作为例进行说明(即第一电压端V1输入高电平信号，第四电压端V4输入低电平信号)。
本公开中的移位寄存器的驱动方法包括：输入阶段、输出阶段、下拉阶段。
由于针对第一级移位寄存器RS1和第一级移位寄存器RS1以后的移位寄存器(RS2、RS3……RSn)，在输入阶段的控制信号具有一定的区别，因此，以下以图7的栅极驱动电路(采用图5的移位寄存器)结合图8的控制时序图，对第一级移位寄存器RS1和第一级移位寄存器RS1以后的移位寄存器(RS2、RS3……RSn)在输入阶段的区别进行说明。
参考图8，以第一级移位寄存器RS1和第二级移位寄存器RS2为例，第一级移位寄存器RS1的驱动过程包括：输入阶段P1’、输出阶段P2’、下拉阶段P3’。第二级移位寄存器RS2的驱动过程包括：输入阶段P1、输出阶段P2、下拉阶段P3。第一级移位寄存器RS1的输出阶段P2’与第二级移位寄存器RS2输入阶段P1为同一时段；第一级移位寄存器RS1的下拉阶段P3’与第二级移位寄存器RS2的输出阶段P2为同一时段。
第一级移位寄存器RS1和第二级移位寄存器RS2在输入阶段的时序控制的区别在于：第一级移位寄存器RS1在输入阶段P1’，第一时钟信号端CKB为低电位，而第二级移位寄存器RS2在输入阶段P1，第一时钟信号端CKB为高电平，但两者都可以保证栅极驱动电路的正常工作。
以下，以第二级移位寄存器RS2为例，结合图5的移位寄存器中的各晶体管的通断以及图8的时序，对移位寄存器在一图像帧(例如第U帧，U≥1，U为正整数)的不同的阶段中各晶体管的通断情况进行详细的举例说明。在输入阶段P1，S1＝1，CK＝0(对应图8中(CKB’))，CKB＝1(对应图8中(CK’))，S3＝0，S4＝0；“0”表示低电平，“1”表示高电平。
第一电压端V1输出高电平，因此第一晶体管T1导通，从而将第一信号端S1的高电平输出至第一节点A，控制第二晶体管T2开启，第二电压端V2的电压经第二晶体管T2传输至第二节点B。由于第二电压端V2恒定输出高电平，因此第七晶体管T7为常开晶体管。第二节点B上的高电平经第七晶体管T7滤波后输出至上拉节点PU，并通过第二电容C2对该高电平进行存储。在上拉节点PU高电位的控制下，第十一晶体管T11导通，将第二时钟信号端CK的低电平至信号输出端Oput，并控制第五晶体管T5截止。
与此同时，第一信号端S1的高电平输出至第一节点A，第一节点A的高电平控制第四晶体管T4开启，将第三电压端V3的低电平传输至下拉节点PD。此时，即使在第二电压端V2输出的高电平的控制下，第六晶体 管T6导通，将第一时钟信号端CKB的高电平输出至第三晶体管T3的栅极，控制第三晶体管T3开启，将第一时钟信号端CKB的高电平输出至下拉节点PD，但第三晶体管T3、第四晶体管T4和第六晶体管T6在下拉节点PD的分压使得第九晶体管T9和第十晶体管T10仍处于截止状态，保证上拉节点PU的充电状态。
第三信号端S3输入低电平控制第十二晶体管T12截止。第四信号端S4输入低电平信号，控制第十三晶体管T13、第十四晶体管T14、第十五晶体管T15截止。
综上所述，在输入阶段P1，第一晶体管T1开启、第二晶体管T2开启、第三晶体管T3截止、第四晶体管T4开启、第五晶体管T5截止、第六晶体管T6开启、第七晶体管T7开启、第八晶体管T8截止、第九晶体管T9截止、第十晶体管T10截止、第十一晶体管T11开启、第十二晶体管T12截止、第十三晶体管T13截止、第十四晶体管T14截止、第十五晶体管T15截止，信号输出端Oput在上述输入阶段P1输出低电平。
输出阶段P2，S1＝0，CK＝1，CKB＝0，S3＝0，S4＝0。
第一电压端V1输出高电平，因此第一晶体管T1导通，从而将第一信号端S1的低电平输出至第一节点A，控制第二晶体管T2和第四晶体管T4截止。第二电容C2将输入阶段P1存储的高电平对上拉节点PU进行充电，从而使得第十一晶体管T11保持开启状态。在此情况下，第二时钟信号端CK的高电平通过第十一晶体管T11输出至信号输出端Oput，并控制第五晶体管T5开启，第三电压端V3的低电平经过第五晶体管T5传输至下拉节点PD。下拉节点PD的低电平控制第九晶体管T9和第十晶体管T10截止。
此外，在第二电容C2的自举(Bootstrapping)作用下，上拉节点PU的电位进一步升高(第二电容C2与信号输出端Oput连接的一端的电位由0跳变为1，在第二电容C2对上拉节点PU进行充电时，上拉节点PU的电位在1的基础上再向高电位跳变1)，以维持第十一晶体管T11处于导通的状态。从而使得第二时钟信号端CK的高电平能够作为栅极扫描信号输出至与信号输出端Oput相连接的栅线上。
与此同时，在第二电压端V2输出的高电平的控制下，第六晶体管T6导通。第一时钟信号端CKB输出的低电平，控制第三晶体管T3截止。
第三信号端S3输入低电平控制第十二晶体管T12截止。第四信号端 S4输入低电平，控制第十三晶体管T13、第十四晶体管T14、第十五晶体管T15截止。
综上所述，在输出阶段P2，第一晶体管T1开启、第二晶体管T2截止、第三晶体管T3截止、第四晶体管T4截止、第五晶体管T5开启、第六晶体管T6开启、第七晶体管T7开启、第八晶体管T8截止、第九晶体管T9截止、第十晶体管T10截止、第十一晶体管T11开启、第十二晶体管T12截止、第十三晶体管T13截止、第十四晶体管T14截止、第十五晶体管T15截止，信号输出端Oput在上述输出阶段P2输出高电平，以向与信号输出端Oput相连接的栅线输出栅极扫描信号。
下拉阶段P3，S1＝0，CK＝0，CKB＝1，S3＝0，S4＝0。
第一电压端V1输出高电平，第一晶体管T1导通，从而将第一信号端S1的低电平输出至第一节点A，控制第二晶体管T2和第四晶体管T4截止。在第二电压端V2输出的高电平的控制下，第七晶体管T7和第六晶体管T6导通，第一时钟信号端CKB输出的高电平控制第三晶体管T3开启，并将第一时钟信号端CKB输出的高电平传输至下拉节点PD。下拉节点PD控制第九晶体管T9和第十晶体管T10均开启，通过第九晶体管T9将第二节点B的电位下拉至第三电压端V3的低电平。第二节点B的低电平经第七晶体管T7滤除杂波后传输至上拉节点PU，即，将上拉节点PU的电位下拉至第三电压端V3的低电平，并控制第十一晶体管T11截止。通过第十晶体管T10将信号输出端Oput的电位下拉至第三电压端V3的低电平，并控制第五晶体管T5截止。第一电容C1将下拉节点PD的高电平进行存储，使下拉节点PD长时间稳定的保持高电平。
此外，第三信号端S3输入低电平，控制第十二晶体管T12截止。第四信号端S4输入低电平，控制第十三晶体管T13、第十四晶体管T14、第十五晶体管T15截止。
综上所述，在下拉阶段P3，第一晶体管T1开启、第二晶体管T2截止、第三晶体管T3开启、第四晶体管T4截止、第五晶体管T5截止、第六晶体管T6开启、第七晶体管T7开启、第八晶体管T8截止、第九晶体管T9开启、第十晶体管T10开启、第十一晶体管T11截止、第十二晶体管T12截止、第十三晶体管T13截止、第十四晶体管T14截止、第十五晶体管T15截止，信号输出端Oput在上述下拉阶段P3输出低电平。
需要说明的是，针对如图3所示的移位寄存器，由于移位寄存器不包 括第六晶体管T6，因此，在上述下拉阶段P3中，通过第一时钟信号端CKB的高电平控制第三晶体管T3开启，并将第一时钟信号端CKB的高电平传输至下拉节点PD。在移位寄存器中包括第六晶体管T6的情况下，则第一时钟信号端CKB的高电平经开启的第六晶体管T6传输至第三晶体管T3的栅极，控制第三晶体管T3开启，第一时钟信号端CKB的高电平经第三晶体管T3传输至下拉节点PD。
在移位寄存器不包括第六晶体管T6的情况下，下拉节点PD的电压如图9中虚线所示。在移位寄存器包括第六晶体管T6的情况下，下拉节点PD的电压如图9中实线所示。从图9可知，在移位寄存器不包括第六晶体管T6的情况下，移位寄存器中下拉节点PD电压无法完整保持第一时钟信号的高电平(存在损失)，这是因为N型晶体管在输出高电平时存在不可避免的阈值损失，导致第三晶体管T3在给下拉节点PD充电时无法达到完整的高点平幅值，存在一定的损失。在移位寄存器包括第六晶体管T6的情况下，移位寄存器中下拉节点PD电压如图9所示，能完整保持第一时钟信号的高电平。增加第六晶体管T6后，第六晶体管T6和第三晶体管T3配合，使得第三晶体管T3栅极发生自举，使得第一时钟信号端CKB的高电平通过第三晶体管T3能完整的给下拉节点PD充电，避免阈值损失，实现第一时钟信号端CKB的高电平无损输入到下拉节点PD。起到对下拉节点PD上的电压信号进行提升驱动能力及波形整形的作用，从而确保下拉节点PD上的电压信号的持续稳定，提升了显示器栅极驱动的性能及稳定性。
参考图10中相关技术的移位寄存器，本级移位寄存器在上述下拉阶段输出低电平无法由本级移位寄存器来实现，而是依靠下一级移位寄存器(即OputN+1端)输出的高电平来完成的(也即图10中的晶体管M1在下一级移位寄存器输出的高电平到来之前一直保持开启)。这样一来，如图11所示，在下一级异常输出的情况下，无法实现本级移位寄存器在下拉阶段的复位，导致后续连锁输出异常。
另外，相比图10中将上一级移位寄存器的信号输出端OputN-1与本级移位寄存器中的相应的晶体管的栅极连接。本公开提供的移位寄存器中，增加了第二晶体管T2，并改变上一级移位寄存器的信号输出端Oput与本级移位寄存器的连接方式后(上一级移位寄存器的信号输出端Oput不与本级移位寄存器第一晶体管T1的栅极相连)，移位寄存器在下拉阶段的复 位和保持复位都是第三晶体管T3完成。其中，本公开提供的移位寄存器中，由于本级第四晶体管T4在输入低电平后保持关闭状态，即第一节点A在输入阶段之后一直保持低电平(如图8中A点的时序所示)，使得第一时钟信号端CKB的高电平可以由第三晶体管T3传输至下拉节点PD，以拉高下拉节点PD的电位，拉低上拉节点PU的电位，从而实现在下拉阶段复位的目的。避免下一级异常输出使本级无法复位，避免出现后续连锁异常输出，提升显示器栅极驱动的性能及稳定性。
在移位寄存器包括初始化子电路80的情况下，在初始化阶段，S1＝0，CK＝0，CKB＝0，S3＝1，S4＝0。
第三信号端S3输出高电平，控制第十二晶体管T12开启，将第二电压端V2的高电平输出至下拉节点PD。下拉节点PD控制第九晶体管T9和第十晶体管T10开启，第九晶体管T9将第三电压端V3的低电平输出至上拉节点PU，第十晶体管T10将第三电压端V3的低电平输出至信号输出端Oput，将上拉节点PU和信号输出端Oput的电压均拉低，完成对移位寄存器的初始化。
综上所述，在该初始化阶段P4，第一晶体管T1开启、第二晶体管T2截止、第三晶体管T3截止、第四晶体管T4截止、第五晶体管T5截止、第六晶体管T6开启、第七晶体管T7开启、第八晶体管T8截止、第九晶体管T9开启、第十晶体管T10开启、第十一晶体管T11截止、第十二晶体管T12开启、第十三晶体管T13截止、第十四晶体管T14截止、第十五晶体管T15截止，信号输出端Oput在上述初始化阶段P4输出低电平。
在移位寄存器包括残荷消除子电路90的情况下，在栅极驱动电路每次关机时，在残荷消除阶段，S1＝0，S3＝0，S4＝1。
第四信号端S4输出高电平，控制第十三晶体管T13、第十四晶体管T14、第十五晶体管T15开启。第十四晶体管T14开启，将第四信号端S4的高电平输出至信号输出端Oput，使信号输出端Oput输出高电平，以使整个电路完成放电，消除因异常显示而残留在电路内的电荷。
为了保证残荷的消除效果，第十五晶体管T15开启，将第三电压端V3输出的低电平输出至上拉节点PU，以避免其他信号影响信号输出端Oput的电位。
与此同时，为了进一步保证残荷的消除效果，第十三晶体管T13开启，将第三电压端V3输出的低电平输出至下拉节点PD，以避免其他信号影响 下拉节点PD的电位。
需要说明的是，若移位寄存器没有上述第十三晶体管T13，则仍然可以通过第十四晶体管T14单独工作，完成残荷消除任务。
本公开提供的残荷消除子电路90，包括第十三晶体管T13、第十四晶体管T14和第十五晶体管T15，三个晶体管相配合，实现保持上拉节点PU为高电平，提升了显示器栅极驱动的性能及稳定性。
综上所述，在该残荷消除阶段，第一晶体管T1开启、第二晶体管T2截止、第三晶体管T3截止、第四晶体管T4截止、第五晶体管T5截止、第六晶体管T6开启、第七晶体管T7开启、第八晶体管T8截止、第九晶体管T9截止、第十晶体管T10截止、第十一晶体管T11截止、第十二晶体管T12截止、第十三晶体管T13开启、第十四晶体管T14开启、第十五晶体管T15开启，信号输出端Oput在上述残荷消除阶段P5输出高电平。
需要说明的是，上述实施例中晶体管的通、断过程是以所有晶体管为N型晶体管为例进行说明的。当所有晶体管均为P型时，需要对图5中各个控制信号进行翻转，而移位寄存器中各个子电路的晶体管的通断过程同上所述，此处不再赘述。
此外，上述移位寄存器的工作过程，是以上述多个移位寄存器级联构成的栅极驱动电路采用正向扫描的方式为例进行的说明。当采用反向扫描时，在图3、图4和图5所示的移位寄存器中，在输入阶段P1，使第一晶体管T1截止，第八晶体管T8开启即可。
本公开的一些实施例提供一种用于驱动上述任意一种移位寄存器的方法，如图12所示，所述驱动方法包括步骤10-30(S10-S30)：
输入阶段P1：
S10、在来自第一电压端V1的电压的控制下，第一输入子电路10将第一信号端S1输入的电压输出至第一节点A，以通过第一节点A控制上拉控制子电路20开启，将第二电压端V2的电压经第二节点B输出至上拉节点PU。与此同时，在来自第一节点A的电压的控制下，下拉控制子电路30将第三电压端V3的电压输出至下拉节点PD。
在移位寄存器单元还包括滤波子电路40的情况下，在该输入阶段P1：
在第一电压端V1的控制下，第一输入子电路10将第一信号端S1输入的电压输出至第一节点A，第一节点A控制上拉控制子电路20开启，将第二电压端V2的电压输出至第二节点B，滤波子电路40将第二节点B 输入的电压中的杂波滤除后输出至上拉节点PU。
在该上述移位寄存器还包括下拉子电路60、初始化子电路80和残荷消除子电路90的情况下，该输入阶段P1中，下拉子电路60、初始化子电路80、残荷消除子电路90均关闭。在一些实施例中，上述移位寄存器中各个子电路的结构如图5所示，且各个子电路中的晶体管均为N型晶体管。在该输入阶段P1中，第一信号端S1输入高电平，第一时钟信号端CKB输入高电平，第二时钟信号端CK输入低电平，第三信号端S3输入低电平，第四信号端S4输入低电平，第一电压端V1输入高电平，第二电压端V2输入高电平，第三电压端V3输入低电平，第四电压端V4输入低电平，上拉节点PU为高电平，下拉节点PD为低电平，信号输出端Oput输出低电平。
在此情况下，由于第一电压端V1输出高电平，因此第一晶体管T1导通，从而将第一信号端S1的高电平输出至第一节点A，控制第二晶体管T2开启，第二电压端V2的电压经第二晶体管T2传输至第二节点B。由于第二电压端V2输出高电平，因此第七晶体管T7为常开晶体管，第二节点B上的高电平经第七晶体管T7滤波后输出至上拉节点PU，并通过第二电容C2对该高电平进行存储。在上拉节点PU高电平的控制下，第十一晶体管T11导通，将第二时钟信号端CK的低电平输出至信号输出端Oput，并控制第五晶体管T5截止。
与此同时，第一节点A的高电平控制第四晶体管T4开启，将第三电压端V3的低电平传输至下拉节点PD，此时，即使在第二电压端V2输出的高电平的控制下，第六晶体管T6导通，将第一时钟信号端CKB的高电平输出至第三晶体管T3的栅极，控制第三晶体管T3开启，将第一时钟信号端CKB的高电平输出至下拉节点PD，但第三晶体管T3、第四晶体管T4和第六晶体管T6在下拉节点PD的分压使得第九晶体管T9和第十晶体管T10仍处于截止状态，保证上拉节点PU的充电状态。
第三信号端S3输入低电平控制第十二晶体管T12截止，第四信号端S4输入低电平，控制第十三晶体管T13、第十四晶体管T14、第十五晶体管T15截止。
输出阶段P2：
S20、在来自第一节点A的电压的控制下，使上拉控制子电路20处于关闭状态；并在来自信号输出端Oput的电压的控制下，下拉控制子电路 30将第三电压端V3的电压输出至下拉节点PD。
在该输出阶段P2中，在来自上拉节点PU的电压的控制下，输出子电路70将第二时钟信号端CK的时钟信号(高电位)输出至信号输出端Oput，该信号输出端Oput输出栅极扫描信号。
与此同时，在信号输出端Oput输出的高电平控制下，下拉控制子电路30将第三电压端V3的低电平输出至下拉节点PD，控制下拉子电路60关闭。初始化子电路80和残荷消除子电路90均关闭。
在一些实施例中，上述移位寄存器中各个子电路的结构如图5所示，且各个子电路中的晶体管均为N型晶体管。在该输出阶段P2中，第一信号端S1输入低电平，第二时钟信号端CK输入高电平，第一时钟信号端CKB输入低电平，第三信号端S3输入低电平，第四信号端S4输入低电平，第一电压端V1输入高电平，第二电压端V2输入高电平，第三电压端V3输入低电平，第四电压端V4输入低电平，上拉节点PU为高电平，下拉节点PD为低电平，信号输出端Oput输出高电平。
此时，由于第一电压端V1输出高电平，因此第一晶体管T1导通，从而将第一信号端S1的低电平输出至第一节点A，控制第二晶体管T2和第四晶体管T4截止。第二电容C2用输入阶段P1存储的高电平对上拉节点PU进行充电，从而使得第十一晶体管T11保持开启状态。在此情况下，第二时钟信号端CK的高电平通过第十一晶体管T11输出至信号输出端Oput，并控制第五晶体管T5开启，第三电压端V3的低电平经过第五晶体管T5传输至下拉节点PD，下拉节点PD的低电平控制第九晶体管T9和第十晶体管T10截止。
此外，在第二电容C2的自举作用下，上拉节点PU的电位进一步升高，以维持第十一晶体管T11处于导通的状态，从而使得第二时钟信号端CK的高电平能够作为栅极扫描信号输出至与信号输出端Oput相连接的栅线上。
与此同时，在第二电压端V2输出的高电平的控制下，第六晶体管T6导通，第一时钟信号输出低电平，控制第三晶体管T3截止。
第三信号端S3输入低电平控制第十二晶体管T12截止，第四信号端S4输入低电平，控制第十三晶体管T13、第十四晶体管T14、第十五晶体管T15截止。
下拉阶段P3：
S30、在来自第一节点A的电压的控制下，使上拉控制子电路20处于关闭状态；并在第一时钟信号端CKB的控制下，下拉控制子电路30将第一时钟信号端CKB的时钟信号(高电位)输出至下拉节点PD。
在下拉阶段P3中，在来自下拉节点PD的电压控制下，下拉子电路60将第三电压端V3输入的电压输出至第二节点B，滤波子电路40将第二节点B输入的电压中的杂波滤除后输出至上拉节点PU，控制输出子电路70关闭。下拉子电路60还将第三电压端V3输入的电压输出至信号输出端Oput。
与此同时，输出子电路70、初始化子电路80和残荷消除子电路90均关闭。
在一些实施例中，上述移位寄存器中各个子电路的结构如图5所示，且各个子电路中的晶体管均为N型晶体管。在该下拉阶段P3中，第一信号端S1输入低电平，第二时钟信号端CK输入低电平，第一时钟信号端CKB输入高电平，第三信号端S3输入低电平，第四信号端S4输入低电平，第一电压端V1输入高电平，第二电压端V2输入高电平，第三电压端V3输入低电平，第四电压端V4输入低电平，上拉节点PU为低电平，下拉节点PD为高电平，信号输出端Oput输出低电平。
此时，由于第一电压端V1输出高电平，因此第一晶体管T1导通，从而将第一信号端S1的低电平输出至第一节点A，控制第二晶体管T2和第四晶体管T4截止。在第二电压端V2输出的高电平的控制下，第七晶体管T7和第六晶体管T6导通，第一时钟信号端CKB输出的高电平控制第三晶体管T3开启，并将第一时钟信号端CKB输出的高电平输出至下拉节点PD。下拉节点PD控制第九晶体管T9和第十晶体管T10均开启，通过第九晶体管T9将第二节点B的电位下拉至第三电压端V3的低电平。第二节点B的低电平经第七晶体管T7滤除杂波后传输至上拉节点PU，即将上拉节点PU的电位下拉至第三电压端V3的低电平，并控制第十一晶体管T11截止。通过第十晶体管T10将信号输出端Oput的电位下拉至第三电压端V3的低电平，并控制第五晶体管T5截止。第一电容C1将下拉节点PD的高电平进行存储，使下拉节点PD长时间稳定的保持高电平。
此外，第三信号端S3输入低电平控制第十二晶体管T12截止，第四信号端S4输入低电平，控制第十三晶体管T13、第十四晶体管T14、第十五晶体管T15截止。
在移位寄存器包括初始化子电路80和残荷消除子电路90的情况下，在一图像帧开始或者结束时，如图13所示，该移位寄存器的驱动方法还包括步骤40(S40)：
初始化阶段：
S40、在来自第三信号端S3的信号的控制下，初始化子电路80将第二电压端V2的电压输出至下拉节点PD；在来自下拉节点PD的电压的控制下，下拉子电路60将第三电压端V3输入的电压输出至第二节点B，滤波子电路40将第二节点B输入的电压中的杂波滤除后输出至上拉节点PU；下拉子电路60还将第三电压端V3输入的下拉信号输出至信号输出端Oput。
在该初始化阶段中，初始化子电路80、下拉子电路60、滤波子电路40开启。
在一些实施例中，上述移位寄存器中各个子电路的结构如图5所示，且各个子电路中的晶体管均为N型晶体管。在该初始化阶段中，第一信号端S1输入低电平，第二时钟信号端CK输入低电平，第一时钟信号端CKB输入低电平，第三信号端S3输入高电平，第四信号端S4输入低电平，第一电压端V1输入高电平，第二电压端V2输入高电平，第三电压端V3输入低电平，第四电压端V4输入低电平，上拉节点PU为低电平，下拉节点PD为高电平，信号输出端Oput输出低电平。
此时，第三信号端S3输出高电平，控制第十二晶体管T12开启，将第二电压端V2的高电平输出至下拉节点PD，下拉节点PD控制第九晶体管T9和第十晶体管T10开启。第九晶体管T9将第三电压端V3的低电平输出至上拉节点PU，第十晶体管T10将第三电压端V3的低电平输出至信号输出端Oput，将上拉节点PU和信号输出端Oput的电压均拉低，完成对移位寄存器的初始化。
在移位寄存器包括残荷消除子电路90的情况下，栅极驱动电路在每次关机时，如图14所示，该移位寄存器的驱动方法还包括步骤50(S50)：
残荷消除阶段：
S50、在来自第四信号端S4的控制下，残荷消除子电路90将第三电压端V3的电压输出至下拉节点PD和第二节点B，滤波子电路40将第二节点B输入的电压中的杂波滤除后输出至上拉节点PU；残荷消除子电路90还将第四信号端S4的电压输出至信号输出端Oput。
在该残荷消除阶段，残荷消除子电路90、下拉子电路60、滤波子电路40开启。
在一些实施例中，上述移位寄存器中各个子电路的结构如图5所示，且各个子电路中的晶体管均为N型晶体管。在该残荷消除阶段中，第一信号端S1输入低电平，第二时钟信号端CK输入低电平，第一时钟信号端CKB输入高电平，第三信号端S3输入低电平，第四信号端S4输入高电平，第一电压端V1输入高电平，第二电压端V2输入高电平，第三电压端V3输入低电平，第四电压端V4输入低电平。
此时，第四信号端S4输出高电平，控制第十三晶体管T13、第十四晶体管T14、第十五晶体管T15开启。第十四晶体管T14开启将第四信号端S4的高电平输出至信号输出端Oput。第十五晶体管T15开启将第三电压端V3输出的低电平输出至上拉节点PU。第十三晶体管T13开启将第三电压端V3输出的低电平输出至下拉节点PD，下拉节点PD控制第九晶体管T9和第十晶体管T10截止。
以上是以第一输入子电路10开启，栅极驱动电路进行正向扫描进行示意说明的，此时，即使移位寄存器中包括第二输入子电路50，在第一输入子电路10开启的情况下，第二输入子电路50也保持关闭。
在移位寄存器包括第二输入子电路50的情况下，若要实现栅极驱动电路反向扫描，则第一输入子电路10关闭，第二输入子电路50开启即可，即第四电压端V4输入高电平，第一电压端V1输入低电平，其他信号不变。
相对于正向扫描而言，反向扫描与正向扫描的区别在于：在输入阶段P1，在来自第四电压端V4的电压的控制下，第二输入子电路50将第二信号端S2输入的电压输出至第一节点A，以通过第一节点A的电压控制上拉控制子电路20开启，将第二电压端V2的电压经第二节点B输出至上拉节点PU；同时，在来自第一节点A的电压的控制下，下拉控制子电路30将第三电压端V3的电压输出至下拉节点PD。
对于其他阶段的驱动过程，与前述的各阶段的驱动过程一致，具体可以参考前述，此处不再赘述。对于在各阶段中各晶体管的开启与关闭而言，其区别仅在于，将前述第一晶体管T1的开启替换为第八晶体管T8的开启，其余晶体管在各阶段的开启与关闭与前述一致，此处不再赘述。
需要说明的是，在移位寄存器应用于栅极驱动电路的情况下，在每一图像帧内，均包括输入阶段P1、输出阶段P2和下拉阶段P3。而对于初始 化阶段而言，一般设置于每一图像帧开始或者结束时进行。对于残荷消除阶段而言，则在栅极驱动电路每次关机时进行。
本公开的实施例提供的移位寄存器的驱动方法，其有益效果与上述位移寄存器相同，此处不再赘述。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (23)

  1. 一种移位寄存器，包括：第一输入子电路、上拉控制子电路和下拉控制子电路；
    所述第一输入子电路，连接到第一信号端、第一电压端和第一节点；所述第一输入子电路配置为在来自所述第一电压端的电压的控制下，将所述第一信号端的电压输出至所述第一节点；
    所述上拉控制子电路，连接到所述第一节点、第二电压端和第二节点；所述上拉控制子电路配置为在来自所述第一节点的电压的控制下，处于开启或者关闭状态，且在所述上拉控制子电路处于开启状态时，将所述第二电压端的电压输出至所述第二节点；
    所述下拉控制子电路，连接到所述第一节点、第三电压端、第一时钟信号端、所述信号输出端和下拉节点；所述下拉控制子电路配置为在来自所述第一节点的电压的控制下，将所述第三电压端的电压输出至所述下拉节点；在来自所述信号输出端的电压的控制下，将所述第三电压端的电压输出至所述下拉节点；在来自所述第一时钟信号端的电压的控制下，将所述第一时钟信号端的电压输出至所述下拉节点；
    其中，所述第二节点与上拉节点相连接。
  2. 根据权利要求1所述的移位寄存器，其中，所述上拉节点配置为控制所述移位寄存器的信号输出端输出栅极扫描信号，所述下拉节点配置为停止所述信号输出端输出栅极扫描信号。
  3. 根据权利要求1或2所述的移位寄存器，还包括：滤波子电路和/或第二输入子电路；
    所述滤波子电路，连接到所述第二节点、所述上拉节点、所述第二电压端；所述滤波子电路配置为在来自所述第二电压端的电压的控制下，将所述第二节点输入至所述滤波子电路的电压中的杂波滤除后，输出至所述上拉节点；
    所述第二输入子电路，连接到第二信号端、第四电压端和所述第一节点；所述第二输入子电路配置为在来自所述第四电压端的电压的控制下，将所述第二信号端的电压输出至所述第一节点。
  4. 根据权利要求1-3任一项所述的移位寄存器，还包括：下拉子电路和输出子电路；
    所述下拉子电路，连接到所述下拉节点、所述第二节点、所述信号输 出端和所述第三电压端；所述下拉子电路配置为在来自所述下拉节点的电压的控制下，将所述第三电压端的电压输出至所述第二节点和所述信号输出端；
    所述输出子电路，连接到所述上拉节点、第二时钟信号端、所述信号输出端；所述输出子电路配置为在来自所述上拉节点的电压的控制下，将所述第二时钟信号端的电压输出至所述信号输出端。
  5. 根据权利要求1-3任一项所述的移位寄存器，还包括：初始化子电路和/或残荷消除子电路；
    所述初始化子电路，连接到第三信号端、所述第二电压端和所述下拉节点；所述初始化子电路配置为在来自所述第三信号端的电压的控制下，将所述第二电压端的电压输出至所述下拉节点；
    所述残荷消除子电路，连接到第四信号端、所述第三电压端、所述第二节点、所述下拉节点和所述信号输出端；所述残荷消除子电路配置为在来自所述第四信号端的电压的控制下，将所述第三电压端的电压输出至所述第二节点和所述下拉节点；所述残荷消除子电路还配置为将所述第四信号端的电压输出至所述信号输出端。
  6. 根据权利要求1-5任一项所述的移位寄存器，其中，所述第一输入子电路包括第一晶体管；
    所述第一晶体管的栅极连接到所述第一信号端，第一极连接到所述第一电压端，第二极连接到所述第一节点。
  7. 根据权利要求1-5任一项所述的移位寄存器，其中，所述上拉控制子电路包括第二晶体管；
    所述第二晶体管的栅极连接到所述第一节点，第一极连接到所述第二电压端，第二极连接到所述第二节点。
  8. 根据权利要求1-5任一项所述的移位寄存器，其中，所述下拉控制子电路包括第三晶体管、第四晶体管、第五晶体管；
    所述第三晶体管的栅极连接到所述第一时钟信号端，第一极连接到所述第一时钟信号端，第二极连接到所述下拉节点；
    所述第四晶体管的栅极连接到所述第一节点，第一极连接到所述下拉节点，第二极连接到所述第三电压端；所述第五晶体管的栅极连接到所述信号输出端，第一极连接到所述下拉节点，第二极连接到所述第三电压端。
  9. 根据权利要求8所述的移位寄存器，其中，所述下拉控制子电路还 包括第六晶体管；
    所述第六晶体管的栅极连接到所述第二电压端，第一极连接到所述第一时钟信号端，第二极连接到所述第三晶体管的栅极。
  10. 根据权利要求8或9所述的移位寄存器，其中，所述下拉控制子电路还包括第一电容；
    所述第一电容的第一极连接到所述下拉节点，第二极连接到所述第三电压端。
  11. 根据权利要求3所述的移位寄存器，其中，在所述移位寄存器包括滤波子电路的情况下，所述滤波子电路包括第七晶体管；
    所述第七晶体管的栅极连接到所述第二电压端，第一极连接到所述第二节点，第二极连接到所述上拉节点。
  12. 根据权利要求3所述的移位寄存器，其中，在所述移位寄存器包括第二输入子电路的情况下，所述第二输入子电路包括第八晶体管；
    所述第八晶体管的栅极连接到所述第二信号端，第一极连接到所述第一节点，第二极连接到所述第四电压端。
  13. 根据权利要求4所述的移位寄存器，其中，所述下拉子电路包括第九晶体管和第十晶体管，所述输出子电路包括第十一晶体管和第二电容；
    所述第九晶体管的栅极连接到所述下拉节点，第一极连接到所述第二节点，第二极连接到所述第三电压端；
    所述第十晶体管的栅极连接到所述下拉节点，第一极连接到所述信号输出端，第二极连接到所述第三电压端；
    所述第二电容的第一极连接到所述上拉节点，第二极连接到所述信号输出端；
    所述第十一晶体管的栅极连接到所述上拉节点，第一极连接到所述第二时钟信号端，第二极连接到所述信号输出端。
  14. 根据权利要求5所述的移位寄存器，其中，在所述移位寄存器包括初始化子电路的情况下，所述初始化子电路包括第十二晶体管；
    所述第十二晶体管的栅极连接到所述第三信号端，第一极连接到所述下拉节点，第二极连接到所述第二电压端。
  15. 根据权利要求5所述的移位寄存器，其中，在所述移位寄存器包括残荷消除子电路的情况下，所述残荷消除子电路包括第十三晶体管、第十四晶体管和第十五晶体管；
    所述第十三晶体管的栅极连接到所述第四信号端，第一极连接到所述下拉节点，第二极连接到所述第三电压端；
    所述第十四晶体管的栅极连接到所述第四信号端，第一极连接到所述信号输出端，第二极连接到所述第四信号端；
    所述第十五晶体管的栅极连接到所述第四信号端，第一极连接到所述第二节点，第二极连接到所述第三电压端。
  16. 一种栅极驱动电路，包括至少两级级联的如权利要求1-15任一项所述的移位寄存器；
    第一级移位寄存器的第一信号端与起始信号端相连接；
    除了所述第一级移位寄存器以外，每一级移位寄存器的第一信号端与其上一级移位寄存器的信号输出端相连接。
  17. 根据权利要求16所述的栅极驱动电路，其中，在所述移位寄存器包括第二信号输入子电路的情况下，除了最后一级移位寄存器以外，每一级移位寄存器的第二信号端与其下一级移位寄存器的信号输出端相连接；
    所述最后一级移位寄存器的第二信号端连接所述起始信号端或者复位信号端。
  18. 根据权利要求16所述的栅极驱动电路，其中，所述移位寄存器包括输出子电路的情况下；
    奇数级的移位寄存器中第一时钟信号端与第一时钟信号线连接，第二时钟信号端与第二时钟信号线连接；偶数级的移位寄存器中第一时钟信号端与所述第二时钟信号线连接，第二时钟信号端与所述第一时钟信号线连接。
  19. 一种显示装置，其特征在于，包括权利要求16-18任一项所述的栅极驱动电路。
  20. 一种用于驱动权利要求1-15任一项所述的移位寄存器单元的驱动方法，包括：
    输入阶段：
    在来自第一电压端的电压的控制下，第一输入子电路将第一信号端的电压输出至第一节点，以通过所述第一节点的电压控制上拉控制子电路开启，将第二电压端的电压经第二节点输出至上拉节点；同时，在来自所述第一节点的电压的控制下，下拉控制子电路将第三电压端的电压输出至下拉节点；
    输出阶段：
    在来自所述第一节点的电压的控制下，使所述上拉控制子电路处于关闭状态；并在来自信号输出端的电压的控制下，所述下拉控制子电路将所述第三电压端的电压输出至所述下拉节点；
    下拉阶段：
    在来自所述第一节点的电压的控制下，使所述上拉控制子电路处于关闭状态；并在第一时钟信号端的控制下，所述下拉控制子电路将所述第一时钟信号端的时钟信号输出至下拉节点。
  21. 根据权利要求20所述的驱动方法，其中，所述移位寄存器包括滤波子电路、下拉子电路和输出子电路的情况下；
    在所述输入阶段，所述方法还包括：
    所述滤波子电路将所述第二节点输入的电压中的杂波滤除后输出至所述上拉节点；
    在所述输出阶段，所述方法还包括：
    在来自所述上拉节点的电压的控制下，所述输出子电路将第二时钟信号端的时钟信号输出至信号输出端，所述信号输出端输出栅极扫描信号；
    在所述下拉阶段，所述方法还包括：
    在来自所述下拉节点的电压的控制下，下拉子电路将第三电压端的电压输出至所述第二节点，所述滤波子电路将所述第二节点输入的电压中的杂波滤除后输出至所述上拉节点，控制所述输出子电路关闭；所述下拉子电路还将所述第三电压端的电压输出至所述信号输出端。
  22. 根据权利要求21所述的驱动方法，其中，所述移位寄存器包括初始化子电路和残荷消除子电路的情况下；
    所述方法还包括：
    初始化阶段：
    在来自第三信号端的信号的控制下，所述初始化子电路将所述第二电压端的电压输出至所述下拉节点；
    在来自所述下拉节点的电压的控制下，下拉子电路将所述第三电压端的电压输出至所述第二节点，所述滤波子电路将所述第二节点输入的电压中的杂波滤除后输出至所述上拉节点；所述下拉子电路还将所述第三电压端的电压输出至所述信号输出端；
    残荷消除阶段：
    在来自第四信号端的信号的控制下，所述残荷消除子电路将所述第三电压端的电压输出至所述下拉节点和所述第二节点，所述滤波子电路将所述第二节点输入的电压中的杂波滤除后输出至所述上拉节点；所述残荷消除子电路还将所述第四信号端的电压输出至所述信号输出端。
  23. 一种用于驱动权利要求2-15任一项所述的移位寄存器单元的驱动方法，其中，所述移位寄存器包括第二输入子电路的情况下；
    所述驱动方法包括：
    输入阶段：
    在来自第四电压端的电压的控制下，第二输入子电路将第二信号端输入的电压输出至所述第一节点，以通过所述第一节点的电压控制上拉控制子电路开启，将第二电压端的电压经第二节点输出至上拉节点；同时，在来自所述第一节点的电压的控制下，下拉控制子电路将第三电压端的电压输出至下拉节点；
    输出阶段：
    在来自所述第一节点的电压的控制下，使所述上拉控制子电路处于关闭状态；并在来自信号输出端的电压的控制下，所述下拉控制子电路将所述第三电压端的电压输出至所述下拉节点；
    下拉阶段：
    在来自所述第一节点的电压的控制下，使所述上拉控制子电路处于关闭状态；并在第一时钟信号端的控制下，所述下拉控制子电路将所述第一时钟信号端的时钟信号输出至下拉节点。
PCT/CN2018/111954 2017-12-08 2018-10-25 移位寄存器、栅极驱动电路及驱动方法、显示装置 Ceased WO2019109751A1 (zh)

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