WO2019118651A1 - Fabrication of high-temperature superconducting striated tape combinations - Google Patents

Fabrication of high-temperature superconducting striated tape combinations Download PDF

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Publication number
WO2019118651A1
WO2019118651A1 PCT/US2018/065296 US2018065296W WO2019118651A1 WO 2019118651 A1 WO2019118651 A1 WO 2019118651A1 US 2018065296 W US2018065296 W US 2018065296W WO 2019118651 A1 WO2019118651 A1 WO 2019118651A1
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WIPO (PCT)
Prior art keywords
striated
temperature superconducting
tape
sided adhesive
laser
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Ceased
Application number
PCT/US2018/065296
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French (fr)
Inventor
Joseph C. PRESTIGIACOMO
Raymond C.Y. AUYEUNG
Michael S. OSOFSKY
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US Department of Navy
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US Department of Navy
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Publication date
Application filed by US Department of Navy filed Critical US Department of Navy
Priority to KR1020207020343A priority Critical patent/KR20200099555A/en
Priority to EP18888651.9A priority patent/EP3724898A4/en
Priority to JP2020542823A priority patent/JP2021516443A/en
Priority to CA3089491A priority patent/CA3089491A1/en
Publication of WO2019118651A1 publication Critical patent/WO2019118651A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/02—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape
    • B23K35/0222—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape for use in soldering or brazing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01B—CABLES; CONDUCTORS; INSULATORS; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING OR DIELECTRIC PROPERTIES
    • H01B12/00—Superconductive or hyperconductive conductors, cables, or transmission lines
    • H01B12/02—Superconductive or hyperconductive conductors, cables, or transmission lines characterised by their form
    • H01B12/06—Films or wires on bases or cores
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B23K1/0008—Soldering, e.g. brazing, or unsoldering specially adapted for particular articles or work
    • B23K1/0016—Soldering of electronic components
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K3/00—Tools, devices or special appurtenances for soldering, e.g. brazing, or unsoldering, not specially adapted for particular methods
    • B23K3/06—Solder feeding devices; Solder melting pans
    • B23K3/0607—Solder feeding devices
    • B23K3/0623—Solder feeding devices for shaped solder piece feeding, e.g. preforms, bumps, balls, pellets, droplets
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01B—CABLES; CONDUCTORS; INSULATORS; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING OR DIELECTRIC PROPERTIES
    • H01B13/00—Apparatus or processes specially adapted for manufacturing conductors or cables
    • H01B13/0036—Details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3465—Application of solder
    • H05K3/3478—Application of solder preforms; Transferring prefabricated solder patterns
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/01—Manufacture or treatment
    • H10N60/0268—Manufacture or treatment of devices comprising copper oxide
    • H10N60/0661—Processes performed after copper oxide formation, e.g. patterning
    • H10N60/0688—Etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/01—Manufacture or treatment
    • H10N60/0268—Manufacture or treatment of devices comprising copper oxide
    • H10N60/0801—Manufacture or treatment of filaments or composite wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/20—Permanent superconducting devices
    • H10N60/203—Permanent superconducting devices comprising high-Tc ceramic materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/04—Apparatus for manufacture or treatment
    • H10P72/0428—Apparatus for mechanical treatment or grinding or cutting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/50—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for positioning, orientation or alignment
    • H10P72/53—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for positioning, orientation or alignment using optical controlling means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7402—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/78—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using vacuum or suction, e.g. Bernoulli chucks
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K2101/00—Articles made by soldering, welding or cutting
    • B23K2101/36—Electric or electronic devices
    • B23K2101/42—Printed circuits
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
    • B23K35/24—Selection of soldering or welding materials proper
    • B23K35/26—Selection of soldering or welding materials proper with the principal constituent melting at less than 400°C
    • B23K35/264—Bi as the principal constituent
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0502—Patterning and lithography
    • H05K2203/0531—Decalcomania, i.e. transfer of a pattern detached from its carrier before affixing the pattern to the substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/10—Using electric, magnetic and electromagnetic fields; Using laser light
    • H05K2203/107—Using laser light
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/15—Position of the PCB during processing
    • H05K2203/1545—Continuous processing, i.e. involving rolls moving a band-like or solid carrier along a continuous production path
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/16—Inspection; Monitoring; Aligning
    • H05K2203/167—Using mechanical means for positioning, alignment or registration, e.g. using rod-in-hole alignment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7408—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support the auxiliary support including alignment aids
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H10W72/01904—Manufacture or treatment of bond pads using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E40/00—Technologies for an efficient electrical power generation, transmission or distribution
    • Y02E40/60—Superconducting electric elements or equipment; Power systems integrating superconducting elements or equipment
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P80/00—Climate change mitigation technologies for sector-wide applications
    • Y02P80/30—Reducing waste in manufacturing processes; Calculations of released waste quantities

Definitions

  • This disclosure concerns high-temperature superconducting striated tape and methods of making high-temperature superconducting striated tape combinations.
  • This disclosure concerns high-temperature superconducting striated tape and methods of making high-temperature superconducting striated tape combinations.
  • tape in this invention is generalized to mean structures that do or do not contain adhesive.
  • HTS zero DC resistance property
  • the second generation (2G) HTS coated conductors used in such DC applications consist of flat metal tapes coated by thin layers of oxide buffer layers and thin HTS coatings.
  • Different types of cables and wires that use 2G HTS are being developed for high current applications but the flat geometry causes significant losses in AC applications.
  • AC loss of YBCO coated conductors can be reduced by dividing the YBCO film into thin filament arrays. AC losses can be further reduced by the periodic introduction of filament bridges along the conductor length that allow for flux penetration in all the filaments.
  • This approach requires that two striated HTS tapes be bonded with the filament sides facing each other separated by an insulating layer. The filaments from the two tapes must electrically connect each another only at the edges to prevent shorting. Table I.
  • the insulating layer creates a gap between the tapes that complicates the electrical bonding process.
  • the insulating layers previously used do not provide adequate isolation of adjacent filaments during solder bonding.
  • the filament widths in HTS tapes are ⁇ few hundred microns and openings in the insulating layer must be aligned precisely between the upper and lower filaments.
  • This invention disclosure describes a process that enables the precise alignment and placement of the HTS striated tape and insulating layers by incorporating indexing holes in each constituent tape.
  • This invention disclosure enables reliable adhesion of the top and bottom tapes while providing containment of solder to the bond area without relying on just electrical bonds for adhesion strength.
  • This disclosme teaches methods for making high-temperature superconducting striated tape and the product high- temperature superconducting striated tape.
  • This disclosure describes an efficient and scalable method for aligning and bonding two superimposed high-temperature superconducting (HTS) filamentary tapes to form a single integrated tape structure.
  • HTS high-temperature superconducting
  • This invention aligns a bottom and top HTS tape with a thin intervening insulator layer with microscopic precision, and electrically connects the two sets of tape filaments with each other.
  • the insulating layer also reinforces adhesion of the top and bottom tapes, mitigating mechanical stress at the electrical connections.
  • FIG 1 is an illustration of final components in assembled tape and actual components used to fabricate the striated tape structure for low AC loss.
  • Drawing is not to scale.
  • Figure 2 illustrates a step-by-step diagram of the low AC-loss HTS cable fabrication process. Step #2 is performed on a separate fixture.
  • This disclosure teaches electrically and mechanically connected high-temperature superconducting striated tape combinations and methods of making electrically and mechanically connected high-temperature superconducting striated tape combinations.
  • This disclosure describes an efficient and scalable method for aligning and bonding two superimposed high-temperature superconducting (HTS) filamentary tapes to form a single integrated tape structure.
  • HTS high-temperature superconducting
  • This invention aligns a bottom and top HTS tape with a thin intervening insulator layer with microscopic precision, and electrically connects the two sets of tape filaments with each other.
  • the insulating layer also reinforces adhesion of the top and bottom tapes, mitigating mechanical stress at the electrical connections.
  • An alignment jig (not shown) with index pins is used to align all components together.
  • An alignment jig is a device or structure that helps align and assemble all the separate components together on a 2-D planar or 3-D curved surface with high precision. With judicious choice of indexing holes and pins in each component of the superconducting tape structure, all components can be aligned and bonded with less than 50 microns spatial tolerance. Other methods of indexing each component of the striated tape structure such as mechanical means (e.g. notches, holes, guides) or optical means (e.g. laser, LED, lamp) are possible. As long as there is a’complementary’ structure on the alignment jig to match the indexed component, then high spatial accuracy can be maintained.
  • the striated HTS tapes are made by laser lithography and patterning techniques and the indexing holes are made by laser micromachining.
  • liquid photoresists can be applied to the tape using spray, spin or dip processes, or a solid film photoresist can be laminated to the tape.
  • a solid film resist can be pre-patterned and pre-indexed before being applied to the tape and could simplify the setup and shorten processing time.
  • indexing holes may be used to ensure alignment over long lengths.
  • index holes can be spaced regularly along both edges of the tape in a reel-to-reel system.
  • the indexing holes can also be made in a separate carrier to which the HTS tape is securely attached. This arrangement would conserve the HTS material while still taking advantage of the indexing feature.
  • the double-sided adhesive is 1 mil thick (adhesive only) and initially protected by a liner on both sides.
  • the DSA is rated for operation over a wide temperature range (-185 to 260°C).
  • Openings that coincide with the ends of the HTS filaments are laser-machined through the adhesive.
  • This adhesive (with one liner removed) is carefully aligned and placed over one of the HTS tapes using the alignment jig.
  • HTS high-temperature superconductor
  • Solder preform release tape with indexing holes
  • DSA Double-sided silicone-based thin adhesive
  • Alignment jig with indexing pins for aligning and bonding tape structures Alignment jig with indexing pins for aligning and bonding tape structures.
  • Laser micromachining system which includes: a) Laser - preferably pulsed UV (355 nm wavelength, 30-70 ns pulsewidth, > 10 kHz repetition rate) with enough energy to both expose photoresist and laser-cut thin metal foils ( ⁇ 500 microns) and b) Laser micromachining system incorporating a) fast-scanning galvanometric (galvo) mirrors, laser pulse amplitude and timing control, high-precision and accuracy X-Y translation stage pair, vacuum chuck, parfocal optical inspection camera, and stage and mirror scanning software.
  • UV 355 nm wavelength, 30-70 ns pulsewidth, > 10 kHz repetition rate
  • Laser micromachining system incorporating a) fast-scanning galvanometric (galvo) mirrors, laser pulse amplitude and timing control, high-precision and accuracy X-Y translation stage pair, vacuum chuck, parfocal optical inspection camera, and stage and mirror scanning software.
  • the DSA must be laser-cut with a pattern of‘through-hole’ windows that matches the pattern of solder preforms.
  • the sizes of these windows must allow the solder to flow and fill the window area to a uniform thickness without excess material escaping beyond the window edges.
  • the sizes of the windows must be designed in conjunction with the solder and DSA thicknesses such that the reflowed / melted solder thickness will not exceed the DSA thickness.
  • the laser energy and galvo scan parameters must be chosen to cut completely through the liners and adhesive without causing any melting which would make it difficult to remove the liners without damaging the adhesive.
  • non-adhesive tabs must be fabricated to extend beyond the adhesive portion of the DSA to facilitate its handling and application onto a receiving surface.
  • indexing holes must also be laser-cut into the DSA tape without damaging the adhesive.
  • the critical factor in creating a striated tape structure is the precision bonding of narrow individual filaments from the top and bottom tapes to form a continuous circuit.
  • the indexing holes of all components of the superconducting tape assembly and the indexing pins of the alignment jig ensure precise spatial alignment between all components with very low errors.
  • edge bonds formed by diffusion bonding require either crimping at the edges [1], etching a recessed area of the filament’s silver coating in order to fill the interior region with photoresist as insulation and create a raised mesa contact area at the edge [2], or sputtering additional silver.
  • a more practical solution is to use a low melting temperature solder for bonding the 2G HTS coated conductors that prevents damaging or delaminating the layered structure.
  • solder Several types of solder exist with different melting temperatures and resistivities at 77 K, (T m , R k), such as In Sii (118°C, 12.5 mW-cm), Wood’s metal (70°C, 19.3 mW-cm), In 2 Bi (72°C, 39 mW-cm), and B ⁇ h ⁇ eSnn (79°C, 41 mW-cm) [17]
  • In 2 Bi solder is recommended because of the low melting temperature and its commercial availability in a flat ribbon form.
  • a simple soldering method for selectively bonding multiple isolated areas on a surface exploits the different solder wetting properties of the filament surfaces and the insulator layers (as in solder masking) so that the solder would only bond to the filament areas.
  • This technique is traditionally used with solder pastes; however, the high temperatures needed to activate the solder flux are incompatible with 2G HTS tapes.
  • either the edges of the entire tape structure can be dipped in a low melting temperature eutectic solder or a bead of solder applied to the tape edges.
  • tests have shown that the solder occasionally adheres to the insulator layer and solder bonds were inconsistent at the filaments.
  • Solder preforms deliver a consistent and precise amount of solder in various shapes and sizes and are used routinely in‘pick-and-place’ machines in electronics assembly lines.
  • a reel of solder preforms of a prescribed shape and size could be used in a‘pick-and-place’ machine to bond to the striated tape.
  • this is a serial process which may limit throughput.
  • solder preforms of any geometry By pre-placing solder preforms of any geometry at pre -determined locations on a release tape, then the entire pattern of solder preforms can be transferred and bonded to the striated tape in a parallel manner thereby increasing throughput.
  • DIBS Decal Imprinting and Bonding of Solder
  • solder release tape canbe easily adapted to a reel-to-reel system by using regularly spaced indexed holes to match the guide pins in a rotating reel.
  • the solder preforms before reflow are slightly higher than the adhesive (e.g. In 2 Bi 2-mil thick eutectic solder ribbon) and are placed (using DIBS) onto a bare striated HTS tape or the HTS tape already covered with the adhesive.
  • the adhesive e.g. In 2 Bi 2-mil thick eutectic solder ribbon
  • the thickness of the adhesive and the solder preforms are minimized to reduce electrical resistive losses, but the two thicknesses must be designed together with the DSA window such that the final thickness of the reflowed solder does not exceed the thickness of the DSA nor the final solder dimensions exceed those of the DSA window.
  • the ends of each filament can be widened to increase the solder bond area and hence lower its contact resistance.
  • the first and final few filaments terminate in large pads that allow the attachment of leads for electrical measurement across the transposed region.
  • the current lead pads of striated HTS tape #1 are solder-bonded to the extended pads on tape #2 to allow leads access to the pads on the same side. This last feature reduces shearing forces between tapes when clamping the pads since only one side of the stacked tape structure is gripped.
  • top striated HTS tape is next placed over the alignment jig with the filament side facing the adhesive using the indexing pins as guides.
  • the alignment jig is then placed in a press and then heat and/or pressure treated to melt the solder to provide electrical connection between the lower and upper HTS filaments.
  • Typical heat, pressure, and time conditions are 200°F at 250 PSI for ⁇ 10s.
  • the striated tapes can be made by laser ablation but its AC loss properties may not be as good as those made by laser lithography.
  • Other double-sided thin adhesive layers or even photodefinable films such as a photoresist film (Riston) can also be used but must be amenable to laser machining or photopatteming and can survive temperatures near liquid nitrogen (-196 °C).
  • Solder preforms can be loaded and bonded to the striated tape by another apparatus if it can handle thin ( ⁇ 2 mil) and small (100’s pm - 1mm) objects and place them in precise microscopic locations reliably.
  • This invention provides an efficient and scalable method for aligning and bonding two superimposed high-temperature superconducting (HTS) filamentary tapes to form a single integrated tape structure.
  • HTS high-temperature superconducting
  • This invention enables the alignment of a bottom and top HTS tape with a thin intervening insulator layer with microscopic precision, and electrically connects the two sets of tape filaments with each other.
  • the insulating layer also reinforces adhesion of the top and bottom tapes, mitigating mechanical stress at the electrical connections.
  • This method of fabricating a striated HTS tape structure allows precision alignment and bonding of filaments between an upper and lower HTS striated tape.
  • the alignment can be maintained before and during the bonding process with high spatial precision and accuracy.
  • the thin double-sided adhesive minimizes the thickness of the insulating layer and therefore, the contact resistance between the upper and lower filaments.
  • This invention in combination with DIBS, enables the precise placement of a consistent volume of solder at the bond locations of each filament thus ensuring reliable electrical connection and eliminating interfilamentaiy shorting.
  • the double sided adhesive provides mechanical bonding and the solder preforms provide electrical bonding.

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Abstract

This disclosure teaches methods for making high-temperature superconducting striated tape combinations and the product high-temperature superconducting striated tape combinations. This disclosure describes an efficient and scalable method for aligning and bonding two superimposed high-temperature superconducting (HTS) filamentary tapes to form a single integrated tape structure. This invention aligns a bottom and top HTS tape with a thin intervening insulator layer with microscopic precision, and electrically connects the two sets of tape filaments with each other. The insulating layer also reinforces adhesion of the top and bottom tapes, mitigating mechanical stress at the electrical connections. The ability of this method to precisely align separate tapes to form a single tape structure makes it compatible with a reel-to-reel production process.

Description

TITLE OF THE INVENTION
Fabrication of High-Temperature Superconducting Striated Tape Combinations REFERENCE TO RELATED APPLICATION
This application is a non-provisional of, and claims priority to and the benefits of, United States Provisional Patent Application Number 62/598,541 filed on December 14, 2017, United States Provisional Patent Application Number 62/598,539 filed on December 14, 2017, and United States Provisional Patent Application Number 62/728,650 filed on September 07, 2018.
TECHNICAL FIELD
This disclosure concerns high-temperature superconducting striated tape and methods of making high-temperature superconducting striated tape combinations.
BACKGROUND ART
This disclosure concerns high-temperature superconducting striated tape and methods of making high-temperature superconducting striated tape combinations.
The term‘tape’ in this invention is generalized to mean structures that do or do not contain adhesive.
The zero DC resistance property of HTS enable them to carry large currents even in significant magnetic fields and thus enables the reduction of conductor weight and volume of various systems.
The second generation (2G) HTS coated conductors used in such DC applications consist of flat metal tapes coated by thin layers of oxide buffer layers and thin HTS coatings. Different types of cables and wires that use 2G HTS are being developed for high current applications but the flat geometry causes significant losses in AC applications.
The lack of conductors and cables suitable for AC applications has created a bottleneck that complicates the development of inductors, transformers, and stators for motors and generators.
There has been no demonstration of a practical transposed multifilament twisted HTS coated conductor with low AC losses.
AC loss of YBCO coated conductors can be reduced by dividing the YBCO film into thin filament arrays. AC losses can be further reduced by the periodic introduction of filament bridges along the conductor length that allow for flux penetration in all the filaments. This approach requires that two striated HTS tapes be bonded with the filament sides facing each other separated by an insulating layer. The filaments from the two tapes must electrically connect each another only at the edges to prevent shorting. Table I.
Figure imgf000004_0001
A summary of previous work in connecting two composite electrical tapes face-to-face is given in Table I.
There are several technical challenges associated with these prior art methods.
First, in all cases the integrity of the bond relies on the mechanical strength of the electrical connection for adhesion.
Second, the time required for diffusion bonding prevents practical scale-up of the fabrication.
Third, the insulating layer creates a gap between the tapes that complicates the electrical bonding process.
Fourth, the insulating layers previously used do not provide adequate isolation of adjacent filaments during solder bonding.
Fifth, the filament widths in HTS tapes are < few hundred microns and openings in the insulating layer must be aligned precisely between the upper and lower filaments.
This invention disclosure describes a process that enables the precise alignment and placement of the HTS striated tape and insulating layers by incorporating indexing holes in each constituent tape.
This invention disclosure enables reliable adhesion of the top and bottom tapes while providing containment of solder to the bond area without relying on just electrical bonds for adhesion strength.
DISCLOSURE OF INVENTION
Description
This disclosme teaches methods for making high-temperature superconducting striated tape and the product high- temperature superconducting striated tape.
This disclosure describes an efficient and scalable method for aligning and bonding two superimposed high-temperature superconducting (HTS) filamentary tapes to form a single integrated tape structure.
This invention aligns a bottom and top HTS tape with a thin intervening insulator layer with microscopic precision, and electrically connects the two sets of tape filaments with each other.
The insulating layer also reinforces adhesion of the top and bottom tapes, mitigating mechanical stress at the electrical connections.
The ability of this method to precisely align separate tapes to form a single tape structure makes it compatible with a reel-to-reel production process. BRIEF DESCRIPTION OF THE DRAWINGS
The following description and drawings set forth certain illustrative implementations of the disclosure in detail, which are indicative of several exemplary ways in which the various principles of the disclosure may be carried out. The illustrated examples, however, are not exhaustive of the many possible embodiments of the disclosure. Other objects, advantages and novel features of the disclosure will be set forth in the following detailed description when considered in conjunction with the drawings.
Figure 1 is an illustration of final components in assembled tape and actual components used to fabricate the striated tape structure for low AC loss. Double sided adhesive (DSA) shown with backing layers present and solder preforms shown attached to release tape for the decal imprinting and bonding of solder (DIBS) procedure, invented by the same inventors and detailed in another patent application. Drawing is not to scale. Figure 2 illustrates a step-by-step diagram of the low AC-loss HTS cable fabrication process. Step #2 is performed on a separate fixture.
BEST MODE FOR CARRYING OUT THE INVENTION
This disclosure teaches electrically and mechanically connected high-temperature superconducting striated tape combinations and methods of making electrically and mechanically connected high-temperature superconducting striated tape combinations.
This disclosure describes an efficient and scalable method for aligning and bonding two superimposed high-temperature superconducting (HTS) filamentary tapes to form a single integrated tape structure.
This invention aligns a bottom and top HTS tape with a thin intervening insulator layer with microscopic precision, and electrically connects the two sets of tape filaments with each other.
The insulating layer also reinforces adhesion of the top and bottom tapes, mitigating mechanical stress at the electrical connections.
The ability of this method to precisely align separate tapes to form a single tape structure makes it compatible with a reel-to-reel production process.
Example 1
The basic components of a bonded striated tape are shown in Figure 1.
It consists of two striated HTS tapes, an insulator (and adhesive) layer and solder preforms.
An alignment jig (not shown) with index pins is used to align all components together. An alignment jig is a device or structure that helps align and assemble all the separate components together on a 2-D planar or 3-D curved surface with high precision. With judicious choice of indexing holes and pins in each component of the superconducting tape structure, all components can be aligned and bonded with less than 50 microns spatial tolerance. Other methods of indexing each component of the striated tape structure such as mechanical means (e.g. notches, holes, guides) or optical means (e.g. laser, LED, lamp) are possible. As long as there is a’complementary’ structure on the alignment jig to match the indexed component, then high spatial accuracy can be maintained.
The striated HTS tapes are made by laser lithography and patterning techniques and the indexing holes are made by laser micromachining.
With lithography, liquid photoresists can be applied to the tape using spray, spin or dip processes, or a solid film photoresist can be laminated to the tape.
Example 2
A solid film resist can be pre-patterned and pre-indexed before being applied to the tape and could simplify the setup and shorten processing time.
Depending on the chemistries of the process, either positive or negative resists could be used.
Note that different shapes and quantities of indexing holes may be used to ensure alignment over long lengths.
For example, rectangular index holes can be spaced regularly along both edges of the tape in a reel-to-reel system. The indexing holes can also be made in a separate carrier to which the HTS tape is securely attached. This arrangement would conserve the HTS material while still taking advantage of the indexing feature.
Example 3
The double-sided adhesive (DSA) is 1 mil thick (adhesive only) and initially protected by a liner on both sides.
The DSA is rated for operation over a wide temperature range (-185 to 260°C).
Openings that coincide with the ends of the HTS filaments are laser-machined through the adhesive.
This adhesive (with one liner removed) is carefully aligned and placed over one of the HTS tapes using the alignment jig.
Example 4
Two striated high-temperature superconductor (HTS) tapes or foils made by standard laser lithography and patterning techniques and include laser machined indexing holes.
Solder preform release tape with indexing holes.
Double-sided silicone-based thin adhesive, (DSA), with protective liners on both sides with a wide operating temperature range and with laser machined indexing holes.
Alignment jig with indexing pins for aligning and bonding tape structures.
Laser micromachining system which includes: a) Laser - preferably pulsed UV (355 nm wavelength, 30-70 ns pulsewidth, > 10 kHz repetition rate) with enough energy to both expose photoresist and laser-cut thin metal foils (< 500 microns) and b) Laser micromachining system incorporating a) fast-scanning galvanometric (galvo) mirrors, laser pulse amplitude and timing control, high-precision and accuracy X-Y translation stage pair, vacuum chuck, parfocal optical inspection camera, and stage and mirror scanning software.
The DSA must be laser-cut with a pattern of‘through-hole’ windows that matches the pattern of solder preforms. The sizes of these windows must allow the solder to flow and fill the window area to a uniform thickness without excess material escaping beyond the window edges. The sizes of the windows must be designed in conjunction with the solder and DSA thicknesses such that the reflowed / melted solder thickness will not exceed the DSA thickness. The laser energy and galvo scan parameters must be chosen to cut completely through the liners and adhesive without causing any melting which would make it difficult to remove the liners without damaging the adhesive. In addition, non-adhesive tabs must be fabricated to extend beyond the adhesive portion of the DSA to facilitate its handling and application onto a receiving surface. Of course, indexing holes must also be laser-cut into the DSA tape without damaging the adhesive.
The parts, structure and alignment of the final HTS assembly are the critical elements of this invention, the components of the striated tape structure can be assembled in different ways provided all the layers and their order are preserved as shown in Figure 1.
One option, as discussed below, is to bond the solder preforms onto one HTS tape first and then apply the DSA over this tape with the openings surrounding the preforms as shown in Figure 2.
Example 5
Place HTS tape #2 with patterned side facing up onto the alignment jig using the indexing pins as a guide.
Align the solder release tape with indexing holes (with the preforms facing the HTS tape) over the indexing pins of the alignment jig and press onto HTS tape #2.
Separate the release tape from the solder preforms leaving them bonded to the HTS tape #2.
Remove one liner and align the laser-patterned DSA over the indexing pins of the alignment jig before placing onto HTS tape #2. The windows of the DSA will be aligned with the solder preforms.
Remove second liner from DSA tape.
Align indexing holes of HTS tape # 1 (with patterned side facing tape #2) over the indexing pins of the alignment jig and place onto tape #2.
Apply pressure and/or heat to the entire assembly until solder has melted and bonded the entire HTS tape assembly.
The critical factor in creating a striated tape structure is the precision bonding of narrow individual filaments from the top and bottom tapes to form a continuous circuit. The indexing holes of all components of the superconducting tape assembly and the indexing pins of the alignment jig ensure precise spatial alignment between all components with very low errors.
As summarized in Table I, different methods have been used to electrically bond the filament edges from the two tapes. Three of these methods involve thermal annealing of the tapes to allow diffusion bonding across the interface of the two filament surfaces [ 1-3] . However, the long processing times (2-3 hours), high pressures (several MPa), and in some cases the pure 02 atmosphere [1,3] required limit this prior art method’s practicality. In addition, to make up for the gap between the tapes caused by the inclusion of an insulating layer, the edge bonds formed by diffusion bonding require either crimping at the edges [1], etching a recessed area of the filament’s silver coating in order to fill the interior region with photoresist as insulation and create a raised mesa contact area at the edge [2], or sputtering additional silver.
A more practical solution is to use a low melting temperature solder for bonding the 2G HTS coated conductors that prevents damaging or delaminating the layered structure. Several types of solder exist with different melting temperatures and resistivities at 77 K, (Tm, R k), such as In Sii (118°C, 12.5 mW-cm), Wood’s metal (70°C, 19.3 mW-cm), In2Bi (72°C, 39 mW-cm), and B^h^eSnn (79°C, 41 mW-cm) [17] In2Bi solder is recommended because of the low melting temperature and its commercial availability in a flat ribbon form. Measurements of single junction bonds of HTS filaments using In2Bi have shown that the contact resistance is similar to that achieved using diffusion bonding. In addition, the thermal expansion of the solder between room temperature and the operating temperature is a factor that must be considered. For In2Bi, the thermal expansion between 300 K and 77 K is approximately - 0.65% while YBCO coated conductor is approximately -0.25%. Despite this mismatch, no delamination effects upon cooldown have been observed.
A simple soldering method for selectively bonding multiple isolated areas on a surface exploits the different solder wetting properties of the filament surfaces and the insulator layers (as in solder masking) so that the solder would only bond to the filament areas. This technique is traditionally used with solder pastes; however, the high temperatures needed to activate the solder flux are incompatible with 2G HTS tapes. Alternatively, either the edges of the entire tape structure can be dipped in a low melting temperature eutectic solder or a bead of solder applied to the tape edges. However, tests have shown that the solder occasionally adheres to the insulator layer and solder bonds were inconsistent at the filaments. Even doctor blading the solder into well-defined windows over the striated tape did not produce sufficiently uniform bonds. Preventing the solder from bleeding out of the bond area and bridging to adjacent edge contacts becomes critical once their spacing reaches the order of the insulating layer thickness, since current sharing among adjacent filaments will negatively affect the transposed conduction path.
Solder preforms deliver a consistent and precise amount of solder in various shapes and sizes and are used routinely in‘pick-and-place’ machines in electronics assembly lines. A reel of solder preforms of a prescribed shape and size could be used in a‘pick-and-place’ machine to bond to the striated tape. However, since all the solder preforms on a reel are the same size and the preforms are individually placed onto the HTS tape, this is a serial process which may limit throughput. Example 6
By pre-placing solder preforms of any geometry at pre -determined locations on a release tape, then the entire pattern of solder preforms can be transferred and bonded to the striated tape in a parallel manner thereby increasing throughput.
The Decal Imprinting and Bonding of Solder (DIBS) process, described in a separate patent application, allows any combination of size, shape and location of solder preforms to be pre-assembled on a release tape and bonded collectively to a receiving surface.
Note that this solder release tape canbe easily adapted to a reel-to-reel system by using regularly spaced indexed holes to match the guide pins in a rotating reel.
For bonding the filaments in a stacked striated tape structure, the solder preforms before reflow are slightly higher than the adhesive (e.g. In2Bi 2-mil thick eutectic solder ribbon) and are placed (using DIBS) onto a bare striated HTS tape or the HTS tape already covered with the adhesive.
The thickness of the adhesive and the solder preforms are minimized to reduce electrical resistive losses, but the two thicknesses must be designed together with the DSA window such that the final thickness of the reflowed solder does not exceed the thickness of the DSA nor the final solder dimensions exceed those of the DSA window. The ends of each filament can be widened to increase the solder bond area and hence lower its contact resistance.
The first and final few filaments terminate in large pads that allow the attachment of leads for electrical measurement across the transposed region. The current lead pads of striated HTS tape #1 are solder-bonded to the extended pads on tape #2 to allow leads access to the pads on the same side. This last feature reduces shearing forces between tapes when clamping the pads since only one side of the stacked tape structure is gripped.
The top striated HTS tape is next placed over the alignment jig with the filament side facing the adhesive using the indexing pins as guides.
The alignment jig is then placed in a press and then heat and/or pressure treated to melt the solder to provide electrical connection between the lower and upper HTS filaments. Typical heat, pressure, and time conditions are 200°F at 250 PSI for <10s.
The striated tapes can be made by laser ablation but its AC loss properties may not be as good as those made by laser lithography. Other double-sided thin adhesive layers (or even photodefinable films such as a photoresist film (Riston)) can also be used but must be amenable to laser machining or photopatteming and can survive temperatures near liquid nitrogen (-196 °C). Solder preforms can be loaded and bonded to the striated tape by another apparatus if it can handle thin (< 2 mil) and small (100’s pm - 1mm) objects and place them in precise microscopic locations reliably.
This invention provides an efficient and scalable method for aligning and bonding two superimposed high-temperature superconducting (HTS) filamentary tapes to form a single integrated tape structure.
This invention enables the alignment of a bottom and top HTS tape with a thin intervening insulator layer with microscopic precision, and electrically connects the two sets of tape filaments with each other. The insulating layer also reinforces adhesion of the top and bottom tapes, mitigating mechanical stress at the electrical connections.
The ability of this method to precisely align separate tapes to form a single tape structure makes it compatible with a reel-to-reel production process.
This method of fabricating a striated HTS tape structure allows precision alignment and bonding of filaments between an upper and lower HTS striated tape.
By using indexing holes in the tapes and its components and indexing pins in an alignment jig, the alignment can be maintained before and during the bonding process with high spatial precision and accuracy.
The thin double-sided adhesive minimizes the thickness of the insulating layer and therefore, the contact resistance between the upper and lower filaments.
This invention, in combination with DIBS, enables the precise placement of a consistent volume of solder at the bond locations of each filament thus ensuring reliable electrical connection and eliminating interfilamentaiy shorting. The double sided adhesive provides mechanical bonding and the solder preforms provide electrical bonding. The features of the current invention (including DIBS) are easily adaptable to a reel-to-reel system and therefore hold high promise for its eventual
commercialization.
The above examples are merely illustrative of several possible embodiments of various aspects of the present disclosure, wherein equivalent alterations and/or modifications will occur to others skilled in the art upon reading and understanding this specification and the annexed drawings. In addition, although a particular feature of the disclosure may have been illustrated and/or described with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application. Also, to the extent that the terms "including", "includes", "having", "has", "with", or variants thereof are used in the detailed description and/or in the claims, such terms are intended to be inclusive in a manner similar to the term "comprising".

Claims

Claims What we claim is:
1. A method of making a high-temperature superconducting striated tape combination comprising the steps of: placing a first striated high-temperature superconducting tape with a patterned side facing up and with indexed holes onto an alignment jig using indexing pins as a guide;
placing a solder release tape with preforms and with indexed holes and wherein the preforms are facing the first striated high-temperature superconducting tape onto the first striated high-temperature superconducting tape on the alignment jig;
pressing the solder release tape with preforms wherein the preforms are facing the first striated high- temperature superconducting tape onto the first striated high-temperature superconducting tape;
separating the release tape from the solder preforms;
allowing the solder preforms to remain bonded to the first striated high-temperature superconducting tape;
providing a laser-patterned double sided adhesive with windows and with a first liner and a second liner and with indexed holes;
removing the first liner of the double sided adhesive;
aligning the laser-patterned double sided adhesive over the indexing pins of the alignment jig with the adhesive side facing the first striated high-temperature superconducting tape;
placing the laser-patterned double sided adhesive onto the first striated high-temperature superconducting tape;
wherein the windows of the laser-patterned double sided adhesive are aligned with the solder preforms;
removing the second liner from the laser-patterned double sided adhesive;
aligning indexing holes of a second striated high-temperature superconducting tape with patterned side facing the first striated high-temperature superconducting tape over the indexing pins of the alignment jig; placing the second striated high-temperature superconducting tape onto the laser-patterned double sided adhesive;
applying pressure and/or heat to the first striated high-temperature superconducting tape and to the laser-patterned double sided adhesive and to the second striated high-temperature superconducting tape; and bonding the first striated high-temperature superconducting tape and the laser-patterned double sided adhesive and the second striated high-temperature superconducting tape.
2. The method of making a high-temperature superconducting striated tape combination
of claim 1
wherein the alignment jig is a device or structure that aligns and assembles separate components on a 2- D planar or 3-D curved surface with precision.
3. The method of making a high-temperature superconducting striated tape combination
of claim 2 wherein the indexed hole matches a complementary index in the alignment jig.
4. The method of making a high-temperature superconducting striated tape combination
of claim 1
wherein the tape, double sided adhesive, and solder preforms are aligned and bonded with less than 50 microns spatial tolerance.
5. The method of making a high-temperature superconducting striated tape combination
of claim 1
wherein mechanical adhesion between the first striated high-temperature superconducting tape and the second striated high-temperature superconducting tape is provided by the double-sided adhesive.
6. The method of making a high-temperature superconducting striated tape combination
of claim 1
wherein electrical isolation or resistance between the first striated high-temperature superconducting tape and the second striated high-temperature superconducting tape is provided by the double-sided adhesive.
7. The method of making a high-temperature superconducting striated tape combination
of claim 1
wherein the double-sided adhesive operates from a temperature minimum of -185°C to a temperature maximum of at least 260°C.
8. The method of making a high-temperature superconducting striated tape combination
of claim 1
wherein the step of bonding the first striated high-temperature superconducting tape and the laser- patterned double sided adhesive and the second striated high-temperature superconducting tape occurs when the solder melts.
9. The method of making a high-temperature superconducting striated tape combination
of claim 8
wherein electrical continuity or conduction between electronic circuitry located on the first striated high-temperature superconducting tape and electronic circuitry located on the second striated high-temperature superconducting tape is provided by solder preforms.
10. The method of making a high-temperature superconducting striated tape combination
of claim 1
wherein the laser patterned double sided adhesive is laser-cut with a pattern of through-hole windows that matches the pattern of solder preforms.
11. The method of making a high-temperature superconducting striated tape combination of claim 1
wherein the method comprises a reel-to-reel system.
12. The method of making a high-temperature superconducting striated tape combination
of claim 11
wherein the temperature is at about 200°F.
13. The method of making a high-temperature superconducting striated tape combination
of claim 12
wherein the pressure is at about 250 PSI for <10 seconds.
14. A product of the process comprising the steps of:
placing a first striated high-temperature superconducting tape with a patterned side facing up and with indexed holes onto an alignment jig using indexing pins as a guide;
placing a solder release tape with preforms and with indexed holes and wherein the preforms are facing the first striated high-temperature superconducting tape onto the first striated high-temperature superconducting tape on the alignment jig;
pressing the solder release tape with preforms wherein the preforms are facing the first striated high- temperature superconducting tape onto the first striated high-temperature superconducting tape;
separating the release tape from the solder preforms;
allowing the solder preforms to remain bonded to the first striated high-temperature superconducting tape;
providing a laser-patterned double sided adhesive with windows and with a first liner and a second liner and with indexed holes;
removing the first liner of the double sided adhesive;
aligning the laser-patterned double sided adhesive over the indexing pins of the alignment jig with adhesive side facing the first striated high-temperature superconducting tape;
placing the laser-patterned double sided adhesive onto the first striated high-temperature superconducting tape;
wherein the windows of the laser-patterned double sided adhesive are aligned with the solder preforms;
removing the second liner from the laser-patterned double sided adhesive;
aligning indexing holes of a second striated high-temperature superconducting tape with patterned side facing the first striated high-temperature superconducting tape over the indexing pins of the alignment jig; placing the second striated high-temperature superconducting tape onto the laser-patterned double sided adhesive;
applying pressure and/or heat to the first striated high-temperature superconducting tape and to the laser-patterned double sided adhesive and to the second striated high-temperature superconducting tape; and bonding the first striated high-temperature superconducting tape and the laser-patterned double sided adhesive and the second striated high-temperature superconducting tape.
PCT/US2018/065296 2017-12-14 2018-12-12 Fabrication of high-temperature superconducting striated tape combinations Ceased WO2019118651A1 (en)

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JP2020542823A JP2021516443A (en) 2017-12-14 2018-12-12 Fabrication of combinations of high-temperature superconducting linear tapes
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KR20200099555A (en) 2020-08-24
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