WO2019137045A1 - 像素电路及其驱动方法、显示面板 - Google Patents

像素电路及其驱动方法、显示面板 Download PDF

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Publication number
WO2019137045A1
WO2019137045A1 PCT/CN2018/108759 CN2018108759W WO2019137045A1 WO 2019137045 A1 WO2019137045 A1 WO 2019137045A1 CN 2018108759 W CN2018108759 W CN 2018108759W WO 2019137045 A1 WO2019137045 A1 WO 2019137045A1
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Prior art keywords
circuit
control
signal
transistor
illumination control
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PCT/CN2018/108759
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English (en)
French (fr)
Inventor
高雪岭
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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Priority to JP2019547359A priority Critical patent/JP7159182B2/ja
Priority to EP18865349.7A priority patent/EP3739567B1/en
Priority to US16/342,035 priority patent/US11386838B2/en
Publication of WO2019137045A1 publication Critical patent/WO2019137045A1/zh
Anticipated expiration legal-status Critical
Priority to US17/859,159 priority patent/US11657759B2/en
Ceased legal-status Critical Current

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    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
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    • G09G2300/00—Aspects of the constitution of display devices
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    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
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    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G09G2300/0866—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes by means of changes in the pixel supply voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements

Definitions

  • Embodiments of the present disclosure relate to a pixel circuit, a driving method thereof, and a display panel.
  • Organic Light Emitting Diode (OLED) display devices are gradually gaining popularity due to their wide viewing angle, high contrast ratio, fast response speed, and higher brightness and lower driving voltage than inorganic light-emitting display devices. extensive attention. Due to the above characteristics, the organic light emitting diode (OLED) can be applied to a device having a display function such as a mobile phone, a display, a notebook computer, a digital camera, an instrument meter, and the like.
  • the pixel circuit in the OLED display device generally adopts a matrix driving method, and is divided into an active matrix (AM) driving and a passive matrix (PM) driving according to whether or not a switching component is introduced in each pixel unit.
  • AM active matrix
  • PM passive matrix
  • AMOLED integrates a set of thin film transistors and storage capacitors in the pixel circuit of each pixel. By controlling the driving of the thin film transistor and the storage capacitor, the current flowing through the OLED is controlled, so that the OLED is required according to the needs. Glowing.
  • AMOLED Compared with PMOLED, AMOLED requires less drive current, lower power consumption and longer life, which can meet the needs of large-size display with high resolution and multiple gray scales. At the same time, AMOLED has obvious advantages in terms of viewing angle, color reduction, power consumption and response time, and is suitable for display devices with high information content and high resolution.
  • At least one embodiment of the present disclosure provides a pixel circuit including a driving circuit, a data writing circuit, a compensation circuit, a reset circuit, and a first lighting control circuit.
  • the driving circuit includes a control end, a first end and a second end, and is configured to control a driving current for driving the light emitting element to emit light;
  • the data writing circuit is connected to the first end of the driving circuit, and is configured to respond to The scan signal writes a data signal to the first end of the drive circuit;
  • the compensation circuit is coupled to the control terminal and the second end of the drive circuit and coupled to the first voltage terminal, configured to be responsive to the scan signal and Writing the data signal to compensate the driving circuit;
  • the reset circuit is connected to the control terminal and the second end of the driving circuit and connected to the light emitting element, and is configured to reset the voltage in response to the reset signal Applied to a control end of the drive circuit and a first end of the light emitting element;
  • the first illumination control circuit is coupled to a first end of the drive circuit,
  • a pixel circuit provided by an embodiment of the present disclosure further includes a second illumination control circuit.
  • the first end and the second end of the second illumination control circuit are respectively coupled to the first end of the light emitting element and the second end of the drive circuit, and are configured to respond to the second illumination control signal to cause the A driving current can be applied to the light emitting element.
  • a pixel circuit provided by an embodiment of the present disclosure further includes an illumination control signal switching circuit.
  • the illumination control signal switching circuit is electrically connected to a control end of the first illumination control circuit and a control end of the second illumination control circuit, and is configured to transmit the first illumination control signal and in response to an illumination control switching signal
  • the second illumination control signal is alternately applied to a control end of the first illumination control circuit and a control end of the second illumination control circuit.
  • the driving circuit includes a first transistor.
  • a gate of the first transistor serves as a control end of the driving circuit, a first pole of the first transistor serves as a first end of the driving circuit, and a second pole of the first transistor serves as the driving circuit The second end.
  • the data writing circuit includes a second transistor.
  • a gate of the second transistor as a control end of the data write circuit is configured to be connected to a scan line to receive the scan signal, and a first pole of the second transistor is the first of the data write circuit The end is configured to be coupled to the data line to receive the data signal, and the second electrode of the second transistor is coupled to the first end of the data input circuit and the first end of the drive circuit.
  • the compensation circuit includes a third transistor and a capacitor. a gate of the third transistor and a scan line connected to receive the scan signal, a first pole of the third transistor being coupled to a control terminal of the driver circuit, a second pole of the third transistor, and the The second end of the driving circuit is connected; the first pole of the capacitor is connected to the control end of the driving circuit, and the second pole of the capacitor is connected to the first voltage terminal to receive the first voltage.
  • the reset circuit includes a fourth transistor and a fifth transistor.
  • a gate of the fourth transistor is connected to the reset control line to receive the reset signal, a first pole of the fourth transistor is connected to a control terminal of the driving circuit, and a second pole of the fourth transistor is reset a voltage terminal connected to receive the reset voltage;
  • a gate of the fifth transistor and the reset control line being connected to receive the reset signal, a first pole of the fifth transistor and a first end of the light emitting element Connected, the second pole of the fifth transistor is configured to be coupled to the reset voltage terminal to receive the reset voltage.
  • the first illumination control circuit includes a sixth transistor.
  • a gate of the sixth transistor as a control end of the first illumination control circuit is configured to be coupled to the first illumination control line to receive the first illumination control signal
  • the first pole of the sixth transistor being the a first end of the first illumination control circuit is configured to be coupled to the first voltage terminal to receive the first voltage
  • a second pole of the sixth transistor is used as a second end of the first illumination control circuit The first end of the drive circuit is connected.
  • the second illumination control circuit includes a seventh transistor.
  • a gate of the seventh transistor is connected as a control end of the second illumination control circuit and a second illumination control line to receive the second illumination control signal, and a first pole of the seventh transistor is used as the second
  • a second end of the illumination control circuit is coupled to the second end of the drive circuit, and a second end of the seventh transistor is coupled to the first end of the second illumination control circuit and the first end of the illumination element.
  • the first lighting control signal and the second lighting control signal are simultaneously an ON signal for at least part of a period of time.
  • the light emission control signal switching circuit includes an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor; a gate of the eighth transistor is configured to receive The illumination control switching signal, the first pole of the eighth transistor is coupled to the first illumination control line to receive the first illumination control signal, the second pole of the eighth transistor, and the first illumination control circuit a control terminal connection; the gate of the ninth transistor is configured to receive the illumination control switching signal, and the first pole of the ninth transistor and the second illumination control line are connected to receive the second illumination control signal, a second pole of the ninth transistor is connected to a control end of the second illuminating control circuit; a gate of the tenth transistor is configured to receive the illuminating control switching signal, a first pole of the tenth transistor a second illumination control line is connected, a second pole of the tenth transistor is connected to a control end of the first illumination control circuit; and a gate of the eleventh transistor is configured to be connected Receiving the
  • At least one embodiment of the present disclosure also provides a display panel including a plurality of pixel units arranged in an array.
  • the plurality of pixel units each include a pixel circuit and a light emitting element provided by an embodiment of the present disclosure.
  • the pixel circuit further includes an illumination control signal switching circuit, the first illumination control circuit, and a second illumination control circuit.
  • the illumination control signal switching circuit is electrically connected to the first illumination control line, the second illumination control line, the control end of the first illumination control circuit, and the control end of the second illumination control circuit, and is configured to respond to illumination control a switching signal alternately applying the first illumination control signal provided by the first illumination control line and the second illumination control signal provided by the second illumination control line to a control end of the first illumination control circuit and the a control end of the second illumination control circuit;
  • the display panel further includes a plurality of illumination control switching signal lines, the plurality of pixel units are arranged in a plurality of rows, and the control of the illumination control signal switching circuit of the pixel circuit of the m-th row pixel unit The end is connected to the same illumination control switching signal line, or the control end of the illumination control signal switching circuit of the pixel circuit of the mth pixel unit is connected to two illumination control switching
  • a first end of the light emitting element is configured to receive the driving current from a second end of the driving circuit, and a second end of the light emitting element is configured to The second voltage terminal is connected.
  • At least one embodiment of the present disclosure also provides a driving method of a pixel circuit, including: an initialization phase, a data writing and compensation phase, and an illumination phase.
  • the reset signal is input to turn on the reset circuit, the reset voltage is applied to a control terminal of the driving circuit and a first end of the light emitting element; and the data is written and compensated a step of inputting the scan signal and the data signal to turn on the data write circuit, the drive circuit, and the compensation circuit, the data write circuit writing the data signal to the drive circuit
  • the compensation circuit compensates the driving circuit; during the lighting phase, the first lighting control signal is input to turn on the first lighting control circuit and the driving circuit, and the first lighting control circuit will A driving current is applied to the light emitting element to cause it to emit light.
  • At least one embodiment of the present disclosure also provides a driving method of a pixel circuit, including: an initialization phase, a data writing and compensation phase, a pre-lighting phase, and an illumination phase.
  • the initialization phase inputting the reset signal and the second lighting control signal to turn on the reset circuit and the second lighting control circuit, and applying the reset voltage to the control end and the second end of the driving circuit And a first end of the light emitting element;
  • the data writing and compensating phase inputting the scan signal and the data signal to turn on the data write circuit, the drive circuit, and the compensation circuit Writing a data signal to the driving circuit, the compensation circuit compensating the driving circuit;
  • the pre-lighting phase inputting the first lighting control signal to turn on the first An illumination control circuit and the drive circuit, the first illumination control circuit applying the first voltage to a first end of the drive circuit; in the illumination phase, inputting the first illumination control signal and the a second lighting control signal to turn on the first lighting control circuit, the second lighting control circuit, and the driving circuit, the second lighting control circuit
  • At least one embodiment of the present disclosure also provides a driving method of a pixel circuit, including: an initialization phase, a data writing and compensation phase, a pre-lighting phase, and an illumination phase.
  • the initialization phase inputting the reset signal, the second illumination control signal, and the illumination control switching signal to turn on the reset circuit and the illumination control signal switching circuit to enable the second illumination control signal Applying to a control end of the first lighting control circuit or a control end of the second lighting control circuit, and applying the reset voltage to a control end of the driving circuit and a first end of the light emitting element;
  • the data writing and compensating stage inputting the scan signal and the data signal to turn on the data writing circuit, the driving circuit and the compensation circuit, wherein the data writing circuit writes the data signal Into the driving circuit, the compensation circuit compensates the driving circuit; in the pre-lighting phase, inputting the lighting control switching signal and the first lighting control signal to apply the first lighting control signal To the control end of the first illumination control circuit or the control end of the second illumination control circuit, the first
  • 1A is a schematic diagram of an image 1 displayed by a display device
  • FIG. 1B is a schematic diagram of an image 2 to be displayed by the above display device
  • 1C is a schematic diagram of an image 2 actually displayed by the above display device
  • FIG. 2 is a schematic block diagram of a pixel circuit according to an embodiment of the present disclosure
  • FIG. 3 is a schematic block diagram of another pixel circuit according to an embodiment of the present disclosure.
  • FIG. 4 is a circuit diagram showing a specific implementation example of the pixel circuit shown in FIG. 2;
  • FIG. 5 is a circuit diagram showing a specific implementation example of the pixel circuit shown in FIG. 3;
  • FIG. 5 is a circuit diagram showing a specific implementation example of the pixel circuit shown in FIG. 3;
  • FIG. 6 is a timing diagram of a driving method according to an embodiment of the present disclosure.
  • 7A to 7D are circuit diagrams showing four stages in the display process of the pixel circuit shown in FIG. 5 corresponding to the image of the Nth frame in FIG. 6;
  • 8A to 8D are circuit diagrams showing four stages in the display process of the pixel circuit shown in FIG. 5 corresponding to the image of the (N+1)th frame in FIG. 6;
  • FIG. 9 is a circuit diagram of a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 10 is a circuit diagram of another pixel circuit according to an embodiment of the present disclosure.
  • FIG. 11 is a schematic diagram of a display device according to an embodiment of the present disclosure.
  • the basic pixel circuit used in the AMOLED display device is usually a 2T1C pixel circuit, that is, a basic function of driving the OLED to emit light by using two TFTs (Thin-film transistors) and one storage capacitor Cs.
  • An OLED display device typically includes a plurality of pixel units arranged in an array, each of which may include, for example, the above-described pixel circuits.
  • the threshold voltage of the driving transistor in each pixel circuit may be different due to the fabrication process, and the threshold voltage of the driving transistor may be drifted due to, for example, a change in temperature. Therefore, the difference in the threshold voltage of each of the driving transistors may cause display failure (e.g., display unevenness), so it is necessary to compensate the threshold voltage. At the same time, when it is in the off state, it may cause poor display due to the presence of leakage current. Therefore, the industry also provides other pixel circuits with compensation functions based on the basic pixel circuits of the above 2T1C.
  • the compensation function can be implemented by voltage compensation, current compensation or hybrid compensation.
  • the pixel circuit with compensation function can be, for example, 4T1C or 4T2C, etc., will not be detailed here.
  • the hysteresis effect of the driving transistor in the pixel circuit of the display device due to the hysteresis effect of the driving transistor in the pixel circuit of the display device, when the display device displays the same image for a while, when the previous display image is switched to the next image, the original previous display image partially remains and appears below In an image, the afterimage disappears after a while, and this phenomenon is called a short-term afterimage.
  • the hysteresis effect is mainly caused by the shift of the threshold voltage (Vth) caused by the remaining movable carriers in the drive transistor.
  • V GS the voltage between the gate and source of the driving transistor
  • V GS the voltage between the gate and source of the driving transistor
  • FIG. 1A is a schematic diagram of an image displayed by a display device
  • FIG. 1B is a schematic diagram of an image 2 to be displayed by the display device
  • FIG. 1C is a schematic diagram of an image 2 actually displayed by the display device.
  • the display device displays an image, for example, a black and white checkerboard image as shown in FIG. 1A
  • a new image 2 for example, an image having a grayscale of 48 as shown in FIG. 1B
  • a checkerboard image of the image one shown in Fig. 1A is still partially retained, as shown in Fig. 1C.
  • the pixel circuit includes a driving circuit, a data writing circuit, a compensation circuit, a reset circuit, and a first lighting control circuit.
  • the driving circuit includes a control end, a first end and a second end, and is configured to control a driving current for driving the light emitting element to emit light;
  • the data writing circuit is connected to the first end of the driving circuit, and is configured to write the data signal in response to the scan signal a first end of the driving circuit;
  • the compensation circuit is connected to the control end and the second end of the driving circuit and connected to the first voltage end, configured to compensate the driving circuit in response to the scanning signal and the written data signal;
  • the reset circuit and a control end of the driving circuit and the light emitting element are connected, and configured to apply a reset voltage to the control end of the driving circuit and the first end of the light emitting element in response to the reset signal;
  • the first light emitting control circuit is connected to the first end of the driving circuit,
  • An illumination control circuit is configured to apply a first voltage of the first
  • At least one embodiment of the present disclosure also provides a driving method and a display panel corresponding to the above pixel circuit.
  • the pixel circuit and the driving method thereof and the display panel provided by the above embodiments of the present disclosure may, on the one hand, enable the driving transistor therein to be in an off-bias state or an on state (on-) in which V GS is a fixed bias in an initialization phase. Bias), thereby improving the short-term afterimage problem that may occur due to the hysteresis effect; on the other hand, the threshold voltage of the driving circuit of the pixel circuit can be compensated to avoid uneven display of the display device, thereby improving the adoption of the pixel The display effect of the display device of the circuit.
  • One example of an embodiment of the present disclosure provides a pixel circuit 10 that, for example, is used to drive a light-emitting element 600 in a sub-pixel of a display device to emit light.
  • the display panel of the display device is prepared, for example, by a glass substrate, and the specific structure and preparation process may employ a conventional method in the art, which will not be described in detail herein, and embodiments of the present disclosure No restrictions.
  • the pixel circuit 10 includes a driving circuit 100, a data writing circuit 200, a compensation circuit 300, a reset circuit 400, and a first lighting control circuit 500.
  • the driving circuit 100 includes a first end 110, a second end 120, and a control end 130 configured to control a driving current for driving the light emitting element 600 to emit light, and the control end 130 of the driving circuit 100 is connected to the first node N1, and the driving circuit The first end 110 of the 100 is connected to the second node N2, and the second end 120 of the driving circuit 100 is connected to the third node N3.
  • the driving circuit 100 may supply a driving current to the light emitting element 600 to drive the light emitting element 600 to emit light, and may emit light according to a desired "grayscale".
  • the light emitting element 600 may be an OLED or QLED (Quantum Dot Light Emitting Diodes) or the like, and configured to be connected to the third node N3 and the second voltage terminal VSS (eg, a low voltage terminal), the present disclosure Embodiments include, but are not limited to, this situation.
  • the display panel is an OLED display panel or a QLED display panel.
  • the OLED is taken as an example, and the corresponding description is also applicable to the QLED.
  • data write circuit 200 is coupled to first terminal 110 (second node N2) of drive circuit 100 and is configured to write a data signal to first end 110 of drive circuit 100 in response to the scan signal.
  • the data writing circuit 200 includes a first terminal 210, a second terminal 220, and a control terminal 230, and is connected to a data line (data signal terminal Vdata), a second node N2, and a scanning line (scanning signal terminal Gate), respectively.
  • a scan signal from the scan signal terminal Gate is applied to the control terminal 230 of the data write circuit 200 to control whether the data write circuit 200 is turned on or not.
  • the data write circuit 200 can be turned on in response to the scan signal so that the data signal can be written to the first end 110 (second node N2) of the drive circuit 100 and the data signal stored in the compensation
  • a driving current for driving the light-emitting element 600 to emit light can be generated based on the data signal, for example, at the light-emitting stage.
  • the magnitude of the data voltage Vdata determines the luminance of the pixel unit (ie, the grayscale used for display).
  • the compensation circuit 300 is connected to the control terminal 130 (first node N1) and the second terminal 120 (third node N3) of the driving circuit and is connected to the first voltage terminal VDD (eg, a high voltage terminal), configured to respond to The scan signal and the written data signal compensate the drive circuit 100.
  • the compensation circuit 300 can be connected to the scan signal terminal Gate, the first voltage terminal VDD, the first node N1, and the third node N3.
  • a scan signal from the scan signal terminal Gate is applied to the compensation circuit 300 to control whether it is turned on or not.
  • the compensation circuit 300 can be turned on in response to the scan signal, so that the data signal written by the data write circuit 200 can be stored in the capacitor.
  • the compensation circuit 300 can electrically connect the control terminal 130 and the second terminal 120 of the driving circuit 100, so that the related information of the threshold voltage of the driving circuit 100 can be correspondingly stored in the capacitor.
  • the drive circuit 100 can thus be controlled with a stored signal comprising a data signal and a threshold voltage, for example in the illumination phase, such that the output of the drive circuit 100 is compensated.
  • the light emitting element 600 includes a first end 610 and a second end 620, the first end 610 of the light emitting element 600 is configured to receive a driving current from the second end 120 of the driving circuit 100, and the second end 620 of the light emitting element 600 is configured to The second voltage terminal VSS is connected.
  • the first end 610 of the light emitting element 600 is connected to the fourth node N4.
  • the reset circuit 400 is coupled to the control terminal 130 (first node N1) of the driving circuit 100 and the first terminal 610 of the light emitting element 600, and is configured to apply the reset voltage Vint to the control terminal 130 of the driving circuit in response to the reset signal and The first end 610 of the light emitting element 600.
  • the reset circuit 400 is connected to the first node N1, the reset voltage terminal Vint, the first terminal 610 of the light-emitting element 600, and the reset control terminal Rst (reset control line), respectively.
  • the reset circuit 400 can be turned on in response to the reset signal, so that a reset voltage can be applied to the first node N1 and the first end 610 of the light emitting element 600, so that the driving circuit 100, the compensation circuit 300, and the light can be emitted Element 600 performs a reset operation that eliminates the effects of the previous illumination phase.
  • V GS satisfies:
  • Vth is usually a negative value.
  • Vth is usually It is a positive value so that the drive transistor is in an off-bias with V GS being a fixed bias.
  • the data signal of the previous frame is black or white
  • the driving transistor starts from a fixed biased off state to enter, for example, a data writing and compensation phase, thereby improving the conventional pixel circuit.
  • the short-term afterimage problem that may occur due to the hysteresis effect of the display device.
  • the first lighting control circuit 500 is coupled to the first end 110 (second node N2) of the driving circuit 100 and configured to apply a first voltage of the first voltage terminal VDD to the driving circuit 100 in response to the first lighting control signal.
  • the first end 110 the first illumination control circuit 500 includes a control terminal 530, a first end 510, and a second end 520, which are respectively connected to the first illumination control terminal Em1, the first voltage terminal VDD, and the second node N2.
  • the first lighting control terminal Em1 may be connected to a first lighting control line that provides a first lighting control signal or to a control circuit that provides a first lighting control signal.
  • the first illumination control circuit 500 can be turned on in response to the first illumination control signal, such that the first voltage VDD can be applied to the first terminal 110 of the driver circuit 100, and when the driver circuit 100 is turned on, The circuit 100 applies this first voltage VDD to the light emitting element 600 to provide a driving voltage, thereby driving the light emitting element to emit light.
  • the first voltage VDD can be a driving voltage, such as a high voltage.
  • the pixel circuit 10 may further include a second illumination control circuit 700.
  • the second illuminating control circuit 700 includes a control end 730, a first end 710 and a second end 720, which are respectively connected to the second illuminating control end Em2, the first end 610 of the illuminating element 600, and the second end 120 of the driving circuit 100. And configured to be responsive to the second lighting control signal such that a driving current can be applied to the light emitting element 600.
  • the second lighting control circuit 700 is turned on in response to the second lighting control signal provided by the second lighting control terminal Em2, so that the driving circuit 100 can apply a driving current to the light emitting element 600 through the second lighting control circuit 700.
  • the second light-emitting control circuit 700 is turned off in response to the second light-emitting control signal, thereby preventing current from flowing through the light-emitting element 600 to cause it to emit light, and the contrast of the corresponding display device can be improved.
  • the second lighting control circuit 700 can also be turned on in response to the second lighting control signal, so that the reset circuit can be combined to perform a reset operation on the driving circuit 100 and the light emitting element 600.
  • the second illumination control signal may be different from the first illumination control signal, for example, both may be connected to different signal outputs, as described above, for example, in the initialization phase, the second illumination control signal may be individually turned on.
  • the first illumination control signal and the second illumination control signal are simultaneously an ON signal for at least part of the time period, for example, in the illumination phase, the first illumination control signal and the second illumination control signal may be simultaneously turned on, so that the illumination component 600 can shine.
  • the falling edge of the second lighting control signal may also coincide with the falling edge of the first lighting control signal, thereby entering the lighting phase directly from the data writing and compensation phase.
  • the first illumination control signal and the second illumination control signal described in the embodiments of the present disclosure are two illumination control signals having different timings.
  • the first light emission control signal may be the first light emission control circuit 500 in the pixel circuit 10 of the pixel unit of the row.
  • the control signal at the same time, the first illumination control signal also controls the second illumination control circuit 700 in the pixel circuit 10 of the previous row; likewise, the second illumination control signal is the second illumination control circuit 700 in the pixel circuit 10 of the control line.
  • the control signal meanwhile, the second illumination control signal also controls the first illumination control circuit 500 in the next row of pixel circuits 10.
  • the driving circuit 100 is implemented as a driving transistor
  • the gate of the driving transistor may serve as the control terminal 130 of the driving circuit 100 (connected to the first node N1), and the first pole (eg, source) may function as a driving circuit
  • the first end 110 of the 100 connected to the second node N2), the second pole (eg, the drain) can serve as the second end 120 of the drive circuit 100 (connected to the third node N3).
  • the first voltage terminal VDD maintains an input DC high level signal, for example, the DC high level is referred to as a first voltage; and the second voltage terminal VSS maintains an input DC low level, for example.
  • the signal, the DC low level is referred to as a second voltage, for example, the second voltage is less than the first voltage.
  • the symbol Vdata can represent both the data signal end and the level of the data signal.
  • the symbol Vint can represent both the reset voltage terminal and the reset voltage.
  • VDD can represent both the first voltage terminal and the first voltage
  • the symbol VSS can represent both the second voltage terminal and the second voltage.
  • the pixel circuit 10 provided by the above embodiment of the present disclosure can not only improve the short-term afterimage problem that may be generated by the display device of the above-described pixel circuit due to the hysteresis effect, but also compensate the threshold voltage inside the driving circuit 100 so as to drive the driving of the light-emitting element 600.
  • the current is not affected by the threshold voltage, so that the display effect of the display device using the pixel circuit can be improved and the life of the light-emitting element 600 can be extended.
  • the pixel circuit 10 may further include an illumination control signal switching circuit 800.
  • the illumination control signal switching circuit 800 is electrically connected to the first illumination control terminal Em1, the second illumination control terminal Em2, the control terminal 530 of the first illumination control circuit 500, and the control terminal 730 of the second illumination control circuit 700, and is configured to respond.
  • the first illumination control signal and the second illumination control signal are alternately applied to the control terminal 530 of the first illumination control circuit 500 and the control terminal 730 of the second illumination control circuit 700 in the illumination control switching signal.
  • the illumination control switching signal may include one or more.
  • the illumination control signal switching circuit 800 can apply the first illumination control signal to the control terminal 530 of the first illumination control circuit 500 in response to the illumination control switching signal, and apply the second illumination control signal to the control of the second illumination control circuit 700.
  • the terminal 730 so that when the reset voltage Vint is applied to the gate of the driving transistor through the reset circuit 400, the potential of the source of the driving transistor is discharged to Vint-Vth, so that the gate and the source of the driving transistor can be made at this stage.
  • the voltage V GS satisfies:
  • the illumination control signal switching circuit 800 can apply the second illumination control signal to the control terminal 530 of the first illumination control circuit 500 in response to the illumination control switching signal, and apply the first illumination control signal to the control of the second illumination control circuit 700.
  • the terminal 730 so that when the reset voltage Vint is applied to the gate of the driving transistor through the reset circuit 400, the first voltage VDD is applied to the source of the driving transistor, so that the voltage V GS of the gate and source of the driving transistor can be satisfied. :
  • the data signal DATA of the previous frame is black or white
  • the driving transistor starts from a fixed biased on state to enter, for example, a data writing and compensation phase, thereby improving the use of conventional pixels.
  • a short-term afterimage problem that may occur due to the hysteresis effect of the display device of the circuit.
  • the pixel circuit 10 provided by the embodiment of the present disclosure can solve the short-term afterimage problem not only by the fixed biased off state, but also by the fixed biased open state.
  • the pixel circuit 10 shown in FIG. 2 can be embodied as the pixel circuit structure shown in FIG.
  • the pixel circuit 10 includes first to seventh transistors T1, T2, T3, T4, T5, T6, and T7 and a capacitor C1 and a light-emitting element L1.
  • the first transistor T1 is used as a driving transistor, and the other second to seventh transistors are used as switching transistors.
  • the light-emitting element L1 may be various types of OLEDs, such as top emission, bottom emission, double-sided emission, etc., and may emit red, green, blue, or white light, etc., which is not limited by the embodiments of the present disclosure.
  • the driving circuit 100 can be implemented as the first transistor T1.
  • the gate of the first transistor T1 is connected to the first node N1 as the control terminal 130 of the driving circuit 100; the first electrode of the first transistor T1 is connected to the first node 110 of the driving circuit 100, and is connected to the second node N2;
  • the second pole of the transistor T1 is connected to the third node N3 as the second end 120 of the driving circuit 100.
  • the driving circuit 100 may also be a circuit composed of other components.
  • the driving circuit 100 may have two sets of driving transistors.
  • the two sets of driving transistors may be switched according to specific conditions.
  • the data write circuit 200 can be implemented as a second transistor T2.
  • the gate of the second transistor T2 serves as the control terminal 230 of the data write circuit 200, and is configured to be connected to the scan line (scan signal terminal Gate) to receive the scan signal, and the first pole of the second transistor T2 is used as the data write circuit 200.
  • the first end 210 is configured to be connected to the data line (data signal terminal Vdata) to receive the data signal, and the second pole of the second transistor T2 is connected to the second node 220 of the data writing circuit 200 and connected to the second node N2.
  • the data writing circuit 200 may also be a circuit composed of other components.
  • the data writing circuit 200 may have two sets of data writing circuits, for example, the two sets of data writing circuits. You can switch according to the specific situation.
  • the compensation circuit 300 can be implemented as a third transistor T3 and a capacitor C1.
  • the gate of the third transistor T3 is configured to be connected to the scan line (scan signal terminal Gate) to receive the scan signal, and the first electrode of the third transistor T3 is connected to the control terminal 130 (first node N1) of the drive circuit 100, and the third The second pole of the transistor is connected to the second terminal 120 (third node N3) of the driving circuit 100; the first pole of the capacitor C1 is connected to the control terminal 130 of the driving circuit 100, and the second pole of the capacitor C1 is configured to be the first voltage Terminal VDD connection.
  • the compensation circuit 300 may also be a circuit composed of other components.
  • the compensation circuit 300 may have two sets of compensation circuits.
  • the two sets of compensation circuits may be switched according to specific conditions.
  • the first end 610 (here, the anode) of the light emitting element L1 and the fourth node N4 are connected to receive a driving current from the second end 120 of the driving circuit 100, and the second end 620 (here, the cathode) of the light emitting element L1 is configured to be
  • the second voltage terminal VSS is connected to receive the second voltage.
  • the second voltage terminal can be grounded, that is, VSS can be 0V.
  • the reset circuit 400 can be implemented as a fourth transistor T4 and a fifth transistor T5.
  • the gate of the fourth transistor T4 is configured to be connected to the reset control line (reset control terminal Rst) to receive the reset signal, and the first electrode of the fourth transistor T4 is connected to the control terminal 130 (first node N1) of the driving circuit 100,
  • the second pole of the four transistor T4 is configured to be connected to the reset voltage terminal Vint to receive the reset voltage;
  • the gate of the fifth transistor T5 is configured to be connected to the reset control line to receive the reset signal, the first pole of the fifth transistor T5 and the light emitting element
  • the first terminal 610 of L1 is coupled, and the second electrode of the fifth transistor T5 is configured to be coupled to the reset voltage terminal Vint to receive a reset voltage.
  • the reset circuit 400 may also be a circuit composed of other components.
  • the reset circuit 400 may have two sets of reset circuits.
  • the two sets of reset circuits may be switched according to specific conditions.
  • the first lighting control circuit 500 can be implemented as a sixth transistor T6.
  • the gate of the sixth transistor T6 is used as the control terminal 530 of the first illumination control circuit 500, and is configured to be connected to the first illumination control terminal Em1 to receive the first illumination control signal, and the first pole of the sixth transistor T6 is used as the first illumination control.
  • the first end of the circuit 500 is configured to be coupled to the first voltage terminal VDD to receive the first voltage, the second pole of the sixth transistor T6 as the second end of the first lighting control circuit 500, and the first end 110 of the driving circuit (second node N2) is connected.
  • the first illumination control circuit 500 may also be a circuit composed of other components.
  • the first illumination control circuit 500 may have two sets of first illumination control circuits, for example, the two groups. A lighting control circuit can be switched according to specific conditions.
  • the second light emission control circuit 700 can be implemented as a seventh transistor T7.
  • the gate of the seventh transistor T7 serves as the control terminal 730 of the second illumination control circuit 700, and is connected to the second illumination control line second illumination control terminal Em2 to receive the second illumination control signal, and the first pole of the seventh transistor T7 is used as the first
  • the second end 720 of the second illumination control circuit 700 is coupled to the first end 610 (fourth node N4) of the light emitting element L1, and the second end of the seventh transistor T7 serves as the first end 710 of the second illumination control circuit 700, and The second end 120 (third node N3) of the drive circuit 100 is connected.
  • the second illumination control circuit 700 may also be a circuit composed of other components.
  • the second illumination control circuit 700 may have two sets of second illumination control circuits, for example, the two groups. The two illumination control circuits can be switched according to specific conditions.
  • the first node N1, the second node N2, the third node N3, and the fourth node N4 do not represent actual components, but represent convergence points of related electrical connections in the circuit diagram.
  • FIG. 5 is a schematic diagram of another pixel circuit according to an embodiment of the present disclosure.
  • the pixel circuit shown in FIG. 3 can be embodied as the pixel circuit structure shown in FIG. 5.
  • the pixel circuit shown in FIG. 5 is substantially the same as the pixel circuit shown in FIG. 4, except that the pixel circuit 10 shown in FIG. 5 further includes an illumination control signal switching circuit 800, and the illumination control signal switching circuit 800 is implemented as the eighth to the Eleven transistors T8, T9, T10, T11.
  • the light emission control signal switching circuit 800 can be implemented as the eighth to eleventh transistors T8, T9, T10, T11.
  • the gate of the eighth transistor T8 receives the first illumination control switching signal CK1, the first pole of the eighth transistor T8 is connected to the first illumination control signal terminal Em1, the second pole of the eighth transistor T8 and the first illumination control circuit 500
  • the control terminal 530 is connected.
  • the gate of the ninth transistor T9 receives the first illuminating control switching signal CK1, the first pole of the ninth transistor T9 is connected to the second illuminating control signal terminal Em2, the second pole of the ninth transistor T9 and the second illuminating control circuit 700
  • the control terminal 730 is connected; the gate of the tenth transistor T10 receives the second illumination control switching signal CK2, the first pole of the tenth transistor T10 is connected to the second illumination control signal terminal Em2, and the second pole of the tenth transistor T10 and the first
  • the control terminal 530 of the illumination control circuit 500 is connected; the gate of the eleventh transistor T11 receives the second illumination control switching signal CK2, and the first pole of the eleventh transistor T11 is connected to the first illumination control signal terminal Em1, the eleventh transistor
  • the second pole of T11 is coupled to the control terminal 730 of the second lighting control circuit 700.
  • the illumination control signal switching circuit 800 may also be a circuit composed of other components.
  • the illumination control signal switching circuit 800 may have two sets of illumination control signal switching circuits, for example, the two sets of illumination.
  • the control signal switching circuit can be switched according to the specific situation.
  • the symbol CK1 may represent both the first illumination control switching signal end and the level of the first illumination control switching signal.
  • the symbol CK2 may represent the second.
  • the illumination control switching signal terminal can in turn represent the level of the second illumination control switching signal.
  • each transistor is a P-type transistor as an example, but the embodiment of the present disclosure is not limited thereto.
  • the P-type transistor is turned on in response to the low-level signal and turned off in response to the high-level signal, and the following embodiments are the same as those described herein, and will not be described again.
  • the display process of each frame image includes four stages, namely, an initialization phase 1, a data writing and compensation phase 2, a pre-lighting phase 3, and an illumination phase 4, which are shown in each phase. Timing waveform of each signal.
  • FIG. 7A to FIG. 7D are respectively schematic diagrams of the pixel circuit shown in FIG. 5 in the image display process of the Nth frame
  • FIGS. 8A to 8D are respectively the pixel circuit shown in FIG. Schematic diagram of the 1-frame image display process.
  • FIG. 7A is a schematic diagram of the pixel circuit shown in FIG. 5 in the initialization phase 1 during the image display of the Nth frame
  • FIG. 7B is the data writing and compensation in the image display process of the Nth frame in the pixel circuit shown in FIG.
  • FIG. 7C is a schematic diagram of the pixel circuit shown in FIG. 5 in the pre-lighting phase 3 during the image display of the Nth frame
  • FIG. 7D is the image display of the pixel circuit shown in FIG.
  • Schematic diagram of the illumination phase 4 during the process For example, the falling edge of the second lighting control signal may also coincide with the falling edge of the first lighting control signal, thereby entering the lighting phase 4 directly from the data writing and compensation phase 2.
  • FIG. 8A is a schematic diagram of the pixel circuit shown in FIG. 5 in the initialization phase 1 during the N+1th frame image display process
  • FIG. 8B is the data in the pixel circuit shown in FIG. 5 in the N+1 frame image display process
  • FIG. 8C is a schematic diagram of the pixel circuit shown in FIG. 5 in the pre-lighting phase 3 during the N+1th frame image display process
  • FIG. 8D is the pixel circuit shown in FIG.
  • the transistors identified by broken lines in FIGS. 7A to 8D are each shown to be in an off state in the corresponding phase, and the dotted line with arrows in FIGS. 7A to 8D indicates the current direction of the pixel circuit in the corresponding phase.
  • the transistors shown in FIGS. 7A to 8B are all described by taking a P-type transistor as an example, that is, the gates of the respective transistors are turned on when they are connected to a low level, and are turned off when they are connected to a high level.
  • the first illumination control switching signal (provided by the first illumination control switching signal terminal CK1) is input to turn on the illumination control signal switching circuit, and the first illumination control signal is applied to the first illumination control circuit 500.
  • the control terminal 530 applies a second lighting control signal to the control terminal 730 of the second lighting control circuit 700.
  • the eighth transistor T8 and the ninth transistor T9 are turned on by the low level of the first light emission control switching signal CK1; and the tenth transistor T10 and the eleventh transistor T11 are turned off by the high level of the second light emission control switching signal CK2.
  • a light-emitting control signal switching path is formed (as shown by a dotted line with an arrow in the light-emitting control signal switching circuit portion in FIGS. 7A to 7D), and the first transistor T8 can be turned on, as shown in FIG. 7A to FIG.
  • the light emission control signal is applied to the gate of the sixth transistor T6, and since the ninth transistor T9 is turned on, the second light emission control signal can be applied to the gate of the seventh transistor T7.
  • the reset signal and the second light emission control signal are input to turn on the reset circuit 400 and the second light emission control circuit 700, and the reset voltage is applied to the control terminal 130 and the second terminal 120 of the driving circuit 100 and the light emitting element 600 One end 610.
  • the fourth transistor T4 and the fifth transistor T5 are turned on by the low level of the reset signal, and the seventh transistor T7 is turned on by the low level of the second light-emission control signal;
  • the second transistor T2 and the third transistor T3 are turned off by the high level of the scan signal, and the sixth transistor T6 is turned off by the high level of the first light emission control signal.
  • a reset path is formed (shown by a broken line with an arrow in FIG. 7A), and since the fourth transistor T4 is turned on, the reset voltage Vint can be applied to the gate of the first transistor T1. Due to the conduction of the fifth transistor T5 and the seventh transistor T7, the reset voltage Vint can be applied to the second electrode of the first transistor T1 and the light-emitting element L1, thereby resetting the first node N1 and the light-emitting element L1. Therefore, after the initialization phase 1, the potential of the first node N1 is the reset voltage Vint (a low level signal, for example, may be grounded or other low level signal).
  • the sixth transistor T6 is turned off, and according to the characteristics of the first transistor T1 itself, the potential of the source of the first transistor T1 is discharged to Vint-Vth. Therefore, at this stage, the voltage V GS of the gate (ie, the first node N1) and the source (ie, the second node N2) of the first transistor T1 can be made to satisfy:
  • the potential of the first node N1 is the reset voltage Vint, and the potential of the second node N2 is Vint-Vth.
  • the capacitor C1 is reset, discharging the voltage stored in the capacitor C1, so that the data signal in the subsequent stage can be stored in the capacitor C1 more quickly and more reliably; at the same time, the third node N3 and the light
  • the element L1 is also reset, so that the light-emitting element L1 can be displayed in a black state before the light-emitting phase 4, and the display effect of the contrast of the display device using the above-described pixel circuit can be improved.
  • the scan signal and the data signal are input to turn on the data write circuit 200, the drive circuit 100, and the compensation circuit 300.
  • the data write circuit 200 writes the data signal to the drive circuit 100, and the compensation circuit 300 drives the drive. Circuit 100 performs compensation.
  • the second transistor T2 and the third transistor T3 are turned on by the low level of the scan signal; meanwhile, the fourth transistor T4 and the fifth transistor T5 are reset.
  • the high level of the signal is turned off, the sixth transistor T6 is turned off by the high level of the first light emission control signal, and the seventh transistor T7 is turned off by the high level of the second light emission control signal.
  • a data writing and compensation path is formed (shown by a broken line with an arrow in FIG. 7B), and the data signal passes through the second transistor T2, the first transistor T1, and the After the three transistors T3, the first node N1 is charged (i.e., the capacitor C1 is charged), that is, the potential of the first node N1 becomes large. It is easy to understand that the potential of the second node N2 is maintained at Vdata, and according to the self-characteristic of the first transistor T1, when the potential of the first node N1 is increased to Vdata+Vth, the first transistor T1 is turned off, and the charging process ends.
  • Vdata represents the voltage value of the data signal
  • Vth represents the threshold voltage of the first transistor. Since the first transistor T1 is a P-type transistor as an example in the present embodiment, the threshold voltage Vth here is used. Can be a negative value.
  • the potentials of the first node N1 and the third node N3 are both Vdata+Vth, that is, the voltage information with the data signal and the threshold voltage Vth is stored in the capacitor C1 for use in Subsequent to the illumination phase, gray scale display data is provided and the threshold voltage of the first transistor T1 itself is compensated.
  • a first illumination control signal is input to turn on the first illumination control circuit 500 and the drive circuit 100, and the first illumination control circuit 500 applies a first voltage to the first terminal 110 of the drive circuit 100.
  • the sixth transistor T6 is turned on by the low level of the first light emission control signal; meanwhile, the second transistor T2 and the third transistor T3 are scanned as the high level of the signal.
  • the fourth transistor T4 and the fifth transistor T5 are turned off by the high level of the reset signal, and the seventh transistor T7 is turned off by the high level of the second light emission control signal.
  • a pre-emission path is formed (shown by a broken line with an arrow in Fig. 7C).
  • the first voltage is charged to the second node N2 via the sixth transistor T6, and the potential of the second node N2 is changed from Vdata to the first voltage VDD. Since the seventh transistor T7 is turned off at this stage, the light-emitting element L1 is the next stage. The light is ready.
  • the first lighting control signal and the second lighting control signal are input to turn on the first lighting control circuit 500, the second lighting control circuit 700, and the driving circuit 100, and the second lighting control circuit 700 applies a driving current to the light emitting element.
  • L1 is made to emit light.
  • the sixth transistor T6 is turned on by the low level of the first illuminating control signal, and the seventh transistor T7 is turned on by the low level of the second illuminating control signal;
  • the second transistor T2 and the third transistor T3 are turned off by the high level of the scan signal, and the fourth transistor T4 and the fifth transistor T5 are turned off by the high level of the reset signal.
  • the potential Vdata+Vth of the first node N1 and the potential of the second node N2 are VDD, so the first transistor T1 also remains turned on at this stage.
  • a driving light-emitting path is formed (as indicated by a broken line with an arrow in Fig. 7D).
  • the light emitting element L1 can emit light under the action of a driving current flowing through the first transistor T1.
  • the value of the drive current I L1 flowing through the light-emitting element L1 can be obtained according to the following formula:
  • I L1 K(V GS -Vth) 2
  • Vth represents the threshold voltage of the first transistor T1
  • V GS represents the voltage between the gate and the source of the first transistor T1 (here, the first pole)
  • K is a constant associated with the driving transistor itself. Value. It can be seen from the above formula of I L1 that the driving current I L1 flowing through the light-emitting element L1 is no longer related to the threshold voltage Vth of the first transistor T1, thereby compensating the pixel circuit and solving the driving transistor (
  • the first transistor T1) has a problem of threshold voltage drift due to process process and long-time operation, and its influence on the driving current I L1 is eliminated, so that the display effect of the display device using the same can be improved.
  • the second illumination control switching signal (the second illumination control switching signal terminal CK2) is input to turn on the illumination control signal switching circuit, and the second illumination is performed.
  • the control signal is applied to the control terminal 530 of the first illumination control circuit 500, and the first illumination control signal is applied to the control terminal 730 of the second illumination control circuit 700.
  • the tenth transistor T10 and the eleventh transistor T11 are turned on by the low level of the second light emission control switching signal CK2;
  • the eighth transistor T8 and the ninth transistor T9 are turned off by the high level of the first light emission control switching signal CK1.
  • a light-emitting control signal switching path is formed (as shown by a broken line with an arrow in the portion of the light-emitting control signal switching circuit in FIGS. 8A to 8D), and the second transistor T10 can be turned on.
  • the light emission control signal is applied to the gate of the sixth transistor T6, and since the eleventh transistor T11 is turned on, the first light emission control signal can be applied to the gate of the seventh transistor T7.
  • the working principle of the image display of the N+1th frame is basically the same as that of the image display of the Nth frame, the difference is that in the initialization phase 1 in the image display process of the (N+1)th frame, the sixth transistor T6 is controlled by the second light emission control signal.
  • the low level is turned on, and the seventh transistor T7 is turned off by the high level of the first light emission control signal, so that at this stage, since the sixth transistor T6 is turned on, the potential of the source of the first transistor T1 is charged to the first The voltage VDD, such that the voltage V GS of the gate (ie, the first node N1) and the source (ie, the second node N2) of the first transistor T1 satisfies:
  • the sixth transistor T6 is turned off due to the high level of the second light emission control signal, and the seventh transistor T7 is due to the first light emission control signal.
  • the low level is turned on, so that the light of the next stage of the light-emitting element L1 is prepared.
  • the operation principle of the pixel circuit 10 shown in FIG. 4 is basically the same as that of the pixel circuit shown in FIG. 5 shown in FIGS. 7A to 7D, and the difference is that the pixel circuit 10 shown in FIG. 4 does not include the light emission control signal.
  • the control circuit 530 of the first illumination control circuit 500 is directly connected to the first illumination control signal terminal Em1
  • the control terminal 730 of the second illumination control circuit 700 is directly connected to the second illumination control signal terminal Em2.
  • the case where the N frame is switched to the N+1th frame.
  • the transistors used in the embodiments of the present disclosure may each be a thin film transistor or a field effect transistor or other switching device having the same characteristics.
  • a thin film transistor is taken as an example for description.
  • the source and drain of the transistor used here may be structurally symmetrical, so that the source and the drain may be structurally indistinguishable.
  • the embodiment of the present disclosure in order to distinguish the two poles of the transistor except the gate, one of the first poles and the other pole are directly described.
  • the transistors in the pixel circuit 10 shown in FIG. 5 are all described by taking a P-type transistor as an example.
  • the first electrode may be a drain and the second electrode may be a source.
  • the cathode of the light-emitting element L1 in the pixel circuit 10 is connected to the second voltage terminal VSS to receive the second voltage.
  • the cathodes of the light-emitting elements L1 can be electrically connected to the same voltage terminal, that is, by a common cathode connection.
  • Embodiments of the present disclosure include, but are not limited to, the configuration in FIG. 5.
  • only one illumination control switching signal line may be included in the illumination control signal switching circuit.
  • the transistors in the pixel circuit 10 can be mixed with a P-type transistor and an N-type transistor, as long as the port polarity of the selected type of transistor is simultaneously in accordance with an embodiment of the present disclosure.
  • the port polarity of the corresponding transistor can be connected accordingly.
  • the first to ninth transistors T1-T9 employ P-type transistors
  • the tenth transistor T10 and the eleventh transistor T11 employ N-type transistors.
  • the eighth transistor to the eleventh transistor T8-T11 are simultaneously connected to the first light emission control switching signal terminal CK1.
  • IGZO Indium Gallium Zinc Oxide
  • LTPS Low Temperature Poly Silicon
  • amorphous silicon for example, hydrogenated amorphous silicon
  • the pixel circuit 10 can be implemented by connecting an inverter 900 between the gates of the tenth transistor T10 and the eleventh transistor T11 and the first light-emission control switching signal terminal CK1.
  • the inverter is implemented as an operational amplifier A, a first resistor R1, and a second resistor R2.
  • the inverter 900 is not limited to the above structure, and the embodiment of the present disclosure does not limit this.
  • the inverter 900 can be a TTL inverter or a CMOS inverter.
  • An embodiment of the present disclosure further provides a display panel 11.
  • the display panel 11 is located in the display device 1.
  • the display device 1 includes a gate driver 12, a data driver 14, and a timing controller 13.
  • the display panel 11 includes a pixel unit P defined in accordance with a plurality of scan lines GL and a plurality of data lines DL; a gate driver 12 for driving a plurality of scan lines GL; and a data driver 14 for driving a plurality of data lines DL
  • a timing controller 13 for processing image data RGB input from outside the display device 1, supplying image data RGB processed to the data driver 14, and outputting scan control signals GCS and data control signals to the gate driver 12 and the data driver 14.
  • the DCS controls the gate driver 12 and the data driver 14.
  • the display panel 11 includes a plurality of pixel units P arranged in an array, each of which includes any of the pixel circuits 10 and the light-emitting elements (not shown) provided in the above embodiments.
  • the pixel circuit 10 shown in FIG. 5 is included.
  • a pixel circuit as shown in Fig. 4 may also be included.
  • the first end of the light emitting element is configured to receive a drive current from the second end 120 of the drive circuit 100 in the pixel circuit 10, and the second end of the light emitting element is configured to be coupled to the second voltage terminal VSS.
  • the display panel 11 further includes a plurality of scanning lines GL and a plurality of data lines DL.
  • the pixel unit P is disposed at an intersection area of the scanning line GL and the data line DL.
  • each pixel unit P is connected to six scanning lines GL (providing a scanning signal, a reset control signal, a first lighting control signal, a second lighting control signal, a first lighting control switching signal, and a second, respectively).
  • An illumination control switching signal a data line DL, a first voltage line for providing a first voltage, a second voltage line for providing a second voltage, and a reset voltage line for providing a reset voltage.
  • the first voltage line or the second voltage line may be replaced with a corresponding plate-like common electrode (eg, a common anode or a common cathode).
  • a corresponding plate-like common electrode eg, a common anode or a common cathode.
  • the plurality of pixel units P are arranged in a plurality of rows, and the control terminal 230 of the data writing circuit 200 of the pixel circuit of the pixel circuit P of the nth (n is an integer of 2 or more) is connected to the control terminal of the compensation circuit 300.
  • One scanning line GL, and the control terminal of the reset circuit 400 of the pixel circuit of the pixel unit P of the nth row is connected to the other scanning line GL.
  • the other scanning line GL is also connected to the control terminal 230 of the data writing circuit 200 of the pixel circuit of the pixel unit P of the n-1th row and the control terminal of the compensation circuit 300.
  • the data line DL of each column is coupled to the first terminal 210 of the data write circuit 200 in the column of pixel circuits 10 to provide a data signal.
  • the display panel 11 may further include a plurality of reset control lines.
  • a plurality of pixel units P are arranged in a plurality of rows, and a control terminal of the data writing circuit 200 of the pixel circuit 10 of one row of pixel units P and a control terminal of the compensation circuit 300 are connected to the same scanning line, and pixels of one row of pixel units P
  • the control terminal of the reset circuit 400 of the circuit 10 is connected to the same reset control line (reset control terminal Rst).
  • the display panel 11 may further include a plurality of light emission control lines.
  • a plurality of pixel units are arranged in a plurality of rows, and a m-th (m is an integer equal to or greater than 1 integer) pixel control unit of the pixel unit P of the pixel control unit 530 is connected to the same light-emitting control line, and m
  • the control terminal 730 of the second illumination control circuit 700 of the pixel circuit of the row pixel unit P is connected to another illumination control line.
  • the other light emission control line is also connected to the control terminal of the first light emission control circuit 500 of the pixel circuit of the pixel unit P of the m+1th row.
  • the display panel 11 may further include a plurality of light emission control switching signal lines.
  • a plurality of pixel units are arranged in a plurality of rows, and a control terminal of the light emission control signal switching circuit of the pixel circuit of the m-th row pixel unit is connected to the same light emission control switching signal line.
  • the control terminal of the light emission control signal switching circuit of the pixel circuit of the mth row pixel unit is connected to two light emission control switching signal lines. For example, a rising edge of the light emission control switching signal provided by one of the two light emission control switching signal lines is a falling edge of the light emission control switching signal provided by the other light emission control switching signal line.
  • the gate driver 12 supplies a plurality of strobe signals to the plurality of scan lines GL in accordance with a plurality of scan control signals GCS derived from the timing controller 13.
  • the plurality of strobe signals include a scan signal, a first illuminating control signal, a second illuminating control signal, and a reset signal. These signals are supplied to each of the pixel units P through a plurality of scanning lines GL.
  • the data driver 14 converts the digital image data RGB input from the timing controller 13 into a data signal in accordance with a plurality of data control signals DCS derived from the timing controller 13 using the reference gamma voltage.
  • the data driver 14 supplies the converted data signals to the plurality of data lines DL.
  • the timing controller 13 processes the externally input image data RGB to match the size and resolution of the display panel 11, and then supplies the processed image data to the data driver 14.
  • the timing controller 13 generates a plurality of scan control signals GCS and a plurality of data control signals DCS using a synchronization signal (for example, a dot clock DCLK, a data enable signal DE, a horizontal synchronization signal Hsync, and a vertical synchronization signal Vsync) input from the outside of the display device.
  • the timing controller 13 supplies the generated scan control signal GCS and data control signal DCS to the gate driver 12 and the data driver 14, respectively, for control of the gate driver 12 and the data driver 14.
  • the data driver 14 may be connected to the plurality of data lines DL to provide the data signal Vdata; and may also be connected to the plurality of first voltage lines, the plurality of second voltage lines, and the plurality of reset voltage lines to respectively provide the first voltage , the second voltage and the reset voltage.
  • the gate driver 12 and the data driver 14 can be implemented as a semiconductor chip.
  • the display device 1 may also include other components, such as signal decoding circuits, voltage conversion circuits, etc., which may be, for example, conventional conventional components, and will not be described in detail herein.
  • the display device 1 provided in this embodiment may be any product or component having a display function such as an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • Embodiments of the present disclosure also provide a driving method that can be used to drive the pixel circuit 10 provided by an embodiment of the present disclosure.
  • the driving method includes an initialization phase, a data writing and compensation phase, and an illumination phase.
  • a reset signal is input to turn on the reset circuit 400, and a reset voltage is applied to the control terminal 130 of the driving circuit 100 and the first end 610 of the light emitting element 600.
  • the scan signal and the data signal are input to turn on the data write circuit 200, the drive circuit 100, and the compensation circuit 300.
  • the data write circuit 200 writes the data signal to the drive circuit 100, and the compensation circuit 300 pairs the drive circuit. 100 for compensation.
  • a first light emission control signal is input to turn on the first light emission control circuit 500 and the drive circuit 100, and the first light emission control circuit 500 applies a drive current to the light emitting element 600 to cause it to emit light.
  • the pixel circuit 10 further includes a second lighting control circuit 700, the driving method further including a pre-lighting phase.
  • the reset signal and the second lighting control signal are input to turn on the reset circuit 400 and the second lighting control circuit 700, and the reset voltage is applied to the control terminal 130 and the second terminal 120 of the driving circuit 100 and the light emitting element 600 One end 610.
  • the scan signal and the data signal are input to turn on the data write circuit 200, the drive circuit 100, and the compensation circuit 300.
  • the data write circuit 200 writes the data signal to the drive circuit 100, and the compensation circuit 300 pairs the drive circuit. 100 for compensation.
  • a first lighting control signal is input to turn on the first lighting control circuit 500 and the driving circuit 100, and the first lighting control circuit 500 applies a first voltage to the first end 110 of the driving circuit 100.
  • the first light emission control signal and the second light emission control signal are input to turn on the first light emission control circuit 500, the second light emission control circuit 700, and the drive circuit 100, and the second light emission control circuit 700 applies a drive current to the light emitting element 600. To make it shine.
  • the pixel circuit 10 further includes an illumination control signal switching circuit 800, the driving method including the following steps.
  • the reset signal, the second illumination control signal, and the illumination control switching signal are input to turn on the reset circuit 400 and the illumination control signal switching circuit 800 to apply the second illumination control signal to the control terminal 530 of the first illumination control circuit 500.
  • the control terminal 730 of the second illumination control circuit 700, and the reset voltage is applied to the control terminal 130 of the driving circuit 100 and the first end 610 of the light emitting element 600;
  • the scan signal and the data signal are input to turn on the data write circuit 200, the drive circuit 100, and the compensation circuit 300.
  • the data write circuit 200 writes the data signal to the drive circuit 100, and the compensation circuit 300 pairs the drive circuit. 100 for compensation;
  • the illumination control switching signal and the first illumination control signal are input to apply the first illumination control signal to the control terminal 530 of the first illumination control circuit 500 or the control terminal 730 of the second illumination control circuit 700.
  • the first lighting control signal is applied to the control terminal 530 of the first lighting control circuit 500, the first lighting control circuit 500 applies the first voltage VDD to the first end 510 of the driving circuit 100;
  • the light emission control switching signal, the first light emission control signal, and the second light emission control signal are input to turn on the first light emission control circuit 500, the second light emission control circuit 700, and the driving circuit 100, and the second light emission control circuit 700 drives the current It is applied to the light emitting element 600 to cause it to emit light.
  • the driving method provided by the embodiment can improve the short-term afterimage problem that may occur due to the hysteresis effect, and compensate the threshold voltage of the driving circuit, for example, can avoid display unevenness, thereby improving the display effect of the display device using the pixel circuit.

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Abstract

一种像素电路及其驱动方法、显示面板。该像素电路(10)包括驱动电路(100)、数据写入电路(200)、补偿电路(300)、复位电路(400)和第一发光控制电路(500)。驱动电路(100)包括控制端(130)、第一端(110)和第二端(120)，且配置为控制驱动发光元件(600)发光的驱动电流；数据写入电路(200)配置为响应于扫描信号将数据信号写入驱动电路(100)的第一端(110)；补偿电路(300)配置为响应于扫描信号以及写入的数据信号对驱动电路(100)进行补偿；复位电路(400)配置为响应于复位信号将复位电压施加至驱动电路(100)的控制端(130)以及发光元件(600)的第一端(610)；第一发光控制电路(500)配置为响应于第一发光控制信号将第一电压端的第一电压施加至驱动电路(100)的第一端(110)。该像素电路可以改善短期残像问题并对驱动电路的阈值电压进行补偿。

Description

像素电路及其驱动方法、显示面板
本申请要求于2018年1月10日递交的中国专利申请第201810023293.3号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开实施例涉及一种像素电路及其驱动方法、显示面板。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)显示装置由于具有视角宽、对比度高、响应速度快以及相比于无机发光显示器件更高的发光亮度、更低的驱动电压等优势而逐渐受到人们的广泛关注。由于上述特点，有机发光二极管(OLED)可以适用于手机、显示器、笔记本电脑、数码相机、仪器仪表等具有显示功能的装置。
OLED显示装置中的像素电路一般采用矩阵驱动方式，根据每个像素单元中是否引入开关元器件分为有源矩阵(Active Matrix，AM)驱动和无源矩阵(Passive Matrix，PM)驱动。PMOLED虽然工艺简单、成本较低，但因存在交叉串扰、高功耗、低寿命等缺点，不能满足高分辨率大尺寸显示的需求。相比之下，AMOLED在每一个像素的像素电路中都集成了一组薄膜晶体管和存储电容，通过对薄膜晶体管和存储电容的驱动控制，实现对流过OLED的电流的控制，从而使OLED根据需要发光。相比PMOLED，AMOLED所需驱动电流小、功耗低、寿命更长，可以满足高分辨率多灰度的大尺寸显示需求。同时，AMOLED在可视角度、色彩的还原、功耗以及响应时间等方面具有明显的优势，适用于高信息含量、高分辨率的显示装置。
发明内容
本公开至少一实施例提供一种像素电路，包括驱动电路、数据写入电路、 补偿电路、复位电路和第一发光控制电路。所述驱动电路包括控制端、第一端和第二端，且配置为控制驱动发光元件发光的驱动电流；所述数据写入电路与所述驱动电路的第一端连接，且配置为响应于扫描信号将数据信号写入所述驱动电路的第一端；所述补偿电路与所述驱动电路的控制端以及第二端连接且与第一电压端连接，配置为响应于所述扫描信号以及写入的所述数据信号对所述驱动电路进行补偿；所述复位电路与所述驱动电路的控制端以及第二端连接且与所述发光元件连接，且配置为响应于复位信号将复位电压施加至所述驱动电路的控制端以及所述发光元件的第一端；所述第一发光控制电路与所述驱动电路的第一端连接，所述第一发光控制电路配置为响应于第一发光控制信号将所述第一电压端的第一电压施加至所述驱动电路的第一端。
例如，本公开一实施例提供的像素电路还包括第二发光控制电路。所述第二发光控制电路的第一端和第二端分别和所述发光元件的第一端以及所述驱动电路的第二端连接，且配置为响应于第二发光控制信号以使得所述驱动电流可被施加至所述发光元件。
例如，本公开一实施例提供的像素电路还包括发光控制信号切换电路。所述发光控制信号切换电路与所述第一发光控制电路的控制端和所述第二发光控制电路的控制端电连接，且配置为响应于发光控制切换信号将所述第一发光控制信号和所述第二发光控制信号交替施加至所述第一发光控制电路的控制端和所述第二发光控制电路的控制端。
例如，在本公开一实施例提供的像素电路中，所述驱动电路包括第一晶体管。所述第一晶体管的栅极作为所述驱动电路的控制端，所述第一晶体管的第一极作为所述驱动电路的第一端，所述第一晶体管的第二极作为所述驱动电路的第二端。
例如，在本公开一实施例提供的像素电路中，所述数据写入电路包括第二晶体管。所述第二晶体管的栅极作为所述数据写入电路的控制端配置为和扫描线连接以接收所述扫描信号，所述第二晶体管的第一极作为所述数据写入电路的第一端配置为和数据线连接以接收所述数据信号，所述第二晶体管的第二极作为所述数据写入电路的第二端和所述驱动电路的第一端连接。
例如，在本公开一实施例提供的像素电路中，所述补偿电路包括第三晶体管和电容。所述第三晶体管的栅极和扫描线连接以接收所述扫描信号，所述第三晶体管的第一极和所述驱动电路的控制端连接，所述第三晶体管的第二极和所述驱动电路的第二端连接；所述电容的第一极和所述驱动电路的控制端连接，所述电容的第二极和所述第一电压端连接以接收所述第一电压。
例如，在本公开一实施例提供的像素电路中，所述复位电路包括第四晶体管和第五晶体管。所述第四晶体管的栅极和复位控制线连接以接收所述复位信号，所述第四晶体管的第一极和所述驱动电路的控制端连接，所述第四晶体管的第二极和复位电压端连接以接收所述复位电压；所述第五晶体管的栅极和所述复位控制线连接以接收所述复位信号，所述第五晶体管的第一极和所述发光元件的第一端连接，所述第五晶体管的第二极配置为和所述复位电压端连接以接收所述复位电压。
例如，在本公开一实施例提供的像素电路中，所述第一发光控制电路包括第六晶体管。所述第六晶体管的栅极作为所述第一发光控制电路的控制端配置为和第一发光控制线连接以接收所述第一发光控制信号，所述第六晶体管的第一极作为所述第一发光控制电路的第一端配置为和所述第一电压端连接以接收所述第一电压，所述第六晶体管的第二极作为所述第一发光控制电路的第二端和所述驱动电路的第一端连接。
例如，在本公开一实施例提供的像素电路中，所述第二发光控制电路包括第七晶体管。所述第七晶体管的栅极作为所述第二发光控制电路的控制端和第二发光控制线连接以接收所述第二发光控制信号，所述第七晶体管的第一极作为所述第二发光控制电路的第二端和所述驱动电路的第二端连接，所述第七晶体管的第二极作为所述第二发光控制电路的第一端和所述发光元件的第一端连接。
例如，在本公开一实施例提供的像素电路中，所述第一发光控制信号和所述第二发光控制信号至少部分时间段内同时为开启信号。
例如，在本公开一实施例提供的像素电路中，所述发光控制信号切换电路包括第八晶体管、第九晶体管、第十晶体管和第十一晶体管；所述第八晶体管的栅极配置为接收所述发光控制切换信号，所述第八晶体管的第一极和 第一发光控制线连接以接收所述第一发光控制信号，所述第八晶体管的第二极和所述第一发光控制电路的控制端连接；所述第九晶体管的栅极配置为接收所述发光控制切换信号，所述第九晶体管的第一极和第二发光控制线连接以接收所述第二发光控制信号，所述第九晶体管的第二极和所述第二发光控制电路的控制端连接；所述第十晶体管的栅极配置为接收所述发光控制切换信号，所述第十晶体管的第一极和所述第二发光控制线连接，所述第十晶体管的第二极和所述第一发光控制电路的控制端连接；所述第十一晶体管的栅极配置为接收所述发光控制切换信号，所述第十一晶体管的第一极和所述第一发光控制线连接，所述第十一晶体管的第二极和所述第二发光控制电路的控制端连接。
本公开至少一实施例还提供一种显示面板，包括阵列布置的多个像素单元。所述多个像素单元每个包括本公开的实施例提供的像素电路以及发光元件。
例如，在本公开一实施例提供的显示面板中，所述像素电路还包括发光控制信号切换电路、所述第一发光控制电路和第二发光控制电路。所述发光控制信号切换电路与第一发光控制线、第二发光控制线、所述第一发光控制电路的控制端和所述第二发光控制电路的控制端电连接，配置为响应于发光控制切换信号将所述第一发光控制线提供的所述第一发光控制信号和所述第二发光控制线提供的第二发光控制信号交替施加至所述第一发光控制电路的控制端和所述第二发光控制电路的控制端；所述显示面板还包括多条发光控制切换信号线，所述多个像素单元排列为多行，第m行像素单元的像素电路的发光控制信号切换电路的控制端连接到同一条发光控制切换信号线，或者所述第m行像素单元的像素电路的发光控制信号切换电路的控制端连接到两条发光控制切换信号线，其中，所述两条发光控制切换信号线中的一条发光控制切换信号线提供的发光控制切换信号的上升沿是另一条发光控制切换信号线提供的发光控制切换信号的下降沿，其中m为大于等于1整数。
例如，在本公开一实施例提供的显示面板中，所述发光元件的第一端配置为从所述驱动电路的第二端接收所述驱动电流，所述发光元件的第二端配置为与第二电压端连接。
本公开至少一实施例还提供一种像素电路的驱动方法，包括：初始化阶段、数据写入及补偿阶段和发光阶段。在所述初始化阶段，输入所述复位信号以开启所述复位电路，将所述复位电压施加至所述驱动电路的控制端以及所述发光元件的第一端；在所述数据写入及补偿阶段，输入所述扫描信号和所述数据信号以开启所述数据写入电路、所述驱动电路和所述补偿电路，所述数据写入电路将所述数据信号写入所述驱动电路，所述补偿电路对所述驱动电路进行补偿；在所述发光阶段，输入所述第一发光控制信号以开启所述第一发光控制电路和所述驱动电路，所述第一发光控制电路将所述驱动电流施加至所述发光元件以使其发光。
本公开至少一实施例还提供一种像素电路的驱动方法，包括：初始化阶段、数据写入及补偿阶段、预发光阶段和发光阶段。在所述初始化阶段，输入所述复位信号和所述第二发光控制信号以开启所述复位电路和第二发光控制电路，将所述复位电压施加至所述驱动电路的控制端和第二端以及所述发光元件的第一端；在所述数据写入及补偿阶段，输入所述扫描信号和所述数据信号以开启所述数据写入电路、所述驱动电路和所述补偿电路，所述数据写入电路将所述数据信号写入所述驱动电路，所述补偿电路对所述驱动电路进行补偿；在所述预发光阶段，输入所述第一发光控制信号以开启所述第一发光控制电路和所述驱动电路，所述第一发光控制电路将所述第一电压施加至所述驱动电路的第一端；在所述发光阶段，输入所述第一发光控制信号和所述第二发光控制信号以开启所述第一发光控制电路、所述第二发光控制电路和所述驱动电路，所述第二发光控制电路将所述驱动电流施加至所述发光元件以使其发光。
本公开至少一实施例还提供一种像素电路的驱动方法，包括：初始化阶段、数据写入及补偿阶段、预发光阶段和发光阶段。在所述初始化阶段，输入所述复位信号、所述第二发光控制信号和所述发光控制切换信号以开启所述复位电路和所述发光控制信号切换电路，以将所述第二发光控制信号施加于所述第一发光控制电路的控制端或所述第二发光控制电路的控制端，并将所述复位电压施加至所述驱动电路的控制端以及所述发光元件的第一端；在所述数据写入及补偿阶段，输入所述扫描信号和所述数据信号以开启所述数 据写入电路、所述驱动电路和所述补偿电路，所述数据写入电路将所述数据信号写入所述驱动电路，所述补偿电路对所述驱动电路进行补偿；在所述预发光阶段，输入所述发光控制切换信号和所述第一发光控制信号以将所述第一发光控制信号施加至所述第一发光控制电路的控制端或所述第二发光控制电路的控制端，所述第一发光控制信号施加至所述第一发光控制电路的控制端时，所述第一发光控制电路将所述第一电压施加至所述驱动电路的第一端；在所述发光阶段，输入所述发光控制切换信号、所述第一发光控制信号和所述第二发光控制信号以开启所述第一发光控制电路、所述第二发光控制电路和所述驱动电路，所述第二发光控制电路将所述驱动电流施加至所述发光元件以使其发光。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1A为一种显示装置显示的图像一的示意图；
图1B为上述显示装置要显示的图像二的示意图；
图1C为上述显示装置实际显示的图像二的示意图；
图2为本公开一实施例提供的一种像素电路的示意框图；
图3为本公开一实施例提供的另一种像素电路的示意框图；
图4为图2中所示的像素电路的一种具体实现示例的电路图；
图5为图3中所示的像素电路的一种具体实现示例的电路图；
图6为本公开一实施例提供的驱动方法的时序图；
图7A至图7D分别为图5中所示的像素电路对应于图6中第N帧图像的显示过程中四个阶段的电路示意图；
图8A至图8D分别为图5中所示的像素电路对应于图6中第N+1帧图像的显示过程中四个阶段的电路示意图；
图9为本公开一实施例提供的一种像素电路的电路图；
图10为本公开一实施例提供的另一种像素电路的电路图；以及
图11为本公开一实施例提供的一种显示装置的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。以下所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其它实施例，都属于本公开保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
下面详细描述本公开的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，旨在用于解释本公开，而不能理解为对本公开的实施例的限制。
AMOLED显示装置中使用的基础像素电路通常为2T1C像素电路，即利用两个TFT(Thin-film transistor，薄膜晶体管)和一个存储电容Cs来实现驱动OLED发光的基本功能。
OLED显示装置通常包括多个按阵列排布的像素单元，每个像素单元例如可以包括上述像素电路。在OLED显示装置中，各个像素电路中的驱动晶体管的阈值电压由于制备工艺可能存在差异，而且由于例如温度变化的影响，驱动晶体管的阈值电压可能会产生漂移现象。因此，各个驱动晶体管的阈值电压的不同可能会导致显示不良(例如显示不均匀)，所以就需要对阈值电 压进行补偿。同时在处于关态时，由于泄露电流的存在，也可能会导致显示不良。因此，业界还在上述2T1C的基本像素电路的基础上提供了其他具有补偿功能的像素电路，补偿功能可以通过电压补偿、电流补偿或混合补偿来实现，具有补偿功能的像素电路例如可以为4T1C或4T2C等，这里不再详述。
由于显示装置的像素电路中的驱动晶体管的迟滞效应，当显示装置显示同一个图像一段时间后，在把前一个显示图像切换到下一个图像时，原先的前一个显示图像会部分残留而浮现在下一个图像中，一段时间后残像会消失，这种现象称为短期残像。迟滞效应主要是因为驱动晶体管中残留的可移动载流子造成阈值电压(Vth)偏移所导致的。在不同画面切换时其初始化阶段的V GS(驱动晶体管的栅极和源极之间的电压)可能不同，所以可能会造成驱动晶体管不同程度的阈值电压偏移，从而造成短期残像。
例如，图1A为一种显示装置显示的图像一的示意图，图1B为该显示装置要显示的图像二的示意图，图1C为该显示装置实际显示的图像二的示意图。在该显示装置显示图像一例如如图1A所示的黑白棋盘图像一段时间后，当显示装置显示的图像切换到新的图像二(例如如图1B所示的灰阶为48的图像)时，仍然会部分残留图1A所示图像一的棋盘图像，如图1C所示。
本公开至少一实施例提供一种像素电路。该像素电路包括驱动电路、数据写入电路、补偿电路、复位电路和第一发光控制电路。驱动电路包括控制端、第一端和第二端，且配置为控制驱动发光元件发光的驱动电流；数据写入电路与驱动电路的第一端连接，且配置为响应于扫描信号将数据信号写入驱动电路的第一端；补偿电路与驱动电路的控制端以及第二端连接且与第一电压端连接，配置为响应于扫描信号以及写入的数据信号对驱动电路进行补偿；复位电路与驱动电路的控制端以及发光元件连接，且配置为响应于复位信号将复位电压施加至驱动电路的控制端以及发光元件的第一端；第一发光控制电路与驱动电路的第一端连接，第一发光控制电路配置为响应于第一发光控制信号将第一电压端的第一电压施加至驱动电路的第一端。
本公开至少一实施例还提供对应于上述像素电路的驱动方法和显示面板。
本公开上述实施例提供的像素电路及其驱动方法、显示面板，一方面，可以使其中的驱动晶体管在初始化阶段处于V GS为固定偏置的截止状态(off-bias)或开启状态(on-bias)，从而可以改善由于迟滞效应可能产生的短期残像问题；另一方面，还可以对像素电路的驱动电路的阈值电压进行补偿，以避免显示装置显示不均匀的现象，从而可以改善采用该像素电路的显示装置的显示效果。
下面结合附图对本公开的实施例及其示例进行详细说明。
本公开实施例的一个示例提供一种像素电路10，该像素电路10例如用于驱动显示装置的子像素中的发光元件600发光。在本公开的至少一个实施例中，显示装置的显示面板例如通过玻璃衬底制备，具体结构与制备工艺可以采用本领域中的常规方法，这里不再详述，且本公开的实施例对此不作限制。
如图2所示，该像素电路10包括驱动电路100、数据写入电路200、补偿电路300、复位电路400和第一发光控制电路500。
例如，驱动电路100包括第一端110、第二端120和控制端130，其配置为控制驱动发光元件600发光的驱动电流，且驱动电路100的控制端130和第一节点N1连接，驱动电路100的第一端110和第二节点N2连接，驱动电路100的第二端120和第三节点N3连接。例如，在发光阶段，驱动电路100可以向发光元件600提供驱动电流以驱动发光元件600进行发光，且可以根据需要的“灰度”发光。例如，发光元件600可以采用OLED或QLED(Quantum Dot Light Emitting Diodes，量子点发光二极管)等，且配置为和第三节点N3以及第二电压端VSS(例如，低电压端)连接，本公开的实施例包括但不限于此情形。相应的，显示面板为OLED显示面板或QLED显示面板。下面以发光元件为OLED为例进行说明，相应的描述也同样适用于QLED。
例如，数据写入电路200与驱动电路100的第一端110(第二节点N2)连接，且配置为响应于扫描信号将数据信号写入驱动电路100的第一端110。例如，数据写入电路200包括第一端210、第二端220和控制端230，且分别和数据线(数据信号端Vdata)、第二节点N2以及扫描线(扫描信号端Gate)连接。例如，来自扫描信号端Gate的扫描信号被施加至数据写入电路200 的控制端230以控制数据写入电路200开启与否。
例如，在数据写入阶段，数据写入电路200可以响应于扫描信号而开启，从而可以将数据信号写入驱动电路100的第一端110(第二节点N2)，并将数据信号存储在补偿电路300中，以在例如发光阶段时可以根据该数据信号生成驱动发光元件600发光的驱动电流。例如，该数据电压Vdata的大小决定了该像素单元的发光亮度(即用于显示的灰度)。
例如，补偿电路300与驱动电路的控制端130(第一节点N1)以及第二端120(第三节点N3)连接且与第一电压端VDD(例如，高电压端)连接，配置为响应于扫描信号以及写入的数据信号对驱动电路100进行补偿。例如，补偿电路300可以与扫描信号端Gate、第一电压端VDD、第一节点N1以及第三节点N3连接。例如，来自扫描信号端Gate的扫描信号被施加至补偿电路300以控制其开启与否。例如，在补偿电路300包括电容的情形下，例如在数据写入和补偿阶段，补偿电路300可以响应于扫描信号而开启，从而可以将数据写入电路200写入的数据信号存储在该电容中。例如，同时在数据写入和补偿阶段，补偿电路300可以将驱动电路100的控制端130和第二端120电连接，从而可以使驱动电路100的阈值电压的相关信息也相应地存储在该电容中，从而例如在发光阶段可以利用存储的包括数据信号以及阈值电压的信号对驱动电路100进行控制，使得驱动电路100的输出得到补偿。
例如，发光元件600包括第一端610和第二端620，发光元件600的第一端610配置为从驱动电路100的第二端120接收驱动电流，发光元件600的第二端620配置为与第二电压端VSS连接。例如，如图2所示，在该像素电路10包括第二发光控制电路时，发光元件600的第一端610与第四节点N4连接。
例如，复位电路400与驱动电路100的控制端130(第一节点N1)以及发光元件600的第一端610连接，且配置为响应于复位信号将复位电压Vint施加至驱动电路的控制端130以及发光元件600的第一端610。例如，如图2所示，该复位电路400分别和第一节点N1、复位电压端Vint、发光元件600的第一端610以及复位控制端Rst(复位控制线)连接。例如，在初始化阶段，复位电路400可以响应于复位信号而开启，从而可以将复位电压施加至 第一节点N1以及发光元件600的第一端610，从而可以对驱动电路100、补偿电路300以及发光元件600进行复位操作，消除之前的发光阶段的影响。
例如，当复位电压Vint通过复位电路400施加至驱动晶体管的栅极，同时驱动晶体管的源极的电位被放电至Vint-Vth，从而在此阶段，可以使驱动晶体管的栅极和源极的电压V GS满足：|V GS|<|Vth|(Vth为驱动晶体管的阈值电压，例如在驱动晶体管为P型晶体管时，Vth通常为负值，例如，在驱动晶体管为N型晶体管时，Vth通常为正值)，从而使驱动晶体管处于V GS为固定偏置的截止状态(off-bias)。采用这种配置方式，可以实现不论前一帧的数据信号为黑态还是白态信号，驱动晶体管都由固定偏置的截止状态开始进入例如数据写入及补偿阶段，从而可以改善采用传统像素电路的显示装置的由于迟滞效应可能产生的短期残像问题。
例如，第一发光控制电路500与驱动电路100的第一端110(第二节点N2)连接，且配置为响应于第一发光控制信号将第一电压端VDD的第一电压施加至驱动电路100的第一端110。例如，如图2所示，第一发光控制电路500包括控制端530、第一端510和第二端520，分别和第一发光控制端Em1、第一电压端VDD以及第二节点N2连接。例如，第一发光控制端Em1可以和提供第一发光控制信号的第一发光控制线连接，或者与提供第一发光控制信号的控制电路连接。例如，在发光阶段，第一发光控制电路500可以响应于第一发光控制信号而开启，从而可以将第一电压VDD施加至驱动电路100的第一端110，在驱动电路100导通时，驱动电路100将此第一电压VDD施加至发光元件600以提供驱动电压，从而驱动发光元件发光。例如，第一电压VDD可以是驱动电压，例如高电压。
例如，如图2所示，在本实施例的另一个示例中，像素电路10还可以包括第二发光控制电路700。第二发光控制电路700包括控制端730、第一端710和第二端720和，其分别和第二发光控制端Em2、发光元件600的第一端610以及驱动电路100的第二端120连接，且配置为响应于第二发光控制信号以使得驱动电流可被施加至发光元件600。
例如，在发光阶段，第二发光控制电路700响应于第二发光控制端Em2提供的第二发光控制信号而开启，从而驱动电路100可以通过第二发光控制 电路700将驱动电流施加至发光元件600以使其发光；而在非发光阶段，第二发光控制电路700响应于第二发光控制信号而截止，从而避免有电流流过发光元件600而使其发光，可以提高相应的显示装置的对比度。
又例如，在初始化阶段，第二发光控制电路700也可以响应于第二发光控制信号而开启，从而可以结合复位电路以对驱动电路100以及发光元件600进行复位操作。
例如，第二发光控制信号不同于第一发光控制信号，例如二者可以连接到不同的信号输出端，如上所述例如在初始化阶段可以单独使第二发光控制信号为开启信号。例如，第一发光控制信号和第二发光控制信号至少部分时间段内同时为开启信号，例如在发光阶段，可以使第一发光控制信号和第二发光控制信号同时为开启信号，以使得发光元件600可发光。例如，第二发光控制信号的下降沿也可以与第一发光控制信号下降沿同时，从而由数据写入与补偿阶段直接进入发光阶段。
需要说明的是，在本公开的实施例中所述的第一发光控制信号和第二发光控制信号是两个时序不同的发光控制信号。例如，在一个显示装置中，当像素电路10呈阵列排布时，对于一行像素单元而言，第一发光控制信号可以为控制本行像素单元的像素电路10中的第一发光控制电路500的控制信号，同时，该第一发光控制信号还控制上一行像素电路10中的第二发光控制电路700；同样的，第二发光控制信号为控制本行像素电路10中的第二发光控制电路700的控制信号，同时，该第二发光控制信号还控制下一行像素电路10中的第一发光控制电路500。
例如，在驱动电路100实现为驱动晶体管的情形时，例如驱动晶体管的栅极可以作为驱动电路100的控制端130(连接到第一节点N1)，第一极(例如源极)可以作为驱动电路100的第一端110(连接到第二节点N2)，第二极(例如漏极)可以作为驱动电路100的第二端120(连接到第三节点N3)。
需要说明的是，本公开的实施例中的第一电压端VDD例如保持输入直流高电平信号，将该直流高电平称为第一电压；第二电压端VSS例如保持输入直流低电平信号，将该直流低电平称为第二电压，例如，该第二电压小于第一电压。以下各实施例与此相同，不再赘述。
需要说明的是，在本公开的实施例的描述中，符号Vdata既可以表示数据信号端又可以表示数据信号的电平，同样地，符号Vint既可以表示复位电压端又可以表示复位电压，符号VDD既可以表示第一电压端又可以表示第一电压，符号VSS既可以表示第二电压端又可以表示第二电压。以下各实施例与此相同，不再赘述。
本公开上述实施例提供的像素电路10不仅可以改善采用上述像素电路的显示装置由于迟滞效应可能产生的短期残像问题，还可以对驱动电路100内部的阈值电压进行补偿，使得驱动发光元件600的驱动电流不受该阈值电压的影响，从而可以改善使用该像素电路的显示装置的显示效果以及延长发光元件600的使用寿命。
例如，如图3所示，在本实施例的另一个示例中，像素电路10还可以包括发光控制信号切换电路800。
例如，发光控制信号切换电路800与第一发光控制端Em1、第二发光控制端Em2、第一发光控制电路500的控制端530和第二发光控制电路700的控制端730电连接，配置为响应于发光控制切换信号将第一发光控制信号和第二发光控制信号交替施加至第一发光控制电路500的控制端530和第二发光控制电路700的控制端730。例如，在不同的示例中，发光控制切换信号可以包括一个，也可以包括多个。
例如，发光控制信号切换电路800可以响应于发光控制切换信号将第一发光控制信号施加至第一发光控制电路500的控制端530，将第二发光控制信号施加至第二发光控制电路700的控制端730，从而当复位电压Vint通过复位电路400施加至驱动晶体管的栅极，同时驱动晶体管的源极的电位被放电至Vint-Vth截止，从而在此阶段可以使驱动晶体管的栅极和源极的电压V GS满足：|V GS|<|Vth|，从而使驱动晶体管处于V GS为固定偏置的截止状态。采用这种配置方式，可以实现不论前一帧的数据信号为黑态还是白态信号，驱动晶体管都由固定偏置的截止状态(off-bias)开始进入例如数据写入及补偿阶段，从而可以改善采用上述像素电路的显示装置的由于迟滞效应可能产生的短期残像问题。
例如，发光控制信号切换电路800可以响应于发光控制切换信号将第二 发光控制信号施加至第一发光控制电路500的控制端530，将第一发光控制信号施加至第二发光控制电路700的控制端730，从而当复位电压Vint通过复位电路400施加至驱动晶体管的栅极，同时将第一电压VDD施加至驱动晶体管的源极，从而可以使驱动晶体管的栅极和源极的电压V GS满足：|V GS|>|Vth|，从而使驱动晶体管处于V GS为固定偏置的开启状态(on-bias)。采用这种配置方式，可以实现不论前一帧的数据信号DATA为黑态还是白态信号，驱动晶体管都由固定偏置的开启状态开始进入例如数据写入和补偿阶段，从而可以改善采用传统像素电路的显示装置的由于迟滞效应可能产生的短期残像问题。
在一个显示面板中，本公开实施例提供的像素电路10不仅可以通过固定偏置的截止状态解决短期残像问题，也可以通过固定偏置的开启状态解决短期残像问题。
例如，图2中所示的像素电路10可以具体实现为图4所示的像素电路结构。如图4所示，该像素电路10包括：第一至第七晶体管T1、T2、T3、T4、T5、T6、T7以及包括电容C1和发光元件L1。例如，第一晶体管T1被用作驱动晶体管，其他的第二至第七晶体管被用作开关晶体管。例如，发光元件L1可以为各种类型的OLED，例如顶发射、底发射、双侧发射等，可以发红光、绿光、蓝光或白光等，本公开的实施例对此不作限制。
例如，如图4所示，更详细地，驱动电路100可以实现为第一晶体管T1。第一晶体管T1的栅极作为驱动电路100的控制端130，和第一节点N1连接；第一晶体管T1的第一极作为驱动电路100的第一端110，和第二节点N2连接；第一晶体管T1的第二极作为驱动电路100的第二端120，和第三节点N3连接。需要注意的是，不限于此，驱动电路100也可以是由其他的组件组成的电路，例如，驱动电路100可以具有两组驱动晶体管，例如，该两组驱动晶体管可以根据具体情况进行切换。
数据写入电路200可以实现为第二晶体管T2。第二晶体管T2的栅极作为数据写入电路200的控制端230，配置为和扫描线(扫描信号端Gate)连接以接收扫描信号，第二晶体管T2的第一极作为数据写入电路200的第一端210，配置为和数据线(数据信号端Vdata)连接以接收数据信号，第二晶 体管T2的第二极作为数据写入电路200的第二端220，和第二节点N2连接。需要注意的是，不限于此，数据写入电路200也可以是由其他的组件组成的电路，例如，数据写入电路200可以具有两组数据写入电路，例如，该两组数据写入电路可以根据具体情况进行切换。
补偿电路300可以实现为第三晶体管T3和电容C1。第三晶体管T3的栅极配置为和扫描线(扫描信号端Gate)连接以接收扫描信号，第三晶体管T3的第一极和驱动电路100的控制端130(第一节点N1)连接，第三晶体管的第二极和驱动电路100的第二端120(第三节点N3)连接；电容C1的第一极和驱动电路100的控制端130连接，电容C1的第二极配置为和第一电压端VDD连接。需要注意的是，不限于此，补偿电路300也可以是由其他的组件组成的电路，例如，补偿电路300可以具有两组补偿电路，例如，该两组补偿电路可以根据具体情况进行切换。
发光元件L1的第一端610(这里为阳极)和第四节点N4连接配置为从驱动电路100的第二端120接收驱动电流，发光元件L1的第二端620(这里为阴极)配置为和第二电压端VSS连接以接收第二电压。例如第二电压端可以接地，即VSS可以为0V。
复位电路400可以实现为第四晶体管T4和第五晶体管T5。第四晶体管T4的栅极配置为和复位控制线(复位控制端Rst)连接以接收复位信号，第四晶体管T4的第一极和驱动电路100的控制端130(第一节点N1)连接，第四晶体管T4的第二极配置为和复位电压端Vint连接以接收复位电压；第五晶体管T5的栅极配置为和复位控制线连接以接收复位信号，第五晶体管T5的第一极和发光元件L1的第一端610连接，第五晶体管T5的第二极配置为和复位电压端Vint连接以接收复位电压。需要注意的是，不限于此，复位电路400也可以是由其他的组件组成的电路，例如，复位电路400可以具有两组复位电路，例如，该两组复位电路可以根据具体情况进行切换。
第一发光控制电路500可以实现为第六晶体管T6。第六晶体管T6的栅极作为第一发光控制电路500的控制端530，配置为和第一发光控制端Em1连接以接收第一发光控制信号，第六晶体管T6的第一极作为第一发光控制电路500的第一端，配置为和第一电压端VDD连接以接收第一电压，第六 晶体管T6的第二极作为第一发光控制电路500的第二端，和驱动电路的第一端110(第二节点N2)连接。需要注意的是，不限于此，第一发光控制电路500也可以是由其他的组件组成的电路，例如，第一发光控制电路500可以具有两组第一发光控制电路，例如，该两组第一发光控制电路可以根据具体情况进行切换。
第二发光控制电路700可以实现为第七晶体管T7。第七晶体管T7的栅极作为第二发光控制电路700的控制端730，和第二发光控制线第二发光控制端Em2连接以接收第二发光控制信号，第七晶体管T7的第一极作为第二发光控制电路700的第二端720，和发光元件L1的第一端610(第四节点N4)连接，第七晶体管T7的第二极作为第二发光控制电路700的第一端710，和驱动电路100的第二端120(第三节点N3)连接。需要注意的是，不限于此，第二发光控制电路700也可以是由其他的组件组成的电路，例如，第二发光控制电路700可以具有两组第二发光控制电路，例如，该两组第二发光控制电路可以根据具体情况进行切换。
在本公开的说明中，第一节点N1、第二节点N2、第三节点N3、第四节点N4并非表示实际存在的部件，而是表示电路图中相关电连接的汇合点。
图5示出了本公开一实施例提供的另一种像素电路的示意图。图3所示的像素电路可以具体实现为图5所示的像素电路结构。图5所示的像素电路与图4所示的像素电路基本相同，区别在于图5所示的像素电路10还包括发光控制信号切换电路800，该发光控制信号切换电路800实现为第八至第十一晶体管T8、T9、T10、T11。
例如，如图5所示，更详细地，发光控制信号切换电路800可以实现为第八至第十一晶体管T8、T9、T10、T11。第八晶体管T8的栅极接收第一发光控制切换信号CK1，第八晶体管T8的第一极和第一发光控制信号端Em1连接，第八晶体管T8的第二极和第一发光控制电路500的控制端530连接。第九晶体管T9的栅极接收第一发光控制切换信号CK1，第九晶体管T9的第一极和第二发光控制信号端Em2连接，第九晶体管T9的第二极和第二发光控制电路700的控制端730连接；第十晶体管T10的栅极接收第二发光控制切换信号CK2，第十晶体管T10的第一极和第二发光控制信号端Em2连接， 第十晶体管T10的第二极和第一发光控制电路500的控制端530连接；第十一晶体管T11的栅极接收第二发光控制切换信号CK2，第十一晶体管T11的第一极和第一发光控制信号端Em1连接，第十一晶体管T11的第二极和第二发光控制电路700的控制端730连接。需要注意的是，不限于此，发光控制信号切换电路800也可以是由其他的组件组成的电路，例如，发光控制信号切换电路800可以具有两组发光控制信号切换电路，例如，该两组发光控制信号切换电路可以根据具体情况进行切换。
需要说明的是，在本公开的实施例的描述中，符号CK1既可以表示第一发光控制切换信号端又可以表示第一发光控制切换信号的电平，同样地，符号CK2既可以表示第二发光控制切换信号端又可以表示第二发光控制切换信号的电平。
下面结合图6所示的信号时序图，对图5所示的像素电路10的工作原理进行说明，并且这里以各个晶体管为P型晶体管为例进行说明，但是本公开的实施例不限于此。例如，P型晶体管响应于低电平信号而导通，响应于高电平信号而截止，以下实施例与此相同，不再赘述。
图6包括第N(N为大于等于1的整数)帧图像的显示过程和第N+1帧图像的显示过程。如图6所示，每一帧图像的显示过程包括四个阶段，分别为初始化阶段1、数据写入及补偿阶段2、预发光阶段3以及发光阶段4，图中示出了每个阶段中各个信号的时序波形。
需要说明的是，图7A至图7D分别为图5中所示的像素电路处于第N帧图像显示过程中的示意图，图8A至图8D分别为图5中所示的像素电路处于第N+1帧图像显示过程中的示意图。
图7A为图5中所示的像素电路处于第N帧图像显示过程中初始化阶段1时的示意图，图7B为图5中所示的像素电路处于第N帧图像显示过程中数据写入及补偿阶段2时的示意图，图7C为图5中所示的像素电路处于第N帧图像显示过程中预发光阶段3时的示意图，图7D为图5中所示的像素电路处于第N帧图像显示过程中发光阶段4时的示意图。例如，第二发光控制信号的下降沿也可以与第一发光控制信号下降沿同时，从而由数据写入与补偿阶段2直接进入发光阶段4。
图8A为图5中所示的像素电路处于第N+1帧图像显示过程中初始化阶段1时的示意图，图8B为图5中所示的像素电路处于第N+1帧图像显示过程中数据写入及补偿阶段2时的示意图，图8C为图5中所示的像素电路处于第N+1帧图像显示过程中预发光阶段3时的示意图，图8D为图5中所示的像素电路处于第N+1帧图像显示过程中发光阶段4时的示意图。
另外，图7A至图8D中用虚线标识的晶体管均表示在对应阶段内处于截止状态，图7A至图8D中带箭头的虚线表示像素电路在对应阶段内的电流方向。图7A至图8B中所示的晶体管均以P型晶体管为例进行说明，即各个晶体管的栅极在接入低电平时导通，而在接入高电平时截止。
在第N帧图像的显示过程中，输入第一发光控制切换信号(第一发光控制切换信号端CK1提供)以开启发光控制信号切换电路，将第一发光控制信号施加至第一发光控制电路500的控制端530，将第二发光控制信号施加至第二发光控制电路700的控制端730。
如图6和图7A至图7D所示，在第N帧图像的显示过程中，第八晶体管T8和第九晶体管T9被第一发光控制切换信号CK1的低电平导通；同时第十晶体管T10和第十一晶体管T11被第二发光控制切换信号CK2的高电平截止。如图7A至图7D所示，形成一条发光控制信号切换路径(如图7A至图7D中发光控制信号切换电路部分带箭头的虚线所示)，由于第八晶体管T8导通，可以将第一发光控制信号施加至第六晶体管T6的栅极，由于第九晶体管T9导通，可以将第二发光控制信号施加至第七晶体管T7的栅极。
在初始化阶段1，输入复位信号和第二发光控制信号以开启复位电路400和第二发光控制电路700，将复位电压施加至驱动电路100的控制端130和第二端120以及发光元件600的第一端610。
如图6和图7A示，在初始化阶段1，第四晶体管T4和第五晶体管T5被复位信号的低电平导通，第七晶体管T7被第二发光控制信号的低电平导通；同时，第二晶体管T2和第三晶体管T3被扫描信号的高电平截止，第六晶体管T6被第一发光控制信号的高电平截止。
如图7A所示，在初始化阶段1，形成一条复位路径(如图7A中带箭头的虚线所示)，由于第四晶体管T4导通，可以将复位电压Vint施加至第一 晶体管T1的栅极，由于第五晶体管T5和第七晶体管T7的导通，可以将复位电压Vint施加至第一晶体管T1的第二极以及发光元件L1，从而将第一节点N1和发光元件L1复位。所以，经过初始化阶段1后第一节点N1的电位为复位电压Vint(低电平信号，例如可以接地或为其他低电平信号)。在此阶段，由于第一晶体管T1和第七晶体管T7导通，第六晶体管T6截止，根据第一晶体管T1自身的特性，第一晶体管T1的源极的电位被放电至Vint-Vth截止。从而在此阶段，可以使第一晶体管T1的栅极(即第一节点N1)和源极(即第二节点N2)的电压V GS满足：|V GS|<|Vth|，从而使第一晶体管T1处于V GS为固定偏置的截止状态(off-bias)。采用这种配置方式，可以实现不论前一帧的数据信号为黑态还是白态信号，第一晶体管T1都由固定偏置的截止状态开始进入数据写入及补偿阶段2，从而可以改善采用像素电路10的显示装置的由于迟滞效应可能产生的短期残像问题。
经过初始化阶段1后，第一节点N1的电位为复位电压Vint，第二节点N2的电位为Vint-Vth。在初始化阶段1，电容C1被复位，使存储在电容C1中的电压放电，从而使后续阶段中的数据信号可以被更迅速、更可靠地存储在电容C1中；同时，第三节点N3和发光元件L1也被复位，从而可以使发光元件L1在发光阶段4之前显示为黑态不发光，改善采用上述像素电路的显示装置的对比度等显示效果。
在数据写入及补偿阶段2，输入扫描信号和数据信号以开启数据写入电路200、驱动电路100和补偿电路300，数据写入电路200将数据信号写入驱动电路100，补偿电路300对驱动电路100进行补偿。
如图6和图7B所示，在数据写入及补偿阶段2，第二晶体管T2和第三晶体管T3被扫描信号的低电平导通；同时，第四晶体管T4和第五晶体管T5被复位信号的高电平截止，第六晶体管T6被第一发光控制信号的高电平截止，第七晶体管T7被第二发光控制信号的高电平截止。
如图7B所示，在数据写入及补偿阶段2，形成一条数据写入及补偿路径(如图7B中带箭头的虚线所示)，数据信号经过第二晶体管T2、第一晶体管T1和第三晶体管T3后对第一节点N1进行充电(即对电容C1充电)，也就是说第一节点N1的电位变大。容易理解，第二节点N2的电位保持为 Vdata，同时根据第一晶体管T1的自身特性，当第一节点N1的电位增大到Vdata+Vth时，第一晶体管T1截止，充电过程结束。需要说明的是，Vdata表示数据信号的电压值，Vth表示第一晶体管的阈值电压，由于在本实施例中，第一晶体管T1是以P型晶体管为例就行说明的，所以此处阈值电压Vth可以是个负值。
经过数据写入阶段2后，第一节点N1和第三节点N3的电位均为Vdata+Vth，也就是说将带有数据信号和阈值电压Vth的电压信息存储在了电容C1中，以用于后续在发光阶段时，提供灰度显示数据和对第一晶体管T1自身的阈值电压进行补偿。
在预发光阶段3，输入第一发光控制信号以开启第一发光控制电路500和驱动电路100，第一发光控制电路500将第一电压施加至驱动电路100的第一端110。
如图6和图7C所示，在预发光阶段3，第六晶体管T6被第一发光控制信号的低电平导通；同时，第二晶体管T2和第三晶体管T3被扫描信号的高电平截止，第四晶体管T4和第五晶体管T5被复位信号的高电平截止，第七晶体管T7被第二发光控制信号的高电平截止。
如图7C所示，在预发光阶段3，形成一条预发光路径(如图7C中带箭头的虚线所示)。第一电压经过第六晶体管T6对第二节点N2进行充电，第二节点N2的电位由Vdata变为第一电压VDD，由于在此阶段第七晶体管T7截止，所以为下一阶段的发光元件L1的发光做准备。
在发光阶段4，输入第一发光控制信号和第二发光控制信号以开启第一发光控制电路500、第二发光控制电路700和驱动电路100，第二发光控制电路700将驱动电流施加至发光元件L1以使其发光。
如图6和图7D所示，在发光阶段4，第六晶体管T6被第一发光控制信号的低电平导通，第七晶体管T7被第二发光控制信号的低电平导通；同时，第二晶体管T2和第三晶体管T3被扫描信号的高电平截止，第四晶体管T4和第五晶体管T5被复位信号的高电平截止。同时，第一节点N1的电位Vdata+Vth，第二节点N2的电位为VDD，所以在此阶段第一晶体管T1也保持导通。
如图7D所示，在发光阶段4，形成一条驱动发光路径(如图7D中带箭头的虚线所示)。发光元件L1可以在流经第一晶体管T1的驱动电流的作用下发光。
具体地，流经发光元件L1的驱动电流I L1的值可以根据下述公式得出：
I L1＝K(V GS-Vth) 2
＝K[(Vdata+Vth-VDD)-Vth] 2
＝K(Vdata-VDD) 2
其中，K＝W*C OX*U/L。
在上述公式中，Vth表示第一晶体管T1的阈值电压，V GS表示第一晶体管T1的栅极和源极(这里为第一极)之间的电压，K为与驱动晶体管本身相关的一常数值。从上述I L1的计算公式可以看出，流经发光元件L1的驱动电流I L1不再与第一晶体管T1的阈值电压Vth有关，由此可以实现对该像素电路的补偿，解决了驱动晶体管(在本公开的实施例中为第一晶体管T1)由于工艺制程及长时间的操作造成阈值电压漂移的问题，消除其对驱动电流I L1的影响，从而可以改善采用其的显示装置的显示效果。
如图8A至图8D中所示，在第N+1帧图像显示过程中，输入第二发光控制切换信号(第二发光控制切换信号端CK2)以开启发光控制信号切换电路，将第二发光控制信号施加至第一发光控制电路500的控制端530，将第一发光控制信号施加至第二发光控制电路700的控制端730。
如图6和图8A至图8D所示，在第N+1帧图像的显示过程中，第十晶体管T10和第十一晶体管T11被第二发光控制切换信号CK2的低电平导通；同时第八晶体管T8和第九晶体管T9被第一发光控制切换信号CK1的高电平截止。如图8A至图8D所示，形成一条发光控制信号切换路径(如图8A至图8D中发光控制信号切换电路部分带箭头的虚线所示)，由于第十晶体管T10导通，可以将第二发光控制信号施加至第六晶体管T6的栅极，由于第十一晶体管T11导通，可以将第一发光控制信号施加至第七晶体管T7的栅极。
第N+1帧图像显示的工作原理与第N帧图像显示的工作原理基本相同，区别在于：在第N+1帧图像显示过程中的初始化阶段1，第六晶体管T6被 第二发光控制信号的低电平导通，第七晶体管T7被第一发光控制信号的高电平截止，从而在此阶段，由于第六晶体管T6导通，第一晶体管T1的源极的电位被充电至第一电压VDD，从而第一晶体管T1的栅极(即第一节点N1)和源极(即第二节点N2)的电压V GS满足：|V GS|>|Vth|，从而使第一晶体管T1处于V GS为固定偏置的开启状态(on-bias)。采用这种配置方式，可以实现不论前一帧的数据信号为黑态还是白态信号，第一晶体管T1都由固定偏置的开启状态开始进入数据写入及补偿阶段2，从而可以改善采用像素电路10的显示装置的由于迟滞效应可能产生的短期残像问题。
另外，如图8C所示，在第N+1帧图像显示过程中的预发光阶段3，第六晶体管T6由于第二发光控制信号的高电平截止，第七晶体管T7由于第一发光控制信号的低电平导通，所以为下一阶段的发光元件L1的发光做准备。
图4所示的像素电路10的工作原理与图7A至图7D中所示的图5所示的像素电路的工作原理基本相同，其区别在于图4所示的像素电路10不包括发光控制信号切换电路800，因此第一发光控制电路500的控制端530直接与第一发光控制信号端Em1连接，第二发光控制电路700的控制端730直接与第二发光控制信号端Em2连接，不存在第N帧与第N+1帧切换的情形。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。
另外，需要说明的是，图5中所示的像素电路10中的晶体管均是以P型晶体管为例进行说明的，此时，第一极可以是漏极，第二极可以是源极。如图5所示，该像素电路10中的发光元件L1的阴极和第二电压端VSS连接以接收第二电压。例如，在一个显示面板中，当图5中所示的像素电路10呈阵列排布时，发光元件L1的阴极可以电连接到同一个电压端，即采用共阴极连接方式。
本公开的实施例包括但不限于图5中的配置方式，在本公开的另一个实 施例中，发光控制信号切换电路中还可以包括仅一条发光控制切换信号线。
例如，在一个示例中，如图9所示，像素电路10中的晶体管可以混合采用P型晶体管和N型晶体管，只需同时将选定类型的晶体管的端口极性按照本公开的实施例中的相应晶体管的端口极性相应连接即可。例如，如图9所示，第一至第九晶体管T1-T9采用P型晶体管，第十晶体管T10和第十一晶体管T11采用N型晶体管。例如，第八晶体管至第十一晶体管T8-T11同时连接到第一发光控制切换信号端CK1。
需要说明的是，在本公开的实施例中，当第十晶体管T10和第十一晶体管T11采用N型晶体管时，其可以采用IGZO(Indium Gallium Zinc Oxide，氧化铟镓锌)作为薄膜晶体管的有源层，相对于采用LTPS(Low Temperature Poly Silicon，低温多晶硅)或非晶硅(例如氢化非晶硅)作为薄膜晶体管的有源层，可以有效减小驱动晶体管的尺寸以及防止漏电流。
例如，在另一个示例中，如图10所示，像素电路10可以通过在第十晶体管T10和第十一晶体管T11的栅极与第一发光控制切换信号端CK1之间连接反相器900实现，例如，该反相器实现为运算放大器A、第一电阻R1和第二电阻R2。需要注意的是，反相器900不限于上述结构，本公开的实施例对此不作限制。例如，该反相器900可以为TTL反相器，也可以为CMOS反相器。
本公开一实施例还提供一种显示面板11，如图11所示，显示面板11位于显示装置1中，该显示装置1包括栅极驱动器12、数据驱动器14和定时控制器13。该显示面板11包括根据多条扫描线GL和多条数据线DL交叉限定的像素单元P；栅极驱动器12，用于驱动多条扫描线GL；数据驱动器14，用于驱动多条数据线DL；以及定时控制器13，用于处理从显示装置1外部输入的图像数据RGB、向数据驱动器14提供处理的图像数据RGB以及向栅极驱动器12和数据驱动器14输出扫描控制信号GCS和数据控制信号DCS，以对栅极驱动器12和数据驱动器14进行控制。
例如，该显示面板11包括阵列布置的多个像素单元P，该多个像素单元P每个包括上述实施例中提供的任一像素电路10以及发光元件(图中未示出)。例如，包括图5所示像素电路10。例如，也可以包括如图4所示的像 素电路。例如，发光元件的第一端配置为从像素电路10中的驱动电路100的第二端120接收驱动电流，发光元件的第二端配置为与第二电压端VSS连接。
如图11所示，显示面板11还包括多条扫描线GL和多条数据线DL。例如，像素单元P设置在扫描线GL和数据线DL的交叉区域。例如，如图11所示，每个像素单元P连接到六条扫描线GL(分别提供扫描信号、复位控制信号、第一发光控制信号、第二发光控制信号、第一发光控制切换信号以及第二发光控制切换信号)、一条数据线DL、用于提供第一电压的第一电压线、用于提供第二电压的第二电压线以及用于提供复位电压的复位电压线。例如，第一电压线或第二电压线可以用相应的板状公共电极(例如公共阳极或公共阴极)替代。需要说明的是，在图11中仅示出了部分的像素单元P、扫描线GL、数据线DL。
例如，该多个像素单元P排列为多行，第n(n为大于等于2整数)行像素单元P的像素电路的数据写入电路200的控制端230和补偿电路300的控制端连接到同一条扫描线GL，且第n行像素单元P的像素电路的复位电路400的控制端连接到另一条扫描线GL。例如，该另一条扫描线GL还与第n-1行的像素单元P的像素电路的数据写入电路200的控制端230和补偿电路300的控制端连接。例如，每一列的数据线DL和本列像素电路10中的数据写入电路200的第一端210连接以提供数据信号。
又例如，显示面板11还可以包括多条复位控制线。例如，多个像素单元P排列为多行，一行像素单元P的像素电路10的数据写入电路200的控制端和补偿电路300的控制端连接到同一条扫描线，且一行像素单元P的像素电路10的复位电路400的控制端连接到同一条复位控制线(复位控制端Rst)。
例如，在像素电路10包括第二发光控制电路700的情形下，显示面板11还可以包括多条发光控制线。
例如，多个像素单元排列为多行，第m(m为大于等于1整数)行像素单元P的像素电路的第一发光控制电路500的控制端530连接到同一条发光控制线，且第m行像素单元P的像素电路的第二发光控制电路700的控制端730连接到另一条发光控制线。例如，另一条发光控制线还与第m+1行的像 素单元P的像素电路的第一发光控制电路500的控制端连接。
例如，在像素电路10包括发光控制信号切换电路800的情形下，显示面板11还可以包括多条发光控制切换信号线。
例如，在一个示例中，多个像素单元排列为多行，第m行像素单元的像素电路的发光控制信号切换电路的控制端连接到同一条发光控制切换信号线。例如，在另一个示例中，第m行像素单元的像素电路的发光控制信号切换电路的控制端连接到两条发光控制切换信号线。例如，两条发光控制切换信号线中的一条发光控制切换信号线提供的发光控制切换信号的上升沿是另一条发光控制切换信号线提供的发光控制切换信号的下降沿。
例如，栅极驱动器12根据源自定时控制器13的多个扫描控制信号GCS向多个扫描线GL提供多个选通信号。多个选通信号包括扫描信号、第一发光控制信号、第二发光控制信号以及复位信号。这些信号通过多个扫描线GL提供给每个像素单元P。
例如，数据驱动器14使用参考伽玛电压根据源自定时控制器13的多个数据控制信号DCS将从定时控制器13输入的数字图像数据RGB转换成数据信号。数据驱动器14向多条数据线DL提供转换的数据信号。
例如，定时控制器13对外部输入的图像数据RGB进行处理以匹配显示面板11的大小和分辨率，然后向数据驱动器14提供处理的图像数据。定时控制器13使用从显示装置外部输入的同步信号(例如点时钟DCLK、数据使能信号DE、水平同步信号Hsync以及垂直同步信号Vsync)产生多条扫描控制信号GCS和多条数据控制信号DCS。定时控制器13分别向栅极驱动器12和数据驱动器14提供产生的扫描控制信号GCS和数据控制信号DCS，以用于栅极驱动器12和数据驱动器14的控制。
例如，数据驱动器14可以与多条数据线DL连接，以提供数据信号Vdata；同时还可以与多条第一电压线、多条第二电压线和多条复位电压线连接以分别提供第一电压、第二电压和复位电压。
例如，栅极驱动器12和数据驱动器14可以实现为半导体芯片。该显示装置1还可以包括其他部件，例如信号解码电路、电压转换电路等，这些部件例如可以采用已有的常规部件，这里不再详述。
关于显示装置1的技术效果可以参考本公开的实施例中提供的像素电路10的技术效果，这里不再赘述。
例如，本实施例提供的显示装置1可以为电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开的实施例还提供一种驱动方法，可以用于驱动本公开的实施例提供的像素电路10。例如，在一个示例中，该驱动方法包括初始化阶段、数据写入及补偿阶段和发光阶段。
在初始化阶段，输入复位信号以开启复位电路400，将复位电压施加至驱动电路100的控制端130以及发光元件600的第一端610。
在数据写入及补偿阶段，输入扫描信号和数据信号以开启数据写入电路200、驱动电路100和补偿电路300，数据写入电路200将数据信号写入驱动电路100，补偿电路300对驱动电路100进行补偿。
在发光阶段，输入第一发光控制信号以开启第一发光控制电路500和驱动电路100，第一发光控制电路500将驱动电流施加至发光元件600以使其发光。
例如，在另一个示例中，在上述示例的基础上，像素电路10还包括第二发光控制电路700，该驱动方法还包括预发光阶段。
在所初始化阶段，输入复位信号和第二发光控制信号以开启复位电路400和第二发光控制电路700，将复位电压施加至驱动电路100的控制端130和第二端120以及发光元件600的第一端610。
在数据写入及补偿阶段，输入扫描信号和数据信号以开启数据写入电路200、驱动电路100和补偿电路300，数据写入电路200将数据信号写入驱动电路100，补偿电路300对驱动电路100进行补偿。
在预发光阶段，输入第一发光控制信号以开启第一发光控制电路500和驱动电路100，第一发光控制电路500将第一电压施加至驱动电路100的第一端110。
在发光阶段，输入第一发光控制信号和第二发光控制信号以开启第一发光控制电路500、第二发光控制电路700和驱动电路100，第二发光控制电路 700将驱动电流施加至发光元件600以使其发光。
在另一个示例中，在上述示例的基础上，像素电路10还包括发光控制信号切换电路800，该驱动方法包括以下步骤。
在初始化阶段，输入复位信号、第二发光控制信号和发光控制切换信号以开启复位电路400和发光控制信号切换电路800，以将第二发光控制信号施加于第一发光控制电路500的控制端530或第二发光控制电路700的控制端730，并将复位电压施加至驱动电路100的控制端130以及发光元件600的第一端610；
在数据写入及补偿阶段，输入扫描信号和数据信号以开启数据写入电路200、驱动电路100和补偿电路300，数据写入电路200将数据信号写入驱动电路100，补偿电路300对驱动电路100进行补偿；
在预发光阶段，输入发光控制切换信号和第一发光控制信号以将第一发光控制信号施加至第一发光控制电路500的控制端530或第二发光控制电路700的控制端730。当第一发光控制信号施加至第一发光控制电路500的控制端530时，第一发光控制电路500将第一电压VDD施加至驱动电路100的第一端510；
在发光阶段，输入发光控制切换信号、第一发光控制信号和第二发光控制信号以开启第一发光控制电路500、第二发光控制电路700和驱动电路100，第二发光控制电路700将驱动电流施加至发光元件600以使其发光。
需要说明的是，关于该驱动方法的详细描述可以参考本公开的实施例中对于像素电路10的工作原理的描述，这里不再赘述。
本实施例提供的驱动方法可以改善由于迟滞效应可能产生的短期残像问题，并对驱动电路的阈值电压进行补偿，例如可以避免显示不均匀，从而可以改善采用该像素电路的显示装置的显示效果。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (17)

  1. 一种像素电路，包括：驱动电路、数据写入电路、补偿电路、复位电路和第一发光控制电路；其中，
    所述驱动电路包括控制端、第一端和第二端，且配置为控制驱动发光元件发光的驱动电流；
    所述数据写入电路与所述驱动电路的第一端连接，且配置为响应于扫描信号将数据信号写入所述驱动电路的第一端；
    所述补偿电路与所述驱动电路的控制端以及第二端连接且与第一电压端连接，且配置为响应于所述扫描信号以及写入的所述数据信号对所述驱动电路进行补偿；
    所述复位电路与所述驱动电路的控制端以及第二端连接且与所述发光元件连接，且配置为响应于复位信号将复位电压施加至所述驱动电路的控制端以及所述发光元件的第一端；
    所述第一发光控制电路与所述驱动电路的第一端连接，且配置为响应于第一发光控制信号将所述第一电压端的第一电压施加至所述驱动电路的第一端。
  2. 根据权利要求1所述的像素电路，还包括第二发光控制电路，其中，
    所述第二发光控制电路的第一端和第二端分别和所述发光元件的第一端以及所述驱动电路的第二端连接，且配置为响应于第二发光控制信号以使得所述驱动电流可被施加至所述发光元件。
  3. 根据权利要求2所述的像素电路，还包括发光控制信号切换电路，其中，
    所述发光控制信号切换电路与所述第一发光控制电路的控制端和所述第二发光控制电路的控制端电连接，且配置为响应于发光控制切换信号将所述第一发光控制信号和所述第二发光控制信号交替施加至所述第一发光控制电路的控制端和所述第二发光控制电路的控制端。
  4. 根据权利要求1-3任一所述的像素电路，其中，所述驱动电路包括第一晶体管；
    所述第一晶体管的栅极作为所述驱动电路的控制端，所述第一晶体管的第一极作为所述驱动电路的第一端，所述第一晶体管的第二极作为所述驱动电路的第二端。
  5. 根据权利要求1-3任一所述的像素电路，其中，所述数据写入电路包括第二晶体管；
    所述第二晶体管的栅极作为所述数据写入电路的控制端配置为和扫描线连接以接收所述扫描信号，所述第二晶体管的第一极作为所述数据写入电路的第一端配置为和数据线连接以接收所述数据信号，所述第二晶体管的第二极作为所述数据写入电路的第二端和所述驱动电路的第一端连接。
  6. 根据权利要求1-3任一所述的像素电路，其中，所述补偿电路包括第三晶体管和电容；
    所述第三晶体管的栅极和扫描线连接以接收所述扫描信号，所述第三晶体管的第一极和所述驱动电路的控制端连接，所述第三晶体管的第二极和所述驱动电路的第二端连接；
    所述电容的第一极和所述驱动电路的控制端连接，所述电容的第二极和所述第一电压端连接以接收所述第一电压。
  7. 根据权利要求1-3任一所述的像素电路，其中，所述复位电路包括第四晶体管和第五晶体管；
    所述第四晶体管的栅极和复位控制线连接以接收所述复位信号，所述第四晶体管的第一极和所述驱动电路的控制端连接，所述第四晶体管的第二极和复位电压端连接以接收所述复位电压；
    所述第五晶体管的栅极和所述复位控制线连接以接收所述复位信号，所述第五晶体管的第一极和所述发光元件的第一端连接，所述第五晶体管的第二极和所述复位电压端连接以接收所述复位电压。
  8. 根据权利要求1-3任一所述的像素电路，其中，所述第一发光控制电路包括第六晶体管；
    所述第六晶体管的栅极作为所述第一发光控制电路的控制端配置为和第一发光控制线连接以接收所述第一发光控制信号，所述第六晶体管的第一极作为所述第一发光控制电路的第一端配置为和所述第一电压端连接以接收所 述第一电压，所述第六晶体管的第二极作为所述第一发光控制电路的第二端和所述驱动电路的第一端连接。
  9. 根据权利要求2或3所述的像素电路，其中，所述第二发光控制电路包括第七晶体管；
    所述第七晶体管的栅极作为所述第二发光控制电路的控制端和第二发光控制线连接以接收所述第二发光控制信号，所述第七晶体管的第一极作为所述第二发光控制电路的第二端和所述驱动电路的第二端连接，所述第七晶体管的第二极作为所述第二发光控制电路的第一端和所述发光元件的第一端连接。
  10. 根据权利要求2、3或9任一所述的像素电路，其中，所述第一发光控制信号和所述第二发光控制信号至少部分时间段内同时为开启信号。
  11. 根据权利要求3所述的像素电路，其中，所述发光控制信号切换电路包括第八晶体管、第九晶体管、第十晶体管和第十一晶体管；
    所述第八晶体管的栅极配置为接收所述发光控制切换信号，所述第八晶体管的第一极和第一发光控制线连接以接收所述第一发光控制信号，所述第八晶体管的第二极和所述第一发光控制电路的控制端连接；
    所述第九晶体管的栅极配置为接收所述发光控制切换信号，所述第九晶体管的第一极和第二发光控制线连接以接收所述第二发光控制信号，所述第九晶体管的第二极和所述第二发光控制电路的控制端连接；
    所述第十晶体管的栅极配置为接收所述发光控制切换信号，所述第十晶体管的第一极和所述第二发光控制线连接，所述第十晶体管的第二极和所述第一发光控制电路的控制端连接；
    所述第十一晶体管的栅极配置为接收所述发光控制切换信号，所述第十一晶体管的第一极和所述第一发光控制线连接，所述第十一晶体管的第二极和所述第二发光控制电路的控制端连接。
  12. 一种显示面板，包括阵列布置的多个像素单元，其中，所述多个像素单元每个包括权利要求1所述的像素电路以及发光元件。
  13. 根据权利要求12所述的显示面板，其中，所述像素电路还包括发光控制信号切换电路、所述第一发光控制电路和第二发光控制电路，所述发光 控制信号切换电路与第一发光控制线、第二发光控制线、所述第一发光控制电路的控制端和所述第二发光控制电路的控制端电连接，配置为响应于发光控制切换信号将所述第一发光控制线提供的所述第一发光控制信号和所述第二发光控制线提供的第二发光控制信号交替施加至所述第一发光控制电路的控制端和所述第二发光控制电路的控制端；
    所述显示面板还包括多条发光控制切换信号线，其中，所述多个像素单元排列为多行，第m行像素单元的像素电路的发光控制信号切换电路的控制端连接到同一条发光控制切换信号线，或者所述第m行像素单元的像素电路的发光控制信号切换电路的控制端连接到两条发光控制切换信号线，其中，所述两条发光控制切换信号线中的一条发光控制切换信号线提供的发光控制切换信号的上升沿是另一条发光控制切换信号线提供的发光控制切换信号的下降沿，其中m为大于等于1整数。
  14. 根据权利要求12所述的显示面板，其中，所述发光元件的第一端配置为从所述驱动电路的第二端接收所述驱动电流，所述发光元件的第二端配置为与第二电压端连接。
  15. 一种如权利要求1所述的像素电路的驱动方法，包括：初始化阶段、数据写入及补偿阶段和发光阶段；其中，
    在所述初始化阶段，输入所述复位信号以开启所述复位电路，将所述复位电压施加至所述驱动电路的控制端以及所述发光元件的第一端；
    在所述数据写入及补偿阶段，输入所述扫描信号和所述数据信号以开启所述数据写入电路、所述驱动电路和所述补偿电路，所述数据写入电路将所述数据信号写入所述驱动电路，所述补偿电路对所述驱动电路进行补偿；
    在所述发光阶段，输入所述第一发光控制信号以开启所述第一发光控制电路和所述驱动电路，所述第一发光控制电路将所述驱动电流施加至所述发光元件以使其发光。
  16. 一种如权利要求2所述的像素电路的驱动方法，包括：初始化阶段、数据写入及补偿阶段、预发光阶段和发光阶段；其中，
    在所述初始化阶段，输入所述复位信号和所述第二发光控制信号以开启所述复位电路和所述第二发光控制电路，将所述复位电压施加至所述驱动电 路的控制端和第二端以及所述发光元件的第一端；
    在所述数据写入及补偿阶段，输入所述扫描信号和所述数据信号以开启所述数据写入电路、所述驱动电路和所述补偿电路，所述数据写入电路将所述数据信号写入所述驱动电路，所述补偿电路对所述驱动电路进行补偿；
    在所述预发光阶段，输入所述第一发光控制信号以开启所述第一发光控制电路和所述驱动电路，所述第一发光控制电路将所述第一电压施加至所述驱动电路的第一端；
    在所述发光阶段，输入所述第一发光控制信号和所述第二发光控制信号以开启所述第一发光控制电路、所述第二发光控制电路和所述驱动电路，所述第二发光控制电路将所述驱动电流施加至所述发光元件以使其发光。
  17. 一种如权利要求3所述的像素电路的驱动方法，包括：初始化阶段、数据写入及补偿阶段、预发光阶段和发光阶段；其中，
    在所述初始化阶段，输入所述复位信号、所述第二发光控制信号和所述发光控制切换信号以开启所述复位电路和所述发光控制信号切换电路，以将所述第二发光控制信号施加于所述第一发光控制电路的控制端或所述第二发光控制电路的控制端，并将所述复位电压施加至所述驱动电路的控制端以及所述发光元件的第一端；
    在所述数据写入及补偿阶段，输入所述扫描信号和所述数据信号以开启所述数据写入电路、所述驱动电路和所述补偿电路，所述数据写入电路将所述数据信号写入所述驱动电路，所述补偿电路对所述驱动电路进行补偿；
    在所述预发光阶段，输入所述发光控制切换信号和所述第一发光控制信号以将所述第一发光控制信号施加至所述第一发光控制电路的控制端或所述第二发光控制电路的控制端，其中，所述第一发光控制信号施加至所述第一发光控制电路的控制端时，所述第一发光控制电路将所述第一电压施加至所述驱动电路的第一端；
    在所述发光阶段，输入所述发光控制切换信号、所述第一发光控制信号和所述第二发光控制信号以开启所述第一发光控制电路、所述第二发光控制电路和所述驱动电路，所述第二发光控制电路将所述驱动电流施加至所述发光元件以使其发光。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12008956B2 (en) 2021-02-09 2024-06-11 Samsung Electronics Co., Ltd. Electronic device and method capable of reducing afterimage of display
US12293715B2 (en) * 2022-06-24 2025-05-06 Boe Technology Group Co., Ltd. Pixel circuit, driving method and display device

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110942743B (zh) * 2019-12-26 2021-04-13 云谷（固安）科技有限公司 像素电路的驱动方法、显示面板和显示装置
CN111540315B (zh) * 2020-02-21 2024-03-15 福州京东方光电科技有限公司 像素驱动电路及其驱动方法、显示装置
CN113748454B (zh) * 2020-03-31 2023-10-24 京东方科技集团股份有限公司 像素电路及其驱动方法以及显示面板
CN113838415B (zh) * 2020-06-08 2023-01-17 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示面板及显示装置
KR102779924B1 (ko) * 2020-07-14 2025-03-12 삼성디스플레이 주식회사 표시 장치
WO2022094738A1 (zh) * 2020-11-03 2022-05-12 京东方科技集团股份有限公司 像素电路及驱动方法、显示面板、显示装置
CN113192458B (zh) 2021-01-12 2022-04-15 京东方科技集团股份有限公司 一种像素电路及其驱动方法、显示面板
CN112908258B (zh) * 2021-03-23 2022-10-21 武汉天马微电子有限公司 像素驱动电路、驱动方法、显示面板与显示装置
US12205542B2 (en) * 2021-07-30 2025-01-21 Chengdu Boe Optoelectronics Technology Co., Ltd. Pixel driving circuit and driving method thereof, and display panel
WO2023004813A1 (zh) * 2021-07-30 2023-02-02 京东方科技集团股份有限公司 像素电路、驱动方法和显示装置
KR20230036763A (ko) 2021-09-08 2023-03-15 삼성전자주식회사 디스플레이 패널 및 그 동작 방법
WO2023226013A1 (zh) 2022-05-27 2023-11-30 京东方科技集团股份有限公司 像素电路及其驱动方法、显示基板、显示装置
CN114927102B (zh) 2022-05-30 2023-12-05 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示面板、显示装置
CN117897759A (zh) * 2022-07-21 2024-04-16 京东方科技集团股份有限公司 像素驱动电路及驱动方法、显示面板、显示装置
CN115240582B (zh) * 2022-09-23 2022-12-13 昆山国显光电有限公司 像素电路及其驱动方法、显示面板
CN118197199A (zh) * 2022-12-12 2024-06-14 上海和辉光电股份有限公司 像素驱动电路、显示面板以及像素驱动电路的驱动方法
CN116434700B (zh) * 2023-03-31 2025-12-23 武汉天马微电子有限公司 显示面板及其驱动方法、显示装置
KR20240154448A (ko) * 2023-04-18 2024-10-25 캐논 가부시끼가이샤 전기광학소자를 구동하는 구동 트랜지스터를 갖는 표시 장치
KR20250037017A (ko) * 2023-09-07 2025-03-17 삼성디스플레이 주식회사 표시 장치 및 그의 구동 방법과, 표시 장치를 포함하는 전자 장치
CN120266194A (zh) * 2023-10-27 2025-07-04 京东方科技集团股份有限公司 显示基板和显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102568374A (zh) * 2010-12-10 2012-07-11 三星移动显示器株式会社 像素、包括像素的显示装置以及显示装置的驱动方法
CN105590955A (zh) * 2015-12-25 2016-05-18 昆山国显光电有限公司 像素电路及其驱动方法和有源矩阵有机发光显示器
CN107358918A (zh) * 2017-08-25 2017-11-17 京东方科技集团股份有限公司 一种像素电路及其驱动方法、显示装置
CN107452334A (zh) * 2017-08-30 2017-12-08 京东方科技集团股份有限公司 像素电路及其驱动方法、显示基板及其驱动方法、显示装置
CN107452331A (zh) * 2017-08-25 2017-12-08 京东方科技集团股份有限公司 一种像素电路及其驱动方法、显示装置
CN107767819A (zh) * 2017-09-28 2018-03-06 京东方科技集团股份有限公司 像素驱动电路及方法、显示装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009288767A (ja) * 2008-05-01 2009-12-10 Sony Corp 表示装置及びその駆動方法
KR20100009219A (ko) 2008-07-18 2010-01-27 삼성모바일디스플레이주식회사 화소 및 이를 이용한 유기전계발광 표시장치
KR101970545B1 (ko) * 2011-11-22 2019-04-22 엘지디스플레이 주식회사 유기발광다이오드 표시장치 및 그 구동방법
KR102159390B1 (ko) 2013-11-13 2020-09-24 삼성디스플레이 주식회사 유기전계발광 표시장치 및 그의 구동방법
KR102343143B1 (ko) 2014-11-12 2021-12-27 삼성디스플레이 주식회사 표시 장치 및 그의 구동 방법
CN104751799B (zh) * 2015-04-10 2016-12-14 京东方科技集团股份有限公司 像素电路及其驱动方法、显示装置
SG11201807505SA (en) 2016-03-28 2018-09-27 Apple Inc Light-emitting diode displays
KR102709910B1 (ko) * 2016-12-07 2024-09-27 삼성디스플레이 주식회사 표시장치 및 그의 구동방법

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102568374A (zh) * 2010-12-10 2012-07-11 三星移动显示器株式会社 像素、包括像素的显示装置以及显示装置的驱动方法
CN105590955A (zh) * 2015-12-25 2016-05-18 昆山国显光电有限公司 像素电路及其驱动方法和有源矩阵有机发光显示器
CN107358918A (zh) * 2017-08-25 2017-11-17 京东方科技集团股份有限公司 一种像素电路及其驱动方法、显示装置
CN107452331A (zh) * 2017-08-25 2017-12-08 京东方科技集团股份有限公司 一种像素电路及其驱动方法、显示装置
CN107452334A (zh) * 2017-08-30 2017-12-08 京东方科技集团股份有限公司 像素电路及其驱动方法、显示基板及其驱动方法、显示装置
CN107767819A (zh) * 2017-09-28 2018-03-06 京东方科技集团股份有限公司 像素驱动电路及方法、显示装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3739567A4

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12008956B2 (en) 2021-02-09 2024-06-11 Samsung Electronics Co., Ltd. Electronic device and method capable of reducing afterimage of display
US12293715B2 (en) * 2022-06-24 2025-05-06 Boe Technology Group Co., Ltd. Pixel circuit, driving method and display device

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