WO2019144305A1 - 电容检测电路、触摸检测装置和终端设备 - Google Patents

电容检测电路、触摸检测装置和终端设备 Download PDF

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Publication number
WO2019144305A1
WO2019144305A1 PCT/CN2018/073914 CN2018073914W WO2019144305A1 WO 2019144305 A1 WO2019144305 A1 WO 2019144305A1 CN 2018073914 W CN2018073914 W CN 2018073914W WO 2019144305 A1 WO2019144305 A1 WO 2019144305A1
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Prior art keywords
switch
capacitor
circuit
voltage
current source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2018/073914
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English (en)
French (fr)
Inventor
汪正锋
范硕
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen Goodix Technology Co Ltd
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Shenzhen Goodix Technology Co Ltd
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Filing date
Publication date
Application filed by Shenzhen Goodix Technology Co Ltd filed Critical Shenzhen Goodix Technology Co Ltd
Priority to CN201880002731.6A priority Critical patent/CN109496273B/zh
Priority to EP18877307.1A priority patent/EP3543668B1/en
Priority to PCT/CN2018/073914 priority patent/WO2019144305A1/zh
Priority to US16/420,146 priority patent/US10921938B2/en
Publication of WO2019144305A1 publication Critical patent/WO2019144305A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G01R27/26—Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants ; Measuring impedance or related variables
    • G01R27/2605—Measuring capacitance
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/0418—Control or interface arrangements specially adapted for digitisers for error correction or compensation, e.g. based on parallax, calibration or alignment
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/94—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the way in which the control signals are generated
    • H03K17/96—Touch switches
    • H03K17/962—Capacitive touch switches
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means

Definitions

  • the present application relates to the field of electronic technologies, and in particular, to a capacitance detecting circuit, a touch detecting device, and a terminal device.
  • Capacitive sensors are widely used in the field of human-computer interaction of electronic products. Specifically, a capacitance (or a basic capacitance) is formed between the detecting electrode and the ground. When a conductor (such as a finger) approaches or touches the detecting electrode, the detecting electrode The capacitance between the ground and the earth changes, and the user's operation is judged by detecting the change amount of the capacitance to obtain the information of the conductor approaching or touching the detecting electrode.
  • the performance of the capacitance detection circuit directly affects the user's operating experience. Therefore, improving the anti-interference ability of the capacitance detection circuit and improving the sensitivity of the capacitance detection circuit become an urgent problem to be solved.
  • the embodiment of the present application provides a capacitance detecting circuit, a touch detecting device, and a terminal device, which can improve the anti-interference ability of the capacitance detecting circuit and improve the sensitivity of the capacitance detecting circuit.
  • a capacitance detecting circuit for detecting a capacitance change amount of a detecting capacitor with respect to a base capacitance value, the capacitance detecting circuit including a first front end circuit, a second front end circuit, and a control circuit And a processing circuit for controlling the first front end circuit and the second front end circuit to cause the first front end circuit to be used to control a capacitance of the detecting capacitor under control of the control circuit
  • the signal is converted into a first voltage signal
  • the second front end circuit is configured to convert the capacitance signal of the detection capacitor into a second voltage signal under the control of the control circuit;
  • the first front end circuit comprises a first calibration capacitor, a first charge and discharge circuit and a first integration circuit
  • the detection capacitor is connected to the first charge and discharge circuit
  • the first calibration capacitor and the first a charge and discharge circuit connected to the first input end of the first integrating circuit
  • the first charging and discharging circuit is configured to charge and discharge the detecting capacitor and the first calibration capacitor connected to the first front end circuit, and the first integrating circuit is configured to pass the first calibration capacitor Converting a capacitance signal of the detecting capacitor into the first voltage signal;
  • the second front end circuit includes a second calibration capacitor, a second charge and discharge circuit, and a second integration circuit, and the second calibration capacitor is connected to the first input end of the second charge and discharge circuit and the second integrator ;
  • the second charging and discharging circuit is configured to charge and discharge the second calibration capacitor, and the second integrating circuit is configured to convert a capacitance signal of the detecting capacitor into the second voltage by using the second calibration capacitor signal;
  • the processing circuit is connected to the output ends of the first integrating circuit and the second integrating circuit, and configured to calculate the first voltage signal output by the first integrating circuit and the output of the second integrating circuit Deriving a differential signal of the second voltage signal, and determining a capacitance change amount of the detecting capacitor with respect to the base capacitance value according to the differential signal.
  • the capacitance detecting circuit converts the capacitance signals of the detecting capacitor into the first voltage signal and the second voltage signal respectively through the first front end circuit and the second front end circuit, and according to the differential signals of the first voltage signal and the second voltage signal, The amount of change in capacitance of the sense capacitor relative to the base capacitor value is determined.
  • the differential signal according to the first voltage signal and the second voltage signal may be The amount of capacitance change is obtained to improve the efficiency of capacitance detection.
  • the interference of the noise signal can be eliminated to some extent, the signal-to-noise ratio is improved, the anti-interference ability of the capacitance detecting circuit is improved, and the capacitance detecting circuit is further improved. Sensitivity.
  • the first integrating circuit converts the capacitance signal of the detecting capacitor into the first voltage signal, which is indirectly implemented by the first calibration capacitor.
  • the charge and discharge time of the first calibration capacitor is equal to the charge and discharge time of the detection capacitor, and the charge and discharge time of the detection capacitor is that the detection capacitor is discharged from a power supply voltage to a specific voltage or from zero to a specific voltage. The time elapsed.
  • the first charging and discharging circuit includes a first current source and a second current source
  • the second charging and discharging circuit includes a third current source
  • a ratio of a capacitance value of the first calibration capacitor to the base capacitance value is equal to a ratio of a current value of the second current source to a current value of the first current source
  • the third current source and the second calibration a capacitor connected to charge or discharge the second calibration capacitor
  • a ratio of a capacitance value of the second calibration capacitor to the base capacitance value being equal to a current value of the third current source and the first current source The ratio of the current values.
  • control circuit in the initialization phase, is configured to control the charge clearing on the first integrating circuit and the second integrating circuit;
  • the first charge and discharge circuit is configured to discharge the detection capacitor to a voltage of the detection capacitor equal to zero, and discharge the first calibration capacitor to a voltage of the first calibration capacitor equal to zero,
  • the second charging and discharging circuit is configured to charge the second calibration capacitor to a voltage of the second calibration capacitor equal to a power supply voltage;
  • the first current source is configured to charge the detection capacitor until a voltage of the detection capacitor reaches a first voltage, and the second current source is used at the first current source
  • the first calibration capacitor is charged during a period in which the detection capacitor is charged, the third current source being used to cause the second calibration capacitor during the period in which the first current source charges the detection capacitor Discharging the third current source;
  • the first integration circuit is configured to convert a capacitance signal of the first calibration capacitor into the first voltage signal
  • the second integration circuit is configured to convert a capacitance signal of the second calibration capacitor Converted into the second voltage signal, wherein an input voltage of a second input of the first integrating circuit is equal to the first voltage, and an input voltage of a second input of the second integrating circuit is equal to a second voltage.
  • the first charging and discharging circuit includes a first switch, a second switch, a third switch, and a fourth switch
  • the second charging and discharging circuit includes a fifth switch and a a sixth switch
  • the first integrating circuit includes a seventh switch
  • the second integrating circuit includes an eighth switch, wherein one end of the first switch is grounded and the other end is connected to the first end of the detecting capacitor
  • One end of the second switch is connected to the first current source and one end is connected to the first end of the detecting capacitor
  • one end of the third switch is connected to the second current source and the other end is connected to the first a first end of the calibration capacitor is connected
  • one end of the fourth switch is grounded and the other end is connected to the first end of the first calibration capacitor
  • the sixth switch has one end connected to the power source and the other end connected to the first end of the second calibration capacitor, one end of the seventh switch and the
  • the first switch, the fourth switch, and the sixth switch are closed in the first phase, and the second The switch, the third switch, the fifth switch, the seventh switch, and the eighth switch are turned off; in the second phase, the second switch, the third switch, and the first The fifth switch is closed, and the first switch, the fourth switch, the sixth switch, the seventh switch, and the eighth switch are turned off; in the third stage, the seventh switch and The eighth switch is closed, and the first switch, the second switch, the third switch, the fourth switch, the fifth switch, and the sixth switch are open.
  • the first voltage signal V OUTP output by the first integrating circuit and the second voltage signal V OUTN output by the second integrating circuit are respectively:
  • V R1 is a voltage value of the first voltage
  • V R2 is a voltage value of the second voltage
  • I 1 is the first current source a current value
  • I 2 is a current value of the second current source
  • I 3 is a current value of the third current source
  • C S1 is a capacitance value of the first integration capacitor
  • C S2 is a capacitance value of the second integration capacitor
  • ⁇ Cx is a capacitance change amount of the capacitance value of the detection capacitor with respect to the base capacitance value
  • V DD is a power supply voltage
  • N is a number of executions of the first stage to the third stage
  • N is a positive integer.
  • control circuit in the initialization phase, is configured to control the charge clearing on the first integrating circuit and the second integrating circuit;
  • the first charge and discharge circuit is configured to charge the detection capacitor to a voltage of the detection capacitor equal to a supply voltage, and to charge the first calibration capacitor to a voltage of the first calibration capacitor a power supply voltage, the second charge and discharge circuit is configured to discharge the second calibration capacitor to a voltage of the second calibration capacitor equal to zero;
  • the first current source is configured to discharge the detection capacitor to the first current source until the voltage of the detection capacitor reaches a first voltage
  • the second current source is used to Discharging the first calibration capacitor to the second current source during a period in which the detection capacitor discharges to the first current source, the third current source being used to pass the detection capacitor to the first current Charging the second calibration capacitor during the period of source discharge;
  • the first integration circuit is configured to convert a capacitance signal of the first calibration capacitor into the first voltage signal
  • the second integration circuit is configured to convert a capacitance signal of the second calibration capacitor Converted into the second voltage signal, wherein an input voltage of a second input of the first integrating circuit is equal to the first voltage, and an input voltage of a second input of the second integrating circuit is equal to a second voltage.
  • the first charging and discharging circuit includes a first switch, a second switch, a third switch, and a fourth switch
  • the second charging and discharging circuit includes a fifth switch and a a sixth switch
  • the first integrating circuit includes a seventh switch
  • the second integrating circuit includes an eighth switch
  • the first switch has one end connected to the power source and the other end connected to the first end of the detecting capacitor
  • One end of the second switch is connected to the first current source and one end is connected to the first end of the detecting capacitor
  • one end of the third switch is connected to the second current source and the other end is connected to the a first end of the first calibration capacitor is connected
  • one end of the fourth switch is connected to the power source and the other end is connected to the first end of the first calibration capacitor
  • one end of the fifth switch and the second calibration capacitor The first end is connected and the other end is connected to the third current source
  • one end of the sixth switch is grounded and the other end is connected to the first end of the second calibration capacitor
  • the first switch, the fourth switch, and the sixth switch are closed in the first phase, and the second The switch, the third switch, the fifth switch, the seventh switch, and the eighth switch are turned off; in the second phase, the second switch, the third switch, and the first The fifth switch is closed, and the first switch, the fourth switch, the sixth switch, the seventh switch, and the eighth switch are turned off; in the third stage, the seventh switch and The eighth switch is closed, and the first switch, the second switch, the third switch, the fourth switch, the fifth switch, and the sixth switch are open.
  • the first voltage signal V OUTP output by the first integrating circuit and the second voltage signal V OUTN output by the second integrating circuit are respectively:
  • V R1 is a voltage value of the first voltage
  • V R2 is a voltage value of the second voltage
  • I 1 is the first current source a current value
  • I 2 is a current value of the second current source
  • I 3 is a current value of the third current source
  • C S1 is a capacitance value of the first integration capacitor
  • C S2 is a capacitance value of the second integration capacitor
  • ⁇ Cx is a capacitance change amount of the capacitance value of the detection capacitor with respect to the base capacitance value
  • V DD is a power supply voltage
  • N is a number of executions of the first stage to the third stage
  • N is a positive integer.
  • the capacitance detecting circuit further includes a comparator, a first input end of the comparator is connected to the detecting capacitor, an output end of the comparator, and the control a circuit connected, a second input of the comparator for inputting the first voltage in a second phase, and when the comparator determines, in the second phase, that a voltage of the detecting capacitor reaches the first voltage
  • the control circuit controls the first charge and discharge circuit to stop charging and discharging the detection capacitor and the first calibration capacitor and to stop charging and discharging of the second calibration capacitor by the second charge and discharge circuit.
  • the first charging and discharging circuit includes a first current source, a second current source, and a fourth current source
  • the second charging and discharging circuit includes a third current source
  • the first current source and the fourth current source are both connected to the detection capacitor
  • the first current source is for charging the detection capacitor
  • the fourth current source is for making the detection capacitor Discharging
  • the second current source is coupled to the first calibration capacitor for charging the first calibration capacitor
  • a ratio of a capacitance value of the first calibration capacitor to the base capacitance value is equal to the second a ratio of a current value of the current source to a current value of the first current source
  • the third current source being coupled to the second calibration capacitor for discharging the second calibration capacitor
  • the second calibration capacitor The ratio of the capacitance value to the base capacitance value is equal to the ratio of the current value of the third current source to the current value of the fourth current source.
  • control circuit in an initialization phase, is configured to control charge clearing on the first integrating circuit and the second integrating circuit, and the first charging and discharging a circuit for clearing a charge on the first calibration capacitor and the detection capacitor;
  • the first current source is configured to charge the detection capacitor until a voltage of the detection capacitor reaches a first voltage, and the second current source is used at the first current source Charging the first calibration capacitor during a period in which the detection capacitor is charged;
  • the first integrating circuit is configured to convert a capacitance signal of the first calibration capacitor into the first voltage signal
  • the first charging and discharging circuit is configured to charge the detection capacitor to the Detecting a voltage of the capacitor equal to a power supply voltage
  • the second charge and discharge circuit is configured to charge the second calibration capacitor to a voltage of the second calibration capacitor equal to a power supply voltage, wherein a second input of the first integration circuit The input voltage of the terminal is equal to the first voltage
  • the fourth current source is configured to discharge the detection capacitor to the fourth current source until the voltage of the detection capacitor reaches a second voltage, and the third current source is used to Discharging the second calibration capacitor to the third current source during a period in which the detection capacitor discharges to the fourth current source;
  • the second integrating circuit is configured to convert a capacitance signal of the second calibration capacitor into the second voltage signal
  • the first charging and discharging circuit is configured to discharge the detection capacitor to the The voltage of the sense capacitor is equal to zero, and the voltage at which the first calibration capacitor is discharged to the first calibration capacitor is equal to zero, wherein the input voltage of the second input of the second integrating circuit is equal to the second voltage.
  • the first charging and discharging circuit includes a first switch, a second switch, a third switch, a fourth switch, a ninth switch, and a tenth switch
  • the second charging The discharge circuit includes a fifth switch and a sixth switch
  • the first integration circuit includes a seventh switch
  • the second integration circuit includes an eighth switch.
  • one end of the first switch is grounded and the other end is connected to the first end of the detecting capacitor
  • one end of the second switch is connected to the first current source and the other end is connected to the first end of the detecting capacitor
  • one end of the third switch is connected to the second current source and the other end is connected to the first end of the first calibration capacitor
  • one end of the fourth switch is grounded and the other end is opposite to the first a first end of the calibration capacitor is connected
  • one end of the ninth switch is connected to the fourth current source and the other end is connected to the first end of the detection capacitor
  • one end of the tenth switch is connected to the power source and the other end Connected to the first end of the detecting capacitor
  • one end of the fifth switch is connected to the first end of the second calibration capacitor and the other end is connected to the third current source
  • one end of the sixth switch is The power source is connected and the other end is connected to the first end of the second calibration capacitor
  • one end of the seventh switch is connected to the first end of the first calibration capacitor and the
  • the second switch and the third switch are closed in the first phase, and the first switch, the fourth a switch, the fifth switch, the sixth switch, the seventh switch, the eighth switch, the ninth switch, and the tenth switch being turned off; in the second phase, the sixth The switch, the seventh switch, and the tenth switch are closed, and the first switch, the second switch, the third switch, the fourth switch, the fifth switch, and the eighth The switch and the ninth switch are open; in the third phase, the fifth switch and the ninth switch are closed, and the first switch, the second switch, the third switch, The fourth switch, the sixth switch, the seventh switch, the eighth switch, and the tenth switch are turned off; in the fourth stage, the first switch, the fourth switch, and The eighth switch is closed, and the second switch, the third switch, the fifth switch, the sixth switch, the The seventh switch, the ninth switch, and the tenth switch are turned off.
  • the first voltage signal V OUTP output by the first integrating circuit and the second voltage signal V OUTN output by the second integrating circuit are respectively:
  • V R1 is a voltage value of the first voltage
  • V R2 is a voltage value of the second voltage
  • V DD is a power supply voltage
  • I 1 is a current value of the first current source
  • I 2 is the a current value of the second current source
  • I 3 is a current value of the third current source
  • I 4 is a current value of the fourth current source
  • C S1 is a capacitance value of the first integration capacitor
  • C S2 is a second value
  • ⁇ Cx is the capacitance change amount of the capacitance value of the detection capacitor with respect to the base capacitance value
  • N is the number of executions of the first stage to the third stage
  • N is an even number.
  • the embodiment of the present application provides a touch detection device, including the capacitance detection circuit according to the first aspect or any optional implementation of the first aspect, wherein the touch detection device is determined according to the capacitance detection circuit.
  • the amount of change in capacitance of the detection capacitor relative to the base capacitor determines a touch position of the user.
  • an embodiment of the present application provides a terminal device, including the touch detection device according to the second aspect.
  • FIG. 1 is a schematic circuit diagram of a conventional capacitance detecting circuit.
  • FIG. 2 is a schematic circuit diagram of a capacitance detecting circuit of an embodiment of the present application.
  • FIG. 3 is a schematic circuit diagram of a capacitance detecting circuit of one embodiment of the present application.
  • FIG. 4 is a logic timing diagram of a capacitance detecting circuit of one embodiment of the present application.
  • FIG. 5 is a schematic circuit diagram of a capacitance detecting circuit of another embodiment of the present application.
  • FIG. 6 is a logic timing diagram of a capacitance detecting circuit of another embodiment of the present application.
  • FIG. 7 is a schematic circuit diagram of a capacitance detecting circuit according to still another embodiment of the present application.
  • FIG. 8 is a logic timing diagram of a capacitance detecting circuit according to still another embodiment of the present application.
  • FIG. 9 is a schematic circuit diagram of a touch detection device according to an embodiment of the present application.
  • FIG. 1 For ease of understanding, a schematic diagram of one possible application scenario of the capacitance detecting circuit of the embodiment of the present application is described below with reference to FIG. 1 .
  • FIG. 1 shows a conventional capacitance detecting circuit 100 including an integrating circuit 110 and an analog to digital converter (ADC) circuit 120 connected to the integrating circuit 110.
  • a detection capacitor (or a detection capacitor) Cx has one end grounded and the other end connected to the input of the integrator 110.
  • the integrator 110 converts the capacitance signal of the detection capacitor Cx into a voltage signal, and outputs the voltage signal to the ADC circuit 120, which converts the voltage signal into a digital signal, thereby completing capacitance detection.
  • the capacitance value of the capacitor Cx is equal to the basic capacitance value Cx 0 (ie, the capacitance value when not operating), when the finger approaches or touches the detecting electrode corresponding to the detecting capacitor
  • the capacitance value of the capacitor Cx detected by the capacitance detecting circuit 100 changes, for example, becomes Cx 0 + ⁇ Cx. Therefore, by detecting the detected capacitance change amount ⁇ Cx of the detecting capacitor, it is possible to acquire information that the finger approaches or touches the detecting electrode.
  • the embodiment of the present application provides a capacitance detecting circuit, which includes two front end circuits for respectively converting a capacitance signal of a detecting capacitor into two voltage signals through respective connected calibration capacitors.
  • the differential signal obtained by differentially processing the two voltage signals determines the capacitance variation of the detection capacitor relative to the base capacitance value associated with the two calibration capacitors, thereby effectively improving the anti-interference capability of the capacitance detection circuit and improving the signal
  • the noise ratio improves the sensitivity of the capacitance detection circuit, thereby improving the user experience.
  • the capacitance detecting circuit of the embodiment of the present application can be applied to any scene, in particular, to a touch detecting device for detecting touch information of a user.
  • FIG. 2 is a schematic structural diagram of a capacitance detecting circuit 200 according to an embodiment of the present application.
  • the capacitance detecting circuit 200 is configured to detect a capacitance change amount ⁇ Cx of the detecting capacitor with respect to the base capacitance value Cx 0 , including the first front end circuit 210, the second front end circuit 220, the control circuit 230, and the processing circuit 240.
  • the control circuit 230 is configured to control the first front end circuit 210 and the second front end circuit 220, so that the first front end circuit 210 is used under the control of the control circuit 230 to convert the capacitance signal of the detecting capacitor into the first A voltage signal V OUTP , the second front end circuit 220 is used under the control of the control circuit 230 to convert the capacitance signal of the detection capacitor into the second voltage signal V OUTN .
  • the first front end circuit 210 includes a first calibration capacitor C C1 , a first charging and discharging circuit 211 , and a first integrating circuit 212 .
  • the detecting capacitor is connected to the first charging and discharging circuit 211
  • the first charging and discharging circuit 211 is connected to the first input end of the first integrating circuit 212.
  • the first charging and discharging circuit 211 is configured to charge and discharge the detecting capacitor and the first calibration capacitor C C1 connected to the first front end circuit 210
  • the first integrating circuit 212 is configured to pass the first calibration capacitor C C1 .
  • the capacitance signal of the detection capacitor is converted into the first voltage signal V OUTP .
  • the second front end circuit 220 includes a second calibration capacitor C C2 , a second charging and discharging circuit 221 , and a second integrating circuit 222 .
  • the second calibration capacitor C C2 and the second charging and discharging circuit 221 and the second integrating circuit 222 The first input is connected.
  • the second charging and discharging circuit 221 is configured to charge and discharge the second calibration capacitor C C2
  • the second integrating circuit 222 is configured to convert the capacitance signal of the detecting capacitor into the second voltage by using the second calibration capacitor C C2 .
  • Signal V OUTN is configured to convert the capacitance signal of the detecting capacitor into the second voltage by using the second calibration capacitor C C2 .
  • the processing circuit 240 is connected to the output ends of the first integrating circuit 212 and the second integrating circuit 222 for calculating the first voltage signal V OUTP output by the first integrating circuit 212 and the output of the second integrating circuit 222 And a differential signal of the second voltage signal V OUTN , and determining a capacitance change amount of the detection capacitor relative to the base capacitance value according to the differential signal.
  • the capacitance detecting circuit converts the capacitance signals of the detecting capacitor into the first voltage signal and the second voltage signal respectively through the first front end circuit and the second front end circuit, and according to the first voltage signal and the second voltage
  • the differential signal of the signal determines the amount of capacitance change of the sense capacitor relative to the base capacitor value.
  • the differential signal according to the first voltage signal and the second voltage signal may be The amount of capacitance change is obtained to improve the efficiency of capacitance detection.
  • the interference of the noise signal can be eliminated to some extent, the signal-to-noise ratio is improved, the anti-interference ability of the capacitance detecting circuit is improved, and the capacitance detecting circuit is further improved. Sensitivity.
  • the first integrating circuit 212 converts the capacitance signal of the detecting capacitor into the first voltage signal V OUTP , which is indirectly realized by the first calibration capacitor C C1 .
  • the capacitance change amount of the first calibration capacitor is related to the charge and discharge time of the detection capacitor C X .
  • the charge and discharge time of the first calibration capacitor C C1 is equal to the charge and discharge time of the detection capacitor C X .
  • the time elapsed from the charging of the first calibration capacitor C C1 from zero to the stop or the time elapsed from the start of the discharge of the first calibration capacitor C C1 from the power supply voltage V DD to the stop is equal to the detection capacitor C X being charged from zero to particular voltage is equal to the elapsed time or the detected discharge the capacitor C X by the power supply voltage V DD to the voltage experienced by a particular time.
  • the charging and discharging process of the detecting capacitor C X and the charging and discharging process of the first calibration capacitor C C1 are linked by controlling the charging and discharging time of the detecting capacitor C X , so that the first integrating circuit 212 passes the By integrating the calibration capacitor C C1 , the capacitance signal of the detection capacitor C X can be indirectly converted into the first voltage signal V OUTP .
  • the time elapsed from the charging of the second calibration capacitor C C2 from zero to the stop or the time elapsed after the second calibration capacitor C C2 is discharged from the power supply voltage V DD to the stop is equal to the detection capacitor C X being charged from zero to particular voltage is equal to the elapsed time or the detected discharge the capacitor C X by the power supply voltage V DD to the voltage experienced by a particular time.
  • the charging and discharging process of the detecting capacitor C X and the charging and discharging process of the second calibration capacitor C C2 are linked by controlling the charging and discharging time of the detecting capacitor C X , so that the first integrating circuit 212 passes the
  • the second calibration capacitor C C2 performs integration processing to indirectly convert the capacitance signal of the detection capacitor C X into the second voltage signal V OUTN .
  • the first integrating circuit 212 includes a first operational amplifier (OP) 1 and a first integrating capacitor C S1 connected in parallel with the first operational amplifier, that is, the first integrating capacitor C S1 is connected in the first Between the input and output of an operational amplifier.
  • the second integrating circuit 222 includes a second operational amplifier OP2 and a second integrating capacitor C S2 in parallel with the second operational amplifier.
  • the processing circuit 240 includes an analog-to-digital conversion circuit (ADC), and the analog-to-digital conversion circuit is connected to the output ends of the first integration circuit 212 and the second integration circuit 222.
  • the analog to digital conversion circuit is configured to convert the first voltage signal V OUTP output by the first integrating circuit 212 into a digital signal, and convert the second voltage signal V OUTN output by the second integrating circuit 222 into a digital signal.
  • the processing circuit 240 can determine the capacitance change amount ⁇ Cx of the detecting capacitor Cx by the digitized first voltage signal V OUTP and the digitized second voltage signal V OUTN .
  • the capacitance detecting circuit 200 of the embodiment of the present application can be specifically implemented by the following two types of circuit structures, which are respectively described below in conjunction with FIGS. 3 to 8. It should be understood that the examples shown in FIG. 3 to FIG. 8 are intended to help those skilled in the art to better understand the embodiments of the present application, and do not limit the scope of the embodiments of the present application. It will be obvious to those skilled in the art that various modifications and changes can be made without departing from the scope of the embodiments of the present application.
  • the first charging and discharging circuit 211 includes a first current source I 1 , a fourth current source I 4 and a second current source I 2
  • the second charging and discharging circuit 221 includes a third current source I 3 . .
  • the third current source I 3 and the second calibration capacitor C C2 is connected for causing the second calibration capacitor C C2 discharge, the capacitance value of the second calibration capacitor C C2 ratio with the base capacitance is equal to the value of C X0
  • control circuit 230 is configured to control the charge clearing on the first integrating circuit 212 and the second integrating circuit 222, and the first charging and discharging circuit 211 is configured to use the first calibration capacitor C C1 and The charge on capacitor C X is detected to be cleared.
  • the first integrating circuit 212 is configured to convert the capacitance signal of the first calibration capacitor C C1 into the first voltage signal V OUTP
  • the first charging and discharging circuit 211 is configured to charge the detection capacitor C X the detection voltage to capacitor C X is equal to the supply voltage V DD
  • the second charging and discharging circuit 221 for charging the calibration capacitor C C2 to a second voltage of the second calibration capacitor C C2 is equal to the supply voltage V DD
  • the input voltage of the second input of the first integrating circuit 212 in the second phase is equal to the first voltage V R1 .
  • the fourth current source I 4 is configured to discharge the detecting capacitor C X to the fourth current source I 4 until the voltage of the detecting capacitor C X reaches the second voltage V R2 , the third The current source I 3 is for discharging the second calibration capacitor C C2 to the third current source I 3 during a period t discharge during which the detection capacitor C X discharges to the fourth current source I 4 .
  • the second integrating circuit 222 is configured to convert the capacitance signal of the second calibration capacitor C C2 into the second voltage signal V OUTN
  • the first charging and discharging circuit 211 is configured to discharge the detecting capacitor C X
  • the voltage to the detection capacitor C X is equal to zero
  • the voltage of the first calibration capacitor C C1 to the first calibration capacitor C C1 is equal to zero, wherein the input voltage of the second input of the second integration circuit is in the fourth stage It is equal to the second voltage V R2 .
  • the capacitance detecting circuit further includes a comparator COMP, the first input end of the comparator, for example, the non-inverting input terminal is connected to the detecting capacitor C X , and the output end of the comparator is connected to the control circuit 230 , the comparison A second input of the device, such as an inverting input, is used to input the first voltage V R1 during the first phase and to input the second voltage V R2 during the third phase.
  • a comparator COMP the first input end of the comparator, for example, the non-inverting input terminal is connected to the detecting capacitor C X
  • the output end of the comparator is connected to the control circuit 230 , the comparison
  • a second input of the device such as an inverting input, is used to input the first voltage V R1 during the first phase and to input the second voltage V R2 during the third phase.
  • the control circuit 230 controls the first charge and discharge circuit 211 to stop charging and discharging the detection capacitor C X and the first calibration capacitor C C1 and to stop charging and discharging the second calibration capacitor C C2 by the second charge and discharge circuit 221 .
  • the capacitance detecting circuit further includes a switch group for controlling each capacitor to enter a different stage or enter a charging/discharging stage, such as a first charging and discharging.
  • the circuit 211 further includes a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a ninth switch S9, and a tenth switch S10.
  • the second charging and discharging circuit 221 includes a fifth switch S5 and a sixth switch S6,
  • the first integrating circuit 212 includes a seventh switch S7 and an eleventh switch S11
  • the second integrating circuit 222 includes an eighth switch S8 and a twelfth switch S12
  • the comparator includes a thirteenth switch S13 and a fourteenth switch S14.
  • one end of S1 is grounded and the other end is connected to the first end of the detecting capacitor C X
  • one end of S2 is connected to the first current source I 1 and the other end is connected to the first end of the detecting capacitor C X
  • one end of the S3 and the first end The two current sources I 2 are connected and the other end is connected to the first end of the first calibration capacitor C C1
  • one end of the S4 is grounded and the other end is connected to the first end of the first calibration capacitor C C1
  • one end of the S9 and the fourth current source I 4 is connected and the other end is connected to the first end of the detecting capacitor C X , one end of which is connected to the power source and the other end is connected to the first end of the detecting capacitor C X
  • one end of the S5 and the first end of the second calibration capacitor C C2 The other end is connected to the third current source I 3
  • one end of the S6 is connected to the power source and the other end is connected to the first end of the second calibration capacitor
  • S11 is connected in parallel with the first integrating capacitor C S1
  • one end of the S8 is connected to the first end of the second calibration capacitor C C2 and the other end is connected to the second integrating circuit
  • the first input of 222 is connected
  • S12 and second The integrating capacitor C S2 is connected in parallel
  • one end of S13 is connected to the second input end of the comparator and the voltage of the other end is equal to the first voltage V R1
  • one end of S14 is connected to the second input end of the comparator and the voltage of the other end is equal to the second voltage V R2 .
  • the second end of the sense capacitor C X , the second end of the first calibration capacitor C C1 , and the second end of the second calibration capacitor C C2 are both grounded.
  • the size of the first voltage V R1 and the second voltage V R2 are not limited in the embodiment of the present application. The following description is made by taking V R1 >V R2 as an example.
  • the control circuit 230 can control S11 to S13 to be closed, and S1 to S10 are turned off, so that the first capacitive integrator C S1 and the second capacitive integrator C S2 are completely
  • the discharge that is, the voltage discharged to the first capacitive integrator C S1 and the second capacitive integrator C S2 is equal to zero.
  • the inverting input of the comparator is connected to the voltage V R1 .
  • the voltage signal V OUTN V R2 .
  • the control circuit 230 can also control the switches S1, S4, and S13 to be closed, and S2, S3, S5 to S12, and S14 are turned off to make the capacitance C x to be measured and
  • the first calibration capacitor C c1 is completely discharged, that is, the voltage discharged to the capacitor C x to be tested and the first calibration capacitor C c1 is equal to zero.
  • the voltage signal V OUTN V R2 .
  • control circuit 230 can control the switching state of the switch, that is, close or open, thereby implementing the operations of the first stage to the third stage.
  • the following is the switching state shown in Table 1 and the logic timing diagram shown in FIG. The example specifically illustrates the operation of the capacitance detecting circuit.
  • the control circuit 230 can control the switches S1, S4 to S12, S14 to open, and the switches S2, S3, S13 to close.
  • the first current source I 1 charges the detection capacitor C X
  • the second current source I 2 charges the first calibration capacitor C C1 until the voltage of the detection capacitor C X reaches the first voltage V R1 .
  • the length of time during which the first current source I 1 charges the detection capacitor C X and the length of time that the second current source I 2 charges the first calibration capacitor C C1 are equal. It can also be said that charging of the first current source I 1 to the detecting capacitor C X and charging of the second current source I 2 to the first calibration capacitor C C1 are performed simultaneously.
  • the comparator Since the non-inverting input of the comparator is connected to the detecting capacitor C X and the input voltage of the inverting input is equal to the first voltage V R1 , when the voltage on the capacitor C X to be detected reaches the first voltage V R1 , the comparator The signal output from the output to the control circuit 230 is inverted so that the control circuit 230 knows when the detection capacitor C X is charged until its voltage reaches the first voltage V R1 and the voltage at the detection capacitor C X reaches the first voltage V At R1 , control S2, S3, and S13 are turned off and control switch S14 is closed, so that the input voltage of the inverting input terminal of the comparator is equal to the second voltage V R2 .
  • the non-inverting input terminal and the inverting input terminal of the comparator can be exchanged, and only the control module can detect that the signal state of the comparator output is reversed.
  • the length t charge of the period during which the first current source I 1 is charged to the detecting capacitor C X until the voltage of the detecting capacitor C X reaches the first voltage is:
  • C X is a capacitance value of the detection capacitor C X
  • I 1 is a current value of the first current source I 1 .
  • I 2 is the current value of the second current source I 2 .
  • a buffer phase may be included after the first phase, such as t3 to t4 shown in FIG.
  • control circuit 230 can control switches S1 S S13 to open, S 14 to close, and the amount of charge on each capacitor remains the same.
  • control circuit 230 can control the switches S1 to S5, S8 to S9, and S11 to S13 to be turned off, and S6, S7, S10, and S14 are closed.
  • a first integrating circuit 212 so that the first calibration capacitor C C1 is a capacitance signal into a first voltage signal V OUTP, a first charging and discharging circuit 211 detects the voltage charged to the capacitor C X C X detecting capacitor equal to the supply voltage V DD, The second charging and discharging circuit 221 charges the second calibration capacitor C C2 to the second calibration capacitor C C2 by a voltage equal to the power supply voltage V DD , wherein the input voltage of the second input terminal of the first integrating circuit 212 is in the second stage and the first The voltage V R1 is equal.
  • the first integrating circuit 212 starts the integration operation. Due to the virtual short characteristic of the first operational amplifier OP1, the upper plate of the first calibration capacitor C C1 and the left plate voltage of the first integrating capacitor are clamped. Bit to voltage V R1 . Due to the dummy nature of the first operational amplifier OP1, the charge stored on the first calibration capacitor C C1 at time t4 will be redistributed on the first calibration capacitor C C1 and the first integration capacitor C S1 .
  • the charge balance equation is:
  • C S1 is the capacitance value of the first integrating capacitor C S1 .
  • the first voltage signal V OUTP output by the first integrating circuit 212 can be calculated by the formula (3) as:
  • the detection capacitor Cx is charged to the detection capacitor Cx at a voltage equal to the supply voltage V DD
  • the second calibration capacitor C C2 is charged to the second calibration capacitor C C2 at a voltage equal to the supply voltage V DD .
  • the amount of charge stored on the detection capacitor Cx and the second calibration capacitor C C2 are respectively:
  • the control circuit 230 controls the switches S1 to S4, S6 to S8, S10 to S13 to be turned off, and the switches S5, S9, and S14. closure.
  • the fourth current source I 4 discharges the detection capacitor C X
  • the third current source I 3 discharges to the second calibration capacitor C C2 until the voltage of the detection capacitor C X reaches the second voltage V R2 .
  • the length of time during which the detection capacitor C X is discharged to the first current source I 4 is equal to the length of time that the third current source I 3 is discharged to the second calibration capacitor C C2 . It can also be said that the discharge of the detection capacitor C X to the first current source I 4 and the discharge of the third current source I 3 to the second calibration capacitor C C2 are simultaneously performed.
  • the non-inverting input of the comparator is connected to the detecting capacitor C X and the input voltage of the inverting input thereof has been switched to the second voltage V R2 , when the voltage on the capacitor C X to be detected reaches the second voltage V R2 , the comparison is made.
  • the output of the output of the device to the control circuit 230 is inverted, so that the control circuit 230 knows when the detection capacitor C X is discharged until its voltage reaches the second voltage V R2 , so that the voltage of the detection capacitor C X reaches the second
  • the control S5, S9, and S14 are turned off, and the S13 is closed, so that the input voltage of the inverting input terminal of the comparator is switched to the first voltage V R1 .
  • the detection capacitor C X is discharged to the fourth current source I 4 until the length t discharge of the period elapsed when the voltage of the detection capacitor C X reaches the second voltage V R2 is:
  • I 4 is the current value of the first current source I 4 .
  • a buffering stage such as t6 to t7 shown in FIG. 4 may be included after the third stage.
  • the control circuit 230 can control the switches S1 S S12, S 14 to be turned off, S 13 is closed, and the first voltage signal V OUTP and the second voltage signal V OUTN output by the first integrating circuit 212 remain unchanged.
  • the control circuit 230 can control the switches S2 to S3, S5 to S7, S9 to S12, and S14 to be turned off, and the switches S1, S4, S8, and S13 to be closed.
  • the second signal integrating circuit 222 the capacitance of the second calibration capacitor C C2 converted into a second voltage signal V OUTN, the first charge-discharge detection circuit 211 to discharge the capacitor C X C X detecting capacitor voltage is equal to zero, the first calibration capacitor The voltage discharged by C C1 to the first calibration capacitor C C1 is equal to zero, wherein the input voltage of the second input of the second integrating circuit is equal to the second voltage V R2 .
  • the second integrating circuit 222 starts the integration operation. Due to the virtual short characteristic of the second operational amplifier OP2, the left plate voltage of the upper plate of the second calibration capacitor C C2 and the second integrating capacitor C C2 Clamped to the second voltage V R2 . Due to the imaginary nature of the second operational amplifier OP2, the charge stored on the second calibrated capacitor C C2 at time t7 will be redistributed on the second calibrated capacitor C C2 and the second integrating capacitor C S2 .
  • the charge balance equation is:
  • C S2 is the capacitance value of the second integrating capacitor C S2 .
  • the second voltage signal V OUTN output by the second integrating circuit 222 can be calculated by the formula (7) as:
  • the detection capacitor Cx is discharged until the voltage of the detection capacitor Cx is equal to zero, the voltage of the first calibration capacitor C C1 discharged to the first calibration capacitor C C1 is equal to zero, and at time t5, the detection capacitor Cx and the first calibration capacitor C are The amount of charge stored on C1 is zero.
  • the first stage to the fourth stage may be repeatedly performed N times for the detection capacitor C X , that is, the times t2 to t8 in FIG. 4 are repeated N times, and N is an even number.
  • V R2 at this time, the first differential signal is obtained by performing a differential operation on the first voltage signal VOUTP outputted by the first integrating circuit 212 and the second voltage signal V OUTN outputted by the second integrating circuit 222 (for example, equal to V R1 -V R2 ) .
  • the first voltage signal V OUTP output by the circuit 212 and the second voltage signal V OUTN output by the second integrating circuit 222 are respectively:
  • the processing circuit 240 may perform differential processing on the first voltage signal V OUTP and the second voltage signal V OUTN based on the formula (11) and the formula (12) to obtain a second differential signal according to the first differential signal and the second differential signal.
  • the capacitance change amount ⁇ Cx of the detecting capacitor Cx can be determined.
  • the first voltage signal V OUTP and the second voltage signal V OUTN only reflect the capacitance due to the presence of the first calibration capacitor C C1 and the second calibration capacitor C C2 .
  • the variation of the amount of change ⁇ Cx does not involve the detection capacitor Cx (which can be understood as the base capacitance value Cx 0 of the detection capacitor Cx).
  • the first calibration capacitor C C1 cancels the contribution of the base capacitance value Cx 0 to the first voltage signal V OUTP output by the first integration circuit 212; the second calibration capacitor C C2 cancels the basis of the detection capacitor Cx
  • the charging is performed after the charging is taken as an example, that is, the detecting capacitor Cx and the first calibration capacitor C C1 are charged until the voltage of the detecting capacitor Cx reaches the first voltage V R1 , and then the detecting capacitor Cx and The second calibration capacitor C C2 is discharged until the voltage of the detection capacitor Cx reaches the second voltage V R2 .
  • the order of charging and discharging is not limited in the embodiment of the present application.
  • the control circuit 230 can control the detection capacitor Cx and the first calibration capacitor C C1 to be charged to the power supply voltage V DD ; in the first phase, the detection capacitor Cx and the first calibration capacitor C C1 are respectively connected to the respective connected current sources.
  • the first integrating capacitor is integrated, and the detecting capacitor Cx and the second calibration capacitor C C2 are charged to the power supply voltage V DD ;
  • the first current source I 1 and the third current source I 3 respectively charge the detection capacitor Cx and the second calibration capacitor C C2 until the voltage of the detection capacitor Cx reaches the first voltage V R1 ;
  • the two integrators integrate and charge the sense capacitor Cx and the first calibration capacitor C C1 to the supply voltage V DD .
  • one end of the first switch is connected to the detecting capacitor and the other end is connected to the power source.
  • One end of the fourth switch is connected to the first calibration capacitor C C1 and the other end is connected to the power source, and one end of the sixth switch is connected to the second calibration capacitor and the other end is connected.
  • One end is grounded.
  • the first charging and discharging circuit 211 includes a first current source I 1 and a second current source I 2
  • the second charging and discharging circuit 221 includes a third current source I 3 .
  • control circuit 230 is used to control the charge clearing on the first integrating circuit 212 and the second integrating circuit 222.
  • a first charging and discharging circuit 211 for detecting the capacitor voltage discharges to zero C X C X detecting capacitor, and a first calibration capacitor C C1 is discharged to a first calibration capacitor C C1 is equal to zero voltage, the second The voltage of the charge and discharge circuit 221 for charging the second calibration capacitor C C2 to the second calibration capacitor C C2 is equal to the power supply voltage V DD .
  • the first current source I 1 is used to charge the detection capacitor C X until the voltage of the detection capacitor C X reaches the first voltage V R1 , and the second current source I 2 is used at the first current source I
  • the first calibration capacitor C C1 is charged in a period t charge during which the detection capacitor C X is charged, and the third current source I 3 is used to make the second in the period t charge during which the first current source I 1 charges the detection capacitor C X
  • the calibration capacitor C C2 discharges the third current source I 3 .
  • the first integration circuit 212 is configured to convert the capacitance signal of the first calibration capacitor C C1 into a first voltage signal V OUTP
  • the second integration circuit 222 is configured to convert the capacitance signal of the second calibration capacitor C C2 into The second voltage signal V OUTN .
  • the input voltage of the second input terminal of the first integrating circuit 212 is equal to the first voltage V R1 in the third phase
  • the input voltage of the second input terminal of the second integrating circuit 222 is equal to the second voltage V R2 in the third phase.
  • the capacitance detecting circuit further includes a comparator (COMP), and the first input end (for example, the non-inverting input end) of the comparator is connected to the detecting capacitor C X , and the output end of the comparator is connected to the control circuit 230 .
  • a second input of the comparator eg, an inverting input
  • the control circuit 230 controls the first charging and discharging circuit 211 to stop charging the detecting capacitor C X and the first calibration capacitor C C1 . Discharging, and stopping charging and discharging of the second calibration capacitor C C2 by the second charging and discharging circuit 221 .
  • the capacitance detecting circuit may further include a switch group for controlling each capacitor to enter a different stage or enter a charging/discharging stage, such as a first charging and discharging.
  • the circuit 211 further includes a first switch S1, a second switch S2, a third switch S3 and a fourth switch S4, the second charging and discharging circuit 221 includes a fifth switch S5 and a sixth switch S6, and the first integrating circuit 212 includes a seventh switch S7 and the eleventh switch S11, the second integrating circuit 222 includes an eighth switch S8 and a twelfth switch S12.
  • one end of S1 is grounded and the other end is connected to the first end of the detecting capacitor C X
  • one end of S2 is connected to the first current source I 1 and one end is connected to the first end of the detecting capacitor C X
  • one end of the S3 and the second end The current source I 2 is connected and the other end is connected to the first end of the first calibration capacitor C C1
  • one end of the S4 is grounded and the other end is connected to the first end of the first calibration capacitor C C1
  • one end of the S7 and the first calibration capacitor C The first end of C1 is connected and the other end is connected to the first input end of the first integrating circuit 212
  • S11 is connected in parallel with the first integrating capacitor C S1
  • one end of S5 is connected to the first end of the second calibration capacitor C C2 and the other end is connected
  • one end of the S6 is connected to the power source and the other end is connected to the first end of the second calibration capacitor C C2 , one
  • control circuit 230 can control the switching state of the above switch, that is, close or open, thereby implementing the operations of the first stage to the third stage.
  • the following is the switching state shown in Table 2 and the logic timing diagram shown in FIG. The example specifically illustrates the operation of the capacitance detecting circuit.
  • the control circuit 230 controls S1, S4, and S6 to be closed in the first phase, and S2, S3, S5, S7, S8, S11, and S12 are turned off.
  • the voltage of the detection capacitor C X discharged to the detection capacitor C X is equal to zero
  • the voltage of the first calibration capacitor C C1 discharged to the first calibration capacitor C C1 is equal to zero
  • the voltage of the second calibration capacitor C C2 to the second calibration capacitor C C2 is equal to voltage.
  • the amount of charge stored on the capacitor C X to be tested, the first calibration capacitor C C1 , and the second calibration capacitor C C2 are respectively:
  • the charging phase (t charge ) in the second phase (e.g., the t2 to t3 phases shown in Fig. 6)
  • S2, S3, and S5 are closed, and S1, S4, S6 to S8, S11, and S12 are turned off.
  • the first current source I 1 charges the detection capacitor C X
  • the second current source I 2 charges the first calibration capacitor C C1
  • the second calibration capacitor C C2 discharges the third current source I 3 until the detection capacitor C X
  • the length of time during which the first current source I 1 charges the detection capacitor C X the length of time that the second current source I 2 charges the first calibration capacitor C C1 , and the second calibration capacitor C C2 discharges the third current source I 3 The duration is equal. It can also be said that the first current source I 1 charges the detection capacitor C X , the second current source I 2 charges the first calibration capacitor C C1 , and the second calibration capacitor C C2 discharges the third current source I 3 simultaneously. .
  • the non-inverting input of the comparator is connected to the detecting capacitor C X and the input voltage of the inverting input is equal to the first voltage V R1 , when the voltage on the capacitor C X to be detected reaches the first voltage V R1 (second stage) At the end of the period), the output of the comparator outputs a signal to the control circuit 230, so that the control circuit 230 knows that the detection capacitor C X has been charged until its voltage reaches the first voltage V R1 , thereby controlling S2 and S3. Disconnected from S5.
  • the non-inverting input terminal and the inverting input terminal of the comparator can be exchanged, and only the control module 230 can detect that the signal state of the comparator output is reversed.
  • C X is a capacitance value of the detection capacitor C X
  • I 1 is a current value of the first current source I 1 .
  • I 2 is the current value of the second current source I 2
  • I 3 is the current value of the third current source I 3
  • C C1 is the capacitance value of the first calibration capacitor C C2
  • V DD is the power supply voltage
  • a buffer phase (for example, t3 to t4 shown in FIG. 6) may be included after the second phase.
  • control circuit 230 can control all switches to remain off, and the amount of charge on each capacitor remains the same.
  • the control circuit 230 controls the switches S7 and S8 to be closed, and S1 to S6, S11 and S12 are turned off.
  • the first integrating circuit 212 converts the capacitance signal of the first calibration capacitor C C1 into the first voltage signal V OUTP
  • the second integrating circuit 222 converts the capacitance signal of the second calibration capacitor C C2 into the second voltage signal V OUTN .
  • the input voltage of the second input terminal of the first integrating circuit 212 is equal to the first voltage V R1
  • the input voltage of the second input terminal of the second integrating circuit 222 is equal to the second voltage V R2 .
  • the first integrating circuit 212 and the second integrating circuit 222 start to perform an integrating operation. Due to the virtual short characteristic of the first operational amplifier OP1, the first calibration capacitor C S1 has its upper plate of C C1 and The left plate voltage of the first integrating capacitor C S1 is clamped to the voltage V R1 . Due to the dummy nature of the first operational amplifier OP1, the charge stored on the first calibration capacitor C C1 at time t4 will be redistributed on the first calibration capacitor C C1 and the first integration capacitor C S1 .
  • the charge balance equation is:
  • C S1 is the capacitance value of the first integrating capacitor C S1 .
  • the first voltage signal V OUTP output by the first integrating circuit 212 can be calculated by the formula (4) as:
  • C S2 is the capacitance value of the second integrating capacitor C S2 .
  • the second voltage signal V OUTN output by the second integrating circuit 222 can be calculated by the formula (18) as:
  • a buffer phase (such as t5 to t6 shown in FIG. 6) may be included after the third phase, in which the control circuit 230 can control all The switches are kept in an off state, and the first voltage signal V OUTP output by the first integrating circuit 212 and the second voltage signal V OUTN output by the second integrating circuit 222 remain unchanged.
  • the first voltage signal V OUTP output by the first integrating circuit 212 and the second voltage signal V OUTN output by the second integrating circuit 222 are respectively:
  • the first voltage signal V OUTP output by the integrating circuit 212 and the second voltage signal V OUTN output by the second integrating circuit 222 are respectively:
  • the processing circuit 240 may perform differential processing on the first voltage signal V OUTP and the second voltage signal V OUTN based on the formula (22) and the formula (23) to obtain a second differential signal according to the first differential signal and the second differential signal.
  • the capacitance change amount ⁇ Cx of the detecting capacitor Cx can be determined.
  • the first differential signal is zero, so the second differential signal can directly reflect the capacitance change amount ⁇ Cx, that is, the capacitance change amount ⁇ Cx can be obtained directly through the second differential signal.
  • the change situation does not need to consider the first differential signal.
  • control circuit 230 is used to control the charge clearing on the first integrating circuit 212 and the second integrating circuit 222.
  • a first charging and discharging circuit 211 to charge the capacitor to a voltage detector detecting the capacitor C X is equal to the supply voltage V DD
  • the first calibration capacitor C C1 is charged to a first calibration capacitor C C1 is equal to the supply voltage
  • the voltage V DD the voltage of the second charging and discharging circuit 221 for discharging the second calibration capacitor C C2 to the second calibration capacitor C C2 is equal to zero.
  • the first current source I 1 is for discharging the detection capacitor C X to the first current source I 1 until the stop of detecting the voltage of the capacitor C X reaches the first voltage
  • the second current source I 2 is used for Discharging the first calibration capacitor C C1 to the second current source I 2 during a period t charge during which the detection capacitor C X discharges to the first current source I 1
  • the third current source I 3 being used to first in the detection capacitor C X
  • the second calibration capacitor C C2 is charged during a period t charge during which the current source I 1 is discharged.
  • the first integration circuit 212 is configured to convert the capacitance signal of the first calibration capacitor C C1 into a first voltage signal
  • the second integration circuit 222 is configured to convert the capacitance signal of the second calibration capacitor C C2 into a second a voltage signal, wherein an input voltage of the second input terminal of the first integrating circuit 212 is equal to the first voltage V R1 in the third phase, and an input voltage of the second input terminal of the second integrating circuit 222 is in the third phase and the second voltage V R2 is equal.
  • the capacitance detecting circuit further includes a comparator COMP, the first input end (for example, the non-inverting input end) of the comparator is connected to the detecting capacitor C X , and the output end of the comparator is connected to the control circuit 230 , the comparator A second input (eg, an inverting input) is used to input the first voltage V R1 in the second phase.
  • a comparator COMP the first input end (for example, the non-inverting input end) of the comparator is connected to the detecting capacitor C X
  • the output end of the comparator is connected to the control circuit 230
  • the comparator A second input eg, an inverting input
  • the control circuit 230 controls the first charging and discharging circuit 211 to stop charging and discharging the detecting capacitor C X and the first calibration capacitor C C1 . And stopping charging and discharging of the second calibration capacitor C C2 by the second charging and discharging circuit 221 .
  • the capacitance detecting circuit further includes a switch group for controlling each capacitor to enter a different stage or enter a charging/discharging phase, such as a first charging and discharging circuit.
  • the 211 further includes a first switch S1, a second switch S2, a third switch S3, and a fourth switch S4.
  • the second charging and discharging circuit 221 includes a fifth switch S5 and a sixth switch S6, and the first integrating circuit 212 includes a seventh switch S7.
  • the eleventh switch S11, the second integrating circuit 222 includes an eighth switch S8 and a twelfth switch S12.
  • one end of S1 is connected to the power source and the other end is connected to the first end of the detecting capacitor C X
  • one end of S2 is connected to the first current source I 1 and one end is connected to the first end of the detecting capacitor C X
  • one end of the S3 is
  • the second current source I 2 is connected and the other end is connected to the first end of the first calibration capacitor C C1
  • one end of the S4 is connected to the power source and the other end is connected to the first end of the first calibration capacitor C C1
  • the first end of the second calibration capacitor C C2 is connected and the other end is connected to the third current source I 3 , one end of which is grounded and the other end is connected to the first end of the second calibration capacitor C C2
  • one end of the S7 and the first calibration capacitor The first end of C C1 is connected and the other end is connected to the first input end of the first integrating circuit 212, S11 is connected in parallel with the first end of the first integrating capacitor
  • the control circuit 230 may control the closing of S11 and S12 to completely discharge the first integrating capacitor C S1 and the second capacitive integrator C S2 , that is, discharging.
  • the voltages to the first integrating capacitor C S1 and the second capacitive integrator C S2 are equal to zero.
  • the voltage signal V OUTN V R2 .
  • control circuit 230 can control the switching state of the above switch, that is, to close or open, thereby realizing the operations of the first stage to the third stage.
  • the following is the switching state shown in Table 3 and the logic timing diagram shown in FIG. The example specifically illustrates the operation of the capacitance detecting circuit.
  • control circuit 230 controls S1, S4, and S6 to close in the first phase, while S2, S3, S5, S7, S8, S11, and S12 are open.
  • the voltage of the detection capacitor C X is charged to the detection capacitor C X is equal to the power supply voltage V DD
  • the voltage of the first calibration capacitor C C1 is charged to the first calibration capacitor C C1 is equal to the power supply voltage V DD
  • the second calibration capacitor C C2 is discharged to the first
  • the voltage of the second calibration capacitor C C2 is equal to zero.
  • the amount of charge stored on the capacitor C X to be tested, the calibration capacitor C C1 , and the calibration capacitor C C2 are respectively:
  • the discharge phase (t discharge ) in the second phase (e.g., the t2 to t3 phases shown in Fig. 8), S2, S3, and S5 are closed, and S1, S4, S6 to S8, S11, and S12 are turned off.
  • the detection capacitor C X is discharged to the first current source I 1
  • the first calibration capacitor C C1 is discharged to the second current source I 2
  • the third current source I 3 is charged to the second calibration capacitor C C2 until the detection capacitor C X
  • the length of time during which the detection capacitor C X is discharged to the first current source I 1 the length of time that the first calibration capacitor C C1 is discharged to the second current source I 2 , and the third current source I 3 charge the second calibration capacitor C C2 .
  • the duration is equal. It can also be said that the detection capacitor C X is discharged to the first current source I 1 , the first calibration capacitor is discharged to C C1 to the second current source I 2 , and the third current source I 3 is charged to the second calibration capacitor C C2 . ongoing.
  • the output of the comparator outputs a signal to the control circuit 230, so that the control circuit 230 knows when the detection capacitor C X is charged until its voltage reaches the first voltage V R1 , thereby detecting the capacitor C Controls S2, S3, and S5 are turned off when the voltage of X reaches the first voltage V R1 .
  • the non-inverting input terminal and the inverting input terminal of the comparator can be exchanged, and only the control module 230 can detect that the signal state of the comparator output is reversed.
  • Elapsed time reaches the first stop voltage detector capacitor C X to a first current source I 1 and discharge the capacitor C X until the detection of the length of the period t discharge is:
  • C X is a capacitance value of the detection capacitor C X
  • I 1 is a current value of the first current source I 1 .
  • I 2 is the current value of the second current source I 2
  • I 3 is the current value of the third current source I 3
  • C C2 is the capacitance value of the second calibration capacitor C C2 .
  • a buffer phase (such as t3 to t4 shown in FIG. 8) may be included after the second phase.
  • control circuit 230 can control all switches to remain off, and the amount of charge on each capacitor remains the same.
  • the control circuit 230 controls the switches S7 and S8 to be closed, and S1 to S6, S11 and S12 are turned off.
  • the first integrating circuit 212 converts the capacitance signal of the first calibration capacitor C C1 into the first voltage signal V OUTP
  • the second integrating circuit 222 converts the capacitance signal of the second calibration capacitor C C2 into the second voltage signal V OUTN .
  • the input voltage of the second input terminal of the first integrating circuit 212 is equal to the first voltage V R1
  • the input voltage of the second input terminal of the second integrating circuit 222 is equal to the second voltage V R2 .
  • the first integrating circuit 212 and the second integrating circuit 222 start to perform an integrating operation. Due to the virtual short characteristic of the first operational amplifier OP1, the upper plate and the first integral of the first calibration capacitor C C1 are started. The left plate voltage of the capacitor is clamped to voltage V R1 . Due to the dummy nature of the first operational amplifier OP1, the charge stored on the first calibration capacitor C C1 at time t4 will be redistributed on the first calibration capacitor C C1 and the first integration capacitor C S1 .
  • the charge balance equation is:
  • C S1 is the capacitance value of the first integrating capacitor C S1 .
  • the first voltage signal V OUTP output by the first integrating circuit 212 can be calculated by the formula (27) as:
  • C S2 is the capacitance value of the second integrating capacitor C S2 .
  • the second voltage signal V OUTN output by the second integrating circuit 222 can be calculated as:
  • a buffer phase (such as t5 to t6 shown in FIG. 8) may be included after the third phase, in which the control circuit 230 can control all The switches are kept in an off state, and the first voltage signal V OUTP and the second voltage signal V OUTN output by the first integrating circuit 212 remain unchanged.
  • the first differential signal is obtained by performing a differential operation between the first voltage signal V OUTP outputted by the 212 and the second voltage signal V OUTN output by the second integrating circuit 222.
  • the first voltage signal V OUTP output by the integrating circuit 212 and the second voltage signal V OUTN output by the second integrating circuit 222 are respectively:
  • the processing circuit 240 may perform differential processing on the first voltage signal V OUTP and the second voltage signal V OUTN based on the formula (33) and the formula (34) to obtain a second differential signal according to the first differential signal and the second differential signal.
  • the capacitance change amount ⁇ Cx of the detecting capacitor Cx can be determined.
  • the first differential signal is zero, so the second differential signal can directly reflect the capacitance change amount ⁇ Cx, that is, the capacitance change amount ⁇ Cx can be obtained directly through the second differential signal. There is no need to consider the first differential signal.
  • the capacitance detecting circuit performs different actions.
  • the foregoing divisions for different stages are merely examples, and other divisions may be performed depending on the actions performed by the capacitance detection circuit at different stages.
  • type 2 includes an initialization phase, a first phase, a second phase, and a third phase, and the initialization phase in type 2 needs to clear the charge on the two integration circuits;
  • Initialization phase, first phase, second phase, third phase, and fourth phase, and the initialization phase in type 1 requires not only zeroing the charge on the two integrating circuits, but also the first calibration capacitor C C1 and detection
  • the capacitor C X is fully discharged, so that the first current source I 1 and the second current source I 2 respectively charge the detection capacitor C X and the first calibration capacitor C C1 for the same period of time until the voltage of the detection capacitor C X is Zero reaches the first voltage V R1 .
  • the first calibration capacitor C C1 and the detection capacitor C X need to be completely discharged, so that the first current source I 1 and the second current source I 2
  • the detection capacitor C X and the first calibration capacitor C C1 are respectively charged for the same length of time in the immediately subsequent first stage until the voltage of the detection capacitor C X reaches the first voltage V R1 from zero.
  • the initialization stage of type 1 only needs to include the charge on the two integration circuits. The process of clearing.
  • the process of completely discharging the detection capacitor C X and the first calibration capacitor C C1 in the first stage of the type 2 is divided into the third stage, that is, after the two integrators perform the integration operation in the third stage,
  • the detection capacitor C X and the first calibration capacitor C C1 are fully discharged, and the type 2 initialization phase not only needs to clear the charge on the two integration circuits, but also needs to completely complete the detection capacitor C X and the first calibration capacitor C C1 . Discharge.
  • FIG. 9 is a schematic circuit diagram of a touch detection device 900 according to an embodiment of the present application.
  • the touch detecting device 900 includes a capacitance detecting circuit 200 as shown in FIG. 2.
  • the touch detection device 900 can determine the touch position of the user according to the capacitance change amount of the detection capacitor relative to the base capacitor determined by the capacitance detection circuit.
  • the detection capacitor is a capacitor formed by the electrodes of one touch channel and the ground.
  • the embodiment of the present application provides a terminal device, including the touch detection device 900 shown in FIG. 9.
  • the terminal device 900 may be a mobile phone, a tablet computer, a notebook computer, a desktop computer, an in-vehicle electronic device, or a wearable smart device.

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Abstract

一种能够提高抗干扰能力，提升检测灵敏度的电容检测电路（200），包括第一前端电路（210）、第二前端电路（220）、控制电路（230）和处理电路（240），控制电路（230）用于控制第一前端电路（210）和第二前端电路（220），以使第一前端电路（210）用于通过所连接的第一校准电容器（CC1）将检测电容器（CX）的电容信号转化为第一电压信号（VOUTP），并使第二前端电路（220）用于通过所连接的第二校准电容器（CC2）将检测电容器（CX）的电容信号转化为第二电压信号（V OUTN），处理电路（230）与第一积分电路（212）和第二积分电路（222）的输出端相连，用于计算第一积分电路（212）输出的第一电压信号（VOUTP）和第二积分电路（222）输出的第二电压信号（VOUTN）的差分信号，并根据差分信号确定检测电容器（CX）相对于基础电容值的电容变化量。

Description

电容检测电路、触摸检测装置和终端设备 技术领域
本申请涉及电子技术领域，尤其涉及一种电容检测电路、触摸检测装置和终端设备。
背景技术
电容型传感器广泛应用于电子产品的人机交互领域，具体地，在检测电极和大地之间会形成电容(或者称基础电容)，当有导体(例如手指)靠近或触摸检测电极时，检测电极和大地之间的电容会发生变化，通过检测电容的变化量获取导体靠近或触摸检测电极的信息，从而判断用户的操作。电容检测电路的性能直接影响用户的操作体验，因此，提高电容检测电路的抗干扰能力，提升电容检测电路的灵敏度成为急需解决的问题。
发明内容
本申请实施例提供了一种电容检测电路、触摸检测装置和终端设备，能够提高电容检测电路的抗干扰能力，提升电容检测电路的灵敏度。
第一方面，提供了一种电容检测电路，所述电容检测电路用于检测检测电容器相对于基础电容值的电容变化量，所述电容检测电路包括第一前端电路、第二前端电路、控制电路和处理电路，所述控制电路用于控制所述第一前端电路和所述第二前端电路，以使所述第一前端电路在所述控制电路的控制下用于将所述检测电容器的电容信号转化为第一电压信号，所述第二前端电路在所述控制电路的控制下用于将所述检测电容器的电容信号转化为第二电压信号；
其中，所述第一前端电路包括第一校准电容器、第一充放电电路和第一积分电路，所述检测电容器与所述第一充放电电路相连，所述第一校准电容器与所述第一充放电电路和所述第一积分电路的第一输入端相连；
所述第一充放电电路用于对所述第一前端电路所连接的所述检测电容器和所述第一校准电容器进行充放电，所述第一积分电路用于通过所述第一校准电容器将所述检测电容器的电容信号转化为所述第一电压信号；
所述第二前端电路包括第二校准电容器、第二充放电电路和第二积分电 路，所述第二校准电容器与所述第二充放电电路和所述第二积分器的第一输入端相连；
所述第二充放电电路用于对所述第二校准电容器进行充放电，所述第二积分电路用于通过所述第二校准电容器将所述检测电容器的电容信号转化为所述第二电压信号；
所述处理电路与所述第一积分电路和所述第二积分电路的输出端相连，用于计算所述第一积分电路输出的所述第一电压信号和所述第二积分电路输出的所述第二电压信号的差分信号，并根据所述差分信号确定所述检测电容器相对于基础电容值的电容变化量。
因此，该电容检测电路通过第一前端电路和第二前端电路将检测电容器的电容信号分别转化为第一电压信号和第二电压信号，并根据第一电压信号和第二电压信号的差分信号，确定检测电容器相对于基础电容值的电容变化量。一方面，由于第一电压信号和第二电压信号中由基础电容值贡献的信号量已经被第一校准电容器和第二校准电容器抵消，因此可以根据第一电压信号和第二电压信号的差分信号获得电容变化量从而提高电容检测的效率。另一方面，由于对第一电压信号和第二电压信号进行了差分处理，因此能够一定程度消除噪声信号的干扰，提高信噪比，从而提高电容检测电路的抗干扰能力，进一步提升电容检测电路的灵敏度。
这里，所述第一积分电路将所述检测电容器的电容信号转化为所述第一电压信号，是间接地通过第一校准电容器实现的。其中，所述第一校准电容器的充放电时间与所述检测电容器的充放电时间相等，所述检测电容器的充放电时间为所述检测电容器由电源电压放电至特定电压或者由零充电至特定电压所经历的时间。
可选地，在一种可能的实现方式中，所述第一充放电电路包括第一电流源和第二电流源，所述第二充放电电路包括第三电流源，其中，所述第一电流源与所述检测电容器相连，用于对所述检测电容器充电或放电，所述第二电流源与所述第一校准电容器相连，用于对所述第一校准电容器充电或放电，所述第一校准电容器的电容值与所述基础电容值的比值等于所述第二电流源的电流值与所述第一电流源的电流值的比值，所述第三电流源与所述第二校准电容器相连，用于对所述第二校准电容器充电或放电，所述第二校准电容器的电容值与所述基础电容值的比值等于所述第三电流源的电流值与 所述第一电流源的电流值的比值。
可选地，在一种可能的实现方式中，在初始化阶段，所述控制电路用于控制所述第一积分电路和所述第二积分电路上的电荷清零；
在第一阶段，所述第一充放电电路用于使所述检测电容器放电至所述检测电容器的电压等于零，以及将所述第一校准电容器放电至所述第一校准电容器的电压等于零，所述第二充放电电路用于向所述第二校准电容器充电至所述第二校准电容器的电压等于电源电压；
在第二阶段，所述第一电流源用于向所述检测电容器充电，直至所述检测电容器的电压达到第一电压时停止，所述第二电流源用于在所述第一电流源向所述检测电容器充电的时段内对所述第一校准电容器充电，所述第三电流源用于在所述第一电流源向所述检测电容器充电的所述时段内使所述第二校准电容器对所述第三电流源放电；
在第三阶段，所述第一积分电路用于将所述第一校准电容器的电容信号转化为所述第一电压信号，所述第二积分电路用于将所述第二校准电容器的电容信号转化为所述第二电压信号，其中，所述第一积分电路的第二输入端的输入电压等于所述第一电压，所述第二积分电路的第二输入端的输入电压等于第二电压。
可选地，在一种可能的实现方式中，所述第一充放电电路包括第一开关、第二开关、第三开关和第四开关，所述第二充放电电路包括第五开关和第六开关，所述第一积分电路包括第七开关，所述第二积分电路包括第八开关，其中，所述第一开关的一端接地且另一端与所述检测电容器的第一端相连，所述第二开关的一端与所述第一电流源相连且一端与所述检测电容器的第一端相连，所述第三开关的一端与所述第二电流源相连且另一端与所述第一校准电容器的第一端相连，所述第四开关的一端接地且另一端与所述第一校准电容器的第一端相连，所述第五开关的一端与所述第二校准电容器的第一端相连且另一端与所述第三电流源相连，所述第六开关的一端与电源相连且另一端与所述第二校准电容器的第一端相连，所述第七开关的一端与所述第一校准电容器的第一端相连且另一端与所述第一积分电路的第一输入端相连，所述第八开关的一端与所述第二校准电容器的第一端相连且另一端与所述第二积分电路的第一输入端相连，所述检测电容器的第二端、所述第一校准电容器的第二端、和所述第二校准电容器的第二端均接地。
可选地，在一种可能的实现方式中，在所述第一阶段，所述第一开关、所述第四开关和所述第六开关在所述第一阶段闭合，而所述第二开关、所述第三开关、所述第五开关、所述第七开关和所述第八开关断开；在所述第二阶段，所述第二开关、所述第三开关和所述第五开关闭合，而所述第一开关、所述第四开关、所述第六开关、所述第七开关和所述第八开关断开；在所述第三阶段，所述第七开关和所述第八开关闭合，而所述第一开关、所述第二开关、所述第三开关、所述第四开关、所述第五开关和所述第六开关断开。
可选地，在一种可能的实现方式中，所述第一积分电路输出的所述第一电压信号V OUTP和所述第二积分电路输出的所述第二电压信号V OUTN分别为：
Figure PCTCN2018073914-appb-000001
其中，V R1＝V R2＝V DD/2＝V CM，V R1为所述第一电压的电压值，V R2为所述第二电压的电压值，I 1为所述第一电流源的电流值，I 2为所述第二电流源的电流值，I 3为所述第三电流源的电流值，C S1为第一积分电容器的电容值，C S2为第二积分电容器的电容值，ΔCx为所述检测电容器的电容值相对于所述基础电容值的电容变化量，V DD为电源电压，N为所述第一阶段至所述第三阶段的执行次数，N为正整数。
可选地，在一种可能的实现方式中，在初始化阶段，所述控制电路用于控制所述第一积分电路和所述第二积分电路上的电荷清零；
在第一阶段，所述第一充放电电路用于将所述检测电容器充电至所述检测电容器的电压等于电源电压，以及将所述第一校准电容器充电至所述第一校准电容器的电压等于电源电压，所述第二充放电电路用于使所述第二校准电容器放电至所述第二校准电容器的电压等于零；
在第二阶段，所述第一电流源用于使所述检测电容器向所述第一电流源放电，直至所述检测电容器的电压达到第一电压时停止，所述第二电流源用于在所述检测电容器向所述第一电流源放电的时段内使所述第一校准电容器向所述第二电流源放电，所述第三电流源用于在所述检测电容器向所述第一电流源放电的所述时段内对所述第二校准电容器充电；
在第三阶段，所述第一积分电路用于将所述第一校准电容器的电容信号转化为所述第一电压信号，所述第二积分电路用于将所述第二校准电容器的 电容信号转化为所述第二电压信号，其中，所述第一积分电路的第二输入端的输入电压等于所述第一电压，所述第二积分电路的第二输入端的输入电压等于第二电压。
可选地，在一种可能的实现方式中，所述第一充放电电路包括第一开关、第二开关、第三开关和第四开关，所述第二充放电电路包括第五开关和第六开关，所述第一积分电路包括第七开关，所述第二积分电路包括第八开关，其中，所述第一开关的一端与电源相连且另一端与所述检测电容器的第一端相连，所述第二开关的一端与所述第一电流源相连且一端与所述检测电容器的第一端相连，所述第三开关的一端与所述第二电流源相连且另一端与所述第一校准电容器的第一端相连，所述第四开关的一端与电源相连且另一端与所述第一校准电容器的第一端相连，所述第五开关的一端与所述第二校准电容器的第一端相连且另一端与所述第三电流源相连，所述第六开关的一端接地且另一端与所述第二校准电容器的第一端相连，所述第七开关的一端与所述第一校准电容器的第一端相连且另一端与所述第一积分电路的第一输入端相连，所述第八开关的一端与所述第二校准电容器的第一端相连且另一端与所述第二积分电路的第一输入端相连，所述检测电容器的第二端、所述第一校准电容器的第二端、和所述第二校准电容器的第二端均接地。
可选地，在一种可能的实现方式中，在所述第一阶段，所述第一开关、所述第四开关和所述第六开关在所述第一阶段闭合，而所述第二开关、所述第三开关、所述第五开关、所述第七开关和所述第八开关断开；在所述第二阶段，所述第二开关、所述第三开关和所述第五开关闭合，而所述第一开关、所述第四开关、所述第六开关、所述第七开关和所述第八开关断开；在所述第三阶段，所述第七开关和所述第八开关闭合，而所述第一开关、所述第二开关、所述第三开关、所述第四开关、所述第五开关和所述第六开关断开。
可选地，在一种可能的实现方式中，所述第一积分电路输出的所述第一电压信号V OUTP和所述第二积分电路输出的所述第二电压信号V OUTN分别为：
Figure PCTCN2018073914-appb-000002
其中，V R1＝V R2＝V DD/2＝V CM，V R1为所述第一电压的电压值，V R2为所述第二电压的电压值，I 1为所述第一电流源的电流值，I 2为所述第二电流源 的电流值，I 3为所述第三电流源的电流值，C S1为第一积分电容器的电容值，C S2为第二积分电容器的电容值，ΔCx为所述检测电容器的电容值相对于所述基础电容值的电容变化量，V DD为电源电压，N为所述第一阶段至所述第三阶段的执行次数，N为正整数。
可选地，在一种可能的实现方式中，所述电容检测电路还包括比较器，所述比较器的第一输入端与所述检测电容器相连，所述比较器的输出端与所述控制电路相连，所述比较器的第二输入端用于在第二阶段输入所述第一电压，当所述比较器在所述第二阶段判断所述检测电容器的电压达到所述第一电压时，所述控制电路控制所述第一充放电电路停止对所述检测电容器和所述第一校准电容器的充放电以及停止所述第二充放电电路对所述第二校准电容器的充放电。
可选地，在一种可能的实现方式中，所述第一充放电电路包括第一电流源、第二电流源和第四电流源，所述第二充放电电路包括第三电流源，其中，所述第一电流源和所述第四电流源均与所述检测电容器相连，所述第一电流源用于对所述检测电容器充电，所述第四电流源用于使所述检测电容器放电，所述第二电流源与所述第一校准电容器相连，用于对所述第一校准电容器充电，所述第一校准电容器的电容值与所述基础电容值的比值等于所述第二电流源的电流值与所述第一电流源的电流值的比值，所述第三电流源与所述第二校准电容器相连，用于对所述第二校准电容器放电，所述第二校准电容器的电容值与所述基础电容值的比值等于所述第三电流源的电流值与所述第四电流源的电流值的比值。
可选地，在一种可能的实现方式中，在初始化阶段，所述控制电路用于控制所述第一积分电路和所述第二积分电路上的电荷清零，且所述第一充放电电路用于将所述第一校准电容器和所述检测电容器上的电荷清零；
在第一阶段，所述第一电流源用于对所述检测电容器充电，直至所述检测电容器的电压达到第一电压时停止，所述第二电流源用于在所述第一电流源向所述检测电容器充电的时段内对所述第一校准电容器充电；
在第二阶段，所述第一积分电路用于将所述第一校准电容器的电容信号转化为所述第一电压信号，所述第一充放电电路用于将所述检测电容器充电至所述检测电容器的电压等于电源电压，所述第二充放电电路用于将所述第二校准电容器充电至所述第二校准电容器的电压等于电源电压，其中，所述 第一积分电路的第二输入端的输入电压等于所述第一电压；
在第三阶段，所述第四电流源用于使所述检测电容器向所述第四电流源放电，直至所述检测电容器的电压达到第二电压时停止，所述第三电流源用于在所述检测电容器向所述第四电流源放电的时段内使所述第二校准电容器对所述第三电流源放电；
在第四阶段，所述第二积分电路用于将所述第二校准电容器的电容信号转化为所述第二电压信号，所述第一充放电电路用于将所述检测电容器放电至所述检测电容器的电压等于零，以及将所述第一校准电容器放电至所述第一校准电容器的电压等于零，其中，所述第二积分电路的第二输入端的输入电压等于所述第二电压。
可选地，在一种可能的实现方式中，所述第一充放电电路包括第一开关、第二开关、第三开关、第四开关、第九开关和第十开关，所述第二充放电电路包括第五开关和第六开关，所述第一积分电路包括第七开关，所述第二积分电路包括第八开关。其中，所述第一开关的一端接地且另一端与所述检测电容器的第一端相连，所述第二开关的一端与所述第一电流源相连且另一端与所述检测电容器的第一端相连，所述第三开关的一端与所述第二电流源相连且另一端与所述第一校准电容器的第一端相连，所述第四开关的一端接地且另一端与所述第一校准电容器的第一端相连，所述第九开关的一端与所述第四电流源相连且另一端与所述检测电容器的第一端相连，所述第十开关的一端与电源相连且另一端与所述检测电容器的第一端相连，所述第五开关的一端与所述第二校准电容器的第一端相连且另一端与所述第三电流源相连，所述第六开关的一端与电源相连且另一端与所述第二校准电容器的第一端相连，所述第七开关的一端与所述第一校准电容器的第一端相连且另一端与所述第一积分电路的第一输入端相连，所述第八开关的一端与所述第二校准电容器的第一端相连且另一端与所述第二积分电路的第一输入端相连，所述检测电容器的第二端、所述第一校准电容器的第二端、和所述第二校准电容器的第二端均接地。
可选地，在一种可能的实现方式中，在所述第一阶段，所述第二开关和所述第三开关在所述第一阶段闭合，而所述第一开关、所述第四开关、所述第五开关、所述第六开关、所述第七开关、所述第八开关所述第九开关和所述第十开关断开；在所述第二阶段，所述第六开关、所述第七开关和所述第 十开关闭合，而所述第一开关、所述第二开关、所述第三开关、所述第四开关、所述第五开关、所述第八开关和所述第九开关断开；在所述第三阶段，所述第五开关和所述第九开关闭合，而所述第一开关、所述第二开关、所述第三开关、所述第四开关、所述第六开关、所述第七开关、所述第八开关和所述第十开关断开；在所述第四阶段，所述第一开关、所述第四开关和所述第八开关闭合，而所述第二开关、所述第三开关、所述第五开关、所述第六开关、所述第七开关、所述第九开关和所述第十开关断开。
可选地，在一种可能的实现方式中，所述第一积分电路输出的所述第一电压信号V OUTP和所述第二积分电路输出的所述第二电压信号V OUTN分别为：
Figure PCTCN2018073914-appb-000003
其中，V R1为所述第一电压的电压值，V R2为所述第二电压的电压值，V DD为电源电压，I 1为所述第一电流源的电流值，I 2为所述第二电流源的电流值，I 3为所述第三电流源的电流值，I 4为所述第四电流源的电流值，C S1为第一积分电容器的电容值，C S2为第二积分电容器的电容值，ΔCx为所述检测电容器的电容值相对于所述基础电容值的电容变化量，N为所述第一阶段至所述第三阶段的执行次数，N为偶数。
第二方面，本申请实施例提供了一种触摸检测装置，包括第一方面或第一方面任一可选实现方式所述的电容检测电路，所述触摸检测装置根据所述电容检测电路所确定的所述检测电容器相对于所述基础电容器的电容变化量，确定用户的触摸位置。
第三方面，本申请实施例提供了一种终端设备，包括如第二方面所述的触摸检测装置。
附图说明
图1是现有的电容检测电路的示意性电路图。
图2是本申请实施例的电容检测电路的示意性电路图。
图3是本申请一个实施例的电容检测电路的示意性电路图。
图4是本申请一个实施例的电容检测电路的逻辑时序图。
图5是本申请另一个实施例的电容检测电路的示意性电路图。
图6是本申请另一个实施例的电容检测电路的逻辑时序图。
图7是本申请再一个实施例的电容检测电路的示意性电路图。
图8是本申请再一个实施例的电容检测电路的逻辑时序图。
图9是本申请实施例的一种触摸检测装置的示意性电路图。
具体实施方式
下面将结合附图，对本申请实施例中的技术方案进行描述。
为了便于理解，下面结合图1描述本申请实施例的电容检测电路的一种可能的应用场景的示意图。
图1示出了一种常用的电容检测电路100，该电容检测电路100包括积分电路110和与所述积分电路110相连的模数转换电路(Analog to Digital Converter，ADC)电路120。检测电容器(或称待测电容器，detection capacitor)Cx的一端接地，另一端与该积分器110的输入端相连。该积分器110将该检测电容器Cx的电容信号转换成电压信号，并将该电压信号输出至ADC电路120，ADC电路120将该电压信号转换成数字信号，从而完成电容检测。当没有手指触摸或者靠近触摸该检测电容器对应的检测电极时，该电容器Cx的电容值等于基础电容值Cx 0(即非操作时的电容值)，当手指靠近或触摸该检测电容器对应的检测电极时，该电容检测电路100检测到的电容器Cx的电容值会发生变化，例如变为Cx 0+△Cx。因此，通过检测到的该检测电容器的电容变化量△Cx，就可以获取手指靠近或触摸检测电极的信息。
本申请实施例提供了一种电容检测电路，该电容检测电路包括两个前端电路，这两个前端电路分别用于通过各自连接的校准电容器将检测电容器的电容信号转化为两个电压信号，通过对两个电压信号进行差分处理得到的差分信号，确定与两个校准电容器相关的该检测电容器相对于基础电容值的电容变化量，从而能够有效地提高电容检测电路的抗干扰能力，提高了信噪比，提升电容检测电路的灵敏度，从而提升了用户体验。
应理解，本申请实施例的电容检测电路可以应用于任何场景中，特别地，适用于触摸检测装置，以用来对用户的触摸信息进行检测。
以下，结合图2至图8详细说明根据本申请实施例的电容检测电路。
图2是本申请实施例的电容检测电路200的示意性结构图。
如图2所示，该电容检测电路200用于检测检测电容器相对于基础电容 值Cx 0的电容变化量△Cx，包括第一前端电路210、第二前端电路220、控制电路230和处理电路240，该控制电路230用于控制该第一前端电路210和该第二前端电路220，以使该第一前端电路210在该控制电路230的控制下用于将该检测电容器的电容信号转化为第一电压信号V OUTP，该第二前端电路220在该控制电路230的控制下用于将该检测电容器的电容信号转化为第二电压信号V OUTN。
其中，该第一前端电路210包括第一校准电容器C C1、第一充放电电路211和第一积分电路212，该检测电容器与该第一充放电电路211相连，该第一校准电容器C C1与该第一充放电电路211和该第一积分电路212的第一输入端相连。
该第一充放电电路211用于对该第一前端电路210所连接的该检测电容器和该第一校准电容器C C1进行充放电，该第一积分电路212用于通过该第一校准电容器C C1将该检测电容器的电容信号转化为该第一电压信号V OUTP。
该第二前端电路220包括第二校准电容器C C2、第二充放电电路221和第二积分电路222，该第二校准电容器C C2与该第二充放电电路221和该第二积分电路222的第一输入端相连。
该第二充放电电路221用于对该第二校准电容器C C2进行充放电，该第二积分电路222用于通过该第二校准电容器C C2将该检测电容器的电容信号转化为该第二电压信号V OUTN。
该处理电路240与该第一积分电路212和该第二积分电路222的输出端相连，用于计算该第一积分电路212输出的该第一电压信号V OUTP和该第二积分电路222输出的该第二电压信号V OUTN的差分信号，并根据该差分信号确定该检测电容器相对于基础电容值的电容变化量。
在本申请实施例中，该电容检测电路通过第一前端电路和第二前端电路将检测电容器的电容信号分别转化为第一电压信号和第二电压信号，并根据第一电压信号和第二电压信号的差分信号，确定检测电容器相对于基础电容值的电容变化量。一方面，由于第一电压信号和第二电压信号中由基础电容值贡献的信号量已经被第一校准电容器和第二校准电容器抵消，因此可以根据第一电压信号和第二电压信号的差分信号获得电容变化量从而提高电容检测的效率。另一方面，由于对第一电压信号和第二电压信号进行了差分处理，因此能够一定程度消除噪声信号的干扰，提高信噪比，从而提高电容检 测电路的抗干扰能力，进一步提升电容检测电路的灵敏度。
应理解，该第一积分电路212将该检测电容器的电容信号转化为该第一电压信号V OUTP，是间接地通过第一校准电容器C C1实现的。其中，第一校准电容器的电容变化量与检测电容器C X的充放电时间相关。具体地，第一校准电容器C C1的充放电时间与检测电容器C X的充放电时间相等。例如，该第一校准电容器C C1从零开始充电至停止所经过的时间或者该第一校准电容器C C1从电源电压V DD开始放电至停止所经过的时间，等于检测电容器C X由零充电至特定电压所经历的时间或者等于检测电容器C X由电源电压V DD放电至特定电压所经历的时间。因此，检测电容器C X的充放电过程与第一校准电容器C C1的充放电过程之间就通过控制检测电容器C X的该充放电时间而联系在一起，从而第一积分电路212通过对该第一校准电容器C C1进行积分处理，就可以间接地实现将检测电容器C X的电容信号转化为该第一电压信号V OUTP。
同样，该第二校准电容器C C2从零开始充电至停止所经过的时间或者该第二校准电容器C C2从电源电压V DD开始放电至停止所经过的时间，等于检测电容器C X由零充电至特定电压所经历的时间或者等于检测电容器C X由电源电压V DD放电至特定电压所经历的时间。因此，检测电容器C X的充放电过程与第二校准电容器C C2的充放电过程之间就通过控制检测电容器C X的该充放电时间而联系在一起，从而第一积分电路212通过对该第二校准电容器C C2进行积分处理，就可以间接地实现将检测电容器C X的电容信号转化为该第二电压信号V OUTN。
可选地，该第一积分电路212包括第一运算放大器(Operational Amplifier，OP)1以及与该第一运算放大器并联的第一积分电容器C S1，也就是第一积分电容器C S1跨接在第一运算放大器的输入端与输出端之间。该第二积分电路222包括第二运算放大器OP2以及与该第二运算放大器并联的第二积分电容器C S2。
可选地，该处理电路240中包括模数转换电路(Analog-to-Dgital Conversion，ADC)，该模数转换电路与该第一积分电路212和该第二积分电路222的输出端相连，该模数转换电路用于将该第一积分电路212输出的该第一电压信号V OUTP转化为数字信号，以及将该第二积分电路222输出的该第二电压信号V OUTN转化为数字信号。从而该处理电路240可以通过数字化 的第一电压信号V OUTP和数字化的该第二电压信号V OUTN确定检测电容器Cx的电容变化量△Cx。
本申请实施例的电容检测电路200可以具体通过以下两种类型的电路结构来实现，下面结合图3至图8分别进行描述。应理解，图3至图8所示的例子是为了帮助本领域技术人员更好地理解本申请实施例，而非要限制本申请实施例的范围。本领域技术人员根据所给出的图3至图8，显然可以进行各种等价的修改或变化，这样的修改或变化也落入本申请实施例的范围内。
类型1
请参考图3，可选地，第一充放电电路211包括第一电流源I 1、第四电流源I 4和第二电流源I 2，第二充放电电路221包括第三电流源I 3。
其中，该第一电流源I 1和该第四电流源I 4均与该检测电容器C X相连，该第一电流源I 1用于对该检测电容器C X充电，该第四电流源I 4用于使该检测电容器C X放电，该第二电流源I 2与该第一校准电容器C C1相连，用于对该第一校准电容器C C1充电，该第一校准电容器C C1的电容值与该基础电容值C X0的比值等于该第二电流源I 2的电流值与该第一电流源I 1的电流值的比值，即C C1/C X0＝I 2/I 1。
该第三电流源I 3与该第二校准电容器C C2相连，用于使该第二校准电容器C C2放电，该第二校准电容器C C2的电容值与该基础电容值C X0的比值等于该第三电流源I 3的电流值与该第四电流源I 4的电流值的比值，即C C1/C X0＝I 3/I 1。
在初始化阶段，所述控制电路230用于控制所述第一积分电路212和所述第二积分电路222上的电荷清零，且第一充放电电路211用于将第一校准电容器C C1和检测电容器C X上的电荷清零。
在第一阶段，该第一电流源I 1用于对该检测电容器C X充电，直至该检测电容器C X的电压达到第一电压V R1时停止，该第二电流源I 2用于在该第一电流源I 1向该检测电容器C X充电的时段t charge内对该第一校准电容器C C1充电。
在第二阶段，该第一积分电路212用于将该第一校准电容器C C1的电容信号转化为该第一电压信号V OUTP，该第一充放电电路211用于将该检测电容器C X充电至该检测电容器C X的电压等于电源电压V DD，该第二充放电电路221用于将该第二校准电容器C C2充电至该第二校准电容器C C2的电压等 于电源电压V DD，其中，该第一积分电路212的第二输入端在第二阶段的输入电压与该第一电压V R1相等。
在第三阶段，该第四电流源I 4用于使该检测电容器C X向该第四电流源I 4放电，直至该检测电容器C X的电压达到第二电压V R2时停止，该第三电流源I 3用于在该检测电容器C X向该第四电流源I 4放电的时段t discharge内使该第二校准电容器C C2对该第三电流源I 3放电。
在第四阶段，该第二积分电路222用于将该第二校准电容器C C2的电容信号转化为该第二电压信号V OUTN，该第一充放电电路211用于将该检测电容器C X放电至该检测电容器C X的电压等于零，以及将该第一校准电容器C C1放电至该第一校准电容器C C1的电压等于零，其中，该第二积分电路的第二输入端的输入电压在第四阶段与该第二电压V R2相等。
可选地，该电容检测电路还包括比较器COMP，该比较器的第一输入端，例如同相输入端与该检测电容器C X相连，该比较器的输出端与该控制电路230相连，该比较器的第二输入端，例如反相输入端用于在该第一阶段输入该第一电压V R1，以及在该第三阶段输入该第二电压V R2。
其中，当该比较器在该第一阶段判断该检测电容器C X的电压达到该第一电压V R1或者在该第三阶段判断该检测电容器C X的电压达到该第二电压V R2时，该控制电路230控制该第一充放电电路211停止对该检测电容器C X和该第一校准电容器C C1的充放电以及停止该第二充放电电路221对该第二校准电容器C C2的充放电。
下面以图3为例进行说明，在前述关于图3的电路结构描述基础之上，电容检测电路还包括用于控制各电容进入不同阶段或者进入充电/放电阶段的开关组，比如第一充放电电路211进一步包括第一开关S1、第二开关S2、第三开关S3、第四开关S4、第九开关S9和第十开关S10第二充放电电路221包括第五开关S5和第六开关S6，第一积分电路212包括第七开关S7和第十一开关S11，第二积分电路222包括第八开关S8和第十二开关S12，比较器包括第十三开关S13和第十四开关S14。
其中，S1的一端接地且另一端与检测电容器C X的第一端相连，S2的一端与第一电流源I 1相连且另一端与检测电容器C X的第一端相连，S3的一端与第二电流源I 2相连且另一端与第一校准电容器C C1的第一端相连，S4的一端接地且另一端与第一校准电容器C C1的第一端相连，S9的一端与第四电流 源I 4相连且另一端与检测电容器C X的第一端相连，S10的一端与电源相连且另一端与检测电容器C X的第一端相连，S5的一端与第二校准电容器C C2的第一端相连且另一端与第三电流源I 3相连，S6的一端与电源相连且另一端与第二校准电容器C C2的第一端相连，S7的一端与第一校准电容器C C1的第一端相连且另一端与第一积分电路212的第一输入端相连，S11与第一积分电容器C S1并联，S8的一端与第二校准电容器C C2的第一端相连且另一端与第二积分电路222的第一输入端相连，S12与第二积分电容器C S2并联，S13一端与比较器的第二输入端相连且另一端的电压等于第一电压V R1，S14一端与比较器的第二输入端相连且另一端的电压等于第二电压V R2。检测电容器C X的第二端、所述第一校准电容器C C1的第二端、和所述第二校准电容器C C2的第二端均接地。
本申请实施例对第一电压V R1和第二电压V R2的大小不作限定，下面仅以V R1＞V R2为例进行描述。
在初始化阶段中，例如图4所示的t0至t1阶段，控制电路230可以控制S11～S13闭合，S1～S10断开，以使第一电容积分器C S1和第二电容积分器C S2完全放电，即放电至第一电容积分器C S1和第二电容积分器C S2的电压等于零。同时，比较器的反相输入端接电压V R1。此时，第一积分电容器C S1、第二积分电容器C S2上存储的电荷量为零，第一积分电路212输出的第一电压信号V OUTP＝V R1，第二积分电路222输出的第二电压信号V OUTN＝V R2。当第一积分电容器C S1和第二积分电容器C S2上存储的电荷量达到上限时，可以重新控制S11和S12闭合以清零第一电容积分器C S1和第二电容积分器C S2上存储的电荷。
在初始化阶段中，例如图4所示的t1至t2阶段，控制电路230还可以控制开关S1、S4、S13闭合，S2、S3、S5～S12、S14断开，以使待测电容C x和第一校准电容C c1完全放电，即放电至待测电容C x和第一校准电容C c1的电压等于零。在t2时刻，待测电容C x和第一校准电容C c1上存储的电荷量为零，第一积分电路212输出的第一电压信号V OUTP＝V R1，第二积分电路222输出的第二电压信号V OUTN＝V R2。
接下来，控制电路230可以控制上述开关的开关状态即闭合或断开，从而实现第一阶段至第三阶段的操作，下面以表一所示的开关状态和图4所示的逻辑时序图为例具体说明该电容检测电路的工作过程。
表一
Figure PCTCN2018073914-appb-000004
在第一阶段，例如图4所示的t2至t3阶段，控制电路230可以控制开关S1、S4～S12、S14断开，开关S2、S3、S13闭合。从而第一电流源I 1对检测电容器C X充电，第二电流源I 2向第一校准电容器C C1充电，直至检测电容器C X的电压达到第一电压V R1时停止。应注意，第一电流源I 1向检测电容器C X充电的时长与第二电流源I 2向第一校准电容器C C1充电的时长是相等的。也可以说，第一电流源I 1向检测电容器C X充电与第二电流源I 2向第一校准电容器C C1充电是同时进行的。
由于比较器的同相输入端与检测电容器C X相连，而其反相输入端的输入电压等于第一电压V R1，因此当待检测电容C X上的电压达到第一电压V R1时，比较器的输出端向控制电路230输出的信号会发生翻转，从而使控制电路230知道检测电容器C X何时被充电至其电压达到第一电压V R1，并在检测电容器C X的电压达到第一电压V R1时控制S2、S3、S13断开并控制开关S14闭合，使比较器反相输入端的输入电压等于第二电压V R2。
其中，本申请实施例中，比较器的同相输入端和反相输入端可以调换，只需控制模块能够检测到比较器输出的信号状态翻转即可。
第一电流源I 1向检测电容器C X充电直至检测电容器C X的电压达到第一电压时停止所经过的该时段的长度t charge为：
Figure PCTCN2018073914-appb-000005
其中，C X为检测电容器C X的电容值，I 1为第一电流源I 1的电流值。
在t3时刻，第一校准电容C C1上存储的电荷量为：
Figure PCTCN2018073914-appb-000006
其中，t charge需满足条件t charge≤t3-t2。I 2为第二电流源I 2的电流值。
可选地，为了避免开关频繁切换导致的电荷泄露，在该第一阶段之后还可以包括一个缓冲阶段，例如图4中所示的t3至t4。在该缓冲阶段，控制电路230可以控制开关S1～S13断开、S14闭合，各个电容器上的电荷量均保持不变。
在第二阶段，例如图4所示的t4至t5阶段，控制电路230可以控制开关S1～S5、S8～S9、S11～S13断开，S6、S7、S10、S14闭合。从而第一积分电路212将第一校准电容器C C1的电容信号转化为第一电压信号V OUTP，第一充放电电路211将检测电容器C X充电至检测电容器C X的电压等于电源电压V DD，第二充放电电路221将第二校准电容器C C2充电至第二校准电容器C C2的电压等于电源电压V DD，其中，第一积分电路212的第二输入端的输入电压在第二阶段与第一电压V R1相等。
具体地，S7闭合后，第一积分电路212开始进行积分操作，由于第一运算放大器OP1的虚短特性，第一校准电容器C C1的上极板和第一积分电容器的左极板电压被钳位到电压V R1。由于第一运算放大器OP1的虚断特性，在t4时刻第一校准电容器C C1上存储的电荷将会在第一校准电容器C C1以及第一积分电容器C S1上进行重新分配，电荷平衡方程为：
Figure PCTCN2018073914-appb-000007
其中，C S1为第一积分电容器C S1的电容值。
通过公式(3)可计算第一积分电路212输出的第一电压信号V OUTP为：
Figure PCTCN2018073914-appb-000008
S6和S10闭合后，检测电容器Cx被充电至检测电容器Cx的电压等于电源电压V DD，第二校准电容器C C2被充电至第二校准电容器C C2的电压等于电源电压V DD。在t5时刻，检测电容器Cx和第二校准电容器C C2上存储的电荷量分别为：
Q CX,t4～t5＝C XV DD；Q CC2,t4～t5＝C C2V DD；
在第三阶段(例如图4所示的t5至t6阶段)内的放电时段(t discharge)，控制电路230控制开关S1～S4、S6～S8、S10～S13断开，开关S5、S9、S14闭合。第四电流源I 4使检测电容器C X放电，第三电流源I 3向第二校准电容器C C2放电，直至检测电容器C X的电压达到第二电压V R2时停止。应注意，检测电容器C X向第一电流源I 4放电的时长与第三电流源I 3向第二校准电容器C C2放电的时长是相等的。也可以说，检测电容器C X向第一电流源I 4放电与第三电流源I 3向第二校准电容器C C2放电充电是同时进行的。
由于比较器的同相输入端与检测电容器C X相连，而其反相输入端的输入电压已经切换至第二电压V R2，因此当待检测电容C X上的电压达到第二电压V R2时，比较器的输出端向控制电路230输出的信号会发生翻转，从而使控制电路230知道检测电容器C X何时被放电至其电压达到第二电压V R2，从而在检测电容器C X的电压达到第二电压V R2时(第三阶段的末尾时段)控制S5、S9、S14断开，S13闭合，使比较器反相输入端的输入电压再切换为第一电压V R1。
检测电容器C X向第四电流源I 4放电直至检测电容器C X的电压达到第二电压V R2时停止所经过的该时段的长度t discharge为：
Figure PCTCN2018073914-appb-000009
其中，I 4为第一电流源I 4的电流值。
在t6时刻，第二校准电容C C2上存储的电荷量为：
Figure PCTCN2018073914-appb-000010
其中，t discharge需满足条件t discharge≤t6-t5。
可选地，为了避免开关频繁切换导致的电荷泄露，在该第三阶段之后也可以包括一个缓冲阶段例如图4中所示的t6至t7。在该缓冲阶段，控制电路230可以控制开关S1～S12、S14断开，S13闭合，第一积分电路212输出的第一电压信号V OUTP和第二电压信号V OUTN保持不变。
在第四阶段，例如图4所示的t7至t8阶段，控制电路230可以控制开关S2～S3、S5～S7、S9～S12、S14断开，开关S1、S4、S8、S13闭合。第二积分电路222将第二校准电容器C C2的电容信号转化为第二电压信号V OUTN，第一充放电电路211将检测电容器C X放电至检测电容器C X的电压等于零， 将第一校准电容器C C1放电至第一校准电容器C C1的电压等于零，其中，第二积分电路的第二输入端的输入电压等于第二电压V R2。
具体地，S8闭合后，第二积分电路222开始进行积分操作，由于第二运算放大器OP2的虚短特性，第二校准电容器C C2的上极板和第二积分电容器C C2的左极板电压被钳位到第二电压V R2。由于第二运算放大器OP2的虚断特性，在t7时刻第二校准电容器C C2上存储的电荷将会在第二校准电容器C C2以及第二积分电容器C S2上进行重新分配，电荷平衡方程为：
Figure PCTCN2018073914-appb-000011
其中，C S2为第二积分电容器C S2的电容值。
通过公式(7)可计算第二积分电路222输出的第二电压信号V OUTN为：
Figure PCTCN2018073914-appb-000012
开关S1和S4闭合后，检测电容器Cx放电至检测电容器Cx的电压等于零，第一校准电容器C C1放电至第一校准电容器C C1的电压等于零，在t5时刻，检测电容器Cx和第一校准电容器C C1上存储的电荷量均为0。
在电容检测的过程中，可以针对该检测电容器C X重复执行N次第一阶段至第四阶段，即重复进行图4中的t2至t8时段N次，N为偶数。图4仅示出了N＝2的情况。重复进行上述过程N次后，第一积分电路212输出的第一电压信号V OUTP和第二积分电路222输出的第二电压信号V OUTN分别为：
Figure PCTCN2018073914-appb-000013
Figure PCTCN2018073914-appb-000014
其中，可选地，C C1＝C XI 2/I 1，即C C1-C XI 2/I 1＝0，并且C C2＝C XI 3/I 4，即C C2-C XI 3/I 4＝0。
当电容传感器没有操作时，待检测电容C X等于基础电容值C X0，第一积分电路212输出的第一电压信号V OUTP＝V R1，第二积分电路222输出的第二电压信号V OUTP＝V R2，此时对第一积分电路212输出的第一电压信号VOUTP和第二积分电路222输出的第二电压信号V OUTN进行差分运算可以得到第一差分信号(例如等于V R1-V R2)。
在传感器有操作例如用户触摸该检测电容器对应的触摸点时，待检测电 容C X由基础电容值Cx 0变为Cx 0+ΔCx，根据公式(9)和公式(10)，可以得到第一积分电路212输出的第一电压信号V OUTP和第二积分电路222输出的第二电压信号V OUTN分别为：
Figure PCTCN2018073914-appb-000015
Figure PCTCN2018073914-appb-000016
处理电路240可以基于公式(11)和公式(12)，对第一电压信号V OUTP和第二电压信号V OUTN进行差分处理可以得到第二差分信号，根据第一差分信号和第二差分信号就可以确定检测电容器Cx的电容变化量△Cx。特别地，当V R1＝V R2时，第一差分信号为零，因此第二差分信号可以直接反应电容变化量△Cx，也就是直接通过第二差分信号即可得到电容变化量△Cx而无需考虑第一差分信号。
另外，根据公式(11)和公式(12)可以看出，由于第一校准电容器C C1和第二校准电容器C C2的存在，第一电压信号V OUTP和第二电压信号V OUTN仅反应了电容变化量△Cx的变化情况，而并不涉及检测电容器Cx(可理解为检测电容器Cx的基础电容值Cx 0)。换句话说，第一校准电容器C C1抵消了基础电容值Cx 0对所述第一积分电路212输出的第一电压信号V OUTP的贡献量；第二校准电容器C C2抵消了检测电容器Cx的基础电容值Cx 0对所述第二积分电路222输出的第二电压信号V OUTN的贡献量。从而，当导体(例如，手指)接近或触摸检测电极时，该电容检测电路输出的信号量都为有用的信号量，即都为△Cx贡献的信号量，从而能够大大提高电容检测的灵敏度。
在类型1中，是以先充电后放电为例进行描述的，即先对检测电容器Cx和第一校准电容器C C1充电直至检测电容器Cx的电压达到第一电压V R1，后对检测电容器Cx和第二校准电容器C C2放电直至检测电容器Cx的电压达到第二电压V R2，但是，本申请实施例对充放电的顺序不作任何限定。例如，在初始化阶段，控制电路230可以控制检测电容器Cx和第一校准电容器C C1充电至电源电压V DD；在第一阶段，检测电容器Cx和第一校准电容器C C1分别向各自连接的电流源放电，直至检测电容器Cx的电压达到第二电压V R2时停止；在第二阶段，第一积分电容器积分，并对检测电容器Cx和第二校 准电容器C C2充电至电源电压V DD；在第三阶段，第一电流源I 1和第三电流源I 3分别向检测电容器Cx和第二校准电容器C C2充电，直至检测电容器Cx的电压达到第一电压V R1时停止；在第四阶段，第二积分器积分，并将检测电容器Cx和第一校准电容器C C1充电至电源电压V DD。此时，第一开关的一端与检测电容器相连而另一端接电源，第四开关的一端与第一校准电容器C C1相连且另一端接电源，第六开关的一端与第二校准电容器相连且另一端接地。
类型2
可选地，第一充放电电路211包括第一电流源I 1和第二电流源I 2，第二充放电电路221包括第三电流源I 3。
其中，第一电流源I 1与检测电容器C X相连，用于对检测电容器C X充电或放电，第二电流源I 2与第一校准电容器C C1相连，用于对第一校准电容器C C1充电或放电，其中，第一校准电容器C C1的电容值与基础电容值C X0的比值等于第二电流源I 2的电流值与第一电流源I 1的电流值的比值，即C C1/C X0＝I 2/I 1。
第三电流源I 3与第二校准电容器C C2相连，用于对第二校准电容器C C2充电或放电，其中，第二校准电容器C C2的电容值与基础电容值C X0的比值等于第三电流源I 3的电流值与第一电流源I 1的电流值的比值，即C C2/C X0＝I 3/I 1。
首先描述类型2中第一电流源I 1用于向检测电容器C X充电的情况。
在初始化阶段，控制电路230用于控制第一积分电路212和第二积分电路222上的电荷清零。
在第一阶段，第一充放电电路211用于将检测电容器C X放电至检测电容器C X的电压等于零，以及将第一校准电容器C C1放电至第一校准电容器C C1的电压等于零，第二充放电电路221用于向第二校准电容器C C2充电至第二校准电容器C C2的电压等于电源电压V DD。
在第二阶段，第一电流源I 1用于向检测电容器C X充电，直至检测电容器C X的电压达到第一电压V R1时停止，第二电流源I 2用于在第一电流源I 1向检测电容器C X充电的时段t charge内对第一校准电容器C C1充电，第三电流源I 3用于在第一电流源I 1向检测电容器C X充电的时段t charge内使第二校准电容器C C2对第三电流源I 3放电。
在第三阶段，第一积分电路212用于将第一校准电容器C C1的电容信号转化为第一电压信号V OUTP，第二积分电路222用于将第二校准电容器C C2的电容信号转化为第二电压信号V OUTN。其中，第一积分电路212的第二输入端的输入电压在第三阶段与第一电压V R1相等，第二积分电路222的第二输入端的输入电压在第三阶段与第二电压V R2相等。
可选地，电容检测电路还包括比较器(Comparator，COMP)，该比较器的第一输入端(例如同相输入端)与检测电容器C X相连，该比较器的输出端与控制电路230相连，该比较器的第二输入端(例如反相输入端)用于在第二阶段输入第一电压V R1。
其中，当该比较器在第二阶段判断检测电容器C X的电压达到第一电压V R1时，控制电路230控制第一充放电电路211停止对检测电容器C X和第一校准电容器C C1的充放电，以及停止第二充放电电路221对第二校准电容器C C2的充放电。
以图5为例进行说明，在前述关于图5的电路结构描述基础之上，电容检测电路还可以包括用于控制各电容进入不同阶段或者进入充电/放电阶段的开关组，比如第一充放电电路211进一步包括第一开关S1、第二开关S2、第三开关S3和第四开关S4，第二充放电电路221包括第五开关S5和第六开关S6，第一积分电路212包括第七开关S7和第十一开关S11，第二积分电路222包括第八开关S8和第十二开关S12。
其中，S1的一端接地且另一端与检测电容器C X的第一端相连，S2的一端与第一电流源I 1相连且一端与检测电容器C X的第一端相连，S3的一端与第二电流源I 2相连且另一端与第一校准电容器C C1的第一端相连，S4的一端接地且另一端与第一校准电容器C C1的第一端相连，S7的一端与第一校准电容器C C1的第一端相连且另一端与第一积分电路212的第一输入端相连，S11与第一积分电容器C S1并联，S5的一端与第二校准电容器C C2的第一端相连且另一端与第三电流源I 3相连，S6的一端与电源相连且另一端与第二校准电容器C C2的第一端相连，S8的一端与第二校准电容器C C2的第一端相连且另一端与第二积分电路222的第一输入端相连，S12与第二积分电容器C S2并联。检测电容器C X的第二端、所述第一校准电容器C C1的第二端、和所述第二校准电容器C C2的第二端均接地。
可选地，在初始化阶段中，例如图6所示的t0至t1阶段，控制电路230 可以控制S11和S12闭合，以使第一积分电容器C S1和第二电容积分器C S2完全放电，即放电至第一积分电容器C S1和第二电容积分器C S2的电压等于零。此时，第一积分电容器C S1、第二积分电容器C S2上存储的电荷量为零，第一积分电路212输出的第一电压信号V OUTP＝V R1，第二积分电路222输出的第二电压信号V OUTN＝V R2。当第一积分电容器C S1和第二积分电容器C S2上存储的电荷量达到上限时，可以通过控制S11和S12闭合以清零第一积分电容器C S1和第二积分电容器C S2上存储的电荷。
接下来，控制电路230可以控制上述开关的开关状态即闭合或断开，从而实现第一阶段至第三阶段的操作，下面以表二所示的开关状态和图6所示的逻辑时序图为例具体说明该电容检测电路的工作过程。
表二
Figure PCTCN2018073914-appb-000017
在第一阶段，例如图6所示的t1至t2阶段，控制电路230控制S1、S4和S6在第一阶段闭合，而S2、S3、S5、S7、S8、S11和S12断开。从而检测电容器C X放电至检测电容器C X的电压等于零，第一校准电容器C C1放电至第一校准电容器C C1的电压等于零，第二校准电容器C C2充电至第二校准电容器C C2的电压等于电源电压。
t2时刻，待测电容C X、第一校准电容C C1、第二校准电容C C2上存储的电荷量分别为：
Q Cx,t1～t2＝0；Q CC1,t1～t2＝0；Q CC2,t1～t2＝C C2V DD；
此时，第一积分电路212输出的第一电压信号V OUTP＝V R1，第二积分电路222输出的第二电压信号V OUTN＝V R2。
在第二阶段(例如图6所示的t2至t3阶段)内的充电阶段(t charge)，S2、 S3和S5闭合，而S1、S4、S6～S8、S11和S12断开。从而第一电流源I 1向检测电容器C X充电，第二电流源I 2对第一校准电容器C C1充电，第二校准电容器C C2对第三电流源I 3放电，直至检测电容器C X的电压达到第一电压V R1时停止。应注意，第一电流源I 1向检测电容器C X充电的时长、第二电流源I 2对第一校准电容器C C1充电的时长、以及第二校准电容器C C2对第三电流源I 3放电的时长是相等的。也可以说，第一电流源I 1向检测电容器C X充电、第二电流源I 2对第一校准电容器C C1充电以及第二校准电容器C C2对第三电流源I 3放电是同时进行的。
由于比较器的同相输入端与检测电容器C X相连，而其反相输入端的输入电压等于第一电压V R1，因此当待检测电容C X上的电压达到第一电压V R1时(第二阶段的末尾时段)，该比较器的输出端向控制电路230输出的信号会发生翻转，从而使控制电路230知道检测电容器C X已被充电至其电压达到第一电压V R1，从而控制S2、S3和S5断开。
其中，本申请实施例中，该比较器的同相输入端和反相输入端可以调换，只需控制模块230能够检测到比较器输出的信号状态翻转即可。
第一电流源I 1向检测电容器C X充电直至检测电容器C X的电压达到第一电压V R1时停止所经过的该时段的长度t charge为：
Figure PCTCN2018073914-appb-000018
其中，C X为检测电容器C X的电容值，I 1为第一电流源I 1的电流值。
在t3时刻，第一校准电容C C1、第二校准电容C C2上存储的电荷量分别为：
Figure PCTCN2018073914-appb-000019
Figure PCTCN2018073914-appb-000020
其中，t charge需满足条件t charge≤t3-t2。I 2为第二电流源I 2的电流值，I 3为第三电流源I 3的电流值，C C1为第一校准电容器C C2的电容值，V DD为电源电压。
可选地，为了避免开关频繁切换导致的电荷泄露，在该第二阶段之后还可以包括一个缓冲阶段(例如图6所示的t3至t4)。在该缓冲阶段，控制电路230可以控制所有开关均保持断开状态，各个电容上的电荷量均保持不变。
在第三阶段(例如图6所示的t4至t5阶段)，控制电路230控制开关S7和S8闭合，而S1～S6、S11和S12断开。从而第一积分电路212将第一校准电容器C C1的电容信号转化为第一电压信号V OUTP，第二积分电路222将第二校准电容器C C2的电容信号转化为第二电压信号V OUTN。其中，第一积分电路212的第二输入端的输入电压等于第一电压V R1，第二积分电路222的第二输入端的输入电压等于第二电压V R2。
具体地，S7和S8闭合后，第一积分电路212和第二积分电路222开始进行积分操作，由于第一运算放大器OP1的虚短特性，第一校准电容器C S1其C C1的上极板和第一积分电容器C S1其的左极板电压被钳位到电压V R1。由于第一运算放大器OP1的虚断特性，在t4时刻第一校准电容器C C1上存储的电荷将会在第一校准电容器C C1以及第一积分电容器C S1上进行重新分配，电荷平衡方程为：
Figure PCTCN2018073914-appb-000021
其中，C S1为第一积分电容器C S1的电容值。
通过公式(4)可计算第一积分电路212输出的第一电压信号V OUTP为：
Figure PCTCN2018073914-appb-000022
由于第二运算放大器OP2的虚短特性，第二校准电容器C C2的上极板和第二积分电容器C S2的左极板电压被钳位到第二电压V R2。由于第二运算放大器OP2的虚断特性，在t3时刻第二校准电容器C C2上存储的电荷将会在第二校准电容器C C2以及第二积分电容器C S2上进行重新分配，电荷平衡方程为：
Figure PCTCN2018073914-appb-000023
其中，C S2为第二积分电容器C S2的电容值。
通过公式(18)可计算第二积分电路222输出的第二电压信号V OUTN为：
Figure PCTCN2018073914-appb-000024
可选地，为了避免开关频繁切换导致的电荷泄露，在该第三阶段之后也可以包括一个缓冲阶段(例如图6中所示的t5至t6)，在该缓冲阶段，控制电路230可以控制所有开关均保持断开状态，第一积分电路212输出的第一 电压信号V OUTP和第二积分电路222输出的第二电压信号V OUTN保持不变。
在电容检测的过程中，可以针对该检测电容器C X重复执行N次第一阶段至第三阶段，以提升电容检测的灵敏度。即，重复图6中的t1至t6时段N次，N为正整数。图6仅示出了N＝2的情况。重复进行上述过程N次后，第一积分电路212输出的第一电压信号V OUTP和第二积分电路222输出的第二电压信号V OUTN分别为：
Figure PCTCN2018073914-appb-000025
Figure PCTCN2018073914-appb-000026
其中，可选地，C C1＝C XI 2/I 1，即C C1-C XI 2/I 1＝0，并且C C2＝C XI 3/I 1，即C C2-C XI 3/I 1＝0。
可选地，取V R1＝V R2＝V DD/2＝V CM。
当电容传感器没有操作时，待检测电容C X等于基础电容值C X0，第一积分电路212输出的第一电压信号V OUTP和第二积分电路222输出的第二电压信号VOUT N为V OUTP＝V OUTN＝V CM，此时，对第一电压信号VOUTP和第二电压信号V OUTN进行差分运算可以得到第一差分信号。
在传感器有操作例如用户触摸该检测电容器对应的触摸点时，待检测电容C X由基础电容值Cx 0变为Cx 0+ΔCx，根据公式(20)和公式(21)，可以分别得到第一积分电路212输出的第一电压信号V OUTP和第二积分电路222输出的第二电压信号V OUTN分别为：
Figure PCTCN2018073914-appb-000027
Figure PCTCN2018073914-appb-000028
处理电路240可以基于公式(22)和公式(23)，对第一电压信号V OUTP和第二电压信号V OUTN进行差分处理可以得到第二差分信号，根据第一差分信号和第二差分信号就可以确定检测电容器Cx的电容变化量△Cx。特别地，V OUTP＝V OUTN＝V CM时，第一差分信号为零，因此第二差分信号可以直接反应电容变化量△Cx，也就是直接通过第二差分信号即可得到电容变化量△Cx的变化情况而无需考虑第一差分信号。
接下来描述类型2中第一电流源I 1用于使检测电容器C X向第一电流源 I 1放电的情况。
在初始化阶段，控制电路230用于控制第一积分电路212和第二积分电路222上的电荷清零。
在第一阶段，第一充放电电路211用于向检测电容器充电至检测电容器C X的电压等于电源电压V DD，以及将第一校准电容器C C1充电至第一校准电容器C C1的电压等于电源电压V DD，第二充放电电路221用于将第二校准电容器C C2放电至第二校准电容器C C2的电压等于零。
在第二阶段，第一电流源I 1用于使检测电容器C X向第一电流源I 1放电，直至检测电容器C X的电压达到第一电压时的停止，第二电流源I 2用于在检测电容器C X向第一电流源I 1放电的时段t charge内使第一校准电容器C C1向第二电流源I 2放电，第三电流源I 3用于在检测电容器C X向第一电流源I 1放电的时段t charge内对第二校准电容器C C2充电。
在第三阶段，第一积分电路212用于将第一校准电容器C C1的电容信号转化为第一电压信号，第二积分电路222用于将第二校准电容器C C2的电容信号转化为第二电压信号，其中，第一积分电路212的第二输入端的输入电压在第三阶段与第一电压V R1相等，第二积分电路222的第二输入端的输入电压在第三阶段与第二电压V R2相等。
可选地，该电容检测电路还包括比较器COMP，该比较器的第一输入端(例如同相输入端)与检测电容器C X相连，该比较器的输出端与控制电路230相连，该比较器的第二输入端(例如反相输入端)用于在第二阶段输入第一电压V R1。
其中，当比较器判断检测电容器C X的电压在第二阶段达到第一电压V R1时，控制电路230控制第一充放电电路211停止对检测电容器C X和第一校准电容器C C1的充放电以及停止第二充放电电路221对第二校准电容器C C2的充放电。
以图7为例进行描述，在前述关于图5的电路结构描述基础之上，电容检测电路还包括用于控制各电容进入不同阶段或者进入充电/放电阶段的开关组，比如第一充放电电路211进一步包括第一开关S1、第二开关S2、第三开关S3和第四开关S4，第二充放电电路221包括第五开关S5和第六开关S6，第一积分电路212包括第七开关S7和第十一开关S11，第二积分电路222包括第八开关S8和第十二开关S12。
其中，S1的一端与电源相连且另一端与检测电容器C X的第一端相连，S2的一端与第一电流源I 1相连且一端与检测电容器C X的第一端相连，S3的一端与第二电流源I 2相连且另一端与第一校准电容器C C1的第一端相连，S4的一端与电源相连且另一端与第一校准电容器C C1的第一端相连，S5的一端与第二校准电容器C C2的第一端相连且另一端与第三电流源I 3相连，S6的一端接地且另一端与第二校准电容器C C2的第一端相连，S7的一端与第一校准电容器C C1的第一端相连且另一端与第一积分电路212的第一输入端相连，S11与第一积分电容器C S1的第一端并联，S8的一端与第二校准电容器C C2的第一端相连且另一端与第二积分电路222的第一输入端相连，S12与第二积分电容器并联。检测电容器C X的第二端、所述第一校准电容器C C1的第二端、和所述第二校准电容器C C2的第二端均接地。
可选地，在初始化阶段，例如图8所示的t0至t1阶段，控制电路230可以控制S11和S12闭合，以使第一积分电容器C S1和第二电容积分器C S2完全放电，即放电至第一积分电容器C S1和第二电容积分器C S2的电压等于零。此时，第一积分电容C S1和第二积分电容C S2上存储的电荷量为零，第一积分电路212输出的第一电压信号V OUTP＝V R1，第二积分电路222输出的第二电压信号V OUTN＝V R2。当第一积分电容器C S1和第二积分电容器C S2上存储的电荷量达到上限时，可以通过控制S11和S12闭合以清零第一积分电容器C S1和第二积分电容器C S2上存储的电荷。
接下来，控制电路230可以控制上述开关的开关状态即闭合或断开，从而实现第一阶段至第三阶段的操作，下面以表三所示的开关状态和图8所示的逻辑时序图为例具体说明该电容检测电路的工作过程。
表三
Figure PCTCN2018073914-appb-000029
在第一阶段，例如图8所示的t1至t2阶段，控制电路230控制S1、S4和S6在第一阶段闭合，而S2、S3、S5、S7、S8、S11和S12断开。从而检测电容器C X充电至检测电容器C X的电压等于电源电压V DD，第一校准电容器C C1充电至第一校准电容器C C1的电压等于电源电压V DD，第二校准电容器C C2放电至第二校准电容器C C2的电压等于零。
t2时刻，待测电容C X、校准电容C C1、校准电容C C2上存储的电荷量分别为：
Q Cx,t1～t2＝C XV DD；Q CC1,t1～t2＝C C1V DD；Q CC1,t1～t2＝0；
此时，第一积分电路212输出的第一电压信号V OUTP＝V R1，第二积分电路222输出的第二电压信号V OUTN＝V R2。
在第二阶段(例如图8所示的t2至t3阶段)内的放电阶段(t discharge)，S2、S3和S5闭合，而S1、S4、S6～S8、S11和S12断开。从而检测电容器C X向第一电流源I 1放电，第一校准电容器C C1向第二电流源I 2放电，第三电流源I 3对第二校准电容器C C2充电，直至检测电容器C X的电压达到第一电压V R1时停止。应注意，检测电容器C X向第一电流源I 1放电的时长、第一校准电容器C C1向第二电流源I 2放电的时长、以及第三电流源I 3对第二校准电容器C C2充电的时长时相等的。也可以说，检测电容器C X向第一电流源I 1放电、第一校准电容器向C C1向第二电流源I 2放电、以及第三电流源I 3对第二校准电容器C C2充电是同时进行的。
由于比较器的同相输入端与检测电容器C X相连，而其反相输入端的输入电压等于第一电压V R1，因此当待检测电容C X上的电压达到第一电压V R1时(第二阶段的末尾时段)，比较器的输出端向控制电路230输出的信号会发生翻转，从而使控制电路230知道检测电容器C X何时被充电至其电压达到第一电压V R1，从而在检测电容器C X的电压达到第一电压V R1时控制S2、S3和S5断开。
本申请实施例中，该比较器的同相输入端和反相输入端可以调换，只需控制模块230能够检测到比较器输出的信号状态翻转即可。
检测电容器C X向第一电流源I 1放电直至检测电容器C X的电压达到第一电压时停止所经过的该时段的长度t discharge为：
Figure PCTCN2018073914-appb-000030
其中，C X为检测电容器C X的电容值，I 1为第一电流源I 1的电流值。
在t3时刻，校准电容C C1、校准电容C C2上存储的电荷量分别为：
Figure PCTCN2018073914-appb-000031
Figure PCTCN2018073914-appb-000032
其中，t charge需满足条件t charge≤t3-t2。I 2为第二电流源I 2的电流值，I 3为第三电流源I 3的电流值，C C2为第二校准电容器C C2的电容值。
可选地，为了避免开关频繁切换导致的电荷泄露，在该第二阶段之后可以包括一个缓冲阶段(例如图8中所示的t3至t4)。在该缓冲阶段，控制电路230可以控制所有开关均保持断开状态，各个电容上的电荷量均保持不变。
在第三阶段(例如图8所示的t4至t5阶段)，控制电路230控制开关S7和S8闭合，而S1～S6、S11和S12断开。从而第一积分电路212将第一校准电容器C C1的电容信号转化为第一电压信号V OUTP，第二积分电路222将第二校准电容器C C2的电容信号转化为第二电压信号V OUTN。其中，第一积分电路212的第二输入端的输入电压等于第一电压V R1，第二积分电路222的第二输入端的输入电压等于第二电压V R2。
具体地，S7和S8闭合后，第一积分电路212和第二积分电路222开始进行积分操作，由于第一运算放大器OP1的虚短特性，第一校准电容器C C1的上极板和第一积分电容器的左极板电压被钳位到电压V R1。由于第一运算放大器OP1的虚断特性，在t4时刻第一校准电容器C C1上存储的电荷将会在第一校准电容器C C1以及第一积分电容器C S1上进行重新分配，电荷平衡方程为：
Figure PCTCN2018073914-appb-000033
其中，C S1为第一积分电容器C S1的电容值。
通过公式(27)可以计算出第一积分电路212输出的第一电压信号V OUTP为：
Figure PCTCN2018073914-appb-000034
由于第二运算放大器OP2的虚短特性，第二校准电容器C C2的上极板和第二积分电容器C C2的左极板电压被钳位到第二电压V R2。由于第二运算放 大器OP2的虚断特性，在t3时刻第二校准电容器C C2上存储的电荷将会在第二校准电容器C C2以及第二积分电容器C S2上进行重新分配，电荷平衡方程为：
Figure PCTCN2018073914-appb-000035
其中，C S2为第二积分电容器C S2的电容值。
通过该式可以计算出第二积分电路222输出的第二电压信号V OUTN为：
Figure PCTCN2018073914-appb-000036
可选地，为了避免开关频繁切换导致的电荷泄露，在该第三阶段之后也可以包括一个缓冲阶段(例如图8中所示的t5至t6)，在该缓冲阶段，控制电路230可以控制所有开关均保持断开状态，第一积分电路212输出的第一电压信号V OUTP和第二电压信号V OUTN保持不变。
同样，可以针对该检测电容器C X重复执行N次第一阶段至第三阶段，即重复图8中的t1至t6时段N次，以提升电容检测的灵敏度。图8仅示出了N＝2的情况，重复进行上述过程N次后，第一积分电路212输出的第一电压信号V OUTP和第二积分电路222输出的第二电压信号V OUTN分别为：
Figure PCTCN2018073914-appb-000037
Figure PCTCN2018073914-appb-000038
其中，可选地，C C1＝C XI 2/I 1，即C C1-C XI 2/I 1＝0，并且C C2＝C XI 3/I 1，即C C2-C XI 3/I 1＝0。
可选地，取V R1＝V R2＝V DD/2＝V CM。
当电容传感器没有操作时，待检测电容C X等于基础电容值C X0，第一积分电路212和第二积分电路222输出的信号V OUTP＝V OUTN＝V CM，此时，对第一积分电路212输出的第一电压信号V OUTP和第二积分电路222输出的第二电压信号V OUTN进行差分运算可以得到第一差分信号。
在传感器有操作例如用户触摸该检测电容器对应的触摸点时，待检测电容C X由基础电容值Cx 0变为Cx 0+ΔCx，根据公式(31)和公式(32)，可以分别得到第一积分电路212输出的第一电压信号V OUTP和第二积分电路222输出的第二电压信号V OUTN分别为：
Figure PCTCN2018073914-appb-000039
Figure PCTCN2018073914-appb-000040
处理电路240可以基于公式(33)和公式(34)，对第一电压信号V OUTP和第二电压信号V OUTN进行差分处理可以得到第二差分信号，根据第一差分信号和第二差分信号就可以确定检测电容器Cx的电容变化量△Cx。特别地，V OUTP＝V OUTN＝V CM时，第一差分信号为零，因此第二差分信号可以直接反应电容变化量△Cx，也就是直接通过第二差分信号即可得到电容变化量△Cx而无需考虑第一差分信号。
类型1和类型2中的各个阶段中，电容检测电路执行的动作不同。前述对于不同阶段的划分仅仅是示例，根据该电容检测电路在不同阶段执行的动作，也可以有其他的划分方式。
以初始阶段的划分为例，类型2中包括初始化阶段、第一阶段、第二阶段和第三阶段，且类型2中的初始化阶段需要将两个积分电路上的电荷清零；类型1中包括初始化阶段、第一阶段、第二阶段、第三阶段和第四阶段，且类型1中的初始化阶段不仅需要对两个积分电路上的电荷清零，还需要对第一校准电容器C C1和检测电容器C X进行完全放电，从而第一电流源I 1和第二电流源I 2在第一阶段分别对检测电容器C X和第一校准电容器C C1充电相同时长，直至检测电容器C X的电压从零达到第一电压V R1。而类型1中的第四阶段，两个积分电路执行积分操作之后还需要对第一校准电容器C C1和检测电容器C X进行完全放电，以使第一电流源I 1和第二电流源I 2在紧接下来的第一阶段中分别对检测电容器C X和第一校准电容器C C1充电相同时长，直至检测电容器C X的电压从零达到第一电压V R1。
如果将类型1的第四阶段中对检测电容器C X和第一校准电容器C C1完全放电的过程，划分至第一阶段，那么类型1的初始化阶段则仅需要包括将两个积分电路上的电荷清零的过程。
又或者，如果将类型2的第一阶段中的将检测电容器C X和第一校准电容器C C1完全放电的过程划分至第三阶段，即第三阶段中两个积分器执行积分操作后，还将检测电容器C X和第一校准电容器C C1进行完全放电，则类型2的初始化阶段不仅需要将两个积分电路上的电荷清零，还需要将检测电 容器C X和第一校准电容器C C1完全放电。
图9是本申请实施例的触摸检测装置900的示意性电路图。
如图9所示，该触摸检测装置900包括如图2所示的电容检测电路200。其中，该触摸检测装置900可以根据所述电容检测电路所确定的该检测电容器相对于该基础电容器的电容变化量，确定用户的触摸位置。
可选地，该检测电容器为一个触摸通道的电极与地形成的电容器。
可选地，本申请实施例提供了一种终端设备，包括如图9所示的触摸检测装置900。作为示例而非限定，所述终端设备900可以为手机、平板电脑、笔记本电脑、台式机电脑、车载电子设备或穿戴式智能设备等。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种电容检测电路，其特征在于，所述电容检测电路用于检测检测电容器相对于基础电容值的电容变化量，所述电容检测电路包括第一前端电路、第二前端电路、控制电路和处理电路，所述控制电路用于控制所述第一前端电路和所述第二前端电路，以使所述第一前端电路在所述控制电路的控制下用于将所述检测电容器的电容信号转化为第一电压信号，所述第二前端电路在所述控制电路的控制下用于将所述检测电容器的电容信号转化为第二电压信号；
    其中，所述第一前端电路包括第一校准电容器、第一充放电电路和第一积分电路，所述检测电容器与所述第一充放电电路相连，所述第一校准电容器与所述第一充放电电路和所述第一积分电路的第一输入端相连；
    所述第一充放电电路用于对所述第一前端电路所连接的所述检测电容器和所述第一校准电容器进行充放电，所述第一积分电路用于通过所述第一校准电容器将所述检测电容器的电容信号转化为所述第一电压信号；
    所述第二前端电路包括第二校准电容器、第二充放电电路和第二积分电路，所述第二校准电容器与所述第二充放电电路和所述第二积分器的第一输入端相连；
    所述第二充放电电路用于对所述第二校准电容器进行充放电，所述第二积分电路用于通过所述第二校准电容器将所述检测电容器的电容信号转化为所述第二电压信号；
    所述处理电路与所述第一积分电路和所述第二积分电路的输出端相连，用于计算所述第一积分电路输出的所述第一电压信号和所述第二积分电路输出的所述第二电压信号的差分信号，并根据所述差分信号确定所述检测电容器相对于基础电容值的电容变化量。
  2. 根据权利要求1所述的电容检测电路，其特征在于，所述第一充放电电路包括第一电流源和第二电流源，所述第二充放电电路包括第三电流源，
    其中，所述第一电流源与所述检测电容器相连，用于对所述检测电容器充电或放电，所述第二电流源与所述第一校准电容器相连，用于对所述第一校准电容器充电或放电，所述第一校准电容器的电容值与所述基础电容值的比值等于所述第二电流源的电流值与所述第一电流源的电流值的比值，
    所述第三电流源与所述第二校准电容器相连，用于对所述第二校准电容器充电或放电，所述第二校准电容器的电容值与所述基础电容值的比值等于所述第三电流源的电流值与所述第一电流源的电流值的比值。
  3. 根据权利要求2所述的电容检测电路，其特征在于，在初始化阶段，所述控制电路用于控制所述第一积分电路和所述第二积分电路上的电荷清零；
    在第一阶段，所述第一充放电电路用于将所述检测电容器放电至所述检测电容器的电压等于零，以及将所述第一校准电容器放电至所述第一校准电容器的电压等于零，所述第二充放电电路用于向所述第二校准电容器充电至所述第二校准电容器的电压等于电源电压；
    在第二阶段，所述第一电流源用于向所述检测电容器充电，直至所述检测电容器的电压达到第一电压时停止，所述第二电流源用于在所述第一电流源向所述检测电容器充电的时段内对所述第一校准电容器充电，所述第三电流源用于在所述第一电流源向所述检测电容器充电的所述时段内使所述第二校准电容器对所述第三电流源放电；
    在第三阶段，所述第一积分电路用于将所述第一校准电容器的电容信号转化为所述第一电压信号，所述第二积分电路用于将所述第二校准电容器的电容信号转化为所述第二电压信号，其中，所述第一积分电路的第二输入端的输入电压等于所述第一电压，所述第二积分电路的第二输入端的输入电压等于第二电压。
  4. 根据权利要求3所述的电容检测电路，其特征在于，所述第一充放电电路包括第一开关、第二开关、第三开关和第四开关，所述第二充放电电路包括第五开关和第六开关，所述第一积分电路包括第七开关，所述第二积分电路包括第八开关，
    其中，所述第一开关的一端接地且另一端与所述检测电容器的第一端相连，所述第二开关的一端与所述第一电流源相连且一端与所述检测电容器的第一端相连，所述第三开关的一端与所述第二电流源相连且另一端与所述第一校准电容器的第一端相连，所述第四开关的一端接地且另一端与所述第一校准电容器的第一端相连，所述第五开关的一端与所述第二校准电容器的第一端相连且另一端与所述第三电流源相连，所述第六开关的一端与电源相连且另一端与所述第二校准电容器的第一端相连，所述第七开关的一端与所述 第一校准电容器的第一端相连且另一端与所述第一积分电路的第一输入端相连，所述第八开关的一端与所述第二校准电容器的第一端相连且另一端与所述第二积分电路的第一输入端相连，所述检测电容器的第二端、所述第一校准电容器的第二端、和所述第二校准电容器的第二端均接地。
  5. 根据权利要求4所述的电容检测电路，其特征在于，
    在所述第一阶段，所述第一开关、所述第四开关和所述第六开关在所述第一阶段闭合，而所述第二开关、所述第三开关、所述第五开关、所述第七开关和所述第八开关断开，
    在所述第二阶段，所述第二开关、所述第三开关和所述第五开关闭合，而所述第一开关、所述第四开关、所述第六开关、所述第七开关和所述第八开关断开，
    在所述第三阶段，所述第七开关和所述第八开关闭合，而所述第一开关、所述第二开关、所述第三开关、所述第四开关、所述第五开关和所述第六开关断开。
  6. 根据权利要求3至5中任一项所述的电容检测电路，其特征在于，所述第一积分电路输出的所述第一电压信号V OUTP和所述第二积分电路输出的所述第二电压信号V OUTN分别为：
    Figure PCTCN2018073914-appb-100001
    其中，V R1＝V R2＝V DD/2＝V CM，V R1为所述第一电压的电压值，V R2为所述第二电压的电压值，I 1为所述第一电流源的电流值，I 2为所述第二电流源的电流值，I 3为所述第三电流源的电流值，C S1为第一积分电容器的电容值，C S2为第二积分电容器的电容值，ΔCx为所述检测电容器的电容值相对于所述基础电容值的电容变化量，V DD为电源电压，N为所述第一阶段至所述第三阶段的执行次数，N为正整数。
  7. 根据权利要求2所述的电容检测电路，其特征在于，
    在初始化阶段，所述控制电路用于控制所述第一积分电容器和所述第二积分电容器上的电荷清零；
    在第一阶段，所述第一充放电电路用于将所述检测电容器充电至所述检测电容器的电压等于电源电压，以及将所述第一校准电容器充电至所述第一校准电容器的电压等于电源电压，所述第二充放电电路用于将所述第二校准 电容器放电至所述第二校准电容器的电压等于零；
    在第二阶段，所述第一电流源用于使所述检测电容器向所述第一电流源放电，直至所述检测电容器的电压达到第一电压时停止，所述第二电流源用于在所述检测电容器向所述第一电流源放电的时段内使所述第一校准电容器向所述第二电流源放电，所述第三电流源用于在所述检测电容器向所述第一电流源放电的所述时段内对所述第二校准电容器充电；
    在第三阶段，所述第一积分电路用于将所述第一校准电容器的电容信号转化为所述第一电压信号，所述第二积分电路用于将所述第二校准电容器的电容信号转化为所述第二电压信号，其中，所述第一积分电路的第二输入端的输入电压等于所述第一电压，所述第二积分电路的第二输入端的输入电压等于第二电压。
  8. 根据权利要求7所述的电容检测电路，其特征在于，
    所述第一充放电电路包括第一开关、第二开关、第三开关和第四开关，所述第二充放电电路包括第五开关和第六开关，所述第一积分电路包括第七开关，所述第二积分电路包括第八开关，
    其中，所述第一开关的一端与电源相连且另一端与所述检测电容器的第一端相连，所述第二开关的一端与所述第一电流源相连且一端与所述检测电容器的第一端相连，所述第三开关的一端与所述第二电流源相连且另一端与所述第一校准电容器的第一端相连，所述第四开关的一端与电源相连且另一端与所述第一校准电容器的第一端相连，所述第五开关的一端与所述第二校准电容器的第一端相连且另一端与所述第三电流源相连，所述第六开关的一端接地且另一端与所述第二校准电容器的第一端相连，所述第七开关的一端与所述第一校准电容器的第一端相连且另一端与所述第一积分电路的第一输入端相连，所述第八开关的一端与所述第二校准电容器的第一端相连且另一端与所述第二积分电路的第一输入端相连，所述检测电容器的第二端、所述第一校准电容器的第二端、和所述第二校准电容器的第二端均接地。
  9. 根据权利要求8所述的电容检测电路，其特征在于，
    在所述第一阶段，所述第一开关、所述第四开关和所述第六开关在所述第一阶段闭合，而所述第二开关、所述第三开关、所述第五开关、所述第七开关和所述第八开关断开，
    在所述第二阶段，所述第二开关、所述第三开关和所述第五开关闭合， 而所述第一开关、所述第四开关、所述第六开关、所述第七开关和所述第八开关断开，
    在所述第三阶段，所述第七开关和所述第八开关闭合，而所述第一开关、所述第二开关、所述第三开关、所述第四开关、所述第五开关和所述第六开关断开。
  10. 根据权利要求7至9中任一项所述的电容检测电路，其特征在于，所述第一积分电路输出的所述第一电压信号V OUTP和所述第二积分电路输出的所述第二电压信号V OUTN分别为：
    Figure PCTCN2018073914-appb-100002
    其中，V R1＝V R2＝V DD/2＝V CM，V R1为所述第一电压的电压值，V R2为所述第二电压的电压值，I 1为所述第一电流源的电流值，I 2为所述第二电流源的电流值，I 3为所述第三电流源的电流值，C S1为第一积分电容器的电容值，C S2为第二积分电容器的电容值，ΔCx为所述检测电容器的电容值相对于所述基础电容值的电容变化量，V DD为电源电压，N为所述第一阶段至所述第三阶段的执行次数，N为正整数。
  11. 根据权利要求3至10中任一项所述的电容检测电路，其特征在于，所述电容检测电路还包括比较器，所述比较器的第一输入端与所述检测电容器相连，所述比较器的输出端与所述控制电路相连，所述比较器的第二输入端用于在第二阶段输入所述第一电压，
    当所述比较器在所述第二阶段判断所述检测电容器的电压达到所述第一电压时，所述控制电路控制所述第一充放电电路停止对所述检测电容器和所述第一校准电容器的充放电以及停止所述第二充放电电路对所述第二校准电容器的充放电。
  12. 根据权利要求1所述的电容检测电路，其特征在于，所述第一充放电电路包括第一电流源、第二电流源和第四电流源，所述第二充放电电路包括第三电流源，
    其中，所述第一电流源和所述第四电流源均与所述检测电容器相连，所述第一电流源用于对所述检测电容器充电，所述第四电流源用于使所述检测电容器放电，所述第二电流源与所述第一校准电容器相连，用于对所述第一校准电容器充电，所述第一校准电容器的电容值与所述基础电容值的比值等 于所述第二电流源的电流值与所述第一电流源的电流值的比值，
    所述第三电流源与所述第二校准电容器相连，用于使所述第二校准电容器放电，所述第二校准电容器的电容值与所述基础电容值的比值等于所述第三电流源的电流值与所述第四电流源的电流值的比值。
  13. 根据权利要求12所述的电容检测电路，其特征在于，
    在初始化阶段，所述控制电路用于控制所述第一积分电路和所述第二积分电路上的电荷清零，且所述第一充放电电路用于将所述第一校准电容器和所述检测电容器上的电荷清零；
    在第一阶段，所述第一电流源用于对所述检测电容器充电，直至所述检测电容器的电压达到第一电压时停止，所述第二电流源用于在所述第一电流源向所述检测电容器充电的时段内对所述第一校准电容器充电；
    在第二阶段，所述第一积分电路用于将所述第一校准电容器的电容信号转化为所述第一电压信号，所述第一充放电电路用于将所述检测电容器充电至所述检测电容器的电压等于电源电压，所述第二充放电电路用于将所述第二校准电容器充电至所述第二校准电容器的电压等于电源电压，其中，所述第一积分电路的第二输入端的输入电压等于所述第一电压；
    在第三阶段，所述第四电流源用于使所述检测电容器向所述第四电流源放电，直至所述检测电容器的电压达到第二电压时停止，所述第三电流源用于在所述检测电容器向所述第四电流源放电的时段内使所述第二校准电容器对所述第三电流源放电；
    在第四阶段，所述第二积分电路用于将所述第二校准电容器的电容信号转化为所述第二电压信号，所述第一充放电电路用于将所述检测电容器放电至所述检测电容器的电压等于零，以及将所述第一校准电容器放电至所述第一校准电容器的电压等于零，其中，所述第二积分电路的第二输入端的输入电压等于所述第二电压。
  14. 根据权利要求13所述的电容检测电路，其特征在于，
    所述第一充放电电路包括第一开关、第二开关、第三开关、第四开关、第九开关和第十开关，所述第二充放电电路包括第五开关和第六开关，所述第一积分电路包括第七开关，所述第二积分电路包括第八开关，
    其中，所述第一开关的一端接地且另一端与所述检测电容器的第一端相连，所述第二开关的一端与所述第一电流源相连且另一端与所述检测电容器 的第一端相连，所述第三开关的一端与所述第二电流源相连且另一端与所述第一校准电容器的第一端相连，所述第四开关的一端接地且另一端与所述第一校准电容器的第一端相连，所述第九开关的一端与所述第四电流源相连且另一端与所述检测电容器的第一端相连，所述第十开关的一端与电源相连且另一端与所述检测电容器的第一端相连，所述第五开关的一端与所述第二校准电容器的第一端相连且另一端与所述第三电流源相连，所述第六开关的一端与电源相连且另一端与所述第二校准电容器的第一端相连，所述第七开关的一端与所述第一校准电容器的第一端相连且另一端与所述第一积分电路的第一输入端相连，所述第八开关的一端与所述第二校准电容器的第一端相连且另一端与所述第二积分电路的第一输入端相连，所述检测电容器的第二端、所述第一校准电容器的第二端、和所述第二校准电容器的第二端均接地。
  15. 根据权利要求14所述的电容检测电路，其特征在于，
    在所述第一阶段，所述第二开关和所述第三开关在所述第一阶段闭合，而所述第一开关、所述第四开关、所述第五开关、所述第六开关、所述第七开关、所述第八开关所述第九开关和所述第十开关断开，
    在所述第二阶段，所述第六开关、所述第七开关和所述第十开关闭合，而所述第一开关、所述第二开关、所述第三开关、所述第四开关、所述第五开关、所述第八开关和所述第九开关断开，
    在所述第三阶段，所述第五开关和所述第九开关闭合，而所述第一开关、所述第二开关、所述第三开关、所述第四开关、所述第六开关、所述第七开关、所述第八开关和所述第十开关断开，
    在所述第四阶段，所述第一开关、所述第四开关和所述第八开关闭合，而所述第二开关、所述第三开关、所述第五开关、所述第六开关、所述第七开关、所述第九开关和所述第十开关断开。
  16. 根据权利要求13至15中任一项所述的电容检测电路，其特征在于，所述电容检测电路还包括比较器，所述比较器的第一输入端与所述检测电容器相连，所述比较器的输出端与所述控制电路相连，所述比较器的第二输入端用于在所述第一阶段输入所述第一电压，以及在所述第三阶段输入所述第二电压，
    当所述比较器在所述第一阶段判断所述检测电容器的电压达到所述第一电压或者在所述第三阶段判断所述检测电容器的电压达到所述第二电压 时，所述控制电路控制所述第一充放电电路停止对所述检测电容器和所述第一校准电容器的充放电，以及控制所述第二充放电电路停止对所述第二校准电容器的充放电。
  17. 根据权利要求13至16中任一项所述的电容检测电路，其特征在于，所述第一积分电路输出的所述第一电压信号V OUTP和所述第二积分电路输出的所述第二电压信号V OUTN分别为：
    Figure PCTCN2018073914-appb-100003
    其中，V R1为所述第一电压的电压值，V R2为所述第二电压的电压值，V DD为电源电压，I 1为所述第一电流源的电流值，I 2为所述第二电流源的电流值，I 3为所述第三电流源的电流值，I 4为所述第四电流源的电流值，C S1为第一积分电容器的电容值，C S2为第二积分电容器的电容值，ΔCx为所述检测电容器的电容值相对于所述基础电容值的电容变化量，N为所述第一阶段至所述第三阶段的执行次数，N为偶数。
  18. 根据权利要求1至17中任一项所述的电容检测电路，其特征在于，所述第一积分电路包括第一运算放大器和与所述第一运算放大器并联的第一积分电容器，所述第二积分电路包括第二运算放大器和与所述第二运算放大器并联的第二积分电容器。
  19. 一种触摸检测装置，其特征在于，包括：如权利要求1至18中任一项所述的电容检测电路，所述触摸检测装置根据所述电容检测电路确定的所述检测电容器相对于所述基础电容值的电容变化量，确定用户的触摸位置。
  20. 一种终端设备，其特征在于，包括：如权利要求19所述的触摸检测装置。
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