WO2019153230A1 - 一种具有高稳定性粘结层的半导体装置及其制备方法 - Google Patents

一种具有高稳定性粘结层的半导体装置及其制备方法 Download PDF

Info

Publication number
WO2019153230A1
WO2019153230A1 PCT/CN2018/075947 CN2018075947W WO2019153230A1 WO 2019153230 A1 WO2019153230 A1 WO 2019153230A1 CN 2018075947 W CN2018075947 W CN 2018075947W WO 2019153230 A1 WO2019153230 A1 WO 2019153230A1
Authority
WO
WIPO (PCT)
Prior art keywords
metal
layer
semiconductor chip
bonding
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2018/075947
Other languages
English (en)
French (fr)
Inventor
杨人毅
许�鹏
滕辉
李晓勇
陈特伟
韩梅
张韧
魏雷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Huawei Technologies Co Ltd
Original Assignee
Huawei Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Priority to PCT/CN2018/075947 priority Critical patent/WO2019153230A1/zh
Priority to EP18905755.7A priority patent/EP3723116A4/en
Priority to CN201880067522.XA priority patent/CN111226308A/zh
Publication of WO2019153230A1 publication Critical patent/WO2019153230A1/zh
Priority to US16/984,805 priority patent/US20200365547A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/121—Arrangements for protection of devices protecting against mechanical damage
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/013—Manufacture or treatment of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/016—Manufacture or treatment using moulds
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/40—Encapsulations, e.g. protective coatings characterised by their materials
    • H10W74/47—Encapsulations, e.g. protective coatings characterised by their materials comprising organic materials, e.g. plastics or resins
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/0711—Apparatus therefor
    • H10W72/07141—Means for applying energy, e.g. ovens or lasers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07331—Connecting techniques
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07331—Connecting techniques
    • H10W72/07334—Using a reflow oven
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07351—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting
    • H10W72/07352—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting changes in structures or sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07351—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting
    • H10W72/07355—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting changes in materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/321—Structures or relative sizes of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/321—Structures or relative sizes of die-attach connectors
    • H10W72/325—Die-attach connectors having a filler embedded in a matrix
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H10W72/352—Materials of die-attach connectors comprising metals or metalloids, e.g. solders
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H10W72/353—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/127—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed characterised by arrangements for sealing or adhesion
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/40—Encapsulations, e.g. protective coatings characterised by their materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

  • the present application relates to the field of semiconductor chip packaging technologies, and in particular, to a semiconductor device and a method of fabricating the same.
  • EMC Epoxy Molding Compound
  • the semiconductor chip plastic packaging structure adopted by the industry has the following defects:
  • the embodiments of the present application provide a semiconductor device and a method for fabricating the same to overcome the above drawbacks.
  • a first aspect of the present application provides a semiconductor device comprising:
  • the bonding layer comprises a sintered metal;
  • the interior of the sintered metal includes a plurality of voids, at least partially hollow The inside is filled with a specific material; wherein the specific material has a certain fluidity when it is higher than a preset temperature, and can be solidified after being heated and melted.
  • the semiconductor device provided by the present application reduces the probability of moisture in the external environment accumulating inside the semiconductor device due to filling at least part of the cavity inside the sintered metal with a specific material, and reduces the mounting of the semiconductor device to the printing after reflow soldering.
  • the possibility of delamination of the chip and the substrate is caused; in addition, the ultrasonic scanning microscope image of the cavity filled with the specific material is significantly different from the image of the inner layer of the semiconductor, and thus the internal layer of the semiconductor device is layered. The detection accuracy is high.
  • the semiconductor device further includes: a molding body wrapped around the semiconductor chip and the periphery of the bonding layer, the specific material and the plastic sealing body corresponding to the molding body The same material.
  • the molded body can protect the semiconductor chip and the adhesive layer inside, and thus the reliability of the semiconductor device can be improved. Moreover, this embodiment can simplify the fabrication process of the semiconductor device and reduce the manufacturing cost.
  • a second possible embodiment in conjunction with the first aspect of the present application and its first possible embodiment, more than 85% of the voids in the interior of the sintered metal are filled with the specific material.
  • a third possible embodiment more than 90% of the voids in the interior of the sintered metal are filled with the specific material.
  • a first metal layer is disposed on a surface of the semiconductor chip bonded to the bonding layer, A first metal alloy layer is formed between the first metal layer and the bonding layer due to a metal bonding force.
  • This embodiment can improve the connection performance between the semiconductor chip and the bonding layer, and reduce the possibility of delamination between the two.
  • the surface of the substrate bonded to the bonding layer is provided with a second metal layer, the second A second metal alloy layer is formed between the metal layer and the bonding layer due to the metal bonding force.
  • This embodiment can improve the connection performance between the substrate and the bonding layer, and reduce the possibility of delamination between the two.
  • the specific material is introduced into the cavity from the outside of the bonding layer after forming the bonding layer by the sintering curing process, thereby achieving the effect of filling the cavity.
  • the sintered metal is sintered silver. This embodiment can improve the heat conduction and electrical conductivity of the bonding layer.
  • the metal powder comprises at least one of nano-scale and micro-scale metal particles.
  • the sintered metal is made from a metal powder through a sintering process.
  • a second aspect of the present application provides a method of fabricating a semiconductor device, the method comprising:
  • the bonding layer is used for bonding the semiconductor chip and the substrate, wherein the bonding layer is composed of sintered metal, and the sintered metal includes a plurality of voids therein; At least a portion of the void is filled with a particular material; the particular material has a certain fluidity above a predetermined temperature and is capable of solidifying after heating and melting.
  • the probability of moisture in the external environment accumulating inside the semiconductor device is reduced, and the semiconductor device is reduced when it is reflow mounted on the printed circuit board.
  • the possibility of layering of the chip and the substrate; in addition, the ultrasonic scanning microscope image of the cavity filled with the specific material is significantly different from the image of the inner layer of the semiconductor, so the detection accuracy of the internal layering of the semiconductor device is high.
  • the preparation method further includes: forming a molding body encapsulating the semiconductor chip and the bonding layer, and a molding material corresponding to the molding material and the molding material the same.
  • the molded body can protect the semiconductor chip and the bonding layer inside thereof, and thus, the reliability of the semiconductor device can be improved.
  • the filling the at least part of the cavity with a specific material comprises: flowing while forming the plastic body The molding compound flows into the at least a portion of the cavity such that the at least a portion of the cavity is filled with the molding compound.
  • This possible implementation can simplify the packaging process of the semiconductor device and reduce the packaging cost.
  • the method further comprises: The body is shaped and cured.
  • the filling the at least part of the cavity with a specific material comprises: heating the specific material above the preset temperature to enable the specific material to flow The specific material capable of flowing is injected into at least a portion of the void within the bonding layer.
  • This possible embodiment can increase the filling effect of the void.
  • a fifth possible embodiment after the fluid is injected into at least a portion of the cavity in the bonding layer by capillary force, include:
  • the structure filled with the specific material is placed under a certain temperature condition to post-cure the fluid injected into the cavity. This possible embodiment can improve the reliability of the semiconductor device.
  • a sixth possible embodiment more than 85% of the voids in the interior of the sintered metal are filled with the specific material.
  • This possible embodiment can reduce the possibility of delamination of the chip and the substrate when the semiconductor device is reflow mounted onto the printed wiring board. And improving the detection accuracy of the internal layering of the semiconductor device.
  • a surface of the semiconductor chip bonded to the bonding layer is provided with a first metal layer, A first metal alloy layer is formed between the first metal layer and the bonding layer due to a metal bonding force.
  • This possible embodiment can improve the connection performance between the semiconductor chip and the bonding layer, and reduce the possibility of delamination between the two.
  • a second metal layer is disposed on a surface of the substrate bonded to the bonding layer, A second metal alloy layer is formed between the two metal layers and the bonding layer due to a metal bonding force.
  • This possible embodiment can improve the connection performance between the substrate and the bonding layer, reducing the possibility of delamination between the two.
  • the sintered metal is sintered silver.
  • the bonding layer for bonding the semiconductor chip and the circuit substrate is composed of a sintered metal made of a high-conductivity and heat-conductive metal powder sintering process. Moreover, in the embodiment of the present application, at least part of the cavity existing inside the sintered metal is filled with a specific material. In this way, after the cavity is filled with a specific material, it is advantageous to reduce the moisture accommodation, and avoid large-scale moisture in the external environment from collecting inside the semiconductor chip molding structure, and further, avoiding chip and substrate due to external moisture accumulation inside. Layering.
  • the probability of moisture in the external environment accumulating inside the semiconductor molding structure is greatly reduced, thereby reducing when the semiconductor device is reflow mounted on the printed wiring board. , the possibility of delamination of the chip and substrate.
  • the ultrasonic scanning microscope image is significantly different from the ultrasonic scanning microscope image in which the internal chip of the semiconductor device and the circuit substrate are layered, and the image of the filled cavity can be easily removed by the ultrasonic scanning microscope image, thereby reducing the layering.
  • the detected interference is high. Therefore, the detection accuracy of the internal layering of the semiconductor device provided by the embodiment of the present application is high.
  • FIG. 1 is a schematic view of a semiconductor chip molding structure commonly used in the art
  • FIG. 2 is a schematic view showing the structure of a sintered silver-connected semiconductor chip and a circuit substrate in the art
  • FIG. 3 is a schematic diagram showing the principle of internal layering of a semiconductor chip plastic package structure
  • FIG. 4 is a perspective perspective view of a semiconductor device according to an embodiment of the present application.
  • FIG. 4 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present application.
  • FIG. 5 is a schematic flow chart of a method for fabricating a semiconductor device according to an embodiment of the present application.
  • FIG. 6 is a schematic cross-sectional structural diagram of a series of processes for fabricating a semiconductor device according to an embodiment of the present application.
  • FIG. 7 is a schematic flow chart of another method for fabricating a semiconductor device according to an embodiment of the present application.
  • a bonding layer for example, a sintered silver structure
  • At least one item means one or more, and "a plurality” means two or more.
  • a and / or B can mean: only A exists, only B exists, and both A and B exist. , where A, B can be singular or plural.
  • the character "/” generally indicates that the contextual object is an "or” relationship.
  • At least one of the following” or a similar expression thereof refers to any combination of these items, including any combination of a single item or a plurality of items.
  • At least one of a, b or c may mean: a, b, c, "a and b", “a and c", “b and c", or "a and b and c" ", where a, b, c can be single or multiple.
  • the semiconductor chip plastic package structure is generally as shown in FIG. 1, and includes a semiconductor chip 11 and a substrate 12, and the semiconductor chip 11 is usually bonded to the substrate 12 with a conductive paste 13.
  • the substrate 12 may be a printed wiring board or a ceramic circuit board.
  • the circuit board can be used to lay a printed circuit to achieve electrical signal transmission.
  • the semiconductor chip 11 since the semiconductor chip 11 generates heat during operation, the main heat dissipation path of the semiconductor chip is conduction heat dissipation, and the circuit board can also perform heat dissipation to transfer the heat generated by the semiconductor chip 11 to the outside of the plastic package structure, specifically As shown in FIG. 1, the heat generated by the semiconductor chip 11 can be conducted and emitted through the conductive paste 13 and the substrate 12 under the semiconductor chip 11.
  • the epoxy resin Since the epoxy epoxy has the advantages of simple operation, stable performance and good electrical conductivity in the adhesive sheet, the epoxy resin is generally used as a material commonly used in the molding of semiconductor chips. .
  • the thermal conductivity of epoxy resin silver gel is relatively low, generally less than 10 watts/meter ⁇ degree (w/m ⁇ k).
  • epoxy resin silver glue cannot quickly and efficiently turn the semiconductor chip 11
  • the heat generated during operation is dissipated, which causes the temperature of the PN junction of the semiconductor chip (hereinafter referred to as the junction temperature) to rise, thereby shortening the life of the chip.
  • the surface of the semiconductor chip 11 and the surface of the substrate 12 which are in contact with the conductive paste 13 are usually the surface of the metal layer, and the conductive paste 13 is usually an organic resin system. Therefore, the conductive adhesive 13 and the material which is in contact with the bonding are not a system, resulting in stickiness. The knot is weak. When the stress at the interface is too large, such as when the temperature of the application environment of the chip changes greatly, the stress generated during the thermal expansion and contraction of the material is likely to cause the bond of the chip and the substrate to fall off and cause delamination.
  • a sintered metal such as sintered silver.
  • the sintered metal is formed by sintering a metal particle at a high temperature (sintering temperature of 170 ° C - 300 ° C for sintered silver).
  • a specific bonding process is described by taking sintered silver as an example: a silver paste 23 is disposed between the semiconductor chip 21 and the substrate 22.
  • the silver paste 23 is composed of nano- or micro-scale silver powder particles 231 and an auxiliary solvent 232.
  • the auxiliary solvent 232 may be, for example, one of butyl anhydride acetate, diethylene glycol butyl ether acetate, diethylene glycol diethyl ether acetate, or isophorone. It should be understood that the auxiliary solvent 232 is not limited to the above list. Several solvents. The auxiliary solvent 232 has a certain volatility, which can be volatilized at a certain temperature, and the auxiliary solvent 232 has a certain lubricating effect in the silver paste 23, so that the silver powder particles 231 can flow.
  • the auxiliary solvent 232 is volatilized, and the nano- or micro-sized metal powder particles are agglomerated into the sintered silver block 24, and a large number of voids 25 remain in the sintered silver block 24.
  • Sintered metals have bonding, electrical and thermal conductivity functions. Moreover, the thermal conductivity of the sintered metal is higher than that of the conductive paste. For example, the thermal conductivity of the sintered silver reaches 100 w/m.k or more, completely overcoming the weakness of the thermal conductivity of the epoxy silver paste. In addition, during the sintering process, the sintered metal forms a metallic bond alloy with the metal at the interface with the interface, so that the sintered metal forms a good bond with the surface of the chip in contact with the substrate, thereby also solving the interface. The material is not a system that causes poor adhesion and is prone to the weakness of semiconductor chip and substrate delamination.
  • an effective means for verifying the internal layering of the semiconductor chip plastic package structure is an ultrasonic scanning microscope image, and the cavity inside the sintered metal and the ultrasonic layered image of the inner layer of the plastic sealing structure are difficult to distinguish, and therefore, the cavity interference existing inside the sintered metal
  • the layered inspection which results in the presence or absence of delamination inside the semiconductor chip molding structure, is less accurate.
  • the inner layer of the plastic sealing structure mainly refers to the layering between the semiconductor chip and the connecting structure and the layering between the connecting structure and the substrate.
  • the embodiment of the present application provides a semiconductor device. See the following examples for details.
  • the semiconductor device in the embodiment of the present application may have a plastic sealing structure.
  • FIG. 4 is a perspective view of a semiconductor device provided by an embodiment of the present application
  • FIG. 4 is a schematic cross-sectional view of a semiconductor device having a plastic package structure according to an embodiment of the present application.
  • the semiconductor device 400 includes:
  • the semiconductor device 400 further includes: a molding body 44 wrapped around the semiconductor chip 41 and the bonding layer 43;
  • the bonding layer 43 is composed of sintered silver; the interior of the sintered silver includes a plurality of voids 431, and at least a portion of the voids 431 are filled with a specific material 45 having a certain flow at a temperature higher than a preset temperature. Sex, and can be solidified after heating and melting.
  • curing molding means that a specific material undergoes a chemical crosslinking reaction inside the heating and melting to form a chemical crosslinking bond. After heating again, the solidified material does not melt flow.
  • the specific material 45 is injected from the outside of the adhesive layer 43 into the cavity, thereby achieving the effect of filling the void.
  • the number of voids 431 inside the sintered silver has a great relationship with the internal moisture accumulation of the entire semiconductor device.
  • the proportion of the filled void can be controlled by controlling the viscosity of the specific material.
  • the lower the viscosity of the material the better the fluidity and the better the fluidity.
  • a material with a low viscosity can be selected as the specific material for filling the void.
  • the specific material described in the embodiments of the present application may be a molding compound forming the molding body 44.
  • the filling of the voids can be performed simultaneously with the formation of the molding body, so that the step of filling the voids can be omitted, thereby simplifying the packaging process and reducing the packaging cost.
  • the main components of the molding compound are a resin, a filler, and a curing agent
  • other components of the molding compound may further include a catalyst, a releasing agent, and the like.
  • the molding compound can be flow-deformed only when the processing temperature is greater than the melting temperature of the resin. Therefore, in this embodiment, the preset temperature may be the melting temperature of the resin constituting the molding compound, and in order to make the molding compound have better fluidity.
  • the preset temperature may be a temperature higher than a certain temperature of the melting temperature, which is not limited by the embodiment of the present application.
  • the internal resin chemically reacts with the curing agent, so that the molding compound can be solidified and molded.
  • the particular material may also be other materials, such as silicone-based materials and the like.
  • the cavity filled with the specific material accounts for more than 85%, or even more than 90% of all the voids. .
  • more than 85% or even more than 90% of the voids are filled with specific materials.
  • the proportion of voids filled with a specific material can be controlled by controlling the viscosity of the molding compound during the molding process.
  • the lower the viscosity of the molding compound the more the molding compound can flow into the cavity, thereby being coated with a specific material. The proportion of filled voids will be higher.
  • the back surface of the semiconductor chip 41 is bonded to the substrate 42.
  • the back surface of the semiconductor chip 41 refers to the side opposite to the surface on which the active region of the chip is located.
  • the surface of the semiconductor chip bonded to the bonding layer 43 is provided with a first metal layer 411, and the first metal layer 411 and the bonding layer 43 are formed by a metal bonding force.
  • a metal layer is generally disposed on the surface of the substrate 42 bonded to the bonding layer 43.
  • the silver in the silver paste forms a metal bond on the surface of the metal layer in contact therewith.
  • the bonding is performed to form a metal alloy layer between the substrate 42 and the bonding layer 43.
  • the surface of the substrate bonded to the bonding layer 43 is provided with a second metal layer 421 between the second metal layer 421 and the bonding layer 43 due to the metal bonding force.
  • a second metal alloy layer 47 is formed.
  • the metal material constituting the first metal layer 411 may be gold, because gold is not easily oxidized, it is difficult to react with other materials at normal temperature, and gold has
  • the first metal layer may be other metals such as silver, tin or copper.
  • the metal material constituting the second metal layer 431 may be gold, silver, tin or copper.
  • the metal material constituting the first metal layer 411 or the second metal layer 431 may also be other metals that can form a metal alloy layer with the bonding layer, and the present application does not make metal types of the first metal layer and the second metal layer. limit.
  • the molding body 44 may include a periphery of the substrate 42 in addition to the semiconductor chip 41 and the bonding layer 43, thereby protecting the substrate 42 from external damage to the substrate 42.
  • the bonding layer 43 for connecting the semiconductor chip 41 and the substrate 42 is formed by using sintered silver, and the sintered silver has good electrical and thermal conductivity, wherein the thermal conductivity reaches 100 w/m.k or more. Therefore, the heat generated by the operation of the semiconductor chip 41 can be dissipated to the outside of the semiconductor device through the bonding layer 43 and the substrate 42, thereby reducing the overall thermal resistance of the semiconductor chip 41 from the front PN junction to the chip housing, thereby facilitating the improvement of the semiconductor.
  • the service life of the chip 41 it is also advantageous to increase the input power of the semiconductor chip, increase the power density of the semiconductor chip, and increase the power consumption of the semiconductor chip.
  • At least a part of the cavity 431 existing inside the sintered metal is filled with a specific material.
  • the ultrasonic scanning microscope image of the cavity after filling is significantly different from the ultrasonic scanning microscope image of the inner layer of the semiconductor chip plastic-molded structure, based on which ultrasonic scanning is performed.
  • the microscope image can easily eliminate the image of the filled cavity, thereby reducing the interference of the layered detection. Therefore, the detection accuracy of the internal layer of the semiconductor chip plastic package provided by the embodiment of the present application is high.
  • the back surface of the semiconductor chip 41 is usually a metal layer surface, which belongs to a metal system
  • the bonding layer 43 is composed of sintered silver, which also belongs to a metal system, in the process of forming the bonding layer 43, silver is sintered.
  • the metal on the surface of the semiconductor chip 41 that is in contact therewith forms a metal bond, so that a strong connection between the semiconductor chip 41 and the adhesive layer 43 can be formed, and the formation of the secure connection can reduce the semiconductor chip 41 and the adhesive layer 43.
  • a strong connection is formed between the substrate 42 and the bonding layer 43, and the formation of the secure connection can also reduce the possibility of delamination between the substrate 42 and the bonding layer 43.
  • the bonding layer 43 is not limited to a sintered silver material, which may be made of any kind of sintered metal.
  • a semiconductor device in which the bonding layer 43 is made of a sintered metal made of a metal powder sintering process is within the scope of protection of the present application.
  • the metal powder may include at least one of nano-scale and micro-scale metal particles.
  • the embodiment of the present application further provides a specific implementation manner of a method for fabricating a semiconductor device. See the following examples for details.
  • a method for fabricating a semiconductor device includes the following steps:
  • S501 The semiconductor chip 41 is bonded to the substrate 42 using the original slurry 61 of sintered silver.
  • the semiconductor chip 41 may be bonded to the substrate 42 by a sintered silver paste 61 using a die bonder.
  • S501 may specifically be: coating the original slurry of sintered silver on the substrate 42, and then placing the semiconductor chip 41 adsorbed thereon onto the substrate 42 by using a die bonder.
  • the original silver paste 61 is sintered, and thus, the process of bonding the semiconductor chip 41 to the substrate 42 is completed.
  • the raw slurry 61 of sintered silver is composed of nano- or micro-scale silver powder particles 611 and auxiliary auxiliary 612.
  • the auxiliary auxiliary agent 612 may be one of butyl anhydride acetate, diethylene glycol butyl ether acetate, diethylene glycol diethyl ether acetate or isophorone.
  • the sintered silver raw slurry 61 is cured to form a bonding layer 43 that bonds the semiconductor chip 41 and the substrate 42, and the bonding layer 43 is composed of solidified sintered silver, and the interior of the sintered silver includes a plurality of voids 431.
  • This step may be specifically: curing and sintering the sintered silver original slurry 61 (also referred to as sintered silver paste) in an oven or on a heating table according to the furnace temperature curve of the sintered silver and the corresponding baking gas.
  • the auxiliary solvent 612 in the sintered silver raw slurry 61 is emitted, and the nano- or micro-sized silver powder particles 611 are agglomerated into a sintered silver block, thereby forming a bonding layer connecting the semiconductor chip 41 and the substrate 42. 43.
  • the bonding layer 43 is composed of solidified sintered silver, and the interior of the sintered silver includes a plurality of voids 431.
  • the method for fabricating the semiconductor device according to the embodiment of the present application may further include the following steps. :
  • the first metal alloy layer 46 is sintered between the first metal layer 411 and the bonding layer 43 while curing the sintered silver original slurry 61.
  • the metal atoms in the first metal layer 411 bond with the silver in the sintered silver to form a metal bond under the action of high-temperature sintering, so that The first metal alloy layer 46 is sintered between the first metal layer 411 and the bonding layer 43.
  • the method for fabricating the semiconductor device according to the embodiment of the present application may further include the following steps:
  • the second metal alloy layer 47 is sintered between the second metal layer 421 and the bonding layer 43 while curing the sintered silver original slurry 61.
  • the metal atoms in the second metal layer 421 bond with the silver in the sintered silver to form a metal bond under the action of high-temperature sintering, so that The first metal alloy layer 47 is formed by sintering between the second metal layer 421 and the bonding layer 43.
  • FIG. 6B A schematic diagram of the corresponding cross-sectional structure performed in this step is shown in FIG. 6B.
  • S503 Fill at least part of the cavity 431 with a specific material.
  • the specific material has a certain fluidity when it is higher than the preset temperature, and can be solidified and molded after being heated and melted.
  • the embodiment of the present application selects a material with better fluidity as a specific material for filling voids.
  • the specific material may be a mold material having better fluidity.
  • the particular material selected can fill at least a portion of the void.
  • the selected specific material can fill more than 85% or more and even more than 90% of the cavity.
  • step S503 may specifically include the following steps:
  • S5031 Heating a specific material to a temperature higher than a preset temperature to make a specific material into a fluid that can flow.
  • S5032 Injecting a fluid that can flow into at least a portion of the void within the bonding layer.
  • the capillary force refers to the phenomenon that the immersion liquid rises in the thin tube and the non-wetting liquid is lowered in the thin tube.
  • the phenomenon Among them, the catheter in the stem of the plant is a very fine capillary in the plant body, which can suck up the moisture in the soil, and the bricks absorb water, the towel absorbs sweat, and the pen ink absorbs the common capillary phenomenon. There are many small pores in these objects that act as capillaries. The combination of surface tension, cohesion and adhesion of the liquid allows the water to rise to a certain height in the smaller diameter capillary, called capillary phenomenon.
  • the capillary force is a force that enables the fluid to automatically rise in the capillary.
  • the voids existing in the adhesive layer are openings having a very small diameter. Therefore, the structure of the void is similar to that of the capillary, so that the adhesive layer structure is placed inside the fluid capable of flowing, in the capillary Under force, the fluid can be injected into at least a portion of the void within the bonding layer.
  • S5033 The structure filled with a specific material is placed under a certain temperature condition to post-cure the fluid injected into the cavity.
  • the temperature and time at the time of post-cure can be determined according to the properties of the specific material itself.
  • the temperature at the time of post-cure may be related to the melting temperature of the resin inside the specific material and the curing temperature of the curing agent.
  • FIG. 6C A schematic cross-sectional structure corresponding to the execution of this step is shown in Fig. 6C.
  • S504 The semiconductor chips 41 and the substrate 42 connected together are molded and packaged by using a molding compound to form a molding body 44 wrapped around the periphery of the semiconductor chip 41 and the bonding layer 43.
  • This step may be specifically: selecting a suitable molding temperature according to the properties of the molding compound, and molding and packaging the semiconductor chips 41 and the substrate 42 connected together to form a plastic package surrounding the periphery of the semiconductor chip 41 and the bonding layer 43. Body 44.
  • the resulting structure is shown in Figure 4.
  • a molding body encasing the substrate 42 may be formed on the periphery of the substrate 42, thereby protecting the substrate 42 from external damage to the substrate 42.
  • a metal bonding wire 48 connecting the front surface of the semiconductor chip 41 and the substrate 42 is formed. and many more. It should be understood that the metal bond wires 48 are metal leads for electrically connecting the pads on the front side of the semiconductor chip 41 to the pads on the substrate 42.
  • the molded semiconductor chip molding structure is placed under the corresponding temperature and atmosphere conditions, and the molding body 44 is shaped and solidified to finally obtain a cured molded semiconductor chip plastic sealing structure.
  • the filling of the voids in the sintered silver is accomplished by a specialized filling process.
  • the specific material filled in the cavity can be a molding compound, in order to simplify the packaging process and reduce the packaging cost, the cavity filling process can be simultaneously performed in the molding and packaging process. See the following examples for details.
  • a method for fabricating another semiconductor device includes the following steps:
  • S701 to S702 are the same as S501 to S502 in the above embodiment, and will not be described in detail herein for the sake of brevity.
  • S703 molding and bonding the bonded semiconductor chip 41 and the substrate 42 with a molding compound to form a molding body 44 wrapped around the semiconductor chip 41 and the bonding layer 43, and molding the package while molding The material flows into at least a portion of the void 431 such that at least a portion of the void 431 is filled with a molding compound.
  • the molding compound in a molten state can flow into at least a part of the cavity under the action of the molding pressure and the capillary force, so that at least part of the cavity
  • the cavity is filled with a molding compound.
  • the molding compound in a molten state flows into the cavity, thereby achieving void filling.
  • the molding compound flows into the cavity under the action of the molding pressure and the capillary force. Compared with the case where only the capillary force is applied, the filling of the cavity is realized by the molding and packaging process, and a better filling effect can be achieved.
  • S704 is the same as S505 described above, and will not be described in detail herein for the sake of brevity.
  • the above is a specific implementation manner of a method for fabricating another semiconductor device provided by the embodiment of the present application.
  • the filling of the voids is completed simultaneously in the process of molding and packaging, thereby reducing a void filling process, simplifying the packaging process, and reducing the packaging cost.

Landscapes

  • Die Bonding (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)

Abstract

一种半导体装置(400)及其制备方法，该半导体装置(400)中，用于粘结半导体芯片(41)和基板(42)的粘结层(43)由高导电和导热的金属粉末烧结工艺制成的烧结金属构成，并且存在于烧结金属内部的至少部分空洞(431)内填充有特定材料。如此，空洞(431)被特定材料填充后，有利于减少潮气的容纳，因而减少了当半导体装置(400)经过回流焊贴装到印刷线路板上时，引起的芯片(41)和基板(42)的分层的可能性。另外，填充后的空洞(431)不会干扰分层的检测结果，因而提高了半导体装置(400)分层检测结果的准确性。

Description

一种具有高稳定性粘结层的半导体装置及其制备方法 技术领域
本申请涉及半导体芯片封装技术领域，尤其涉及一种半导体装置及其制备方法。
背景技术
由于环氧成型化合物(Epoxy Molding Compound,EMC)的材料成本较低，又适合大规模自动化生产，因此，半导体芯片通常采用EMC封装。采用EMC封装得到的结构称为EMC封装结构或塑封结构。
目前，业界采用的半导体芯片塑封结构存在以下缺陷：
第一：当半导体芯片塑封结构长时间暴露在潮湿的环境中后，当半导体芯片塑封结构器件经过回流焊贴装到印刷线路板上时，有可能会引起半导体芯片和线路基板的粘结材料失效，导致两者分层。
第二：半导体芯片塑封结构内部是否存在分层的检测准确性较低。
发明内容
有鉴于此，本申请实施例提供了一种半导体装置及其制备方法，以克服上述缺陷。
为了解决上述技术问题，本申请采用了如下技术方案：
本申请的第一方面提供了一种半导体装置，包括：
半导体芯片、基板以及位于该半导体芯片和该基板之间用于粘结该半导体芯片和该基板的粘结层；该粘结层包括烧结金属；该烧结金属的内部包括多个空洞，至少部分空洞内填充有特定材料；其中，该特定材料在高于预设温度时，具有一定的流动性，并且在加热熔融后能够固化成型。
本申请提供的半导体装置由于烧结金属内部的至少部分空洞内填充有特定材料，降低了外界环境中的潮气聚集在半导体装置内部的概率，减少了当半导体装置经过回流焊(reflow)贴装到印刷线路板上时，引起的芯片和基板的分层的可能性；另外，填充有特定材料的空洞的超声波扫描显微镜图像与半导体内部分层的图像有明显区别，因此该半导体装置的内部分层的检测准确性较高。
结合本申请的第一方面，在第一种可能的实施方式中，该半导体装置还包括：包裹在该半导体芯片和该粘结层外围的塑封体，该特定材料与形成该塑封体对应的塑封料相同。
该实施方式中，塑封体能够保护其内部的半导体芯片和粘结层，从而，能够提高半导体装置的可靠性。并且该实施方式能够简化半导体装置的制作工艺，降低制作成本。
结合本申请的第一方面及其第一种可能的实施方式中，在第二种可能的实施方式中，所述烧结金属内部85％以上的空洞填充有所述特定材料。
结合本申请的第一方面的第二种可能的实施方式中，在第三种可能的实施方式中，所述烧结金属内部90％以上的空洞填充有所述特定材料。
当更高比例的空洞被特定材料填充时，因空洞容纳潮气而导致的分层可能性更低，通 过超声波扫描显微镜检测内部分层状况的准确性更高。
结合本申请的第一方面及其上述各种可能的实施方式中，在第四种可能的实施方式中，在该半导体芯片与该粘结层相粘结的表面上设置有第一金属层，该第一金属层与该粘结层之间由于金属键合力形成第一金属合金层。
该实施方式能够提高半导体芯片与粘结层之间的连接性能，降低两者之间分层的可能。
结合本申请的第一方面及其上述各种可能的实施方式中，在第五种可能的实施方式中，与该粘结层相粘结的基板表面上设置有第二金属层，该第二金属层与该粘结层之间由于金属键合力形成第二金属合金层。
该实施方式能够提高基板与粘结层之间的连接性能，降低两者之间分层的可能。
结合本申请的第一方面，在第六种可能的实施方式中，特定材料是在通过烧结固化工艺形成粘结层之后，从该粘结层的外部引入到空洞内，从而达到填充空洞的效果。
结合本申请的第一方面及其上述各种可能的实施方式中，在第七种可能的实施方式中，该烧结金属为烧结银。该实施方式能够提高粘结层的导热、导电性能。
结合本申请的第一方面及其上述各种可能的实施方式，在第八种可能的实施方式中，该金属粉末包括：纳米级和微米级的金属颗粒中的至少一项。
结合本申请的第一方面及其上述各种可能的实施方式，在第九种可能的实施方式中，烧结金属由金属粉末经过烧结工艺制成。
本申请的第二方面提供了一种半导体装置的制备方法，所述制备方法包括：
通过烧结固化工艺在半导体芯片和基板之间形成粘结层，该粘结层用于粘结该半导体芯片和该基板，其中该粘结层由烧结金属组成，该烧结金属内部包括多个空洞；采用特定材料填充至少部分该空洞；该特定材料在高于预设温度时，具有一定的流动性，并且在加热熔融后能够固化成型。
由于烧结金属内部的至少部分空洞内填充有特定材料，降低了外界环境中的潮气聚集在半导体装置内部的概率，减少了当半导体装置经过回流焊(reflow)贴装到印刷线路板上时，引起的芯片和基板的分层的可能性；另外，填充有特定材料的空洞的超声波扫描显微镜图像与半导体内部分层的图像有明显区别，因此该半导体装置的内部分层的检测准确性较高。
结合本申请的第二方面，在第一种可能的实施方式中，所述制备方法还包括：形成包裹该半导体芯片和该粘结层的塑封体，且特定材料与该塑封体对应的塑封料相同。
该可能的实施方式中，塑封体能够保护其内部的半导体芯片和粘结层，从而，能够提高半导体装置的可靠性。
结合本申请的第二方面的第一种可能的实施方式，在第二种可能的实施方式中，所述采用特定材料填充至少部分该空洞，具体包括：在形成所述塑封体的同时，流动的塑封料流入所述至少部分所述空洞内，以使得所述至少部分所述空洞内填充有所述塑封料。
该可能的实施方式能够简化半导体装置的封装工艺，降低封装成本。
结合本申请的第二方面及其上述各种可能的实施方式，在第三种可能的实施方式中，所述形成包裹该半导体芯片和该粘结层的塑封体之后，还包括：对该塑封体进行定型固化。
结合本申请的第二方面，在第四种可能的实施方式中，所述采用特定材料填充至少部分该空洞，具体包括：加热该特定材料至高于该预设温度，以使该特定材料能够流动；将该能够流动的特定材料注入到该粘结层内的至少部分空洞内。
该可能的实施方式能够提高空洞的填充效果。
结合本申请的第二方面的第四种可能的实施方式，在第五种可能的实施方式中，所述利用毛细作用力将该流体注入到该粘结层内的至少部分空洞内之后，还包括：
将填充有该特定材料的结构放置到一定温度条件下，对注入到空洞内的流体进行后固化。该可能的实施方式能够提高半导体装置的可靠性。
结合本申请的第二方面及其上述各种可能的实施方式，在第六种可能的实施方式中，所述烧结金属内部85％以上的空洞填充有所述特定材料。
该可能的实施方式能够减少当半导体装置经过回流焊(reflow)贴装到印刷线路板上时，引起的芯片和基板的分层的可能性。以及提高半导体装置的内部分层的检测准确性。
结合本申请的第二方面及其上述各种可能的实施方式，在第七种可能的实施方式中，与所述粘结层相粘结的半导体芯片表面上设置有第一金属层，所述第一金属层与所述粘结层之间由于金属键合力形成第一金属合金层。
该可能的实施方式能够提高半导体芯片与粘结层之间的连接性能，降低两者之间分层的可能。
结合本申请的第二方面及其上述各种可能的实施方式，在第八种可能的实施方式中，与所述粘结层相粘结的基板表面上设置有第二金属层，所述第二金属层与所述粘结层之间由于金属键合力形成第二金属合金层。
该可能的实施方式能够提高基板与粘结层之间的连接性能，降低两者之间分层的可能。
结合本申请的第二方面及其上述各种可能的实施方式，在第九种可能的实施方式中，所述烧结金属为烧结银。
相较于现有技术，本申请具有以下有益效果：
基于上述技术方案可知，本申请实施例提供的半导体装置中，用于粘结半导体芯片和线路基板的粘结层由高导电和导热的金属粉末烧结工艺制成的烧结金属构成。并且，在本申请实施例中，存在于烧结金属内部的至少部分空洞内填充有特定材料。如此，空洞被特定材料填充后，有利于减少潮气的容纳，避免外界环境中的较大规模的潮气聚集在半导体芯片塑封结构内部，进一步的，避免由于外界湿气在内部的聚集导致芯片和基板的分层。因此，当该半导体装置暴露在潮湿的环境中后，外界环境中的潮气聚集在半导体塑封结构内部的概率大大降低，因而减少了当半导体装置经过回流焊(reflow)贴装到印刷线路板上时，引起的芯片和基板的分层的可能性。
另外，半导体装置内部是否存在分层的检测手段为超声波扫描显微镜检测(Scanning Acoustic Tomography,或SAT)，而烧结金属的空洞和分层的超声波扫描显微镜图像很难区分，而填充后烧结金属的空洞的超声波扫描显微镜图像与半导体装置内部芯片和线路基板分层的超声波扫描显微镜图像具有明显区别，基于此通过超声波扫描显微镜图像可以很 容易将填充后的空洞的图像排除掉，从而降低了对分层检测的干扰，因此，本申请实施例提供的半导体装置的内部分层的检测准确性较高。
附图说明
图1是本领域常用的半导体芯片塑封结构示意图；
图2是本领域采用烧结银连接半导体芯片和线路基板的结构示意图；
图3是半导体芯片塑封结构发生内部分层的原理示意图；
图4’是本申请实施例提供的半导体装置立体透视图；
图4是本申请实施例提供的一种半导体装置剖面示意图；
图5是本申请实施例提供的一种半导体装置的制备方法的流程示意图；
图6A至图6C是本申请实施例提供的一种半导体装置的制备方法的一系列制程对应的剖面结构示意图；
图7是本申请实施例提供的另一种半导体装置的制备方法的流程示意图。
附图标记：
11、21、41：半导体芯片，
12、22、42：基板，
13：导电胶，
23：银浆，
231、611：纳米级或微米级银粉末颗粒，
232、612：辅助溶剂，
24：烧结银块，
400：半导体芯片塑封结构，
43：粘结层(例如烧结银结构)，
44：塑封体，
45：特定材料，
431：空洞，
411：第一金属层，
421：第二金属层，
46：第一金属合金层，
47：第二金属合金层，
48：金属键合线，
61：烧结银的原始浆料。
具体实施方式
应当理解，在本申请中，“至少一个(项)”是指一个或者多个，“多个”是指两个或两个以上。“和/或”，用于描述关联对象的关联关系，表示可以存在三种关系，例如，“A和/或B”可以表示：只存在A，只存在B以及同时存在A和B三种情况，其中A，B可以是单 数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。“以下至少一项(个)”或其类似表达，是指这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b或c中的至少一项(个)，可以表示：a，b，c，“a和b”，“a和c”，“b和c”，或“a和b和c”，其中a，b，c可以是单个，也可以是多个。
半导体芯片塑封结构通常如图1所示，包括半导体芯片11和基板12，半导体芯片11通常采用导电胶13粘结在基板12上。作为示例，基板12可以为印刷线路板或陶瓷类的线路板。在一种可选的情况中，当基板为印刷线路板或陶瓷类的线路板时，该线路板可用于敷设印刷电路从而实现电信号的传递。此外，由于半导体芯片11在工作时，会产生热量，而半导体芯片的主要散热途径是传导散热，线路板还可以起到散热作用，将半导体芯片11产生的热量传递到塑封结构的外侧，具体地，如图1所示，半导体芯片11产生的热量可以经由半导体芯片11下方的导电胶13和基板12传导并散发出去。
由于环氧树脂银胶(Silver epoxy)在粘片时具有操作简单、性能稳定且具有良好的导电性能，因此，环氧树脂银胶通常作为半导体芯片塑封中常用的材料。。然而，环氧树脂银胶的导热系数较低，一般小于10瓦/米·度(w/m·k)，在高功率芯片应用中，环氧树脂银胶不能快速、有效地将半导体芯片11工作时产生的热量散发出去，会导致半导体芯片的PN结(PN junction)的温度(下称结温)升高，进而缩短芯片的使用寿命。另外，与导电胶13接触的半导体芯片11表面和基板12表面通常为金属层表面，而导电胶13通常为有机树脂体系，因此，导电胶13和其接触粘结的材料不是一个体系，导致粘结性较弱。当界面处应力过大，比如芯片应用环境温度变化较大时产生的材料热胀冷缩时的应力，容易产生芯片和基板的粘结脱落，产生分层。
为了解决导电胶的缺陷，近年来，另一种新型粘结材料出现并应用于EMC封装中，该新型粘结材料为烧结金属，例如烧结银。烧结金属是金属颗粒在高温下(针对烧结银来说，其烧结温度为170℃-300℃)烧结形成的。如图2所示，以烧结银为例说明具体粘结过程：在半导体芯片21和基板22之间设置有银浆23。银浆23由纳米级或微米级银粉末颗粒231和辅助溶剂232组成。辅助溶剂232例如可以为：丁基溶酐乙酸酯、二乙二醇丁醚醋酸酯、二甘醇乙醚醋酸酯、或异佛尔酮中的一项，应当理解，辅助溶剂232不局限于上述列举的几种溶剂。辅助溶剂232具有一定的挥发性，其能够在一定温度下挥发，并且辅助溶剂232在银浆23中具有一定的润滑作用，从而使得银粉末颗粒231能够流动。
银浆23经过高温下烘烤后，辅助溶剂232挥发完毕，纳米级或微米级金属粉末颗粒结晶团聚成烧结银块24，在烧结银块24内部残留有很多空洞25。
烧结金属具有粘结、导电和导热功能。并且，相较于导电胶，烧结金属的导热率较高，例如，烧结银的导热率达到了100w/m.k以上，完全克服了环氧银胶的导热率不高的弱点。此外，烧结金属在烧结过程中，会与其接触界面的金属形成金属键合金(metallic bond alloy)，如此，烧结金属会与其接触的芯片表面和基板表面形成良好的粘结，因而，也解决了界面材料不是一个体系造成的粘结性差、容易产生半导体芯片和基板分层的弱点。
然而，采用烧结金属粘结半导体芯片和基板的半导体芯片塑封结构存在背景技术中所述的缺陷，具体如下：
第一：当半导体芯片塑封结构长时间暴露在潮湿的环境中后，当半导体芯片塑封结构器件经过回流焊贴装到印刷线路板上时，有可能会引起芯片和基板的分层。
第二：半导体芯片塑封结构内部是否存在分层的检测准确性较低。
烧结金属在高温烧结成型的过程中，会产生大量的空洞(void)，即烧结金属内部充满了大量空洞。当采用烧结金属来粘结半导体芯片和基板时，该空洞就会存在于半导体芯片塑封结构中。如此，当该半导体芯片塑封结构长时间暴露在潮湿的空气中，潮湿的空气会聚集到烧结金属空洞内，使得烧结金属空洞内的气体环境会达到和塑封结构外界气体环境一致。参见图3，如果塑封结构器件在贴片前没有加入器件烘烤除湿步骤，当塑封结构器件经过回流焊贴装到印刷线路板上时内部容易产生由空洞内湿气迅速热膨胀带来的压力，引发芯片和基板的分层，严重的甚至导致塑封结构器件爆裂。
目前，验证半导体芯片塑封结构内部分层的有效手段是超声波扫描显微镜图像，而烧结金属内部的空洞和塑封结构内部分层的超声波扫描显微镜图像很难区分，因此，存在于烧结金属内部的空洞干扰了分层的检测，如此导致半导体芯片塑封结构内部是否存在分层的检测准确性较低。
需要说明，在本申请实施例中，塑封结构内部分层主要是指半导体芯片与连接结构之间的分层以及连接结构与基板之间的分层。
为了解决半导体芯片塑封结构的上述缺陷，本申请实施例提供了一种半导体装置。具体参见以下实施例。
需要说明，在一种可选的情况中，本申请实施例中的半导体装置可以具有塑封结构。
图4’是本申请实施例提供的半导体装置立体透视图；图4为本申请实施例提供的具有塑封结构的半导体装置剖面示意图。如图4’和图4所示，该半导体装置400包括：
半导体芯片41、基板42以及位于半导体芯片41和基板42之间用于粘结半导体芯片41和基板42的粘结层43；
该半导体装置400还包括：包裹在半导体芯片41和粘结层43外围的塑封体44；
其中，所述粘结层43由烧结银构成；该烧结银的内部包括多个空洞431，至少部分空洞431内填充有特定材料45，该特定材料在高于预设温度时，具有一定的流动性，并且在加热熔融后能够固化成型。
需要说明，在本申请实施例中，所谓固化成型是指特定材料在加热熔融后，其内部会发生化学交联反应，形成化学交联键。再次加热后，固化成型的材料不会熔融流动。
在本申请实施例中，可以在通过烧结固化工艺形成粘结层43之后，将特定材料45从粘结层43的外部注入到空洞内，从而达到填充空洞的效果。
此外，烧结银内部的空洞431的多少与整个半导体装置的外界湿气在内部聚集有很大关系。空洞越少，外界湿气在内部聚集越少，空洞越多，外界湿气在内部聚集越多。因此，为了使得整个半导体装置免于由于外界湿气在内部的聚集导致芯片和基板的分层，作为本申请的一个可选实施例，特定材料在高于预设温度时，可以具有较好的流动性，从而使特定材料能够流入到尽可能多的空洞内，填充尽可能多的空洞，进而减少整个半导体装置内 部的空洞，最终使得半导体装置内部聚集的湿气为零或者很少，去除半导体装置的芯片和基板的分层风险。在本申请实施例中，可以通过控制特定材料的粘度来控制被填充的空洞的比例数，在一种可选的情况中，材料的粘度越低，其流动性越好，流动性越好的材料越能够流入更多的空洞内，从而使更多的空洞被填充，示例性的，为了能够使尽可能多的空洞被填充，可以选用粘度低的材料作为填充空洞的特定材料。
作为本申请的另一个可选实施例，为了简化封装工艺，降低封装成本，本申请实施例所述的特定材料可以为形成塑封体44的塑封料。如此，空洞的填充可以与形成塑封体同时进行，因而可以省略填充空洞的步骤，从而达到简化封装工艺，降低封装成本的目的。
此外，因塑封料的主要成分为树脂、填料和固化剂，此外，塑封料的其它成分还可以包括催化剂、脱模剂等等。只有当加工温度大于树脂的熔融温度时，塑封料才能流动变形，因此，在该实施例中，预设温度可以为组成塑封料的树脂的熔融温度，而且为了使得塑封料具有较好的流动性，该预设温度可以为高于熔融温度一定幅度的温度，本申请实施例对此不做限定。
而且，塑封料在加热熔融后，内部的树脂与固化剂发生化学反应，从而使得塑封料能够固化成型。
在另一种可选的情况中，特定材料还可以为其它材料，例如硅胶类材料等。
此外，作为本申请的另一可选实施例，为了能够确保本申请实施例提供的半导体装置能够克服前述所述的缺陷，填充有特定材料的空洞占所有空洞的85％以上，甚至90％以上。换句话说，有85％以上甚至90％以上的空洞内填充有特定材料。示例性的，可以通过控制塑封过程中塑封料的粘度来控制填充有特定材料的空洞的比例，示例性的，塑封料的粘度越低，可流入空洞内的塑封料越多，从而被特定材料填充的空洞的比例将会越高。
此外，在本申请实施例中，半导体芯片41中，可选的，与基板42粘结在一起的是半导体芯片41的背面。需要说明，半导体芯片41的背面是指与芯片有源区(active region)所在的表面相对的一面。当半导体芯片41的背面上设置有金属层时，也就是说与粘结层43相粘结的半导体芯片表面上设置有金属层时，在烧结银的银浆料的烧结过程中，银浆料中的银颗粒会与半导体芯片41背面的金属层之间形成金属键合键，从而形成金属合金层。如此，作为本申请的一个可选实施例，与粘结层43相粘结的半导体芯片表面上设置有第一金属层411，第一金属层411与粘结层43之间由于金属键合力形成有第一金属合金层46。
此外，与粘结层43相粘结的基板42表面上一般也设置有金属层，在烧结银的银浆料的烧结过程中，银浆料中的银会与其接触的金属层表面形成金属键合键，从而在基板42与粘结层43之间形成金属合金层。如此，作为本申请的一个可选实施例，与粘结层43接相粘结的基板表面上设置有第二金属层421，在第二金属层421和粘结层43之间由于金属键合力形成有第二金属合金层47。
在一种可选的情况中，在本申请实施例中，组成第一金属层411的金属材料可以为金，这是因为金不易发生氧化，在常温下不易与其它材料发生反应，而且金具有较好的粘结性能，可选的，第一金属层也可以为银、锡或铜等其他金属。可选的，组成第二金属层431的金属材料可以为金、银、锡或铜。此外，组成第一金属层411或第二金属层431的金属 材料也可以是其他可与粘结层生成金属合金层的金属，本申请对第一金属层和第二金属层的金属类型不做限制。
此外，作为本申请的另一可选实施例，塑封体44除了包裹半导体芯片41和粘结层43之外，还可以包括基板42的外围，从而保护基板42，防止外力对基板42的破坏。
以上为本申请实施例提供的半导体装置的具体实现方式。在该具体实现方式中，采用烧结银形成用于连接半导体芯片41和基板42的粘结层43，因烧结银具有良好的导电导热性能，其中，导热率达到了100w/m.k以上。因此，半导体芯片41工作时产生的热量，能够通过粘结层43和基板42散发到半导体装置的外部，从而降低了半导体芯片41从其正面PN结到芯片外壳的整体热阻，有利于提高半导体芯片41的使用寿命。此外，也有利于增大半导体芯片的输入功率，提升半导体芯片的功率密度，提升半导体芯片的使用功率。
此外，在本申请实施例中，存在于烧结金属内部的至少部分空洞431内填充有特定材料。如此，空洞431被特定材料填充后，有利于减少潮气的容纳，避免外界环境中的潮气聚集在半导体芯片塑封结构内部，进一步的，避免由于外界湿气在内部的聚集导致芯片和基板的分层。因此，当该半导体塑封结构暴露在潮湿的环境中后，外界环境中的潮气聚集在半导体塑封结构内部的概率大大降低，因而减少了当半导体装置经过回流焊贴装到印刷线路板上时，引起的半导体芯片41与基板42的分层的可能性。
另外，当采用超声波扫描显微镜检测半导体芯片塑封结构内部是否存在分层时，因填充后空洞的超声波扫描显微镜图像与半导体芯片塑封结构内部分层的超声波扫描显微镜图像具有明显区别，基于此通过超声波扫描显微镜图像可以很容易将填充后的空洞的图像排除掉，从而降低了对分层检测的干扰，因此，本申请实施例提供的半导体芯片塑封结构的内部分层的检测准确性较高。
此外，在申请实施例中，因半导体芯片41背面通常为金属层表面，属于金属体系，而粘结层43由烧结银组成，也属于金属体系，在粘结层43形成的过程中，烧结银会与其接触的半导体芯片41表面上的金属形成金属键合键，从而能够使半导体芯片41与粘结层43之间形成牢固的连接，该牢固连接的形成能够减少半导体芯片41与粘结层43之间的分层的可能。
基于上述相同的原理，基板42与粘结层43之间形成牢固的连接，该牢固连接的形成也能够减少基板42与粘结层43之间的分层的可能。
需要说明，在上述实施例中，以烧结银为例说明粘结层43的具体结构。实际上，作为本申请实施例的扩展，粘结层43不限于烧结银材料，其可以为任何种类的烧结金属制成。如此，只要粘结层43由金属粉末烧结工艺制成的烧结金属构成的半导体装置均在本申请的保护范围之列。作为示例，当粘结层由金属粉末烧结工艺制成的烧结金属构成时，该金属粉末可以包括纳米级和微米级的金属颗粒中的至少一种。
以上为本申请实施例提供的半导体装置的具体实现方式。基于该半导体装置的具体实现方式，本申请实施例还提供了一种半导体装置的制备方法的具体实现方式。具体参见以下实施例。
需要说明，在本申请实施例中，以烧结银作为烧结金属的示例来描述本申请实施例提 供的半导体装置的制备方法的具体实现方式。此外，当采用烧结银以外的其它种类的烧结金属应用于本申请实施例时，该具体实现方式与采用烧结银的具体实现方式相同，其不同之处在于烧结金属的固化成型条件不同。因此，本领域技术人员根据烧结银的具体实现方式很容易想到采用其它种类的烧结金属的实现方式，在此不再详细描述其它种类的烧结金属的具体实现方式。
请参见图5至图6C，本申请实施例提供的一种半导体装置的制备方法包括以下步骤：
S501：采用烧结银的原始浆料61将半导体芯片41粘结在基板42上。
作为示例，如图6A所示。可以采用芯片粘片机(die bonder)通过烧结银的原始浆料61将半导体芯片41粘结在基板42上。
作为本申请的一具体示例，S501可以具体为：将烧结银的原始浆料涂覆在基板42上，然后，采用芯片粘片机将其吸附的半导体芯片41放置到涂覆在基板42上方的烧结银的原始浆料61上，如此，完成将半导体芯片41粘结在基板42上的过程。
需要说明，在本申请实施例中，烧结银的原始浆料61由纳米级或微米级银粉颗粒611和辅助助剂612组成。作为示例，辅助助剂612可以为：丁基溶酐乙酸酯、二乙二醇丁醚醋酸酯、二甘醇乙醚醋酸酯或异氟尔酮中的一种等。
S502：固化烧结银的原始浆料61，以形成粘结半导体芯片41和基板42的粘结层43，粘结层43由固化成型的烧结银组成，该烧结银的内部包括多个空洞431。
本步骤可以具体为：根据烧结银的炉温曲线以及相应的烘烤气体，在烤箱内或加热台上对烧结银的原始浆料61(也可以称为烧结银浆)进行固化烧结。在固化烧结过程中，烧结银的原始浆料61内的辅助溶剂612会发掉，纳米级或微米级银粉颗粒611结晶团聚成烧结银块，从而形成连接半导体芯片41和基板42的粘结层43。如此，该粘结层43由固化成型的烧结银组成，该烧结银的内部包括多个空洞431。
作为本申请的一可选实施例，当与粘结层43相粘结的半导体芯片表面上设置有第一金属层411时，本申请实施例所述的半导体装置的制备方法还可以包括以下步骤：
在固化烧结银的原始浆料61的同时，在第一金属层411和粘结层43之间烧结形成第一金属合金层46。
需要说明，在固化烧结银的原始浆料61的同时，在高温烧结的作用下，第一金属层411内的金属原子会与烧结银内的银产生键合作用形成金属键，如此，便在第一金属层411和粘结层43之间烧结形成了第一金属合金层46。
作为本申请的另一可选实施例，当与粘结层43接触的基板42表面上设置有第二金属层421时，本申请实施例所述的半导体装置的制备方法还可以包括以下步骤：
在固化烧结银的原始浆料61的同时，在第二金属层421与粘结层43之间烧结形成第二金属合金层47。
需要说明，在固化烧结银的原始浆料61的同时，在高温烧结的作用下，第二金属层421内的金属原子会与烧结银内的银产生键合作用形成金属键，如此，便在第二金属层421和粘结层43之间烧结形成了第一金属合金层47。
该步骤执行完对应的剖面结构示意图如图6B所示。
S503：采用特定材料填充至少部分空洞431。
需要说明，在本申请实施例中，特定材料在高于预设温度时，具有一定的流动性，并且在加热熔融后能够固化成型。
为了能够使特定材料能够填充尽可能多的空洞，以及达到较好的填充效果，本申请实施例选择流动性较好的材料作为填充空洞的特定材料。例如，该特定材料可以为流动性较好的塑封料。作为一具体实施例，选择的特定材料能够填充至少部分空洞。并且，为了保证最终形成的半导体塑封结构能够克服现有技术中的半导体塑封结构的缺陷，作为本申请的一可选实施例，选择的特定材料能够填充85％以上甚至90％以上的空洞。
作为示例，步骤S503可以具体包括以下步骤：
S5031：加热特定材料至高于预设温度，以使特定材料变成能够流动的流体。
S5032：将能够流动的流体注入到粘结层内的至少部分空洞内。
应当理解，将能够流动的流体注入到粘结层内的至少部分空洞内借助了毛细作用力原理，毛细作用力是指浸润液体在细管里升高的现象和不浸润液体在细管里降低的现象。其中，植物茎内的导管就是植物体内的极细的毛细管,它能把土壤里的水分吸上来，砖块吸水、毛巾吸汗、钢笔吸墨水都是常见的毛细现象。在这些物体中有许多细小的孔道起着毛细管的作用，液体的表面张力、内聚力和附着力的共同作用使水分可以在较小直径的毛细管中上升到一定的高度，称之为毛细现象。
所谓毛细作用力即为能够使流体在毛细管中自动上升的力。
在本申请实施例中，存在于粘结层内的空洞均为口径很细小的开口，因此，该空洞的结构类似于毛细管，如此，将粘接层结构置于能够流动的流体内部，在毛细作用力下，流体能够注入到粘结层内的至少部分空洞内。
S5033：将填充有特定材料的结构放置到一定温度条件下，对注入到空洞内的流体进行后固化。
需要说明，后固化时的温度和时间可以根据特定材料本身的性能确定。作为示例，后固化时的温度可以与特定材料内部的树脂的熔融温度和固化剂的固化温度相关。
执行完该步骤对应的剖面结构示意图如图6C所示。
S504：采用塑封料对连接在一起的半导体芯片41和基板42进行模塑封装，以形成包裹在半导体芯片41和粘结层43外围的塑封体44。
本步骤可以具体为：根据塑封料的性能，选择合适的模塑温度，对连接在在一起的半导体芯片41和基板42进行模塑封装，从而形成包裹半导体芯片41和粘结层43外围的塑封体44。形成的结构如图4所示。
此外，作为本申请的另一可选实施例，还可以在基板42的外围形成包裹基板42的塑封体，从而使基板42得到保护，防止外力对基板42的破坏。
需要说明，在本申请实施例中，在进行模塑封装之前，还可以执行从固晶到塑封之间的其它芯片封装步骤，例如制作连接半导体芯片41正面和基板42的金属键合线48，等等。应当理解，金属键合线48即为金属引线，用于实现半导体芯片41正面上的焊垫与基板42 上的焊垫的电连接。
S505：对塑封体44进行定型固化。
根据塑封料的固化成型条件，将模塑成型后的半导体芯片塑封结构放置到相应的温度和气氛条件下，对塑封体44进行定型固化，最终得到固化成型的半导体芯片塑封结构。
以上为本申请实施例提供的一种半导体装置的制备方法的具体实现方式。
在该具体实现方式中，对烧结银内部空洞的填充是通过一专门的填充工艺来实现的。
因填充在空洞内的特定材料可以为塑封料，为了简化封装工艺，降低封装成本，该填充空洞的过程可以在模塑封装过程中同时完成。具体参见以下实施例。
请参见图7，本申请实施例提供的另一种半导体装置的制备方法包括以下步骤：
S701至S702与上述实施例中的S501至S502相同，为了简要起见，在此不再详细描述。
S703：采用塑封料对粘结在一起的半导体芯片41和基板42进行模塑封装，以形成包裹在半导体芯片41和所述粘结层43外围的塑封体44，在模塑封装的同时，塑封料流入至少部分空洞431内，以使得至少部分空洞431内填充有塑封料。
在采用塑封料对连接在一起的半导体芯片41和基板42进行模塑封装时，在模塑压力和毛细作用力的作用下，呈熔融状态的塑封料能够流入至少部分空洞内，从而使得至少部分空洞内填充有塑封料。
在本申请实施例中，在模塑封装的同时，呈熔融状态的塑封料流入空洞内，从而实现空洞的填充。在模塑封装过程中，塑封料在模塑压力和毛细作用力的共同作用下，流入空洞内。相较于仅有毛细作用力的情形，利用模塑封装工艺实现对空洞的填充，能够达到更好的填充效果。
S704与上述S505相同，为了简要起见，在此不再详细描述。
以上为本申请实施例提供的另一种半导体装置的制备方法的具体实现方式。在该具体实现方式中，空洞的填充在模塑封装的过程中同时完成，从而减少了一道空洞填充工艺过程，简化了封装工艺，降低了封装成本。
以上为本申请实施例提供的半导体装置以及半导体装置的制备方法的具体实现方式。应当理解，以上所述实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (13)

  1. 一种半导体装置，其特征在于，包括：
    半导体芯片、基板以及位于所述半导体芯片和所述基板之间用于粘结所述半导体芯片和所述基板的粘结层；
    所述粘结层包括烧结金属；所述烧结金属的内部包括多个空洞，至少部分所述空洞内填充有特定材料；其中，所述特定材料在高于预设温度时，具有一定的流动性，并且在加热熔融后能够固化成型。
  2. 根据权利要求1所述的半导体装置，其特征在于，所述半导体装置还包括：包裹在所述半导体芯片和所述粘结层外围的塑封体，所述特定材料与所述塑封体对应的塑封料相同。
  3. 根据权利要求1或2所述的半导体装置，其特征在于，所述烧结金属内部85％以上的空洞填充有所述特定材料。
  4. 根据权利要求1-3任一项所述的半导体装置，其特征在于，在所述半导体芯片与所述粘结层相粘结的表面上设置有第一金属层，所述第一金属层与所述粘结层之间由于金属键合力形成有第一金属合金层。
  5. 根据权利要求1-4任一项所述的半导体装置，其特征在于，与所述粘结层相粘结的基板表面上设置有第二金属层，所述第二金属层与所述粘结层之间由于金属键合力形成有第二金属合金层。
  6. 一种半导体装置的制备方法，其特征在于，所述制备方法包括：
    通过烧结固化工艺在半导体芯片和基板之间形成粘结层，所述粘结层用于粘结所述半导体芯片和所述基板，其中所述粘结层由烧结金属组成，所述烧结金属内部包括多个空洞；
    采用特定材料填充至少部分所述空洞；所述特定材料在高于预设温度时，具有一定的流动性，并且在加热熔融后能够固化成型。
  7. 根据权利要求6所述的制备方法，其特征在于，所述制备方法还包括：
    形成包裹所述半导体芯片和所述粘结层的塑封体，所述特定材料与所述塑封体对应的塑封料相同。
  8. 根据权利要求6或7所述的制备方法，其特征在于，所述烧结金属内部85％以上的空洞填充有所述特定材料。
  9. 根据权利要求7或8所述的制备方法，其特征在于，所述采用特定材料填充至少部分所述空洞，具体包括：
    在形成所述塑封体的同时，流动的塑封料流入所述至少部分所述空洞内，以使得所述至少部分所述空洞内填充有所述塑封料。
  10. 根据权利要求6-9任一项所述的制备方法，其特征在于，所述形成包裹所述半导体芯片和所述粘结层的塑封体之后，还包括：对所述塑封体进行定型固化。
  11. 根据权利要求6-10任一项所述的制备方法，其特征在于，所述采用特定材料填充至少部分所述空洞，具体包括：
    加热所述特定材料至高于所述预设温度，以使所述特定材料能够流动；
    将所述能够流动的所述特定材料注入到所述粘结层内的所述至少部分空洞内。
  12. 根据权利要求6-11任一项所述的制备方法，其特征在于，与所述粘结层相粘结的半导体芯片表面上设置有第一金属层，所述第一金属层与所述粘结层之间由于金属键合力形成第一金属合金层。
  13. 根据权利要求6-12任一项所述的制备方法，其特征在于，与所述粘结层相粘结的基板表面上设置有第二金属层，所述第二金属层与所述粘结层之间由于金属键合力形成第二金属合金层。
PCT/CN2018/075947 2018-02-09 2018-02-09 一种具有高稳定性粘结层的半导体装置及其制备方法 Ceased WO2019153230A1 (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
PCT/CN2018/075947 WO2019153230A1 (zh) 2018-02-09 2018-02-09 一种具有高稳定性粘结层的半导体装置及其制备方法
EP18905755.7A EP3723116A4 (en) 2018-02-09 2018-02-09 SEMICONDUCTOR COMPONENT WITH HIGHLY STABLE CONNECTING LAYER AND MANUFACTURING METHOD FOR THE DEVICE
CN201880067522.XA CN111226308A (zh) 2018-02-09 2018-02-09 一种具有高稳定性粘结层的半导体装置及其制备方法
US16/984,805 US20200365547A1 (en) 2018-02-09 2020-08-04 Semiconductor apparatus with high-stability bonding layer and production method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2018/075947 WO2019153230A1 (zh) 2018-02-09 2018-02-09 一种具有高稳定性粘结层的半导体装置及其制备方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US16/984,805 Continuation US20200365547A1 (en) 2018-02-09 2020-08-04 Semiconductor apparatus with high-stability bonding layer and production method thereof

Publications (1)

Publication Number Publication Date
WO2019153230A1 true WO2019153230A1 (zh) 2019-08-15

Family

ID=67548122

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/075947 Ceased WO2019153230A1 (zh) 2018-02-09 2018-02-09 一种具有高稳定性粘结层的半导体装置及其制备方法

Country Status (4)

Country Link
US (1) US20200365547A1 (zh)
EP (1) EP3723116A4 (zh)
CN (1) CN111226308A (zh)
WO (1) WO2019153230A1 (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20210249330A1 (en) * 2020-02-06 2021-08-12 Intel Corporation Composite thermal matrix
US12218090B2 (en) 2020-12-25 2025-02-04 Yibu Semiconductor Co., Ltd. Semiconductor packaging method, semiconductor assembly and electronic device comprising semiconductor assembly
US12154884B2 (en) 2021-02-01 2024-11-26 Yibu Semiconductor Co., Ltd. Semiconductor packaging method, semiconductor assembly and electronic device comprising semiconductor assembly
CN112992699B (zh) * 2021-02-01 2024-03-22 上海易卜半导体有限公司 半导体封装方法、半导体组件以及包含其的电子设备
US12500203B2 (en) 2021-02-22 2025-12-16 Yibu Semiconductor Co., Ltd. Semiconductor packaging method, semiconductor assembly and electronic device comprising semiconductor assembly
US12027489B2 (en) * 2021-03-15 2024-07-02 Nano-X Imaging Ltd Systems and methods for fabricating silicon die stacks for electron emitter array chips
CN113691229B (zh) * 2021-08-25 2023-11-28 北京超材信息科技有限公司 声学装置封装结构
CN117182227A (zh) * 2023-11-08 2023-12-08 日月新检测科技(苏州)有限公司 集成电路检测方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11354575A (ja) * 1998-06-04 1999-12-24 Matsushita Electric Ind Co Ltd 半導体ユニットおよび半導体素子の実装方法
US20100187678A1 (en) * 2009-01-23 2010-07-29 Renesas Technology Corp. Semiconductor device and method of manufacturing the same
US20100195292A1 (en) * 2009-01-30 2010-08-05 Hitachi, Ltd. Electronic member, electronic part and manufacturing method therefor
CN203179944U (zh) * 2013-02-21 2013-09-04 深圳市瑞丰光电子股份有限公司 一种ｌｅｄ灯
JP2014027095A (ja) * 2012-07-26 2014-02-06 Denso Corp 電子装置およびその製造方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10009678C1 (de) * 2000-02-29 2001-07-19 Siemens Ag Wärmeleitende Klebstoffverbindung und Verfahren zum Herstellen einer wärmeleitenden Klebstoffverbindung
JP5123633B2 (ja) * 2007-10-10 2013-01-23 ルネサスエレクトロニクス株式会社 半導体装置および接続材料
JP2011165871A (ja) * 2010-02-09 2011-08-25 Denso Corp 電子装置およびその製造方法
JP5525335B2 (ja) * 2010-05-31 2014-06-18 株式会社日立製作所 焼結銀ペースト材料及び半導体チップ接合方法
JP5975911B2 (ja) * 2013-03-15 2016-08-23 ルネサスエレクトロニクス株式会社 半導体装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11354575A (ja) * 1998-06-04 1999-12-24 Matsushita Electric Ind Co Ltd 半導体ユニットおよび半導体素子の実装方法
US20100187678A1 (en) * 2009-01-23 2010-07-29 Renesas Technology Corp. Semiconductor device and method of manufacturing the same
US20100195292A1 (en) * 2009-01-30 2010-08-05 Hitachi, Ltd. Electronic member, electronic part and manufacturing method therefor
JP2014027095A (ja) * 2012-07-26 2014-02-06 Denso Corp 電子装置およびその製造方法
CN203179944U (zh) * 2013-02-21 2013-09-04 深圳市瑞丰光电子股份有限公司 一种ｌｅｄ灯

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3723116A4 *

Also Published As

Publication number Publication date
EP3723116A4 (en) 2021-02-17
EP3723116A1 (en) 2020-10-14
US20200365547A1 (en) 2020-11-19
CN111226308A (zh) 2020-06-02

Similar Documents

Publication Publication Date Title
WO2019153230A1 (zh) 一种具有高稳定性粘结层的半导体装置及其制备方法
US8334591B2 (en) Semiconductor device and method of manufacturing the same
US20140070428A1 (en) Semiconductor device and method for manufacturing the same
CN111384008A (zh) 粘合膜、半导体设备及半导体封装
US9799580B2 (en) Semiconductor device package and methods of manufacture thereof
CN103956350A (zh) 包括将半导体芯片键合至铜表面的烧结接合部的模块
TW200816423A (en) Semiconductor device and method for manufacturing the same
TWI236740B (en) Chip package structure
CN103904172A (zh) 一种陶瓷体上常温超声波焊接led芯片的方法
CN104103609A (zh) 封装及其制造方法
US9589864B2 (en) Substrate with embedded sintered heat spreader and process for making the same
CN209328886U (zh) 石墨烯基ipm模块的先进封装结构
CN104465455A (zh) 将银纳米材料嵌入到裸片背侧中以增强封装性能及可靠性
TWI332694B (en) Chip package structure and process for fabricating the same
CN109786345B (zh) 石墨烯基ipm模块的先进封装结构及加工工艺
JP5898575B2 (ja) 半導体装置
CN104064532A (zh) 一种带有散热结构的器件封装结构及制造方法
CN204067330U (zh) 一种基板片式载体csp封装件
CN208077964U (zh) 高功率密度塑封式ipm模块的封装结构
CN116053144A (zh) 功率模块及其封装方法
CN118315349A (zh) 芯片集成封装散热系统及其制备方法
CN212062388U (zh) 半导体封装结构
CN211238224U (zh) 具有散热片的半导体封装结构
CN112435974B (zh) 高强度dfn封装半导体器件
CN201229938Y (zh) 芯片封装结构

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18905755

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2018905755

Country of ref document: EP

Effective date: 20200710

NENP Non-entry into the national phase

Ref country code: DE