WO2019183866A1 - 频率产生器以及频率产生方法 - Google Patents

频率产生器以及频率产生方法 Download PDF

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Publication number
WO2019183866A1
WO2019183866A1 PCT/CN2018/080993 CN2018080993W WO2019183866A1 WO 2019183866 A1 WO2019183866 A1 WO 2019183866A1 CN 2018080993 W CN2018080993 W CN 2018080993W WO 2019183866 A1 WO2019183866 A1 WO 2019183866A1
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Prior art keywords
signal
frequency
cyclic
generate
phase
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PCT/CN2018/080993
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English (en)
French (fr)
Inventor
黄彦颖
张镕谕
徐铭锋
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Shenzhen Goodix Technology Co Ltd
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Shenzhen Goodix Technology Co Ltd
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Priority to CN201880000440.3A priority Critical patent/CN110612667B/zh
Priority to EP18897872.0A priority patent/EP3573242B1/en
Priority to PCT/CN2018/080993 priority patent/WO2019183866A1/zh
Priority to US16/507,654 priority patent/US10680620B2/en
Publication of WO2019183866A1 publication Critical patent/WO2019183866A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/16—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using saturable magnetic devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0802—Details of the phase-locked loop the loop being adapted for reducing power consumption
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/181—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a numerical count result being used for locking the loop, the counter counting during fixed time intervals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
    • H03L7/193—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number the frequency divider/counter comprising a commutable pre-divider, e.g. a two modulus divider

Definitions

  • the present application relates to a frequency generator, and more particularly to a low power open loop fractional frequency generator.
  • Electronic systems require frequency signals of different frequencies to suit different operations or applications. Based on design and cost considerations, electronic systems typically generate frequency signals of various frequencies based on reference frequency signals.
  • FIG. 1 is a schematic diagram of a multi-phase frequency generator 10.
  • the multi-phase frequency generator 10 includes a phase generator 100, a multiplexer 102, an edge combiner 104 (Edge Combiner), and a phase selector 106.
  • the phase generator 100 is operative to receive the input signal CKIN to generate a plurality of phase signals; the multiplexer 102 selects the desired phase based on the indication of the phase selector 106 and passes it to the edge synthesizer 104, which produces an output signal accordingly.
  • phase selector 106 is passed to phase selector 106. It is worth noting that in the frequency division operation of the fraction, more phase generating units are required in the phase generator 100 to improve the resolution of the plurality of phase signals, thereby generating additional power consumption, and further, the phase generating unit A mismatch between them also increases the noise of the output signal.
  • FIG. 2 is a schematic diagram of a frequency synthesizer 20.
  • the frequency synthesizer 20 includes a frequency phase detector 200, a charge pump 202, a low pass filter 204, a voltage controlled oscillator 206, a programmable frequency divider 208, and a delta-sigma modulator 210.
  • the frequency synthesizer 20 receives the divided output frequency signal CKOUT by the delta-sigma modulator 210, thereby adjusting the divisor of the programmable frequency divider 208.
  • the average of the output frequency signal CKOUT generated by the frequency synthesizer 20 is a fractional divisor relationship with the reference frequency signal CKIN.
  • the delta-sigma modulator 210 in the frequency synthesizer 20 generates quantization noise, it is necessary to suppress quantization noise by reducing the loop bandwidth or increasing the resolution of the programmable demultiplexer 208. Reducing the loop bandwidth needs to be achieved by increasing the circuit area, and increasing the resolution needs to be achieved by increasing the number of output phases of the voltage controlled oscillator 206, thus generating additional power consumption.
  • the present application provides a frequency generator including a control unit for receiving an input signal to generate a divisor signal, a phase signal, and a cyclic signal, a frequency divider for receiving the input signal, and Deriving a divisor signal to perform integer frequency division on the input signal to generate a frequency division signal; a cyclic delay circuit coupled to the frequency divider for performing at least one cyclic operation on the frequency division signal, and each time At least one delayed phase signal is generated when the loop operation is performed; the first multiplexer is coupled to the cyclic delay circuit for using the frequency-divided signal and the at least one delayed phase signal according to the phase signal Selecting one of the signals to generate a multiplex signal; and a retimer coupled to the first multiplexer for generating according to the cyclic signal, the multiplex signal, and the frequency-divided signal output signal.
  • the frequency divider divides the frequency of the input signal by an integer or divides by the integer plus one to perform integer division of the input signal to generate the frequency-divided signal.
  • the cyclic delay circuit includes a NAND gate for receiving the frequency-divided signal and a cyclic phase signal to generate a first delayed phase signal; and at least one delay unit connected in series to each other as a sequence.
  • the first delay unit in the sequence receives the first delayed phase signal, each delay unit delays the delayed phase signal output by the previous delay unit to generate the at least one delayed phase signal, and the last delay in the sequence
  • the unit outputs the cyclic phase signal.
  • each of the loop operations inputs the sequence of the at least one delay unit for the frequency division signal, and outputs the cyclic phase signal to the NAND gate by a last delay unit in the sequence.
  • the retimer includes at least one D-type flip-flop connected in series to receive the multiplex signal, and the frequency input end of the at least one D-type flip-flop receives the multiplex signal And generating, by the signal output end of the at least one D-type flip-flop, at least one retiming signal; and a second multiplexer coupled to the at least one D-type flip-flop for using the cyclic signal One of the at least one retiming signal is selected to generate the output signal.
  • the present application further provides a frequency generating method for a frequency generator, wherein the frequency generator includes a frequency divider for receiving an input signal to generate a frequency-divided signal, and a cyclic delay circuit coupled to the frequency-dividing And the multiplexer is coupled to the cyclic delay circuit for signal selection; the retimer is coupled to the multiplexer, and is configured to generate at least one delayed phase signal according to the frequency division signal; Generating an output signal, wherein the frequency generating method includes the frequency divider generating an integer frequency division of the input signal according to a divisor signal generated by a control unit to generate the frequency dividing signal; the cyclic delay circuit according to the dividing The frequency signal is subjected to at least one cyclic operation, and the at least one delayed phase signal is generated each time the cyclic operation is performed; the multiplexer is configured by the frequency division signal according to the phase signal generated by the control unit, Selecting one of the at least one delayed phase signals to generate a multiplex signal; and the retimer is based on the
  • Figure 1 is a schematic diagram of a multi-phase frequency generator.
  • FIG. 2 is a schematic diagram of a frequency synthesizer.
  • FIG. 3 is a schematic diagram of a frequency generator according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of a cyclic delay circuit according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of a retimer according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of related signals when the frequency generator shown in FIG. 3 operates.
  • FIG. 7 is a schematic diagram of a process according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a frequency generator 30 according to an embodiment of the present invention.
  • the frequency generator 30 includes a frequency divider 300, a cyclic delay circuit 302, a multiplexer (MUX) 304, a retimer 306, and a control unit 308.
  • the control unit 308 is configured to receive an input signal CKIN to generate a divisor signal S_DIV, a phase signal S_MUX, and a loop signal S_RET to control various components in the frequency generator 30.
  • the frequency divider 300 receives the input signal CKIN for performing integer division of the input signal CKIN according to the divisor signal S_DIV to generate the frequency-divided signal CK_DIV.
  • the cyclic delay circuit 302 is coupled to the frequency divider 300 for performing a cyclic operation according to the frequency division signal CK_DIV to generate at least one delayed phase signal CK_1 CK CK_M, wherein the cyclic delay circuit 302 can be pre-corrected to adjust the delayed phase signal.
  • the delays of CK_1 to CK_M are repeatedly performed in a loop operation to generate different delayed phase signals CK_1 to CK_M in each loop operation.
  • the multiplexer 304 is coupled to the cyclic delay circuit 302 for selecting one of the frequency-divided signal CK_DIV and the delayed phase signals CK_1-CK_M according to the phase signal S_MUX to generate a multiplex signal CK_MUX.
  • the retimer 306 is coupled to the frequency divider 300 and the multiplexer 304 for generating an output signal CKOUT according to the frequency-divided signal CK_DIV and the cyclic signal S_RET.
  • the re-timer 306 can be selected by the cyclic signal S_RET.
  • the output multiplex signal CK_MUX is the output signal CKOUT during the correct cyclic operation.
  • the frequency generator 30 fractionally divides the input signal CKIN to generate an output signal CKOUT.
  • the frequency generator 30 receives the input signal CKIN using the frequency changer 300 that can change the divisor, and performs integer division on the input signal CKIN to generate the frequency division signal CK_DIV. It should be noted that since the frequency and the period are inversely related, the frequency divider 300 divides the input signal CKIN by increasing the period of the input signal CKIN by an integral multiple.
  • the cyclic delay circuit 302 receives the frequency-divided signal CK_DIV, and generates at least one delayed phase signal CK_1-CK_M according to the loop, wherein the cyclic delay circuit 302 continuously performs the cyclic operation and generates the delayed phase signal CK_1 in each cyclic operation. ⁇ CK_M. It should be noted that the cyclic delay circuit 302 can be adjusted by pre-correction so that the phase or delay of the delayed phase signal can meet the system requirements, and the phase difference between each delayed phase signal CK_1 CK CK_M is Similarly, the frequency generator 30 can select an appropriate cyclic operation and delay the phase signal according to system requirements to obtain an appropriate phase for fractional frequency division operation.
  • the multiplexer 304 receives the frequency-divided signal CK_DIV and the M delayed phase signals CK_1 to CK_M, and selects one of the frequency-divided signal CK_DIV and the M delayed-phase signals CK_1 to CK_M as the multiplex signal CK_MUX according to the phase signal S_MUX.
  • the retimer 306 receives the multiplex signal CK_MUX for outputting the multiplex signal CK_MUX as the output signal CKOUT according to the cyclic signal S_RET and the frequency division signal CK_DIV.
  • the cyclic delay circuit 302 continuously performs the cyclic operation, therefore,
  • the multiplex signal CK_MUX selected by the multiplexer 304 changes the phase every time the loop operation is performed, and the retimer 306 outputs the multiplex signal CK_MUX as the output signal CKOUT according to the cyclic signal S_RET in the correct cyclic operation to complete the fractional division.
  • Frequency operation the present application performs an integer frequency division operation by the frequency divider 300 to generate a frequency division signal CK_DIV whose period is an integer multiple of the input signal CKIN; and generates at least one delayed phase signal by the cyclic delay circuit 302 in each loop operation.
  • the present application can perform a cyclic operation by the cyclic delay circuit 302, continuously generate a phase with a limited circuit, and operate only when CK_DIV is high, thereby reducing power consumption, and then passing through the multiplexer 304 and the retimer 306. To select the appropriate signal and delay to achieve an open loop and low power frequency generator.
  • the frequency generator 30 of the present invention can be used to perform a fractional division operation with a divisor of 17/5.
  • the output period Tout of the output signal CKOUT generated by the frequency generator 30 is an input signal CKIN.
  • the input period Tin is 17/5 times (ie 3+2/5 times).
  • the present application first performs an integer frequency division operation by the frequency divider 300 to generate a frequency division signal CK_DIV whose period is an integer multiple of the input period.
  • the cyclic operation is continuously performed by the cyclic delay circuit 302, and a delayed phase signal is generated in each cyclic operation, and the correct signal and the cyclic operation time are selected by the multiplexer 304 and the retimer 306 to complement the frequency divider 300.
  • Insufficient frequency adjustment produces an output signal CKOUT having a period of 3+2/5 times the input signal CKIN.
  • the frequency divider 300 of the present application can be designed as a frequency divider operation with a divide by three or a divide by four integer division operation, which performs a frequency division operation on the input signal according to the divisor signal S_DIV.
  • the cyclic delay circuit 302 can be designed to generate two sets of delayed phase signals CK_1, CK_2, and the delays of the delayed phase signals CK_1, CK_2 are 1/5 input cycles (ie, Tin/5) and 2/5 input cycles (ie, 2Tin/).
  • FIG. 4 is a schematic diagram of a cyclic delay circuit 402 according to an embodiment of the present invention.
  • the cyclic delay circuit 402 of the present invention includes a NAND gate NAND, and a sequence in which the buffers BUF_1, BUF_2 are connected in series, and the buffers BUF_1, BUF_2 can respectively generate delayed phase signals CK_1, CK_2.
  • the cyclic delay circuit 502 can perform gating through the NAND gate NAND. When the frequency division signal CK_DIV is high and is transferred to the NAND gate NAND, the series sequence of the buffers BUF_1, BUF_1 is turned on and continues.
  • the cyclic operation is performed to continuously generate the delayed phase signals CK_1, CK_2; when the frequency-divided signal CK_DIV is low and is transferred to the NAND gate NAND, the series sequence of the buffers BUF_1, BUF_1 is turned off and no loop operation is performed, and thus The delayed phase signals CK_1, CK_2 are output.
  • the last stage buffer BUF_2 in the sequence returns the delayed phase signal CK_2 to the NAND gate NAND, and the sequence of the delayed phase signal CK_M to the buffer is passed through the NAND gate NAND to complete a complete cyclic operation.
  • the frequency generator 30 of the present application can realize the low power frequency by using the cyclic delay circuit 302 by the gate control of the NAND gate NAND and the repeated use of fewer circuits during the cyclic operation to continuously generate the delayed phase signal. Generator.
  • FIG. 5 is a schematic diagram of a retimer 506 according to an embodiment of the present invention.
  • the retimer 506 includes N D-type flip-flops DFF1 to DFFn and a multiplexer MUX.
  • the data output end of the D-type flip-flop is coupled to the data input end of another D-type flip-flop, and the N D-type flip-flops are connected in series to form a sequence.
  • the D-type The sequence of the flip-flops DFF1 to DFFn is a register (Shift Register).
  • the data input end of the D-type flip-flop DFF1 at the forefront of the sequence is used to receive the frequency-divided signal CK_DIV, and the frequency input terminals of all the D-type flip-flops DFF1 to DFFn in the sequence receive the multiplex signal CK_MUX for the D-type positive
  • the data output ends of the inverters DFF1 to DFFn respectively generate the first retiming signal P_1 to the nth retiming signal P_n, and the D-type flip-flops DFF1 to DFFn in the sequence can transmit the de-sequencing signal CK_DIV according to the trigger of the multiplex signal CK_MUX.
  • the D-type flip-flop DFF1 transfers the frequency-divided signal CK_DIV to the first re-timing signal P_1;
  • the D-type flip-flop DFF2 can transfer the first re-timing signal P_1 to the second re-timing signal P_2.
  • the retimer 506 can generate retiming when the multiplex signal CK_MUX is triggered by different cyclic operations, and then from the first retiming signal P_1 to the nth retiming signal P_n according to the cyclic signal S_RET by the multiplexer MUX.
  • One of the signals is selected as the output signal CKOUT to obtain the appropriate signal phase to achieve the fractional divisor operation of the open loop frequency generator.
  • FIG. 6 is a schematic diagram of related signals when the frequency generator 30 of FIG. 3 operates.
  • the frequency generator 30 can perform a fractional division operation with a divisor of 17/5.
  • the frequency divider 300 can perform a frequency division operation of divide by three or divide by four;
  • the cyclic delay circuit 302 can generate two sets of delayed phase signals CK_1, CK_2, and the delays of the delayed phase signals CK_1, CK_2 are respectively 1 /5 input period Tin and 2/5 input period Tin;
  • multiplexer 304 selects one of delayed phase signals CK_1, CK_2 to generate multiplex signal CK_MUX according to the phase signal;
  • retimer 306 triggers according to multiplex signal CK_MUX and An indication of the cyclic signal S_RET is generated to produce an output signal CKOUT.
  • the input signal CKIN and the output signal CKOUT are aligned with each other.
  • the divisor signal S_DIV generated by the control unit 308 instructs the frequency divider 300 to perform an integer frequency division operation of divisor 3 on the input signal CKIN to generate the frequency division signal CK_DIV; the cyclic delay circuit 302 is used in each loop operation according to the frequency division signal CK_DIV.
  • the delayed phase signals CK_1, CK_2 are generated; the phase signal S_MUX generated by the control unit 308 instructs the multiplexer 304 to select the delayed phase signal CK_2 as the multiplex signal CK_MUX; the cyclic signal S_RET generated by the control unit 308 indicates that the retimer 306 selects the first cycle
  • the multiplexed signal CK_MUX generated by the operation is the output signal CKOUT.
  • the delay phase signal CK_2 of the first cyclic operation is selected by the multiplexer 304 and the retimer 306, and the period of the frequency division signal CK_DIV can be additionally increased by 2/ 5 input period Tin to achieve fractional frequency division operation; likewise, at a time point T2, the divisor of the frequency divider 300 is 3; the multiplexer 304 selects the delayed phase signal CK_2 as the multiplex signal CK_MUX; the retimer 306
  • the multiplex signal CK_MUX generated by the second cyclic operation is selected as the output signal CKOUT according to the phase signal, and therefore, the period of the frequency dividing signal CK_DIV may be extra. Plus 4/5 input period Tin.
  • the divisor of the frequency divider 300 is 3; the multiplexer 304 selects the delayed phase signal CK_2 as the multiplex signal CK_MUX; and the retimer 306 selects the multiplex generated by the third cyclic operation according to the phase signal S_MUX
  • the signal CK_MUX is the output signal CKOUT, so the period of the frequency dividing signal CK_DIV can be additionally increased by 6/5 input period Tin.
  • the divisor signal S_DIV indicates that the divisor of the frequency divider 300 is 4;
  • the phase signal S_MUX indicates that the multiplexer 304 selects the delayed phase signal CK_1 as the multiplex signal CK_MUX;
  • the retimer 306 is based on the phase
  • the multiplex signal CK_MUX generated by the second cycle operation of the signal selection is the output signal CKOUT, so the period of the frequency division signal CK_DIV can be additionally increased by 3/5 input period Tin.
  • the divisor of the frequency divider 300 is 4; the multiplexer 304 selects the frequency-divided signal CK_DIV as the multiplex signal CK_MUX; and the re-timer 306 can output the frequency-divided signal CK_DIV as the multiplex signal CK_MUX.
  • the frequency generator 30 can perform an integer frequency division operation by the frequency divider 300, and the cyclic delay circuit 302 continues to perform a cyclic operation to generate the delayed phase signals CK_1, CK_2, through the multiplexer 304, and through the retimer.
  • the 306 selects the correct cyclic operation and delays the phase signal, preferably adjusts the period of the frequency-divided signal CK_DIV to generate an output signal CKOUT to implement an open-loop and low-power frequency generator.
  • the divisor of the frequency divider 300 is 3
  • the cyclic delay circuit 302, the multiplexer 304, and the retimer 306 additionally increase the input period Tin by 6/5.
  • the frequency divider 300 can also perform a divide by four divisor operation, and the additional input period Tin of the cyclic delay circuit 302, the multiplexer 304, and the retimer 306 is correspondingly adjusted to 1/5 input period. Tin to generate an appropriate output signal CKOUT.
  • the control unit 308 predetermines the integer divisor of the next frequency-divided signal CK_DIV and the delay amount each time the control unit 308 receives the frequency-divided signal CK_DIV to generate a corresponding divisor signal S_DIV, a phase signal S_MUX, and a cyclic signal S_RET to control the frequency division.
  • the frequency division operation performed by the frequency generator 30 causes the output period Tout to be (N+P/M) times the output period Tin (i.e., the period is inversely proportional to the frequency). Therefore, the present invention can perform an N or (N+1) divisor division operation on the input signal CKIN through the frequency divider 300.
  • the frequency division operation of the remaining P/M divisor is implemented by the cyclic delay circuit 302, the multiplexer 304, and the retimer 306.
  • the divisor 17/5 is (3+2/5), so the frequency divider 300 can perform the frequency division operation with the divisor of 3 or the divisor of 4, and the frequency division of the remaining 2/5 divisor.
  • the operation is implemented by a cyclic delay circuit 302, a multiplexer 304, and a retimer 306.
  • the delays of the delayed phase signals CK_1 CK CK_2 at each cycle operation are 1/5 input period Tin and 2/5 input period Tin, respectively, and each cycle operation
  • the delay is 2/5 input period Tin.
  • the appropriate delay phase signal is selected by the multiplexer 304, and the correct cyclic operation is selected by the retimer 306, and the duty cycle ratio (Duty Cycle) of the output signal CKOUT is adjusted.
  • the frequency generator 30 of the present invention can perform a fractional divisor operation on the input signal CKIN to generate an output signal CKOUT.
  • the above-described operation method for the frequency generator to perform the fractional frequency division operation according to the input input signal CKIN to generate the output signal CKOUT can be summarized as a flow 70, as shown in FIG.
  • the process 70 can be used for a frequency generator, and the frequency generator includes a frequency divider receiving input signal CKIN for performing an integer frequency division operation on the input signal according to the divisor signal S_DIV to generate the frequency division signal CK_DIV.
  • a cyclic delay circuit is coupled to the frequency divider for continuously performing a cyclic operation according to the frequency-divided signal CK_DIV, wherein the cyclic delay circuit generates at least one delayed phase signal CK_1-CK_M for each cyclic operation.
  • a multiplexer is coupled to the cyclic delay circuit for selecting one of the frequency-divided signal CK_DIV and the delayed phase signals CK_1-CK_M as the multiplex signal CK_MUX according to the phase signal S_MUX.
  • the retimer is coupled to the multiplexer for generating an output signal CKOUT according to the cyclic signal S_RET and the multiplex signal CK_MUX during the correct cyclic operation.
  • the process 70 includes the following steps:
  • Step 700 Start.
  • Step 702 The frequency divider performs an integer frequency division operation on the input signal CKIN according to the divisor signal S_DIV to generate the frequency division signal CK_DIV.
  • Step 704 The cyclic delay circuit receives the frequency-divided signal CK_DIV to generate at least one delayed phase signal CK_1-CK_M.
  • Step 706 The multiplexer selects one of the frequency-divided signal CK_DIV and the at least one delayed phase signal CK_1-CK_M as the multiplex signal CK_MUX according to the phase signal S_MUX.
  • Step 708 The retimer outputs the multiplex signal CK_MUX as the output signal CKOUT according to the cyclic signal S_RET for the correct cyclic operation time.
  • Step 710 End.
  • the triangular integral modulator increases power consumption and reduces the signal. quality.
  • different phases can be continuously generated by the cyclic delay circuit with a small area consumption, and the phase signal and the correct cycle are selected by the multiplexer and the retimer. Operate to achieve an open circuit and low power frequency generator.

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Abstract

一种频率产生器，包括控制单元，用来接收输入信号，以产生除数信号、相位信号以及循环信号；除频器，用来接收所述输入信号，以及根据所述除数信号对所述输入信号进行整数除频而产生除频信号；循环式延迟电路，耦接于所述除频器，用来对所述除频信号进行至少一循环操作，且于每次进行所述循环操作时产生至少一延迟相位信号；第一多工器，耦接于所述循环式延迟电路，用来根据所述相位信号由所述除频信号以及所述至少一延迟相位信号中选择其中之一信号，以产生多工信号；以及重定时器，耦接于所述第一多工器，用来根据所述循环信号、所述多工信号以及所述除频信号，产生输出信号。

Description

频率产生器以及频率产生方法 技术领域
本申请涉及一种频率产生器，尤其涉及一种低功率的开回路分数型频率产生器。
背景技术
电子系统需要不同频率的频率信号以适应不同的操作或应用，基于设计与成本考虑，电子系统通常是根据参考频率信号产生各种不同频率的频率信号。
一般来说，当输入信号的频率与输出信号的频率之间为分数倍数关系，可利用多相位频率产生器以及频率合成器取得所需要的输出信号。请参考图1，图1为一多相位频率产生器10的示意图。多相位频率产生器10包括相位产生器100、多工器102、边缘合成器104(Edge Combiner)以及相位选择器106。相位产生器100用来接收输入信号CKIN以产生复数个相位信号；多工器102根据相位选择器106的指示选择所需要的相位并传递至边缘合成器104，边缘合成器104据此产生输出信号CKOUT，并传递至相位选择器106。值得注意的是，在进行分数的除频操作时，相位产生器100中需设置更多的相位产生单元来改善复数个相位信号的分辨率，因而产生了额外的功率消耗，此外，相位产生单元之间的不匹配亦会使输出信号的噪声提高。
另外，请参考图2，图2为一频率合成器20的示意图。频率合成器20包 括频率相位侦测器200、充电泵202、低通滤波器204、压控振荡器206、可程序化除频器208以及三角积分调变器210。频率合成器20利用三角积分调变器210接收除频后的输出频率信号CKOUT，进而调整可程序化除频器208的除数。如此一来，频率合成器20产生的输出频率信号CKOUT的平均与参考频率信号CKIN之间为分数除数的关系。然而，由于频率合成器20中的三角积分调变器210会产生量化噪声(Quantization Noise)，需藉由降低回路带宽或是提高可程序化除频器208的分辨率以抑制量化噪声，其中，降低回路带宽需要通过增加电路面积以实现，提高分辨率需要通过增加压控振荡器206的输出相位数量以实现，因而产生额外的功率消耗。
因此，现有技术实有改善的必要。
发明内容
因此，本申请的部分实施例的目的即在于提供一种低功率的开回路分数型频率产生器，以改善现有技术的缺点。
为了解决上述问题，本申请提出一种频率产生器，包括控制单元，用来接收输入信号，以产生除数信号、相位信号以及循环信号；除频器，用来接收所述输入信号，以及根据所述除数信号对所述输入信号进行整数除频而产生除频信号；循环式延迟电路，耦接于所述除频器，用来对所述除频信号进行至少一循环操作，且于每次进行所述循环操作时产生至少一延迟相位信号；第一多工器，耦接于所述循环式延迟电路，用来根据所述相位信号由所述除频信号以及 所述至少一延迟相位信号中选择其中之一信号，以产生多工信号；以及重定时器，耦接于所述第一多工器，用来根据所述循环信号、所述多工信号以及所述除频信号，产生输出信号。
例如，所述除频器将所述输入信号的频率除以一整数或除以所述整数加一，以对所述输入信号进行整数除频而产生所述除频信号。
例如，所述循环式延迟电路包括与非门，用来接收所述除频信号以及循环相位信号，以产生第一延迟相位信号；以及至少一延迟单元，相互串接连接为一序列，由所述序列中最前一延迟单元接收所述第一延迟相位信号，每一延迟单元将前一延迟单元输出的延迟相位信号延迟以产生所述至少一延迟相位信号，以及由所述序列中最后一延迟单元输出所述循环相位信号。
例如，其中每一循环操作为所述除频信号输入所述至少一延迟单元的所述序列，由所述序列中最后一延迟单元输出所述循环相位信号至所述与非门。
例如，所述重定时器包括至少一D型正反器，相互串接连接，用来接收所述多工信号，且所述至少一D型正反器的频率输入端接收所述多工信号，以于所述至少一D型正反器的的信号输出端产生至少一重定时信号；以及第二多工器，耦接于所述至少一D型正反器，用来根据所述循环信号由所述至少一重定时信号中选择其中之一信号，以产生所述输出信号。
本申请另提出一种频率产生方法，用于频率产生器，其中所述频率产生器包括除频器，用来接收输入信号而产生除频信号；循环式延迟电路，耦接于所述除频器，用来根据所述除频信号产生至少一延迟相位信号；多工器，耦接于循环式延迟电路，用来进行信号选择；重定时器，耦接于所述多工器，用来产生输出信号，其中所述频率产生方法包括所述除频器根据控制单元产生的除数信号对所述输入信号进行整数除频而产生所述除频信号；所述循环式延迟电路根据所述除频信号进行至少一循环操作，且于每次进行所述循环操作时产生所述至少一延迟相位信号；所述多工器根据所述控制单元产生的相位信号由所述除频信号、所述至少一延迟相位信号中选择其中之一信号而产生多工信号；以及所述重定时器根据所述控制单元产生的循环信号、所述除频信号以及所述多工信号以产生所述输出信号。
附图说明
图1为一多相位频率产生器的示意图。
图2为一频率合成器的示意图。
图3为本发明实施例一频率产生器的示意图。
图4为本发明实施例一循环式延迟电路的示意图。
图5为本发明实施例一重定时器的示意图。
图6为图3所示频率产生器运作时相关信号的示意图。
图7为本发明实施例一流程的示意图。
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。此外，本发明用来描述两组件之间的链接关系所使用的文字，例如「耦接」以及「连接」，不应用来限制两组件之间的连接关系为直接连结或间接连结。
请参考图3，图3为本发明实施例一频率产生器30的示意图。频率产生器30包括除频器300、循环式延迟电路302、多工器(MUX)304、重定时器(Retimer)306以及控制单元308。控制单元308用来接收一输入信号CKIN，以产生一除数信号S_DIV、一相位信号S_MUX以及一循环信号S_RET，以控制频率产生器30中的各个组件。除频器300接收输入信号CKIN，用来根据除数信号S_DIV对输入信号CKIN进行整数除频以产生除频信号CK_DIV。循环式延迟电路302耦接于除频器300，用来根据除频信号CK_DIV进行循环操作，以产生至少一延迟相位信号CK_1～CK_M，其中，循环式延迟电路302可预先校正以调整延迟相位信号CK_1～CK_M的延迟，且重复地进行循环操作以在每次的循环操作产生不同的延迟相位信号CK_1～CK_M。多工器304耦接于循环式延迟电路302，用来根据相位信号S_MUX由除频信号CK_DIV以及延迟相位信号CK_1～CK_M中选择其中之一信号，以产生一多工信号CK_MUX。重定时器306耦接于除频器300以及多工器304，用来根据除频信号CK_DIV以及循环信号S_RET产生一输出信号CKOUT，换句话说，重定时器306可通过循环信号S_RET的选择，在正确的循环操作时输出多工信号CK_MUX为输出信号CKOUT。
详细而言，频率产生器30对输入信号CKIN进行分数除频以产生输出信号CKOUT。为了达到分数除频的操作，首先，频率产生器30利用可改变除数的除频器300接收输入信号CKIN，对输入信号CKIN进行整数除频以产生除频信号CK_DIV。值得注意的是，由于频率与周期为倒数关系，所以除频器300对输入信号CKIN进行除频即为将输入信号CKIN的周期增加整数倍。接着，循环式延迟电路302接收除频信号CK_DIV，并据此产生至少一延迟相位信号CK_1～CK_M，其中，循环式延迟电路302会不断地进行循环操作且于每次循环操作产生延迟相位信号CK_1～CK_M。值得注意的是，循环式延迟电路302可藉由预先校正(Calibration)进行调整，使延迟相位信号的相位或延迟可符合系统需求，此外，每一延迟相位信号CK_1～CK_M之间的相位差均相同，频率产生器30可根据系统需求选择适当的循环操作以及延迟相位信号，以取得适当的相位进行分数除频操作。多工器304接收除频信号CK_DIV以及M个延迟相位信号CK_1～CK_M，根据相位信号S_MUX由除频信号CK_DIV以及M个延迟相位信号CK_1～CK_M中选择其中之一为多工信号CK_MUX。重定时器306接收多工信号CK_MUX，用来根据循环信号S_RET以及除频信号CK_DIV以输出多工信号CK_MUX为输出信号CKOUT，换句话说，循环式延迟电路302会不断地进行循环操作，因此，多工器304选择的多工信号CK_MUX会在每次循环操作时改变相位，重定时器306即根据循环信号S_RET以在正确的循环操作时输出多工信号CK_MUX为输出信号CKOUT，以完成分数除频操作。详细而言，本申请通过除频器300进行整数除频操作，以产生周期为输入信号CKIN整数倍的除频信号CK_DIV；通过循环式延迟电路302于每次循环 操作时产生至少一延迟相位信号CK_1～CK_M；通过多工器304根据相位信号由除频信号CK_DIV以及M个延迟相位信号CK_1～CK_M中选择其中之一信号为多工信号CK_MUX；通过重定时器306根据循环信号S_RET以于正确的循环操作时取得延迟相位信号的相位，将多工信号CK_MUX输出为输出信号CKOUT。如此一来，本申请可通过循环式延迟电路302进行循环操作，以有限的电路不断产生相位，且只在CK_DIV为高时运作，进而降低功率消耗，再通过多工器304以及重定时器306以选择适当的信号以及延迟，以实现开回路且低功率的频率产生器。
举例而言，在一实施例中，本发明的频率产生器30可用来进行除数为17/5的分数除频操作，换言之，频率产生器30产生的输出信号CKOUT的输出周期Tout为输入信号CKIN的输入周期Tin的17/5倍(即3+2/5倍)。为了将输入周期Tin增加至3+2/5倍，本申请通过除频器300先进行整数的除频操作，以产生周期为输入周期整数倍的除频信号CK_DIV。接着，通过循环式延迟电路302不断地进行循环操作，且于每次循环操作产生延迟相位信号，以多工器304以及重定时器306选择正确的信号以及循环操作时间，以补足除频器300不足的频率调整，产生周期为输入信号CKIN的3+2/5倍的输出信号CKOUT。
详细而言，本申请的除频器300可设计为除数为3或除数为4的整数除频操作的除频器，其根据除数信号S_DIV以对输入信号进行除频操作。循环式延迟电路302可设计为产生两组延迟相位信号CK_1、CK_2，且延迟相位信号CK_1、CK_2的延迟分别为1/5输入周期(即Tin/5)以及2/5输入周期(即2Tin/5)， 如此一来，在第一次循环操作时延迟相位信号CK_1、CK_2的延迟分别为1/5输入周期Tin以及2/5输入周期Tin；在第二次循环操作时延迟相位信号CK_1、CK_2的延迟分别为3/5输入周期Tin以及4/5输入周期Tin；依此类推，循环式延迟电路302可据此产生不同的延迟相位信号以补足除频信号CK_DIV不足的除频操作。进一步而言，关于本发明的循环式延迟电路，请参考图4，图4为本发明实施例一循环式延迟电路402的示意图。本发明的循环式延迟电路402包括一与非门NAND，以及缓冲器BUF_1、BUF_2相互串联连接的一序列，且缓冲器BUF_1、BUF_2可分别产生延迟相位信号CK_1、CK_2。首先，循环式延迟电路502可通过与非门NAND进行闸控(Gating)，当除频信号CK_DIV为高且传递至与非门NAND时，则缓冲器BUF_1、BUF_1的串联序列则会开启且持续进行循环操作，不断地产生延迟相位信号CK_1、CK_2；当除频信号CK_DIV为低且传递至与非门NAND时，则缓冲器BUF_1、BUF_1的串联序列则会关闭且不进行循环操作，因而不输出延迟相位信号CK_1、CK_2。此外，序列中的最后一级缓冲器BUF_2会将延迟相位信号CK_2回授至与非门NAND，通过与非门NAND传递延迟相位信号CK_M至缓冲器的序列，以完成一次完整的循环操作。如此一来，通过与非门NAND的闸控，以及循环操作时重复利用较少的电路以不断地产生延迟相位信号，本申请的频率产生器30可利用循环式延迟电路302实现低功率的频率产生器。
接着，关于此实施例的重定时器请进一步参考图5，图5为本发明实施例一重定时器506的示意图。重定时器506包括N个D型正反器DFF1～DFFn以及多工器MUX。如图所示，D型正反器的数据输出端耦接至另一D型正反 器的数据输入端，N个D型正反器相互串接形成一序列，在此情况下，D型正反器DFF1～DFFn的序列即为一寄存器(Shift Register)。在序列最前端的D型正反器DFF1的数据输入端用来接收除频信号CK_DIV，序列中所有的D型正反器DFF1～DFFn的频率输入端接收多工信号CK_MUX，以于D型正反器DFF1～DFFn的数据输出端分别产生第一重定时信号P_1～第n重定时信号P_n，序列中的D型正反器DFF1～DFFn可根据多工信号CK_MUX的触发以传递除频信号CK_DIV，于第一次循环操作时，多工信号CK_MUX第一次触发D型正反器DFF1～DFFn时，D型正反器DFF1将除频信号CK_DIV传递至第一重定时信号P_1；于第二次循环操作时，多工信号CK_MUX第二次触发D型正反器DFF1～DFFn时，D型正反器DFF2可将第一重定时信号P_1传递至第二重定时信号P_2。藉此，重定时器506可于多工信号CK_MUX在不同循环操作的触发时，产生重定时，再通过多工器MUX根据循环信号S_RET由第一重定时信号P_1～第n重定时信号P_n之中选择其中之一信号为输出信号CKOUT，以取得适当的信号相位，达到分数除数操作的开回路频率产生器。
进一步而言，请参考图6，图6为图3所示频率产生器30运作时相关信号的示意图。在此实施例中，频率产生器30可进行除数为17/5的分数除频操作。详细而言，除频器300可进行除数为除3或除4的除频操作；循环式延迟电路302可产生两组延迟相位信号CK_1、CK_2，且延迟相位信号CK_1、CK_2的延迟分别为1/5输入周期Tin以及2/5输入周期Tin；多工器304根据相位信号选择延迟相位信号CK_1、CK_2中之一信号以产生多工信号CK_MUX；重定时器306根据多工信号CK_MUX的触发以及循环信号S_RET的指示以产生输 出信号CKOUT。如图所示，在一时间点T1时，输入信号CKIN与输出信号CKOUT互相对齐。控制单元308产生的除数信号S_DIV指示除频器300对输入信号CKIN进行除数为3的整数除频操作以产生除频信号CK_DIV；循环式延迟电路302根据除频信号CK_DIV以于每次循环操作时产生延迟相位信号CK_1、CK_2；控制单元308产生的相位信号S_MUX指示多工器304选择延迟相位信号CK_2为多工信号CK_MUX；控制单元308产生的循环信号S_RET指示重定时器306选择第一次循环操作所产生的多工信号CK_MUX为输出信号CKOUT，如此一来，通过多工器304以及重定时器306选择第一次循环操作的延迟相位信号CK_2，除频信号CK_DIV的周期可额外增加2/5输入周期Tin，以实现分数除频操作；同样地，在一时间点T2时，除频器300的除数为3；多工器304选择延迟相位信号CK_2为多工信号CK_MUX；重定时器306根据相位信号选择第二次循环操作所产生的多工信号CK_MUX为输出信号CKOUT，因此，除频信号CK_DIV的周期可额外增加4/5输入周期Tin。在一时间点T3时，除频器300的除数为3；多工器304选择延迟相位信号CK_2为多工信号CK_MUX；重定时器306根据相位信号S_MUX选择第三次循环操作所产生的多工信号CK_MUX为输出信号CKOUT，因此除频信号CK_DIV的周期可额外增加6/5输入周期Tin。值得注意的是，在一时间点T4时，除数信号S_DIV指示除频器300的除数为4；相位信号S_MUX指示多工器304选择延迟相位信号CK_1为多工信号CK_MUX；重定时器306根据相位信号选择第二次循环操作所产生的多工信号CK_MUX为输出信号CKOUT，因此除频信号CK_DIV的周期可额外增加3/5输入周期Tin。在一时间点T5时，除频器300的除数为4；多工器304选择除频信号CK_DIV为多工信号CK_MUX；重定时 器306可将除频信号CK_DIV输出为多工信号CK_MUX。如此一来，频率产生器30可通过除频器300进行整数的除频操作，以及循环式延迟电路302持续进行循环操作以产生延迟相位信号CK_1、CK_2，通过多工器304以及通过重定时器306选择正确的循环操作以及延迟相位信号，较佳地调整除频信号CK_DIV的周期而产生输出信号CKOUT，以实现开回路且低功率的频率产生器。至于时间点T3时，除频器300的除数为3，循环式延迟电路302、多工器304以及重定时器306额外增加6/5输入周期Tin。取而代之的是，除频器300亦可进行除数为4的除频操作，循环式延迟电路302、多工器304以及重定时器306额外增加的输入周期Tin相对应地调整为1/5输入周期Tin，以产生适当地输出信号CKOUT。只要其调整前后的除数相等即可(调整前的除数为(3+6/5)，调整后的除数为(4+1/5))。通过控制单元308于每次接收到除频信号CK_DIV时，预先判断下一次除频信号CK_DIV的整数除数以及延迟量，以产生相对应的除数信号S_DIV、相位信号S_MUX、循环信号S_RET以控制除频器300、循环式延迟电路302、多工器304以及重定时器306。
详细而言，频率产生器30进行除数为Q/M的分数除频操作时，可视为将频率进行除数为(N+P/M)的分数除频操作，其中N、P与M为正整数，而P、Q、M、N之间的关系为(Q＝MN+P)。另一方面，频率产生器30进行的除频操作会使输出周期Tout为输出周期Tin的(N+P/M)倍(即周期与频率成反比)。因此，本发明透过除频器300可对输入信号CKIN进行N或(N+1)除数的除频操作。而剩余P/M除数的除频操作则通过循环式延迟电路302、多工器304以及重定时器306实现。，在上述实施例中，除数17/5即为(3+2/5)，因此， 除频器300可进行除数为3或除数为4的除频操作，而剩余2/5除数的除频操作则通过循环式延迟电路302、多工器304以及重定时器306实现。首先，藉由调整循环式延迟电路302的延迟，使延迟相位信号CK_1～CK_2于每次循环操作时的延迟分别为1/5输入周期Tin以及2/5输入周期Tin，且每次的循环操作延迟为2/5输入周期Tin。再透过多工器304选择适当的延迟相位信号，以及透过重定时器306选择正确的循环操作，且调整输出信号CKOUT的工作周期比(Duty Cycle)。如此一来，本发明的频率产生器30可对输入信号CKIN进行分数除数的除频操作以产生输出信号CKOUT。
上述关于频率产生器根据输入输入信号CKIN进行分数除频操作以产生输出信号CKOUT的运作方法可归纳为一流程70，如图7所示。流程70可用于一频率产生器，频率产生器包括一除频器接收输入信号CKIN，用来根据除数信号S_DIV对输入信号进行整数除频操作以产生除频信号CK_DIV。一循环式延迟电路耦接于除频器，用来根据除频信号CK_DIV持续进行循环操作，其中，循环式延迟电路于每次循环操作产生至少一延迟相位信号CK_1～CK_M。一多工器耦接于循环式延迟电路，用来根据相位信号S_MUX由除频信号CK_DIV以及延迟相位信号CK_1～CK_M中选择其中之一信号为多工信号CK_MUX。重定时器耦接于多工器，用来根据循环信号S_RET以及多工信号CK_MUX，以于正确的循环操作时产生一输出信号CKOUT。流程70包括以下步骤：
步骤700：开始。
步骤702：除频器根据除数信号S_DIV对输入信号CKIN进行整数除频操作，以产生除频信号CK_DIV。
步骤704：循环式延迟电路接收除频信号CK_DIV以产生至少一延迟相位信号CK_1～CK_M。
步骤706：多工器根据相位信号S_MUX由除频信号CK_DIV以及至少一延迟相位信号CK_1～CK_M中选择其中之一信号为多工信号CK_MUX。
步骤708：重定时器根据循环信号S_RET以于正确的循环操作时间将多工信号CK_MUX输出为输出信号CKOUT。
步骤710：结束。
流程70的细节请参考前述相关段落(但不限于此)，故不于此赘述。
习知技术中，为了产生不同的相位以进行分数除频操作，无论通过设置大量的相位产生单元以增加输出信号，或是通过频率合成器的三角积分调变器皆会增加功率消耗且降低信号质量。相较之下，通过本申请的频率产生器，可通过循环式延迟电路在较小的面积消耗下不断地产生不同的相位，再通过多工器以及重定时器进行选择相位信号以及正确的循环操作，以达到开回路且低功率的频率产生器。

Claims (6)

  1. 一种频率产生器，包括：
    控制单元，用来接收输入信号，以产生除数信号、相位信号以及循环信号；
    除频器，用来接收所述输入信号，以及根据所述除数信号对所述输入信号进行整数除频而产生除频信号；
    循环式延迟电路，耦接于所述除频器，用来对所述除频信号进行至少一循环操作，且于每次进行所述循环操作时产生至少一延迟相位信号；
    第一多工器，耦接于所述循环式延迟电路，用来根据所述相位信号由所述除频信号以及所述至少一延迟相位信号中选择其中之一信号，以产生多工信号；以及
    重定时器，耦接于所述第一多工器，用来根据所述循环信号、所述多工信号以及所述除频信号，产生输出信号。
  2. 如权利要求1所述的频率产生器，其中所述除频器将所述输入信号的频率除以一整数或除以所述整数加一，以对所述输入信号进行整数除频而产生所述除频信号。
  3. 如权利要求1所述的频率产生器，其中所述循环式延迟电路包括：
    与非门，用来接收所述除频信号以及循环相位信号，以产生第一延迟相位信号；以及
    至少一延迟单元，相互串接连接为一序列，由所述序列中最前一延迟单元接收所述第一延迟相位信号，每一延迟单元将前一延迟单元输出的延 迟相位信号延迟以产生所述至少一延迟相位信号，以及由所述序列中最后一延迟单元输出所述循环相位信号。
  4. 如权利要求3所述的频率产生器，其中每一循环操作为所述除频信号输入所述至少一延迟单元的所述序列，由所述序列中最后一延迟单元输出所述循环相位信号至所述与非门。
  5. 如权利要求1所述的频率产生器，所述重定时器包括：
    至少一D型正反器，相互串接连接，用来接收所述多工信号，且所述至少一D型正反器的频率输入端接收所述多工信号，以于所述至少一D型正反器的的信号输出端产生至少一重定时信号；以及
    第二多工器，耦接于所述至少一D型正反器，用来根据所述循环信号由所述至少一重定时信号中选择其中之一信号，以产生所述输出信号。
  6. 一种频率产生方法，用于频率产生器，其中所述频率产生器包括除频器，用来接收输入信号而产生除频信号；循环式延迟电路，耦接于所述除频器，用来根据所述除频信号产生至少一延迟相位信号；多工器，耦接于循环式延迟电路，用来进行信号选择；重定时器，耦接于所述多工器，用来产生输出信号，其中所述频率产生方法包括：
    所述除频器根据控制单元产生的除数信号对所述输入信号进行整数除频而产生所述除频信号；
    所述循环式延迟电路根据所述除频信号进行至少一循环操作，且于每次进行所述循环操作时产生所述至少一延迟相位信号；
    所述多工器根据所述控制单元产生的相位信号由所述除频信号、所述至少一延迟相位信号中选择其中之一信号而产生多工信号；以及
    所述重定时器根据所述控制单元产生的循环信号、所述除频信号以及所述多工信号以产生所述输出信号。
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